Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.61 99.36 98.73 100.00 100.00 100.00 99.55


Total test records in report: 581
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T509 /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.132935972 Jul 19 05:06:41 PM PDT 24 Jul 19 05:06:43 PM PDT 24 37256480 ps
T79 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.3422600087 Jul 19 05:06:37 PM PDT 24 Jul 19 05:06:39 PM PDT 24 98342895 ps
T510 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.3003753740 Jul 19 05:06:25 PM PDT 24 Jul 19 05:06:27 PM PDT 24 24669450 ps
T511 /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.3447802822 Jul 19 05:06:33 PM PDT 24 Jul 19 05:06:37 PM PDT 24 216133324 ps
T512 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.1137775598 Jul 19 05:06:24 PM PDT 24 Jul 19 05:06:26 PM PDT 24 26482354 ps
T513 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.521994281 Jul 19 05:06:58 PM PDT 24 Jul 19 05:06:59 PM PDT 24 58141323 ps
T514 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.4173777578 Jul 19 05:06:23 PM PDT 24 Jul 19 05:06:24 PM PDT 24 356608086 ps
T515 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1322434605 Jul 19 05:06:33 PM PDT 24 Jul 19 05:06:36 PM PDT 24 123092177 ps
T516 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.580065330 Jul 19 05:07:08 PM PDT 24 Jul 19 05:07:11 PM PDT 24 56327557 ps
T517 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.1268805876 Jul 19 05:06:36 PM PDT 24 Jul 19 05:06:39 PM PDT 24 35670470 ps
T518 /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3061662170 Jul 19 05:06:52 PM PDT 24 Jul 19 05:06:56 PM PDT 24 32390847 ps
T92 /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.3306382595 Jul 19 05:06:49 PM PDT 24 Jul 19 05:06:51 PM PDT 24 34287011 ps
T519 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.184174526 Jul 19 05:06:57 PM PDT 24 Jul 19 05:06:59 PM PDT 24 32579968 ps
T520 /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2822513229 Jul 19 05:06:33 PM PDT 24 Jul 19 05:06:36 PM PDT 24 68291516 ps
T521 /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.982753527 Jul 19 05:06:58 PM PDT 24 Jul 19 05:07:01 PM PDT 24 17705001 ps
T522 /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.309876022 Jul 19 05:06:40 PM PDT 24 Jul 19 05:06:43 PM PDT 24 73940801 ps
T523 /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.2430707953 Jul 19 05:07:00 PM PDT 24 Jul 19 05:07:03 PM PDT 24 102990796 ps
T524 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.4004616760 Jul 19 05:06:41 PM PDT 24 Jul 19 05:06:44 PM PDT 24 92938465 ps
T525 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.316926378 Jul 19 05:06:38 PM PDT 24 Jul 19 05:06:40 PM PDT 24 156040552 ps
T526 /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.979697239 Jul 19 05:06:41 PM PDT 24 Jul 19 05:06:44 PM PDT 24 20593278 ps
T527 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.2210872856 Jul 19 05:06:51 PM PDT 24 Jul 19 05:06:54 PM PDT 24 167431662 ps
T528 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.2559313475 Jul 19 05:06:51 PM PDT 24 Jul 19 05:06:54 PM PDT 24 37738851 ps
T529 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.746457346 Jul 19 05:07:06 PM PDT 24 Jul 19 05:07:09 PM PDT 24 79272111 ps
T530 /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.3278718435 Jul 19 05:06:24 PM PDT 24 Jul 19 05:06:27 PM PDT 24 57170171 ps
T531 /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.917525314 Jul 19 05:06:24 PM PDT 24 Jul 19 05:06:26 PM PDT 24 21603183 ps
T532 /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.2658772428 Jul 19 05:06:34 PM PDT 24 Jul 19 05:06:36 PM PDT 24 35692886 ps
T533 /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.1218521285 Jul 19 05:06:50 PM PDT 24 Jul 19 05:06:54 PM PDT 24 40370319 ps
T534 /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.3324689556 Jul 19 05:06:40 PM PDT 24 Jul 19 05:06:43 PM PDT 24 117021793 ps
T535 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.4243455121 Jul 19 05:06:40 PM PDT 24 Jul 19 05:06:42 PM PDT 24 16143594 ps
T536 /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3221802332 Jul 19 05:06:41 PM PDT 24 Jul 19 05:06:44 PM PDT 24 75549823 ps
T537 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2429248864 Jul 19 05:06:27 PM PDT 24 Jul 19 05:06:32 PM PDT 24 63828696 ps
T538 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.2856882759 Jul 19 05:06:52 PM PDT 24 Jul 19 05:06:55 PM PDT 24 12301233 ps
T539 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1534816175 Jul 19 05:06:40 PM PDT 24 Jul 19 05:06:43 PM PDT 24 43883689 ps
T540 /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.1668709848 Jul 19 05:06:58 PM PDT 24 Jul 19 05:07:00 PM PDT 24 15111581 ps
T541 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.563252007 Jul 19 05:06:52 PM PDT 24 Jul 19 05:06:56 PM PDT 24 32759472 ps
T542 /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.3863401857 Jul 19 05:07:15 PM PDT 24 Jul 19 05:07:18 PM PDT 24 46111406 ps
T543 /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.2476613312 Jul 19 05:06:58 PM PDT 24 Jul 19 05:07:00 PM PDT 24 43177347 ps
T544 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.4013203919 Jul 19 05:06:58 PM PDT 24 Jul 19 05:06:59 PM PDT 24 95691383 ps
T545 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.39671365 Jul 19 05:06:36 PM PDT 24 Jul 19 05:06:38 PM PDT 24 17099390 ps
T546 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2603275900 Jul 19 05:06:43 PM PDT 24 Jul 19 05:06:46 PM PDT 24 12158658 ps
T547 /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.2410635817 Jul 19 05:06:59 PM PDT 24 Jul 19 05:07:01 PM PDT 24 11880407 ps
T548 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.2663626928 Jul 19 05:07:15 PM PDT 24 Jul 19 05:07:19 PM PDT 24 35764748 ps
T549 /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.2298430508 Jul 19 05:06:41 PM PDT 24 Jul 19 05:06:44 PM PDT 24 135310113 ps
T550 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.2056032894 Jul 19 05:06:40 PM PDT 24 Jul 19 05:06:43 PM PDT 24 134560738 ps
T551 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.1891293250 Jul 19 05:06:40 PM PDT 24 Jul 19 05:06:41 PM PDT 24 36316234 ps
T552 /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.2794909553 Jul 19 05:06:34 PM PDT 24 Jul 19 05:06:36 PM PDT 24 13769140 ps
T553 /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.108915929 Jul 19 05:06:25 PM PDT 24 Jul 19 05:06:28 PM PDT 24 35942346 ps
T554 /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.3427388968 Jul 19 05:06:59 PM PDT 24 Jul 19 05:07:02 PM PDT 24 55778473 ps
T555 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.440963829 Jul 19 05:07:01 PM PDT 24 Jul 19 05:07:04 PM PDT 24 20673626 ps
T80 /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.2535997936 Jul 19 05:06:49 PM PDT 24 Jul 19 05:06:50 PM PDT 24 14951857 ps
T556 /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.4221505321 Jul 19 05:06:57 PM PDT 24 Jul 19 05:06:59 PM PDT 24 266690635 ps
T557 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2893808415 Jul 19 05:06:32 PM PDT 24 Jul 19 05:06:35 PM PDT 24 89532168 ps
T558 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1302808725 Jul 19 05:07:00 PM PDT 24 Jul 19 05:07:03 PM PDT 24 44905637 ps
T559 /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.3488365659 Jul 19 05:06:33 PM PDT 24 Jul 19 05:06:37 PM PDT 24 376457996 ps
T560 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3353590025 Jul 19 05:06:44 PM PDT 24 Jul 19 05:06:47 PM PDT 24 46897271 ps
T561 /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.447872495 Jul 19 05:06:34 PM PDT 24 Jul 19 05:06:37 PM PDT 24 94621184 ps
T562 /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.3441723089 Jul 19 05:07:04 PM PDT 24 Jul 19 05:07:06 PM PDT 24 122048366 ps
T563 /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.935504252 Jul 19 05:06:26 PM PDT 24 Jul 19 05:06:29 PM PDT 24 33551453 ps
T81 /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.1845622624 Jul 19 05:06:23 PM PDT 24 Jul 19 05:06:25 PM PDT 24 58144026 ps
T564 /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.2275224519 Jul 19 05:06:58 PM PDT 24 Jul 19 05:06:59 PM PDT 24 13113757 ps
T565 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.371898318 Jul 19 05:07:00 PM PDT 24 Jul 19 05:07:03 PM PDT 24 12114480 ps
T566 /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.2880554118 Jul 19 05:06:33 PM PDT 24 Jul 19 05:06:36 PM PDT 24 139258400 ps
T567 /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.2874346353 Jul 19 05:06:53 PM PDT 24 Jul 19 05:06:56 PM PDT 24 37256289 ps
T83 /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.4073691719 Jul 19 05:06:24 PM PDT 24 Jul 19 05:06:26 PM PDT 24 516971234 ps
T568 /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1890442632 Jul 19 05:07:01 PM PDT 24 Jul 19 05:07:04 PM PDT 24 24999687 ps
T569 /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.134975754 Jul 19 05:06:59 PM PDT 24 Jul 19 05:07:02 PM PDT 24 14359879 ps
T570 /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.3080112026 Jul 19 05:06:50 PM PDT 24 Jul 19 05:06:53 PM PDT 24 18177633 ps
T571 /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.93725136 Jul 19 05:06:51 PM PDT 24 Jul 19 05:06:55 PM PDT 24 164619944 ps
T572 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.2339657511 Jul 19 05:07:00 PM PDT 24 Jul 19 05:07:03 PM PDT 24 34931361 ps
T84 /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.798224386 Jul 19 05:06:58 PM PDT 24 Jul 19 05:06:59 PM PDT 24 18468514 ps
T573 /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.1026848967 Jul 19 05:06:24 PM PDT 24 Jul 19 05:06:27 PM PDT 24 214237848 ps
T85 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.395563711 Jul 19 05:07:00 PM PDT 24 Jul 19 05:07:03 PM PDT 24 15024667 ps
T574 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2190296983 Jul 19 05:06:42 PM PDT 24 Jul 19 05:06:45 PM PDT 24 122170258 ps
T575 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.2407517566 Jul 19 05:07:15 PM PDT 24 Jul 19 05:07:19 PM PDT 24 15100319 ps
T576 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.3770098575 Jul 19 05:06:51 PM PDT 24 Jul 19 05:06:54 PM PDT 24 33613757 ps
T86 /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.3851862644 Jul 19 05:06:24 PM PDT 24 Jul 19 05:06:26 PM PDT 24 125246926 ps
T577 /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1336085001 Jul 19 05:06:34 PM PDT 24 Jul 19 05:06:36 PM PDT 24 105358448 ps
T578 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.921788063 Jul 19 05:06:38 PM PDT 24 Jul 19 05:06:40 PM PDT 24 66910819 ps
T579 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.1170201667 Jul 19 05:06:35 PM PDT 24 Jul 19 05:06:36 PM PDT 24 16962191 ps
T580 /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.1397339383 Jul 19 05:06:23 PM PDT 24 Jul 19 05:06:25 PM PDT 24 76687942 ps
T581 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.3905327377 Jul 19 05:07:00 PM PDT 24 Jul 19 05:07:05 PM PDT 24 128588576 ps

Test location /workspace/coverage/default/11.rv_timer_stress_all_with_rand_reset.1994887016
Short name T9
Test name
Test status
Simulation time 188851046625 ps
CPU time 367.61 seconds
Started Jul 19 05:10:17 PM PDT 24
Finished Jul 19 05:16:26 PM PDT 24
Peak memory 206476 kb
Host smart-f2b89510-a355-42c2-8268-948aa4e636fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994887016 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all_with_rand_reset.1994887016
Directory /workspace/11.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.4110196844
Short name T11
Test name
Test status
Simulation time 637420444846 ps
CPU time 2344.41 seconds
Started Jul 19 05:10:18 PM PDT 24
Finished Jul 19 05:49:24 PM PDT 24
Peak memory 191768 kb
Host smart-70935619-7480-4a3e-a6d8-2b477fa1c641
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110196844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.4110196844
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.24294753
Short name T56
Test name
Test status
Simulation time 747599598013 ps
CPU time 1453.62 seconds
Started Jul 19 05:11:19 PM PDT 24
Finished Jul 19 05:35:34 PM PDT 24
Peak memory 196360 kb
Host smart-e0cf73ab-94bb-4de8-91fe-1981ad2234ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24294753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all.24294753
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3445805786
Short name T28
Test name
Test status
Simulation time 292563440 ps
CPU time 1.09 seconds
Started Jul 19 05:06:52 PM PDT 24
Finished Jul 19 05:06:55 PM PDT 24
Peak memory 195124 kb
Host smart-119c790e-7f27-4c48-8268-95a0073aafaf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445805786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.3445805786
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.887574040
Short name T57
Test name
Test status
Simulation time 5069088682081 ps
CPU time 2049.06 seconds
Started Jul 19 05:11:20 PM PDT 24
Finished Jul 19 05:45:31 PM PDT 24
Peak memory 191788 kb
Host smart-c04868d4-1295-4c41-a54d-b2eed2caaeaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887574040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all.
887574040
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.1283337157
Short name T157
Test name
Test status
Simulation time 2222288030989 ps
CPU time 4029.97 seconds
Started Jul 19 05:10:40 PM PDT 24
Finished Jul 19 06:17:52 PM PDT 24
Peak memory 196256 kb
Host smart-3db4b65f-38e2-43de-b4c4-0e3ab1f86f04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283337157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.1283337157
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.3018924560
Short name T53
Test name
Test status
Simulation time 497348630294 ps
CPU time 727.79 seconds
Started Jul 19 05:10:07 PM PDT 24
Finished Jul 19 05:22:18 PM PDT 24
Peak memory 196380 kb
Host smart-e50592fd-dc45-4375-abc1-b837109eed7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018924560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
3018924560
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all_with_rand_reset.4215522264
Short name T70
Test name
Test status
Simulation time 115303563989 ps
CPU time 845.78 seconds
Started Jul 19 05:10:06 PM PDT 24
Finished Jul 19 05:24:15 PM PDT 24
Peak memory 208948 kb
Host smart-2f9e1616-78e4-4441-bd8a-8d025d2283ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215522264 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all_with_rand_reset.4215522264
Directory /workspace/5.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.1630351731
Short name T202
Test name
Test status
Simulation time 1682966527967 ps
CPU time 2739.13 seconds
Started Jul 19 05:11:30 PM PDT 24
Finished Jul 19 05:57:11 PM PDT 24
Peak memory 191804 kb
Host smart-4136ee18-9bb9-4a55-bd70-9f89d390cb6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630351731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.1630351731
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.3128572271
Short name T60
Test name
Test status
Simulation time 3408754868761 ps
CPU time 1524.94 seconds
Started Jul 19 05:11:32 PM PDT 24
Finished Jul 19 05:36:58 PM PDT 24
Peak memory 191788 kb
Host smart-06c72c76-174f-4ec8-9758-fe9e7cb913da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128572271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.3128572271
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.3523318730
Short name T168
Test name
Test status
Simulation time 505772964265 ps
CPU time 755.64 seconds
Started Jul 19 05:11:03 PM PDT 24
Finished Jul 19 05:23:39 PM PDT 24
Peak memory 191776 kb
Host smart-e4f59ff1-a7ea-4ec4-9792-fa87d26e9409
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523318730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.3523318730
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.440971830
Short name T109
Test name
Test status
Simulation time 493830937051 ps
CPU time 1196.4 seconds
Started Jul 19 05:10:05 PM PDT 24
Finished Jul 19 05:30:04 PM PDT 24
Peak memory 191752 kb
Host smart-bd38e003-e11a-4226-bf96-024d53b08ed5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440971830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.440971830
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.3538189834
Short name T101
Test name
Test status
Simulation time 1797677487891 ps
CPU time 1194.15 seconds
Started Jul 19 05:10:18 PM PDT 24
Finished Jul 19 05:30:13 PM PDT 24
Peak memory 196200 kb
Host smart-3bde504e-0b2b-404e-8518-aa76e9ff06f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538189834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
3538189834
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.177855816
Short name T16
Test name
Test status
Simulation time 332045276 ps
CPU time 0.93 seconds
Started Jul 19 05:10:04 PM PDT 24
Finished Jul 19 05:10:06 PM PDT 24
Peak memory 214952 kb
Host smart-3e2c1ca7-f0d9-45a4-9939-c90e5325f2cb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177855816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.177855816
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.438225750
Short name T54
Test name
Test status
Simulation time 1496145802671 ps
CPU time 1191.98 seconds
Started Jul 19 05:10:37 PM PDT 24
Finished Jul 19 05:30:29 PM PDT 24
Peak memory 191776 kb
Host smart-e8d06534-e527-483d-9f13-1b531fbd700e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438225750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all.
438225750
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.438659343
Short name T146
Test name
Test status
Simulation time 396388766984 ps
CPU time 2920.2 seconds
Started Jul 19 05:11:20 PM PDT 24
Finished Jul 19 06:00:02 PM PDT 24
Peak memory 196236 kb
Host smart-83c99d51-ab12-4a46-a0a0-2dccb9467883
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438659343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all.
438659343
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.2399894732
Short name T235
Test name
Test status
Simulation time 3872889695091 ps
CPU time 1614.19 seconds
Started Jul 19 05:10:01 PM PDT 24
Finished Jul 19 05:36:57 PM PDT 24
Peak memory 191780 kb
Host smart-b2a97c88-93fe-49e3-93f2-7443b4f82aa5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399894732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
2399894732
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.3195944899
Short name T55
Test name
Test status
Simulation time 864633061407 ps
CPU time 1515.82 seconds
Started Jul 19 05:11:10 PM PDT 24
Finished Jul 19 05:36:27 PM PDT 24
Peak memory 191776 kb
Host smart-1c4a0540-2476-49e2-9f19-dee5f948ca42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195944899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.3195944899
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.2325583172
Short name T159
Test name
Test status
Simulation time 6460185319487 ps
CPU time 2593.01 seconds
Started Jul 19 05:10:32 PM PDT 24
Finished Jul 19 05:53:48 PM PDT 24
Peak memory 191788 kb
Host smart-b6f6f40b-07fa-4fb5-816f-e2ff8fb8b5d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325583172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.2325583172
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.1326989886
Short name T178
Test name
Test status
Simulation time 323746327250 ps
CPU time 852.39 seconds
Started Jul 19 05:10:37 PM PDT 24
Finished Jul 19 05:24:50 PM PDT 24
Peak memory 196656 kb
Host smart-a4f226af-8033-47b6-8df5-9d007d343eba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326989886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.1326989886
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.1030969837
Short name T271
Test name
Test status
Simulation time 401386003481 ps
CPU time 850.07 seconds
Started Jul 19 05:10:32 PM PDT 24
Finished Jul 19 05:24:45 PM PDT 24
Peak memory 191732 kb
Host smart-3f80c44c-ac7b-4c88-8ef8-ac2ea5c7bf48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030969837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.1030969837
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_random.3182857260
Short name T124
Test name
Test status
Simulation time 164135945738 ps
CPU time 271.81 seconds
Started Jul 19 05:11:19 PM PDT 24
Finished Jul 19 05:15:52 PM PDT 24
Peak memory 191724 kb
Host smart-84704cca-ce61-4b1a-a44a-07c1a41cc263
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182857260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.3182857260
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.2961927525
Short name T153
Test name
Test status
Simulation time 2074085593835 ps
CPU time 1899.4 seconds
Started Jul 19 05:10:24 PM PDT 24
Finished Jul 19 05:42:05 PM PDT 24
Peak memory 191772 kb
Host smart-4d988275-8696-49a2-af09-8af78e97a87c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961927525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.2961927525
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/137.rv_timer_random.3527252784
Short name T113
Test name
Test status
Simulation time 177079605334 ps
CPU time 659.68 seconds
Started Jul 19 05:12:31 PM PDT 24
Finished Jul 19 05:23:32 PM PDT 24
Peak memory 191792 kb
Host smart-7517c4df-0b2d-4c46-a64a-21bf2bb92589
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527252784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.3527252784
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.568139445
Short name T61
Test name
Test status
Simulation time 1540495310071 ps
CPU time 919.2 seconds
Started Jul 19 05:11:12 PM PDT 24
Finished Jul 19 05:26:32 PM PDT 24
Peak memory 191772 kb
Host smart-687f40a3-e4f8-4f7b-b526-64b0efe78c30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568139445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all.
568139445
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/155.rv_timer_random.1689273463
Short name T238
Test name
Test status
Simulation time 438639531976 ps
CPU time 2089.31 seconds
Started Jul 19 05:12:38 PM PDT 24
Finished Jul 19 05:47:29 PM PDT 24
Peak memory 191728 kb
Host smart-c2f9ba01-b89c-430f-8c06-58ae5c2006fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689273463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.1689273463
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.940625362
Short name T68
Test name
Test status
Simulation time 289683306504 ps
CPU time 262.98 seconds
Started Jul 19 05:10:52 PM PDT 24
Finished Jul 19 05:15:15 PM PDT 24
Peak memory 191784 kb
Host smart-cfc5bc59-2368-4afb-b861-67a43b3e7a82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940625362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all.
940625362
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_random.4265509020
Short name T297
Test name
Test status
Simulation time 361658166068 ps
CPU time 662.83 seconds
Started Jul 19 05:11:04 PM PDT 24
Finished Jul 19 05:22:08 PM PDT 24
Peak memory 194860 kb
Host smart-728fb238-087f-4b75-8f8e-e325378f2c6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265509020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.4265509020
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random.1609195025
Short name T273
Test name
Test status
Simulation time 409880178974 ps
CPU time 375.91 seconds
Started Jul 19 05:11:14 PM PDT 24
Finished Jul 19 05:17:31 PM PDT 24
Peak memory 191788 kb
Host smart-1ef7cf96-b911-4906-9201-802d70ec604d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609195025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.1609195025
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.810611368
Short name T160
Test name
Test status
Simulation time 663891419050 ps
CPU time 335.2 seconds
Started Jul 19 05:10:06 PM PDT 24
Finished Jul 19 05:15:43 PM PDT 24
Peak memory 183460 kb
Host smart-898b072c-9bd7-486e-80b0-bfc54c95a35d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810611368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.rv_timer_cfg_update_on_fly.810611368
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_random.3802165305
Short name T139
Test name
Test status
Simulation time 313502776315 ps
CPU time 552.97 seconds
Started Jul 19 05:10:16 PM PDT 24
Finished Jul 19 05:19:29 PM PDT 24
Peak memory 191780 kb
Host smart-b6450904-7970-4d81-a516-40281e23ba22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802165305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.3802165305
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/60.rv_timer_random.2477064524
Short name T122
Test name
Test status
Simulation time 425066476824 ps
CPU time 921.5 seconds
Started Jul 19 05:11:42 PM PDT 24
Finished Jul 19 05:27:05 PM PDT 24
Peak memory 191764 kb
Host smart-9a8eac86-c5f2-4e3a-9148-170795bd96c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477064524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.2477064524
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.4208312005
Short name T284
Test name
Test status
Simulation time 294938433849 ps
CPU time 458.63 seconds
Started Jul 19 05:11:43 PM PDT 24
Finished Jul 19 05:19:23 PM PDT 24
Peak memory 191788 kb
Host smart-bceafae0-9f09-472e-84ba-5a678aea3517
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208312005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.4208312005
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.4073691719
Short name T83
Test name
Test status
Simulation time 516971234 ps
CPU time 0.83 seconds
Started Jul 19 05:06:24 PM PDT 24
Finished Jul 19 05:06:26 PM PDT 24
Peak memory 192604 kb
Host smart-d8642251-495b-4cb3-a5d4-cfd333aa44b7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073691719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.4073691719
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/default/151.rv_timer_random.2515560733
Short name T240
Test name
Test status
Simulation time 204410508542 ps
CPU time 257.81 seconds
Started Jul 19 05:12:37 PM PDT 24
Finished Jul 19 05:16:56 PM PDT 24
Peak memory 191772 kb
Host smart-a64adcfc-d9fe-4d73-8702-73c8714e4b01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515560733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.2515560733
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.837869690
Short name T288
Test name
Test status
Simulation time 230295783959 ps
CPU time 510.19 seconds
Started Jul 19 05:12:54 PM PDT 24
Finished Jul 19 05:21:24 PM PDT 24
Peak memory 195780 kb
Host smart-04516936-d375-495c-b1cc-87223a57fe68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837869690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.837869690
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.2750477108
Short name T59
Test name
Test status
Simulation time 2349600310123 ps
CPU time 1146.02 seconds
Started Jul 19 05:11:20 PM PDT 24
Finished Jul 19 05:30:28 PM PDT 24
Peak memory 191788 kb
Host smart-25d9ca1b-b084-49b9-b99e-fac377464c45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750477108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.2750477108
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.1616709289
Short name T154
Test name
Test status
Simulation time 272057466976 ps
CPU time 840.75 seconds
Started Jul 19 05:11:30 PM PDT 24
Finished Jul 19 05:25:32 PM PDT 24
Peak memory 191772 kb
Host smart-b1d9efae-0da2-43a6-b502-861815523221
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616709289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.1616709289
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/105.rv_timer_random.4228700013
Short name T129
Test name
Test status
Simulation time 319309242056 ps
CPU time 154.09 seconds
Started Jul 19 05:12:10 PM PDT 24
Finished Jul 19 05:14:45 PM PDT 24
Peak memory 191776 kb
Host smart-c9c85437-52f4-442d-8e25-699e6f647720
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228700013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.4228700013
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.3984009583
Short name T223
Test name
Test status
Simulation time 2519041942259 ps
CPU time 1178.22 seconds
Started Jul 19 05:10:17 PM PDT 24
Finished Jul 19 05:29:57 PM PDT 24
Peak memory 183560 kb
Host smart-88dd0626-061d-45bb-8d23-2400d2ea7512
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984009583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.3984009583
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/142.rv_timer_random.1308566818
Short name T295
Test name
Test status
Simulation time 2542999824385 ps
CPU time 1681.81 seconds
Started Jul 19 05:12:30 PM PDT 24
Finished Jul 19 05:40:33 PM PDT 24
Peak memory 191768 kb
Host smart-ca42354e-5830-447e-9b45-9b61b612587d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308566818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.1308566818
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random.1561246683
Short name T221
Test name
Test status
Simulation time 153880090825 ps
CPU time 231.73 seconds
Started Jul 19 05:10:32 PM PDT 24
Finished Jul 19 05:14:26 PM PDT 24
Peak memory 191744 kb
Host smart-4b182b17-ef92-4030-bddb-f4d6935bd0bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561246683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.1561246683
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.3573545138
Short name T182
Test name
Test status
Simulation time 162640760964 ps
CPU time 229.54 seconds
Started Jul 19 05:10:32 PM PDT 24
Finished Jul 19 05:14:23 PM PDT 24
Peak memory 183568 kb
Host smart-b4fa1b76-1b8f-46e8-8da2-17188cb318ab
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573545138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.3573545138
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.1713272667
Short name T97
Test name
Test status
Simulation time 586932268792 ps
CPU time 279.67 seconds
Started Jul 19 05:10:38 PM PDT 24
Finished Jul 19 05:15:19 PM PDT 24
Peak memory 183564 kb
Host smart-3b968872-9758-4490-a240-6c7f2552b974
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713272667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.1713272667
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_random.3462742773
Short name T356
Test name
Test status
Simulation time 228623462395 ps
CPU time 1629.91 seconds
Started Jul 19 05:10:38 PM PDT 24
Finished Jul 19 05:37:48 PM PDT 24
Peak memory 191796 kb
Host smart-e07a8b4b-300c-4c4e-9257-b8e60bf2b960
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462742773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.3462742773
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.161618452
Short name T27
Test name
Test status
Simulation time 67675162859 ps
CPU time 117 seconds
Started Jul 19 05:10:57 PM PDT 24
Finished Jul 19 05:12:55 PM PDT 24
Peak memory 183572 kb
Host smart-be5c7d60-da54-42ad-adb3-ac955983a464
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161618452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.rv_timer_cfg_update_on_fly.161618452
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.364872763
Short name T198
Test name
Test status
Simulation time 875456479287 ps
CPU time 587.46 seconds
Started Jul 19 05:11:03 PM PDT 24
Finished Jul 19 05:20:52 PM PDT 24
Peak memory 191788 kb
Host smart-d2bb2ca4-92ae-4a37-8e56-2abbb0c8b742
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364872763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all.
364872763
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.2798221680
Short name T334
Test name
Test status
Simulation time 870922582197 ps
CPU time 959.7 seconds
Started Jul 19 05:10:07 PM PDT 24
Finished Jul 19 05:26:09 PM PDT 24
Peak memory 191688 kb
Host smart-57ae22eb-0137-4d2f-a830-1df339660ef4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798221680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
2798221680
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/88.rv_timer_random.1259752311
Short name T125
Test name
Test status
Simulation time 2349892827663 ps
CPU time 1699.25 seconds
Started Jul 19 05:12:00 PM PDT 24
Finished Jul 19 05:40:20 PM PDT 24
Peak memory 191780 kb
Host smart-e6b66d4a-35b1-44ec-a802-6d957d99ee49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259752311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.1259752311
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random.3007111238
Short name T266
Test name
Test status
Simulation time 520764745246 ps
CPU time 165.8 seconds
Started Jul 19 05:10:17 PM PDT 24
Finished Jul 19 05:13:04 PM PDT 24
Peak memory 191772 kb
Host smart-b57a93e2-e8ea-4ae0-8596-9aa2a8a44fc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007111238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.3007111238
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/110.rv_timer_random.4276505286
Short name T239
Test name
Test status
Simulation time 241293330897 ps
CPU time 131.84 seconds
Started Jul 19 05:12:15 PM PDT 24
Finished Jul 19 05:14:28 PM PDT 24
Peak memory 191772 kb
Host smart-cdfe3d51-edfd-46e9-86d4-35e2229facfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276505286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.4276505286
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.3665590844
Short name T326
Test name
Test status
Simulation time 70411937117 ps
CPU time 114.81 seconds
Started Jul 19 05:12:23 PM PDT 24
Finished Jul 19 05:14:19 PM PDT 24
Peak memory 191792 kb
Host smart-7deb782f-e3e2-4a1d-97fe-e2613ffec146
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665590844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.3665590844
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/140.rv_timer_random.3427110471
Short name T117
Test name
Test status
Simulation time 204849251731 ps
CPU time 96.11 seconds
Started Jul 19 05:12:30 PM PDT 24
Finished Jul 19 05:14:08 PM PDT 24
Peak memory 191768 kb
Host smart-43dbe17a-a985-42b1-99e8-3c87cb9323c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427110471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.3427110471
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.3555893780
Short name T105
Test name
Test status
Simulation time 225410008181 ps
CPU time 1056.02 seconds
Started Jul 19 05:12:46 PM PDT 24
Finished Jul 19 05:30:23 PM PDT 24
Peak memory 191776 kb
Host smart-4290787b-fe0d-4cd6-a23e-4e65f90aeafb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555893780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.3555893780
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random.3146130849
Short name T257
Test name
Test status
Simulation time 693963388636 ps
CPU time 224.1 seconds
Started Jul 19 05:10:38 PM PDT 24
Finished Jul 19 05:14:23 PM PDT 24
Peak memory 191768 kb
Host smart-07a70ff4-6f12-4b67-831f-3cc62120ae30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146130849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.3146130849
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.4052854072
Short name T177
Test name
Test status
Simulation time 1610237970530 ps
CPU time 898.11 seconds
Started Jul 19 05:10:07 PM PDT 24
Finished Jul 19 05:25:08 PM PDT 24
Peak memory 191688 kb
Host smart-b73bdfea-bf50-4565-af31-81724d424413
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052854072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
4052854072
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.30114016
Short name T32
Test name
Test status
Simulation time 18800716 ps
CPU time 0.57 seconds
Started Jul 19 05:06:25 PM PDT 24
Finished Jul 19 05:06:28 PM PDT 24
Peak memory 182580 kb
Host smart-64a67aa2-7a08-479b-b3bd-664c609f4e95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30114016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.30114016
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/100.rv_timer_random.2693376358
Short name T358
Test name
Test status
Simulation time 190287328273 ps
CPU time 249.28 seconds
Started Jul 19 05:12:08 PM PDT 24
Finished Jul 19 05:16:18 PM PDT 24
Peak memory 191780 kb
Host smart-954fed91-e88f-49e3-a19d-6e7621334f08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693376358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.2693376358
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.1359065505
Short name T207
Test name
Test status
Simulation time 2257047117454 ps
CPU time 1083.35 seconds
Started Jul 19 05:12:07 PM PDT 24
Finished Jul 19 05:30:11 PM PDT 24
Peak memory 191752 kb
Host smart-fd5f6316-eef6-4f1c-bfb3-5464a68d05ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359065505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.1359065505
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.3571106588
Short name T44
Test name
Test status
Simulation time 135514582201 ps
CPU time 611 seconds
Started Jul 19 05:12:15 PM PDT 24
Finished Jul 19 05:22:28 PM PDT 24
Peak memory 191792 kb
Host smart-ff4b4eb6-0f54-4c58-90ed-ee8b03b7c1d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571106588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.3571106588
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.2136049569
Short name T67
Test name
Test status
Simulation time 91094503072 ps
CPU time 132.12 seconds
Started Jul 19 05:12:19 PM PDT 24
Finished Jul 19 05:14:32 PM PDT 24
Peak memory 191932 kb
Host smart-db982727-4d6c-4a13-abb8-8cf1e7331b84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136049569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.2136049569
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.2713889329
Short name T187
Test name
Test status
Simulation time 164504937638 ps
CPU time 391.31 seconds
Started Jul 19 05:10:15 PM PDT 24
Finished Jul 19 05:16:47 PM PDT 24
Peak memory 194812 kb
Host smart-b76c9253-f14f-4d0c-8523-1f3578bb35a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713889329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.2713889329
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/168.rv_timer_random.4082908236
Short name T331
Test name
Test status
Simulation time 228457748386 ps
CPU time 394.94 seconds
Started Jul 19 05:12:48 PM PDT 24
Finished Jul 19 05:19:24 PM PDT 24
Peak memory 191720 kb
Host smart-9efa1086-189f-4712-b5af-2fa7b58ca185
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082908236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.4082908236
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.2214792374
Short name T66
Test name
Test status
Simulation time 380553528533 ps
CPU time 214.81 seconds
Started Jul 19 05:12:50 PM PDT 24
Finished Jul 19 05:16:26 PM PDT 24
Peak memory 191780 kb
Host smart-7a3a3ffa-c871-4a6d-8d47-cce59df9d287
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214792374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.2214792374
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random.52519010
Short name T251
Test name
Test status
Simulation time 338255492598 ps
CPU time 471 seconds
Started Jul 19 05:10:31 PM PDT 24
Finished Jul 19 05:18:23 PM PDT 24
Peak memory 191772 kb
Host smart-97eea85b-488f-4668-b959-a7d2c46d3c0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52519010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.52519010
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.3072103676
Short name T175
Test name
Test status
Simulation time 23941876453 ps
CPU time 41.17 seconds
Started Jul 19 05:10:38 PM PDT 24
Finished Jul 19 05:11:20 PM PDT 24
Peak memory 191744 kb
Host smart-5102a4a8-ddfc-4690-9e77-741771b8c8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072103676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.3072103676
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.2836142836
Short name T298
Test name
Test status
Simulation time 1405631425364 ps
CPU time 1013.74 seconds
Started Jul 19 05:11:03 PM PDT 24
Finished Jul 19 05:27:57 PM PDT 24
Peak memory 191724 kb
Host smart-a3dcc2d7-bbbc-4f2d-9dcb-fcd45146e2a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836142836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.2836142836
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_random.2766942284
Short name T304
Test name
Test status
Simulation time 149511435551 ps
CPU time 850.85 seconds
Started Jul 19 05:11:20 PM PDT 24
Finished Jul 19 05:25:32 PM PDT 24
Peak memory 191660 kb
Host smart-8686397e-8c35-4e62-90d3-69ea275b85c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766942284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.2766942284
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1174059446
Short name T104
Test name
Test status
Simulation time 196916768 ps
CPU time 1.36 seconds
Started Jul 19 05:06:26 PM PDT 24
Finished Jul 19 05:06:30 PM PDT 24
Peak memory 194924 kb
Host smart-d681b7f5-7b1e-4701-a866-bb9f8a7de393
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174059446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.1174059446
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.962536858
Short name T320
Test name
Test status
Simulation time 111253868491 ps
CPU time 98.88 seconds
Started Jul 19 05:10:01 PM PDT 24
Finished Jul 19 05:11:41 PM PDT 24
Peak memory 195716 kb
Host smart-7f73531f-b0c8-403e-b4ec-98025d22faa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962536858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.962536858
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/101.rv_timer_random.2840995385
Short name T201
Test name
Test status
Simulation time 1194282428887 ps
CPU time 515.04 seconds
Started Jul 19 05:12:10 PM PDT 24
Finished Jul 19 05:20:46 PM PDT 24
Peak memory 191680 kb
Host smart-45bda480-a0a7-4a4d-947c-f6c7cf8c3fb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840995385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.2840995385
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.2253325768
Short name T345
Test name
Test status
Simulation time 323699825101 ps
CPU time 195.22 seconds
Started Jul 19 05:12:07 PM PDT 24
Finished Jul 19 05:15:23 PM PDT 24
Peak memory 195352 kb
Host smart-da3c280f-0b66-45f1-afb8-eb20856e92c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253325768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.2253325768
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.1649268853
Short name T111
Test name
Test status
Simulation time 112350271516 ps
CPU time 198.79 seconds
Started Jul 19 05:12:10 PM PDT 24
Finished Jul 19 05:15:29 PM PDT 24
Peak memory 191932 kb
Host smart-00532331-8e4c-49e2-af79-41b72f85e764
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649268853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.1649268853
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.2105544194
Short name T280
Test name
Test status
Simulation time 13038282736 ps
CPU time 124.75 seconds
Started Jul 19 05:12:15 PM PDT 24
Finished Jul 19 05:14:20 PM PDT 24
Peak memory 191780 kb
Host smart-5f6d6d83-b055-4e3f-984e-72da9fab0854
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105544194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.2105544194
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.4063493199
Short name T268
Test name
Test status
Simulation time 332239711341 ps
CPU time 253.64 seconds
Started Jul 19 05:12:16 PM PDT 24
Finished Jul 19 05:16:31 PM PDT 24
Peak memory 191780 kb
Host smart-dd5f4902-df34-4d87-861b-2db3c789154e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063493199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.4063493199
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random.872068622
Short name T130
Test name
Test status
Simulation time 237002026607 ps
CPU time 131.56 seconds
Started Jul 19 05:10:19 PM PDT 24
Finished Jul 19 05:12:32 PM PDT 24
Peak memory 191728 kb
Host smart-11599dfb-75bd-42ac-87f4-4bd69fa82885
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872068622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.872068622
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.1961249006
Short name T307
Test name
Test status
Simulation time 169183116021 ps
CPU time 139.63 seconds
Started Jul 19 05:10:19 PM PDT 24
Finished Jul 19 05:12:40 PM PDT 24
Peak memory 183612 kb
Host smart-ac0054ac-67c5-49ba-9fbb-4fff107b214f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961249006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.1961249006
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.3574988310
Short name T275
Test name
Test status
Simulation time 184629874758 ps
CPU time 558.4 seconds
Started Jul 19 05:10:24 PM PDT 24
Finished Jul 19 05:19:44 PM PDT 24
Peak memory 191760 kb
Host smart-61a33535-4302-46f8-8b02-924cfa99d293
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574988310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.3574988310
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/152.rv_timer_random.2107046620
Short name T190
Test name
Test status
Simulation time 121332750458 ps
CPU time 1340.08 seconds
Started Jul 19 05:12:40 PM PDT 24
Finished Jul 19 05:35:02 PM PDT 24
Peak memory 191780 kb
Host smart-3b8b9ffb-77db-42f5-afc7-f0d823d00812
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107046620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.2107046620
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.3381267446
Short name T24
Test name
Test status
Simulation time 166430362328 ps
CPU time 86.48 seconds
Started Jul 19 05:12:38 PM PDT 24
Finished Jul 19 05:14:06 PM PDT 24
Peak memory 191780 kb
Host smart-2d5e1f8f-828d-48c9-983a-23bb610cf162
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381267446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.3381267446
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.180434289
Short name T335
Test name
Test status
Simulation time 79568164868 ps
CPU time 125.35 seconds
Started Jul 19 05:12:36 PM PDT 24
Finished Jul 19 05:14:42 PM PDT 24
Peak memory 194992 kb
Host smart-bb6efd3c-5d9a-4339-bfe3-dcb2adccfc28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180434289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.180434289
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.3594792909
Short name T205
Test name
Test status
Simulation time 238337935719 ps
CPU time 239.65 seconds
Started Jul 19 05:13:00 PM PDT 24
Finished Jul 19 05:17:01 PM PDT 24
Peak memory 191780 kb
Host smart-e507a954-ef27-43a4-a5f5-56fb5113473c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594792909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.3594792909
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.2922106417
Short name T174
Test name
Test status
Simulation time 75346502557 ps
CPU time 133.99 seconds
Started Jul 19 05:13:03 PM PDT 24
Finished Jul 19 05:15:17 PM PDT 24
Peak memory 191752 kb
Host smart-a88ba9ef-17c9-457f-b358-c85528b39c2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922106417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.2922106417
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.1521859805
Short name T165
Test name
Test status
Simulation time 297245167688 ps
CPU time 528.37 seconds
Started Jul 19 05:10:11 PM PDT 24
Finished Jul 19 05:19:01 PM PDT 24
Peak memory 191784 kb
Host smart-5e0a0c73-a30c-49e2-b952-3b12c92f4f0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521859805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
1521859805
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_random.1595014305
Short name T270
Test name
Test status
Simulation time 163900874658 ps
CPU time 1033.41 seconds
Started Jul 19 05:10:32 PM PDT 24
Finished Jul 19 05:27:47 PM PDT 24
Peak memory 194348 kb
Host smart-9631f9ab-8799-45a5-a569-0fa5e5fb7862
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595014305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.1595014305
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.2527191827
Short name T208
Test name
Test status
Simulation time 1392962191266 ps
CPU time 1648.05 seconds
Started Jul 19 05:10:31 PM PDT 24
Finished Jul 19 05:38:00 PM PDT 24
Peak memory 191808 kb
Host smart-30f387e4-6ed2-40c5-81ea-0d7e4eb9df8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527191827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.2527191827
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.1407119861
Short name T115
Test name
Test status
Simulation time 125440741226 ps
CPU time 111.59 seconds
Started Jul 19 05:10:41 PM PDT 24
Finished Jul 19 05:12:34 PM PDT 24
Peak memory 191764 kb
Host smart-0ae1a0f8-63d9-4d32-99e9-65f2a40d341c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407119861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.1407119861
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.3538058385
Short name T226
Test name
Test status
Simulation time 311519484838 ps
CPU time 59.23 seconds
Started Jul 19 05:10:40 PM PDT 24
Finished Jul 19 05:11:41 PM PDT 24
Peak memory 191796 kb
Host smart-cbeb4ef4-649f-4b8b-b6e3-e2f3f2805e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538058385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.3538058385
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.47942903
Short name T46
Test name
Test status
Simulation time 663938630479 ps
CPU time 1193.29 seconds
Started Jul 19 05:10:55 PM PDT 24
Finished Jul 19 05:30:49 PM PDT 24
Peak memory 191740 kb
Host smart-43754da0-c21f-4528-800e-c77a37ac384f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47942903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all.47942903
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_random.1357684549
Short name T162
Test name
Test status
Simulation time 806480410032 ps
CPU time 2327.57 seconds
Started Jul 19 05:10:14 PM PDT 24
Finished Jul 19 05:49:03 PM PDT 24
Peak memory 194920 kb
Host smart-4709c6e5-03bb-402d-9f66-748f654b4739
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357684549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.1357684549
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.821207754
Short name T309
Test name
Test status
Simulation time 2032792017 ps
CPU time 3.94 seconds
Started Jul 19 05:11:11 PM PDT 24
Finished Jul 19 05:11:16 PM PDT 24
Peak memory 183504 kb
Host smart-eea9c779-467a-4292-8141-179199d0eeca
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821207754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.rv_timer_cfg_update_on_fly.821207754
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.3980953089
Short name T302
Test name
Test status
Simulation time 95861706920 ps
CPU time 251.25 seconds
Started Jul 19 05:11:11 PM PDT 24
Finished Jul 19 05:15:23 PM PDT 24
Peak memory 191728 kb
Host smart-e8a34ac5-91e7-49c3-b90e-eff7042092b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980953089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.3980953089
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_random.3299405321
Short name T217
Test name
Test status
Simulation time 97745820928 ps
CPU time 140.2 seconds
Started Jul 19 05:11:21 PM PDT 24
Finished Jul 19 05:13:42 PM PDT 24
Peak memory 191804 kb
Host smart-9b66aecf-bcbd-4840-9acb-bd7badb40e68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299405321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.3299405321
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.2729920411
Short name T172
Test name
Test status
Simulation time 501200908733 ps
CPU time 315.49 seconds
Started Jul 19 05:11:37 PM PDT 24
Finished Jul 19 05:16:53 PM PDT 24
Peak memory 191748 kb
Host smart-4f9f9904-15c8-4c03-bc61-cf501b289bbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729920411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.2729920411
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.2767102497
Short name T209
Test name
Test status
Simulation time 437759473729 ps
CPU time 199.64 seconds
Started Jul 19 05:11:42 PM PDT 24
Finished Jul 19 05:15:03 PM PDT 24
Peak memory 191764 kb
Host smart-2bfcc70b-b36a-44c3-bcd6-b84147112692
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767102497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.2767102497
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.1387744787
Short name T170
Test name
Test status
Simulation time 165086744052 ps
CPU time 268.94 seconds
Started Jul 19 05:11:44 PM PDT 24
Finished Jul 19 05:16:14 PM PDT 24
Peak memory 191776 kb
Host smart-9684ab6a-edfa-4977-b383-f0fe3663deae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387744787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.1387744787
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.3827429667
Short name T317
Test name
Test status
Simulation time 516422460667 ps
CPU time 267.65 seconds
Started Jul 19 05:11:59 PM PDT 24
Finished Jul 19 05:16:27 PM PDT 24
Peak memory 191792 kb
Host smart-c08f8225-aa90-4124-93de-0baeb7114b57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827429667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.3827429667
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.277079772
Short name T503
Test name
Test status
Simulation time 536285244 ps
CPU time 1.49 seconds
Started Jul 19 05:06:25 PM PDT 24
Finished Jul 19 05:06:29 PM PDT 24
Peak memory 182700 kb
Host smart-1591e3cc-e238-4e81-980e-0ec87d4d4828
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277079772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_b
ash.277079772
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.1845622624
Short name T81
Test name
Test status
Simulation time 58144026 ps
CPU time 0.55 seconds
Started Jul 19 05:06:23 PM PDT 24
Finished Jul 19 05:06:25 PM PDT 24
Peak memory 182540 kb
Host smart-a41b5b57-4311-4149-aaf7-a17676932fcd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845622624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.1845622624
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.2593600907
Short name T50
Test name
Test status
Simulation time 79090625 ps
CPU time 0.67 seconds
Started Jul 19 05:06:24 PM PDT 24
Finished Jul 19 05:06:26 PM PDT 24
Peak memory 194908 kb
Host smart-55bda773-48b4-490c-9417-d08ba0cd55cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593600907 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.2593600907
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.705728006
Short name T465
Test name
Test status
Simulation time 14780982 ps
CPU time 0.56 seconds
Started Jul 19 05:06:23 PM PDT 24
Finished Jul 19 05:06:24 PM PDT 24
Peak memory 182448 kb
Host smart-603dea40-672e-4e80-9bce-4fe66c985f5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705728006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.705728006
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.917525314
Short name T531
Test name
Test status
Simulation time 21603183 ps
CPU time 0.77 seconds
Started Jul 19 05:06:24 PM PDT 24
Finished Jul 19 05:06:26 PM PDT 24
Peak memory 191476 kb
Host smart-f4d7a9fa-4440-421e-a2e6-19a0c58a5932
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917525314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_tim
er_same_csr_outstanding.917525314
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2429248864
Short name T537
Test name
Test status
Simulation time 63828696 ps
CPU time 3.16 seconds
Started Jul 19 05:06:27 PM PDT 24
Finished Jul 19 05:06:32 PM PDT 24
Peak memory 197288 kb
Host smart-45dc0d73-c2a2-4e49-bad5-b327a1603649
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429248864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.2429248864
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.1137775598
Short name T512
Test name
Test status
Simulation time 26482354 ps
CPU time 0.72 seconds
Started Jul 19 05:06:24 PM PDT 24
Finished Jul 19 05:06:26 PM PDT 24
Peak memory 182608 kb
Host smart-a361ff85-fb85-47d7-a301-2054b3299301
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137775598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.1137775598
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.507531799
Short name T82
Test name
Test status
Simulation time 87708751 ps
CPU time 3.2 seconds
Started Jul 19 05:06:26 PM PDT 24
Finished Jul 19 05:06:32 PM PDT 24
Peak memory 193724 kb
Host smart-6572b35d-70ac-49e5-9304-9a298d999ffd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507531799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_b
ash.507531799
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.3003753740
Short name T510
Test name
Test status
Simulation time 24669450 ps
CPU time 0.53 seconds
Started Jul 19 05:06:25 PM PDT 24
Finished Jul 19 05:06:27 PM PDT 24
Peak memory 182116 kb
Host smart-2b24c58c-d0f8-4b4e-9e1d-d1c0ac6d2213
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003753740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.3003753740
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.4173777578
Short name T514
Test name
Test status
Simulation time 356608086 ps
CPU time 0.83 seconds
Started Jul 19 05:06:23 PM PDT 24
Finished Jul 19 05:06:24 PM PDT 24
Peak memory 196472 kb
Host smart-1c634588-bf46-442f-8795-c2d3cb827ec6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173777578 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.4173777578
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.3851862644
Short name T86
Test name
Test status
Simulation time 125246926 ps
CPU time 0.54 seconds
Started Jul 19 05:06:24 PM PDT 24
Finished Jul 19 05:06:26 PM PDT 24
Peak memory 182560 kb
Host smart-5cc80a4e-b1e4-423e-82d6-b334c968fa21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851862644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.3851862644
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.1256979882
Short name T456
Test name
Test status
Simulation time 33648363 ps
CPU time 0.56 seconds
Started Jul 19 05:06:25 PM PDT 24
Finished Jul 19 05:06:27 PM PDT 24
Peak memory 182432 kb
Host smart-07b7676d-263e-4664-a729-af7943f5f407
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256979882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.1256979882
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.3278718435
Short name T530
Test name
Test status
Simulation time 57170171 ps
CPU time 0.78 seconds
Started Jul 19 05:06:24 PM PDT 24
Finished Jul 19 05:06:27 PM PDT 24
Peak memory 193432 kb
Host smart-aeb9dee2-75ea-42bd-ac63-69498302fd08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278718435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.3278718435
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.3156821447
Short name T455
Test name
Test status
Simulation time 97307582 ps
CPU time 2.08 seconds
Started Jul 19 05:06:25 PM PDT 24
Finished Jul 19 05:06:30 PM PDT 24
Peak memory 197332 kb
Host smart-46402bb6-cea3-4718-bcd1-642a22fd924d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156821447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.3156821447
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3072824599
Short name T502
Test name
Test status
Simulation time 808361176 ps
CPU time 1.39 seconds
Started Jul 19 05:06:26 PM PDT 24
Finished Jul 19 05:06:30 PM PDT 24
Peak memory 195132 kb
Host smart-4721a444-3234-4935-a99e-67f8e7038341
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072824599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.3072824599
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.4243455121
Short name T535
Test name
Test status
Simulation time 16143594 ps
CPU time 0.64 seconds
Started Jul 19 05:06:40 PM PDT 24
Finished Jul 19 05:06:42 PM PDT 24
Peak memory 192984 kb
Host smart-6dbd5e30-9f2b-4665-ae8f-75cc91c6d3f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243455121 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.4243455121
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.3041199388
Short name T485
Test name
Test status
Simulation time 20990130 ps
CPU time 0.54 seconds
Started Jul 19 05:06:44 PM PDT 24
Finished Jul 19 05:06:47 PM PDT 24
Peak memory 182464 kb
Host smart-a44ce301-0bd9-45f7-8aba-97120962fbee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041199388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.3041199388
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.2167487939
Short name T486
Test name
Test status
Simulation time 39852877 ps
CPU time 0.54 seconds
Started Jul 19 05:06:41 PM PDT 24
Finished Jul 19 05:06:43 PM PDT 24
Peak memory 182504 kb
Host smart-84dd7ada-d811-40e1-b80c-c0ef1967b97e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167487939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.2167487939
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2810766049
Short name T90
Test name
Test status
Simulation time 22407668 ps
CPU time 0.62 seconds
Started Jul 19 05:06:42 PM PDT 24
Finished Jul 19 05:06:45 PM PDT 24
Peak memory 191208 kb
Host smart-c8cb0684-e05d-47df-a262-fdfcee988c78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810766049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.2810766049
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.3810474777
Short name T475
Test name
Test status
Simulation time 380739654 ps
CPU time 2.23 seconds
Started Jul 19 05:06:40 PM PDT 24
Finished Jul 19 05:06:44 PM PDT 24
Peak memory 197308 kb
Host smart-2a45f5e0-98bc-4cd4-9b72-51753129b319
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810474777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.3810474777
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.3324689556
Short name T534
Test name
Test status
Simulation time 117021793 ps
CPU time 1.34 seconds
Started Jul 19 05:06:40 PM PDT 24
Finished Jul 19 05:06:43 PM PDT 24
Peak memory 195296 kb
Host smart-8648644c-6f99-466a-9fd4-67d3c67ea88e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324689556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.3324689556
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.2147577328
Short name T490
Test name
Test status
Simulation time 84359975 ps
CPU time 0.86 seconds
Started Jul 19 05:06:41 PM PDT 24
Finished Jul 19 05:06:44 PM PDT 24
Peak memory 196148 kb
Host smart-e5051214-b071-472d-90dc-82e8bcee0ef0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147577328 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.2147577328
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.210874891
Short name T78
Test name
Test status
Simulation time 51247433 ps
CPU time 0.6 seconds
Started Jul 19 05:06:42 PM PDT 24
Finished Jul 19 05:06:45 PM PDT 24
Peak memory 182592 kb
Host smart-f598d931-7f36-4c2a-b56d-d8cfbe2e9905
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210874891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.210874891
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.10222122
Short name T481
Test name
Test status
Simulation time 52278714 ps
CPU time 0.55 seconds
Started Jul 19 05:06:43 PM PDT 24
Finished Jul 19 05:06:46 PM PDT 24
Peak memory 182304 kb
Host smart-cd4935c8-a9c3-4798-9e0d-ee99978685d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10222122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.10222122
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.309876022
Short name T522
Test name
Test status
Simulation time 73940801 ps
CPU time 0.75 seconds
Started Jul 19 05:06:40 PM PDT 24
Finished Jul 19 05:06:43 PM PDT 24
Peak memory 193268 kb
Host smart-79063a92-1814-4ccc-8f36-44f40cafcf9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309876022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_ti
mer_same_csr_outstanding.309876022
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.4150027078
Short name T492
Test name
Test status
Simulation time 74623408 ps
CPU time 2.11 seconds
Started Jul 19 05:06:41 PM PDT 24
Finished Jul 19 05:06:45 PM PDT 24
Peak memory 197324 kb
Host smart-94f558a8-debe-479a-ba64-b8480d0375a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150027078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.4150027078
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3221802332
Short name T536
Test name
Test status
Simulation time 75549823 ps
CPU time 0.81 seconds
Started Jul 19 05:06:41 PM PDT 24
Finished Jul 19 05:06:44 PM PDT 24
Peak memory 193652 kb
Host smart-cf6875a9-8bf2-4ce6-a98e-b86c406c8c82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221802332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.3221802332
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.563252007
Short name T541
Test name
Test status
Simulation time 32759472 ps
CPU time 1.43 seconds
Started Jul 19 05:06:52 PM PDT 24
Finished Jul 19 05:06:56 PM PDT 24
Peak memory 197344 kb
Host smart-4b27590d-bcb8-41d7-94c8-ed549965aca6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563252007 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.563252007
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2603275900
Short name T546
Test name
Test status
Simulation time 12158658 ps
CPU time 0.55 seconds
Started Jul 19 05:06:43 PM PDT 24
Finished Jul 19 05:06:46 PM PDT 24
Peak memory 182328 kb
Host smart-f9fd96a2-d681-4414-9cf4-e9ab07eb5459
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603275900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.2603275900
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.1635863081
Short name T473
Test name
Test status
Simulation time 15809051 ps
CPU time 0.57 seconds
Started Jul 19 05:06:39 PM PDT 24
Finished Jul 19 05:06:40 PM PDT 24
Peak memory 182496 kb
Host smart-ac4a21b0-c3f8-444c-b9f5-15609ed206a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635863081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.1635863081
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1534816175
Short name T539
Test name
Test status
Simulation time 43883689 ps
CPU time 0.59 seconds
Started Jul 19 05:06:40 PM PDT 24
Finished Jul 19 05:06:43 PM PDT 24
Peak memory 191284 kb
Host smart-ed2dafe6-1b42-4992-82fc-c935ef05c925
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534816175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.1534816175
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.4232745861
Short name T476
Test name
Test status
Simulation time 84754639 ps
CPU time 1.13 seconds
Started Jul 19 05:06:43 PM PDT 24
Finished Jul 19 05:06:47 PM PDT 24
Peak memory 195960 kb
Host smart-9d465a3b-a4a1-4ab3-9db9-259d1cfa3612
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232745861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.4232745861
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.940001822
Short name T495
Test name
Test status
Simulation time 37381978 ps
CPU time 0.81 seconds
Started Jul 19 05:06:42 PM PDT 24
Finished Jul 19 05:06:45 PM PDT 24
Peak memory 193244 kb
Host smart-8054a358-901e-43c6-a189-2a1d4522d013
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940001822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_in
tg_err.940001822
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.93725136
Short name T571
Test name
Test status
Simulation time 164619944 ps
CPU time 0.91 seconds
Started Jul 19 05:06:51 PM PDT 24
Finished Jul 19 05:06:55 PM PDT 24
Peak memory 197136 kb
Host smart-d8140104-b7fb-4a42-847f-d838f945c103
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93725136 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.93725136
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3713433500
Short name T102
Test name
Test status
Simulation time 33044621 ps
CPU time 0.54 seconds
Started Jul 19 05:06:51 PM PDT 24
Finished Jul 19 05:06:54 PM PDT 24
Peak memory 182476 kb
Host smart-9d429862-40dc-44d2-999d-af3a20730f8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713433500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.3713433500
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.2559313475
Short name T528
Test name
Test status
Simulation time 37738851 ps
CPU time 0.56 seconds
Started Jul 19 05:06:51 PM PDT 24
Finished Jul 19 05:06:54 PM PDT 24
Peak memory 182468 kb
Host smart-f298f02b-2aee-4f39-a89b-3327d33c211f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559313475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.2559313475
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.3611298166
Short name T74
Test name
Test status
Simulation time 87976844 ps
CPU time 0.7 seconds
Started Jul 19 05:06:52 PM PDT 24
Finished Jul 19 05:06:55 PM PDT 24
Peak memory 191516 kb
Host smart-848da06b-039e-4738-8444-090042b04d2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611298166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.3611298166
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.2795009226
Short name T48
Test name
Test status
Simulation time 222355638 ps
CPU time 1.33 seconds
Started Jul 19 05:06:52 PM PDT 24
Finished Jul 19 05:06:55 PM PDT 24
Peak memory 197128 kb
Host smart-8d0614cd-d2a7-4c89-bcc0-6b4077bb04ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795009226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.2795009226
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1777340018
Short name T497
Test name
Test status
Simulation time 1056581136 ps
CPU time 1.31 seconds
Started Jul 19 05:06:50 PM PDT 24
Finished Jul 19 05:06:53 PM PDT 24
Peak memory 194876 kb
Host smart-8cf3614d-6143-44eb-8964-6e86486fc4bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777340018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.1777340018
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.538673583
Short name T501
Test name
Test status
Simulation time 16631816 ps
CPU time 0.66 seconds
Started Jul 19 05:06:51 PM PDT 24
Finished Jul 19 05:06:53 PM PDT 24
Peak memory 192960 kb
Host smart-98907ceb-acfa-49f6-8131-c31441b28a6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538673583 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.538673583
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.606427610
Short name T77
Test name
Test status
Simulation time 41709216 ps
CPU time 0.6 seconds
Started Jul 19 05:06:50 PM PDT 24
Finished Jul 19 05:06:52 PM PDT 24
Peak memory 182352 kb
Host smart-abb644a6-1a3c-472c-8b9c-a4f935580334
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606427610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.606427610
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.3080112026
Short name T570
Test name
Test status
Simulation time 18177633 ps
CPU time 0.57 seconds
Started Jul 19 05:06:50 PM PDT 24
Finished Jul 19 05:06:53 PM PDT 24
Peak memory 182392 kb
Host smart-351adc9b-2eb2-4934-bbd1-b7f575a654fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080112026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.3080112026
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.3306382595
Short name T92
Test name
Test status
Simulation time 34287011 ps
CPU time 0.61 seconds
Started Jul 19 05:06:49 PM PDT 24
Finished Jul 19 05:06:51 PM PDT 24
Peak memory 191744 kb
Host smart-8920471d-62c2-4730-894d-60a5be2023ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306382595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.3306382595
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2728251339
Short name T49
Test name
Test status
Simulation time 638412170 ps
CPU time 2.95 seconds
Started Jul 19 05:06:49 PM PDT 24
Finished Jul 19 05:06:53 PM PDT 24
Peak memory 197328 kb
Host smart-653d9bd4-ab02-415b-8d98-80bad226ee66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728251339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.2728251339
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.2210872856
Short name T527
Test name
Test status
Simulation time 167431662 ps
CPU time 0.82 seconds
Started Jul 19 05:06:51 PM PDT 24
Finished Jul 19 05:06:54 PM PDT 24
Peak memory 182864 kb
Host smart-f6636fee-cba8-4da9-95fa-822e48904a22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210872856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.2210872856
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.2874346353
Short name T567
Test name
Test status
Simulation time 37256289 ps
CPU time 0.88 seconds
Started Jul 19 05:06:53 PM PDT 24
Finished Jul 19 05:06:56 PM PDT 24
Peak memory 196616 kb
Host smart-0a558add-33ae-4139-bdb7-143d5af7a9a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874346353 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.2874346353
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.2535997936
Short name T80
Test name
Test status
Simulation time 14951857 ps
CPU time 0.57 seconds
Started Jul 19 05:06:49 PM PDT 24
Finished Jul 19 05:06:50 PM PDT 24
Peak memory 182600 kb
Host smart-b6b134e2-f95a-4ebd-b834-ba39759abef1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535997936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.2535997936
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.3770098575
Short name T576
Test name
Test status
Simulation time 33613757 ps
CPU time 0.6 seconds
Started Jul 19 05:06:51 PM PDT 24
Finished Jul 19 05:06:54 PM PDT 24
Peak memory 182436 kb
Host smart-506ef215-8558-4a51-b712-0e96ea12a8ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770098575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.3770098575
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.859153626
Short name T72
Test name
Test status
Simulation time 58198770 ps
CPU time 0.65 seconds
Started Jul 19 05:06:53 PM PDT 24
Finished Jul 19 05:06:56 PM PDT 24
Peak memory 191516 kb
Host smart-42a17566-7f8a-4f2b-b49b-2bd15f6b2590
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859153626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_ti
mer_same_csr_outstanding.859153626
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.3308928692
Short name T469
Test name
Test status
Simulation time 523123082 ps
CPU time 2.58 seconds
Started Jul 19 05:06:51 PM PDT 24
Finished Jul 19 05:06:56 PM PDT 24
Peak memory 197284 kb
Host smart-1df24e25-967f-4d9d-bd22-f7f5578b8d20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308928692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.3308928692
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.751482262
Short name T51
Test name
Test status
Simulation time 83907056 ps
CPU time 1.32 seconds
Started Jul 19 05:06:49 PM PDT 24
Finished Jul 19 05:06:52 PM PDT 24
Peak memory 193892 kb
Host smart-593e8e3c-cf70-4628-a079-2d10220824a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751482262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_in
tg_err.751482262
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.2740424434
Short name T461
Test name
Test status
Simulation time 105892098 ps
CPU time 0.81 seconds
Started Jul 19 05:06:52 PM PDT 24
Finished Jul 19 05:06:56 PM PDT 24
Peak memory 195824 kb
Host smart-d52785ba-60f8-4a36-9002-4dc2a7c0be53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740424434 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.2740424434
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.2856882759
Short name T538
Test name
Test status
Simulation time 12301233 ps
CPU time 0.52 seconds
Started Jul 19 05:06:52 PM PDT 24
Finished Jul 19 05:06:55 PM PDT 24
Peak memory 182308 kb
Host smart-b17a95ea-5797-448e-a319-d559908644ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856882759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.2856882759
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2676219331
Short name T470
Test name
Test status
Simulation time 153476867 ps
CPU time 0.58 seconds
Started Jul 19 05:06:52 PM PDT 24
Finished Jul 19 05:06:55 PM PDT 24
Peak memory 182444 kb
Host smart-2689f47f-d5b9-422d-b9fc-256306024e8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676219331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.2676219331
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.3519704053
Short name T89
Test name
Test status
Simulation time 28069755 ps
CPU time 0.74 seconds
Started Jul 19 05:06:51 PM PDT 24
Finished Jul 19 05:06:53 PM PDT 24
Peak memory 193184 kb
Host smart-3a4c00a8-a4f0-4e67-a55c-6effc35d1285
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519704053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.3519704053
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3061662170
Short name T518
Test name
Test status
Simulation time 32390847 ps
CPU time 1.71 seconds
Started Jul 19 05:06:52 PM PDT 24
Finished Jul 19 05:06:56 PM PDT 24
Peak memory 197316 kb
Host smart-ae184e46-4bf9-4232-a50a-f97a7fe65280
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061662170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.3061662170
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.610508629
Short name T30
Test name
Test status
Simulation time 111258520 ps
CPU time 0.87 seconds
Started Jul 19 05:06:50 PM PDT 24
Finished Jul 19 05:06:52 PM PDT 24
Peak memory 193780 kb
Host smart-d0e42e8d-52e8-472f-a622-7d94c2ca0c1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610508629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_in
tg_err.610508629
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.2663626928
Short name T548
Test name
Test status
Simulation time 35764748 ps
CPU time 0.91 seconds
Started Jul 19 05:07:15 PM PDT 24
Finished Jul 19 05:07:19 PM PDT 24
Peak memory 196612 kb
Host smart-f2685216-16a6-4a94-850b-03d7fd7c1bcf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663626928 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.2663626928
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.395563711
Short name T85
Test name
Test status
Simulation time 15024667 ps
CPU time 0.6 seconds
Started Jul 19 05:07:00 PM PDT 24
Finished Jul 19 05:07:03 PM PDT 24
Peak memory 182548 kb
Host smart-128fb24a-f47b-4d23-9be1-324fbff80dd8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395563711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.395563711
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1302808725
Short name T558
Test name
Test status
Simulation time 44905637 ps
CPU time 0.57 seconds
Started Jul 19 05:07:00 PM PDT 24
Finished Jul 19 05:07:03 PM PDT 24
Peak memory 182440 kb
Host smart-794d9f4b-8250-40bc-bd21-75f37ff7ab45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302808725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.1302808725
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.3441723089
Short name T562
Test name
Test status
Simulation time 122048366 ps
CPU time 0.84 seconds
Started Jul 19 05:07:04 PM PDT 24
Finished Jul 19 05:07:06 PM PDT 24
Peak memory 191544 kb
Host smart-b5449965-ff66-4664-975e-31f44b8f4298
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441723089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.3441723089
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.1218521285
Short name T533
Test name
Test status
Simulation time 40370319 ps
CPU time 1.92 seconds
Started Jul 19 05:06:50 PM PDT 24
Finished Jul 19 05:06:54 PM PDT 24
Peak memory 197312 kb
Host smart-41c1506f-c921-476f-9775-c04d397a5ed0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218521285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.1218521285
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.184174526
Short name T519
Test name
Test status
Simulation time 32579968 ps
CPU time 1.56 seconds
Started Jul 19 05:06:57 PM PDT 24
Finished Jul 19 05:06:59 PM PDT 24
Peak memory 197328 kb
Host smart-fcd463e6-cf2f-43f3-b0c8-51ce64a20e1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184174526 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.184174526
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.1790594864
Short name T76
Test name
Test status
Simulation time 13488637 ps
CPU time 0.56 seconds
Started Jul 19 05:07:00 PM PDT 24
Finished Jul 19 05:07:04 PM PDT 24
Peak memory 182376 kb
Host smart-1cff2f57-7357-4bfd-a15f-cfa735122b49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790594864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.1790594864
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.2275224519
Short name T564
Test name
Test status
Simulation time 13113757 ps
CPU time 0.54 seconds
Started Jul 19 05:06:58 PM PDT 24
Finished Jul 19 05:06:59 PM PDT 24
Peak memory 181948 kb
Host smart-773d8a48-4cdb-449a-a678-2f6eeb27592b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275224519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.2275224519
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.4221505321
Short name T556
Test name
Test status
Simulation time 266690635 ps
CPU time 0.69 seconds
Started Jul 19 05:06:57 PM PDT 24
Finished Jul 19 05:06:59 PM PDT 24
Peak memory 192172 kb
Host smart-c8148465-2169-4c42-a396-4fc3f0ad4fd4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221505321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.4221505321
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.862895856
Short name T494
Test name
Test status
Simulation time 179335378 ps
CPU time 3.07 seconds
Started Jul 19 05:07:00 PM PDT 24
Finished Jul 19 05:07:05 PM PDT 24
Peak memory 197320 kb
Host smart-76d25432-068d-4408-8631-d156fbe4e72d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862895856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.862895856
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.4013203919
Short name T544
Test name
Test status
Simulation time 95691383 ps
CPU time 0.8 seconds
Started Jul 19 05:06:58 PM PDT 24
Finished Jul 19 05:06:59 PM PDT 24
Peak memory 182884 kb
Host smart-281007eb-7089-4a35-9659-6103ec0b3070
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013203919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.4013203919
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.1910953924
Short name T458
Test name
Test status
Simulation time 68423532 ps
CPU time 0.6 seconds
Started Jul 19 05:06:58 PM PDT 24
Finished Jul 19 05:07:00 PM PDT 24
Peak memory 192940 kb
Host smart-a9aec97d-870b-4e92-8878-841b397d6eb9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910953924 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.1910953924
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.798224386
Short name T84
Test name
Test status
Simulation time 18468514 ps
CPU time 0.59 seconds
Started Jul 19 05:06:58 PM PDT 24
Finished Jul 19 05:06:59 PM PDT 24
Peak memory 182520 kb
Host smart-e4ea289e-d118-4e80-a27a-7c580005fe59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798224386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.798224386
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.371898318
Short name T565
Test name
Test status
Simulation time 12114480 ps
CPU time 0.54 seconds
Started Jul 19 05:07:00 PM PDT 24
Finished Jul 19 05:07:03 PM PDT 24
Peak memory 181620 kb
Host smart-131a9707-d9b2-40fe-ab24-67aa571f18d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371898318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.371898318
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2984855054
Short name T87
Test name
Test status
Simulation time 55601178 ps
CPU time 0.74 seconds
Started Jul 19 05:07:00 PM PDT 24
Finished Jul 19 05:07:03 PM PDT 24
Peak memory 192560 kb
Host smart-d9d748b5-224f-44f2-b3f1-f377c2cf2c5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984855054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.2984855054
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.1651267163
Short name T479
Test name
Test status
Simulation time 213885875 ps
CPU time 1.27 seconds
Started Jul 19 05:07:00 PM PDT 24
Finished Jul 19 05:07:03 PM PDT 24
Peak memory 197104 kb
Host smart-2501561b-f95b-4145-9d4f-56af4f8a9f6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651267163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.1651267163
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.3905327377
Short name T581
Test name
Test status
Simulation time 128588576 ps
CPU time 1.38 seconds
Started Jul 19 05:07:00 PM PDT 24
Finished Jul 19 05:07:05 PM PDT 24
Peak memory 195220 kb
Host smart-8c4b0b70-c975-4371-9e15-e56f80b85600
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905327377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.3905327377
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.108915929
Short name T553
Test name
Test status
Simulation time 35942346 ps
CPU time 0.63 seconds
Started Jul 19 05:06:25 PM PDT 24
Finished Jul 19 05:06:28 PM PDT 24
Peak memory 182552 kb
Host smart-7ef1e0cb-f501-45b9-a945-e45388c0bdfd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108915929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alias
ing.108915929
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1041450399
Short name T500
Test name
Test status
Simulation time 719453257 ps
CPU time 2.51 seconds
Started Jul 19 05:06:25 PM PDT 24
Finished Jul 19 05:06:30 PM PDT 24
Peak memory 190860 kb
Host smart-c4d7a65f-2d4a-4096-8a6e-38bc50db92cf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041450399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.1041450399
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.1397339383
Short name T580
Test name
Test status
Simulation time 76687942 ps
CPU time 0.56 seconds
Started Jul 19 05:06:23 PM PDT 24
Finished Jul 19 05:06:25 PM PDT 24
Peak memory 182588 kb
Host smart-7622b513-253d-4fa1-b257-53f4645b8c23
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397339383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.1397339383
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3577328241
Short name T459
Test name
Test status
Simulation time 31822290 ps
CPU time 1.46 seconds
Started Jul 19 05:06:24 PM PDT 24
Finished Jul 19 05:06:27 PM PDT 24
Peak memory 197352 kb
Host smart-40716fb5-307b-4cbd-8b20-b7f17686f777
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577328241 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.3577328241
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.738742561
Short name T508
Test name
Test status
Simulation time 40727038 ps
CPU time 0.54 seconds
Started Jul 19 05:06:25 PM PDT 24
Finished Jul 19 05:06:28 PM PDT 24
Peak memory 182272 kb
Host smart-a5159b90-a7b4-484c-b5bf-219c75ea3b59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738742561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.738742561
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.3377629673
Short name T472
Test name
Test status
Simulation time 16760052 ps
CPU time 0.59 seconds
Started Jul 19 05:06:24 PM PDT 24
Finished Jul 19 05:06:27 PM PDT 24
Peak memory 182508 kb
Host smart-6a9314f9-6658-4b18-b1e4-3328397df964
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377629673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.3377629673
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.935504252
Short name T563
Test name
Test status
Simulation time 33551453 ps
CPU time 0.92 seconds
Started Jul 19 05:06:26 PM PDT 24
Finished Jul 19 05:06:29 PM PDT 24
Peak memory 193912 kb
Host smart-16b3e366-9a6b-499b-8b6c-51c5b94f9c3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935504252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_tim
er_same_csr_outstanding.935504252
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.2856222614
Short name T477
Test name
Test status
Simulation time 193751262 ps
CPU time 3.32 seconds
Started Jul 19 05:06:26 PM PDT 24
Finished Jul 19 05:06:31 PM PDT 24
Peak memory 197216 kb
Host smart-920f3f8f-6ea1-4f30-bb57-826e66dee6ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856222614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.2856222614
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.1190750662
Short name T489
Test name
Test status
Simulation time 438549980 ps
CPU time 1.33 seconds
Started Jul 19 05:06:25 PM PDT 24
Finished Jul 19 05:06:29 PM PDT 24
Peak memory 195004 kb
Host smart-ed8d703d-9831-476e-883d-b7525b18f293
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190750662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.1190750662
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.1502129920
Short name T487
Test name
Test status
Simulation time 13171086 ps
CPU time 0.56 seconds
Started Jul 19 05:07:01 PM PDT 24
Finished Jul 19 05:07:04 PM PDT 24
Peak memory 181956 kb
Host smart-1b76b34d-fd21-402f-a7ba-dea3e37306ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502129920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.1502129920
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1930074427
Short name T474
Test name
Test status
Simulation time 14166634 ps
CPU time 0.54 seconds
Started Jul 19 05:06:58 PM PDT 24
Finished Jul 19 05:07:00 PM PDT 24
Peak memory 181968 kb
Host smart-184a221f-21c2-4450-a4de-815cdfa825a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930074427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.1930074427
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.2271531505
Short name T483
Test name
Test status
Simulation time 12678538 ps
CPU time 0.55 seconds
Started Jul 19 05:06:58 PM PDT 24
Finished Jul 19 05:07:01 PM PDT 24
Peak memory 181920 kb
Host smart-aa23c4a7-cf22-4cc7-a681-06c3a704f7df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271531505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.2271531505
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.2410635817
Short name T547
Test name
Test status
Simulation time 11880407 ps
CPU time 0.55 seconds
Started Jul 19 05:06:59 PM PDT 24
Finished Jul 19 05:07:01 PM PDT 24
Peak memory 181968 kb
Host smart-a9a3908a-cd65-4645-bb8e-bdad2cf4537d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410635817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.2410635817
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.3427388968
Short name T554
Test name
Test status
Simulation time 55778473 ps
CPU time 0.59 seconds
Started Jul 19 05:06:59 PM PDT 24
Finished Jul 19 05:07:02 PM PDT 24
Peak memory 182392 kb
Host smart-d82f06c9-0421-4727-833f-5389aeff44cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427388968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.3427388968
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.2430707953
Short name T523
Test name
Test status
Simulation time 102990796 ps
CPU time 0.55 seconds
Started Jul 19 05:07:00 PM PDT 24
Finished Jul 19 05:07:03 PM PDT 24
Peak memory 182428 kb
Host smart-23514d08-fb51-45c0-9321-95202f2fb308
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430707953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.2430707953
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.982753527
Short name T521
Test name
Test status
Simulation time 17705001 ps
CPU time 0.62 seconds
Started Jul 19 05:06:58 PM PDT 24
Finished Jul 19 05:07:01 PM PDT 24
Peak memory 182496 kb
Host smart-b841c151-f409-4743-937b-d4cfd62dcc7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982753527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.982753527
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.440963829
Short name T555
Test name
Test status
Simulation time 20673626 ps
CPU time 0.55 seconds
Started Jul 19 05:07:01 PM PDT 24
Finished Jul 19 05:07:04 PM PDT 24
Peak memory 181956 kb
Host smart-f8b15e93-f857-4a1f-86d6-c0f7b4e977e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440963829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.440963829
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.521994281
Short name T513
Test name
Test status
Simulation time 58141323 ps
CPU time 0.58 seconds
Started Jul 19 05:06:58 PM PDT 24
Finished Jul 19 05:06:59 PM PDT 24
Peak memory 182408 kb
Host smart-238571af-895f-4a36-b0f6-8573e83e3f0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521994281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.521994281
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.2339657511
Short name T572
Test name
Test status
Simulation time 34931361 ps
CPU time 0.54 seconds
Started Jul 19 05:07:00 PM PDT 24
Finished Jul 19 05:07:03 PM PDT 24
Peak memory 182424 kb
Host smart-bc2f2c6b-eeba-442f-8466-2ebc9c04b638
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339657511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.2339657511
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3560140612
Short name T73
Test name
Test status
Simulation time 26091588 ps
CPU time 0.72 seconds
Started Jul 19 05:06:36 PM PDT 24
Finished Jul 19 05:06:38 PM PDT 24
Peak memory 191768 kb
Host smart-339a3b3d-471e-4557-b2b3-6d52a9a863c2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560140612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.3560140612
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.2880554118
Short name T566
Test name
Test status
Simulation time 139258400 ps
CPU time 1.38 seconds
Started Jul 19 05:06:33 PM PDT 24
Finished Jul 19 05:06:36 PM PDT 24
Peak memory 191852 kb
Host smart-b2e9f292-ff3b-4d20-80c1-357343b0e0f9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880554118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.2880554118
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.530695690
Short name T498
Test name
Test status
Simulation time 14373769 ps
CPU time 0.55 seconds
Started Jul 19 05:06:38 PM PDT 24
Finished Jul 19 05:06:39 PM PDT 24
Peak memory 182196 kb
Host smart-c774b59f-0c94-48df-8d4d-60a77c677f01
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530695690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_re
set.530695690
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.39671365
Short name T545
Test name
Test status
Simulation time 17099390 ps
CPU time 0.61 seconds
Started Jul 19 05:06:36 PM PDT 24
Finished Jul 19 05:06:38 PM PDT 24
Peak memory 193008 kb
Host smart-7e9f750a-70c2-4dd1-b79c-96f12d4398c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39671365 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.39671365
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.2302807897
Short name T466
Test name
Test status
Simulation time 28445618 ps
CPU time 0.62 seconds
Started Jul 19 05:06:32 PM PDT 24
Finished Jul 19 05:06:33 PM PDT 24
Peak memory 191816 kb
Host smart-944faa94-d68c-480c-9789-ad529f682350
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302807897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.2302807897
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.4085400482
Short name T496
Test name
Test status
Simulation time 83300495 ps
CPU time 0.54 seconds
Started Jul 19 05:06:32 PM PDT 24
Finished Jul 19 05:06:34 PM PDT 24
Peak memory 182448 kb
Host smart-32f474ae-81c8-452e-bc0a-02b177885c15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085400482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.4085400482
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.3389986887
Short name T75
Test name
Test status
Simulation time 66432784 ps
CPU time 0.7 seconds
Started Jul 19 05:06:33 PM PDT 24
Finished Jul 19 05:06:35 PM PDT 24
Peak memory 193028 kb
Host smart-25517f37-c87e-46e6-a8a5-fa41701a9633
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389986887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.3389986887
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.603422681
Short name T488
Test name
Test status
Simulation time 305034899 ps
CPU time 1.44 seconds
Started Jul 19 05:06:24 PM PDT 24
Finished Jul 19 05:06:27 PM PDT 24
Peak memory 197300 kb
Host smart-d9e8dd5a-7a7a-4166-8877-e090daeb0b3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603422681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.603422681
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.1026848967
Short name T573
Test name
Test status
Simulation time 214237848 ps
CPU time 0.82 seconds
Started Jul 19 05:06:24 PM PDT 24
Finished Jul 19 05:06:27 PM PDT 24
Peak memory 192972 kb
Host smart-297a2118-6898-4dab-a4b5-d3bdadfcb136
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026848967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.1026848967
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.2476613312
Short name T543
Test name
Test status
Simulation time 43177347 ps
CPU time 0.53 seconds
Started Jul 19 05:06:58 PM PDT 24
Finished Jul 19 05:07:00 PM PDT 24
Peak memory 181940 kb
Host smart-a207f7cc-4d04-4602-907f-2b13004799f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476613312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.2476613312
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.2959389709
Short name T463
Test name
Test status
Simulation time 74489669 ps
CPU time 0.55 seconds
Started Jul 19 05:07:15 PM PDT 24
Finished Jul 19 05:07:19 PM PDT 24
Peak memory 182296 kb
Host smart-700e0ef6-dbd2-48d9-b72c-90aaf8e7b475
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959389709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.2959389709
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.326143006
Short name T471
Test name
Test status
Simulation time 43504235 ps
CPU time 0.53 seconds
Started Jul 19 05:07:15 PM PDT 24
Finished Jul 19 05:07:19 PM PDT 24
Peak memory 182032 kb
Host smart-81a56549-1705-4100-85ba-e63297705ad5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326143006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.326143006
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.753147044
Short name T493
Test name
Test status
Simulation time 15320393 ps
CPU time 0.57 seconds
Started Jul 19 05:07:02 PM PDT 24
Finished Jul 19 05:07:05 PM PDT 24
Peak memory 182452 kb
Host smart-232e672e-1c3a-4928-a3bc-7100cecf218f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753147044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.753147044
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.2239904489
Short name T460
Test name
Test status
Simulation time 17840817 ps
CPU time 0.57 seconds
Started Jul 19 05:07:15 PM PDT 24
Finished Jul 19 05:07:19 PM PDT 24
Peak memory 182296 kb
Host smart-5e16d412-a48d-4659-97b6-2ac8fed42054
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239904489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.2239904489
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2136422357
Short name T468
Test name
Test status
Simulation time 15207815 ps
CPU time 0.57 seconds
Started Jul 19 05:07:17 PM PDT 24
Finished Jul 19 05:07:21 PM PDT 24
Peak memory 182464 kb
Host smart-f567bfdb-23ee-498b-bb97-73ad81468c15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136422357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.2136422357
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.3863401857
Short name T542
Test name
Test status
Simulation time 46111406 ps
CPU time 0.57 seconds
Started Jul 19 05:07:15 PM PDT 24
Finished Jul 19 05:07:18 PM PDT 24
Peak memory 181804 kb
Host smart-d68665ad-1adf-4976-bf74-37a408648b57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863401857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.3863401857
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.1148346176
Short name T467
Test name
Test status
Simulation time 22786621 ps
CPU time 0.62 seconds
Started Jul 19 05:07:02 PM PDT 24
Finished Jul 19 05:07:05 PM PDT 24
Peak memory 182504 kb
Host smart-7093e2bb-a4d1-4b43-b6b5-5e74f20c1b7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148346176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.1148346176
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.2904918470
Short name T457
Test name
Test status
Simulation time 18427961 ps
CPU time 0.59 seconds
Started Jul 19 05:07:00 PM PDT 24
Finished Jul 19 05:07:03 PM PDT 24
Peak memory 182504 kb
Host smart-4215029b-be4d-43b5-802f-c550e7380fac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904918470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.2904918470
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.134975754
Short name T569
Test name
Test status
Simulation time 14359879 ps
CPU time 0.56 seconds
Started Jul 19 05:06:59 PM PDT 24
Finished Jul 19 05:07:02 PM PDT 24
Peak memory 182024 kb
Host smart-29b83e0b-fe93-401d-8acd-752471aa5de2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134975754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.134975754
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1322434605
Short name T515
Test name
Test status
Simulation time 123092177 ps
CPU time 0.83 seconds
Started Jul 19 05:06:33 PM PDT 24
Finished Jul 19 05:06:36 PM PDT 24
Peak memory 182592 kb
Host smart-da37f604-9dfc-489f-93c3-8a42822c42a6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322434605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.1322434605
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.3780794459
Short name T31
Test name
Test status
Simulation time 976007047 ps
CPU time 2.3 seconds
Started Jul 19 05:06:33 PM PDT 24
Finished Jul 19 05:06:36 PM PDT 24
Peak memory 190724 kb
Host smart-7abab0ef-6ccf-4daa-97f3-6c51e44b1b77
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780794459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.3780794459
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2842817265
Short name T52
Test name
Test status
Simulation time 32276809 ps
CPU time 0.59 seconds
Started Jul 19 05:06:33 PM PDT 24
Finished Jul 19 05:06:35 PM PDT 24
Peak memory 182592 kb
Host smart-2bfa0577-412f-4d28-8aa2-8dff243ae317
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842817265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.2842817265
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3990942136
Short name T491
Test name
Test status
Simulation time 39685737 ps
CPU time 0.95 seconds
Started Jul 19 05:06:33 PM PDT 24
Finished Jul 19 05:06:35 PM PDT 24
Peak memory 197080 kb
Host smart-91ec8506-95b6-4adc-ae9b-4a9235de06e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990942136 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.3990942136
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.3422600087
Short name T79
Test name
Test status
Simulation time 98342895 ps
CPU time 0.57 seconds
Started Jul 19 05:06:37 PM PDT 24
Finished Jul 19 05:06:39 PM PDT 24
Peak memory 182552 kb
Host smart-71fec74b-60b8-4712-bf9d-4b1e86d807ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422600087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.3422600087
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.3615510307
Short name T462
Test name
Test status
Simulation time 147799976 ps
CPU time 0.55 seconds
Started Jul 19 05:06:36 PM PDT 24
Finished Jul 19 05:06:37 PM PDT 24
Peak memory 182480 kb
Host smart-8bf656b4-1fd4-408a-aa7b-ba2781d506b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615510307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.3615510307
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.2658772428
Short name T532
Test name
Test status
Simulation time 35692886 ps
CPU time 0.7 seconds
Started Jul 19 05:06:34 PM PDT 24
Finished Jul 19 05:06:36 PM PDT 24
Peak memory 192984 kb
Host smart-217af898-915e-416d-9e40-daa8428979df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658772428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.2658772428
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2399203253
Short name T482
Test name
Test status
Simulation time 132120384 ps
CPU time 2.43 seconds
Started Jul 19 05:06:33 PM PDT 24
Finished Jul 19 05:06:37 PM PDT 24
Peak memory 197336 kb
Host smart-ec5a42fc-82ed-4cab-8f3f-6e77561865d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399203253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.2399203253
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2893808415
Short name T557
Test name
Test status
Simulation time 89532168 ps
CPU time 1.09 seconds
Started Jul 19 05:06:32 PM PDT 24
Finished Jul 19 05:06:35 PM PDT 24
Peak memory 183136 kb
Host smart-11d50180-0e79-47c4-bc65-d7c776d8d3fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893808415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.2893808415
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.2944901943
Short name T454
Test name
Test status
Simulation time 13900511 ps
CPU time 0.58 seconds
Started Jul 19 05:06:59 PM PDT 24
Finished Jul 19 05:07:02 PM PDT 24
Peak memory 182464 kb
Host smart-40d30b78-39ce-4a14-9ba3-12bd13bfe0e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944901943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.2944901943
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.1668709848
Short name T540
Test name
Test status
Simulation time 15111581 ps
CPU time 0.57 seconds
Started Jul 19 05:06:58 PM PDT 24
Finished Jul 19 05:07:00 PM PDT 24
Peak memory 182072 kb
Host smart-c4628e93-4036-4a3b-91e0-e49d2861b1e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668709848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.1668709848
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1890442632
Short name T568
Test name
Test status
Simulation time 24999687 ps
CPU time 0.55 seconds
Started Jul 19 05:07:01 PM PDT 24
Finished Jul 19 05:07:04 PM PDT 24
Peak memory 182148 kb
Host smart-a1b37563-fec1-412c-8a66-d7441a751a1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890442632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.1890442632
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.2407517566
Short name T575
Test name
Test status
Simulation time 15100319 ps
CPU time 0.61 seconds
Started Jul 19 05:07:15 PM PDT 24
Finished Jul 19 05:07:19 PM PDT 24
Peak memory 182056 kb
Host smart-f6f7d9db-ee64-4761-8bf8-20bac08d37b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407517566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.2407517566
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.2998202598
Short name T464
Test name
Test status
Simulation time 47811915 ps
CPU time 0.55 seconds
Started Jul 19 05:07:15 PM PDT 24
Finished Jul 19 05:07:19 PM PDT 24
Peak memory 182036 kb
Host smart-83d97881-4fff-4253-838a-ae9eba43a726
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998202598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.2998202598
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.746457346
Short name T529
Test name
Test status
Simulation time 79272111 ps
CPU time 0.55 seconds
Started Jul 19 05:07:06 PM PDT 24
Finished Jul 19 05:07:09 PM PDT 24
Peak memory 182452 kb
Host smart-6f58b7f8-a4ef-49a4-b260-cbebb940b262
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746457346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.746457346
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.358795327
Short name T453
Test name
Test status
Simulation time 34842687 ps
CPU time 0.53 seconds
Started Jul 19 05:07:05 PM PDT 24
Finished Jul 19 05:07:07 PM PDT 24
Peak memory 181904 kb
Host smart-45ff9f2f-695a-4524-9c2b-80ff33e29667
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358795327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.358795327
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.3172401179
Short name T480
Test name
Test status
Simulation time 182886667 ps
CPU time 0.55 seconds
Started Jul 19 05:07:07 PM PDT 24
Finished Jul 19 05:07:10 PM PDT 24
Peak memory 182396 kb
Host smart-5e381a3f-eaf7-4273-aa4c-3f76a007574e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172401179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.3172401179
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.580065330
Short name T516
Test name
Test status
Simulation time 56327557 ps
CPU time 0.58 seconds
Started Jul 19 05:07:08 PM PDT 24
Finished Jul 19 05:07:11 PM PDT 24
Peak memory 182500 kb
Host smart-0deff616-eafe-400c-a6ec-9b60cc220525
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580065330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.580065330
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.3121748527
Short name T452
Test name
Test status
Simulation time 13763803 ps
CPU time 0.56 seconds
Started Jul 19 05:07:07 PM PDT 24
Finished Jul 19 05:07:10 PM PDT 24
Peak memory 181896 kb
Host smart-0b430894-4440-4a16-82fb-022d916845db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121748527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.3121748527
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.1268805876
Short name T517
Test name
Test status
Simulation time 35670470 ps
CPU time 1.55 seconds
Started Jul 19 05:06:36 PM PDT 24
Finished Jul 19 05:06:39 PM PDT 24
Peak memory 197316 kb
Host smart-3d7567e3-6b5a-472d-bcf6-b5e9e5120827
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268805876 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.1268805876
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.2794909553
Short name T552
Test name
Test status
Simulation time 13769140 ps
CPU time 0.56 seconds
Started Jul 19 05:06:34 PM PDT 24
Finished Jul 19 05:06:36 PM PDT 24
Peak memory 182284 kb
Host smart-da4855c2-5718-45d1-8a7d-49377bf474ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794909553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.2794909553
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1336085001
Short name T577
Test name
Test status
Simulation time 105358448 ps
CPU time 0.57 seconds
Started Jul 19 05:06:34 PM PDT 24
Finished Jul 19 05:06:36 PM PDT 24
Peak memory 182472 kb
Host smart-dcdce16a-e706-4840-ae67-2f8bdb9ed584
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336085001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.1336085001
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2822513229
Short name T520
Test name
Test status
Simulation time 68291516 ps
CPU time 0.87 seconds
Started Jul 19 05:06:33 PM PDT 24
Finished Jul 19 05:06:36 PM PDT 24
Peak memory 193368 kb
Host smart-7ce7a1ce-4bb5-47d8-a10f-4fbc9dfab9db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822513229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.2822513229
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.3488365659
Short name T559
Test name
Test status
Simulation time 376457996 ps
CPU time 1.82 seconds
Started Jul 19 05:06:33 PM PDT 24
Finished Jul 19 05:06:37 PM PDT 24
Peak memory 197332 kb
Host smart-0c3acfdf-e912-42f9-870b-1cb08bc5aa68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488365659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.3488365659
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.316926378
Short name T525
Test name
Test status
Simulation time 156040552 ps
CPU time 1.13 seconds
Started Jul 19 05:06:38 PM PDT 24
Finished Jul 19 05:06:40 PM PDT 24
Peak memory 194904 kb
Host smart-7ade50a8-274e-400b-9ace-6c74f7c37bb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316926378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_int
g_err.316926378
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.2298430508
Short name T549
Test name
Test status
Simulation time 135310113 ps
CPU time 0.89 seconds
Started Jul 19 05:06:41 PM PDT 24
Finished Jul 19 05:06:44 PM PDT 24
Peak memory 196316 kb
Host smart-0b629165-f6e1-442e-a012-dbf5a971154d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298430508 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.2298430508
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.3548477019
Short name T71
Test name
Test status
Simulation time 13089060 ps
CPU time 0.6 seconds
Started Jul 19 05:06:38 PM PDT 24
Finished Jul 19 05:06:39 PM PDT 24
Peak memory 182560 kb
Host smart-fc222be4-4eb0-4473-ab1e-3c5e4a75858b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548477019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.3548477019
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.1170201667
Short name T579
Test name
Test status
Simulation time 16962191 ps
CPU time 0.55 seconds
Started Jul 19 05:06:35 PM PDT 24
Finished Jul 19 05:06:36 PM PDT 24
Peak memory 182480 kb
Host smart-5ef9af37-5544-4a2a-b0a2-757e1cde9ac6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170201667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.1170201667
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.3484924796
Short name T88
Test name
Test status
Simulation time 35216776 ps
CPU time 0.79 seconds
Started Jul 19 05:06:40 PM PDT 24
Finished Jul 19 05:06:42 PM PDT 24
Peak memory 191556 kb
Host smart-4a265ea1-13f5-4a61-8959-5f554aa56e60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484924796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.3484924796
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.3447802822
Short name T511
Test name
Test status
Simulation time 216133324 ps
CPU time 2.32 seconds
Started Jul 19 05:06:33 PM PDT 24
Finished Jul 19 05:06:37 PM PDT 24
Peak memory 197276 kb
Host smart-6c20abdc-9b4f-4871-a9fb-23dddd54bdbe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447802822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.3447802822
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.447872495
Short name T561
Test name
Test status
Simulation time 94621184 ps
CPU time 1.32 seconds
Started Jul 19 05:06:34 PM PDT 24
Finished Jul 19 05:06:37 PM PDT 24
Peak memory 183044 kb
Host smart-abc75083-8982-47b1-9fd2-534de76178d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447872495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_int
g_err.447872495
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2190296983
Short name T574
Test name
Test status
Simulation time 122170258 ps
CPU time 1.37 seconds
Started Jul 19 05:06:42 PM PDT 24
Finished Jul 19 05:06:45 PM PDT 24
Peak memory 197388 kb
Host smart-cca6e37b-bc88-44ed-87bf-91b19b1f610d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190296983 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.2190296983
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.3020935432
Short name T499
Test name
Test status
Simulation time 20793595 ps
CPU time 0.59 seconds
Started Jul 19 05:06:39 PM PDT 24
Finished Jul 19 05:06:41 PM PDT 24
Peak memory 182516 kb
Host smart-23076a81-e716-4b4e-9f37-6bba50213dbc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020935432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.3020935432
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.2135907103
Short name T478
Test name
Test status
Simulation time 46054226 ps
CPU time 0.52 seconds
Started Jul 19 05:06:43 PM PDT 24
Finished Jul 19 05:06:46 PM PDT 24
Peak memory 181960 kb
Host smart-cfd1bb67-0028-4c05-aeaa-e9cebcb1b175
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135907103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.2135907103
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.979697239
Short name T526
Test name
Test status
Simulation time 20593278 ps
CPU time 0.66 seconds
Started Jul 19 05:06:41 PM PDT 24
Finished Jul 19 05:06:44 PM PDT 24
Peak memory 191052 kb
Host smart-b46cf4af-c5df-419c-9a7b-a5b83ecb3a75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979697239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_tim
er_same_csr_outstanding.979697239
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.3580148115
Short name T507
Test name
Test status
Simulation time 61075243 ps
CPU time 1.59 seconds
Started Jul 19 05:06:41 PM PDT 24
Finished Jul 19 05:06:45 PM PDT 24
Peak memory 197324 kb
Host smart-583e7bd3-eff8-4257-b7d6-3c83868336e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580148115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.3580148115
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.1473422220
Short name T103
Test name
Test status
Simulation time 201404954 ps
CPU time 1.4 seconds
Started Jul 19 05:06:40 PM PDT 24
Finished Jul 19 05:06:43 PM PDT 24
Peak memory 182888 kb
Host smart-ada4f5b3-7566-4356-b710-796787935cce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473422220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.1473422220
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3353590025
Short name T560
Test name
Test status
Simulation time 46897271 ps
CPU time 0.99 seconds
Started Jul 19 05:06:44 PM PDT 24
Finished Jul 19 05:06:47 PM PDT 24
Peak memory 197264 kb
Host smart-c582c6a4-aee0-43f6-8172-ab74477a8e64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353590025 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.3353590025
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.1891293250
Short name T551
Test name
Test status
Simulation time 36316234 ps
CPU time 0.52 seconds
Started Jul 19 05:06:40 PM PDT 24
Finished Jul 19 05:06:41 PM PDT 24
Peak memory 182420 kb
Host smart-1511b1cd-a568-4416-aac5-7559a86220f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891293250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.1891293250
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.132935972
Short name T509
Test name
Test status
Simulation time 37256480 ps
CPU time 0.54 seconds
Started Jul 19 05:06:41 PM PDT 24
Finished Jul 19 05:06:43 PM PDT 24
Peak memory 181832 kb
Host smart-6bf98b24-c5e3-4c50-bae8-7cfb9d1e60e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132935972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.132935972
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.921788063
Short name T578
Test name
Test status
Simulation time 66910819 ps
CPU time 0.62 seconds
Started Jul 19 05:06:38 PM PDT 24
Finished Jul 19 05:06:40 PM PDT 24
Peak memory 191540 kb
Host smart-05515a7c-8b8d-4ce3-a044-afe580725cde
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921788063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_tim
er_same_csr_outstanding.921788063
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.2056032894
Short name T550
Test name
Test status
Simulation time 134560738 ps
CPU time 2.4 seconds
Started Jul 19 05:06:40 PM PDT 24
Finished Jul 19 05:06:43 PM PDT 24
Peak memory 197168 kb
Host smart-d45b583a-d72c-4adf-97d7-a65c6af7cb0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056032894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.2056032894
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.2231014767
Short name T29
Test name
Test status
Simulation time 128032153 ps
CPU time 1.37 seconds
Started Jul 19 05:06:43 PM PDT 24
Finished Jul 19 05:06:47 PM PDT 24
Peak memory 195092 kb
Host smart-9bdf01e9-c09d-4fd7-87c8-2f4d198999dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231014767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.2231014767
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3333056387
Short name T484
Test name
Test status
Simulation time 31507406 ps
CPU time 1.36 seconds
Started Jul 19 05:06:43 PM PDT 24
Finished Jul 19 05:06:47 PM PDT 24
Peak memory 197348 kb
Host smart-f031a101-6905-48c1-868c-20c0e68cb354
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333056387 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.3333056387
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.4199910716
Short name T505
Test name
Test status
Simulation time 17307460 ps
CPU time 0.58 seconds
Started Jul 19 05:06:39 PM PDT 24
Finished Jul 19 05:06:40 PM PDT 24
Peak memory 182520 kb
Host smart-46e86cc2-0a0f-427d-a8e5-cf4c878be92a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199910716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.4199910716
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.288284740
Short name T506
Test name
Test status
Simulation time 29183607 ps
CPU time 0.57 seconds
Started Jul 19 05:06:40 PM PDT 24
Finished Jul 19 05:06:43 PM PDT 24
Peak memory 182532 kb
Host smart-e28a80bb-83b7-4105-ae3e-ca00addca9ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288284740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.288284740
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1085696138
Short name T91
Test name
Test status
Simulation time 16511580 ps
CPU time 0.64 seconds
Started Jul 19 05:06:41 PM PDT 24
Finished Jul 19 05:06:43 PM PDT 24
Peak memory 192068 kb
Host smart-f9967697-53e4-40a6-80de-fa2a16a3fd3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085696138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.1085696138
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.2447000547
Short name T504
Test name
Test status
Simulation time 99392017 ps
CPU time 1.24 seconds
Started Jul 19 05:06:40 PM PDT 24
Finished Jul 19 05:06:43 PM PDT 24
Peak memory 197172 kb
Host smart-191592ff-9cf5-4f96-9ca6-bd4f4b5a9a6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447000547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.2447000547
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.4004616760
Short name T524
Test name
Test status
Simulation time 92938465 ps
CPU time 1.11 seconds
Started Jul 19 05:06:41 PM PDT 24
Finished Jul 19 05:06:44 PM PDT 24
Peak memory 195000 kb
Host smart-1ed774d0-87d5-4e73-99a5-81b8e66eb069
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004616760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.4004616760
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.3339573654
Short name T368
Test name
Test status
Simulation time 180394116256 ps
CPU time 140.24 seconds
Started Jul 19 05:10:02 PM PDT 24
Finished Jul 19 05:12:23 PM PDT 24
Peak memory 183564 kb
Host smart-298a1efe-32d4-4340-b705-7ff69549cf77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339573654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.3339573654
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.1561168613
Short name T249
Test name
Test status
Simulation time 232154537967 ps
CPU time 153.79 seconds
Started Jul 19 05:10:02 PM PDT 24
Finished Jul 19 05:12:37 PM PDT 24
Peak memory 191784 kb
Host smart-ec44ffe9-d301-4acd-8fa9-6857b88ff567
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561168613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.1561168613
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.2828789780
Short name T435
Test name
Test status
Simulation time 288469087980 ps
CPU time 110.91 seconds
Started Jul 19 05:10:03 PM PDT 24
Finished Jul 19 05:11:56 PM PDT 24
Peak memory 183568 kb
Host smart-762d1cb7-c84a-41d3-b125-052dda4c1302
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828789780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
2828789780
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.1127785947
Short name T412
Test name
Test status
Simulation time 19076479620 ps
CPU time 33.89 seconds
Started Jul 19 05:10:05 PM PDT 24
Finished Jul 19 05:10:41 PM PDT 24
Peak memory 183464 kb
Host smart-631f4262-f0bf-4db9-ba29-a9bb65eb5b20
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127785947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.1127785947
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.3459160910
Short name T385
Test name
Test status
Simulation time 53655485133 ps
CPU time 33.02 seconds
Started Jul 19 05:10:01 PM PDT 24
Finished Jul 19 05:10:35 PM PDT 24
Peak memory 183536 kb
Host smart-7d395cf2-b878-4d2c-a0e3-e7f56d89b8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459160910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.3459160910
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.1451118515
Short name T348
Test name
Test status
Simulation time 49770382612 ps
CPU time 18.57 seconds
Started Jul 19 05:10:00 PM PDT 24
Finished Jul 19 05:10:19 PM PDT 24
Peak memory 183428 kb
Host smart-1451d604-27a2-42df-a61f-6270a5a5a909
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451118515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.1451118515
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.2429504428
Short name T351
Test name
Test status
Simulation time 50800102716 ps
CPU time 179.63 seconds
Started Jul 19 05:10:01 PM PDT 24
Finished Jul 19 05:13:02 PM PDT 24
Peak memory 191732 kb
Host smart-12ff0ef5-d8bc-4d46-b6ed-4490b8e94b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429504428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.2429504428
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.2368658397
Short name T15
Test name
Test status
Simulation time 60891474 ps
CPU time 0.74 seconds
Started Jul 19 05:10:07 PM PDT 24
Finished Jul 19 05:10:10 PM PDT 24
Peak memory 213808 kb
Host smart-81cc8eb7-be34-43b8-999c-2a5094519b77
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368658397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.2368658397
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.3394968002
Short name T324
Test name
Test status
Simulation time 365038206449 ps
CPU time 630.37 seconds
Started Jul 19 05:10:15 PM PDT 24
Finished Jul 19 05:20:46 PM PDT 24
Peak memory 183524 kb
Host smart-32480f27-37f9-46de-90cd-942a4084a92d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394968002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.3394968002
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.2221958491
Short name T386
Test name
Test status
Simulation time 96531474341 ps
CPU time 70.16 seconds
Started Jul 19 05:10:16 PM PDT 24
Finished Jul 19 05:11:27 PM PDT 24
Peak memory 183584 kb
Host smart-5d8ca632-b487-4a7e-9ceb-deca925be1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221958491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.2221958491
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.415713336
Short name T349
Test name
Test status
Simulation time 111006154372 ps
CPU time 251.84 seconds
Started Jul 19 05:10:19 PM PDT 24
Finished Jul 19 05:14:32 PM PDT 24
Peak memory 191712 kb
Host smart-be26a155-eebf-4a1e-9652-1ebc4a27f99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415713336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.415713336
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.1725145928
Short name T374
Test name
Test status
Simulation time 46298989245 ps
CPU time 63.55 seconds
Started Jul 19 05:10:15 PM PDT 24
Finished Jul 19 05:11:20 PM PDT 24
Peak memory 183576 kb
Host smart-0c95c1d5-57f4-4aa2-a2bf-44e21efeb0fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725145928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.1725145928
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.3924962072
Short name T35
Test name
Test status
Simulation time 71139562304 ps
CPU time 768 seconds
Started Jul 19 05:10:16 PM PDT 24
Finished Jul 19 05:23:06 PM PDT 24
Peak memory 210300 kb
Host smart-1097680d-0c7d-44bb-962e-872228fe5884
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924962072 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_reset.3924962072
Directory /workspace/10.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/102.rv_timer_random.2188339210
Short name T228
Test name
Test status
Simulation time 18793852385 ps
CPU time 6.98 seconds
Started Jul 19 05:12:12 PM PDT 24
Finished Jul 19 05:12:20 PM PDT 24
Peak memory 183380 kb
Host smart-d0913195-82a3-491f-933c-db25f230fc4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188339210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.2188339210
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.3458916231
Short name T183
Test name
Test status
Simulation time 204383386477 ps
CPU time 355.24 seconds
Started Jul 19 05:12:10 PM PDT 24
Finished Jul 19 05:18:06 PM PDT 24
Peak memory 191932 kb
Host smart-e41cf0f9-b8c3-4a25-8007-7575b6db3540
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458916231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.3458916231
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.1814560265
Short name T123
Test name
Test status
Simulation time 88469604570 ps
CPU time 226.92 seconds
Started Jul 19 05:12:07 PM PDT 24
Finished Jul 19 05:15:54 PM PDT 24
Peak memory 194928 kb
Host smart-4b957ef9-5415-4eef-84e9-e743d359b477
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814560265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.1814560265
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.4219272108
Short name T380
Test name
Test status
Simulation time 411584240828 ps
CPU time 323.5 seconds
Started Jul 19 05:10:18 PM PDT 24
Finished Jul 19 05:15:42 PM PDT 24
Peak memory 183544 kb
Host smart-e1082efb-ab8b-4dd6-9ca4-5d4def9f1dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219272108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.4219272108
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.4211191255
Short name T161
Test name
Test status
Simulation time 135104111314 ps
CPU time 112.27 seconds
Started Jul 19 05:10:16 PM PDT 24
Finished Jul 19 05:12:09 PM PDT 24
Peak memory 195508 kb
Host smart-df215c6d-48c4-48e6-978a-f69b4e9caee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211191255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.4211191255
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/112.rv_timer_random.3650913285
Short name T357
Test name
Test status
Simulation time 20105297270 ps
CPU time 388.39 seconds
Started Jul 19 05:12:14 PM PDT 24
Finished Jul 19 05:18:43 PM PDT 24
Peak memory 183572 kb
Host smart-26bac04b-778e-44e1-8e7d-59cb9e13da7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650913285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.3650913285
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.1159701869
Short name T258
Test name
Test status
Simulation time 235692465903 ps
CPU time 238.15 seconds
Started Jul 19 05:12:16 PM PDT 24
Finished Jul 19 05:16:15 PM PDT 24
Peak memory 191756 kb
Host smart-62e8b5ea-7307-4ba3-9873-5f9d0b5b8eeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159701869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.1159701869
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.258565576
Short name T176
Test name
Test status
Simulation time 113359141725 ps
CPU time 362.04 seconds
Started Jul 19 05:12:15 PM PDT 24
Finished Jul 19 05:18:19 PM PDT 24
Peak memory 191764 kb
Host smart-ef48780d-6805-4008-beb5-476a7786f01e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258565576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.258565576
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.162443784
Short name T166
Test name
Test status
Simulation time 117583978334 ps
CPU time 616.62 seconds
Started Jul 19 05:12:16 PM PDT 24
Finished Jul 19 05:22:34 PM PDT 24
Peak memory 191772 kb
Host smart-cea99e0c-275e-4664-b605-96b596076651
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162443784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.162443784
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.3485088808
Short name T323
Test name
Test status
Simulation time 125445741380 ps
CPU time 507.38 seconds
Started Jul 19 05:12:17 PM PDT 24
Finished Jul 19 05:20:45 PM PDT 24
Peak memory 191772 kb
Host smart-4c4d4b01-140b-4109-b071-af82fd9899fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485088808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.3485088808
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.1495001469
Short name T233
Test name
Test status
Simulation time 730445910887 ps
CPU time 1815.31 seconds
Started Jul 19 05:12:15 PM PDT 24
Finished Jul 19 05:42:31 PM PDT 24
Peak memory 191796 kb
Host smart-fd3789c8-cc50-400f-98a5-91a90016bb67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495001469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.1495001469
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.3089859657
Short name T132
Test name
Test status
Simulation time 136817387879 ps
CPU time 194.92 seconds
Started Jul 19 05:10:18 PM PDT 24
Finished Jul 19 05:13:34 PM PDT 24
Peak memory 183568 kb
Host smart-bb43209a-586e-48e2-b130-d628f4d325a7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089859657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.3089859657
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.2794118614
Short name T406
Test name
Test status
Simulation time 155455667143 ps
CPU time 86.75 seconds
Started Jul 19 05:10:19 PM PDT 24
Finished Jul 19 05:11:47 PM PDT 24
Peak memory 183428 kb
Host smart-b36d29a2-70bb-4bcc-98d7-eb2273af4791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794118614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.2794118614
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/120.rv_timer_random.3452949982
Short name T353
Test name
Test status
Simulation time 124331656910 ps
CPU time 838.96 seconds
Started Jul 19 05:12:23 PM PDT 24
Finished Jul 19 05:26:23 PM PDT 24
Peak memory 191768 kb
Host smart-5e97ca4c-1939-414b-91d5-dda33d8f6c3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452949982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.3452949982
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.3334336940
Short name T321
Test name
Test status
Simulation time 61454879842 ps
CPU time 303.67 seconds
Started Jul 19 05:12:23 PM PDT 24
Finished Jul 19 05:17:28 PM PDT 24
Peak memory 191768 kb
Host smart-da37f0fe-4e6c-4d0b-b5f5-f1fc23ae492a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334336940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.3334336940
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.3783851827
Short name T108
Test name
Test status
Simulation time 96009526427 ps
CPU time 1462.08 seconds
Started Jul 19 05:12:24 PM PDT 24
Finished Jul 19 05:36:48 PM PDT 24
Peak memory 192572 kb
Host smart-dd2baf8f-3370-4552-91eb-e7bf34af18e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783851827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.3783851827
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.433561598
Short name T337
Test name
Test status
Simulation time 126266569105 ps
CPU time 1043.77 seconds
Started Jul 19 05:12:25 PM PDT 24
Finished Jul 19 05:29:50 PM PDT 24
Peak memory 191772 kb
Host smart-b7bd49f8-0872-4584-a9c5-5b5e5538d384
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433561598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.433561598
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.2853217644
Short name T135
Test name
Test status
Simulation time 166896675268 ps
CPU time 495.46 seconds
Started Jul 19 05:12:22 PM PDT 24
Finished Jul 19 05:20:39 PM PDT 24
Peak memory 191772 kb
Host smart-a2052a40-4dd9-4524-9347-39ab0319783f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853217644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.2853217644
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.470984290
Short name T277
Test name
Test status
Simulation time 734375101120 ps
CPU time 838.48 seconds
Started Jul 19 05:12:22 PM PDT 24
Finished Jul 19 05:26:22 PM PDT 24
Peak memory 191748 kb
Host smart-cee66520-d657-4441-a611-3a8cd9f0cdbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470984290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.470984290
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.1360743990
Short name T10
Test name
Test status
Simulation time 119740024310 ps
CPU time 68.88 seconds
Started Jul 19 05:12:22 PM PDT 24
Finished Jul 19 05:13:32 PM PDT 24
Peak memory 183468 kb
Host smart-eaf7ab21-4f57-4cb3-8cc5-5330afc6d3ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360743990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.1360743990
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.2173745168
Short name T289
Test name
Test status
Simulation time 93331406303 ps
CPU time 155.44 seconds
Started Jul 19 05:12:24 PM PDT 24
Finished Jul 19 05:15:01 PM PDT 24
Peak memory 191804 kb
Host smart-0cac868b-ea37-4f44-9734-e0f66732491f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173745168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.2173745168
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.1144078609
Short name T100
Test name
Test status
Simulation time 247726138711 ps
CPU time 124.12 seconds
Started Jul 19 05:12:23 PM PDT 24
Finished Jul 19 05:14:29 PM PDT 24
Peak memory 191772 kb
Host smart-444e5814-c500-4a37-be3e-3d6c7eceaf79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144078609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.1144078609
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.21237100
Short name T301
Test name
Test status
Simulation time 142156447201 ps
CPU time 641.84 seconds
Started Jul 19 05:12:23 PM PDT 24
Finished Jul 19 05:23:06 PM PDT 24
Peak memory 191776 kb
Host smart-18dc33a2-eb45-4fad-a279-15edbce63f18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21237100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.21237100
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.3262094422
Short name T188
Test name
Test status
Simulation time 20631717399 ps
CPU time 10.07 seconds
Started Jul 19 05:10:24 PM PDT 24
Finished Jul 19 05:10:35 PM PDT 24
Peak memory 183576 kb
Host smart-51858926-fabd-4308-8d40-01ffe8eba016
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262094422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.3262094422
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.793214918
Short name T422
Test name
Test status
Simulation time 505536173637 ps
CPU time 84.34 seconds
Started Jul 19 05:10:26 PM PDT 24
Finished Jul 19 05:11:52 PM PDT 24
Peak memory 183592 kb
Host smart-f2e45e2c-97e2-482d-be7a-6a00aefaa4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793214918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.793214918
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.2774199856
Short name T41
Test name
Test status
Simulation time 85491565074 ps
CPU time 225.43 seconds
Started Jul 19 05:10:23 PM PDT 24
Finished Jul 19 05:14:09 PM PDT 24
Peak memory 191748 kb
Host smart-6987ebd6-0307-444f-9226-4f9865aaee6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774199856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.2774199856
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.3817769061
Short name T442
Test name
Test status
Simulation time 24855092308 ps
CPU time 60.68 seconds
Started Jul 19 05:10:27 PM PDT 24
Finished Jul 19 05:11:28 PM PDT 24
Peak memory 191792 kb
Host smart-46ce2939-8f15-4cea-8fc1-8108b3da8589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817769061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.3817769061
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.1011715504
Short name T332
Test name
Test status
Simulation time 102716314836 ps
CPU time 47.54 seconds
Started Jul 19 05:12:23 PM PDT 24
Finished Jul 19 05:13:12 PM PDT 24
Peak memory 183580 kb
Host smart-943a6840-b595-40d5-8757-689777b18e5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011715504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.1011715504
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.4274245088
Short name T267
Test name
Test status
Simulation time 308546875694 ps
CPU time 246.31 seconds
Started Jul 19 05:12:25 PM PDT 24
Finished Jul 19 05:16:32 PM PDT 24
Peak memory 191772 kb
Host smart-932c3f1a-9f54-40a1-96e9-980363000e3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274245088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.4274245088
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.1604153164
Short name T229
Test name
Test status
Simulation time 55379962588 ps
CPU time 93.21 seconds
Started Jul 19 05:12:24 PM PDT 24
Finished Jul 19 05:13:59 PM PDT 24
Peak memory 191764 kb
Host smart-94ae9e03-06b8-4a00-bec0-f68687b8e4a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604153164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.1604153164
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.3744506346
Short name T158
Test name
Test status
Simulation time 46173684407 ps
CPU time 102.82 seconds
Started Jul 19 05:12:25 PM PDT 24
Finished Jul 19 05:14:09 PM PDT 24
Peak memory 191764 kb
Host smart-bf9376e6-1120-40f3-bd41-b2c05d35652b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744506346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.3744506346
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.1716468437
Short name T225
Test name
Test status
Simulation time 119049308588 ps
CPU time 469.82 seconds
Started Jul 19 05:12:24 PM PDT 24
Finished Jul 19 05:20:16 PM PDT 24
Peak memory 191772 kb
Host smart-5968b675-2369-4ccf-9a7b-78a8cb7c70c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716468437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.1716468437
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.966638437
Short name T212
Test name
Test status
Simulation time 288026692318 ps
CPU time 234.09 seconds
Started Jul 19 05:12:32 PM PDT 24
Finished Jul 19 05:16:28 PM PDT 24
Peak memory 191724 kb
Host smart-7589b7a9-8d88-43fb-b7b0-b0db4a700f9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966638437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.966638437
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.205007347
Short name T450
Test name
Test status
Simulation time 184411586837 ps
CPU time 149.86 seconds
Started Jul 19 05:12:33 PM PDT 24
Finished Jul 19 05:15:04 PM PDT 24
Peak memory 191748 kb
Host smart-15634c36-ec0b-4775-a44a-314db13081c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205007347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.205007347
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.2338477968
Short name T255
Test name
Test status
Simulation time 169262833484 ps
CPU time 71.08 seconds
Started Jul 19 05:12:33 PM PDT 24
Finished Jul 19 05:13:46 PM PDT 24
Peak memory 191804 kb
Host smart-4df677ec-b165-441b-b070-d4945691fefd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338477968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.2338477968
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.448549717
Short name T242
Test name
Test status
Simulation time 1810280086225 ps
CPU time 593.56 seconds
Started Jul 19 05:10:23 PM PDT 24
Finished Jul 19 05:20:18 PM PDT 24
Peak memory 183556 kb
Host smart-bba621fd-5f2f-48fa-92c5-9963d492e60a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448549717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.rv_timer_cfg_update_on_fly.448549717
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.1166734909
Short name T26
Test name
Test status
Simulation time 182625536958 ps
CPU time 171.59 seconds
Started Jul 19 05:10:27 PM PDT 24
Finished Jul 19 05:13:19 PM PDT 24
Peak memory 183572 kb
Host smart-1e0596d4-1bda-48d2-accd-3864fe810ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166734909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.1166734909
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.3328740683
Short name T308
Test name
Test status
Simulation time 53578155460 ps
CPU time 86.15 seconds
Started Jul 19 05:10:26 PM PDT 24
Finished Jul 19 05:11:54 PM PDT 24
Peak memory 183580 kb
Host smart-34803722-e479-4365-9325-3a24df495f59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328740683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.3328740683
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.3118180859
Short name T313
Test name
Test status
Simulation time 13986165982 ps
CPU time 22.42 seconds
Started Jul 19 05:10:22 PM PDT 24
Finished Jul 19 05:10:45 PM PDT 24
Peak memory 191776 kb
Host smart-b59fd0d8-7d60-49ea-8263-3e8bebec3a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118180859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.3118180859
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/141.rv_timer_random.692213719
Short name T214
Test name
Test status
Simulation time 1757312766816 ps
CPU time 1175.52 seconds
Started Jul 19 05:12:30 PM PDT 24
Finished Jul 19 05:32:07 PM PDT 24
Peak memory 191660 kb
Host smart-ea2fbb7a-44bc-4255-99de-0ff0217d411c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692213719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.692213719
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.889340093
Short name T211
Test name
Test status
Simulation time 405054727348 ps
CPU time 268.91 seconds
Started Jul 19 05:12:32 PM PDT 24
Finished Jul 19 05:17:03 PM PDT 24
Peak memory 191780 kb
Host smart-402da978-960e-4669-a300-d94183161978
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889340093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.889340093
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.470818661
Short name T290
Test name
Test status
Simulation time 129774720534 ps
CPU time 64.79 seconds
Started Jul 19 05:12:34 PM PDT 24
Finished Jul 19 05:13:40 PM PDT 24
Peak memory 191784 kb
Host smart-042bf31f-61cd-4210-8276-febeb8e990e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470818661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.470818661
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.1190997505
Short name T210
Test name
Test status
Simulation time 27660464269 ps
CPU time 13.76 seconds
Started Jul 19 05:12:31 PM PDT 24
Finished Jul 19 05:12:47 PM PDT 24
Peak memory 191772 kb
Host smart-5d4bfa84-a2b6-4ab8-85a2-f8b652c46428
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190997505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.1190997505
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.2679735736
Short name T224
Test name
Test status
Simulation time 133642503026 ps
CPU time 487.6 seconds
Started Jul 19 05:12:31 PM PDT 24
Finished Jul 19 05:20:40 PM PDT 24
Peak memory 191784 kb
Host smart-e3893292-e49b-4a33-8686-444077e2ebd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679735736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.2679735736
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.2829417892
Short name T184
Test name
Test status
Simulation time 135710074834 ps
CPU time 1261.71 seconds
Started Jul 19 05:12:31 PM PDT 24
Finished Jul 19 05:33:34 PM PDT 24
Peak memory 194776 kb
Host smart-5fe37651-8cbf-437e-b8b8-31aeed9e4d86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829417892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.2829417892
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.940370653
Short name T327
Test name
Test status
Simulation time 275503167174 ps
CPU time 410.42 seconds
Started Jul 19 05:12:30 PM PDT 24
Finished Jul 19 05:19:21 PM PDT 24
Peak memory 191780 kb
Host smart-8d3371fe-20bb-4cc0-b79b-18252b1b46ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940370653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.940370653
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.1451510188
Short name T243
Test name
Test status
Simulation time 33754110015 ps
CPU time 23.75 seconds
Started Jul 19 05:12:31 PM PDT 24
Finished Jul 19 05:12:56 PM PDT 24
Peak memory 191796 kb
Host smart-e92fe2b2-b4be-4bdb-aa6f-85e63bac6af5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451510188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.1451510188
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.1180536794
Short name T6
Test name
Test status
Simulation time 18690696720 ps
CPU time 7.93 seconds
Started Jul 19 05:10:25 PM PDT 24
Finished Jul 19 05:10:34 PM PDT 24
Peak memory 183564 kb
Host smart-af9ecfe2-8451-4b20-ab2f-e924856f67da
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180536794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.1180536794
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.647037442
Short name T366
Test name
Test status
Simulation time 265792579086 ps
CPU time 218.85 seconds
Started Jul 19 05:10:23 PM PDT 24
Finished Jul 19 05:14:03 PM PDT 24
Peak memory 183568 kb
Host smart-e9f256e5-2b71-413b-9454-36fc2de351ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647037442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.647037442
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.2891659316
Short name T256
Test name
Test status
Simulation time 277220020992 ps
CPU time 1314.73 seconds
Started Jul 19 05:10:24 PM PDT 24
Finished Jul 19 05:32:20 PM PDT 24
Peak memory 191788 kb
Host smart-2b7e0b66-6bf8-48b2-af67-9e0cd66ded47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891659316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.2891659316
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.1605459129
Short name T401
Test name
Test status
Simulation time 82776872160 ps
CPU time 164.78 seconds
Started Jul 19 05:10:25 PM PDT 24
Finished Jul 19 05:13:11 PM PDT 24
Peak memory 195264 kb
Host smart-119cc385-b6ac-41c4-b50c-26a7e969b35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605459129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.1605459129
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.2319134882
Short name T191
Test name
Test status
Simulation time 5276242387339 ps
CPU time 1611.32 seconds
Started Jul 19 05:10:23 PM PDT 24
Finished Jul 19 05:37:16 PM PDT 24
Peak memory 196536 kb
Host smart-e28304ac-f2bb-40da-b81b-53411e0b7753
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319134882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.2319134882
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.1985067066
Short name T38
Test name
Test status
Simulation time 39545006236 ps
CPU time 412.74 seconds
Started Jul 19 05:10:22 PM PDT 24
Finished Jul 19 05:17:16 PM PDT 24
Peak memory 206480 kb
Host smart-e359e067-7117-4e9a-86cd-8bd96eba4d11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985067066 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all_with_rand_reset.1985067066
Directory /workspace/15.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.rv_timer_random.3383379747
Short name T431
Test name
Test status
Simulation time 67058031095 ps
CPU time 45.65 seconds
Started Jul 19 05:12:34 PM PDT 24
Finished Jul 19 05:13:21 PM PDT 24
Peak memory 183568 kb
Host smart-125d65af-f675-4dde-89a7-662df570cbe7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383379747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.3383379747
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.251135797
Short name T189
Test name
Test status
Simulation time 219203435617 ps
CPU time 171.79 seconds
Started Jul 19 05:12:39 PM PDT 24
Finished Jul 19 05:15:32 PM PDT 24
Peak memory 183576 kb
Host smart-e88429e2-3285-4e40-8f72-697392fd953e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251135797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.251135797
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.3047764619
Short name T250
Test name
Test status
Simulation time 87322318130 ps
CPU time 243.61 seconds
Started Jul 19 05:12:40 PM PDT 24
Finished Jul 19 05:16:45 PM PDT 24
Peak memory 191780 kb
Host smart-1b8fdd50-50ed-4366-a25a-d4e25471a626
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047764619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.3047764619
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.3378863475
Short name T292
Test name
Test status
Simulation time 462627559270 ps
CPU time 311.84 seconds
Started Jul 19 05:12:40 PM PDT 24
Finished Jul 19 05:17:53 PM PDT 24
Peak memory 191756 kb
Host smart-df2b105e-10cb-4b00-bd1f-9babe811500c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378863475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.3378863475
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.3265041223
Short name T215
Test name
Test status
Simulation time 122421508787 ps
CPU time 175.6 seconds
Started Jul 19 05:12:40 PM PDT 24
Finished Jul 19 05:15:37 PM PDT 24
Peak memory 191780 kb
Host smart-2047e302-f86a-4023-afcc-06975a41682c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265041223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.3265041223
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.3102123495
Short name T193
Test name
Test status
Simulation time 26604265610 ps
CPU time 20.74 seconds
Started Jul 19 05:10:25 PM PDT 24
Finished Jul 19 05:10:47 PM PDT 24
Peak memory 183568 kb
Host smart-3558394a-1df2-4e6b-9b7b-d7323544a043
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102123495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.3102123495
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.2986274345
Short name T364
Test name
Test status
Simulation time 182175212585 ps
CPU time 238.47 seconds
Started Jul 19 05:10:25 PM PDT 24
Finished Jul 19 05:14:24 PM PDT 24
Peak memory 183644 kb
Host smart-383a7488-1f01-42a6-b9bd-21bc69c04429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986274345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.2986274345
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.3673449881
Short name T413
Test name
Test status
Simulation time 317325285746 ps
CPU time 142.46 seconds
Started Jul 19 05:10:25 PM PDT 24
Finished Jul 19 05:12:49 PM PDT 24
Peak memory 191776 kb
Host smart-265d72fa-4e96-4f31-a068-c10ab44bb51c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673449881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.3673449881
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.4188694418
Short name T43
Test name
Test status
Simulation time 150942676169 ps
CPU time 57.27 seconds
Started Jul 19 05:10:32 PM PDT 24
Finished Jul 19 05:11:31 PM PDT 24
Peak memory 183380 kb
Host smart-c0155e6c-7570-4b80-92ab-5b7a05fc504c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188694418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.4188694418
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.2965482169
Short name T350
Test name
Test status
Simulation time 191632014618 ps
CPU time 391.58 seconds
Started Jul 19 05:12:45 PM PDT 24
Finished Jul 19 05:19:17 PM PDT 24
Peak memory 191776 kb
Host smart-e5aecb55-fd8b-4bef-8b78-1d0e90afc69a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965482169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.2965482169
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.1645145605
Short name T3
Test name
Test status
Simulation time 35223564649 ps
CPU time 41.17 seconds
Started Jul 19 05:12:49 PM PDT 24
Finished Jul 19 05:13:31 PM PDT 24
Peak memory 191780 kb
Host smart-9b3330c3-449d-4c50-a97c-b299a4128530
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645145605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.1645145605
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.750774300
Short name T444
Test name
Test status
Simulation time 168148360171 ps
CPU time 77.69 seconds
Started Jul 19 05:12:47 PM PDT 24
Finished Jul 19 05:14:06 PM PDT 24
Peak memory 191788 kb
Host smart-bd408c26-4c3e-4a68-915d-af81b5bdc6b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750774300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.750774300
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.2332979324
Short name T246
Test name
Test status
Simulation time 54951578162 ps
CPU time 535.67 seconds
Started Jul 19 05:12:47 PM PDT 24
Finished Jul 19 05:21:44 PM PDT 24
Peak memory 191748 kb
Host smart-0d506c09-1a33-45f4-a4f3-f54a3ed29e89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332979324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.2332979324
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.2595597659
Short name T294
Test name
Test status
Simulation time 60865131731 ps
CPU time 142.5 seconds
Started Jul 19 05:12:46 PM PDT 24
Finished Jul 19 05:15:09 PM PDT 24
Peak memory 194000 kb
Host smart-089802fc-26cc-4f50-9555-bda0a716885b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595597659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.2595597659
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.2457483981
Short name T291
Test name
Test status
Simulation time 74247419933 ps
CPU time 534.44 seconds
Started Jul 19 05:12:45 PM PDT 24
Finished Jul 19 05:21:41 PM PDT 24
Peak memory 191772 kb
Host smart-39bf5bd6-4f42-46df-ad1a-be374ea58935
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457483981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.2457483981
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.3238543371
Short name T200
Test name
Test status
Simulation time 38072574498 ps
CPU time 115.14 seconds
Started Jul 19 05:12:46 PM PDT 24
Finished Jul 19 05:14:43 PM PDT 24
Peak memory 191780 kb
Host smart-3bd5fcf8-d7ce-40f1-a148-72cb5c1e3b24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238543371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.3238543371
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.3059415382
Short name T62
Test name
Test status
Simulation time 3771382573 ps
CPU time 6.23 seconds
Started Jul 19 05:12:46 PM PDT 24
Finished Jul 19 05:12:54 PM PDT 24
Peak memory 183480 kb
Host smart-08aaf6ea-1966-4b30-9207-08b1697c2509
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059415382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.3059415382
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.2282628247
Short name T428
Test name
Test status
Simulation time 15332460038 ps
CPU time 25.73 seconds
Started Jul 19 05:10:35 PM PDT 24
Finished Jul 19 05:11:02 PM PDT 24
Peak memory 183576 kb
Host smart-ac8c8512-f075-49ff-a6e9-6661df96ed44
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282628247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.2282628247
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.1464501296
Short name T375
Test name
Test status
Simulation time 73921188723 ps
CPU time 115.71 seconds
Started Jul 19 05:10:32 PM PDT 24
Finished Jul 19 05:12:30 PM PDT 24
Peak memory 183480 kb
Host smart-b63ea1ec-e5b7-4f5d-9aca-02f950e6c0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464501296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.1464501296
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.3557824746
Short name T355
Test name
Test status
Simulation time 263849363017 ps
CPU time 178.92 seconds
Started Jul 19 05:10:32 PM PDT 24
Finished Jul 19 05:13:33 PM PDT 24
Peak memory 191744 kb
Host smart-42ffa165-3c52-4daf-b6be-efe38f6d5965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557824746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.3557824746
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.3844262116
Short name T199
Test name
Test status
Simulation time 816180769629 ps
CPU time 722.7 seconds
Started Jul 19 05:10:30 PM PDT 24
Finished Jul 19 05:22:34 PM PDT 24
Peak memory 191800 kb
Host smart-cc248886-d126-4d5d-8482-efc5df165e79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844262116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.3844262116
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/170.rv_timer_random.3299931000
Short name T265
Test name
Test status
Simulation time 113951945328 ps
CPU time 472.54 seconds
Started Jul 19 05:12:47 PM PDT 24
Finished Jul 19 05:20:41 PM PDT 24
Peak memory 191776 kb
Host smart-00228154-2208-4298-9d89-d5107f826570
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299931000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.3299931000
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.557735974
Short name T140
Test name
Test status
Simulation time 192764496648 ps
CPU time 69.55 seconds
Started Jul 19 05:12:45 PM PDT 24
Finished Jul 19 05:13:55 PM PDT 24
Peak memory 183540 kb
Host smart-3a34d5a4-d814-4c32-b466-03d0abbb3138
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557735974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.557735974
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.1989216872
Short name T93
Test name
Test status
Simulation time 165045247249 ps
CPU time 573.57 seconds
Started Jul 19 05:12:46 PM PDT 24
Finished Jul 19 05:22:21 PM PDT 24
Peak memory 191680 kb
Host smart-98737d32-0f2d-452a-9290-a6abc0c99561
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989216872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.1989216872
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.1414649357
Short name T232
Test name
Test status
Simulation time 302731834123 ps
CPU time 135.45 seconds
Started Jul 19 05:12:52 PM PDT 24
Finished Jul 19 05:15:09 PM PDT 24
Peak memory 191780 kb
Host smart-fc195d99-bb4a-44fc-a859-2265654e7236
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414649357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.1414649357
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.1324632761
Short name T179
Test name
Test status
Simulation time 60156580444 ps
CPU time 886.49 seconds
Started Jul 19 05:12:51 PM PDT 24
Finished Jul 19 05:27:39 PM PDT 24
Peak memory 191772 kb
Host smart-7b8d827b-9fe6-4b57-98eb-4f2b5946d845
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324632761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.1324632761
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.3865348560
Short name T186
Test name
Test status
Simulation time 922332130272 ps
CPU time 3358.8 seconds
Started Jul 19 05:12:52 PM PDT 24
Finished Jul 19 06:08:52 PM PDT 24
Peak memory 191792 kb
Host smart-91eff480-da13-471c-8dd5-4ab8821618fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865348560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.3865348560
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.1984179431
Short name T300
Test name
Test status
Simulation time 141620166292 ps
CPU time 403.71 seconds
Started Jul 19 05:12:54 PM PDT 24
Finished Jul 19 05:19:38 PM PDT 24
Peak memory 183572 kb
Host smart-980f10a0-5d8b-44c1-a79e-ce85c7f0fa81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984179431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.1984179431
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.2037215964
Short name T279
Test name
Test status
Simulation time 54380182709 ps
CPU time 636.03 seconds
Started Jul 19 05:12:55 PM PDT 24
Finished Jul 19 05:23:31 PM PDT 24
Peak memory 191748 kb
Host smart-41a96589-3e94-4649-9eab-c3aae14f623f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037215964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.2037215964
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.3669231971
Short name T244
Test name
Test status
Simulation time 79615227306 ps
CPU time 118.73 seconds
Started Jul 19 05:10:29 PM PDT 24
Finished Jul 19 05:12:29 PM PDT 24
Peak memory 183572 kb
Host smart-ab851b68-44bd-43c4-807b-9eaf7d7ef373
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669231971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.3669231971
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.1024535116
Short name T400
Test name
Test status
Simulation time 122820749758 ps
CPU time 170.56 seconds
Started Jul 19 05:10:32 PM PDT 24
Finished Jul 19 05:13:25 PM PDT 24
Peak memory 183588 kb
Host smart-7f593887-ad9f-460f-beb9-d424e4abf98c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024535116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.1024535116
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.2772626452
Short name T318
Test name
Test status
Simulation time 199785362196 ps
CPU time 1476.78 seconds
Started Jul 19 05:10:31 PM PDT 24
Finished Jul 19 05:35:09 PM PDT 24
Peak memory 195336 kb
Host smart-84bdc1d3-6c20-4343-ba41-30a658ee30d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772626452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.2772626452
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.3641033921
Short name T137
Test name
Test status
Simulation time 74814181360 ps
CPU time 64.52 seconds
Started Jul 19 05:10:31 PM PDT 24
Finished Jul 19 05:11:36 PM PDT 24
Peak memory 191768 kb
Host smart-595301cb-a21b-4cad-ae43-b4abb4577561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641033921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.3641033921
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/180.rv_timer_random.831462891
Short name T118
Test name
Test status
Simulation time 93364961529 ps
CPU time 504.49 seconds
Started Jul 19 05:12:52 PM PDT 24
Finished Jul 19 05:21:18 PM PDT 24
Peak memory 191752 kb
Host smart-6ab20696-947d-4e1a-9d68-133a1e56b9f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831462891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.831462891
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.220411837
Short name T131
Test name
Test status
Simulation time 193526751952 ps
CPU time 323.35 seconds
Started Jul 19 05:12:52 PM PDT 24
Finished Jul 19 05:18:17 PM PDT 24
Peak memory 191804 kb
Host smart-18439ec9-43f9-4aa3-8325-2f850c955014
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220411837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.220411837
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.3042895911
Short name T94
Test name
Test status
Simulation time 34760835487 ps
CPU time 50.73 seconds
Started Jul 19 05:12:55 PM PDT 24
Finished Jul 19 05:13:47 PM PDT 24
Peak memory 191756 kb
Host smart-4f047c97-2dd0-4d7d-bdfc-c7908190c7a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042895911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.3042895911
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.3107452454
Short name T409
Test name
Test status
Simulation time 716884192935 ps
CPU time 141.03 seconds
Started Jul 19 05:12:54 PM PDT 24
Finished Jul 19 05:15:15 PM PDT 24
Peak memory 191764 kb
Host smart-e4dd5d5e-2e94-4ab4-b369-08cc99ba9289
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107452454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.3107452454
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.1570026204
Short name T293
Test name
Test status
Simulation time 472144625324 ps
CPU time 577.85 seconds
Started Jul 19 05:12:52 PM PDT 24
Finished Jul 19 05:22:31 PM PDT 24
Peak memory 191772 kb
Host smart-78e59a76-457e-4093-946d-6e6ad99a3a86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570026204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.1570026204
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.1236551217
Short name T65
Test name
Test status
Simulation time 13832735407 ps
CPU time 161.53 seconds
Started Jul 19 05:12:53 PM PDT 24
Finished Jul 19 05:15:36 PM PDT 24
Peak memory 183564 kb
Host smart-852b1128-31b4-446c-91de-45b74c0bafa2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236551217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.1236551217
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.852888101
Short name T283
Test name
Test status
Simulation time 66278786166 ps
CPU time 104.77 seconds
Started Jul 19 05:13:01 PM PDT 24
Finished Jul 19 05:14:47 PM PDT 24
Peak memory 191792 kb
Host smart-c945aa16-4cc4-4196-b550-ca0d479601cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852888101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.852888101
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.2226921356
Short name T432
Test name
Test status
Simulation time 50759179393 ps
CPU time 246.51 seconds
Started Jul 19 05:13:02 PM PDT 24
Finished Jul 19 05:17:09 PM PDT 24
Peak memory 191748 kb
Host smart-67ff2ab7-758e-4e0e-aa85-70e1f94a6f12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226921356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.2226921356
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.890603636
Short name T314
Test name
Test status
Simulation time 106065725496 ps
CPU time 39.36 seconds
Started Jul 19 05:12:59 PM PDT 24
Finished Jul 19 05:13:39 PM PDT 24
Peak memory 183592 kb
Host smart-a928e436-9754-4e8d-9de8-201d8dcbd918
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890603636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.890603636
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.420771798
Short name T315
Test name
Test status
Simulation time 162801982810 ps
CPU time 992.74 seconds
Started Jul 19 05:13:01 PM PDT 24
Finished Jul 19 05:29:35 PM PDT 24
Peak memory 195004 kb
Host smart-44e5ac3e-ab8b-47d2-ab1f-7342af58997b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420771798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.420771798
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.4263483198
Short name T312
Test name
Test status
Simulation time 125026725901 ps
CPU time 31.39 seconds
Started Jul 19 05:10:32 PM PDT 24
Finished Jul 19 05:11:06 PM PDT 24
Peak memory 183564 kb
Host smart-8642f8bc-e9d8-4331-b4a5-3bcb77379a97
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263483198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.4263483198
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.1990951854
Short name T4
Test name
Test status
Simulation time 259202821410 ps
CPU time 95.55 seconds
Started Jul 19 05:10:31 PM PDT 24
Finished Jul 19 05:12:09 PM PDT 24
Peak memory 183592 kb
Host smart-6315f3b4-c597-4b8a-baca-19e88fa0d520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990951854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.1990951854
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.3579281246
Short name T227
Test name
Test status
Simulation time 46825637777 ps
CPU time 41.8 seconds
Started Jul 19 05:10:30 PM PDT 24
Finished Jul 19 05:11:13 PM PDT 24
Peak memory 191736 kb
Host smart-dd3c561a-2145-452b-8a11-f800e42b7f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579281246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.3579281246
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.1400747254
Short name T414
Test name
Test status
Simulation time 240713135414 ps
CPU time 184.22 seconds
Started Jul 19 05:10:35 PM PDT 24
Finished Jul 19 05:13:40 PM PDT 24
Peak memory 195204 kb
Host smart-bfad4e6d-fecc-452c-bebb-222750ef5616
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400747254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.1400747254
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/190.rv_timer_random.3944943969
Short name T282
Test name
Test status
Simulation time 107427214260 ps
CPU time 447.79 seconds
Started Jul 19 05:13:01 PM PDT 24
Finished Jul 19 05:20:30 PM PDT 24
Peak memory 191756 kb
Host smart-6b0b1992-c9e3-4fdd-bc42-32917b6e0b25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944943969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.3944943969
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.1511254649
Short name T316
Test name
Test status
Simulation time 148433687125 ps
CPU time 362.25 seconds
Started Jul 19 05:13:01 PM PDT 24
Finished Jul 19 05:19:04 PM PDT 24
Peak memory 191768 kb
Host smart-52d2494b-8142-4414-8382-16ca42b8d759
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511254649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.1511254649
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.133747737
Short name T149
Test name
Test status
Simulation time 621524384063 ps
CPU time 375.23 seconds
Started Jul 19 05:13:02 PM PDT 24
Finished Jul 19 05:19:18 PM PDT 24
Peak memory 191776 kb
Host smart-0ffc790e-3d13-4805-8241-a6942a90f017
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133747737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.133747737
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.3712750901
Short name T416
Test name
Test status
Simulation time 78563379255 ps
CPU time 121.32 seconds
Started Jul 19 05:13:02 PM PDT 24
Finished Jul 19 05:15:04 PM PDT 24
Peak memory 191772 kb
Host smart-284ac6f5-c872-45b1-8fff-a49bba201952
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712750901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.3712750901
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.3063208659
Short name T285
Test name
Test status
Simulation time 120769282903 ps
CPU time 66.4 seconds
Started Jul 19 05:13:00 PM PDT 24
Finished Jul 19 05:14:08 PM PDT 24
Peak memory 183564 kb
Host smart-e0a54579-3fb1-4b0a-97a3-39b8af72bd1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063208659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.3063208659
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.1319103568
Short name T120
Test name
Test status
Simulation time 219876006798 ps
CPU time 256.36 seconds
Started Jul 19 05:13:02 PM PDT 24
Finished Jul 19 05:17:20 PM PDT 24
Peak memory 191740 kb
Host smart-528f7b7c-1589-435f-acc1-fcc3a0d07b7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319103568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.1319103568
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.62906358
Short name T185
Test name
Test status
Simulation time 369283226583 ps
CPU time 1253.86 seconds
Started Jul 19 05:13:01 PM PDT 24
Finished Jul 19 05:33:56 PM PDT 24
Peak memory 191800 kb
Host smart-6a2c03d5-e97a-4857-ba0f-d40f87c44809
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62906358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.62906358
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.3928615445
Short name T329
Test name
Test status
Simulation time 221796511417 ps
CPU time 466.01 seconds
Started Jul 19 05:13:08 PM PDT 24
Finished Jul 19 05:20:55 PM PDT 24
Peak memory 191792 kb
Host smart-aba72401-1bbb-49f1-907f-6f39bc071f40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928615445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.3928615445
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.1393431852
Short name T142
Test name
Test status
Simulation time 67315471533 ps
CPU time 97.75 seconds
Started Jul 19 05:10:06 PM PDT 24
Finished Jul 19 05:11:46 PM PDT 24
Peak memory 183564 kb
Host smart-91701482-ce5e-4a4a-bff1-b8a5535f5981
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393431852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.1393431852
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.2627048942
Short name T373
Test name
Test status
Simulation time 451068827541 ps
CPU time 199.47 seconds
Started Jul 19 05:10:09 PM PDT 24
Finished Jul 19 05:13:31 PM PDT 24
Peak memory 183428 kb
Host smart-8bf808ad-cb10-4f9b-8f60-749d5c3344db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627048942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.2627048942
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.360772116
Short name T392
Test name
Test status
Simulation time 70615705306 ps
CPU time 51.22 seconds
Started Jul 19 05:10:14 PM PDT 24
Finished Jul 19 05:11:06 PM PDT 24
Peak memory 183536 kb
Host smart-d93277e7-ca3b-44f0-8b80-46193048315d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360772116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.360772116
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.1148917631
Short name T384
Test name
Test status
Simulation time 226488744 ps
CPU time 0.75 seconds
Started Jul 19 05:10:06 PM PDT 24
Finished Jul 19 05:10:09 PM PDT 24
Peak memory 191928 kb
Host smart-a0489f1a-101b-4ce0-9056-2fe502c8c277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148917631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.1148917631
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.3594853893
Short name T18
Test name
Test status
Simulation time 231774838 ps
CPU time 0.83 seconds
Started Jul 19 05:10:06 PM PDT 24
Finished Jul 19 05:10:10 PM PDT 24
Peak memory 213912 kb
Host smart-92095543-b740-400e-938d-847109789297
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594853893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.3594853893
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all_with_rand_reset.4071742644
Short name T33
Test name
Test status
Simulation time 21444527300 ps
CPU time 168.95 seconds
Started Jul 19 05:10:06 PM PDT 24
Finished Jul 19 05:12:57 PM PDT 24
Peak memory 198276 kb
Host smart-7f93d13a-d9b6-4c98-a7a2-42482a8fd39f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071742644 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all_with_rand_reset.4071742644
Directory /workspace/2.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.2100353315
Short name T346
Test name
Test status
Simulation time 75468750866 ps
CPU time 135.73 seconds
Started Jul 19 05:10:32 PM PDT 24
Finished Jul 19 05:12:49 PM PDT 24
Peak memory 183564 kb
Host smart-62ad73fc-cc95-44bd-9ded-8db6cb411e04
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100353315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.2100353315
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.534131233
Short name T391
Test name
Test status
Simulation time 76645489525 ps
CPU time 116.33 seconds
Started Jul 19 05:10:30 PM PDT 24
Finished Jul 19 05:12:27 PM PDT 24
Peak memory 183576 kb
Host smart-34bce423-9641-4bd6-b5f6-9112da3aaae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534131233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.534131233
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.184311654
Short name T152
Test name
Test status
Simulation time 46149006984 ps
CPU time 78.72 seconds
Started Jul 19 05:10:33 PM PDT 24
Finished Jul 19 05:11:54 PM PDT 24
Peak memory 195364 kb
Host smart-9fa3b002-b5f6-4f5e-9b0d-13c315ce9a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184311654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.184311654
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.3766314925
Short name T418
Test name
Test status
Simulation time 283192610110 ps
CPU time 216.38 seconds
Started Jul 19 05:10:32 PM PDT 24
Finished Jul 19 05:14:11 PM PDT 24
Peak memory 183528 kb
Host smart-bc6f3ed9-d15d-4b17-9d2c-d4f1f4f53320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766314925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.3766314925
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.2289989711
Short name T403
Test name
Test status
Simulation time 29077601649 ps
CPU time 38.92 seconds
Started Jul 19 05:10:31 PM PDT 24
Finished Jul 19 05:11:11 PM PDT 24
Peak memory 183580 kb
Host smart-37bd3021-828d-49eb-b652-bf2c59b3064d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289989711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.2289989711
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.932786334
Short name T411
Test name
Test status
Simulation time 2764889407579 ps
CPU time 841.98 seconds
Started Jul 19 05:10:39 PM PDT 24
Finished Jul 19 05:24:41 PM PDT 24
Peak memory 183584 kb
Host smart-7ff2e74e-7dce-4618-83d6-78e739bd6d6c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932786334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.rv_timer_cfg_update_on_fly.932786334
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.1344121466
Short name T426
Test name
Test status
Simulation time 90696802938 ps
CPU time 142.79 seconds
Started Jul 19 05:10:39 PM PDT 24
Finished Jul 19 05:13:03 PM PDT 24
Peak memory 183584 kb
Host smart-eb3ce0c5-f9b2-440e-9b66-eacfc68c93fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344121466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.1344121466
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.2445158161
Short name T2
Test name
Test status
Simulation time 544557992277 ps
CPU time 789.36 seconds
Started Jul 19 05:10:38 PM PDT 24
Finished Jul 19 05:23:48 PM PDT 24
Peak memory 191784 kb
Host smart-05f65e9e-486a-46c2-981d-287c3f40d6da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445158161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.2445158161
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all_with_rand_reset.1374596595
Short name T443
Test name
Test status
Simulation time 133470544498 ps
CPU time 1064.14 seconds
Started Jul 19 05:10:40 PM PDT 24
Finished Jul 19 05:28:25 PM PDT 24
Peak memory 213760 kb
Host smart-4527e835-4b9a-45dd-aaad-727baf582f49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374596595 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all_with_rand_reset.1374596595
Directory /workspace/22.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.1850547123
Short name T425
Test name
Test status
Simulation time 291971107369 ps
CPU time 99.71 seconds
Started Jul 19 05:10:40 PM PDT 24
Finished Jul 19 05:12:21 PM PDT 24
Peak memory 183588 kb
Host smart-07d59284-abfe-4777-8ca0-1099455873e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850547123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.1850547123
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.1316043159
Short name T167
Test name
Test status
Simulation time 109885606858 ps
CPU time 2829.43 seconds
Started Jul 19 05:10:41 PM PDT 24
Finished Jul 19 05:57:52 PM PDT 24
Peak memory 191792 kb
Host smart-213961f9-db19-47fc-9c50-214fcf7f8d54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316043159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.1316043159
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.702791340
Short name T311
Test name
Test status
Simulation time 43095210585 ps
CPU time 34.84 seconds
Started Jul 19 05:10:41 PM PDT 24
Finished Jul 19 05:11:17 PM PDT 24
Peak memory 195468 kb
Host smart-cbb701f4-dea9-44ad-b8cf-5feb17705236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702791340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.702791340
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.2850700414
Short name T112
Test name
Test status
Simulation time 35519188938 ps
CPU time 34.78 seconds
Started Jul 19 05:10:39 PM PDT 24
Finished Jul 19 05:11:15 PM PDT 24
Peak memory 183548 kb
Host smart-a2fe50e7-91b5-4c41-a3e1-5aa4d6d6d930
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850700414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.2850700414
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.997221057
Short name T377
Test name
Test status
Simulation time 581859148316 ps
CPU time 131.72 seconds
Started Jul 19 05:10:38 PM PDT 24
Finished Jul 19 05:12:50 PM PDT 24
Peak memory 183644 kb
Host smart-fc81014a-1547-4713-a9fd-c32f853adfe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997221057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.997221057
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all_with_rand_reset.4241219820
Short name T439
Test name
Test status
Simulation time 33529061122 ps
CPU time 180.59 seconds
Started Jul 19 05:10:39 PM PDT 24
Finished Jul 19 05:13:40 PM PDT 24
Peak memory 198304 kb
Host smart-a1ee7441-7e5c-4839-acd6-24cc0719de88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241219820 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all_with_rand_reset.4241219820
Directory /workspace/24.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.110268781
Short name T341
Test name
Test status
Simulation time 563565607244 ps
CPU time 773.35 seconds
Started Jul 19 05:10:47 PM PDT 24
Finished Jul 19 05:23:42 PM PDT 24
Peak memory 183564 kb
Host smart-e5757c5c-d0e7-495d-86e8-331ca3cf1401
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110268781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.rv_timer_cfg_update_on_fly.110268781
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.270442933
Short name T8
Test name
Test status
Simulation time 264214103446 ps
CPU time 112.54 seconds
Started Jul 19 05:10:48 PM PDT 24
Finished Jul 19 05:12:41 PM PDT 24
Peak memory 183616 kb
Host smart-c7409c3e-6088-4be5-92e7-b0a58fab7bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270442933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.270442933
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.2185142344
Short name T192
Test name
Test status
Simulation time 151355981860 ps
CPU time 639.65 seconds
Started Jul 19 05:10:46 PM PDT 24
Finished Jul 19 05:21:26 PM PDT 24
Peak memory 191772 kb
Host smart-0ef28301-ff34-48e8-8c21-6b13c9127112
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185142344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.2185142344
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.3453745839
Short name T424
Test name
Test status
Simulation time 256043816278 ps
CPU time 117.66 seconds
Started Jul 19 05:10:49 PM PDT 24
Finished Jul 19 05:12:47 PM PDT 24
Peak memory 191500 kb
Host smart-b44c3934-6d57-418c-8ea4-3c0fe8a7b175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453745839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.3453745839
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.1070257864
Short name T376
Test name
Test status
Simulation time 150739825089 ps
CPU time 178.43 seconds
Started Jul 19 05:10:48 PM PDT 24
Finished Jul 19 05:13:48 PM PDT 24
Peak memory 191772 kb
Host smart-e5fcd450-7b2a-49d1-b4f7-e8bef2cacf30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070257864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.1070257864
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.1018275468
Short name T299
Test name
Test status
Simulation time 235578581411 ps
CPU time 405.67 seconds
Started Jul 19 05:10:48 PM PDT 24
Finished Jul 19 05:17:34 PM PDT 24
Peak memory 183524 kb
Host smart-c6534b2e-f109-49a6-b2d5-7feb1a6dff3e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018275468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.1018275468
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.2580224096
Short name T402
Test name
Test status
Simulation time 504856388280 ps
CPU time 188.17 seconds
Started Jul 19 05:10:50 PM PDT 24
Finished Jul 19 05:13:59 PM PDT 24
Peak memory 183572 kb
Host smart-6639dc70-62ad-4ab8-915a-bfe95b691391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580224096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.2580224096
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.2434938869
Short name T110
Test name
Test status
Simulation time 83996428903 ps
CPU time 141.21 seconds
Started Jul 19 05:10:46 PM PDT 24
Finished Jul 19 05:13:08 PM PDT 24
Peak memory 191756 kb
Host smart-d0288271-6f5e-46bb-b74a-8de246217ea0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434938869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.2434938869
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.1536472157
Short name T333
Test name
Test status
Simulation time 29737574757 ps
CPU time 47.51 seconds
Started Jul 19 05:10:45 PM PDT 24
Finished Jul 19 05:11:33 PM PDT 24
Peak memory 191796 kb
Host smart-1fce1ded-bb79-43a1-bfb5-89f6892b5724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536472157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.1536472157
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.1800464005
Short name T438
Test name
Test status
Simulation time 275680029670 ps
CPU time 923.23 seconds
Started Jul 19 05:10:47 PM PDT 24
Finished Jul 19 05:26:11 PM PDT 24
Peak memory 191792 kb
Host smart-3354300f-d672-42a0-89a2-87e86588cf2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800464005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.1800464005
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.2232895044
Short name T430
Test name
Test status
Simulation time 146568482202 ps
CPU time 230.51 seconds
Started Jul 19 05:10:49 PM PDT 24
Finished Jul 19 05:14:40 PM PDT 24
Peak memory 183256 kb
Host smart-a6abe38a-be95-455c-9695-848322acba54
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232895044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.2232895044
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.128174566
Short name T96
Test name
Test status
Simulation time 170180747575 ps
CPU time 124.22 seconds
Started Jul 19 05:10:48 PM PDT 24
Finished Jul 19 05:12:53 PM PDT 24
Peak memory 183588 kb
Host smart-6b500d57-2db3-4949-a112-cb39c19f00b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128174566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.128174566
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.1889475930
Short name T440
Test name
Test status
Simulation time 156818279246 ps
CPU time 231.8 seconds
Started Jul 19 05:10:48 PM PDT 24
Finished Jul 19 05:14:41 PM PDT 24
Peak memory 195312 kb
Host smart-7c99ea52-d646-4673-a1e8-bfa44fd6650d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889475930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.1889475930
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.2640507893
Short name T21
Test name
Test status
Simulation time 103026305161 ps
CPU time 87.24 seconds
Started Jul 19 05:10:48 PM PDT 24
Finished Jul 19 05:12:16 PM PDT 24
Peak memory 191788 kb
Host smart-ba6b1c76-8c66-48e6-84bf-728bde45bdb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640507893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.2640507893
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all_with_rand_reset.2475730583
Short name T36
Test name
Test status
Simulation time 107321991581 ps
CPU time 833.31 seconds
Started Jul 19 05:10:46 PM PDT 24
Finished Jul 19 05:24:40 PM PDT 24
Peak memory 201228 kb
Host smart-83377052-2bb9-4ce9-961b-6975139b47e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475730583 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all_with_rand_reset.2475730583
Directory /workspace/27.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.1763315323
Short name T148
Test name
Test status
Simulation time 1817746439129 ps
CPU time 905.04 seconds
Started Jul 19 05:10:48 PM PDT 24
Finished Jul 19 05:25:54 PM PDT 24
Peak memory 183536 kb
Host smart-047cb2a0-5d2d-413a-8760-6647b46d5303
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763315323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.1763315323
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.2818617277
Short name T382
Test name
Test status
Simulation time 389448498078 ps
CPU time 170.01 seconds
Started Jul 19 05:10:49 PM PDT 24
Finished Jul 19 05:13:40 PM PDT 24
Peak memory 183572 kb
Host smart-96e1ca80-dae3-4004-829e-78977787889a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818617277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.2818617277
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.2383712153
Short name T194
Test name
Test status
Simulation time 441894612238 ps
CPU time 202.75 seconds
Started Jul 19 05:10:47 PM PDT 24
Finished Jul 19 05:14:10 PM PDT 24
Peak memory 191780 kb
Host smart-9b2690eb-431d-4783-bc06-78e1dc8ecf80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383712153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.2383712153
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.3721094175
Short name T22
Test name
Test status
Simulation time 191968821561 ps
CPU time 102.17 seconds
Started Jul 19 05:10:48 PM PDT 24
Finished Jul 19 05:12:31 PM PDT 24
Peak memory 183572 kb
Host smart-91201fe8-2d27-4e09-ba7f-b3c2579c16eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721094175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.3721094175
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.309601833
Short name T230
Test name
Test status
Simulation time 908345851391 ps
CPU time 1395.12 seconds
Started Jul 19 05:10:47 PM PDT 24
Finished Jul 19 05:34:04 PM PDT 24
Peak memory 191768 kb
Host smart-8212aa95-0184-42b7-9f98-99e5ef3cfed6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309601833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all.
309601833
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.3427906570
Short name T448
Test name
Test status
Simulation time 608648177922 ps
CPU time 523.07 seconds
Started Jul 19 05:10:49 PM PDT 24
Finished Jul 19 05:19:33 PM PDT 24
Peak memory 183544 kb
Host smart-c4d5a808-2714-49b6-aadc-cf810a84e52f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427906570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.3427906570
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.2756974152
Short name T396
Test name
Test status
Simulation time 546979445315 ps
CPU time 201.76 seconds
Started Jul 19 05:10:48 PM PDT 24
Finished Jul 19 05:14:10 PM PDT 24
Peak memory 183572 kb
Host smart-01b24813-1aad-4df1-b382-4480e7a47a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756974152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.2756974152
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.1418168883
Short name T434
Test name
Test status
Simulation time 77190230329 ps
CPU time 110.12 seconds
Started Jul 19 05:10:46 PM PDT 24
Finished Jul 19 05:12:37 PM PDT 24
Peak memory 195248 kb
Host smart-14c33ebb-4f7a-4b9d-a6f2-7b8ce62f18a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418168883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.1418168883
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.505904879
Short name T121
Test name
Test status
Simulation time 3290052685 ps
CPU time 2.27 seconds
Started Jul 19 05:10:47 PM PDT 24
Finished Jul 19 05:10:50 PM PDT 24
Peak memory 183592 kb
Host smart-ad1b3a85-230d-4aeb-b977-b56a479e3cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505904879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.505904879
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.2120355056
Short name T447
Test name
Test status
Simulation time 581366890790 ps
CPU time 2128.7 seconds
Started Jul 19 05:10:55 PM PDT 24
Finished Jul 19 05:46:25 PM PDT 24
Peak memory 191692 kb
Host smart-13111429-5073-44dc-a260-70ba93198aa0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120355056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.2120355056
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.4182466722
Short name T127
Test name
Test status
Simulation time 839816985787 ps
CPU time 404.66 seconds
Started Jul 19 05:10:06 PM PDT 24
Finished Jul 19 05:16:53 PM PDT 24
Peak memory 183564 kb
Host smart-efa492f9-8fdc-472a-8859-ed454fa29c92
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182466722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.4182466722
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.1879322998
Short name T379
Test name
Test status
Simulation time 443333779972 ps
CPU time 333.38 seconds
Started Jul 19 05:10:05 PM PDT 24
Finished Jul 19 05:15:41 PM PDT 24
Peak memory 183584 kb
Host smart-c445c9e2-3432-4106-8553-f36aad1dfe97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879322998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.1879322998
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.290878256
Short name T441
Test name
Test status
Simulation time 572808974292 ps
CPU time 252.57 seconds
Started Jul 19 05:10:10 PM PDT 24
Finished Jul 19 05:14:24 PM PDT 24
Peak memory 191768 kb
Host smart-8af08f74-e097-447d-a2f4-37ca435cdb70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290878256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.290878256
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.3733449080
Short name T362
Test name
Test status
Simulation time 607249414 ps
CPU time 1.41 seconds
Started Jul 19 05:10:07 PM PDT 24
Finished Jul 19 05:10:11 PM PDT 24
Peak memory 192008 kb
Host smart-e7def78b-6d9b-4435-9cf4-4b02fc51a953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733449080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.3733449080
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.4090703509
Short name T17
Test name
Test status
Simulation time 188668293 ps
CPU time 0.74 seconds
Started Jul 19 05:10:13 PM PDT 24
Finished Jul 19 05:10:14 PM PDT 24
Peak memory 213804 kb
Host smart-3d7ef7ed-c613-466a-9886-6769a164306e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090703509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.4090703509
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.1545303501
Short name T287
Test name
Test status
Simulation time 799307233008 ps
CPU time 709.79 seconds
Started Jul 19 05:10:54 PM PDT 24
Finished Jul 19 05:22:45 PM PDT 24
Peak memory 183456 kb
Host smart-c3e72c71-db8a-4e8b-913f-a86398ee2bbe
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545303501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.1545303501
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.2859170402
Short name T404
Test name
Test status
Simulation time 381513039534 ps
CPU time 165.02 seconds
Started Jul 19 05:10:55 PM PDT 24
Finished Jul 19 05:13:41 PM PDT 24
Peak memory 183584 kb
Host smart-ea9f8d7a-b2d2-4050-b770-47db964f4dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859170402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.2859170402
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.3703094139
Short name T419
Test name
Test status
Simulation time 33506457320 ps
CPU time 209.05 seconds
Started Jul 19 05:10:55 PM PDT 24
Finished Jul 19 05:14:25 PM PDT 24
Peak memory 183548 kb
Host smart-b5a66393-83f2-4947-b567-6b5d3822e0d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703094139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.3703094139
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.1640118460
Short name T259
Test name
Test status
Simulation time 36726456312 ps
CPU time 16.87 seconds
Started Jul 19 05:10:58 PM PDT 24
Finished Jul 19 05:11:16 PM PDT 24
Peak memory 183740 kb
Host smart-23410712-16d6-4724-b9d0-5449c2cba4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640118460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.1640118460
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.3464414114
Short name T383
Test name
Test status
Simulation time 22136980 ps
CPU time 0.59 seconds
Started Jul 19 05:10:59 PM PDT 24
Finished Jul 19 05:11:00 PM PDT 24
Peak memory 183476 kb
Host smart-def0bbba-33be-4721-b743-96d9f45aac5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464414114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.3464414114
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_random.3709109867
Short name T247
Test name
Test status
Simulation time 127356793224 ps
CPU time 127.34 seconds
Started Jul 19 05:10:58 PM PDT 24
Finished Jul 19 05:13:06 PM PDT 24
Peak memory 191724 kb
Host smart-accf6ee5-d415-4fd0-93d6-1706e86a299f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709109867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.3709109867
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.3153882834
Short name T427
Test name
Test status
Simulation time 295370100 ps
CPU time 0.9 seconds
Started Jul 19 05:10:57 PM PDT 24
Finished Jul 19 05:10:59 PM PDT 24
Peak memory 183328 kb
Host smart-4f7697d4-f9c7-40e4-8015-be91929eba6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153882834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.3153882834
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all_with_rand_reset.2383113844
Short name T37
Test name
Test status
Simulation time 356299340714 ps
CPU time 701.91 seconds
Started Jul 19 05:10:56 PM PDT 24
Finished Jul 19 05:22:38 PM PDT 24
Peak memory 207440 kb
Host smart-b6f465c0-7585-46b6-8b99-75edb0dfd7cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383113844 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all_with_rand_reset.2383113844
Directory /workspace/31.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.2687960710
Short name T147
Test name
Test status
Simulation time 44814505715 ps
CPU time 68.58 seconds
Started Jul 19 05:10:58 PM PDT 24
Finished Jul 19 05:12:07 PM PDT 24
Peak memory 183524 kb
Host smart-e57c99d3-9cfe-48a3-bd00-f252a19f6822
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687960710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.2687960710
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.435535222
Short name T405
Test name
Test status
Simulation time 38688119315 ps
CPU time 59.96 seconds
Started Jul 19 05:10:56 PM PDT 24
Finished Jul 19 05:11:57 PM PDT 24
Peak memory 183536 kb
Host smart-9aad11af-0045-47e3-97e0-1add0f6735c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435535222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.435535222
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.1063386285
Short name T352
Test name
Test status
Simulation time 340598098654 ps
CPU time 628.71 seconds
Started Jul 19 05:10:54 PM PDT 24
Finished Jul 19 05:21:24 PM PDT 24
Peak memory 191748 kb
Host smart-d761aeff-23f6-413c-a7af-0a2e91674aef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063386285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.1063386285
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.226934345
Short name T128
Test name
Test status
Simulation time 83139089844 ps
CPU time 116.96 seconds
Started Jul 19 05:10:55 PM PDT 24
Finished Jul 19 05:12:53 PM PDT 24
Peak memory 183596 kb
Host smart-5dc234d7-2ff0-4b86-a1db-6d6f0c1ce416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226934345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.226934345
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.923440596
Short name T286
Test name
Test status
Simulation time 34616268540 ps
CPU time 26.22 seconds
Started Jul 19 05:10:56 PM PDT 24
Finished Jul 19 05:11:23 PM PDT 24
Peak memory 183576 kb
Host smart-c30c66ec-70bb-47ac-b46e-1778554ba8c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923440596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all.
923440596
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.509403107
Short name T119
Test name
Test status
Simulation time 145970849771 ps
CPU time 263.99 seconds
Started Jul 19 05:10:59 PM PDT 24
Finished Jul 19 05:15:24 PM PDT 24
Peak memory 183528 kb
Host smart-04f25c12-822d-4f9d-8d47-42a33006f7cd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509403107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.rv_timer_cfg_update_on_fly.509403107
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.1371499633
Short name T25
Test name
Test status
Simulation time 411105369000 ps
CPU time 281.47 seconds
Started Jul 19 05:10:55 PM PDT 24
Finished Jul 19 05:15:38 PM PDT 24
Peak memory 183564 kb
Host smart-1c9cf5cf-fbcb-4163-801a-c6f7f52b582c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371499633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.1371499633
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.1991099256
Short name T343
Test name
Test status
Simulation time 447348698244 ps
CPU time 322.44 seconds
Started Jul 19 05:10:54 PM PDT 24
Finished Jul 19 05:16:17 PM PDT 24
Peak memory 191780 kb
Host smart-15016add-cc72-42f5-a22e-08e52625688c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991099256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.1991099256
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.2000108741
Short name T45
Test name
Test status
Simulation time 89371104968 ps
CPU time 131.97 seconds
Started Jul 19 05:10:59 PM PDT 24
Finished Jul 19 05:13:11 PM PDT 24
Peak memory 183708 kb
Host smart-96e2e204-8e1e-4dc6-9af2-191b7488eb18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000108741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.2000108741
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all_with_rand_reset.3350267653
Short name T39
Test name
Test status
Simulation time 153004028078 ps
CPU time 1220.66 seconds
Started Jul 19 05:11:08 PM PDT 24
Finished Jul 19 05:31:29 PM PDT 24
Peak memory 212088 kb
Host smart-e0ed56b3-09f6-486d-b0ef-52f0f15cfc76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350267653 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all_with_rand_reset.3350267653
Directory /workspace/33.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.3493220726
Short name T203
Test name
Test status
Simulation time 10256992252 ps
CPU time 16.85 seconds
Started Jul 19 05:11:04 PM PDT 24
Finished Jul 19 05:11:23 PM PDT 24
Peak memory 183564 kb
Host smart-c3a21260-b7e9-41ef-8227-cf022af57fb9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493220726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.3493220726
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_random.1620997885
Short name T220
Test name
Test status
Simulation time 47198163609 ps
CPU time 77.27 seconds
Started Jul 19 05:11:05 PM PDT 24
Finished Jul 19 05:12:24 PM PDT 24
Peak memory 183576 kb
Host smart-c5bc9b15-613c-4fa6-beed-f8ef4c7168b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620997885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.1620997885
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.3096574247
Short name T98
Test name
Test status
Simulation time 264526130431 ps
CPU time 440.38 seconds
Started Jul 19 05:11:08 PM PDT 24
Finished Jul 19 05:18:29 PM PDT 24
Peak memory 183568 kb
Host smart-50f01eee-e201-4cf2-81ab-f4c0ab96b49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096574247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.3096574247
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.1706008122
Short name T325
Test name
Test status
Simulation time 21371786407 ps
CPU time 35.42 seconds
Started Jul 19 05:11:05 PM PDT 24
Finished Jul 19 05:11:42 PM PDT 24
Peak memory 183468 kb
Host smart-30306681-f9ef-4c37-9dd2-27b20a03a32a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706008122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.1706008122
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all_with_rand_reset.1202366509
Short name T34
Test name
Test status
Simulation time 59996811763 ps
CPU time 455.34 seconds
Started Jul 19 05:11:03 PM PDT 24
Finished Jul 19 05:18:40 PM PDT 24
Peak memory 206520 kb
Host smart-927455de-f664-452a-8ee3-eb0fc2a14f98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202366509 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all_with_rand_reset.1202366509
Directory /workspace/34.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.105726709
Short name T107
Test name
Test status
Simulation time 4805557893664 ps
CPU time 1105.55 seconds
Started Jul 19 05:11:05 PM PDT 24
Finished Jul 19 05:29:32 PM PDT 24
Peak memory 183460 kb
Host smart-03ddf7a4-05f4-44ad-ab65-db8ca671db31
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105726709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.rv_timer_cfg_update_on_fly.105726709
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.3777867380
Short name T40
Test name
Test status
Simulation time 127618772730 ps
CPU time 182.66 seconds
Started Jul 19 05:11:03 PM PDT 24
Finished Jul 19 05:14:06 PM PDT 24
Peak memory 183572 kb
Host smart-0f1c3c87-4a53-453e-b010-2595b9d37f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777867380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.3777867380
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.4144395361
Short name T344
Test name
Test status
Simulation time 222199360039 ps
CPU time 855.09 seconds
Started Jul 19 05:11:03 PM PDT 24
Finished Jul 19 05:25:18 PM PDT 24
Peak memory 195428 kb
Host smart-30da0b11-8259-4361-8f00-c9feb47d58f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144395361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.4144395361
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.3542846637
Short name T361
Test name
Test status
Simulation time 1841711845 ps
CPU time 5.73 seconds
Started Jul 19 05:11:04 PM PDT 24
Finished Jul 19 05:11:11 PM PDT 24
Peak memory 183544 kb
Host smart-e0919a2c-9a5e-445c-a262-113221b77e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542846637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.3542846637
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.1072349574
Short name T197
Test name
Test status
Simulation time 45779923786 ps
CPU time 73.97 seconds
Started Jul 19 05:11:02 PM PDT 24
Finished Jul 19 05:12:17 PM PDT 24
Peak memory 183568 kb
Host smart-b0e5c6f4-a6c3-4ca1-b8e9-38ab2c91793e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072349574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.1072349574
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.127023698
Short name T363
Test name
Test status
Simulation time 255919978913 ps
CPU time 265.15 seconds
Started Jul 19 05:11:04 PM PDT 24
Finished Jul 19 05:15:30 PM PDT 24
Peak memory 183536 kb
Host smart-29e08ab0-7699-4262-a1bc-91c505062f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127023698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.127023698
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.932477114
Short name T145
Test name
Test status
Simulation time 92726202018 ps
CPU time 408.45 seconds
Started Jul 19 05:11:05 PM PDT 24
Finished Jul 19 05:17:55 PM PDT 24
Peak memory 195212 kb
Host smart-fbc33daa-40f2-4f68-99c9-8156cf6eaf8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932477114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.932477114
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.418322254
Short name T415
Test name
Test status
Simulation time 92581306 ps
CPU time 0.7 seconds
Started Jul 19 05:11:04 PM PDT 24
Finished Jul 19 05:11:07 PM PDT 24
Peak memory 183352 kb
Host smart-dbece87e-901c-4e98-8bd1-5da402b60bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418322254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.418322254
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.567279281
Short name T141
Test name
Test status
Simulation time 199677512127 ps
CPU time 190.75 seconds
Started Jul 19 05:11:05 PM PDT 24
Finished Jul 19 05:14:17 PM PDT 24
Peak memory 183588 kb
Host smart-0631ae83-69c7-48b6-a5db-879c05fccac3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567279281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.rv_timer_cfg_update_on_fly.567279281
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.1696525669
Short name T369
Test name
Test status
Simulation time 186951781309 ps
CPU time 63.14 seconds
Started Jul 19 05:11:05 PM PDT 24
Finished Jul 19 05:12:10 PM PDT 24
Peak memory 183576 kb
Host smart-34456b25-49c7-4baa-a1ff-3223b0d76ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696525669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.1696525669
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.3861540546
Short name T42
Test name
Test status
Simulation time 12286898128 ps
CPU time 17.89 seconds
Started Jul 19 05:11:07 PM PDT 24
Finished Jul 19 05:11:26 PM PDT 24
Peak memory 191768 kb
Host smart-c7a0972c-e4c7-4cfc-92b1-2834ef7e8315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861540546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.3861540546
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.2980244405
Short name T58
Test name
Test status
Simulation time 18733456 ps
CPU time 0.61 seconds
Started Jul 19 05:11:05 PM PDT 24
Finished Jul 19 05:11:07 PM PDT 24
Peak memory 182936 kb
Host smart-c9b92429-b1ef-450f-bd08-759acc25d85d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980244405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.2980244405
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.3262179134
Short name T342
Test name
Test status
Simulation time 814658341388 ps
CPU time 404.68 seconds
Started Jul 19 05:11:04 PM PDT 24
Finished Jul 19 05:17:50 PM PDT 24
Peak memory 183592 kb
Host smart-ccc2f17c-0b52-470f-9a5c-fe6481892bba
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262179134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.3262179134
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.4011596756
Short name T445
Test name
Test status
Simulation time 308417995783 ps
CPU time 90.4 seconds
Started Jul 19 05:11:05 PM PDT 24
Finished Jul 19 05:12:37 PM PDT 24
Peak memory 183564 kb
Host smart-29276045-5038-42a6-b63d-b5f9e4dbf2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011596756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.4011596756
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.3889565661
Short name T264
Test name
Test status
Simulation time 91326791578 ps
CPU time 71.15 seconds
Started Jul 19 05:11:05 PM PDT 24
Finished Jul 19 05:12:17 PM PDT 24
Peak memory 194024 kb
Host smart-c34b973c-71d7-44b5-9d57-a30540028539
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889565661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.3889565661
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.2975049562
Short name T136
Test name
Test status
Simulation time 228360357188 ps
CPU time 183.45 seconds
Started Jul 19 05:11:05 PM PDT 24
Finished Jul 19 05:14:10 PM PDT 24
Peak memory 193564 kb
Host smart-e6e9688a-4400-4092-a388-3a2599a009e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975049562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.2975049562
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.3384261384
Short name T19
Test name
Test status
Simulation time 1156061766601 ps
CPU time 817.96 seconds
Started Jul 19 05:11:13 PM PDT 24
Finished Jul 19 05:24:52 PM PDT 24
Peak memory 191732 kb
Host smart-c6eb2d04-76c1-4397-ab8d-cae7d2be5be1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384261384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.3384261384
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.2702842231
Short name T216
Test name
Test status
Simulation time 144225676584 ps
CPU time 145.88 seconds
Started Jul 19 05:11:12 PM PDT 24
Finished Jul 19 05:13:39 PM PDT 24
Peak memory 183564 kb
Host smart-168c5e6c-282c-4948-bad8-2e3073c6792a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702842231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.2702842231
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.1334813582
Short name T408
Test name
Test status
Simulation time 390187099777 ps
CPU time 151.67 seconds
Started Jul 19 05:11:10 PM PDT 24
Finished Jul 19 05:13:42 PM PDT 24
Peak memory 183584 kb
Host smart-b797a09a-8085-4e30-b756-8546988bf1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334813582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.1334813582
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.1362511406
Short name T155
Test name
Test status
Simulation time 101638440043 ps
CPU time 78.87 seconds
Started Jul 19 05:11:12 PM PDT 24
Finished Jul 19 05:12:32 PM PDT 24
Peak memory 191772 kb
Host smart-652779d0-760a-42c9-bce7-fd4e1abaecda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362511406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.1362511406
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.3901117715
Short name T20
Test name
Test status
Simulation time 46337524282 ps
CPU time 76.29 seconds
Started Jul 19 05:11:11 PM PDT 24
Finished Jul 19 05:12:28 PM PDT 24
Peak memory 191788 kb
Host smart-02a97d52-230a-416c-b0e9-e05eec4836ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901117715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.3901117715
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.1135201775
Short name T437
Test name
Test status
Simulation time 90138589944 ps
CPU time 120.48 seconds
Started Jul 19 05:11:11 PM PDT 24
Finished Jul 19 05:13:12 PM PDT 24
Peak memory 191764 kb
Host smart-7d71d843-5ebd-41cb-89dd-96f933f335fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135201775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.1135201775
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.2134957095
Short name T347
Test name
Test status
Simulation time 155169917351 ps
CPU time 268.06 seconds
Started Jul 19 05:10:06 PM PDT 24
Finished Jul 19 05:14:36 PM PDT 24
Peak memory 183544 kb
Host smart-53708bb2-dd5e-4ecb-bfd7-d6f1f1fb271f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134957095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.2134957095
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.2248700643
Short name T449
Test name
Test status
Simulation time 95238892555 ps
CPU time 144.69 seconds
Started Jul 19 05:10:08 PM PDT 24
Finished Jul 19 05:12:35 PM PDT 24
Peak memory 183220 kb
Host smart-1b70a96e-e075-4c9a-b026-96fd6e941b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248700643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.2248700643
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.3674915461
Short name T237
Test name
Test status
Simulation time 49624198616 ps
CPU time 93 seconds
Started Jul 19 05:10:09 PM PDT 24
Finished Jul 19 05:11:44 PM PDT 24
Peak memory 183588 kb
Host smart-8caee84d-cbc5-47ba-9244-868965cc5834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674915461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.3674915461
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.4098622611
Short name T14
Test name
Test status
Simulation time 189056216 ps
CPU time 0.84 seconds
Started Jul 19 05:10:07 PM PDT 24
Finished Jul 19 05:10:11 PM PDT 24
Peak memory 213860 kb
Host smart-649c5703-09eb-47f8-b681-bfcc81431b87
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098622611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.4098622611
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.1455356945
Short name T69
Test name
Test status
Simulation time 636220748411 ps
CPU time 254.47 seconds
Started Jul 19 05:11:14 PM PDT 24
Finished Jul 19 05:15:30 PM PDT 24
Peak memory 183600 kb
Host smart-1d46c3c6-280d-43f5-a069-b0ca060c0aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455356945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.1455356945
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.3138943346
Short name T180
Test name
Test status
Simulation time 69582581084 ps
CPU time 200.39 seconds
Started Jul 19 05:11:14 PM PDT 24
Finished Jul 19 05:14:35 PM PDT 24
Peak memory 191788 kb
Host smart-011e9e53-a2a4-47ec-a82b-f3584523203e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138943346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.3138943346
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.1452782076
Short name T372
Test name
Test status
Simulation time 43708525 ps
CPU time 0.5 seconds
Started Jul 19 05:11:09 PM PDT 24
Finished Jul 19 05:11:10 PM PDT 24
Peak memory 183368 kb
Host smart-1844cc4c-a7c9-4fcf-ab88-965695b5f5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452782076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.1452782076
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.3939753466
Short name T134
Test name
Test status
Simulation time 63296461929 ps
CPU time 96.78 seconds
Started Jul 19 05:11:11 PM PDT 24
Finished Jul 19 05:12:49 PM PDT 24
Peak memory 183536 kb
Host smart-0273cedd-7261-4463-90ca-e5a9c122cb18
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939753466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.3939753466
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.1827303480
Short name T370
Test name
Test status
Simulation time 243645775088 ps
CPU time 181.45 seconds
Started Jul 19 05:11:14 PM PDT 24
Finished Jul 19 05:14:16 PM PDT 24
Peak memory 183604 kb
Host smart-29c6011e-b7f1-4238-a8b6-4e1694946fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827303480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.1827303480
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.3337961823
Short name T276
Test name
Test status
Simulation time 122366294924 ps
CPU time 384.9 seconds
Started Jul 19 05:11:11 PM PDT 24
Finished Jul 19 05:17:38 PM PDT 24
Peak memory 191788 kb
Host smart-891a6803-14b1-4236-9d78-3c1ff7eaeec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337961823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.3337961823
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.2985384770
Short name T388
Test name
Test status
Simulation time 120034801749 ps
CPU time 173.37 seconds
Started Jul 19 05:11:14 PM PDT 24
Finished Jul 19 05:14:08 PM PDT 24
Peak memory 195396 kb
Host smart-4c68f409-96e1-4f2c-bd0c-bede371fbdde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985384770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.2985384770
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.3883910098
Short name T397
Test name
Test status
Simulation time 30389103294 ps
CPU time 46.9 seconds
Started Jul 19 05:11:13 PM PDT 24
Finished Jul 19 05:12:01 PM PDT 24
Peak memory 183560 kb
Host smart-35584594-7373-4729-a760-59d55d8fad34
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883910098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.3883910098
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.1971307327
Short name T417
Test name
Test status
Simulation time 132513142382 ps
CPU time 189.92 seconds
Started Jul 19 05:11:11 PM PDT 24
Finished Jul 19 05:14:22 PM PDT 24
Peak memory 183564 kb
Host smart-adaa350d-4551-4f4b-bde6-eb982cc53653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971307327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.1971307327
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.1683132504
Short name T252
Test name
Test status
Simulation time 530470370415 ps
CPU time 363.67 seconds
Started Jul 19 05:11:13 PM PDT 24
Finished Jul 19 05:17:18 PM PDT 24
Peak memory 191724 kb
Host smart-e0c2c0b4-09cf-4f5d-8917-be2674baba4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683132504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.1683132504
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.2376937636
Short name T150
Test name
Test status
Simulation time 548034768985 ps
CPU time 516.29 seconds
Started Jul 19 05:11:15 PM PDT 24
Finished Jul 19 05:19:52 PM PDT 24
Peak memory 191752 kb
Host smart-3756514a-4356-4570-8543-2540ecb2ffc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376937636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.2376937636
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.2165417299
Short name T95
Test name
Test status
Simulation time 533603718940 ps
CPU time 483.44 seconds
Started Jul 19 05:11:11 PM PDT 24
Finished Jul 19 05:19:16 PM PDT 24
Peak memory 183568 kb
Host smart-71987755-8b07-40b5-ae19-6877e40e0778
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165417299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.2165417299
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.2172560326
Short name T395
Test name
Test status
Simulation time 90215980007 ps
CPU time 120.05 seconds
Started Jul 19 05:11:10 PM PDT 24
Finished Jul 19 05:13:10 PM PDT 24
Peak memory 183580 kb
Host smart-dd172734-49a7-460d-b655-8d552d2f3842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172560326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.2172560326
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.1606975865
Short name T296
Test name
Test status
Simulation time 304387216118 ps
CPU time 92.92 seconds
Started Jul 19 05:11:10 PM PDT 24
Finished Jul 19 05:12:44 PM PDT 24
Peak memory 191756 kb
Host smart-12f8f552-2ad9-4cea-ba2e-54c8114837bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606975865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.1606975865
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.2244859763
Short name T354
Test name
Test status
Simulation time 2417674822 ps
CPU time 4.16 seconds
Started Jul 19 05:11:18 PM PDT 24
Finished Jul 19 05:11:23 PM PDT 24
Peak memory 183560 kb
Host smart-fae0c511-7b13-4632-bd15-1744501e6c4e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244859763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.2244859763
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.3985282717
Short name T371
Test name
Test status
Simulation time 153446355859 ps
CPU time 121.9 seconds
Started Jul 19 05:11:20 PM PDT 24
Finished Jul 19 05:13:23 PM PDT 24
Peak memory 183584 kb
Host smart-3ba32cae-4bae-450c-a01f-98acad98f47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985282717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.3985282717
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.3680321774
Short name T234
Test name
Test status
Simulation time 42095181893 ps
CPU time 81.19 seconds
Started Jul 19 05:11:21 PM PDT 24
Finished Jul 19 05:12:43 PM PDT 24
Peak memory 195436 kb
Host smart-250530d4-4333-4e77-969e-ca43d5beabf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680321774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.3680321774
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.847658778
Short name T47
Test name
Test status
Simulation time 82819175692 ps
CPU time 632.44 seconds
Started Jul 19 05:11:23 PM PDT 24
Finished Jul 19 05:21:56 PM PDT 24
Peak memory 210924 kb
Host smart-31325a45-def8-48b1-b7d9-cb296aa7a1bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847658778 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.847658778
Directory /workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.3513319681
Short name T303
Test name
Test status
Simulation time 582417325503 ps
CPU time 639.79 seconds
Started Jul 19 05:11:19 PM PDT 24
Finished Jul 19 05:21:59 PM PDT 24
Peak memory 183568 kb
Host smart-d394a915-71e6-492b-a3cc-cf6099dcc16d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513319681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.3513319681
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.2050017576
Short name T407
Test name
Test status
Simulation time 121769789012 ps
CPU time 850.55 seconds
Started Jul 19 05:11:19 PM PDT 24
Finished Jul 19 05:25:30 PM PDT 24
Peak memory 191712 kb
Host smart-549fe876-fa4a-4ddd-b9f5-43f546fb29c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050017576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.2050017576
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.260318579
Short name T305
Test name
Test status
Simulation time 344294928871 ps
CPU time 613.96 seconds
Started Jul 19 05:11:19 PM PDT 24
Finished Jul 19 05:21:33 PM PDT 24
Peak memory 183560 kb
Host smart-78de0738-ec6c-4fa9-8631-afc1b4d484f7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260318579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.rv_timer_cfg_update_on_fly.260318579
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.3510101879
Short name T99
Test name
Test status
Simulation time 116753478678 ps
CPU time 29.77 seconds
Started Jul 19 05:11:20 PM PDT 24
Finished Jul 19 05:11:52 PM PDT 24
Peak memory 183596 kb
Host smart-68f001f9-36e2-49ba-9041-b3d6fa99c55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510101879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.3510101879
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.3844243293
Short name T378
Test name
Test status
Simulation time 83664013 ps
CPU time 0.63 seconds
Started Jul 19 05:11:20 PM PDT 24
Finished Jul 19 05:11:22 PM PDT 24
Peak memory 183340 kb
Host smart-f7ddcd92-f7d4-4aa6-9e7d-2b5ae0a982ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844243293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.3844243293
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.3401926248
Short name T173
Test name
Test status
Simulation time 925397495987 ps
CPU time 493.43 seconds
Started Jul 19 05:11:22 PM PDT 24
Finished Jul 19 05:19:36 PM PDT 24
Peak memory 183564 kb
Host smart-9779188b-1c39-4ec5-a6f2-0ed4be6d86e2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401926248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.3401926248
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.1576249924
Short name T387
Test name
Test status
Simulation time 475512110499 ps
CPU time 193.03 seconds
Started Jul 19 05:11:21 PM PDT 24
Finished Jul 19 05:14:35 PM PDT 24
Peak memory 183536 kb
Host smart-81137e35-4397-4990-b9bc-27719fe8752a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576249924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.1576249924
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.2983391845
Short name T106
Test name
Test status
Simulation time 90259162381 ps
CPU time 746.57 seconds
Started Jul 19 05:11:20 PM PDT 24
Finished Jul 19 05:23:48 PM PDT 24
Peak memory 191748 kb
Host smart-83c7dff0-7091-488f-b238-b02aa20b4544
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983391845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.2983391845
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.3869530466
Short name T429
Test name
Test status
Simulation time 84919489 ps
CPU time 0.61 seconds
Started Jul 19 05:11:19 PM PDT 24
Finished Jul 19 05:11:20 PM PDT 24
Peak memory 183340 kb
Host smart-e9f1b808-9b4a-42a2-ba38-8784dd3d0c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869530466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.3869530466
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all_with_rand_reset.4204581627
Short name T12
Test name
Test status
Simulation time 22332149871 ps
CPU time 176.44 seconds
Started Jul 19 05:11:21 PM PDT 24
Finished Jul 19 05:14:19 PM PDT 24
Peak memory 198300 kb
Host smart-ebf30154-c56e-4e86-8ee8-65d6fbab9b31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204581627 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all_with_rand_reset.4204581627
Directory /workspace/47.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.4025715189
Short name T206
Test name
Test status
Simulation time 37293880146 ps
CPU time 32.66 seconds
Started Jul 19 05:11:30 PM PDT 24
Finished Jul 19 05:12:04 PM PDT 24
Peak memory 183560 kb
Host smart-05f36f73-a931-411a-a42a-d8658cbc3654
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025715189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.4025715189
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.729931982
Short name T389
Test name
Test status
Simulation time 290288174123 ps
CPU time 122.1 seconds
Started Jul 19 05:11:31 PM PDT 24
Finished Jul 19 05:13:35 PM PDT 24
Peak memory 183568 kb
Host smart-d98b83bc-c615-4f75-86b1-bbc2e2f773cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729931982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.729931982
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.2811338827
Short name T1
Test name
Test status
Simulation time 176430691393 ps
CPU time 481.6 seconds
Started Jul 19 05:11:29 PM PDT 24
Finished Jul 19 05:19:32 PM PDT 24
Peak memory 194564 kb
Host smart-a2a34d2c-38b4-4221-b773-46c9f5f1516e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811338827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.2811338827
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.2295956618
Short name T245
Test name
Test status
Simulation time 143810425258 ps
CPU time 123.78 seconds
Started Jul 19 05:11:29 PM PDT 24
Finished Jul 19 05:13:34 PM PDT 24
Peak memory 183620 kb
Host smart-c810ad81-ce6f-4d2e-a1f3-9889171511e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295956618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.2295956618
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.758227460
Short name T169
Test name
Test status
Simulation time 960350373970 ps
CPU time 1030.31 seconds
Started Jul 19 05:11:29 PM PDT 24
Finished Jul 19 05:28:41 PM PDT 24
Peak memory 183540 kb
Host smart-42727cb4-97bf-44a6-a4e9-ebc894ae2942
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758227460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.rv_timer_cfg_update_on_fly.758227460
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.2703926871
Short name T390
Test name
Test status
Simulation time 119992234973 ps
CPU time 156.21 seconds
Started Jul 19 05:11:30 PM PDT 24
Finished Jul 19 05:14:07 PM PDT 24
Peak memory 183572 kb
Host smart-fbea9107-de47-42cf-8ea7-29cf67babe3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703926871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.2703926871
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.1027591220
Short name T338
Test name
Test status
Simulation time 22264215615 ps
CPU time 61.67 seconds
Started Jul 19 05:11:28 PM PDT 24
Finished Jul 19 05:12:32 PM PDT 24
Peak memory 193904 kb
Host smart-cb7b2964-fadf-4d87-98f9-81bc03175673
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027591220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.1027591220
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.3543719947
Short name T143
Test name
Test status
Simulation time 42078364698 ps
CPU time 75.23 seconds
Started Jul 19 05:11:30 PM PDT 24
Finished Jul 19 05:12:47 PM PDT 24
Peak memory 183568 kb
Host smart-21215745-7dcd-4f26-9867-7c4e8e15b999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543719947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.3543719947
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.1630595642
Short name T263
Test name
Test status
Simulation time 634313170067 ps
CPU time 599.73 seconds
Started Jul 19 05:10:14 PM PDT 24
Finished Jul 19 05:20:15 PM PDT 24
Peak memory 183540 kb
Host smart-c96649ce-7df3-4d3d-be38-d2d8532c2358
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630595642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.1630595642
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.3462047195
Short name T420
Test name
Test status
Simulation time 541608317649 ps
CPU time 168.68 seconds
Started Jul 19 05:10:08 PM PDT 24
Finished Jul 19 05:13:00 PM PDT 24
Peak memory 183576 kb
Host smart-f5a13fe1-4bab-4b66-b24b-bffd7db0bc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462047195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.3462047195
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.1074448528
Short name T278
Test name
Test status
Simulation time 36765136892 ps
CPU time 54.93 seconds
Started Jul 19 05:10:08 PM PDT 24
Finished Jul 19 05:11:05 PM PDT 24
Peak memory 183592 kb
Host smart-dbd1c06c-e359-4641-bb1b-2543ecd3ce4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074448528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.1074448528
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.2817589370
Short name T261
Test name
Test status
Simulation time 46497848326 ps
CPU time 68.73 seconds
Started Jul 19 05:10:09 PM PDT 24
Finished Jul 19 05:11:20 PM PDT 24
Peak memory 183576 kb
Host smart-3f514450-c889-4fa7-aa3b-d12747d65657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817589370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.2817589370
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.3021059010
Short name T114
Test name
Test status
Simulation time 53703561073 ps
CPU time 68.94 seconds
Started Jul 19 05:11:29 PM PDT 24
Finished Jul 19 05:12:39 PM PDT 24
Peak memory 183572 kb
Host smart-3e0611e0-44aa-41c5-98ca-cc8cefffb255
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021059010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.3021059010
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.2183106190
Short name T241
Test name
Test status
Simulation time 404930419928 ps
CPU time 346.92 seconds
Started Jul 19 05:11:30 PM PDT 24
Finished Jul 19 05:17:19 PM PDT 24
Peak memory 191748 kb
Host smart-2c103253-d957-4134-8011-e143ec5a613d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183106190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.2183106190
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.4003994863
Short name T253
Test name
Test status
Simulation time 96085639502 ps
CPU time 157.32 seconds
Started Jul 19 05:11:30 PM PDT 24
Finished Jul 19 05:14:09 PM PDT 24
Peak memory 195000 kb
Host smart-c48a224d-2306-49ec-9840-9539658252f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003994863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.4003994863
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.1448203667
Short name T116
Test name
Test status
Simulation time 58783979502 ps
CPU time 167.11 seconds
Started Jul 19 05:11:28 PM PDT 24
Finished Jul 19 05:14:17 PM PDT 24
Peak memory 191756 kb
Host smart-5e7fc089-97ba-457e-aab4-e1d650174fe0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448203667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.1448203667
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.3605271790
Short name T7
Test name
Test status
Simulation time 100301274225 ps
CPU time 148.83 seconds
Started Jul 19 05:11:37 PM PDT 24
Finished Jul 19 05:14:06 PM PDT 24
Peak memory 191776 kb
Host smart-89345c3a-0a0a-4abb-85bb-cfdbdf554e06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605271790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.3605271790
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.2379804826
Short name T218
Test name
Test status
Simulation time 67769227935 ps
CPU time 132.52 seconds
Started Jul 19 05:11:42 PM PDT 24
Finished Jul 19 05:13:55 PM PDT 24
Peak memory 191756 kb
Host smart-12ae3a68-504d-4a2a-807e-3656843a8f68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379804826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.2379804826
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.3011196765
Short name T421
Test name
Test status
Simulation time 173383696038 ps
CPU time 133.33 seconds
Started Jul 19 05:11:36 PM PDT 24
Finished Jul 19 05:13:50 PM PDT 24
Peak memory 191768 kb
Host smart-620c9c0e-6a5e-46a2-9e8d-ad89b8c6cf73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011196765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.3011196765
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.3040114668
Short name T126
Test name
Test status
Simulation time 317960207932 ps
CPU time 587.02 seconds
Started Jul 19 05:11:37 PM PDT 24
Finished Jul 19 05:21:24 PM PDT 24
Peak memory 191732 kb
Host smart-1adad1d3-274b-4048-aa75-1a2fbb34de1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040114668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.3040114668
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.1705886615
Short name T236
Test name
Test status
Simulation time 297963583814 ps
CPU time 264.48 seconds
Started Jul 19 05:10:08 PM PDT 24
Finished Jul 19 05:14:35 PM PDT 24
Peak memory 183300 kb
Host smart-f47e90e3-ceea-4379-9921-0d6f18d7d339
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705886615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.1705886615
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.2194754561
Short name T433
Test name
Test status
Simulation time 466691606038 ps
CPU time 199.53 seconds
Started Jul 19 05:10:09 PM PDT 24
Finished Jul 19 05:13:31 PM PDT 24
Peak memory 183560 kb
Host smart-fb138020-9e95-476e-8dea-a0fbcc9c29b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194754561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.2194754561
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.1951099160
Short name T393
Test name
Test status
Simulation time 127443766407 ps
CPU time 1144.46 seconds
Started Jul 19 05:10:07 PM PDT 24
Finished Jul 19 05:29:14 PM PDT 24
Peak memory 183584 kb
Host smart-434c0670-cb71-4ee6-960e-af46f58de0ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951099160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.1951099160
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.1886008548
Short name T410
Test name
Test status
Simulation time 73563139452 ps
CPU time 39.1 seconds
Started Jul 19 05:10:09 PM PDT 24
Finished Jul 19 05:10:50 PM PDT 24
Peak memory 191764 kb
Host smart-b0add8f7-94ea-4906-a99d-35cd8d0fa8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886008548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.1886008548
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/61.rv_timer_random.3393133366
Short name T381
Test name
Test status
Simulation time 62081144088 ps
CPU time 71.59 seconds
Started Jul 19 05:11:42 PM PDT 24
Finished Jul 19 05:12:55 PM PDT 24
Peak memory 183564 kb
Host smart-33700871-584b-4b8c-b5ea-29313d0196e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393133366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.3393133366
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.3502741524
Short name T436
Test name
Test status
Simulation time 334313049895 ps
CPU time 162.13 seconds
Started Jul 19 05:11:36 PM PDT 24
Finished Jul 19 05:14:19 PM PDT 24
Peak memory 183540 kb
Host smart-029ba25f-b088-4516-97f5-61dead37cdcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502741524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.3502741524
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.3089330964
Short name T248
Test name
Test status
Simulation time 679753166426 ps
CPU time 613.66 seconds
Started Jul 19 05:11:35 PM PDT 24
Finished Jul 19 05:21:49 PM PDT 24
Peak memory 191740 kb
Host smart-2f034781-d869-40d4-a9c8-39511756970c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089330964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.3089330964
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.1050441157
Short name T196
Test name
Test status
Simulation time 566222825733 ps
CPU time 576.51 seconds
Started Jul 19 05:12:02 PM PDT 24
Finished Jul 19 05:21:39 PM PDT 24
Peak memory 191764 kb
Host smart-23338a2f-1a50-40c7-a620-d20257a96048
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050441157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.1050441157
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.1832936805
Short name T163
Test name
Test status
Simulation time 122542096892 ps
CPU time 187.87 seconds
Started Jul 19 05:11:43 PM PDT 24
Finished Jul 19 05:14:52 PM PDT 24
Peak memory 195388 kb
Host smart-2ce50f8a-32d3-42e3-aa44-32189e539c4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832936805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.1832936805
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.3258063737
Short name T213
Test name
Test status
Simulation time 270478949891 ps
CPU time 163.31 seconds
Started Jul 19 05:11:43 PM PDT 24
Finished Jul 19 05:14:28 PM PDT 24
Peak memory 191716 kb
Host smart-8fcbda93-0503-4f60-83f6-81eb0d939a4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258063737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.3258063737
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.3886548845
Short name T272
Test name
Test status
Simulation time 635978598655 ps
CPU time 2621.73 seconds
Started Jul 19 05:11:44 PM PDT 24
Finished Jul 19 05:55:27 PM PDT 24
Peak memory 191780 kb
Host smart-2e307251-f661-4eee-a21d-9dc73c440e20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886548845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.3886548845
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.3654311122
Short name T322
Test name
Test status
Simulation time 7514212070 ps
CPU time 1.82 seconds
Started Jul 19 05:11:42 PM PDT 24
Finished Jul 19 05:11:45 PM PDT 24
Peak memory 183408 kb
Host smart-93933c8b-de88-49a5-ac5e-6cfa79791d07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654311122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.3654311122
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.4006273793
Short name T274
Test name
Test status
Simulation time 1254290622512 ps
CPU time 541.15 seconds
Started Jul 19 05:10:07 PM PDT 24
Finished Jul 19 05:19:11 PM PDT 24
Peak memory 183572 kb
Host smart-1c468aeb-c9aa-4019-ad88-29c3ff26abf5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006273793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.4006273793
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.3727893093
Short name T64
Test name
Test status
Simulation time 171183501281 ps
CPU time 220.19 seconds
Started Jul 19 05:10:07 PM PDT 24
Finished Jul 19 05:13:50 PM PDT 24
Peak memory 183536 kb
Host smart-2598438b-ef7d-4085-95f0-3caa7296c969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727893093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.3727893093
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.135406651
Short name T133
Test name
Test status
Simulation time 138606362888 ps
CPU time 245.56 seconds
Started Jul 19 05:10:09 PM PDT 24
Finished Jul 19 05:14:17 PM PDT 24
Peak memory 195492 kb
Host smart-5642c036-055f-4859-969c-f644870f8f60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135406651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.135406651
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.1970219003
Short name T144
Test name
Test status
Simulation time 185415636950 ps
CPU time 136.06 seconds
Started Jul 19 05:10:06 PM PDT 24
Finished Jul 19 05:12:25 PM PDT 24
Peak memory 191736 kb
Host smart-1df0f7e8-1f46-4673-957e-1b67d95794c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970219003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.1970219003
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.385013049
Short name T451
Test name
Test status
Simulation time 49338098 ps
CPU time 0.66 seconds
Started Jul 19 05:10:05 PM PDT 24
Finished Jul 19 05:10:08 PM PDT 24
Peak memory 183328 kb
Host smart-8d20dc99-1ac2-4f69-bcad-8a4fb705c8c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385013049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.385013049
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/70.rv_timer_random.750830284
Short name T336
Test name
Test status
Simulation time 49677591352 ps
CPU time 81.32 seconds
Started Jul 19 05:11:43 PM PDT 24
Finished Jul 19 05:13:06 PM PDT 24
Peak memory 191776 kb
Host smart-c89f432d-809f-4af6-b370-66b925473c18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750830284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.750830284
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.1374979323
Short name T306
Test name
Test status
Simulation time 158198917975 ps
CPU time 261.52 seconds
Started Jul 19 05:11:43 PM PDT 24
Finished Jul 19 05:16:05 PM PDT 24
Peak memory 191756 kb
Host smart-8efe0ca3-0e77-42b9-b36e-019ffa2bc805
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374979323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.1374979323
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.3233436772
Short name T254
Test name
Test status
Simulation time 122363484388 ps
CPU time 171.81 seconds
Started Jul 19 05:11:43 PM PDT 24
Finished Jul 19 05:14:36 PM PDT 24
Peak memory 191776 kb
Host smart-7d133cc5-a2ee-42e5-9df5-825c6fe4f919
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233436772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.3233436772
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.306507332
Short name T5
Test name
Test status
Simulation time 184157149261 ps
CPU time 81.45 seconds
Started Jul 19 05:11:44 PM PDT 24
Finished Jul 19 05:13:06 PM PDT 24
Peak memory 183644 kb
Host smart-2273f850-bc26-4711-9690-50efb053a9e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306507332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.306507332
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.1441441316
Short name T181
Test name
Test status
Simulation time 313406266091 ps
CPU time 501.58 seconds
Started Jul 19 05:11:52 PM PDT 24
Finished Jul 19 05:20:14 PM PDT 24
Peak memory 191780 kb
Host smart-1d16c8aa-55ea-48b0-94f4-e2f428dd7cd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441441316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.1441441316
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.2379347737
Short name T63
Test name
Test status
Simulation time 132956134433 ps
CPU time 1113.52 seconds
Started Jul 19 05:11:53 PM PDT 24
Finished Jul 19 05:30:27 PM PDT 24
Peak memory 191768 kb
Host smart-96eede4a-00dd-45d2-a326-30714a550373
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379347737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.2379347737
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.3054976638
Short name T269
Test name
Test status
Simulation time 390645522335 ps
CPU time 724.45 seconds
Started Jul 19 05:11:53 PM PDT 24
Finished Jul 19 05:23:58 PM PDT 24
Peak memory 191768 kb
Host smart-9341ef39-4e3d-4e72-a407-ddd8b1e230c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054976638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.3054976638
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.1135965128
Short name T204
Test name
Test status
Simulation time 87105791883 ps
CPU time 137.12 seconds
Started Jul 19 05:11:52 PM PDT 24
Finished Jul 19 05:14:10 PM PDT 24
Peak memory 191772 kb
Host smart-43a07e42-625c-4013-ae24-820ae2f19e0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135965128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.1135965128
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.351430260
Short name T330
Test name
Test status
Simulation time 414986634586 ps
CPU time 347.32 seconds
Started Jul 19 05:11:52 PM PDT 24
Finished Jul 19 05:17:40 PM PDT 24
Peak memory 195196 kb
Host smart-27f59659-1a12-43c9-b727-ca40605817a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351430260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.351430260
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.1988162084
Short name T446
Test name
Test status
Simulation time 153359592889 ps
CPU time 224.39 seconds
Started Jul 19 05:10:15 PM PDT 24
Finished Jul 19 05:14:01 PM PDT 24
Peak memory 183576 kb
Host smart-436f6bfa-98ca-4c78-a90d-0ffef63e8212
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988162084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.1988162084
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.689024053
Short name T399
Test name
Test status
Simulation time 131711123513 ps
CPU time 48.83 seconds
Started Jul 19 05:10:16 PM PDT 24
Finished Jul 19 05:11:07 PM PDT 24
Peak memory 183528 kb
Host smart-28014257-4960-401e-9b8a-ce881d88b8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689024053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.689024053
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.2960702691
Short name T151
Test name
Test status
Simulation time 178854016737 ps
CPU time 1618.78 seconds
Started Jul 19 05:10:15 PM PDT 24
Finished Jul 19 05:37:15 PM PDT 24
Peak memory 191792 kb
Host smart-e339fe62-ac82-4e3c-954a-b5e6fb49249a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960702691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.2960702691
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.2401799995
Short name T367
Test name
Test status
Simulation time 170875464 ps
CPU time 0.79 seconds
Started Jul 19 05:10:16 PM PDT 24
Finished Jul 19 05:10:18 PM PDT 24
Peak memory 183356 kb
Host smart-5f06ab25-096f-4cc6-be2b-ced4127c48f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401799995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.2401799995
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.540171584
Short name T138
Test name
Test status
Simulation time 42984290683 ps
CPU time 76.2 seconds
Started Jul 19 05:11:52 PM PDT 24
Finished Jul 19 05:13:09 PM PDT 24
Peak memory 191736 kb
Host smart-9834310c-d3b3-4964-ae52-7258d0873cfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540171584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.540171584
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.1166159168
Short name T281
Test name
Test status
Simulation time 281604551964 ps
CPU time 163.91 seconds
Started Jul 19 05:11:56 PM PDT 24
Finished Jul 19 05:14:41 PM PDT 24
Peak memory 191756 kb
Host smart-8bb175e0-36d8-4f50-85fa-abd801643fbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166159168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.1166159168
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.62306650
Short name T319
Test name
Test status
Simulation time 224495625942 ps
CPU time 914.05 seconds
Started Jul 19 05:12:04 PM PDT 24
Finished Jul 19 05:27:19 PM PDT 24
Peak memory 191756 kb
Host smart-19c5ad11-8058-4f82-88cf-38317a8f74e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62306650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.62306650
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.1985434180
Short name T328
Test name
Test status
Simulation time 252035543704 ps
CPU time 107.11 seconds
Started Jul 19 05:11:59 PM PDT 24
Finished Jul 19 05:13:47 PM PDT 24
Peak memory 191780 kb
Host smart-f5f5534e-09c5-4615-8785-363883bbdc34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985434180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.1985434180
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.2479079879
Short name T360
Test name
Test status
Simulation time 112563608342 ps
CPU time 168.71 seconds
Started Jul 19 05:11:59 PM PDT 24
Finished Jul 19 05:14:48 PM PDT 24
Peak memory 191748 kb
Host smart-43a575c0-235d-4506-aeeb-405fed6995a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479079879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.2479079879
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.3491628349
Short name T231
Test name
Test status
Simulation time 146612577894 ps
CPU time 364.41 seconds
Started Jul 19 05:11:59 PM PDT 24
Finished Jul 19 05:18:04 PM PDT 24
Peak memory 191780 kb
Host smart-8148e764-4bf7-460d-8ecd-5fdc360c09d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491628349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.3491628349
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.3783068086
Short name T310
Test name
Test status
Simulation time 125682356555 ps
CPU time 204.76 seconds
Started Jul 19 05:11:59 PM PDT 24
Finished Jul 19 05:15:25 PM PDT 24
Peak memory 191772 kb
Host smart-98d8cadd-292e-42fa-abcb-fa354f858230
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783068086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.3783068086
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.973909911
Short name T222
Test name
Test status
Simulation time 195969778223 ps
CPU time 770.81 seconds
Started Jul 19 05:12:04 PM PDT 24
Finished Jul 19 05:24:55 PM PDT 24
Peak memory 191756 kb
Host smart-aa29f81f-e64e-4168-8d4a-f904864864b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973909911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.973909911
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.152023509
Short name T219
Test name
Test status
Simulation time 8553492600 ps
CPU time 7.31 seconds
Started Jul 19 05:12:00 PM PDT 24
Finished Jul 19 05:12:08 PM PDT 24
Peak memory 183488 kb
Host smart-c49ac148-2656-45a2-b9eb-9937e9d43595
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152023509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.152023509
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.224855823
Short name T164
Test name
Test status
Simulation time 366482924441 ps
CPU time 174.04 seconds
Started Jul 19 05:10:17 PM PDT 24
Finished Jul 19 05:13:13 PM PDT 24
Peak memory 183564 kb
Host smart-a632257b-8cff-45d2-b403-81862944c38e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224855823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.rv_timer_cfg_update_on_fly.224855823
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.1702404389
Short name T398
Test name
Test status
Simulation time 355684959876 ps
CPU time 122.51 seconds
Started Jul 19 05:10:19 PM PDT 24
Finished Jul 19 05:12:22 PM PDT 24
Peak memory 183588 kb
Host smart-66546fce-4124-46d6-838d-30b7564b4d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702404389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.1702404389
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.2225470622
Short name T171
Test name
Test status
Simulation time 188236996987 ps
CPU time 199.49 seconds
Started Jul 19 05:10:17 PM PDT 24
Finished Jul 19 05:13:37 PM PDT 24
Peak memory 191784 kb
Host smart-b2f3067c-6228-4c69-9f87-008f231b4dc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225470622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.2225470622
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.3681128234
Short name T365
Test name
Test status
Simulation time 61211926 ps
CPU time 0.59 seconds
Started Jul 19 05:10:19 PM PDT 24
Finished Jul 19 05:10:21 PM PDT 24
Peak memory 183312 kb
Host smart-49d94b0d-39ee-4907-ba47-709b9e4d9c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681128234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.3681128234
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.581673773
Short name T156
Test name
Test status
Simulation time 1269889683406 ps
CPU time 1445.26 seconds
Started Jul 19 05:10:18 PM PDT 24
Finished Jul 19 05:34:24 PM PDT 24
Peak memory 196480 kb
Host smart-f2799065-9732-477f-8f8a-ae039aff1a37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581673773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.581673773
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all_with_rand_reset.1551017908
Short name T13
Test name
Test status
Simulation time 3950750098 ps
CPU time 46.47 seconds
Started Jul 19 05:10:17 PM PDT 24
Finished Jul 19 05:11:05 PM PDT 24
Peak memory 198296 kb
Host smart-86927ff3-2068-431d-b4b7-068d2c170be4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551017908 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all_with_rand_reset.1551017908
Directory /workspace/9.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.3381422127
Short name T260
Test name
Test status
Simulation time 276333211572 ps
CPU time 185.43 seconds
Started Jul 19 05:11:59 PM PDT 24
Finished Jul 19 05:15:06 PM PDT 24
Peak memory 191740 kb
Host smart-20e08885-3fd8-473b-a458-c7f060efa564
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381422127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.3381422127
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.1706824579
Short name T340
Test name
Test status
Simulation time 1005887685240 ps
CPU time 375.55 seconds
Started Jul 19 05:12:04 PM PDT 24
Finished Jul 19 05:18:20 PM PDT 24
Peak memory 191760 kb
Host smart-2da8d5da-a6f7-4874-aebe-b16a4abcb79d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706824579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.1706824579
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.4230668183
Short name T195
Test name
Test status
Simulation time 83274578543 ps
CPU time 134.82 seconds
Started Jul 19 05:11:59 PM PDT 24
Finished Jul 19 05:14:15 PM PDT 24
Peak memory 191760 kb
Host smart-da0576a1-bcad-455f-a67d-8f782dde2be5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230668183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.4230668183
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.4097613607
Short name T423
Test name
Test status
Simulation time 106339918407 ps
CPU time 98.93 seconds
Started Jul 19 05:12:01 PM PDT 24
Finished Jul 19 05:13:40 PM PDT 24
Peak memory 183576 kb
Host smart-56cb03ac-8555-479f-b416-46396ce304de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097613607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.4097613607
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.2599425188
Short name T23
Test name
Test status
Simulation time 280455025574 ps
CPU time 62.99 seconds
Started Jul 19 05:12:01 PM PDT 24
Finished Jul 19 05:13:05 PM PDT 24
Peak memory 183580 kb
Host smart-c8820f89-9896-4029-9445-916f875a135f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599425188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.2599425188
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.755777662
Short name T359
Test name
Test status
Simulation time 14237725391 ps
CPU time 79.96 seconds
Started Jul 19 05:12:00 PM PDT 24
Finished Jul 19 05:13:21 PM PDT 24
Peak memory 183568 kb
Host smart-885a3fc6-9a18-4f88-a972-bbbf16bb6eaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755777662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.755777662
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.2551759611
Short name T394
Test name
Test status
Simulation time 208699858014 ps
CPU time 82.39 seconds
Started Jul 19 05:12:10 PM PDT 24
Finished Jul 19 05:13:34 PM PDT 24
Peak memory 183744 kb
Host smart-5d2b6e59-4aff-45d9-aceb-9dd960e76c52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551759611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.2551759611
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.260147412
Short name T339
Test name
Test status
Simulation time 270100761261 ps
CPU time 127.63 seconds
Started Jul 19 05:12:08 PM PDT 24
Finished Jul 19 05:14:17 PM PDT 24
Peak memory 191760 kb
Host smart-22bf43b1-a78f-401e-be62-fa1ecd191286
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260147412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.260147412
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.1617645673
Short name T262
Test name
Test status
Simulation time 52761493288 ps
CPU time 44.45 seconds
Started Jul 19 05:12:12 PM PDT 24
Finished Jul 19 05:12:57 PM PDT 24
Peak memory 191780 kb
Host smart-f618e8e7-9ce4-44f7-aa83-0b1e68195b43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617645673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.1617645673
Directory /workspace/99.rv_timer_random/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%