Summary for Variable cp_intr_pin
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr_pin
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_pins[0] |
135824785 |
1 |
|
T1 |
195 |
|
T2 |
19797 |
|
T3 |
27460 |
Summary for Variable cp_intr_pin_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for cp_intr_pin_value
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x0] |
135821771 |
1 |
|
T1 |
152 |
|
T2 |
19797 |
|
T3 |
27460 |
values[0x1] |
3014 |
1 |
|
T1 |
43 |
|
T4 |
2 |
|
T5 |
2 |
transitions[0x0=>0x1] |
938 |
1 |
|
T1 |
8 |
|
T4 |
1 |
|
T5 |
1 |
transitions[0x1=>0x0] |
938 |
1 |
|
T1 |
8 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Cross cp_intr_pins_all_values
Samples crossed: cp_intr_pin cp_intr_pin_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_intr_pins_all_values
Bins
cp_intr_pin | cp_intr_pin_value | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_pins[0] |
values[0x0] |
135821771 |
1 |
|
T1 |
152 |
|
T2 |
19797 |
|
T3 |
27460 |
all_pins[0] |
values[0x1] |
3014 |
1 |
|
T1 |
43 |
|
T4 |
2 |
|
T5 |
2 |
all_pins[0] |
transitions[0x0=>0x1] |
938 |
1 |
|
T1 |
8 |
|
T4 |
1 |
|
T5 |
1 |
all_pins[0] |
transitions[0x1=>0x0] |
938 |
1 |
|
T1 |
8 |
|
T4 |
1 |
|
T5 |
1 |