Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
1445 |
1 |
|
T1 |
35 |
|
T9 |
14 |
|
T33 |
4 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
783 |
1 |
|
T1 |
20 |
|
T9 |
6 |
|
T33 |
1 |
auto[1] |
662 |
1 |
|
T1 |
15 |
|
T9 |
8 |
|
T33 |
3 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
556 |
1 |
|
T1 |
14 |
|
T9 |
5 |
|
T33 |
1 |
auto[1] |
889 |
1 |
|
T1 |
21 |
|
T9 |
9 |
|
T33 |
3 |
Summary for Variable cp_intr_test
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_test
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
833 |
1 |
|
T1 |
20 |
|
T9 |
7 |
|
T33 |
2 |
auto[1] |
612 |
1 |
|
T1 |
15 |
|
T9 |
7 |
|
T33 |
2 |
Summary for Cross intr_test_cg_cc
Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for intr_test_cg_cc
Bins
cp_intr | cp_intr_test | cp_intr_en | cp_intr_state | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
auto[0] |
314 |
1 |
|
T1 |
10 |
|
T9 |
1 |
|
T66 |
7 |
all_values[0] |
auto[0] |
auto[0] |
auto[1] |
145 |
1 |
|
T1 |
3 |
|
T33 |
1 |
|
T66 |
3 |
all_values[0] |
auto[0] |
auto[1] |
auto[0] |
242 |
1 |
|
T1 |
4 |
|
T9 |
4 |
|
T33 |
1 |
all_values[0] |
auto[0] |
auto[1] |
auto[1] |
132 |
1 |
|
T1 |
3 |
|
T9 |
2 |
|
T66 |
5 |
all_values[0] |
auto[1] |
auto[0] |
auto[1] |
324 |
1 |
|
T1 |
7 |
|
T9 |
5 |
|
T66 |
14 |
all_values[0] |
auto[1] |
auto[1] |
auto[1] |
288 |
1 |
|
T1 |
8 |
|
T9 |
2 |
|
T33 |
2 |
User Defined Cross Bins for intr_test_cg_cc
Excluded/Illegal bins
NAME | COUNT | STATUS |
test_1_state_0 |
0 |
Illegal |