Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.61 99.36 98.73 100.00 100.00 100.00 99.55


Total test records in report: 581
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T506 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.1718613460 Jul 20 04:32:27 PM PDT 24 Jul 20 04:32:31 PM PDT 24 52814085 ps
T507 /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.4216514940 Jul 20 04:32:24 PM PDT 24 Jul 20 04:32:26 PM PDT 24 27778702 ps
T508 /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.1529859189 Jul 20 04:32:02 PM PDT 24 Jul 20 04:32:09 PM PDT 24 2901578002 ps
T509 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.401418648 Jul 20 04:32:32 PM PDT 24 Jul 20 04:32:36 PM PDT 24 63604688 ps
T510 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3739103510 Jul 20 04:32:27 PM PDT 24 Jul 20 04:32:31 PM PDT 24 179460378 ps
T511 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.30643775 Jul 20 04:32:23 PM PDT 24 Jul 20 04:32:27 PM PDT 24 117506721 ps
T100 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2693061863 Jul 20 04:32:29 PM PDT 24 Jul 20 04:32:32 PM PDT 24 14895827 ps
T512 /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.533345318 Jul 20 04:32:09 PM PDT 24 Jul 20 04:32:11 PM PDT 24 17113907 ps
T513 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.1155054103 Jul 20 04:32:50 PM PDT 24 Jul 20 04:32:51 PM PDT 24 102154586 ps
T514 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1051315762 Jul 20 04:34:23 PM PDT 24 Jul 20 04:34:25 PM PDT 24 103936749 ps
T515 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1471188110 Jul 20 04:32:10 PM PDT 24 Jul 20 04:32:14 PM PDT 24 168339146 ps
T516 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3747835886 Jul 20 04:32:31 PM PDT 24 Jul 20 04:32:35 PM PDT 24 19091016 ps
T517 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.2396374388 Jul 20 04:32:27 PM PDT 24 Jul 20 04:32:30 PM PDT 24 12071068 ps
T518 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.902878116 Jul 20 04:32:41 PM PDT 24 Jul 20 04:32:44 PM PDT 24 24742514 ps
T519 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1488078788 Jul 20 04:32:36 PM PDT 24 Jul 20 04:32:39 PM PDT 24 70327355 ps
T520 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.2612048342 Jul 20 04:32:19 PM PDT 24 Jul 20 04:32:21 PM PDT 24 48948288 ps
T521 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.277304586 Jul 20 04:32:25 PM PDT 24 Jul 20 04:32:28 PM PDT 24 30933721 ps
T522 /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.1303460079 Jul 20 04:32:44 PM PDT 24 Jul 20 04:32:46 PM PDT 24 15520641 ps
T523 /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.3790194979 Jul 20 04:32:26 PM PDT 24 Jul 20 04:32:29 PM PDT 24 14156580 ps
T524 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.584557783 Jul 20 04:32:03 PM PDT 24 Jul 20 04:32:08 PM PDT 24 87174908 ps
T525 /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.2390584540 Jul 20 04:32:31 PM PDT 24 Jul 20 04:32:35 PM PDT 24 12269936 ps
T97 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.341606352 Jul 20 04:32:07 PM PDT 24 Jul 20 04:32:09 PM PDT 24 15153882 ps
T526 /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.3596799178 Jul 20 04:32:27 PM PDT 24 Jul 20 04:32:31 PM PDT 24 12776795 ps
T527 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.111536170 Jul 20 04:32:03 PM PDT 24 Jul 20 04:32:08 PM PDT 24 195700123 ps
T528 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3112384382 Jul 20 04:32:29 PM PDT 24 Jul 20 04:32:33 PM PDT 24 30147079 ps
T529 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.3799410135 Jul 20 04:32:08 PM PDT 24 Jul 20 04:32:10 PM PDT 24 15815693 ps
T530 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1120691572 Jul 20 04:32:28 PM PDT 24 Jul 20 04:32:31 PM PDT 24 55935637 ps
T531 /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.458837920 Jul 20 04:34:20 PM PDT 24 Jul 20 04:34:21 PM PDT 24 31985056 ps
T532 /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.1858543154 Jul 20 04:32:28 PM PDT 24 Jul 20 04:32:38 PM PDT 24 33822685 ps
T533 /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.1494386387 Jul 20 04:32:33 PM PDT 24 Jul 20 04:32:37 PM PDT 24 22309942 ps
T534 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.2253246034 Jul 20 04:32:38 PM PDT 24 Jul 20 04:32:41 PM PDT 24 35164771 ps
T535 /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.2363965316 Jul 20 04:32:10 PM PDT 24 Jul 20 04:32:12 PM PDT 24 98352209 ps
T536 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.348458404 Jul 20 04:32:07 PM PDT 24 Jul 20 04:32:09 PM PDT 24 54904503 ps
T537 /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.1284577181 Jul 20 04:32:30 PM PDT 24 Jul 20 04:32:34 PM PDT 24 14216183 ps
T538 /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.3848584460 Jul 20 04:32:21 PM PDT 24 Jul 20 04:32:23 PM PDT 24 13728948 ps
T539 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.3832226326 Jul 20 04:32:30 PM PDT 24 Jul 20 04:32:34 PM PDT 24 43018621 ps
T540 /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3170248380 Jul 20 04:32:42 PM PDT 24 Jul 20 04:32:44 PM PDT 24 78330146 ps
T541 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.313383235 Jul 20 04:32:44 PM PDT 24 Jul 20 04:32:46 PM PDT 24 23397873 ps
T542 /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.4165383826 Jul 20 04:32:04 PM PDT 24 Jul 20 04:32:08 PM PDT 24 36767378 ps
T543 /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.4037710529 Jul 20 04:32:44 PM PDT 24 Jul 20 04:32:47 PM PDT 24 48719692 ps
T544 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.4117255712 Jul 20 04:32:10 PM PDT 24 Jul 20 04:32:15 PM PDT 24 1695904809 ps
T545 /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.535924370 Jul 20 04:32:11 PM PDT 24 Jul 20 04:32:13 PM PDT 24 31927180 ps
T546 /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.334031631 Jul 20 04:32:32 PM PDT 24 Jul 20 04:32:36 PM PDT 24 137493896 ps
T547 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1129972622 Jul 20 04:32:27 PM PDT 24 Jul 20 04:32:31 PM PDT 24 89790629 ps
T548 /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.2548411576 Jul 20 04:32:10 PM PDT 24 Jul 20 04:32:11 PM PDT 24 48246449 ps
T549 /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.1142358160 Jul 20 04:32:08 PM PDT 24 Jul 20 04:32:13 PM PDT 24 1638228527 ps
T550 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1773598842 Jul 20 04:32:46 PM PDT 24 Jul 20 04:32:49 PM PDT 24 51604751 ps
T107 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.674242206 Jul 20 04:32:26 PM PDT 24 Jul 20 04:32:30 PM PDT 24 81099004 ps
T551 /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.4275769440 Jul 20 04:32:25 PM PDT 24 Jul 20 04:32:28 PM PDT 24 40567806 ps
T552 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.493687271 Jul 20 04:32:33 PM PDT 24 Jul 20 04:32:37 PM PDT 24 12162937 ps
T553 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.1501234174 Jul 20 04:32:31 PM PDT 24 Jul 20 04:32:36 PM PDT 24 25548966 ps
T554 /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2386656919 Jul 20 04:32:14 PM PDT 24 Jul 20 04:32:16 PM PDT 24 237628385 ps
T555 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3514689936 Jul 20 04:32:43 PM PDT 24 Jul 20 04:32:45 PM PDT 24 91785242 ps
T556 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.1315807063 Jul 20 04:32:36 PM PDT 24 Jul 20 04:32:39 PM PDT 24 23279152 ps
T557 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1717477698 Jul 20 04:32:01 PM PDT 24 Jul 20 04:32:05 PM PDT 24 66377773 ps
T558 /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3104425967 Jul 20 04:32:24 PM PDT 24 Jul 20 04:32:26 PM PDT 24 22751788 ps
T559 /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.2208278566 Jul 20 04:32:39 PM PDT 24 Jul 20 04:32:44 PM PDT 24 146653256 ps
T560 /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.248330776 Jul 20 04:32:04 PM PDT 24 Jul 20 04:32:08 PM PDT 24 17229618 ps
T561 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.12980271 Jul 20 04:32:30 PM PDT 24 Jul 20 04:32:34 PM PDT 24 59395822 ps
T562 /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.119182970 Jul 20 04:32:36 PM PDT 24 Jul 20 04:32:39 PM PDT 24 12788790 ps
T563 /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.1467051766 Jul 20 04:32:36 PM PDT 24 Jul 20 04:32:39 PM PDT 24 70419909 ps
T564 /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.683049223 Jul 20 04:32:38 PM PDT 24 Jul 20 04:32:42 PM PDT 24 34907902 ps
T565 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.843244362 Jul 20 04:32:29 PM PDT 24 Jul 20 04:32:32 PM PDT 24 101682062 ps
T566 /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.639268005 Jul 20 04:34:21 PM PDT 24 Jul 20 04:34:22 PM PDT 24 190475713 ps
T567 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.1213326560 Jul 20 04:32:24 PM PDT 24 Jul 20 04:32:26 PM PDT 24 40835518 ps
T98 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2301451986 Jul 20 04:32:10 PM PDT 24 Jul 20 04:32:12 PM PDT 24 27347557 ps
T568 /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.1777901121 Jul 20 04:32:39 PM PDT 24 Jul 20 04:32:44 PM PDT 24 202725322 ps
T569 /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.4048405609 Jul 20 04:32:04 PM PDT 24 Jul 20 04:32:07 PM PDT 24 30871744 ps
T570 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.503637641 Jul 20 04:32:34 PM PDT 24 Jul 20 04:32:37 PM PDT 24 15442110 ps
T99 /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3999183519 Jul 20 04:32:30 PM PDT 24 Jul 20 04:32:34 PM PDT 24 31189161 ps
T571 /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.2723174511 Jul 20 04:32:36 PM PDT 24 Jul 20 04:32:39 PM PDT 24 46671739 ps
T572 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.1924425320 Jul 20 04:32:09 PM PDT 24 Jul 20 04:32:10 PM PDT 24 33539871 ps
T573 /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.599683234 Jul 20 04:32:19 PM PDT 24 Jul 20 04:32:20 PM PDT 24 88467433 ps
T574 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.4208267843 Jul 20 04:32:45 PM PDT 24 Jul 20 04:32:47 PM PDT 24 42520178 ps
T575 /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.2025712806 Jul 20 04:32:04 PM PDT 24 Jul 20 04:32:07 PM PDT 24 15855278 ps
T576 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2846990389 Jul 20 04:32:25 PM PDT 24 Jul 20 04:32:28 PM PDT 24 101043852 ps
T577 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.891608357 Jul 20 04:32:32 PM PDT 24 Jul 20 04:32:36 PM PDT 24 16927162 ps
T578 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.2660594223 Jul 20 04:32:25 PM PDT 24 Jul 20 04:32:27 PM PDT 24 85762023 ps
T579 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.867300216 Jul 20 04:32:26 PM PDT 24 Jul 20 04:32:28 PM PDT 24 31119661 ps
T580 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1194457697 Jul 20 04:32:32 PM PDT 24 Jul 20 04:32:36 PM PDT 24 39155312 ps
T581 /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.2549513295 Jul 20 04:32:26 PM PDT 24 Jul 20 04:32:28 PM PDT 24 14398329 ps

Test location /workspace/coverage/default/46.rv_timer_stress_all.826185361
Short name T9
Test name
Test status
Simulation time 1931151652480 ps
CPU time 1628.93 seconds
Started Jul 20 04:33:24 PM PDT 24
Finished Jul 20 05:00:40 PM PDT 24
Peak memory 191640 kb
Host smart-9db8d12b-47bb-4e82-ab5f-e5f7d770dfc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826185361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all.
826185361
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all_with_rand_reset.401247507
Short name T34
Test name
Test status
Simulation time 228759316614 ps
CPU time 591.18 seconds
Started Jul 20 04:33:16 PM PDT 24
Finished Jul 20 04:43:09 PM PDT 24
Peak memory 208556 kb
Host smart-3a253261-5b47-4073-9105-0bf3eea5698f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401247507 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all_with_rand_reset.401247507
Directory /workspace/28.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.2925038245
Short name T84
Test name
Test status
Simulation time 673993997360 ps
CPU time 1641.56 seconds
Started Jul 20 04:32:32 PM PDT 24
Finished Jul 20 04:59:57 PM PDT 24
Peak memory 191616 kb
Host smart-e936dc01-5bf9-42d3-a9e8-70bd6b1883c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925038245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
2925038245
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.489140624
Short name T28
Test name
Test status
Simulation time 357084878 ps
CPU time 1.05 seconds
Started Jul 20 04:32:39 PM PDT 24
Finished Jul 20 04:32:43 PM PDT 24
Peak memory 182936 kb
Host smart-d7d9e89c-c3d7-4d02-b77b-db900448cb1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489140624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_in
tg_err.489140624
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.3406535086
Short name T168
Test name
Test status
Simulation time 2357734170890 ps
CPU time 2191.02 seconds
Started Jul 20 04:33:11 PM PDT 24
Finished Jul 20 05:09:44 PM PDT 24
Peak memory 191604 kb
Host smart-4a6fab18-b45e-413f-bf4c-730727ea218b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406535086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.3406535086
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.2384024454
Short name T273
Test name
Test status
Simulation time 443909133120 ps
CPU time 1358.81 seconds
Started Jul 20 04:33:17 PM PDT 24
Finished Jul 20 04:55:59 PM PDT 24
Peak memory 196928 kb
Host smart-2f214cf0-45fb-47c9-99a0-70a33b6f892f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384024454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.2384024454
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.1944120958
Short name T158
Test name
Test status
Simulation time 1386566496709 ps
CPU time 4453.27 seconds
Started Jul 20 04:33:02 PM PDT 24
Finished Jul 20 05:47:17 PM PDT 24
Peak memory 191640 kb
Host smart-612cb25b-2307-47a3-8813-22510e99a9c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944120958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.1944120958
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.3518161800
Short name T220
Test name
Test status
Simulation time 389781034807 ps
CPU time 846.56 seconds
Started Jul 20 04:33:16 PM PDT 24
Finished Jul 20 04:47:26 PM PDT 24
Peak memory 191580 kb
Host smart-1f731ba8-152a-4f4f-b886-d9220c9bbdbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518161800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.3518161800
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.1913538259
Short name T219
Test name
Test status
Simulation time 528110238124 ps
CPU time 768.57 seconds
Started Jul 20 04:33:22 PM PDT 24
Finished Jul 20 04:46:17 PM PDT 24
Peak memory 191960 kb
Host smart-abbb81da-ee9e-40ec-a5f2-0594057035ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913538259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.1913538259
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.2642533814
Short name T130
Test name
Test status
Simulation time 3808472471936 ps
CPU time 3036.75 seconds
Started Jul 20 04:32:44 PM PDT 24
Finished Jul 20 05:23:23 PM PDT 24
Peak memory 195800 kb
Host smart-10fbc45f-021d-43d1-961b-a92eeca12a65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642533814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.2642533814
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.2622825606
Short name T169
Test name
Test status
Simulation time 322672336491 ps
CPU time 579.33 seconds
Started Jul 20 04:32:52 PM PDT 24
Finished Jul 20 04:42:32 PM PDT 24
Peak memory 195620 kb
Host smart-fb16f2c8-a265-4346-b8d7-faddd0aca01c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622825606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.2622825606
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_random.2107344703
Short name T133
Test name
Test status
Simulation time 349314561514 ps
CPU time 494.21 seconds
Started Jul 20 04:33:17 PM PDT 24
Finished Jul 20 04:41:42 PM PDT 24
Peak memory 191620 kb
Host smart-b7b931e1-b69a-4fab-8195-c0091c4e9ead
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107344703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.2107344703
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.1365996737
Short name T17
Test name
Test status
Simulation time 151625847 ps
CPU time 0.89 seconds
Started Jul 20 04:32:46 PM PDT 24
Finished Jul 20 04:32:49 PM PDT 24
Peak memory 213680 kb
Host smart-d53f92ad-b926-4929-9fc8-f9bf1559732a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365996737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.1365996737
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.560609283
Short name T238
Test name
Test status
Simulation time 3292689530546 ps
CPU time 893.24 seconds
Started Jul 20 04:33:17 PM PDT 24
Finished Jul 20 04:48:15 PM PDT 24
Peak memory 191636 kb
Host smart-7e7913c7-1fbf-46ec-a9a0-d2dccc6ee41a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560609283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all.
560609283
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.1149829559
Short name T32
Test name
Test status
Simulation time 38595009 ps
CPU time 0.67 seconds
Started Jul 20 04:31:59 PM PDT 24
Finished Jul 20 04:32:04 PM PDT 24
Peak memory 191416 kb
Host smart-2ff3d69f-c38c-48fa-85f2-211aa323671e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149829559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.1149829559
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.481678810
Short name T163
Test name
Test status
Simulation time 1246312600043 ps
CPU time 2450.82 seconds
Started Jul 20 04:33:15 PM PDT 24
Finished Jul 20 05:14:09 PM PDT 24
Peak memory 191696 kb
Host smart-15f42756-b45e-456c-b19e-b697109e27cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481678810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all.
481678810
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/148.rv_timer_random.3286540130
Short name T114
Test name
Test status
Simulation time 142753610783 ps
CPU time 607.59 seconds
Started Jul 20 04:33:36 PM PDT 24
Finished Jul 20 04:43:52 PM PDT 24
Peak memory 191580 kb
Host smart-0d930efe-1b70-43c8-ae68-4ac43721f643
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286540130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.3286540130
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.801794632
Short name T216
Test name
Test status
Simulation time 504013505104 ps
CPU time 330.24 seconds
Started Jul 20 04:32:46 PM PDT 24
Finished Jul 20 04:38:18 PM PDT 24
Peak memory 191636 kb
Host smart-74c42fa6-3ee3-4f7c-b883-c7fba2b60776
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801794632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all.
801794632
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.2850735816
Short name T189
Test name
Test status
Simulation time 2798436404613 ps
CPU time 2025.36 seconds
Started Jul 20 04:33:03 PM PDT 24
Finished Jul 20 05:06:50 PM PDT 24
Peak memory 191540 kb
Host smart-0ff8b8ca-9b75-43d7-90ce-f61b72fa4ab3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850735816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.2850735816
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.2446344740
Short name T295
Test name
Test status
Simulation time 1543358877086 ps
CPU time 1501.21 seconds
Started Jul 20 04:33:03 PM PDT 24
Finished Jul 20 04:58:05 PM PDT 24
Peak memory 196344 kb
Host smart-b7c3bcf1-5a71-45c1-bee1-d0955a232d8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446344740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
2446344740
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/130.rv_timer_random.3205313019
Short name T191
Test name
Test status
Simulation time 118264119457 ps
CPU time 196.63 seconds
Started Jul 20 04:33:20 PM PDT 24
Finished Jul 20 04:36:43 PM PDT 24
Peak memory 191580 kb
Host smart-d2b1d7dd-c2b2-415c-81fc-1bd53828d6b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205313019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.3205313019
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.2334136241
Short name T33
Test name
Test status
Simulation time 1074437584873 ps
CPU time 868.71 seconds
Started Jul 20 04:32:58 PM PDT 24
Finished Jul 20 04:47:27 PM PDT 24
Peak memory 191652 kb
Host smart-ecdae636-fb86-4b73-aab4-0dd844f7c9ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334136241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.2334136241
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_random.1027875668
Short name T113
Test name
Test status
Simulation time 91455576278 ps
CPU time 142.72 seconds
Started Jul 20 04:33:21 PM PDT 24
Finished Jul 20 04:35:50 PM PDT 24
Peak memory 191908 kb
Host smart-c53665a2-3a5f-4329-9fcb-c3d76f460c07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027875668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.1027875668
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.2243059192
Short name T174
Test name
Test status
Simulation time 1566848584355 ps
CPU time 528.21 seconds
Started Jul 20 04:32:47 PM PDT 24
Finished Jul 20 04:41:37 PM PDT 24
Peak memory 195804 kb
Host smart-d18798a0-aba3-496a-acdb-018d939d53bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243059192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.2243059192
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_random.2316878585
Short name T145
Test name
Test status
Simulation time 658004961885 ps
CPU time 284.52 seconds
Started Jul 20 04:33:03 PM PDT 24
Finished Jul 20 04:37:49 PM PDT 24
Peak memory 191684 kb
Host smart-3c2cbc3f-a46c-4b79-8ea7-b8ad542064d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316878585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.2316878585
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/100.rv_timer_random.468391631
Short name T255
Test name
Test status
Simulation time 118421813084 ps
CPU time 224.63 seconds
Started Jul 20 04:33:24 PM PDT 24
Finished Jul 20 04:37:16 PM PDT 24
Peak memory 190992 kb
Host smart-fc7fe989-83c5-4268-b3e4-4e556adbb12f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468391631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.468391631
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.1636100536
Short name T279
Test name
Test status
Simulation time 105725441637 ps
CPU time 164.97 seconds
Started Jul 20 04:33:30 PM PDT 24
Finished Jul 20 04:36:22 PM PDT 24
Peak memory 183708 kb
Host smart-ad21e103-90ed-4575-a475-10eddcd317fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636100536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.1636100536
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random.2993443167
Short name T285
Test name
Test status
Simulation time 1218532191481 ps
CPU time 687.64 seconds
Started Jul 20 04:33:09 PM PDT 24
Finished Jul 20 04:44:38 PM PDT 24
Peak memory 191612 kb
Host smart-8cb99d13-cc9e-48b0-a1cc-6372a928e55a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993443167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.2993443167
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.191446761
Short name T46
Test name
Test status
Simulation time 107406539430 ps
CPU time 696.37 seconds
Started Jul 20 04:33:27 PM PDT 24
Finished Jul 20 04:45:11 PM PDT 24
Peak memory 191632 kb
Host smart-7a7a22f1-fb71-4133-9e2c-d20756f65411
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191446761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.191446761
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.3385530239
Short name T153
Test name
Test status
Simulation time 217042770693 ps
CPU time 533.54 seconds
Started Jul 20 04:33:23 PM PDT 24
Finished Jul 20 04:42:23 PM PDT 24
Peak memory 191724 kb
Host smart-4928bdaa-27b9-4fa2-89a7-0426cfcd3f31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385530239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.3385530239
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.570542267
Short name T275
Test name
Test status
Simulation time 162081546684 ps
CPU time 1089.98 seconds
Started Jul 20 04:33:21 PM PDT 24
Finished Jul 20 04:51:38 PM PDT 24
Peak memory 191636 kb
Host smart-c6cc2a01-fd7c-44a0-b0bd-8bd2746ab656
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570542267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.570542267
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.3816867057
Short name T342
Test name
Test status
Simulation time 703811110845 ps
CPU time 487.12 seconds
Started Jul 20 04:33:27 PM PDT 24
Finished Jul 20 04:41:41 PM PDT 24
Peak memory 191632 kb
Host smart-592c8ae1-342e-4434-be26-d03761ac6ed5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816867057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.3816867057
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.963218055
Short name T286
Test name
Test status
Simulation time 317283183386 ps
CPU time 359.71 seconds
Started Jul 20 04:32:37 PM PDT 24
Finished Jul 20 04:38:40 PM PDT 24
Peak memory 191520 kb
Host smart-3d64bbd4-da81-4766-a76d-7bc0ff69b039
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963218055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.963218055
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.2067094824
Short name T144
Test name
Test status
Simulation time 94207903309 ps
CPU time 141.94 seconds
Started Jul 20 04:33:06 PM PDT 24
Finished Jul 20 04:35:29 PM PDT 24
Peak memory 191584 kb
Host smart-2965cc6d-c382-4d42-a4c6-a7e1d0ec9429
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067094824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.2067094824
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/135.rv_timer_random.3730172160
Short name T190
Test name
Test status
Simulation time 286360402496 ps
CPU time 898.47 seconds
Started Jul 20 04:33:33 PM PDT 24
Finished Jul 20 04:48:40 PM PDT 24
Peak memory 191640 kb
Host smart-fa7bb9e4-16a3-4698-92fa-1925e3a69d3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730172160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.3730172160
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.3884045635
Short name T307
Test name
Test status
Simulation time 1018613620669 ps
CPU time 524.04 seconds
Started Jul 20 04:33:12 PM PDT 24
Finished Jul 20 04:41:57 PM PDT 24
Peak memory 191568 kb
Host smart-b6e3824f-5f77-4be0-bcc2-7814ac30306b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884045635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.3884045635
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.699097853
Short name T340
Test name
Test status
Simulation time 886998618810 ps
CPU time 1235.29 seconds
Started Jul 20 04:33:01 PM PDT 24
Finished Jul 20 04:53:38 PM PDT 24
Peak memory 196328 kb
Host smart-ce73025d-3bcc-4eba-b5e9-b4b08f965144
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699097853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all.
699097853
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.3578793744
Short name T49
Test name
Test status
Simulation time 613304935273 ps
CPU time 666.46 seconds
Started Jul 20 04:33:10 PM PDT 24
Finished Jul 20 04:44:17 PM PDT 24
Peak memory 191636 kb
Host smart-6c2a71f3-253a-41d6-98c2-eff4ca7c8ab5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578793744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.3578793744
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/72.rv_timer_random.752662081
Short name T338
Test name
Test status
Simulation time 99522666046 ps
CPU time 918.84 seconds
Started Jul 20 04:33:15 PM PDT 24
Finished Jul 20 04:48:36 PM PDT 24
Peak memory 191580 kb
Host smart-44185cdc-a303-4eec-a86d-5c9e225785f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752662081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.752662081
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random.518620770
Short name T203
Test name
Test status
Simulation time 812336651093 ps
CPU time 345.78 seconds
Started Jul 20 04:32:33 PM PDT 24
Finished Jul 20 04:38:22 PM PDT 24
Peak memory 193728 kb
Host smart-2ce1fb07-6b8b-4860-a2b5-80ca5f874653
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518620770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.518620770
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.1709292600
Short name T185
Test name
Test status
Simulation time 206745409305 ps
CPU time 78.29 seconds
Started Jul 20 04:32:38 PM PDT 24
Finished Jul 20 04:34:00 PM PDT 24
Peak memory 191580 kb
Host smart-31817f7a-a5f0-4fbf-afa5-e6c44c40b8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709292600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.1709292600
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_random.876598705
Short name T330
Test name
Test status
Simulation time 118564481809 ps
CPU time 1814.87 seconds
Started Jul 20 04:32:36 PM PDT 24
Finished Jul 20 05:02:54 PM PDT 24
Peak memory 191616 kb
Host smart-764b03ea-8b7a-424d-99a8-a01d266d59cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876598705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.876598705
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.3412709107
Short name T265
Test name
Test status
Simulation time 160811287443 ps
CPU time 634.09 seconds
Started Jul 20 04:33:15 PM PDT 24
Finished Jul 20 04:43:52 PM PDT 24
Peak memory 191552 kb
Host smart-d61ae741-e421-4e15-bb55-b813c829b222
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412709107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.3412709107
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.386343649
Short name T179
Test name
Test status
Simulation time 200222930760 ps
CPU time 1135.3 seconds
Started Jul 20 04:33:23 PM PDT 24
Finished Jul 20 04:52:25 PM PDT 24
Peak memory 191560 kb
Host smart-1d2533a5-2689-44ae-a896-367cfdd8a841
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386343649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.386343649
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.1603459066
Short name T243
Test name
Test status
Simulation time 208229390703 ps
CPU time 100.55 seconds
Started Jul 20 04:33:32 PM PDT 24
Finished Jul 20 04:35:21 PM PDT 24
Peak memory 192916 kb
Host smart-127045a3-c842-4b1d-826b-ed7fbe29cbb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603459066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.1603459066
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.610171179
Short name T198
Test name
Test status
Simulation time 1151083183471 ps
CPU time 1147.23 seconds
Started Jul 20 04:33:13 PM PDT 24
Finished Jul 20 04:52:23 PM PDT 24
Peak memory 191636 kb
Host smart-28710b23-26fd-4dbd-b7be-6fff8d3bab6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610171179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all.
610171179
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/103.rv_timer_random.435549785
Short name T237
Test name
Test status
Simulation time 98366554590 ps
CPU time 265.71 seconds
Started Jul 20 04:33:19 PM PDT 24
Finished Jul 20 04:37:51 PM PDT 24
Peak memory 183408 kb
Host smart-f176fba2-5af0-4362-bf0b-79a545fb7323
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435549785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.435549785
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.4037296071
Short name T157
Test name
Test status
Simulation time 308514436979 ps
CPU time 254.39 seconds
Started Jul 20 04:33:34 PM PDT 24
Finished Jul 20 04:37:57 PM PDT 24
Peak memory 191632 kb
Host smart-b73c1b04-7bf0-4b57-b646-aff735b13ffa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037296071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.4037296071
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.3969049880
Short name T293
Test name
Test status
Simulation time 181767150900 ps
CPU time 302.01 seconds
Started Jul 20 04:33:19 PM PDT 24
Finished Jul 20 04:38:27 PM PDT 24
Peak memory 191604 kb
Host smart-e94b14f0-a39c-4d30-a5cd-274b499f4d48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969049880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.3969049880
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.4149741765
Short name T115
Test name
Test status
Simulation time 123875518535 ps
CPU time 386.74 seconds
Started Jul 20 04:33:36 PM PDT 24
Finished Jul 20 04:40:11 PM PDT 24
Peak memory 191640 kb
Host smart-b5f50f4f-915f-435a-8840-16c67aca31fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149741765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.4149741765
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.461754446
Short name T166
Test name
Test status
Simulation time 929987262097 ps
CPU time 3568.15 seconds
Started Jul 20 04:33:10 PM PDT 24
Finished Jul 20 05:32:39 PM PDT 24
Peak memory 191696 kb
Host smart-7d03fdd2-4eca-4a88-930a-344886639152
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461754446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all.
461754446
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.3791115893
Short name T278
Test name
Test status
Simulation time 222261422234 ps
CPU time 125.19 seconds
Started Jul 20 04:32:45 PM PDT 24
Finished Jul 20 04:34:53 PM PDT 24
Peak memory 191680 kb
Host smart-a1f4bd9b-1141-4602-9b28-565ff75c8fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791115893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.3791115893
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.3756146553
Short name T143
Test name
Test status
Simulation time 375940320419 ps
CPU time 602.87 seconds
Started Jul 20 04:33:14 PM PDT 24
Finished Jul 20 04:43:19 PM PDT 24
Peak memory 183440 kb
Host smart-c3aa3c0a-d0d3-4080-b73e-401014701bd5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756146553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.3756146553
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_random.3931813109
Short name T146
Test name
Test status
Simulation time 204261924175 ps
CPU time 380.37 seconds
Started Jul 20 04:33:15 PM PDT 24
Finished Jul 20 04:39:37 PM PDT 24
Peak memory 191632 kb
Host smart-cb654aea-a7bf-4748-9c80-1902bd045a70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931813109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.3931813109
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.2459045836
Short name T197
Test name
Test status
Simulation time 104850561117 ps
CPU time 1046.5 seconds
Started Jul 20 04:33:19 PM PDT 24
Finished Jul 20 04:50:51 PM PDT 24
Peak memory 191536 kb
Host smart-cece415f-9d70-46c2-ae78-629259061a17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459045836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.2459045836
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.3124000508
Short name T96
Test name
Test status
Simulation time 16345871 ps
CPU time 0.59 seconds
Started Jul 20 04:32:26 PM PDT 24
Finished Jul 20 04:32:29 PM PDT 24
Peak memory 182364 kb
Host smart-ee368b22-42c9-4df0-a798-7956b6a952e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124000508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.3124000508
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.2906120325
Short name T195
Test name
Test status
Simulation time 1310323400680 ps
CPU time 661.88 seconds
Started Jul 20 04:33:03 PM PDT 24
Finished Jul 20 04:44:07 PM PDT 24
Peak memory 183428 kb
Host smart-47654fc1-de5d-41fe-802d-48c2f4533afd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906120325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.2906120325
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/104.rv_timer_random.2483644031
Short name T111
Test name
Test status
Simulation time 22834211628 ps
CPU time 308.44 seconds
Started Jul 20 04:33:31 PM PDT 24
Finished Jul 20 04:38:48 PM PDT 24
Peak memory 191640 kb
Host smart-596ba51d-e718-4008-a6de-7ad397d3666d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483644031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.2483644031
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.3277201724
Short name T73
Test name
Test status
Simulation time 159541428361 ps
CPU time 595.37 seconds
Started Jul 20 04:33:17 PM PDT 24
Finished Jul 20 04:43:17 PM PDT 24
Peak memory 191608 kb
Host smart-0f9b8ab1-a114-4c3a-858f-a79df1179816
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277201724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.3277201724
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.3007016521
Short name T228
Test name
Test status
Simulation time 179141251463 ps
CPU time 443.76 seconds
Started Jul 20 04:33:27 PM PDT 24
Finished Jul 20 04:40:58 PM PDT 24
Peak memory 191584 kb
Host smart-e782126f-a746-4e80-b7f6-e64c6061e142
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007016521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.3007016521
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.2035232404
Short name T225
Test name
Test status
Simulation time 98441970822 ps
CPU time 192 seconds
Started Jul 20 04:33:31 PM PDT 24
Finished Jul 20 04:36:51 PM PDT 24
Peak memory 191644 kb
Host smart-1e25e848-6b58-41a7-84d2-b99651e7b35b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035232404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.2035232404
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.883038354
Short name T129
Test name
Test status
Simulation time 1099272794242 ps
CPU time 437.76 seconds
Started Jul 20 04:33:18 PM PDT 24
Finished Jul 20 04:40:42 PM PDT 24
Peak memory 191656 kb
Host smart-33189c24-6a8e-479e-85c3-267f5f78f33a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883038354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.883038354
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.1561924268
Short name T208
Test name
Test status
Simulation time 1534218695876 ps
CPU time 314.65 seconds
Started Jul 20 04:33:17 PM PDT 24
Finished Jul 20 04:38:36 PM PDT 24
Peak memory 191460 kb
Host smart-de2a7392-ba11-4aea-9ee5-21d619268fce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561924268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.1561924268
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.1051050195
Short name T155
Test name
Test status
Simulation time 248057065481 ps
CPU time 542.63 seconds
Started Jul 20 04:33:23 PM PDT 24
Finished Jul 20 04:42:32 PM PDT 24
Peak memory 191556 kb
Host smart-9433a830-330c-4dce-9673-da7fd8ad613d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051050195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.1051050195
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.1072416325
Short name T300
Test name
Test status
Simulation time 130662148694 ps
CPU time 179.19 seconds
Started Jul 20 04:33:28 PM PDT 24
Finished Jul 20 04:36:35 PM PDT 24
Peak memory 191588 kb
Host smart-e753bc2e-ef5e-44a8-856f-ea13d87e87bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072416325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.1072416325
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.3523152136
Short name T270
Test name
Test status
Simulation time 95551759190 ps
CPU time 36.25 seconds
Started Jul 20 04:33:30 PM PDT 24
Finished Jul 20 04:34:15 PM PDT 24
Peak memory 183508 kb
Host smart-13b39ed0-a4bc-4314-8e3b-0786c6ca8110
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523152136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.3523152136
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.1834432240
Short name T171
Test name
Test status
Simulation time 867244324770 ps
CPU time 403.92 seconds
Started Jul 20 04:33:34 PM PDT 24
Finished Jul 20 04:40:26 PM PDT 24
Peak memory 192660 kb
Host smart-0b5273b2-e6b8-46fc-91c1-224cc89db048
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834432240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.1834432240
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.3903815939
Short name T182
Test name
Test status
Simulation time 101921590529 ps
CPU time 546.97 seconds
Started Jul 20 04:33:27 PM PDT 24
Finished Jul 20 04:42:41 PM PDT 24
Peak memory 191580 kb
Host smart-2c7deb61-5886-43a9-86d6-205c676c89b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903815939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.3903815939
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.568440431
Short name T79
Test name
Test status
Simulation time 478954866443 ps
CPU time 811.59 seconds
Started Jul 20 04:33:20 PM PDT 24
Finished Jul 20 04:46:58 PM PDT 24
Peak memory 191628 kb
Host smart-60366487-6e9a-4a82-a241-9e53957cea10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568440431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.568440431
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random.258015721
Short name T347
Test name
Test status
Simulation time 141390892967 ps
CPU time 205.9 seconds
Started Jul 20 04:33:17 PM PDT 24
Finished Jul 20 04:36:48 PM PDT 24
Peak memory 191576 kb
Host smart-bd13df71-40db-4f4f-866a-89e32c35bced
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258015721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.258015721
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random.2802783700
Short name T282
Test name
Test status
Simulation time 465655422464 ps
CPU time 246.35 seconds
Started Jul 20 04:33:01 PM PDT 24
Finished Jul 20 04:37:08 PM PDT 24
Peak memory 191576 kb
Host smart-ae5a49c5-5bb6-4b6f-8693-8be7cff22b4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802783700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.2802783700
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.4136592014
Short name T297
Test name
Test status
Simulation time 253898787189 ps
CPU time 413.44 seconds
Started Jul 20 04:33:04 PM PDT 24
Finished Jul 20 04:39:59 PM PDT 24
Peak memory 191624 kb
Host smart-6c0200f0-f6eb-4a2e-95ef-dd6cbac90649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136592014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.4136592014
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/68.rv_timer_random.4151138870
Short name T264
Test name
Test status
Simulation time 891663714264 ps
CPU time 766.25 seconds
Started Jul 20 04:33:21 PM PDT 24
Finished Jul 20 04:46:14 PM PDT 24
Peak memory 191584 kb
Host smart-feee5259-6367-42d1-b455-160c58206b37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151138870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.4151138870
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.1466500536
Short name T257
Test name
Test status
Simulation time 20667780866 ps
CPU time 17.86 seconds
Started Jul 20 04:32:43 PM PDT 24
Finished Jul 20 04:33:03 PM PDT 24
Peak memory 183424 kb
Host smart-4edbffc7-9e38-46ee-b3af-cd2ef8834126
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466500536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.1466500536
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/101.rv_timer_random.828501160
Short name T252
Test name
Test status
Simulation time 94063784976 ps
CPU time 460.7 seconds
Started Jul 20 04:33:21 PM PDT 24
Finished Jul 20 04:41:08 PM PDT 24
Peak memory 191612 kb
Host smart-b83f445a-5d88-4048-8d8c-4ab366d31927
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828501160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.828501160
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random.1548535254
Short name T121
Test name
Test status
Simulation time 1533801928073 ps
CPU time 698.15 seconds
Started Jul 20 04:33:12 PM PDT 24
Finished Jul 20 04:44:52 PM PDT 24
Peak memory 191580 kb
Host smart-0b041395-af29-40a6-bef3-a28d87cd8b16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548535254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.1548535254
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.219472205
Short name T60
Test name
Test status
Simulation time 251319117546 ps
CPU time 129.22 seconds
Started Jul 20 04:33:35 PM PDT 24
Finished Jul 20 04:35:53 PM PDT 24
Peak memory 191612 kb
Host smart-efae1bed-d02f-4dd7-bf89-d5ba12825e69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219472205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.219472205
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.1807056983
Short name T178
Test name
Test status
Simulation time 254428292700 ps
CPU time 893.85 seconds
Started Jul 20 04:33:23 PM PDT 24
Finished Jul 20 04:48:24 PM PDT 24
Peak memory 191632 kb
Host smart-61c9af2e-a323-4e09-a992-66d1b91c4674
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807056983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.1807056983
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.216768280
Short name T431
Test name
Test status
Simulation time 54681257706 ps
CPU time 28.79 seconds
Started Jul 20 04:32:43 PM PDT 24
Finished Jul 20 04:33:13 PM PDT 24
Peak memory 183384 kb
Host smart-48d1f043-3140-4de1-b27a-977c90fb1b22
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216768280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.rv_timer_cfg_update_on_fly.216768280
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/120.rv_timer_random.4198624633
Short name T256
Test name
Test status
Simulation time 83451197251 ps
CPU time 123.69 seconds
Started Jul 20 04:33:18 PM PDT 24
Finished Jul 20 04:35:27 PM PDT 24
Peak memory 191624 kb
Host smart-170b4320-cd20-46f5-8d87-389ed107809b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198624633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.4198624633
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.234213043
Short name T188
Test name
Test status
Simulation time 62065226657 ps
CPU time 874.09 seconds
Started Jul 20 04:33:16 PM PDT 24
Finished Jul 20 04:47:54 PM PDT 24
Peak memory 191636 kb
Host smart-5b16cb9d-7106-4f68-93ef-bd054ba4d668
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234213043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.234213043
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.1653914257
Short name T70
Test name
Test status
Simulation time 20056240100 ps
CPU time 32.1 seconds
Started Jul 20 04:33:21 PM PDT 24
Finished Jul 20 04:33:59 PM PDT 24
Peak memory 191688 kb
Host smart-bceb55c1-a692-45b4-8d38-b44905603f24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653914257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.1653914257
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/140.rv_timer_random.593969965
Short name T72
Test name
Test status
Simulation time 482932988713 ps
CPU time 469.98 seconds
Started Jul 20 04:33:19 PM PDT 24
Finished Jul 20 04:41:15 PM PDT 24
Peak memory 191636 kb
Host smart-89c058eb-bf49-4c6d-aac4-0657a2fadb45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593969965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.593969965
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.1180040859
Short name T239
Test name
Test status
Simulation time 94653332270 ps
CPU time 2400.3 seconds
Started Jul 20 04:33:19 PM PDT 24
Finished Jul 20 05:13:26 PM PDT 24
Peak memory 191560 kb
Host smart-5a36cbf1-d6b3-461c-9f83-d24ed7492c80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180040859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.1180040859
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.1347627107
Short name T271
Test name
Test status
Simulation time 521528447464 ps
CPU time 3398.31 seconds
Started Jul 20 04:33:17 PM PDT 24
Finished Jul 20 05:30:00 PM PDT 24
Peak memory 191480 kb
Host smart-5aa37987-dd94-4463-8c67-aa297a988f1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347627107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.1347627107
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.3675249867
Short name T151
Test name
Test status
Simulation time 118960009525 ps
CPU time 1036.78 seconds
Started Jul 20 04:33:16 PM PDT 24
Finished Jul 20 04:50:36 PM PDT 24
Peak memory 194416 kb
Host smart-dc7a4308-21f3-445d-837d-8f0cfa0d5f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675249867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.3675249867
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.1963339807
Short name T137
Test name
Test status
Simulation time 577379402911 ps
CPU time 851.51 seconds
Started Jul 20 04:33:40 PM PDT 24
Finished Jul 20 04:47:59 PM PDT 24
Peak memory 191908 kb
Host smart-2ae55182-1fd5-4f4f-933c-59ea27067b3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963339807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.1963339807
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.479263483
Short name T317
Test name
Test status
Simulation time 258616173047 ps
CPU time 449.45 seconds
Started Jul 20 04:32:58 PM PDT 24
Finished Jul 20 04:40:28 PM PDT 24
Peak memory 183720 kb
Host smart-ef5dda27-a4b6-4c90-bb1d-1c9a400f486c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479263483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.rv_timer_cfg_update_on_fly.479263483
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_random.190362358
Short name T202
Test name
Test status
Simulation time 346707411139 ps
CPU time 479.16 seconds
Started Jul 20 04:32:54 PM PDT 24
Finished Jul 20 04:40:54 PM PDT 24
Peak memory 191632 kb
Host smart-7f579067-e069-4260-888c-e6464b91aace
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190362358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.190362358
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.380254519
Short name T346
Test name
Test status
Simulation time 69348856473 ps
CPU time 57.14 seconds
Started Jul 20 04:33:27 PM PDT 24
Finished Jul 20 04:34:31 PM PDT 24
Peak memory 183360 kb
Host smart-bdcfa581-2ca8-43df-9638-1f61b134570f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380254519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.380254519
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.3619101127
Short name T112
Test name
Test status
Simulation time 88718145765 ps
CPU time 467.21 seconds
Started Jul 20 04:33:13 PM PDT 24
Finished Jul 20 04:41:02 PM PDT 24
Peak memory 191720 kb
Host smart-6e8cc7ab-a031-4a56-9ca1-0aea9c8590b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619101127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.3619101127
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.3260388709
Short name T223
Test name
Test status
Simulation time 149138250857 ps
CPU time 470.55 seconds
Started Jul 20 04:33:26 PM PDT 24
Finished Jul 20 04:41:24 PM PDT 24
Peak memory 193896 kb
Host smart-7d94d01b-2208-42c9-8a4b-c8f123a5d499
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260388709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.3260388709
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.2119062773
Short name T316
Test name
Test status
Simulation time 665098935755 ps
CPU time 1012.78 seconds
Started Jul 20 04:33:11 PM PDT 24
Finished Jul 20 04:50:05 PM PDT 24
Peak memory 183376 kb
Host smart-2420858c-3128-4283-b35c-9096db75f69b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119062773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.2119062773
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.1346388102
Short name T214
Test name
Test status
Simulation time 188111228891 ps
CPU time 215.65 seconds
Started Jul 20 04:33:03 PM PDT 24
Finished Jul 20 04:36:40 PM PDT 24
Peak memory 191564 kb
Host smart-3de7f473-fc6f-40e4-b9f8-192185219da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346388102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.1346388102
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.3485887620
Short name T141
Test name
Test status
Simulation time 464088214678 ps
CPU time 224 seconds
Started Jul 20 04:33:06 PM PDT 24
Finished Jul 20 04:36:51 PM PDT 24
Peak memory 196440 kb
Host smart-972cf424-7d22-41e4-b95f-e190e9ff0000
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485887620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.3485887620
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_random.2990691965
Short name T187
Test name
Test status
Simulation time 603154052736 ps
CPU time 456.44 seconds
Started Jul 20 04:33:18 PM PDT 24
Finished Jul 20 04:41:01 PM PDT 24
Peak memory 191640 kb
Host smart-76af6243-20af-4198-a285-3e7054e4d1ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990691965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.2990691965
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.3941532392
Short name T266
Test name
Test status
Simulation time 68529184575 ps
CPU time 40.73 seconds
Started Jul 20 04:33:09 PM PDT 24
Finished Jul 20 04:33:50 PM PDT 24
Peak memory 191652 kb
Host smart-5a3317ab-8d85-49f6-bcf4-f2b0e9b83210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941532392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.3941532392
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.456014438
Short name T172
Test name
Test status
Simulation time 1244712803694 ps
CPU time 667.3 seconds
Started Jul 20 04:33:06 PM PDT 24
Finished Jul 20 04:44:14 PM PDT 24
Peak memory 183436 kb
Host smart-0a212cee-74e8-455c-930f-981633e901c6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456014438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.rv_timer_cfg_update_on_fly.456014438
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/79.rv_timer_random.2499124356
Short name T355
Test name
Test status
Simulation time 590662985638 ps
CPU time 656.5 seconds
Started Jul 20 04:33:20 PM PDT 24
Finished Jul 20 04:44:22 PM PDT 24
Peak memory 191568 kb
Host smart-7575d05a-a0ce-456f-90d4-5c995540d3f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499124356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.2499124356
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.2840592133
Short name T240
Test name
Test status
Simulation time 809666853083 ps
CPU time 1807.27 seconds
Started Jul 20 04:32:46 PM PDT 24
Finished Jul 20 05:02:56 PM PDT 24
Peak memory 196488 kb
Host smart-00bc3ba8-4802-431b-b377-5eacd993e7bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840592133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
2840592133
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/99.rv_timer_random.2518055465
Short name T315
Test name
Test status
Simulation time 73114659200 ps
CPU time 292.64 seconds
Started Jul 20 04:33:25 PM PDT 24
Finished Jul 20 04:38:25 PM PDT 24
Peak memory 183360 kb
Host smart-750a99cd-70f5-448d-bbbe-b94589a16285
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518055465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.2518055465
Directory /workspace/99.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.892546779
Short name T474
Test name
Test status
Simulation time 55998087 ps
CPU time 0.78 seconds
Started Jul 20 04:32:39 PM PDT 24
Finished Jul 20 04:32:42 PM PDT 24
Peak memory 182400 kb
Host smart-25dfbdd8-5f6b-474b-9bbf-bec18266238f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892546779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alias
ing.892546779
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.2730860432
Short name T482
Test name
Test status
Simulation time 63494580 ps
CPU time 2.22 seconds
Started Jul 20 04:32:06 PM PDT 24
Finished Jul 20 04:32:11 PM PDT 24
Peak memory 182524 kb
Host smart-fe7fc74f-9ca1-4b78-bec4-374dc7a93f75
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730860432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.2730860432
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.4048405609
Short name T569
Test name
Test status
Simulation time 30871744 ps
CPU time 0.58 seconds
Started Jul 20 04:32:04 PM PDT 24
Finished Jul 20 04:32:07 PM PDT 24
Peak memory 182376 kb
Host smart-74b1c4f6-7977-45e5-9085-01eb24ee258b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048405609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.4048405609
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.3523089748
Short name T468
Test name
Test status
Simulation time 96667175 ps
CPU time 0.69 seconds
Started Jul 20 04:32:04 PM PDT 24
Finished Jul 20 04:32:07 PM PDT 24
Peak memory 193664 kb
Host smart-4989f0e0-9ac9-4ff4-9956-3d90e96c45e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523089748 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.3523089748
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.2025712806
Short name T575
Test name
Test status
Simulation time 15855278 ps
CPU time 0.6 seconds
Started Jul 20 04:32:04 PM PDT 24
Finished Jul 20 04:32:07 PM PDT 24
Peak memory 191628 kb
Host smart-6004bd6c-7bfe-4e41-b100-b8d8ea5f38c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025712806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.2025712806
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.2849980810
Short name T450
Test name
Test status
Simulation time 44780771 ps
CPU time 0.59 seconds
Started Jul 20 04:32:04 PM PDT 24
Finished Jul 20 04:32:07 PM PDT 24
Peak memory 182356 kb
Host smart-dafed38d-ad0f-4fdc-a0f3-82550c50dbc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849980810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.2849980810
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.2124912272
Short name T90
Test name
Test status
Simulation time 33165920 ps
CPU time 0.72 seconds
Started Jul 20 04:32:04 PM PDT 24
Finished Jul 20 04:32:08 PM PDT 24
Peak memory 193156 kb
Host smart-01f703c5-a26c-4b2f-b303-63bc258f67e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124912272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.2124912272
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.584557783
Short name T524
Test name
Test status
Simulation time 87174908 ps
CPU time 1.59 seconds
Started Jul 20 04:32:03 PM PDT 24
Finished Jul 20 04:32:08 PM PDT 24
Peak memory 197092 kb
Host smart-09dc1ca4-f1da-4342-968b-de2bdd917918
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584557783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.584557783
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.111536170
Short name T527
Test name
Test status
Simulation time 195700123 ps
CPU time 1.22 seconds
Started Jul 20 04:32:03 PM PDT 24
Finished Jul 20 04:32:08 PM PDT 24
Peak memory 194860 kb
Host smart-c1a934c8-6fcf-430c-8d6d-4abd8e73232d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111536170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_int
g_err.111536170
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.1143569922
Short name T105
Test name
Test status
Simulation time 113139175 ps
CPU time 0.62 seconds
Started Jul 20 04:32:00 PM PDT 24
Finished Jul 20 04:32:05 PM PDT 24
Peak memory 182304 kb
Host smart-4ea9f4d0-5601-4757-ad8f-7fab3ce54001
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143569922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.1143569922
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.1529859189
Short name T508
Test name
Test status
Simulation time 2901578002 ps
CPU time 3.54 seconds
Started Jul 20 04:32:02 PM PDT 24
Finished Jul 20 04:32:09 PM PDT 24
Peak memory 190772 kb
Host smart-ee59854b-dd6a-4428-8bc2-2933eb97ee31
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529859189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.1529859189
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1717477698
Short name T557
Test name
Test status
Simulation time 66377773 ps
CPU time 0.58 seconds
Started Jul 20 04:32:01 PM PDT 24
Finished Jul 20 04:32:05 PM PDT 24
Peak memory 182432 kb
Host smart-1e86e440-6f25-4a62-966c-9ff629b5ab6d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717477698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.1717477698
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.539457445
Short name T490
Test name
Test status
Simulation time 24211312 ps
CPU time 1.1 seconds
Started Jul 20 04:32:15 PM PDT 24
Finished Jul 20 04:32:17 PM PDT 24
Peak memory 197012 kb
Host smart-edd8970e-08ea-4270-86e1-80c13bb8d132
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539457445 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.539457445
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.3848584460
Short name T538
Test name
Test status
Simulation time 13728948 ps
CPU time 0.56 seconds
Started Jul 20 04:32:21 PM PDT 24
Finished Jul 20 04:32:23 PM PDT 24
Peak memory 182196 kb
Host smart-6eb5e94a-1101-4d83-9b8e-e3876cc8ccbc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848584460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.3848584460
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.248330776
Short name T560
Test name
Test status
Simulation time 17229618 ps
CPU time 0.59 seconds
Started Jul 20 04:32:04 PM PDT 24
Finished Jul 20 04:32:08 PM PDT 24
Peak memory 182328 kb
Host smart-c2a08aa2-4d54-40a5-a6b0-7b76ada1fc8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248330776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.248330776
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.4165383826
Short name T542
Test name
Test status
Simulation time 36767378 ps
CPU time 1.62 seconds
Started Jul 20 04:32:04 PM PDT 24
Finished Jul 20 04:32:08 PM PDT 24
Peak memory 197148 kb
Host smart-78fb5451-2a70-4339-98d1-77e835b8f793
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165383826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.4165383826
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.1433336339
Short name T488
Test name
Test status
Simulation time 207389659 ps
CPU time 1.33 seconds
Started Jul 20 04:32:06 PM PDT 24
Finished Jul 20 04:32:09 PM PDT 24
Peak memory 195180 kb
Host smart-c7529e3e-1bc5-4329-ba8c-e7b8cc5528ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433336339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.1433336339
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.3021190393
Short name T492
Test name
Test status
Simulation time 46183791 ps
CPU time 0.93 seconds
Started Jul 20 04:32:38 PM PDT 24
Finished Jul 20 04:32:42 PM PDT 24
Peak memory 197044 kb
Host smart-97d28ab0-b3e3-415b-be10-e6615f17bd43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021190393 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.3021190393
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.277304586
Short name T521
Test name
Test status
Simulation time 30933721 ps
CPU time 0.55 seconds
Started Jul 20 04:32:25 PM PDT 24
Finished Jul 20 04:32:28 PM PDT 24
Peak memory 181960 kb
Host smart-f0dbcbe2-e898-47a4-9cb0-7d8bcd7d9cf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277304586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.277304586
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.843244362
Short name T565
Test name
Test status
Simulation time 101682062 ps
CPU time 0.74 seconds
Started Jul 20 04:32:29 PM PDT 24
Finished Jul 20 04:32:32 PM PDT 24
Peak memory 193044 kb
Host smart-4ba82b63-2bde-4c31-8f81-7431350e19f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843244362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_ti
mer_same_csr_outstanding.843244362
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.30643775
Short name T511
Test name
Test status
Simulation time 117506721 ps
CPU time 2.59 seconds
Started Jul 20 04:32:23 PM PDT 24
Finished Jul 20 04:32:27 PM PDT 24
Peak memory 197196 kb
Host smart-ce27d6a3-4299-483c-9e16-6e00355303fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30643775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.30643775
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.448281113
Short name T500
Test name
Test status
Simulation time 140409210 ps
CPU time 1.03 seconds
Started Jul 20 04:32:28 PM PDT 24
Finished Jul 20 04:32:32 PM PDT 24
Peak memory 194956 kb
Host smart-7899c535-92f3-47ed-92d1-8abc402cfc99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448281113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_in
tg_err.448281113
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.4140237813
Short name T475
Test name
Test status
Simulation time 167006975 ps
CPU time 0.94 seconds
Started Jul 20 04:32:27 PM PDT 24
Finished Jul 20 04:32:31 PM PDT 24
Peak memory 196700 kb
Host smart-02b63aba-fb3f-40ab-9387-f63a2637c64f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140237813 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.4140237813
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.599683234
Short name T573
Test name
Test status
Simulation time 88467433 ps
CPU time 0.58 seconds
Started Jul 20 04:32:19 PM PDT 24
Finished Jul 20 04:32:20 PM PDT 24
Peak memory 182392 kb
Host smart-2c33dee4-dfe0-47ea-b059-c39c51ed9d2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599683234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.599683234
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.2549513295
Short name T581
Test name
Test status
Simulation time 14398329 ps
CPU time 0.59 seconds
Started Jul 20 04:32:26 PM PDT 24
Finished Jul 20 04:32:28 PM PDT 24
Peak memory 181760 kb
Host smart-66a36730-fca9-4eb0-9765-650c68067cbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549513295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.2549513295
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.4133101601
Short name T31
Test name
Test status
Simulation time 21334153 ps
CPU time 0.63 seconds
Started Jul 20 04:34:19 PM PDT 24
Finished Jul 20 04:34:20 PM PDT 24
Peak memory 191296 kb
Host smart-cb578417-93e1-4476-a300-08c22243df07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133101601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.4133101601
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.231013968
Short name T469
Test name
Test status
Simulation time 34308717 ps
CPU time 1.6 seconds
Started Jul 20 04:32:26 PM PDT 24
Finished Jul 20 04:32:31 PM PDT 24
Peak memory 195816 kb
Host smart-e1e51554-42ad-4f84-97f2-d9d66858a3cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231013968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.231013968
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.1849683658
Short name T108
Test name
Test status
Simulation time 407252536 ps
CPU time 1.34 seconds
Started Jul 20 04:32:17 PM PDT 24
Finished Jul 20 04:32:19 PM PDT 24
Peak memory 195036 kb
Host smart-a64e6543-fd14-4e6c-9522-a3b7cf6b0682
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849683658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.1849683658
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.1730805614
Short name T462
Test name
Test status
Simulation time 33619122 ps
CPU time 0.85 seconds
Started Jul 20 04:32:21 PM PDT 24
Finished Jul 20 04:32:23 PM PDT 24
Peak memory 195884 kb
Host smart-2eea4578-9467-4c7b-91b5-aa2a9646c08c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730805614 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.1730805614
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2693061863
Short name T100
Test name
Test status
Simulation time 14895827 ps
CPU time 0.58 seconds
Started Jul 20 04:32:29 PM PDT 24
Finished Jul 20 04:32:32 PM PDT 24
Peak memory 182392 kb
Host smart-7216f368-5bf4-4176-86a6-75ebbc8a6c1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693061863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.2693061863
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.2396374388
Short name T517
Test name
Test status
Simulation time 12071068 ps
CPU time 0.53 seconds
Started Jul 20 04:32:27 PM PDT 24
Finished Jul 20 04:32:30 PM PDT 24
Peak memory 181908 kb
Host smart-1f95650c-0c98-4d38-bdf7-c402410f013a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396374388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.2396374388
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1120691572
Short name T530
Test name
Test status
Simulation time 55935637 ps
CPU time 0.72 seconds
Started Jul 20 04:32:28 PM PDT 24
Finished Jul 20 04:32:31 PM PDT 24
Peak memory 191372 kb
Host smart-d5bf2511-8d1b-47ab-9ea4-0f553abe44be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120691572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.1120691572
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.1858543154
Short name T532
Test name
Test status
Simulation time 33822685 ps
CPU time 1.16 seconds
Started Jul 20 04:32:28 PM PDT 24
Finished Jul 20 04:32:38 PM PDT 24
Peak memory 197080 kb
Host smart-9af9ee5c-dfef-4b69-ad8f-a4a1ec74eb0a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858543154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.1858543154
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.3904195326
Short name T491
Test name
Test status
Simulation time 159660423 ps
CPU time 1.06 seconds
Started Jul 20 04:32:24 PM PDT 24
Finished Jul 20 04:32:27 PM PDT 24
Peak memory 194684 kb
Host smart-854966fd-80b0-48f0-b66f-e33ad039b6bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904195326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.3904195326
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.106144582
Short name T52
Test name
Test status
Simulation time 32872233 ps
CPU time 0.76 seconds
Started Jul 20 04:32:27 PM PDT 24
Finished Jul 20 04:32:31 PM PDT 24
Peak memory 195056 kb
Host smart-760b8585-1f97-4138-9396-584dddf2207b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106144582 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.106144582
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.867300216
Short name T579
Test name
Test status
Simulation time 31119661 ps
CPU time 0.57 seconds
Started Jul 20 04:32:26 PM PDT 24
Finished Jul 20 04:32:28 PM PDT 24
Peak memory 182372 kb
Host smart-ce6ce5da-8c58-4429-b703-e6b8dda42a2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867300216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.867300216
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3843657558
Short name T449
Test name
Test status
Simulation time 45864546 ps
CPU time 0.57 seconds
Started Jul 20 04:32:25 PM PDT 24
Finished Jul 20 04:32:28 PM PDT 24
Peak memory 182300 kb
Host smart-41d58e70-3005-4a4a-8d79-fd941f835e64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843657558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.3843657558
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1051315762
Short name T514
Test name
Test status
Simulation time 103936749 ps
CPU time 0.73 seconds
Started Jul 20 04:34:23 PM PDT 24
Finished Jul 20 04:34:25 PM PDT 24
Peak memory 191320 kb
Host smart-f3cefdc5-fdf0-4389-bd77-d74b4ab1e220
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051315762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.1051315762
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.2106403178
Short name T477
Test name
Test status
Simulation time 90135866 ps
CPU time 1.58 seconds
Started Jul 20 04:32:24 PM PDT 24
Finished Jul 20 04:32:27 PM PDT 24
Peak memory 197168 kb
Host smart-a30c5a52-7cef-44ce-8e8a-544715f7c610
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106403178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.2106403178
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1672037925
Short name T106
Test name
Test status
Simulation time 181820622 ps
CPU time 1.27 seconds
Started Jul 20 04:32:31 PM PDT 24
Finished Jul 20 04:32:36 PM PDT 24
Peak memory 182808 kb
Host smart-7965b4f5-37f7-4d27-adb6-86bc33fe9d38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672037925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.1672037925
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.2619890446
Short name T465
Test name
Test status
Simulation time 34337790 ps
CPU time 0.86 seconds
Started Jul 20 04:32:25 PM PDT 24
Finished Jul 20 04:32:28 PM PDT 24
Peak memory 196336 kb
Host smart-97a9241e-cc76-4f1a-973a-a5063ab8de39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619890446 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.2619890446
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3598429866
Short name T94
Test name
Test status
Simulation time 21066977 ps
CPU time 0.58 seconds
Started Jul 20 04:32:31 PM PDT 24
Finished Jul 20 04:32:35 PM PDT 24
Peak memory 182444 kb
Host smart-24dc40d9-972c-4a30-9061-522e05d49e50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598429866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.3598429866
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.458837920
Short name T531
Test name
Test status
Simulation time 31985056 ps
CPU time 0.53 seconds
Started Jul 20 04:34:20 PM PDT 24
Finished Jul 20 04:34:21 PM PDT 24
Peak memory 181896 kb
Host smart-6f1d512f-8856-431b-807c-daa52dd05f16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458837920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.458837920
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.4272975972
Short name T101
Test name
Test status
Simulation time 20143534 ps
CPU time 0.68 seconds
Started Jul 20 04:32:37 PM PDT 24
Finished Jul 20 04:32:40 PM PDT 24
Peak memory 191380 kb
Host smart-e9c92937-b978-4f6b-96d0-547f792f2a1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272975972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.4272975972
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2613727246
Short name T457
Test name
Test status
Simulation time 156205618 ps
CPU time 2.09 seconds
Started Jul 20 04:32:23 PM PDT 24
Finished Jul 20 04:32:26 PM PDT 24
Peak memory 197152 kb
Host smart-344f34c4-ea38-41cf-86b3-af0346d9b6b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613727246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.2613727246
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.674242206
Short name T107
Test name
Test status
Simulation time 81099004 ps
CPU time 1.08 seconds
Started Jul 20 04:32:26 PM PDT 24
Finished Jul 20 04:32:30 PM PDT 24
Peak memory 193784 kb
Host smart-b40f8c82-9c0f-4e2b-bb15-a99271edf0ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674242206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_in
tg_err.674242206
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1267819504
Short name T499
Test name
Test status
Simulation time 109499319 ps
CPU time 0.76 seconds
Started Jul 20 04:32:28 PM PDT 24
Finished Jul 20 04:32:32 PM PDT 24
Peak memory 194880 kb
Host smart-3c10bedf-a3a0-42a6-871f-9ca30c59da50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267819504 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.1267819504
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.3538309890
Short name T88
Test name
Test status
Simulation time 14106863 ps
CPU time 0.54 seconds
Started Jul 20 04:32:18 PM PDT 24
Finished Jul 20 04:32:19 PM PDT 24
Peak memory 182432 kb
Host smart-fd328e32-a206-4319-9c63-be15c2de8cc4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538309890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.3538309890
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.1040293159
Short name T451
Test name
Test status
Simulation time 102743783 ps
CPU time 0.52 seconds
Started Jul 20 04:32:26 PM PDT 24
Finished Jul 20 04:32:28 PM PDT 24
Peak memory 181800 kb
Host smart-2f327efc-5e96-40b7-91b5-1150c1633b56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040293159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.1040293159
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.2675125502
Short name T104
Test name
Test status
Simulation time 81526127 ps
CPU time 0.78 seconds
Started Jul 20 04:32:29 PM PDT 24
Finished Jul 20 04:32:32 PM PDT 24
Peak memory 191320 kb
Host smart-0cfeef67-6ac9-4dae-8e77-f020d52adea7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675125502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.2675125502
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.3814542242
Short name T458
Test name
Test status
Simulation time 298991605 ps
CPU time 2.62 seconds
Started Jul 20 04:32:24 PM PDT 24
Finished Jul 20 04:32:28 PM PDT 24
Peak memory 197116 kb
Host smart-8bf6b4b3-07e3-4e11-84c9-fdb60baf3192
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814542242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.3814542242
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.2660594223
Short name T578
Test name
Test status
Simulation time 85762023 ps
CPU time 0.82 seconds
Started Jul 20 04:32:25 PM PDT 24
Finished Jul 20 04:32:27 PM PDT 24
Peak memory 182796 kb
Host smart-e9725cb5-4904-48ea-9019-aeae9a2d6648
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660594223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.2660594223
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.334031631
Short name T546
Test name
Test status
Simulation time 137493896 ps
CPU time 0.98 seconds
Started Jul 20 04:32:32 PM PDT 24
Finished Jul 20 04:32:36 PM PDT 24
Peak memory 197068 kb
Host smart-ea97c8b8-1a63-4292-908e-a5566aaf96d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334031631 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.334031631
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.2187497936
Short name T92
Test name
Test status
Simulation time 40971400 ps
CPU time 0.55 seconds
Started Jul 20 04:32:40 PM PDT 24
Finished Jul 20 04:32:43 PM PDT 24
Peak memory 182428 kb
Host smart-2bfacba7-a202-463a-b6b4-6ec4c74a7e9a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187497936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.2187497936
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.4037710529
Short name T543
Test name
Test status
Simulation time 48719692 ps
CPU time 0.55 seconds
Started Jul 20 04:32:44 PM PDT 24
Finished Jul 20 04:32:47 PM PDT 24
Peak memory 182180 kb
Host smart-6b953dc0-9289-4ae5-b440-2734fc01ad0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037710529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.4037710529
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1803437084
Short name T496
Test name
Test status
Simulation time 44598588 ps
CPU time 0.68 seconds
Started Jul 20 04:32:27 PM PDT 24
Finished Jul 20 04:32:31 PM PDT 24
Peak memory 191400 kb
Host smart-57f2a53f-6b1c-41c6-8194-681fc875c9fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803437084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.1803437084
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.240813853
Short name T65
Test name
Test status
Simulation time 72688819 ps
CPU time 1.58 seconds
Started Jul 20 04:32:29 PM PDT 24
Finished Jul 20 04:32:33 PM PDT 24
Peak memory 197048 kb
Host smart-c8e94e2b-91aa-456b-a064-514f45f77f30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240813853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.240813853
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.798172593
Short name T30
Test name
Test status
Simulation time 45843058 ps
CPU time 0.81 seconds
Started Jul 20 04:32:34 PM PDT 24
Finished Jul 20 04:32:38 PM PDT 24
Peak memory 193552 kb
Host smart-8df1ab0e-f374-4096-8615-77ed9f779b1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798172593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_in
tg_err.798172593
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.1501234174
Short name T553
Test name
Test status
Simulation time 25548966 ps
CPU time 1.08 seconds
Started Jul 20 04:32:31 PM PDT 24
Finished Jul 20 04:32:36 PM PDT 24
Peak memory 197060 kb
Host smart-6b1ee8cc-2d70-437a-94b8-4503c3d0826c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501234174 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.1501234174
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.2368300216
Short name T95
Test name
Test status
Simulation time 14621381 ps
CPU time 0.55 seconds
Started Jul 20 04:32:37 PM PDT 24
Finished Jul 20 04:32:40 PM PDT 24
Peak memory 182204 kb
Host smart-6a58a163-28bf-40f0-b9b3-fbdc97943118
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368300216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.2368300216
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1194457697
Short name T580
Test name
Test status
Simulation time 39155312 ps
CPU time 0.53 seconds
Started Jul 20 04:32:32 PM PDT 24
Finished Jul 20 04:32:36 PM PDT 24
Peak memory 181712 kb
Host smart-a035546b-1f2e-4950-8da9-6ae110261df4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194457697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.1194457697
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.1818955740
Short name T503
Test name
Test status
Simulation time 75004874 ps
CPU time 0.71 seconds
Started Jul 20 04:32:40 PM PDT 24
Finished Jul 20 04:32:43 PM PDT 24
Peak memory 192824 kb
Host smart-7d3b04a9-32d9-4544-8074-b6f05392b5a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818955740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.1818955740
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.3385343003
Short name T453
Test name
Test status
Simulation time 97174779 ps
CPU time 2.44 seconds
Started Jul 20 04:32:48 PM PDT 24
Finished Jul 20 04:32:51 PM PDT 24
Peak memory 197112 kb
Host smart-3627948e-fb9e-4e46-a53e-42745bc86bd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385343003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.3385343003
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3170248380
Short name T540
Test name
Test status
Simulation time 78330146 ps
CPU time 0.81 seconds
Started Jul 20 04:32:42 PM PDT 24
Finished Jul 20 04:32:44 PM PDT 24
Peak memory 193240 kb
Host smart-b366ce00-f8ec-4141-bbd5-fcaef5be0365
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170248380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.3170248380
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.1155054103
Short name T513
Test name
Test status
Simulation time 102154586 ps
CPU time 0.8 seconds
Started Jul 20 04:32:50 PM PDT 24
Finished Jul 20 04:32:51 PM PDT 24
Peak memory 195784 kb
Host smart-f15afe16-fe9a-48cc-b010-66806e74824d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155054103 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.1155054103
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.1303460079
Short name T522
Test name
Test status
Simulation time 15520641 ps
CPU time 0.58 seconds
Started Jul 20 04:32:44 PM PDT 24
Finished Jul 20 04:32:46 PM PDT 24
Peak memory 182360 kb
Host smart-03af9cad-2d61-4373-b429-5ed5b60bfc04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303460079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.1303460079
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.15051714
Short name T467
Test name
Test status
Simulation time 36333855 ps
CPU time 0.57 seconds
Started Jul 20 04:32:33 PM PDT 24
Finished Jul 20 04:32:37 PM PDT 24
Peak memory 181808 kb
Host smart-2bb0a6b3-e849-486f-8818-257728e1edcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15051714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.15051714
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.2375722545
Short name T501
Test name
Test status
Simulation time 91623652 ps
CPU time 0.71 seconds
Started Jul 20 04:32:43 PM PDT 24
Finished Jul 20 04:32:45 PM PDT 24
Peak memory 193032 kb
Host smart-30e027d0-41f9-4a04-9d86-d2780173c06f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375722545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.2375722545
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3514689936
Short name T555
Test name
Test status
Simulation time 91785242 ps
CPU time 1 seconds
Started Jul 20 04:32:43 PM PDT 24
Finished Jul 20 04:32:45 PM PDT 24
Peak memory 196444 kb
Host smart-9ff6a3ff-3944-4b73-bebb-a6daaf2916a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514689936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.3514689936
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.313383235
Short name T541
Test name
Test status
Simulation time 23397873 ps
CPU time 0.68 seconds
Started Jul 20 04:32:44 PM PDT 24
Finished Jul 20 04:32:46 PM PDT 24
Peak memory 194460 kb
Host smart-7d7c5392-823d-4224-ab0e-7971b74ce807
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313383235 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.313383235
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.1186816553
Short name T461
Test name
Test status
Simulation time 21831622 ps
CPU time 0.58 seconds
Started Jul 20 04:32:35 PM PDT 24
Finished Jul 20 04:32:41 PM PDT 24
Peak memory 182432 kb
Host smart-696f5eaf-d4d3-4146-b393-c42982db45df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186816553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.1186816553
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.891608357
Short name T577
Test name
Test status
Simulation time 16927162 ps
CPU time 0.64 seconds
Started Jul 20 04:32:32 PM PDT 24
Finished Jul 20 04:32:36 PM PDT 24
Peak memory 182256 kb
Host smart-ad201bb2-875c-459d-b362-801e2ae5975d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891608357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.891608357
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.1688606193
Short name T103
Test name
Test status
Simulation time 30388042 ps
CPU time 0.73 seconds
Started Jul 20 04:32:38 PM PDT 24
Finished Jul 20 04:32:42 PM PDT 24
Peak memory 192996 kb
Host smart-47292755-b939-44e7-a7fd-820ae1235616
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688606193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.1688606193
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.1777901121
Short name T568
Test name
Test status
Simulation time 202725322 ps
CPU time 2.43 seconds
Started Jul 20 04:32:39 PM PDT 24
Finished Jul 20 04:32:44 PM PDT 24
Peak memory 197120 kb
Host smart-ffdfa53c-fe7c-430c-ba3c-d43f160a03c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777901121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.1777901121
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.554056375
Short name T493
Test name
Test status
Simulation time 65945275 ps
CPU time 1.06 seconds
Started Jul 20 04:32:32 PM PDT 24
Finished Jul 20 04:32:36 PM PDT 24
Peak memory 182860 kb
Host smart-472d2a65-f394-4f1f-a9a6-99d257e3c544
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554056375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_in
tg_err.554056375
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.533345318
Short name T512
Test name
Test status
Simulation time 17113907 ps
CPU time 0.7 seconds
Started Jul 20 04:32:09 PM PDT 24
Finished Jul 20 04:32:11 PM PDT 24
Peak memory 192000 kb
Host smart-952a7077-7fd8-4caf-a2ff-8caf9d4f2ef1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533345318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alias
ing.533345318
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.4117255712
Short name T544
Test name
Test status
Simulation time 1695904809 ps
CPU time 3.6 seconds
Started Jul 20 04:32:10 PM PDT 24
Finished Jul 20 04:32:15 PM PDT 24
Peak memory 193600 kb
Host smart-95bbcc57-798c-49de-9faf-e46d49338424
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117255712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.4117255712
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.652478300
Short name T485
Test name
Test status
Simulation time 26001134 ps
CPU time 0.55 seconds
Started Jul 20 04:32:14 PM PDT 24
Finished Jul 20 04:32:15 PM PDT 24
Peak memory 181900 kb
Host smart-414a4152-f9fa-4e80-90cd-7d6eec73e23a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652478300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_re
set.652478300
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.1642290777
Short name T455
Test name
Test status
Simulation time 17317820 ps
CPU time 0.8 seconds
Started Jul 20 04:32:11 PM PDT 24
Finished Jul 20 04:32:12 PM PDT 24
Peak memory 195116 kb
Host smart-a2b90598-6553-4247-b0cc-2ff9204d702f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642290777 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.1642290777
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.1924425320
Short name T572
Test name
Test status
Simulation time 33539871 ps
CPU time 0.54 seconds
Started Jul 20 04:32:09 PM PDT 24
Finished Jul 20 04:32:10 PM PDT 24
Peak memory 182440 kb
Host smart-b667937e-5fab-419d-bfe1-0e2e2fb63e8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924425320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.1924425320
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.2872408401
Short name T481
Test name
Test status
Simulation time 56372907 ps
CPU time 0.55 seconds
Started Jul 20 04:32:10 PM PDT 24
Finished Jul 20 04:32:16 PM PDT 24
Peak memory 182304 kb
Host smart-cb2b704e-ccb2-4acd-9151-fbd53986e7b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872408401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.2872408401
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.2548411576
Short name T548
Test name
Test status
Simulation time 48246449 ps
CPU time 0.66 seconds
Started Jul 20 04:32:10 PM PDT 24
Finished Jul 20 04:32:11 PM PDT 24
Peak memory 191740 kb
Host smart-78739d45-e628-424e-8cc7-89881d61624b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548411576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.2548411576
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.2612048342
Short name T520
Test name
Test status
Simulation time 48948288 ps
CPU time 1.2 seconds
Started Jul 20 04:32:19 PM PDT 24
Finished Jul 20 04:32:21 PM PDT 24
Peak memory 197112 kb
Host smart-0d1afb86-2658-4a8d-9121-118264d33701
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612048342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.2612048342
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2386656919
Short name T554
Test name
Test status
Simulation time 237628385 ps
CPU time 1.06 seconds
Started Jul 20 04:32:14 PM PDT 24
Finished Jul 20 04:32:16 PM PDT 24
Peak memory 194684 kb
Host smart-c2e049e5-f0dc-4fad-9ffa-5e28255f980f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386656919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.2386656919
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.902878116
Short name T518
Test name
Test status
Simulation time 24742514 ps
CPU time 0.58 seconds
Started Jul 20 04:32:41 PM PDT 24
Finished Jul 20 04:32:44 PM PDT 24
Peak memory 182336 kb
Host smart-9fc84b9c-30a6-4441-a1b0-a76c3d9e4e44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902878116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.902878116
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.493687271
Short name T552
Test name
Test status
Simulation time 12162937 ps
CPU time 0.59 seconds
Started Jul 20 04:32:33 PM PDT 24
Finished Jul 20 04:32:37 PM PDT 24
Peak memory 181852 kb
Host smart-24386ba0-3f0c-4e9a-b9c7-a1e89d465ae3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493687271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.493687271
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.3596799178
Short name T526
Test name
Test status
Simulation time 12776795 ps
CPU time 0.54 seconds
Started Jul 20 04:32:27 PM PDT 24
Finished Jul 20 04:32:31 PM PDT 24
Peak memory 181732 kb
Host smart-a6962234-2d4e-4a4c-88c8-1b8d6b16045b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596799178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.3596799178
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.119182970
Short name T562
Test name
Test status
Simulation time 12788790 ps
CPU time 0.55 seconds
Started Jul 20 04:32:36 PM PDT 24
Finished Jul 20 04:32:39 PM PDT 24
Peak memory 182340 kb
Host smart-37b2ee5e-34e6-4d85-82d5-5fb044443af7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119182970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.119182970
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.1494386387
Short name T533
Test name
Test status
Simulation time 22309942 ps
CPU time 0.59 seconds
Started Jul 20 04:32:33 PM PDT 24
Finished Jul 20 04:32:37 PM PDT 24
Peak memory 182404 kb
Host smart-1508193d-fa03-45e9-a44b-a808468e36e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494386387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.1494386387
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.1284577181
Short name T537
Test name
Test status
Simulation time 14216183 ps
CPU time 0.53 seconds
Started Jul 20 04:32:30 PM PDT 24
Finished Jul 20 04:32:34 PM PDT 24
Peak memory 181728 kb
Host smart-20f36eff-29f2-45c0-87e1-3e0179fcd87c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284577181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.1284577181
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.2390584540
Short name T525
Test name
Test status
Simulation time 12269936 ps
CPU time 0.54 seconds
Started Jul 20 04:32:31 PM PDT 24
Finished Jul 20 04:32:35 PM PDT 24
Peak memory 182296 kb
Host smart-730e1168-5bac-49d3-8518-689fa8da8234
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390584540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.2390584540
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.2917167169
Short name T472
Test name
Test status
Simulation time 22811784 ps
CPU time 0.52 seconds
Started Jul 20 04:32:49 PM PDT 24
Finished Jul 20 04:32:50 PM PDT 24
Peak memory 182004 kb
Host smart-af7d876f-efeb-47d3-9112-2bb2ec7521af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917167169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.2917167169
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1773598842
Short name T550
Test name
Test status
Simulation time 51604751 ps
CPU time 0.56 seconds
Started Jul 20 04:32:46 PM PDT 24
Finished Jul 20 04:32:49 PM PDT 24
Peak memory 182344 kb
Host smart-fac8bc75-8d06-4624-ade7-d9f7cb2cc075
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773598842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.1773598842
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.3810143538
Short name T473
Test name
Test status
Simulation time 15631594 ps
CPU time 0.52 seconds
Started Jul 20 04:32:41 PM PDT 24
Finished Jul 20 04:32:44 PM PDT 24
Peak memory 181800 kb
Host smart-1a4d1972-6f63-4942-a934-b069538e7761
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810143538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.3810143538
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.341606352
Short name T97
Test name
Test status
Simulation time 15153882 ps
CPU time 0.64 seconds
Started Jul 20 04:32:07 PM PDT 24
Finished Jul 20 04:32:09 PM PDT 24
Peak memory 191656 kb
Host smart-ccbda273-54fb-4324-a23f-ec5a87cdcf2e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341606352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alias
ing.341606352
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.1142358160
Short name T549
Test name
Test status
Simulation time 1638228527 ps
CPU time 3.91 seconds
Started Jul 20 04:32:08 PM PDT 24
Finished Jul 20 04:32:13 PM PDT 24
Peak memory 193620 kb
Host smart-60a0e870-4906-485f-b684-bea67d47cc4e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142358160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.1142358160
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3999183519
Short name T99
Test name
Test status
Simulation time 31189161 ps
CPU time 0.58 seconds
Started Jul 20 04:32:30 PM PDT 24
Finished Jul 20 04:32:34 PM PDT 24
Peak memory 182376 kb
Host smart-5091972e-1b95-44f9-8350-e5ed4291cfd6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999183519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.3999183519
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.944881238
Short name T470
Test name
Test status
Simulation time 132096391 ps
CPU time 0.8 seconds
Started Jul 20 04:32:09 PM PDT 24
Finished Jul 20 04:32:11 PM PDT 24
Peak memory 195156 kb
Host smart-96e5b5ac-eb9e-4515-9480-d80272a03628
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944881238 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.944881238
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.348458404
Short name T536
Test name
Test status
Simulation time 54904503 ps
CPU time 0.57 seconds
Started Jul 20 04:32:07 PM PDT 24
Finished Jul 20 04:32:09 PM PDT 24
Peak memory 182440 kb
Host smart-1e691140-a25f-458a-b1d0-e8bb8b143461
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348458404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.348458404
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.2867507404
Short name T505
Test name
Test status
Simulation time 20881323 ps
CPU time 0.56 seconds
Started Jul 20 04:32:14 PM PDT 24
Finished Jul 20 04:32:15 PM PDT 24
Peak memory 182212 kb
Host smart-e3710d5a-2af4-44d2-86d5-822781f38bca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867507404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.2867507404
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.2427475697
Short name T91
Test name
Test status
Simulation time 13637396 ps
CPU time 0.68 seconds
Started Jul 20 04:32:07 PM PDT 24
Finished Jul 20 04:32:10 PM PDT 24
Peak memory 191800 kb
Host smart-99c8708f-acc6-4f85-8921-d5684f07523f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427475697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.2427475697
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.535924370
Short name T545
Test name
Test status
Simulation time 31927180 ps
CPU time 1.63 seconds
Started Jul 20 04:32:11 PM PDT 24
Finished Jul 20 04:32:13 PM PDT 24
Peak memory 197084 kb
Host smart-a83ad520-3b35-4750-a702-58f6b6575f2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535924370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.535924370
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.2323582207
Short name T504
Test name
Test status
Simulation time 187879466 ps
CPU time 1.08 seconds
Started Jul 20 04:32:21 PM PDT 24
Finished Jul 20 04:32:23 PM PDT 24
Peak memory 194520 kb
Host smart-835edb72-6012-46bb-931c-6de5e2f0df47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323582207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.2323582207
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.2723174511
Short name T571
Test name
Test status
Simulation time 46671739 ps
CPU time 0.55 seconds
Started Jul 20 04:32:36 PM PDT 24
Finished Jul 20 04:32:39 PM PDT 24
Peak memory 182264 kb
Host smart-9b5e7b04-4899-466d-9efd-516e5a818a20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723174511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.2723174511
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.1659439909
Short name T486
Test name
Test status
Simulation time 14676815 ps
CPU time 0.59 seconds
Started Jul 20 04:32:42 PM PDT 24
Finished Jul 20 04:32:45 PM PDT 24
Peak memory 182260 kb
Host smart-c6dd5577-4155-4682-9531-6b1bc651e84b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659439909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.1659439909
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.1315807063
Short name T556
Test name
Test status
Simulation time 23279152 ps
CPU time 0.54 seconds
Started Jul 20 04:32:36 PM PDT 24
Finished Jul 20 04:32:39 PM PDT 24
Peak memory 181800 kb
Host smart-9fd9cca3-26eb-489f-84d4-80eb10939398
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315807063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.1315807063
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1488078788
Short name T519
Test name
Test status
Simulation time 70327355 ps
CPU time 0.57 seconds
Started Jul 20 04:32:36 PM PDT 24
Finished Jul 20 04:32:39 PM PDT 24
Peak memory 182256 kb
Host smart-51a11987-265f-481a-b073-d9cf74a40fe6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488078788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.1488078788
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.1164705100
Short name T459
Test name
Test status
Simulation time 96504769 ps
CPU time 0.54 seconds
Started Jul 20 04:32:28 PM PDT 24
Finished Jul 20 04:32:31 PM PDT 24
Peak memory 182324 kb
Host smart-4bd70972-a6bb-4df8-87fc-f43006728aa2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164705100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.1164705100
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.4208267843
Short name T574
Test name
Test status
Simulation time 42520178 ps
CPU time 0.54 seconds
Started Jul 20 04:32:45 PM PDT 24
Finished Jul 20 04:32:47 PM PDT 24
Peak memory 182304 kb
Host smart-93e08ad0-d54d-4d0d-beea-eb281ea72e1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208267843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.4208267843
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.1467051766
Short name T563
Test name
Test status
Simulation time 70419909 ps
CPU time 0.6 seconds
Started Jul 20 04:32:36 PM PDT 24
Finished Jul 20 04:32:39 PM PDT 24
Peak memory 182284 kb
Host smart-532a2648-d8f4-4578-9251-69dbfc50ae7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467051766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.1467051766
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.914677298
Short name T487
Test name
Test status
Simulation time 60319667 ps
CPU time 0.57 seconds
Started Jul 20 04:32:55 PM PDT 24
Finished Jul 20 04:32:56 PM PDT 24
Peak memory 182316 kb
Host smart-189bb764-aea6-4ea1-839d-d06e4df4cbd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914677298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.914677298
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.3905438290
Short name T460
Test name
Test status
Simulation time 35789233 ps
CPU time 0.52 seconds
Started Jul 20 04:32:39 PM PDT 24
Finished Jul 20 04:32:42 PM PDT 24
Peak memory 181768 kb
Host smart-4dcf809e-2bb8-4f21-8fb9-4003236dc760
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905438290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.3905438290
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.2949542234
Short name T456
Test name
Test status
Simulation time 22613135 ps
CPU time 0.52 seconds
Started Jul 20 04:32:28 PM PDT 24
Finished Jul 20 04:32:41 PM PDT 24
Peak memory 181948 kb
Host smart-f4515920-dca5-4b25-89e0-31f8e930c030
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949542234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.2949542234
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.3799410135
Short name T529
Test name
Test status
Simulation time 15815693 ps
CPU time 0.66 seconds
Started Jul 20 04:32:08 PM PDT 24
Finished Jul 20 04:32:10 PM PDT 24
Peak memory 192068 kb
Host smart-a16a6eb6-2bc8-4387-bcb2-5ce46b9f3ec1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799410135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.3799410135
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.1351280070
Short name T54
Test name
Test status
Simulation time 588428584 ps
CPU time 1.59 seconds
Started Jul 20 04:32:07 PM PDT 24
Finished Jul 20 04:32:10 PM PDT 24
Peak memory 190660 kb
Host smart-14f8c5b4-52f0-435c-8195-3e978e5dcbcd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351280070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.1351280070
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.401418648
Short name T509
Test name
Test status
Simulation time 63604688 ps
CPU time 0.57 seconds
Started Jul 20 04:32:32 PM PDT 24
Finished Jul 20 04:32:36 PM PDT 24
Peak memory 182416 kb
Host smart-d08b226d-ee87-4460-ab6e-dda265548877
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401418648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_re
set.401418648
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.1908320243
Short name T478
Test name
Test status
Simulation time 28932858 ps
CPU time 0.63 seconds
Started Jul 20 04:32:25 PM PDT 24
Finished Jul 20 04:32:28 PM PDT 24
Peak memory 192804 kb
Host smart-6d6e0690-6a60-42a7-a032-0ad1d09d83e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908320243 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.1908320243
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2301451986
Short name T98
Test name
Test status
Simulation time 27347557 ps
CPU time 0.6 seconds
Started Jul 20 04:32:10 PM PDT 24
Finished Jul 20 04:32:12 PM PDT 24
Peak memory 182444 kb
Host smart-cb109dd7-5b65-4971-9aa9-41399a12048e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301451986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.2301451986
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.2363965316
Short name T535
Test name
Test status
Simulation time 98352209 ps
CPU time 0.52 seconds
Started Jul 20 04:32:10 PM PDT 24
Finished Jul 20 04:32:12 PM PDT 24
Peak memory 181804 kb
Host smart-c90a7031-c776-4591-808b-158143e385ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363965316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.2363965316
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.667604007
Short name T102
Test name
Test status
Simulation time 29500383 ps
CPU time 0.66 seconds
Started Jul 20 04:32:07 PM PDT 24
Finished Jul 20 04:32:09 PM PDT 24
Peak memory 191328 kb
Host smart-2c513829-3618-42a4-bce6-8c4b4a38498a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667604007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_tim
er_same_csr_outstanding.667604007
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1471188110
Short name T515
Test name
Test status
Simulation time 168339146 ps
CPU time 3.17 seconds
Started Jul 20 04:32:10 PM PDT 24
Finished Jul 20 04:32:14 PM PDT 24
Peak memory 196964 kb
Host smart-570dfd66-822f-4dc8-b477-9b09d981e09e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471188110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.1471188110
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.1943255428
Short name T480
Test name
Test status
Simulation time 331469085 ps
CPU time 0.78 seconds
Started Jul 20 04:32:13 PM PDT 24
Finished Jul 20 04:32:14 PM PDT 24
Peak memory 192996 kb
Host smart-05e28b6e-993d-4595-a7b9-2f709e09cf4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943255428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.1943255428
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.2253246034
Short name T534
Test name
Test status
Simulation time 35164771 ps
CPU time 0.58 seconds
Started Jul 20 04:32:38 PM PDT 24
Finished Jul 20 04:32:41 PM PDT 24
Peak memory 182600 kb
Host smart-85e34b4f-8648-4974-a32a-c1833e40c6ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253246034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.2253246034
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.1419698938
Short name T463
Test name
Test status
Simulation time 38480888 ps
CPU time 0.52 seconds
Started Jul 20 04:32:42 PM PDT 24
Finished Jul 20 04:32:44 PM PDT 24
Peak memory 181772 kb
Host smart-253af27b-6659-411c-9e37-b620865a9e32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419698938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.1419698938
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1895731319
Short name T464
Test name
Test status
Simulation time 15162545 ps
CPU time 0.61 seconds
Started Jul 20 04:32:34 PM PDT 24
Finished Jul 20 04:32:38 PM PDT 24
Peak memory 182352 kb
Host smart-5b9c3b2b-5ee8-4de2-bb7b-732e5bdc6e72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895731319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.1895731319
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.3692156596
Short name T502
Test name
Test status
Simulation time 69381867 ps
CPU time 0.53 seconds
Started Jul 20 04:32:29 PM PDT 24
Finished Jul 20 04:32:32 PM PDT 24
Peak memory 182264 kb
Host smart-00b2a8da-8f99-411d-b95e-2d64be351f23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692156596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.3692156596
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.1758377774
Short name T483
Test name
Test status
Simulation time 72637726 ps
CPU time 0.52 seconds
Started Jul 20 04:32:33 PM PDT 24
Finished Jul 20 04:32:37 PM PDT 24
Peak memory 181752 kb
Host smart-8c082242-a96e-4261-8f7d-011bd99f81cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758377774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.1758377774
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1496412121
Short name T479
Test name
Test status
Simulation time 12794525 ps
CPU time 0.52 seconds
Started Jul 20 04:32:30 PM PDT 24
Finished Jul 20 04:32:33 PM PDT 24
Peak memory 181640 kb
Host smart-240a4c08-f379-4022-b7ce-82ad779f60e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496412121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.1496412121
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3747835886
Short name T516
Test name
Test status
Simulation time 19091016 ps
CPU time 0.55 seconds
Started Jul 20 04:32:31 PM PDT 24
Finished Jul 20 04:32:35 PM PDT 24
Peak memory 182268 kb
Host smart-d9dbc07a-2577-4460-a66f-5483e6655629
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747835886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.3747835886
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.12980271
Short name T561
Test name
Test status
Simulation time 59395822 ps
CPU time 0.54 seconds
Started Jul 20 04:32:30 PM PDT 24
Finished Jul 20 04:32:34 PM PDT 24
Peak memory 182284 kb
Host smart-e0245c00-5616-44a7-a24d-c04ebfab1005
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12980271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.12980271
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.4257630570
Short name T476
Test name
Test status
Simulation time 40293770 ps
CPU time 0.56 seconds
Started Jul 20 04:32:42 PM PDT 24
Finished Jul 20 04:32:44 PM PDT 24
Peak memory 181756 kb
Host smart-45d6fa5f-ab05-47e9-98b1-f107ca51f556
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257630570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.4257630570
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.2009151681
Short name T497
Test name
Test status
Simulation time 10845364 ps
CPU time 0.53 seconds
Started Jul 20 04:32:37 PM PDT 24
Finished Jul 20 04:32:41 PM PDT 24
Peak memory 181944 kb
Host smart-3eb7fef5-b716-4185-9c11-29646a1c9a05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009151681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.2009151681
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2846990389
Short name T576
Test name
Test status
Simulation time 101043852 ps
CPU time 0.87 seconds
Started Jul 20 04:32:25 PM PDT 24
Finished Jul 20 04:32:28 PM PDT 24
Peak memory 196244 kb
Host smart-0e167fdb-fd04-4263-95b5-2dffe52cc37d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846990389 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.2846990389
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.2546929868
Short name T53
Test name
Test status
Simulation time 30876644 ps
CPU time 0.61 seconds
Started Jul 20 04:34:21 PM PDT 24
Finished Jul 20 04:34:22 PM PDT 24
Peak memory 182348 kb
Host smart-53ecda1c-b23b-485b-9c59-5356e1eeb3ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546929868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.2546929868
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.3709020995
Short name T494
Test name
Test status
Simulation time 15852621 ps
CPU time 0.56 seconds
Started Jul 20 04:32:27 PM PDT 24
Finished Jul 20 04:32:31 PM PDT 24
Peak memory 182244 kb
Host smart-ef9107ae-86e6-42b2-8102-05ef86b0a8a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709020995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.3709020995
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.639268005
Short name T566
Test name
Test status
Simulation time 190475713 ps
CPU time 0.75 seconds
Started Jul 20 04:34:21 PM PDT 24
Finished Jul 20 04:34:22 PM PDT 24
Peak memory 191324 kb
Host smart-2ee9ff15-02df-4721-b76a-09a8a8caec6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639268005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_tim
er_same_csr_outstanding.639268005
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.412235432
Short name T489
Test name
Test status
Simulation time 1068019260 ps
CPU time 1.96 seconds
Started Jul 20 04:32:46 PM PDT 24
Finished Jul 20 04:32:49 PM PDT 24
Peak memory 197136 kb
Host smart-99a101ca-8d73-42c1-b149-823154a1415b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412235432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.412235432
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1129972622
Short name T547
Test name
Test status
Simulation time 89790629 ps
CPU time 1.13 seconds
Started Jul 20 04:32:27 PM PDT 24
Finished Jul 20 04:32:31 PM PDT 24
Peak memory 183024 kb
Host smart-6560ad51-4c99-4f83-b7c3-6802394555b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129972622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.1129972622
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.4216514940
Short name T507
Test name
Test status
Simulation time 27778702 ps
CPU time 0.75 seconds
Started Jul 20 04:32:24 PM PDT 24
Finished Jul 20 04:32:26 PM PDT 24
Peak memory 195340 kb
Host smart-a718902b-0b14-4e9a-a459-f426fbf9f9fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216514940 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.4216514940
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.503637641
Short name T570
Test name
Test status
Simulation time 15442110 ps
CPU time 0.55 seconds
Started Jul 20 04:32:34 PM PDT 24
Finished Jul 20 04:32:37 PM PDT 24
Peak memory 182288 kb
Host smart-fa2e779b-ce50-439d-8809-6782adf3a2bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503637641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.503637641
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.1213326560
Short name T567
Test name
Test status
Simulation time 40835518 ps
CPU time 0.57 seconds
Started Jul 20 04:32:24 PM PDT 24
Finished Jul 20 04:32:26 PM PDT 24
Peak memory 182248 kb
Host smart-f85ccce4-e562-46fc-bd7d-9c8564991e1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213326560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.1213326560
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.3790194979
Short name T523
Test name
Test status
Simulation time 14156580 ps
CPU time 0.61 seconds
Started Jul 20 04:32:26 PM PDT 24
Finished Jul 20 04:32:29 PM PDT 24
Peak memory 191152 kb
Host smart-e8c685a7-094e-49dd-913e-b164194368f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790194979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.3790194979
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.1700985342
Short name T466
Test name
Test status
Simulation time 567604862 ps
CPU time 1.45 seconds
Started Jul 20 04:32:21 PM PDT 24
Finished Jul 20 04:32:24 PM PDT 24
Peak memory 197180 kb
Host smart-f028d5db-d744-411e-84b5-dfc2a35cd497
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700985342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.1700985342
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.1261096778
Short name T471
Test name
Test status
Simulation time 49799921 ps
CPU time 0.82 seconds
Started Jul 20 04:32:29 PM PDT 24
Finished Jul 20 04:32:32 PM PDT 24
Peak memory 193588 kb
Host smart-503d3330-11c0-4f49-9d37-51472373b8a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261096778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.1261096778
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2669368188
Short name T484
Test name
Test status
Simulation time 83784832 ps
CPU time 1.07 seconds
Started Jul 20 04:34:04 PM PDT 24
Finished Jul 20 04:34:06 PM PDT 24
Peak memory 196320 kb
Host smart-624184a8-a0aa-407e-8f61-27a37ead28df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669368188 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.2669368188
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.3053723425
Short name T93
Test name
Test status
Simulation time 13241670 ps
CPU time 0.58 seconds
Started Jul 20 04:32:26 PM PDT 24
Finished Jul 20 04:32:29 PM PDT 24
Peak memory 182360 kb
Host smart-64e1aa34-496c-4fdc-9fd9-b224fa3d448c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053723425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.3053723425
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.1453380428
Short name T454
Test name
Test status
Simulation time 37857204 ps
CPU time 0.56 seconds
Started Jul 20 04:32:21 PM PDT 24
Finished Jul 20 04:32:23 PM PDT 24
Peak memory 182244 kb
Host smart-d0973f0c-b841-47a8-a353-ce7fd77a1b6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453380428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.1453380428
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3104425967
Short name T558
Test name
Test status
Simulation time 22751788 ps
CPU time 0.7 seconds
Started Jul 20 04:32:24 PM PDT 24
Finished Jul 20 04:32:26 PM PDT 24
Peak memory 191616 kb
Host smart-977dead1-7803-4b05-b253-4bd280e54302
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104425967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.3104425967
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.1050874477
Short name T498
Test name
Test status
Simulation time 546187693 ps
CPU time 2.51 seconds
Started Jul 20 04:32:22 PM PDT 24
Finished Jul 20 04:32:25 PM PDT 24
Peak memory 197120 kb
Host smart-1fb1c45b-990b-4274-9c7d-f62b51a71158
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050874477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.1050874477
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.1867619016
Short name T29
Test name
Test status
Simulation time 458680448 ps
CPU time 1.34 seconds
Started Jul 20 04:32:22 PM PDT 24
Finished Jul 20 04:32:24 PM PDT 24
Peak memory 193992 kb
Host smart-36f6f8db-e39a-464d-946c-a29b5d628283
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867619016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.1867619016
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3112384382
Short name T528
Test name
Test status
Simulation time 30147079 ps
CPU time 0.59 seconds
Started Jul 20 04:32:29 PM PDT 24
Finished Jul 20 04:32:33 PM PDT 24
Peak memory 192808 kb
Host smart-a847edb3-9a9d-4e62-859d-78a71a8a4a87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112384382 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.3112384382
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.1768178023
Short name T89
Test name
Test status
Simulation time 13391850 ps
CPU time 0.56 seconds
Started Jul 20 04:32:25 PM PDT 24
Finished Jul 20 04:32:28 PM PDT 24
Peak memory 182108 kb
Host smart-a6c72e50-54e7-482f-8ace-acc4f5d303d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768178023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.1768178023
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.1573281418
Short name T452
Test name
Test status
Simulation time 16774807 ps
CPU time 0.56 seconds
Started Jul 20 04:32:35 PM PDT 24
Finished Jul 20 04:32:38 PM PDT 24
Peak memory 182356 kb
Host smart-07680d74-98b2-415f-b5bb-b5cfd2ee746f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573281418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.1573281418
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.3832226326
Short name T539
Test name
Test status
Simulation time 43018621 ps
CPU time 0.84 seconds
Started Jul 20 04:32:30 PM PDT 24
Finished Jul 20 04:32:34 PM PDT 24
Peak memory 191344 kb
Host smart-080f8a78-9ad3-4cbf-af6c-ebb9cb33841a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832226326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.3832226326
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3912098045
Short name T495
Test name
Test status
Simulation time 142931898 ps
CPU time 2.69 seconds
Started Jul 20 04:32:27 PM PDT 24
Finished Jul 20 04:32:32 PM PDT 24
Peak memory 197048 kb
Host smart-907d4695-7932-4ead-b500-2d3532b92456
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912098045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.3912098045
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.590168849
Short name T55
Test name
Test status
Simulation time 208797031 ps
CPU time 0.85 seconds
Started Jul 20 04:32:26 PM PDT 24
Finished Jul 20 04:32:29 PM PDT 24
Peak memory 193400 kb
Host smart-9ac9de89-5e4f-4578-bcff-c4f4ef6d344d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590168849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_int
g_err.590168849
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.4275769440
Short name T551
Test name
Test status
Simulation time 40567806 ps
CPU time 0.99 seconds
Started Jul 20 04:32:25 PM PDT 24
Finished Jul 20 04:32:28 PM PDT 24
Peak memory 197068 kb
Host smart-cdfc4b6a-4cf0-4b0c-8d5f-36192aa84519
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275769440 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.4275769440
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.1718613460
Short name T506
Test name
Test status
Simulation time 52814085 ps
CPU time 0.54 seconds
Started Jul 20 04:32:27 PM PDT 24
Finished Jul 20 04:32:31 PM PDT 24
Peak memory 182444 kb
Host smart-8f0fff91-a51b-4a4d-bad7-c07038906652
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718613460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.1718613460
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.683049223
Short name T564
Test name
Test status
Simulation time 34907902 ps
CPU time 0.53 seconds
Started Jul 20 04:32:38 PM PDT 24
Finished Jul 20 04:32:42 PM PDT 24
Peak memory 181768 kb
Host smart-e6137bf7-b667-471d-af8f-623f364cfd87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683049223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.683049223
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.4149338262
Short name T87
Test name
Test status
Simulation time 50648025 ps
CPU time 0.7 seconds
Started Jul 20 04:32:32 PM PDT 24
Finished Jul 20 04:32:36 PM PDT 24
Peak memory 191404 kb
Host smart-6e9107a8-92c2-49ff-a6ca-aafcf55a2071
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149338262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.4149338262
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.2208278566
Short name T559
Test name
Test status
Simulation time 146653256 ps
CPU time 2.29 seconds
Started Jul 20 04:32:39 PM PDT 24
Finished Jul 20 04:32:44 PM PDT 24
Peak memory 197104 kb
Host smart-2e8eb9d8-a5fc-4d8d-bfcb-c3c841f835c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208278566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.2208278566
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3739103510
Short name T510
Test name
Test status
Simulation time 179460378 ps
CPU time 0.78 seconds
Started Jul 20 04:32:27 PM PDT 24
Finished Jul 20 04:32:31 PM PDT 24
Peak memory 193324 kb
Host smart-0297ce7e-b781-4c2e-8c3b-9d55ad5f49d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739103510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.3739103510
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.2526790174
Short name T393
Test name
Test status
Simulation time 123161415257 ps
CPU time 170.27 seconds
Started Jul 20 04:32:32 PM PDT 24
Finished Jul 20 04:35:25 PM PDT 24
Peak memory 183432 kb
Host smart-77f90304-b867-4ad6-8a12-1523a4c7b70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526790174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.2526790174
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.488285344
Short name T44
Test name
Test status
Simulation time 144834393961 ps
CPU time 359.71 seconds
Started Jul 20 04:32:34 PM PDT 24
Finished Jul 20 04:38:37 PM PDT 24
Peak memory 183484 kb
Host smart-8bb7f2ea-bf0c-48b3-a029-57bfaa8885e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488285344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.488285344
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.1798053489
Short name T22
Test name
Test status
Simulation time 240391223410 ps
CPU time 594.11 seconds
Started Jul 20 04:32:33 PM PDT 24
Finished Jul 20 04:42:30 PM PDT 24
Peak memory 195028 kb
Host smart-3fb628c8-9151-4498-a121-cda2393a204b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798053489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.1798053489
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all_with_rand_reset.564191582
Short name T40
Test name
Test status
Simulation time 11292126841 ps
CPU time 124.24 seconds
Started Jul 20 04:32:42 PM PDT 24
Finished Jul 20 04:34:48 PM PDT 24
Peak memory 196104 kb
Host smart-9554e220-15cb-41a3-87dd-e813fe3ee1fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564191582 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all_with_rand_reset.564191582
Directory /workspace/0.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.1713220010
Short name T444
Test name
Test status
Simulation time 14238072276 ps
CPU time 21.77 seconds
Started Jul 20 04:32:38 PM PDT 24
Finished Jul 20 04:33:03 PM PDT 24
Peak memory 183424 kb
Host smart-7f331053-ecd9-4c69-9cef-09d43c9d7b9f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713220010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.1713220010
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.2258175512
Short name T377
Test name
Test status
Simulation time 94855155167 ps
CPU time 78.86 seconds
Started Jul 20 04:32:32 PM PDT 24
Finished Jul 20 04:33:54 PM PDT 24
Peak memory 183432 kb
Host smart-66c96571-8911-4ae9-949a-91aadd59237f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258175512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.2258175512
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.2813237636
Short name T368
Test name
Test status
Simulation time 20645931 ps
CPU time 0.59 seconds
Started Jul 20 04:32:34 PM PDT 24
Finished Jul 20 04:32:37 PM PDT 24
Peak memory 183168 kb
Host smart-0dc80ce6-95d4-420f-a880-bdc91deeace6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813237636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.2813237636
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.1318647649
Short name T16
Test name
Test status
Simulation time 90613131 ps
CPU time 0.9 seconds
Started Jul 20 04:32:37 PM PDT 24
Finished Jul 20 04:32:45 PM PDT 24
Peak memory 214744 kb
Host smart-bbdf5fa1-20c0-4a8a-87c5-1d2802826669
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318647649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.1318647649
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.1750414159
Short name T384
Test name
Test status
Simulation time 178906575053 ps
CPU time 234.66 seconds
Started Jul 20 04:33:21 PM PDT 24
Finished Jul 20 04:37:22 PM PDT 24
Peak memory 191604 kb
Host smart-41b85d72-a74d-4e51-a82b-ab311e665a52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750414159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
1750414159
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.1197975646
Short name T427
Test name
Test status
Simulation time 167923169193 ps
CPU time 128.93 seconds
Started Jul 20 04:32:58 PM PDT 24
Finished Jul 20 04:35:07 PM PDT 24
Peak memory 183420 kb
Host smart-28ae24db-e162-4b56-81a5-c180badd9731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197975646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.1197975646
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.3214070825
Short name T362
Test name
Test status
Simulation time 298779595216 ps
CPU time 132.67 seconds
Started Jul 20 04:33:10 PM PDT 24
Finished Jul 20 04:35:23 PM PDT 24
Peak memory 192940 kb
Host smart-aece8dbf-495a-4b1d-9eda-53e6c919877f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214070825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.3214070825
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/102.rv_timer_random.2501426995
Short name T231
Test name
Test status
Simulation time 53374499880 ps
CPU time 37.78 seconds
Started Jul 20 04:33:28 PM PDT 24
Finished Jul 20 04:34:14 PM PDT 24
Peak memory 183388 kb
Host smart-e6239238-d66d-42ac-85e9-c577b4a538e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501426995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.2501426995
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.3625415877
Short name T386
Test name
Test status
Simulation time 335825023084 ps
CPU time 86.96 seconds
Started Jul 20 04:33:27 PM PDT 24
Finished Jul 20 04:35:02 PM PDT 24
Peak memory 183416 kb
Host smart-26bfee64-a8d6-4c51-9618-9f17caf2d434
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625415877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.3625415877
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.159806966
Short name T123
Test name
Test status
Simulation time 147834203213 ps
CPU time 218.92 seconds
Started Jul 20 04:33:31 PM PDT 24
Finished Jul 20 04:37:18 PM PDT 24
Peak memory 191596 kb
Host smart-fe273389-19ed-4e9f-8c6a-852ca6d6ff07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159806966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.159806966
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.2134668313
Short name T262
Test name
Test status
Simulation time 6187387910998 ps
CPU time 1669.3 seconds
Started Jul 20 04:32:44 PM PDT 24
Finished Jul 20 05:00:35 PM PDT 24
Peak memory 183352 kb
Host smart-bdb3a763-8da4-45d2-bd5f-428e74556d98
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134668313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.2134668313
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.2544607664
Short name T395
Test name
Test status
Simulation time 652638243881 ps
CPU time 263.35 seconds
Started Jul 20 04:32:36 PM PDT 24
Finished Jul 20 04:37:03 PM PDT 24
Peak memory 183396 kb
Host smart-89ce5cab-0078-4a87-b370-a7ad33eb7eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544607664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.2544607664
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/110.rv_timer_random.527120175
Short name T193
Test name
Test status
Simulation time 497639025835 ps
CPU time 720.87 seconds
Started Jul 20 04:33:18 PM PDT 24
Finished Jul 20 04:45:26 PM PDT 24
Peak memory 191636 kb
Host smart-17c8043d-af54-484e-a63d-009bbc03759b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527120175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.527120175
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.99653008
Short name T269
Test name
Test status
Simulation time 69882978206 ps
CPU time 118 seconds
Started Jul 20 04:33:18 PM PDT 24
Finished Jul 20 04:35:21 PM PDT 24
Peak memory 194912 kb
Host smart-419b459d-e7b4-4be3-959d-ebde0a224cc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99653008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.99653008
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.3140803234
Short name T200
Test name
Test status
Simulation time 312628667679 ps
CPU time 579.25 seconds
Started Jul 20 04:33:38 PM PDT 24
Finished Jul 20 04:43:25 PM PDT 24
Peak memory 191632 kb
Host smart-1541ca55-d767-48d5-a907-b58e82e105f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140803234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.3140803234
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.3830709245
Short name T136
Test name
Test status
Simulation time 21158972681 ps
CPU time 43.76 seconds
Started Jul 20 04:33:25 PM PDT 24
Finished Jul 20 04:34:15 PM PDT 24
Peak memory 191580 kb
Host smart-a8ff2100-8a50-4c8c-9dd6-b6cb1d3abe27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830709245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.3830709245
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.2262184585
Short name T272
Test name
Test status
Simulation time 178190607631 ps
CPU time 431.92 seconds
Started Jul 20 04:33:29 PM PDT 24
Finished Jul 20 04:40:49 PM PDT 24
Peak memory 191628 kb
Host smart-a051b871-a157-4bea-9733-99e1d2d36d65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262184585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.2262184585
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.619667210
Short name T6
Test name
Test status
Simulation time 70010624977 ps
CPU time 348.66 seconds
Started Jul 20 04:33:26 PM PDT 24
Finished Jul 20 04:39:22 PM PDT 24
Peak memory 191628 kb
Host smart-668da37c-2555-42fa-8717-90173a6e879f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619667210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.619667210
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.3282427921
Short name T82
Test name
Test status
Simulation time 171013058193 ps
CPU time 384.29 seconds
Started Jul 20 04:33:21 PM PDT 24
Finished Jul 20 04:39:51 PM PDT 24
Peak memory 191576 kb
Host smart-6cb8d63e-9f31-42f8-90a0-d48f13fb8de1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282427921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.3282427921
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.1366477217
Short name T227
Test name
Test status
Simulation time 77788662732 ps
CPU time 42.51 seconds
Started Jul 20 04:33:26 PM PDT 24
Finished Jul 20 04:34:16 PM PDT 24
Peak memory 191644 kb
Host smart-d7a18103-3a29-4302-9e5a-f3701fef77fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366477217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.1366477217
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.1528376629
Short name T391
Test name
Test status
Simulation time 500544599890 ps
CPU time 208.06 seconds
Started Jul 20 04:32:37 PM PDT 24
Finished Jul 20 04:36:08 PM PDT 24
Peak memory 183384 kb
Host smart-0c5b163f-f1e1-44a3-9a61-ffefd9f35c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528376629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.1528376629
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.4074442261
Short name T371
Test name
Test status
Simulation time 448827747 ps
CPU time 0.75 seconds
Started Jul 20 04:32:41 PM PDT 24
Finished Jul 20 04:32:44 PM PDT 24
Peak memory 191768 kb
Host smart-3133fa40-d30d-416c-a562-d4e39b16d7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074442261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.4074442261
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.3565518053
Short name T138
Test name
Test status
Simulation time 337091755887 ps
CPU time 504.91 seconds
Started Jul 20 04:32:55 PM PDT 24
Finished Jul 20 04:41:20 PM PDT 24
Peak memory 196008 kb
Host smart-eb990c08-b7b5-446b-952c-ef32e3cc0555
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565518053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.3565518053
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/121.rv_timer_random.2579318113
Short name T447
Test name
Test status
Simulation time 75819677469 ps
CPU time 84.78 seconds
Started Jul 20 04:33:28 PM PDT 24
Finished Jul 20 04:35:01 PM PDT 24
Peak memory 183412 kb
Host smart-04335b82-3c07-40ed-853d-b8268d416e92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579318113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.2579318113
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.3169216261
Short name T120
Test name
Test status
Simulation time 43560644032 ps
CPU time 262.03 seconds
Started Jul 20 04:33:20 PM PDT 24
Finished Jul 20 04:37:49 PM PDT 24
Peak memory 191720 kb
Host smart-6d91e845-a9a7-48aa-aed2-672c961702cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169216261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.3169216261
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.1207987509
Short name T336
Test name
Test status
Simulation time 82920455759 ps
CPU time 157.56 seconds
Started Jul 20 04:33:17 PM PDT 24
Finished Jul 20 04:35:59 PM PDT 24
Peak memory 191560 kb
Host smart-5408960d-6c81-4315-aabc-c37bb069b49f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207987509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.1207987509
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.3144530927
Short name T20
Test name
Test status
Simulation time 66743155666 ps
CPU time 409.14 seconds
Started Jul 20 04:33:30 PM PDT 24
Finished Jul 20 04:40:27 PM PDT 24
Peak memory 191584 kb
Host smart-511795fb-bb49-493c-842c-ed17a973a5b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144530927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.3144530927
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.3594183270
Short name T85
Test name
Test status
Simulation time 94437806998 ps
CPU time 1677.57 seconds
Started Jul 20 04:33:32 PM PDT 24
Finished Jul 20 05:01:38 PM PDT 24
Peak memory 191580 kb
Host smart-3b9f7bb3-7ccd-40b2-b35c-59eace9ad75f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594183270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.3594183270
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.1012316750
Short name T196
Test name
Test status
Simulation time 77601568243 ps
CPU time 1421.34 seconds
Started Jul 20 04:33:36 PM PDT 24
Finished Jul 20 04:57:26 PM PDT 24
Peak memory 191636 kb
Host smart-db4ce930-5194-49b0-b263-4f6b63f6a6f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012316750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.1012316750
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.1855248018
Short name T425
Test name
Test status
Simulation time 183713251709 ps
CPU time 223.89 seconds
Started Jul 20 04:33:24 PM PDT 24
Finished Jul 20 04:37:15 PM PDT 24
Peak memory 183432 kb
Host smart-a02bee0a-3844-44a6-bdd3-1adca7770279
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855248018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.1855248018
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.3067663820
Short name T433
Test name
Test status
Simulation time 24527752006 ps
CPU time 43.37 seconds
Started Jul 20 04:32:57 PM PDT 24
Finished Jul 20 04:33:41 PM PDT 24
Peak memory 183416 kb
Host smart-84904b4d-e347-48ed-b9f9-8dcf31bce33b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067663820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.3067663820
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_random.2836488138
Short name T328
Test name
Test status
Simulation time 88647340687 ps
CPU time 34.38 seconds
Started Jul 20 04:32:42 PM PDT 24
Finished Jul 20 04:33:18 PM PDT 24
Peak memory 183216 kb
Host smart-07b0ebd2-3292-4e56-822a-a623d9a0c5bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836488138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.2836488138
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.2491155883
Short name T402
Test name
Test status
Simulation time 47129098 ps
CPU time 1.05 seconds
Started Jul 20 04:32:38 PM PDT 24
Finished Jul 20 04:32:42 PM PDT 24
Peak memory 183260 kb
Host smart-f1e5c2b2-18b7-42b5-bd5b-572e1309a1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491155883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.2491155883
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.716914327
Short name T359
Test name
Test status
Simulation time 514768751692 ps
CPU time 737.54 seconds
Started Jul 20 04:32:44 PM PDT 24
Finished Jul 20 04:45:03 PM PDT 24
Peak memory 191560 kb
Host smart-da90437c-ee4f-4cb0-a3cf-11c69e5359c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716914327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all.
716914327
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/131.rv_timer_random.132922585
Short name T320
Test name
Test status
Simulation time 172340803231 ps
CPU time 153.27 seconds
Started Jul 20 04:33:25 PM PDT 24
Finished Jul 20 04:36:06 PM PDT 24
Peak memory 191560 kb
Host smart-1b07f895-9387-4820-8528-8437004211f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132922585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.132922585
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.2455569904
Short name T351
Test name
Test status
Simulation time 367715755442 ps
CPU time 266.38 seconds
Started Jul 20 04:33:25 PM PDT 24
Finished Jul 20 04:37:58 PM PDT 24
Peak memory 191560 kb
Host smart-f12bd6a7-cc4e-4153-801e-c9f56fa541d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455569904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.2455569904
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.2669388952
Short name T186
Test name
Test status
Simulation time 137232596437 ps
CPU time 469.5 seconds
Started Jul 20 04:33:18 PM PDT 24
Finished Jul 20 04:41:13 PM PDT 24
Peak memory 191440 kb
Host smart-e8bcc7f7-19da-4cc2-aad9-1d37805f6c09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669388952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.2669388952
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.2463334827
Short name T258
Test name
Test status
Simulation time 263337049444 ps
CPU time 205.26 seconds
Started Jul 20 04:33:21 PM PDT 24
Finished Jul 20 04:36:53 PM PDT 24
Peak memory 191588 kb
Host smart-7dd34ecb-ada2-49e3-8f69-aa37f6e316e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463334827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.2463334827
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.4082484844
Short name T164
Test name
Test status
Simulation time 497030176146 ps
CPU time 397.48 seconds
Started Jul 20 04:33:15 PM PDT 24
Finished Jul 20 04:39:54 PM PDT 24
Peak memory 183392 kb
Host smart-011d86ec-ae02-43d1-8727-d345c9e885a1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082484844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.4082484844
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.3692709199
Short name T375
Test name
Test status
Simulation time 121731168572 ps
CPU time 120.29 seconds
Started Jul 20 04:32:41 PM PDT 24
Finished Jul 20 04:34:44 PM PDT 24
Peak memory 183348 kb
Host smart-77bf019c-8cef-463f-a132-780a40ac4c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692709199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.3692709199
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.1348580787
Short name T326
Test name
Test status
Simulation time 67059723391 ps
CPU time 587.3 seconds
Started Jul 20 04:32:43 PM PDT 24
Finished Jul 20 04:42:32 PM PDT 24
Peak memory 191584 kb
Host smart-65ced505-c986-4801-be7c-197e7fb7f06d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348580787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.1348580787
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.306612557
Short name T404
Test name
Test status
Simulation time 9800867021 ps
CPU time 7.88 seconds
Started Jul 20 04:32:57 PM PDT 24
Finished Jul 20 04:33:05 PM PDT 24
Peak memory 183432 kb
Host smart-427b8b31-0ac7-4d4f-be45-de5b6c908b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306612557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.306612557
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/141.rv_timer_random.3623908475
Short name T58
Test name
Test status
Simulation time 343312852621 ps
CPU time 358.93 seconds
Started Jul 20 04:33:20 PM PDT 24
Finished Jul 20 04:39:26 PM PDT 24
Peak memory 191540 kb
Host smart-dda37bd3-6ff5-4439-8daa-bf6d313ec44b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623908475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.3623908475
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.484753282
Short name T177
Test name
Test status
Simulation time 211449475752 ps
CPU time 648.69 seconds
Started Jul 20 04:33:22 PM PDT 24
Finished Jul 20 04:44:17 PM PDT 24
Peak memory 195040 kb
Host smart-91db3787-423a-4e40-b60b-38254ccf39fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484753282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.484753282
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.3134540314
Short name T184
Test name
Test status
Simulation time 707877173356 ps
CPU time 495.84 seconds
Started Jul 20 04:33:41 PM PDT 24
Finished Jul 20 04:42:03 PM PDT 24
Peak memory 191628 kb
Host smart-c2d2a565-a2b3-4c9b-80be-1533f3f16a0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134540314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.3134540314
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.2349631486
Short name T261
Test name
Test status
Simulation time 239015041363 ps
CPU time 420.24 seconds
Started Jul 20 04:33:02 PM PDT 24
Finished Jul 20 04:40:04 PM PDT 24
Peak memory 183412 kb
Host smart-a6484ad2-9d4c-4ce8-b075-a60737ac36a2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349631486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.2349631486
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.2959624129
Short name T416
Test name
Test status
Simulation time 5937564780 ps
CPU time 7.49 seconds
Started Jul 20 04:32:51 PM PDT 24
Finished Jul 20 04:32:59 PM PDT 24
Peak memory 183268 kb
Host smart-e955b504-cdef-4dd5-a0b2-7a028fd37aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959624129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.2959624129
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.1827078340
Short name T128
Test name
Test status
Simulation time 390613908814 ps
CPU time 143.46 seconds
Started Jul 20 04:32:54 PM PDT 24
Finished Jul 20 04:35:18 PM PDT 24
Peak memory 191636 kb
Host smart-d5f911bd-bbf3-4f6c-afe2-8068219310e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827078340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.1827078340
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.2457559396
Short name T67
Test name
Test status
Simulation time 2947915546477 ps
CPU time 761.08 seconds
Started Jul 20 04:32:36 PM PDT 24
Finished Jul 20 04:45:20 PM PDT 24
Peak memory 196120 kb
Host smart-f080d5c3-c259-4d64-a038-c1b26bb6aff4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457559396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.2457559396
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.815379371
Short name T12
Test name
Test status
Simulation time 284819492161 ps
CPU time 1322.4 seconds
Started Jul 20 04:32:39 PM PDT 24
Finished Jul 20 04:54:44 PM PDT 24
Peak memory 215992 kb
Host smart-a0108d5c-7b3d-4eb5-ba06-b50037032eec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815379371 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all_with_rand_reset.815379371
Directory /workspace/15.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.rv_timer_random.135946633
Short name T118
Test name
Test status
Simulation time 78997230369 ps
CPU time 488.9 seconds
Started Jul 20 04:33:35 PM PDT 24
Finished Jul 20 04:41:52 PM PDT 24
Peak memory 192716 kb
Host smart-cab33a2b-1547-43ed-b463-62e11c89d373
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135946633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.135946633
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.4112547236
Short name T319
Test name
Test status
Simulation time 1469849563760 ps
CPU time 328.01 seconds
Started Jul 20 04:33:19 PM PDT 24
Finished Jul 20 04:38:53 PM PDT 24
Peak memory 191632 kb
Host smart-8174c649-0be9-4f30-b19f-31ecfe6a9cfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112547236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.4112547236
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.869289507
Short name T125
Test name
Test status
Simulation time 20265532382 ps
CPU time 36.11 seconds
Started Jul 20 04:33:26 PM PDT 24
Finished Jul 20 04:34:09 PM PDT 24
Peak memory 183432 kb
Host smart-7601d236-11ec-4fc2-a352-b69775a50a7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869289507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.869289507
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.2815905891
Short name T263
Test name
Test status
Simulation time 2079954479711 ps
CPU time 2052.4 seconds
Started Jul 20 04:33:26 PM PDT 24
Finished Jul 20 05:07:46 PM PDT 24
Peak memory 193908 kb
Host smart-7c944c1d-86fb-4796-875e-83b7225b2e57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815905891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.2815905891
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.1879933273
Short name T306
Test name
Test status
Simulation time 70140384464 ps
CPU time 69.51 seconds
Started Jul 20 04:33:24 PM PDT 24
Finished Jul 20 04:34:40 PM PDT 24
Peak memory 183388 kb
Host smart-c8071b45-91ef-4d5f-a316-9271b3f52f7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879933273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.1879933273
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.975068978
Short name T162
Test name
Test status
Simulation time 465578369145 ps
CPU time 197.46 seconds
Started Jul 20 04:33:28 PM PDT 24
Finished Jul 20 04:36:53 PM PDT 24
Peak memory 191580 kb
Host smart-ecf2f881-fd02-4fe4-b41b-e3e97d28da46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975068978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.975068978
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.1656208525
Short name T357
Test name
Test status
Simulation time 75672586892 ps
CPU time 255.05 seconds
Started Jul 20 04:33:37 PM PDT 24
Finished Jul 20 04:38:00 PM PDT 24
Peak memory 191648 kb
Host smart-02fa094a-ba37-4e78-997e-77c99c97f846
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656208525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.1656208525
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.3251702572
Short name T345
Test name
Test status
Simulation time 69997721955 ps
CPU time 294.11 seconds
Started Jul 20 04:33:41 PM PDT 24
Finished Jul 20 04:38:42 PM PDT 24
Peak memory 195344 kb
Host smart-e3a04d5c-4c30-4cff-b2e6-ac7079fcf27c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251702572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.3251702572
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.1716129798
Short name T411
Test name
Test status
Simulation time 104890149456 ps
CPU time 188.09 seconds
Started Jul 20 04:33:26 PM PDT 24
Finished Jul 20 04:36:42 PM PDT 24
Peak memory 191580 kb
Host smart-b2c6c007-15c0-4553-bf04-64f3389afceb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716129798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.1716129798
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.2984433664
Short name T309
Test name
Test status
Simulation time 144899723979 ps
CPU time 247.92 seconds
Started Jul 20 04:33:24 PM PDT 24
Finished Jul 20 04:37:39 PM PDT 24
Peak memory 191548 kb
Host smart-780ff570-ab15-4989-9474-c150bb7caa04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984433664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.2984433664
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.1560003259
Short name T242
Test name
Test status
Simulation time 954043988965 ps
CPU time 348.96 seconds
Started Jul 20 04:33:01 PM PDT 24
Finished Jul 20 04:38:50 PM PDT 24
Peak memory 183484 kb
Host smart-71aca0b7-1f50-462c-b902-ef304c5cbe27
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560003259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.1560003259
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.3687372863
Short name T442
Test name
Test status
Simulation time 74503664860 ps
CPU time 111.82 seconds
Started Jul 20 04:32:46 PM PDT 24
Finished Jul 20 04:34:40 PM PDT 24
Peak memory 183436 kb
Host smart-df62cee5-9f24-490e-8f50-bb376acf2a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687372863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.3687372863
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.3622225454
Short name T126
Test name
Test status
Simulation time 64462202251 ps
CPU time 541.52 seconds
Started Jul 20 04:32:42 PM PDT 24
Finished Jul 20 04:41:45 PM PDT 24
Peak memory 191576 kb
Host smart-7ac7d623-2fa3-43c4-805d-4459f3b44c1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622225454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.3622225454
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.1722657131
Short name T408
Test name
Test status
Simulation time 25880931 ps
CPU time 0.57 seconds
Started Jul 20 04:32:49 PM PDT 24
Finished Jul 20 04:32:50 PM PDT 24
Peak memory 183096 kb
Host smart-50200b77-e1dd-4be5-87a4-c0ce042a4c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722657131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.1722657131
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/161.rv_timer_random.1581835087
Short name T407
Test name
Test status
Simulation time 36413572315 ps
CPU time 30.12 seconds
Started Jul 20 04:33:25 PM PDT 24
Finished Jul 20 04:34:02 PM PDT 24
Peak memory 183400 kb
Host smart-4334d04a-f824-41f6-8ce3-24261c83959f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581835087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.1581835087
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.3842644518
Short name T281
Test name
Test status
Simulation time 153942371034 ps
CPU time 529.98 seconds
Started Jul 20 04:33:34 PM PDT 24
Finished Jul 20 04:42:32 PM PDT 24
Peak memory 191580 kb
Host smart-b07e30fb-9027-48d1-97fb-8b84ec6aaa43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842644518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.3842644518
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.719001069
Short name T224
Test name
Test status
Simulation time 17102703796 ps
CPU time 28.42 seconds
Started Jul 20 04:33:24 PM PDT 24
Finished Jul 20 04:34:00 PM PDT 24
Peak memory 191560 kb
Host smart-6aefa38b-0e47-4164-a026-93dbc69245de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719001069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.719001069
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.3396967267
Short name T45
Test name
Test status
Simulation time 51693220298 ps
CPU time 294.78 seconds
Started Jul 20 04:33:31 PM PDT 24
Finished Jul 20 04:38:34 PM PDT 24
Peak memory 191640 kb
Host smart-fbab93b1-785f-455a-9372-0228be9b2497
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396967267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.3396967267
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.4031176947
Short name T234
Test name
Test status
Simulation time 434405058746 ps
CPU time 178.61 seconds
Started Jul 20 04:33:23 PM PDT 24
Finished Jul 20 04:36:28 PM PDT 24
Peak memory 191548 kb
Host smart-3198a011-c46a-4756-af14-7c6319b943b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031176947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.4031176947
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.2269646884
Short name T259
Test name
Test status
Simulation time 483180396180 ps
CPU time 378.39 seconds
Started Jul 20 04:34:21 PM PDT 24
Finished Jul 20 04:40:40 PM PDT 24
Peak memory 191536 kb
Host smart-7f13440f-e6f7-47a2-b358-5ccf14b43065
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269646884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.2269646884
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.46832152
Short name T329
Test name
Test status
Simulation time 718947774363 ps
CPU time 317.27 seconds
Started Jul 20 04:33:02 PM PDT 24
Finished Jul 20 04:38:21 PM PDT 24
Peak memory 183412 kb
Host smart-4a4229ca-1df2-49f6-b639-593519f550c1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46832152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.rv_timer_cfg_update_on_fly.46832152
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.3930748826
Short name T392
Test name
Test status
Simulation time 487281121438 ps
CPU time 227.26 seconds
Started Jul 20 04:33:06 PM PDT 24
Finished Jul 20 04:36:54 PM PDT 24
Peak memory 183448 kb
Host smart-7235b60c-7163-43c6-b1ca-0bf049b4438e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930748826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.3930748826
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.3097950511
Short name T246
Test name
Test status
Simulation time 2371946719622 ps
CPU time 843.46 seconds
Started Jul 20 04:32:46 PM PDT 24
Finished Jul 20 04:46:51 PM PDT 24
Peak memory 191632 kb
Host smart-8e797350-a31c-40df-bde1-732fa8094082
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097950511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.3097950511
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.2085078412
Short name T268
Test name
Test status
Simulation time 75536884766 ps
CPU time 19.07 seconds
Started Jul 20 04:32:51 PM PDT 24
Finished Jul 20 04:33:11 PM PDT 24
Peak memory 194376 kb
Host smart-a8b83ba5-8889-4994-983a-33a751d38f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085078412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.2085078412
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.2733602857
Short name T1
Test name
Test status
Simulation time 191133757 ps
CPU time 0.68 seconds
Started Jul 20 04:32:54 PM PDT 24
Finished Jul 20 04:32:55 PM PDT 24
Peak memory 183196 kb
Host smart-841a8f0b-9661-4b79-b46c-20aed60cb87e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733602857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.2733602857
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.2601602086
Short name T37
Test name
Test status
Simulation time 48680528583 ps
CPU time 1461.26 seconds
Started Jul 20 04:33:12 PM PDT 24
Finished Jul 20 04:57:35 PM PDT 24
Peak memory 206640 kb
Host smart-3b877154-e744-4240-ada0-b338d73d5a22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601602086 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all_with_rand_reset.2601602086
Directory /workspace/17.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.1224796977
Short name T292
Test name
Test status
Simulation time 120883581676 ps
CPU time 621.83 seconds
Started Jul 20 04:33:37 PM PDT 24
Finished Jul 20 04:44:07 PM PDT 24
Peak memory 191628 kb
Host smart-1c5d9f9a-c4b8-41b8-85ee-254686413826
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224796977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.1224796977
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.3607448770
Short name T109
Test name
Test status
Simulation time 135321422806 ps
CPU time 236.42 seconds
Started Jul 20 04:33:31 PM PDT 24
Finished Jul 20 04:37:36 PM PDT 24
Peak memory 191636 kb
Host smart-50ae1f4a-a082-415c-95bf-32028cb4895c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607448770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.3607448770
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.821492533
Short name T301
Test name
Test status
Simulation time 142669074126 ps
CPU time 359.54 seconds
Started Jul 20 04:33:41 PM PDT 24
Finished Jul 20 04:39:47 PM PDT 24
Peak memory 191580 kb
Host smart-ad830ad5-f2fb-4e0e-9029-4feb3892063c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821492533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.821492533
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.3739281697
Short name T353
Test name
Test status
Simulation time 13957984006 ps
CPU time 18.98 seconds
Started Jul 20 04:33:28 PM PDT 24
Finished Jul 20 04:33:55 PM PDT 24
Peak memory 183436 kb
Host smart-e3da85f5-aff5-4896-89b8-c544d0f2720f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739281697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.3739281697
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.3107043864
Short name T321
Test name
Test status
Simulation time 249032042395 ps
CPU time 147.29 seconds
Started Jul 20 04:33:39 PM PDT 24
Finished Jul 20 04:36:14 PM PDT 24
Peak memory 191632 kb
Host smart-3f4f36f8-83eb-491a-a11f-7e528989d088
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107043864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.3107043864
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.824779639
Short name T260
Test name
Test status
Simulation time 103574954326 ps
CPU time 72.88 seconds
Started Jul 20 04:33:31 PM PDT 24
Finished Jul 20 04:34:52 PM PDT 24
Peak memory 191640 kb
Host smart-89d172e2-9176-473c-b38c-f612a2e54236
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824779639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.824779639
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.3805624107
Short name T127
Test name
Test status
Simulation time 56304068848 ps
CPU time 80.21 seconds
Started Jul 20 04:33:30 PM PDT 24
Finished Jul 20 04:34:58 PM PDT 24
Peak memory 193820 kb
Host smart-c32aa26d-f72b-4c14-b901-00e1fc4d4c02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805624107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.3805624107
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.2743312467
Short name T140
Test name
Test status
Simulation time 172387823366 ps
CPU time 499.59 seconds
Started Jul 20 04:33:40 PM PDT 24
Finished Jul 20 04:42:07 PM PDT 24
Peak memory 191612 kb
Host smart-676ebf34-5bba-4c2a-9f78-3ba15ed255bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743312467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.2743312467
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.3898401101
Short name T372
Test name
Test status
Simulation time 75879601358 ps
CPU time 118.02 seconds
Started Jul 20 04:33:24 PM PDT 24
Finished Jul 20 04:35:29 PM PDT 24
Peak memory 183380 kb
Host smart-9f940f5b-a6e7-4d41-af41-dabbbb63ba74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898401101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.3898401101
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.609321109
Short name T283
Test name
Test status
Simulation time 4027968392 ps
CPU time 6.04 seconds
Started Jul 20 04:33:16 PM PDT 24
Finished Jul 20 04:33:26 PM PDT 24
Peak memory 183256 kb
Host smart-ab29688e-e393-4a81-a5a1-66496ee6cefe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609321109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.609321109
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.646963861
Short name T356
Test name
Test status
Simulation time 187828709443 ps
CPU time 397.61 seconds
Started Jul 20 04:33:03 PM PDT 24
Finished Jul 20 04:39:41 PM PDT 24
Peak memory 191632 kb
Host smart-9016a848-f35a-4a02-9ccc-722f7cbe41ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646963861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.646963861
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.4039607794
Short name T417
Test name
Test status
Simulation time 10950588889 ps
CPU time 20.01 seconds
Started Jul 20 04:32:54 PM PDT 24
Finished Jul 20 04:33:15 PM PDT 24
Peak memory 183436 kb
Host smart-ad8783a0-a052-4af2-8639-38db54681d62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039607794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.4039607794
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/180.rv_timer_random.3453139205
Short name T348
Test name
Test status
Simulation time 413085685677 ps
CPU time 170.43 seconds
Started Jul 20 04:33:24 PM PDT 24
Finished Jul 20 04:36:22 PM PDT 24
Peak memory 191024 kb
Host smart-4025371c-63b3-4456-a463-7a001f131f2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453139205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.3453139205
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.3817598715
Short name T313
Test name
Test status
Simulation time 2536764418733 ps
CPU time 3043.41 seconds
Started Jul 20 04:33:32 PM PDT 24
Finished Jul 20 05:24:24 PM PDT 24
Peak memory 191684 kb
Host smart-f9792ebf-0362-41f0-90e9-878af608daf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817598715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.3817598715
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.993990816
Short name T78
Test name
Test status
Simulation time 123758270110 ps
CPU time 1657.16 seconds
Started Jul 20 04:33:26 PM PDT 24
Finished Jul 20 05:01:11 PM PDT 24
Peak memory 191568 kb
Host smart-08bd8022-a070-4ff5-8042-8415a692996a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993990816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.993990816
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.459001427
Short name T221
Test name
Test status
Simulation time 81777052258 ps
CPU time 150.94 seconds
Started Jul 20 04:33:27 PM PDT 24
Finished Jul 20 04:36:06 PM PDT 24
Peak memory 191584 kb
Host smart-d9b776cd-05b8-4d4b-8709-011b472c8488
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459001427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.459001427
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.2125460695
Short name T448
Test name
Test status
Simulation time 262624682164 ps
CPU time 146.11 seconds
Started Jul 20 04:33:35 PM PDT 24
Finished Jul 20 04:36:09 PM PDT 24
Peak memory 191692 kb
Host smart-fa4a60e3-6502-407e-b173-437b6288d92f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125460695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.2125460695
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.3825920886
Short name T360
Test name
Test status
Simulation time 151344716534 ps
CPU time 39.33 seconds
Started Jul 20 04:33:27 PM PDT 24
Finished Jul 20 04:34:13 PM PDT 24
Peak memory 191580 kb
Host smart-27eee51f-bfa1-46f4-990d-fb1ba702ebef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825920886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.3825920886
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.989841511
Short name T160
Test name
Test status
Simulation time 77044113948 ps
CPU time 133.74 seconds
Started Jul 20 04:33:03 PM PDT 24
Finished Jul 20 04:35:19 PM PDT 24
Peak memory 183436 kb
Host smart-e1681dd1-9f4c-4d9b-9f5d-5021f5981911
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989841511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.rv_timer_cfg_update_on_fly.989841511
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.3398502711
Short name T398
Test name
Test status
Simulation time 125778234942 ps
CPU time 191.32 seconds
Started Jul 20 04:33:17 PM PDT 24
Finished Jul 20 04:36:33 PM PDT 24
Peak memory 183448 kb
Host smart-b28f392f-d2d6-42ff-a99f-9ca91a5ad461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398502711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.3398502711
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.2825631944
Short name T119
Test name
Test status
Simulation time 98466217392 ps
CPU time 139.4 seconds
Started Jul 20 04:32:55 PM PDT 24
Finished Jul 20 04:35:15 PM PDT 24
Peak memory 183384 kb
Host smart-60cdaa3c-1e87-4dc9-b1d0-29823f1288d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825631944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.2825631944
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.1006446583
Short name T388
Test name
Test status
Simulation time 176635738675 ps
CPU time 65.91 seconds
Started Jul 20 04:33:08 PM PDT 24
Finished Jul 20 04:34:15 PM PDT 24
Peak memory 183384 kb
Host smart-5df141d1-118a-4444-a8cb-32cb57b753ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006446583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.1006446583
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/190.rv_timer_random.4072491490
Short name T248
Test name
Test status
Simulation time 145000707262 ps
CPU time 631.12 seconds
Started Jul 20 04:33:39 PM PDT 24
Finished Jul 20 04:44:17 PM PDT 24
Peak memory 191640 kb
Host smart-e635c17d-5cdd-47bf-905d-10c0e0192ad2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072491490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.4072491490
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.647684456
Short name T280
Test name
Test status
Simulation time 1402386219142 ps
CPU time 582.31 seconds
Started Jul 20 04:33:18 PM PDT 24
Finished Jul 20 04:43:05 PM PDT 24
Peak memory 191512 kb
Host smart-20880d47-c5aa-4050-bd78-7b4b4ea1901b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647684456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.647684456
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.3910873691
Short name T59
Test name
Test status
Simulation time 85715768190 ps
CPU time 630.32 seconds
Started Jul 20 04:33:24 PM PDT 24
Finished Jul 20 04:44:02 PM PDT 24
Peak memory 191592 kb
Host smart-a36f2716-d8bc-4d67-bfbd-b1faf0f245b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910873691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.3910873691
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.2155585113
Short name T241
Test name
Test status
Simulation time 87838141925 ps
CPU time 72.01 seconds
Started Jul 20 04:33:33 PM PDT 24
Finished Jul 20 04:34:54 PM PDT 24
Peak memory 191700 kb
Host smart-af7ff666-cd4c-4c15-861a-cda3008de63f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155585113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.2155585113
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.3809247467
Short name T205
Test name
Test status
Simulation time 154380202307 ps
CPU time 379.36 seconds
Started Jul 20 04:33:40 PM PDT 24
Finished Jul 20 04:40:06 PM PDT 24
Peak memory 191588 kb
Host smart-3632e24f-44cc-4dc6-b587-101cd3783228
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809247467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.3809247467
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.3365652461
Short name T117
Test name
Test status
Simulation time 736387717407 ps
CPU time 349.47 seconds
Started Jul 20 04:32:36 PM PDT 24
Finished Jul 20 04:38:28 PM PDT 24
Peak memory 183432 kb
Host smart-80cea48f-86b8-4460-b3b6-cbe88ea3ee27
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365652461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.3365652461
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.3577635013
Short name T405
Test name
Test status
Simulation time 413601098639 ps
CPU time 193.5 seconds
Started Jul 20 04:32:30 PM PDT 24
Finished Jul 20 04:35:46 PM PDT 24
Peak memory 183292 kb
Host smart-e6bacff8-73db-4503-ad25-405332fb9bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577635013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.3577635013
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.1071274993
Short name T181
Test name
Test status
Simulation time 308702009913 ps
CPU time 265.78 seconds
Started Jul 20 04:32:36 PM PDT 24
Finished Jul 20 04:37:07 PM PDT 24
Peak memory 191636 kb
Host smart-04c3348a-8eeb-4c87-bafe-aed15a63d70c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071274993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.1071274993
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.3950865989
Short name T287
Test name
Test status
Simulation time 99954736990 ps
CPU time 74.38 seconds
Started Jul 20 04:32:36 PM PDT 24
Finished Jul 20 04:33:53 PM PDT 24
Peak memory 183340 kb
Host smart-80302670-9d81-438e-b67b-e4079760221d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950865989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.3950865989
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.160577464
Short name T15
Test name
Test status
Simulation time 313481575 ps
CPU time 0.88 seconds
Started Jul 20 04:32:44 PM PDT 24
Finished Jul 20 04:32:46 PM PDT 24
Peak memory 214748 kb
Host smart-827985f0-2345-4d91-bdee-2b7690c18983
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160577464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.160577464
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.2466969071
Short name T381
Test name
Test status
Simulation time 143121397179 ps
CPU time 104.98 seconds
Started Jul 20 04:33:17 PM PDT 24
Finished Jul 20 04:35:06 PM PDT 24
Peak memory 183396 kb
Host smart-a07f14af-b8b9-4e22-ac59-e1cf689c3ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466969071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.2466969071
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.740936391
Short name T47
Test name
Test status
Simulation time 89482700013 ps
CPU time 140.35 seconds
Started Jul 20 04:33:12 PM PDT 24
Finished Jul 20 04:35:34 PM PDT 24
Peak memory 191564 kb
Host smart-07ed48ba-afb7-4f70-a6a9-d027506512d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740936391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.740936391
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.2279727444
Short name T291
Test name
Test status
Simulation time 2110742798481 ps
CPU time 1273.11 seconds
Started Jul 20 04:32:39 PM PDT 24
Finished Jul 20 04:53:55 PM PDT 24
Peak memory 183324 kb
Host smart-967b2f1b-810e-4860-9f9c-e2e3c145d2e8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279727444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.2279727444
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.1354860070
Short name T413
Test name
Test status
Simulation time 187788619211 ps
CPU time 67.46 seconds
Started Jul 20 04:33:01 PM PDT 24
Finished Jul 20 04:34:10 PM PDT 24
Peak memory 183380 kb
Host smart-ca8b4aca-0170-4b3e-a455-dbf53aba96a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354860070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.1354860070
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.3705522349
Short name T352
Test name
Test status
Simulation time 66636987361 ps
CPU time 54.4 seconds
Started Jul 20 04:33:12 PM PDT 24
Finished Jul 20 04:34:08 PM PDT 24
Peak memory 183500 kb
Host smart-2b846a79-9df6-4248-b639-ad5ce466fcbf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705522349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.3705522349
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.3338684174
Short name T387
Test name
Test status
Simulation time 215471463121 ps
CPU time 148.49 seconds
Started Jul 20 04:33:09 PM PDT 24
Finished Jul 20 04:35:38 PM PDT 24
Peak memory 183372 kb
Host smart-5fab2371-78d9-4277-9e80-a783f96f95c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338684174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.3338684174
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.2321492622
Short name T135
Test name
Test status
Simulation time 80815131510 ps
CPU time 1539.04 seconds
Started Jul 20 04:32:58 PM PDT 24
Finished Jul 20 04:58:42 PM PDT 24
Peak memory 191568 kb
Host smart-d85ed94e-2b1a-44a6-9af0-cb29e79208a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321492622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.2321492622
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.3426261895
Short name T327
Test name
Test status
Simulation time 6534071983 ps
CPU time 12.33 seconds
Started Jul 20 04:32:51 PM PDT 24
Finished Jul 20 04:33:05 PM PDT 24
Peak memory 183388 kb
Host smart-34c3a8a4-c640-48b4-9e4a-e65ba3c992f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426261895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.3426261895
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.3131462487
Short name T165
Test name
Test status
Simulation time 209853307885 ps
CPU time 321.22 seconds
Started Jul 20 04:32:55 PM PDT 24
Finished Jul 20 04:38:17 PM PDT 24
Peak memory 183372 kb
Host smart-7cc01d6b-0e5b-4c14-b832-f4bde770a406
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131462487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.3131462487
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.1831453345
Short name T382
Test name
Test status
Simulation time 761792097663 ps
CPU time 287.03 seconds
Started Jul 20 04:32:59 PM PDT 24
Finished Jul 20 04:37:46 PM PDT 24
Peak memory 183432 kb
Host smart-c2b1703c-6848-4a5f-b74a-3cae4bc1b6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831453345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.1831453345
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.1637273133
Short name T277
Test name
Test status
Simulation time 417490558291 ps
CPU time 266.44 seconds
Started Jul 20 04:33:09 PM PDT 24
Finished Jul 20 04:37:37 PM PDT 24
Peak memory 191536 kb
Host smart-a3faa7ef-820a-4583-8034-48b56d714333
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637273133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.1637273133
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.1023893588
Short name T406
Test name
Test status
Simulation time 42719394984 ps
CPU time 374.89 seconds
Started Jul 20 04:32:46 PM PDT 24
Finished Jul 20 04:39:03 PM PDT 24
Peak memory 191628 kb
Host smart-74e9cf1f-937d-405d-8d89-bb48e75ae9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023893588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.1023893588
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.1555063315
Short name T332
Test name
Test status
Simulation time 16344196867 ps
CPU time 9.14 seconds
Started Jul 20 04:33:03 PM PDT 24
Finished Jul 20 04:33:13 PM PDT 24
Peak memory 183328 kb
Host smart-7388e030-7c08-4945-8089-ce7c0d40c8fb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555063315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.1555063315
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.3954221375
Short name T385
Test name
Test status
Simulation time 60321127949 ps
CPU time 47.21 seconds
Started Jul 20 04:32:55 PM PDT 24
Finished Jul 20 04:33:43 PM PDT 24
Peak memory 183420 kb
Host smart-2a0f76f6-69f3-45f3-bee3-deb1068551a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954221375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.3954221375
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.4208886135
Short name T134
Test name
Test status
Simulation time 132517381747 ps
CPU time 211.88 seconds
Started Jul 20 04:33:09 PM PDT 24
Finished Jul 20 04:36:42 PM PDT 24
Peak memory 191584 kb
Host smart-760d3503-7f55-4491-b5c4-8eb6585e0fc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208886135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.4208886135
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.1979671255
Short name T334
Test name
Test status
Simulation time 69385760857 ps
CPU time 344.62 seconds
Started Jul 20 04:32:52 PM PDT 24
Finished Jul 20 04:38:37 PM PDT 24
Peak memory 183428 kb
Host smart-1fd7a258-209d-473e-8291-9412a1d95c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979671255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.1979671255
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.3035784884
Short name T3
Test name
Test status
Simulation time 137411368340 ps
CPU time 235.47 seconds
Started Jul 20 04:33:14 PM PDT 24
Finished Jul 20 04:37:12 PM PDT 24
Peak memory 183336 kb
Host smart-3d387c6d-f523-459b-82e1-ea49c6614a5b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035784884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.3035784884
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.3332972180
Short name T369
Test name
Test status
Simulation time 41095911765 ps
CPU time 61.56 seconds
Started Jul 20 04:33:07 PM PDT 24
Finished Jul 20 04:34:09 PM PDT 24
Peak memory 183356 kb
Host smart-a619f9ce-529e-4067-8434-6e0182d9b023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332972180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.3332972180
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.1895020742
Short name T432
Test name
Test status
Simulation time 49535714730 ps
CPU time 75.46 seconds
Started Jul 20 04:33:07 PM PDT 24
Finished Jul 20 04:34:23 PM PDT 24
Peak memory 183456 kb
Host smart-7ba1bba9-2417-4285-bfb2-99e7cebec532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895020742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.1895020742
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all_with_rand_reset.1519943542
Short name T11
Test name
Test status
Simulation time 4710425838 ps
CPU time 22.43 seconds
Started Jul 20 04:33:03 PM PDT 24
Finished Jul 20 04:33:26 PM PDT 24
Peak memory 198072 kb
Host smart-35c274e5-96b6-45f1-827d-a6e9529ff7e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519943542 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all_with_rand_reset.1519943542
Directory /workspace/25.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.1047862257
Short name T349
Test name
Test status
Simulation time 1422630083516 ps
CPU time 591.22 seconds
Started Jul 20 04:32:37 PM PDT 24
Finished Jul 20 04:42:31 PM PDT 24
Peak memory 183428 kb
Host smart-1503d5cd-c4de-4280-96b9-41c7ba7f60fa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047862257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.1047862257
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.281927410
Short name T363
Test name
Test status
Simulation time 134971119156 ps
CPU time 208.18 seconds
Started Jul 20 04:33:09 PM PDT 24
Finished Jul 20 04:36:38 PM PDT 24
Peak memory 183396 kb
Host smart-938112fd-e630-4506-95f1-98c1a969ad37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281927410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.281927410
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.3727676673
Short name T344
Test name
Test status
Simulation time 106662514227 ps
CPU time 414.75 seconds
Started Jul 20 04:33:18 PM PDT 24
Finished Jul 20 04:40:19 PM PDT 24
Peak memory 191612 kb
Host smart-2c8c4e21-de3b-4d5f-856b-9cf59c8a57fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727676673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.3727676673
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.384488774
Short name T361
Test name
Test status
Simulation time 25178079210 ps
CPU time 4.04 seconds
Started Jul 20 04:32:45 PM PDT 24
Finished Jul 20 04:32:51 PM PDT 24
Peak memory 191632 kb
Host smart-a4824dd0-256e-452c-a386-c70ef3734bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384488774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.384488774
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.2199317312
Short name T86
Test name
Test status
Simulation time 201562868377 ps
CPU time 224.03 seconds
Started Jul 20 04:32:55 PM PDT 24
Finished Jul 20 04:36:40 PM PDT 24
Peak memory 183396 kb
Host smart-d09b5b26-6fda-4b33-a26b-f5f4026761cc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199317312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.2199317312
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.3677985356
Short name T374
Test name
Test status
Simulation time 198573126066 ps
CPU time 232.49 seconds
Started Jul 20 04:33:04 PM PDT 24
Finished Jul 20 04:36:58 PM PDT 24
Peak memory 183396 kb
Host smart-0c00952b-866c-47b1-bd61-82b0499cb820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677985356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.3677985356
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.163264109
Short name T288
Test name
Test status
Simulation time 150813659630 ps
CPU time 132.83 seconds
Started Jul 20 04:33:16 PM PDT 24
Finished Jul 20 04:35:32 PM PDT 24
Peak memory 183432 kb
Host smart-8b508a5c-15a7-4d59-a857-fa51277006cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163264109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.163264109
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.2001637669
Short name T81
Test name
Test status
Simulation time 129353243 ps
CPU time 0.72 seconds
Started Jul 20 04:33:17 PM PDT 24
Finished Jul 20 04:33:22 PM PDT 24
Peak memory 183216 kb
Host smart-99c0f34e-3651-495c-a495-af7a5fed6249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001637669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.2001637669
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all_with_rand_reset.3551789437
Short name T435
Test name
Test status
Simulation time 134382855458 ps
CPU time 313.88 seconds
Started Jul 20 04:33:02 PM PDT 24
Finished Jul 20 04:38:17 PM PDT 24
Peak memory 198116 kb
Host smart-a24538f8-5b14-4968-8b57-4f763c1be1ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551789437 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all_with_rand_reset.3551789437
Directory /workspace/27.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.3425335859
Short name T324
Test name
Test status
Simulation time 5833900794568 ps
CPU time 1534.01 seconds
Started Jul 20 04:33:07 PM PDT 24
Finished Jul 20 04:58:42 PM PDT 24
Peak memory 183328 kb
Host smart-884ae1df-b75a-4a79-a40b-c9e62385e209
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425335859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.3425335859
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.1406955795
Short name T421
Test name
Test status
Simulation time 450431472507 ps
CPU time 171.04 seconds
Started Jul 20 04:33:18 PM PDT 24
Finished Jul 20 04:36:14 PM PDT 24
Peak memory 183432 kb
Host smart-dc7d6744-821d-46e9-a8f2-a3d1936273ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406955795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.1406955795
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.3164091518
Short name T298
Test name
Test status
Simulation time 53651137030 ps
CPU time 83.45 seconds
Started Jul 20 04:32:51 PM PDT 24
Finished Jul 20 04:34:16 PM PDT 24
Peak memory 191628 kb
Host smart-51c8607c-8ac8-4616-ac7f-49a7665d5710
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164091518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.3164091518
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.216768020
Short name T21
Test name
Test status
Simulation time 58487634159 ps
CPU time 56.44 seconds
Started Jul 20 04:33:01 PM PDT 24
Finished Jul 20 04:33:58 PM PDT 24
Peak memory 195580 kb
Host smart-45e841f8-eeb0-40b6-a63c-42818264d076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216768020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.216768020
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.3968680221
Short name T194
Test name
Test status
Simulation time 108311895731 ps
CPU time 441.24 seconds
Started Jul 20 04:33:13 PM PDT 24
Finished Jul 20 04:40:36 PM PDT 24
Peak memory 195700 kb
Host smart-4edfcf86-b70f-4c7c-9949-9b7f6fadb39c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968680221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.3968680221
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.2827555207
Short name T156
Test name
Test status
Simulation time 253290763694 ps
CPU time 129.89 seconds
Started Jul 20 04:33:14 PM PDT 24
Finished Jul 20 04:35:26 PM PDT 24
Peak memory 183428 kb
Host smart-cab1c2a8-6a44-4530-9857-a7c060e52c38
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827555207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.2827555207
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.75534302
Short name T379
Test name
Test status
Simulation time 144713646087 ps
CPU time 114.6 seconds
Started Jul 20 04:33:19 PM PDT 24
Finished Jul 20 04:35:19 PM PDT 24
Peak memory 183420 kb
Host smart-0d5b6a50-86e6-4738-9360-34700f5c8d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75534302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.75534302
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.3696493962
Short name T253
Test name
Test status
Simulation time 34415824372 ps
CPU time 83.08 seconds
Started Jul 20 04:33:12 PM PDT 24
Finished Jul 20 04:34:37 PM PDT 24
Peak memory 183456 kb
Host smart-59fcecab-a5de-4ab3-8869-b2d0543e0382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696493962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.3696493962
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.2989399405
Short name T289
Test name
Test status
Simulation time 1349649121717 ps
CPU time 2063.3 seconds
Started Jul 20 04:32:48 PM PDT 24
Finished Jul 20 05:07:12 PM PDT 24
Peak memory 196324 kb
Host smart-963af3e4-26fb-4e28-9775-8795dcf5d848
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989399405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.2989399405
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.709638361
Short name T428
Test name
Test status
Simulation time 1906460937783 ps
CPU time 1008.42 seconds
Started Jul 20 04:32:44 PM PDT 24
Finished Jul 20 04:49:34 PM PDT 24
Peak memory 183312 kb
Host smart-a0cf7a50-edd6-4749-8e73-43860e397579
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709638361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.rv_timer_cfg_update_on_fly.709638361
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.1716625226
Short name T76
Test name
Test status
Simulation time 41475734778 ps
CPU time 63.65 seconds
Started Jul 20 04:32:47 PM PDT 24
Finished Jul 20 04:33:52 PM PDT 24
Peak memory 183388 kb
Host smart-539f45b2-dc2c-47f4-a7c8-7a3d73ad6745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716625226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.1716625226
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.1420952478
Short name T83
Test name
Test status
Simulation time 168764087300 ps
CPU time 135.23 seconds
Started Jul 20 04:32:34 PM PDT 24
Finished Jul 20 04:34:53 PM PDT 24
Peak memory 191516 kb
Host smart-06e28a8a-01e3-43fe-81ed-e8a5f447fc21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420952478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.1420952478
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.925113919
Short name T364
Test name
Test status
Simulation time 851494193 ps
CPU time 0.98 seconds
Started Jul 20 04:32:52 PM PDT 24
Finished Jul 20 04:32:54 PM PDT 24
Peak memory 183188 kb
Host smart-445feadb-2346-44ea-a968-149649204b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925113919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.925113919
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.4089870948
Short name T14
Test name
Test status
Simulation time 85540285 ps
CPU time 0.94 seconds
Started Jul 20 04:32:44 PM PDT 24
Finished Jul 20 04:32:47 PM PDT 24
Peak memory 214680 kb
Host smart-93051dba-66f0-495f-b11a-7590ce6fa7d0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089870948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.4089870948
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.4216603931
Short name T373
Test name
Test status
Simulation time 215870014376 ps
CPU time 89.12 seconds
Started Jul 20 04:32:40 PM PDT 24
Finished Jul 20 04:34:12 PM PDT 24
Peak memory 195124 kb
Host smart-bb8d617b-c302-4d04-8006-670b728f7a24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216603931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
4216603931
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.2401034413
Short name T341
Test name
Test status
Simulation time 425537239205 ps
CPU time 688.34 seconds
Started Jul 20 04:33:10 PM PDT 24
Finished Jul 20 04:44:39 PM PDT 24
Peak memory 183376 kb
Host smart-e48a579d-caaa-47ca-abb8-75d1c742234b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401034413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.2401034413
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.2408411872
Short name T426
Test name
Test status
Simulation time 196477119756 ps
CPU time 68.71 seconds
Started Jul 20 04:33:32 PM PDT 24
Finished Jul 20 04:34:49 PM PDT 24
Peak memory 183424 kb
Host smart-e015a7b3-1eef-4f56-a11b-187733dc7cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408411872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.2408411872
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.3191935306
Short name T204
Test name
Test status
Simulation time 185971562902 ps
CPU time 502.29 seconds
Started Jul 20 04:33:10 PM PDT 24
Finished Jul 20 04:41:33 PM PDT 24
Peak memory 183440 kb
Host smart-f2a9cc77-8239-483c-9bd1-fd365742939e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191935306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.3191935306
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.2274419345
Short name T175
Test name
Test status
Simulation time 53531853443 ps
CPU time 90.45 seconds
Started Jul 20 04:33:11 PM PDT 24
Finished Jul 20 04:34:43 PM PDT 24
Peak memory 191580 kb
Host smart-b4fc9a39-5438-4a72-9ee2-eab85b6a482e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274419345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.2274419345
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.993396638
Short name T69
Test name
Test status
Simulation time 1216166182434 ps
CPU time 755.95 seconds
Started Jul 20 04:33:21 PM PDT 24
Finished Jul 20 04:46:04 PM PDT 24
Peak memory 195532 kb
Host smart-4452ef44-afff-47d5-9b5f-bf74769ca92a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993396638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all.
993396638
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all_with_rand_reset.867461492
Short name T35
Test name
Test status
Simulation time 23501720728 ps
CPU time 155.88 seconds
Started Jul 20 04:33:04 PM PDT 24
Finished Jul 20 04:35:41 PM PDT 24
Peak memory 198136 kb
Host smart-69471f07-7816-4dd6-94d0-6c102e83aed2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867461492 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all_with_rand_reset.867461492
Directory /workspace/30.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.1890364196
Short name T62
Test name
Test status
Simulation time 212859128364 ps
CPU time 320.74 seconds
Started Jul 20 04:33:12 PM PDT 24
Finished Jul 20 04:38:34 PM PDT 24
Peak memory 183368 kb
Host smart-7d86dd8a-9897-4166-a7dc-5cc05e1e1d8a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890364196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.1890364196
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.156895801
Short name T440
Test name
Test status
Simulation time 17418101392 ps
CPU time 28.1 seconds
Started Jul 20 04:33:01 PM PDT 24
Finished Jul 20 04:33:30 PM PDT 24
Peak memory 183432 kb
Host smart-55962001-f622-4ca1-9ad5-b9f453c10650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156895801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.156895801
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.2114093657
Short name T419
Test name
Test status
Simulation time 175381612108 ps
CPU time 144.24 seconds
Started Jul 20 04:33:02 PM PDT 24
Finished Jul 20 04:35:27 PM PDT 24
Peak memory 191576 kb
Host smart-d9832dbc-682b-4e87-aa59-43eb7a45f9fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114093657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.2114093657
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.3187920517
Short name T318
Test name
Test status
Simulation time 123226153914 ps
CPU time 39.45 seconds
Started Jul 20 04:33:19 PM PDT 24
Finished Jul 20 04:34:04 PM PDT 24
Peak memory 183376 kb
Host smart-d50d15ff-2ff8-4647-bbfd-633b09038ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187920517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.3187920517
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.289175883
Short name T415
Test name
Test status
Simulation time 270277545609 ps
CPU time 403.43 seconds
Started Jul 20 04:33:14 PM PDT 24
Finished Jul 20 04:39:59 PM PDT 24
Peak memory 191572 kb
Host smart-25f38e51-cbbf-4f7c-9ab1-be6b07cd048e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289175883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all.
289175883
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.3352789016
Short name T161
Test name
Test status
Simulation time 4215730820171 ps
CPU time 891.74 seconds
Started Jul 20 04:33:08 PM PDT 24
Finished Jul 20 04:48:01 PM PDT 24
Peak memory 183372 kb
Host smart-32d251e4-0d91-4af6-bc0b-662b8028c6f0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352789016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.3352789016
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.2611326909
Short name T376
Test name
Test status
Simulation time 70483996079 ps
CPU time 12.53 seconds
Started Jul 20 04:33:04 PM PDT 24
Finished Jul 20 04:33:18 PM PDT 24
Peak memory 183404 kb
Host smart-24ed1a56-f55b-4e88-b97b-d45e236d9d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611326909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.2611326909
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.329246007
Short name T77
Test name
Test status
Simulation time 74244158689 ps
CPU time 148.72 seconds
Started Jul 20 04:33:03 PM PDT 24
Finished Jul 20 04:35:34 PM PDT 24
Peak memory 195120 kb
Host smart-c6c50f4a-9a88-4b3b-bf83-840c7f7020b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329246007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.329246007
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.3075739011
Short name T367
Test name
Test status
Simulation time 53516049 ps
CPU time 0.62 seconds
Started Jul 20 04:33:02 PM PDT 24
Finished Jul 20 04:33:03 PM PDT 24
Peak memory 183220 kb
Host smart-22d6aac9-2323-4331-b1b4-dd8d0fa0cb51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075739011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.3075739011
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.2268185586
Short name T66
Test name
Test status
Simulation time 263949858970 ps
CPU time 102.41 seconds
Started Jul 20 04:33:07 PM PDT 24
Finished Jul 20 04:34:50 PM PDT 24
Peak memory 193960 kb
Host smart-94f5b32d-ac86-4108-a5e2-3f1a71760545
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268185586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.2268185586
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.643753160
Short name T284
Test name
Test status
Simulation time 308600531018 ps
CPU time 168.81 seconds
Started Jul 20 04:33:17 PM PDT 24
Finished Jul 20 04:36:09 PM PDT 24
Peak memory 183372 kb
Host smart-6a02611c-5190-4a32-bb7a-eb542c3a6e42
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643753160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.rv_timer_cfg_update_on_fly.643753160
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.3676722288
Short name T412
Test name
Test status
Simulation time 104386982601 ps
CPU time 140.82 seconds
Started Jul 20 04:33:11 PM PDT 24
Finished Jul 20 04:35:33 PM PDT 24
Peak memory 183452 kb
Host smart-1478aab6-9197-4d81-b838-cd7ddc2bd79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676722288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.3676722288
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.435740250
Short name T201
Test name
Test status
Simulation time 636425063856 ps
CPU time 207.7 seconds
Started Jul 20 04:33:14 PM PDT 24
Finished Jul 20 04:36:44 PM PDT 24
Peak memory 191644 kb
Host smart-890c3825-dd25-4456-a775-be125a8cea6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435740250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.435740250
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.2768645275
Short name T68
Test name
Test status
Simulation time 59731178 ps
CPU time 0.57 seconds
Started Jul 20 04:33:15 PM PDT 24
Finished Jul 20 04:33:18 PM PDT 24
Peak memory 183148 kb
Host smart-932c6de8-a119-4991-bf0a-b16dd331a5b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768645275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.2768645275
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all_with_rand_reset.3680852562
Short name T50
Test name
Test status
Simulation time 11152150152 ps
CPU time 76.42 seconds
Started Jul 20 04:33:11 PM PDT 24
Finished Jul 20 04:34:29 PM PDT 24
Peak memory 198084 kb
Host smart-b2f5897b-5ca2-4c35-aa94-38e9a80454ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680852562 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all_with_rand_reset.3680852562
Directory /workspace/33.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.3306587106
Short name T333
Test name
Test status
Simulation time 433978408229 ps
CPU time 217.81 seconds
Started Jul 20 04:33:18 PM PDT 24
Finished Jul 20 04:37:01 PM PDT 24
Peak memory 183480 kb
Host smart-b20ed991-1660-41c7-8ebc-927c353ca22a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306587106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.3306587106
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_random.460660805
Short name T267
Test name
Test status
Simulation time 68433418718 ps
CPU time 96.91 seconds
Started Jul 20 04:33:14 PM PDT 24
Finished Jul 20 04:34:53 PM PDT 24
Peak memory 191632 kb
Host smart-3c4c8e2a-5335-4560-80cf-61a9a3080a09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460660805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.460660805
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.2225025911
Short name T422
Test name
Test status
Simulation time 1257559093 ps
CPU time 2.36 seconds
Started Jul 20 04:33:08 PM PDT 24
Finished Jul 20 04:33:11 PM PDT 24
Peak memory 192164 kb
Host smart-dfcfabac-62c6-432d-ac79-5b2af1bfb7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225025911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.2225025911
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.2611000297
Short name T335
Test name
Test status
Simulation time 65204902512 ps
CPU time 79.59 seconds
Started Jul 20 04:33:19 PM PDT 24
Finished Jul 20 04:34:44 PM PDT 24
Peak memory 183436 kb
Host smart-17e6c68c-8a2a-4d8f-8b53-f7cbf3915d3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611000297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.2611000297
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.1915661260
Short name T414
Test name
Test status
Simulation time 655352209835 ps
CPU time 521.13 seconds
Started Jul 20 04:33:02 PM PDT 24
Finished Jul 20 04:41:44 PM PDT 24
Peak memory 183424 kb
Host smart-30292dd1-9c4f-4927-a35e-ac2187256d31
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915661260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.1915661260
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.3675487940
Short name T420
Test name
Test status
Simulation time 94328335723 ps
CPU time 136.11 seconds
Started Jul 20 04:33:13 PM PDT 24
Finished Jul 20 04:35:31 PM PDT 24
Peak memory 183448 kb
Host smart-7a8d0548-0e15-421c-b7e4-2f49afe591a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675487940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.3675487940
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.3549903619
Short name T209
Test name
Test status
Simulation time 291543315124 ps
CPU time 214.43 seconds
Started Jul 20 04:33:11 PM PDT 24
Finished Jul 20 04:36:46 PM PDT 24
Peak memory 191640 kb
Host smart-74714131-f8cd-47c4-9b1b-f36e631e89a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549903619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.3549903619
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.1808885364
Short name T149
Test name
Test status
Simulation time 138329811521 ps
CPU time 311.36 seconds
Started Jul 20 04:33:04 PM PDT 24
Finished Jul 20 04:38:17 PM PDT 24
Peak memory 191552 kb
Host smart-cfe095c9-8ab2-4378-82da-67fefc859bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808885364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.1808885364
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.3694756305
Short name T394
Test name
Test status
Simulation time 208843903084 ps
CPU time 155.14 seconds
Started Jul 20 04:32:46 PM PDT 24
Finished Jul 20 04:35:23 PM PDT 24
Peak memory 191688 kb
Host smart-d84afb56-c3d5-480d-afce-2039ad9cfd3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694756305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.3694756305
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all_with_rand_reset.4165081290
Short name T36
Test name
Test status
Simulation time 111875797434 ps
CPU time 800.8 seconds
Started Jul 20 04:33:15 PM PDT 24
Finished Jul 20 04:46:38 PM PDT 24
Peak memory 207364 kb
Host smart-29d0d1e9-2f94-445c-9b3f-458f728c2711
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165081290 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all_with_rand_reset.4165081290
Directory /workspace/35.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.4240176673
Short name T276
Test name
Test status
Simulation time 8366627479 ps
CPU time 15.08 seconds
Started Jul 20 04:33:19 PM PDT 24
Finished Jul 20 04:33:40 PM PDT 24
Peak memory 183368 kb
Host smart-966560bf-2fd5-45bc-943d-9f08aa59cd7e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240176673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.4240176673
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.3328396178
Short name T23
Test name
Test status
Simulation time 234832559454 ps
CPU time 44.36 seconds
Started Jul 20 04:33:16 PM PDT 24
Finished Jul 20 04:34:03 PM PDT 24
Peak memory 183444 kb
Host smart-ec5b117e-3f3a-4fa8-bbb2-4331ea8018f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328396178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.3328396178
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.1079312334
Short name T131
Test name
Test status
Simulation time 514241377035 ps
CPU time 256.95 seconds
Started Jul 20 04:32:57 PM PDT 24
Finished Jul 20 04:37:15 PM PDT 24
Peak memory 194972 kb
Host smart-410afee1-8779-4ec0-9231-2f14e513f97d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079312334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.1079312334
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.1139085127
Short name T236
Test name
Test status
Simulation time 832079293514 ps
CPU time 344.67 seconds
Started Jul 20 04:33:21 PM PDT 24
Finished Jul 20 04:39:12 PM PDT 24
Peak memory 191572 kb
Host smart-626129d9-3acc-4bf6-a887-297d9bdbb2e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139085127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.1139085127
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all_with_rand_reset.2729892003
Short name T438
Test name
Test status
Simulation time 113443350504 ps
CPU time 539.37 seconds
Started Jul 20 04:33:17 PM PDT 24
Finished Jul 20 04:42:21 PM PDT 24
Peak memory 207440 kb
Host smart-d4234596-6b11-4a89-ae44-8fe6f3ae025a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729892003 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all_with_rand_reset.2729892003
Directory /workspace/36.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.623384594
Short name T350
Test name
Test status
Simulation time 219753215569 ps
CPU time 123.78 seconds
Started Jul 20 04:33:08 PM PDT 24
Finished Jul 20 04:35:13 PM PDT 24
Peak memory 183440 kb
Host smart-65ac21b3-a67d-4389-81c6-388f4c032946
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623384594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.rv_timer_cfg_update_on_fly.623384594
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.3382243588
Short name T399
Test name
Test status
Simulation time 82764221368 ps
CPU time 59.49 seconds
Started Jul 20 04:33:22 PM PDT 24
Finished Jul 20 04:34:28 PM PDT 24
Peak memory 183724 kb
Host smart-37788d4a-244b-44d4-8033-d7ed6e1593c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382243588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.3382243588
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.3740715839
Short name T312
Test name
Test status
Simulation time 17051330352 ps
CPU time 93.38 seconds
Started Jul 20 04:33:05 PM PDT 24
Finished Jul 20 04:34:40 PM PDT 24
Peak memory 194868 kb
Host smart-9aee1ac2-e104-405f-b403-ea4eed1804f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740715839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.3740715839
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.2438355169
Short name T206
Test name
Test status
Simulation time 31749266512 ps
CPU time 27.69 seconds
Started Jul 20 04:33:18 PM PDT 24
Finished Jul 20 04:33:51 PM PDT 24
Peak memory 183432 kb
Host smart-b1963649-e5b4-4f6c-bc70-e72872682e88
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438355169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.2438355169
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.1036974480
Short name T437
Test name
Test status
Simulation time 146080857893 ps
CPU time 113.66 seconds
Started Jul 20 04:33:22 PM PDT 24
Finished Jul 20 04:35:23 PM PDT 24
Peak memory 183432 kb
Host smart-bee1131b-5721-4649-823b-3e5a17617c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036974480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.1036974480
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.2276817077
Short name T308
Test name
Test status
Simulation time 16036391570 ps
CPU time 22.52 seconds
Started Jul 20 04:33:13 PM PDT 24
Finished Jul 20 04:33:38 PM PDT 24
Peak memory 183432 kb
Host smart-93bd335f-fbe7-4297-a954-2c99ed0a6f7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276817077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.2276817077
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.270432169
Short name T215
Test name
Test status
Simulation time 91255270253 ps
CPU time 171.87 seconds
Started Jul 20 04:33:19 PM PDT 24
Finished Jul 20 04:36:17 PM PDT 24
Peak memory 183224 kb
Host smart-cb2e71b8-8ac9-4061-9e1c-108fe1ce8ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270432169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.270432169
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.2125490577
Short name T43
Test name
Test status
Simulation time 492290744151 ps
CPU time 211.29 seconds
Started Jul 20 04:33:05 PM PDT 24
Finished Jul 20 04:36:38 PM PDT 24
Peak memory 183388 kb
Host smart-99df00b5-cfcf-4cbc-92e9-1adbde7da18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125490577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.2125490577
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.382405354
Short name T25
Test name
Test status
Simulation time 179882043616 ps
CPU time 144.11 seconds
Started Jul 20 04:33:15 PM PDT 24
Finished Jul 20 04:35:41 PM PDT 24
Peak memory 183436 kb
Host smart-1c8a8ec9-1f60-40d2-a6fe-9062f2762d01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382405354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.382405354
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.3079037978
Short name T139
Test name
Test status
Simulation time 28129342449 ps
CPU time 200.01 seconds
Started Jul 20 04:33:17 PM PDT 24
Finished Jul 20 04:36:41 PM PDT 24
Peak memory 191564 kb
Host smart-46c76bcd-f61d-4bc9-9ad7-cd46f67752bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079037978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.3079037978
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all_with_rand_reset.901903111
Short name T13
Test name
Test status
Simulation time 43012393004 ps
CPU time 154.78 seconds
Started Jul 20 04:33:18 PM PDT 24
Finished Jul 20 04:35:57 PM PDT 24
Peak memory 198416 kb
Host smart-a3cccee7-9407-4f67-a180-99a7ad27b01c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901903111 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all_with_rand_reset.901903111
Directory /workspace/39.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.3508841667
Short name T354
Test name
Test status
Simulation time 757787546416 ps
CPU time 392.42 seconds
Started Jul 20 04:32:46 PM PDT 24
Finished Jul 20 04:39:20 PM PDT 24
Peak memory 183480 kb
Host smart-a58f6c88-dcc6-45f9-b997-ee0b1e4ba275
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508841667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.3508841667
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.1380952066
Short name T403
Test name
Test status
Simulation time 127312336054 ps
CPU time 85.45 seconds
Started Jul 20 04:32:35 PM PDT 24
Finished Jul 20 04:34:04 PM PDT 24
Peak memory 183416 kb
Host smart-33c733e1-37c9-4fc1-9984-d0b5466f9378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380952066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.1380952066
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.1518119534
Short name T7
Test name
Test status
Simulation time 32330525333 ps
CPU time 50.63 seconds
Started Jul 20 04:32:32 PM PDT 24
Finished Jul 20 04:33:26 PM PDT 24
Peak memory 191524 kb
Host smart-cb27db2f-4af0-4561-b876-37803d470217
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518119534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.1518119534
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.877742915
Short name T18
Test name
Test status
Simulation time 179426887 ps
CPU time 0.88 seconds
Started Jul 20 04:32:35 PM PDT 24
Finished Jul 20 04:32:39 PM PDT 24
Peak memory 213212 kb
Host smart-570da1ae-810a-4958-8aa8-bc5f434fbd64
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877742915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.877742915
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.295554339
Short name T423
Test name
Test status
Simulation time 568987620616 ps
CPU time 448.03 seconds
Started Jul 20 04:32:45 PM PDT 24
Finished Jul 20 04:40:15 PM PDT 24
Peak memory 191632 kb
Host smart-4f86614d-ddc9-499f-a1cf-7f600ffdd776
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295554339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.295554339
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.856478105
Short name T27
Test name
Test status
Simulation time 1393431861033 ps
CPU time 654.22 seconds
Started Jul 20 04:33:17 PM PDT 24
Finished Jul 20 04:44:15 PM PDT 24
Peak memory 183704 kb
Host smart-066c558b-15d9-4cd1-b63d-eee16f6828db
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856478105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.rv_timer_cfg_update_on_fly.856478105
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.625062406
Short name T409
Test name
Test status
Simulation time 778507124989 ps
CPU time 185.03 seconds
Started Jul 20 04:33:01 PM PDT 24
Finished Jul 20 04:36:06 PM PDT 24
Peak memory 183332 kb
Host smart-19e6b47b-f1be-4c0d-9545-1abcd06099f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625062406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.625062406
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.3437884286
Short name T122
Test name
Test status
Simulation time 551641026592 ps
CPU time 338.2 seconds
Started Jul 20 04:33:13 PM PDT 24
Finished Jul 20 04:38:53 PM PDT 24
Peak memory 191912 kb
Host smart-a491b58e-c9d0-4e94-93e9-8ee668fbd25d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437884286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.3437884286
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.575729772
Short name T400
Test name
Test status
Simulation time 196332325650 ps
CPU time 70.39 seconds
Started Jul 20 04:33:16 PM PDT 24
Finished Jul 20 04:34:30 PM PDT 24
Peak memory 183708 kb
Host smart-19647023-b70b-4a17-adeb-723099ebde85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575729772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.575729772
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all_with_rand_reset.3367249969
Short name T39
Test name
Test status
Simulation time 99129244037 ps
CPU time 245.92 seconds
Started Jul 20 04:33:11 PM PDT 24
Finished Jul 20 04:37:17 PM PDT 24
Peak memory 198108 kb
Host smart-176efa32-9ece-456d-bb8e-1e08040370a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367249969 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all_with_rand_reset.3367249969
Directory /workspace/40.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.4131546941
Short name T148
Test name
Test status
Simulation time 211729933731 ps
CPU time 330.38 seconds
Started Jul 20 04:33:14 PM PDT 24
Finished Jul 20 04:38:47 PM PDT 24
Peak memory 183700 kb
Host smart-c93247ab-1764-470b-9aa3-d96495224ff2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131546941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.4131546941
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.3473380133
Short name T8
Test name
Test status
Simulation time 109537076535 ps
CPU time 74.62 seconds
Started Jul 20 04:33:03 PM PDT 24
Finished Jul 20 04:34:19 PM PDT 24
Peak memory 183396 kb
Host smart-ae3fb48b-2bfc-4e9b-bd03-8aba22f422b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473380133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.3473380133
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.2745348163
Short name T302
Test name
Test status
Simulation time 35651914632 ps
CPU time 51.75 seconds
Started Jul 20 04:33:24 PM PDT 24
Finished Jul 20 04:34:23 PM PDT 24
Peak memory 183424 kb
Host smart-5c25a916-87f4-4741-9da7-4d4c91f770c7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745348163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.2745348163
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.700624928
Short name T2
Test name
Test status
Simulation time 342268973214 ps
CPU time 95.25 seconds
Started Jul 20 04:33:19 PM PDT 24
Finished Jul 20 04:35:00 PM PDT 24
Peak memory 182544 kb
Host smart-447052b9-cd1b-42a5-b6eb-8ea767f1a9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700624928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.700624928
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.2777402460
Short name T212
Test name
Test status
Simulation time 109817894534 ps
CPU time 942.29 seconds
Started Jul 20 04:33:16 PM PDT 24
Finished Jul 20 04:49:02 PM PDT 24
Peak memory 191640 kb
Host smart-85342a95-b333-41df-9b98-10c80c97d08d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777402460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.2777402460
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.685112795
Short name T56
Test name
Test status
Simulation time 771499336969 ps
CPU time 532.82 seconds
Started Jul 20 04:33:22 PM PDT 24
Finished Jul 20 04:42:22 PM PDT 24
Peak memory 191636 kb
Host smart-751dd1a8-c297-4484-817b-15e760664058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685112795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.685112795
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.2161818033
Short name T383
Test name
Test status
Simulation time 498773223628 ps
CPU time 168.29 seconds
Started Jul 20 04:33:19 PM PDT 24
Finished Jul 20 04:36:13 PM PDT 24
Peak memory 183424 kb
Host smart-5ae6cc5c-cfa7-4814-9781-151c9a213c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161818033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.2161818033
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.1021836993
Short name T311
Test name
Test status
Simulation time 161711015500 ps
CPU time 141.21 seconds
Started Jul 20 04:33:11 PM PDT 24
Finished Jul 20 04:35:33 PM PDT 24
Peak memory 183440 kb
Host smart-22ab5e31-8e93-4fa7-bf96-3f87e4e66b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021836993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.1021836993
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.613105601
Short name T343
Test name
Test status
Simulation time 62681439221 ps
CPU time 30.36 seconds
Started Jul 20 04:33:21 PM PDT 24
Finished Jul 20 04:33:58 PM PDT 24
Peak memory 183372 kb
Host smart-23b66668-3332-48f2-8667-93f12e1a8357
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613105601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.rv_timer_cfg_update_on_fly.613105601
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.1480230659
Short name T429
Test name
Test status
Simulation time 33355175394 ps
CPU time 27.32 seconds
Started Jul 20 04:33:06 PM PDT 24
Finished Jul 20 04:33:34 PM PDT 24
Peak memory 183384 kb
Host smart-a1d5b236-971e-450d-9e24-cfc7d114ffc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480230659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.1480230659
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.213681006
Short name T64
Test name
Test status
Simulation time 42832542001 ps
CPU time 280.7 seconds
Started Jul 20 04:33:15 PM PDT 24
Finished Jul 20 04:37:58 PM PDT 24
Peak memory 191964 kb
Host smart-1c6afd37-df30-4beb-be9b-c460d3f85077
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213681006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.213681006
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.1547480424
Short name T251
Test name
Test status
Simulation time 320317341019 ps
CPU time 270.71 seconds
Started Jul 20 04:33:13 PM PDT 24
Finished Jul 20 04:37:45 PM PDT 24
Peak memory 191676 kb
Host smart-e3a98b48-d40c-4829-9c54-0e884bd3b985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547480424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.1547480424
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.428676796
Short name T323
Test name
Test status
Simulation time 15112271774 ps
CPU time 8.37 seconds
Started Jul 20 04:33:24 PM PDT 24
Finished Jul 20 04:33:39 PM PDT 24
Peak memory 183368 kb
Host smart-457506ce-8fba-4b79-85ea-95802f881a26
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428676796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.rv_timer_cfg_update_on_fly.428676796
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.3735471173
Short name T418
Test name
Test status
Simulation time 7422024506 ps
CPU time 11.56 seconds
Started Jul 20 04:33:16 PM PDT 24
Finished Jul 20 04:33:30 PM PDT 24
Peak memory 183204 kb
Host smart-9581f99d-8b5c-4ce0-9774-9ff57b3b12a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735471173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.3735471173
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.1662257386
Short name T75
Test name
Test status
Simulation time 291488511957 ps
CPU time 171.41 seconds
Started Jul 20 04:33:14 PM PDT 24
Finished Jul 20 04:36:07 PM PDT 24
Peak memory 191640 kb
Host smart-f2dd6903-d950-41ab-948a-5c081e8a3395
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662257386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.1662257386
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.850226273
Short name T5
Test name
Test status
Simulation time 89421352408 ps
CPU time 69.81 seconds
Started Jul 20 04:33:11 PM PDT 24
Finished Jul 20 04:34:22 PM PDT 24
Peak memory 191576 kb
Host smart-0c14a552-09d7-4e53-84bb-0f43109bf4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850226273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.850226273
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.2109661816
Short name T365
Test name
Test status
Simulation time 193217675119 ps
CPU time 69.44 seconds
Started Jul 20 04:33:19 PM PDT 24
Finished Jul 20 04:34:34 PM PDT 24
Peak memory 183440 kb
Host smart-ba57b520-81fb-47e0-a39e-246b539127f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109661816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.2109661816
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.1698239976
Short name T167
Test name
Test status
Simulation time 566585391127 ps
CPU time 509.84 seconds
Started Jul 20 04:33:08 PM PDT 24
Finished Jul 20 04:41:38 PM PDT 24
Peak memory 183700 kb
Host smart-358c6b58-8cf6-487c-b6df-776119e439f8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698239976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.1698239976
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.3029749587
Short name T366
Test name
Test status
Simulation time 170187206194 ps
CPU time 224.55 seconds
Started Jul 20 04:33:16 PM PDT 24
Finished Jul 20 04:37:04 PM PDT 24
Peak memory 183452 kb
Host smart-7fa9a12e-9d26-414f-a07e-7d57c1d964f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029749587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.3029749587
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.3456513355
Short name T410
Test name
Test status
Simulation time 32128663371 ps
CPU time 52.01 seconds
Started Jul 20 04:33:14 PM PDT 24
Finished Jul 20 04:34:08 PM PDT 24
Peak memory 183704 kb
Host smart-7a8c647f-1e76-43ef-b0c9-a5d5ef2b5d1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456513355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.3456513355
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.249551133
Short name T154
Test name
Test status
Simulation time 128276647175 ps
CPU time 212.52 seconds
Started Jul 20 04:33:08 PM PDT 24
Finished Jul 20 04:36:42 PM PDT 24
Peak memory 183708 kb
Host smart-bb1a79e4-58d3-4104-9c72-2eab578b3061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249551133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.249551133
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.2884776618
Short name T116
Test name
Test status
Simulation time 506519267853 ps
CPU time 275.88 seconds
Started Jul 20 04:33:19 PM PDT 24
Finished Jul 20 04:38:01 PM PDT 24
Peak memory 183424 kb
Host smart-e682ae1d-5233-4cf2-a399-be42aba10352
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884776618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.2884776618
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.2124325701
Short name T390
Test name
Test status
Simulation time 92823539958 ps
CPU time 132.4 seconds
Started Jul 20 04:33:18 PM PDT 24
Finished Jul 20 04:35:35 PM PDT 24
Peak memory 183348 kb
Host smart-11f456b7-7d5b-4d5c-a1b3-3f8af2a6412e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124325701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.2124325701
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.331944751
Short name T245
Test name
Test status
Simulation time 82388548516 ps
CPU time 146.67 seconds
Started Jul 20 04:33:23 PM PDT 24
Finished Jul 20 04:35:56 PM PDT 24
Peak memory 191644 kb
Host smart-8b9ccb69-68c8-48ec-9d66-6917c32c53ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331944751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.331944751
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.2512474547
Short name T290
Test name
Test status
Simulation time 43222246940 ps
CPU time 86.65 seconds
Started Jul 20 04:33:18 PM PDT 24
Finished Jul 20 04:34:49 PM PDT 24
Peak memory 183384 kb
Host smart-4c0fc506-a9c7-4e72-b78c-7cc8f8a83421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512474547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.2512474547
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.1749664540
Short name T230
Test name
Test status
Simulation time 118024489481 ps
CPU time 543.08 seconds
Started Jul 20 04:33:15 PM PDT 24
Finished Jul 20 04:42:20 PM PDT 24
Peak memory 195216 kb
Host smart-4fba8dc1-6539-4f58-94b7-bc7275b184ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749664540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.1749664540
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all_with_rand_reset.3281105910
Short name T38
Test name
Test status
Simulation time 104596502138 ps
CPU time 885.33 seconds
Started Jul 20 04:33:15 PM PDT 24
Finished Jul 20 04:48:03 PM PDT 24
Peak memory 214428 kb
Host smart-f77b8c4b-cbbb-46c5-b810-22fcd2598ee8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281105910 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all_with_rand_reset.3281105910
Directory /workspace/47.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.2401438275
Short name T132
Test name
Test status
Simulation time 791990661621 ps
CPU time 378.79 seconds
Started Jul 20 04:33:18 PM PDT 24
Finished Jul 20 04:39:42 PM PDT 24
Peak memory 183372 kb
Host smart-120d5c35-4279-4377-9640-f50138d53dc4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401438275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.2401438275
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.1338086047
Short name T434
Test name
Test status
Simulation time 517346546364 ps
CPU time 169.4 seconds
Started Jul 20 04:33:19 PM PDT 24
Finished Jul 20 04:36:14 PM PDT 24
Peak memory 183484 kb
Host smart-7aaa2ffa-3ba0-4c46-8e77-384019027039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338086047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.1338086047
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.1511819738
Short name T159
Test name
Test status
Simulation time 299596256270 ps
CPU time 1036.39 seconds
Started Jul 20 04:33:20 PM PDT 24
Finished Jul 20 04:50:43 PM PDT 24
Peak memory 191628 kb
Host smart-b679122c-12df-432a-a62a-1e1d36e7b7da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511819738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.1511819738
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.3418602499
Short name T322
Test name
Test status
Simulation time 20003932080 ps
CPU time 34.87 seconds
Started Jul 20 04:33:18 PM PDT 24
Finished Jul 20 04:33:58 PM PDT 24
Peak memory 191744 kb
Host smart-55119af4-9362-49a7-8433-1f0a89de0805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418602499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.3418602499
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.2946549569
Short name T192
Test name
Test status
Simulation time 955818927977 ps
CPU time 1007.91 seconds
Started Jul 20 04:33:30 PM PDT 24
Finished Jul 20 04:50:25 PM PDT 24
Peak memory 191684 kb
Host smart-5e09404f-a3fe-4445-91b4-a71543f82eb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946549569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.2946549569
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all_with_rand_reset.206249704
Short name T51
Test name
Test status
Simulation time 19470369491 ps
CPU time 151.82 seconds
Started Jul 20 04:33:17 PM PDT 24
Finished Jul 20 04:35:54 PM PDT 24
Peak memory 198056 kb
Host smart-ffb5aed2-9091-4e38-9519-c0942fbcea7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206249704 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all_with_rand_reset.206249704
Directory /workspace/48.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.759424048
Short name T304
Test name
Test status
Simulation time 326090482612 ps
CPU time 275.3 seconds
Started Jul 20 04:33:29 PM PDT 24
Finished Jul 20 04:38:12 PM PDT 24
Peak memory 183420 kb
Host smart-00619843-9dc9-4080-8ffa-46c344db5cc7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759424048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.rv_timer_cfg_update_on_fly.759424048
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.3557913524
Short name T370
Test name
Test status
Simulation time 85014669695 ps
CPU time 32.74 seconds
Started Jul 20 04:33:19 PM PDT 24
Finished Jul 20 04:33:58 PM PDT 24
Peak memory 183380 kb
Host smart-8ec2760a-b9da-4cc7-b5f6-8fe0577c0b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557913524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.3557913524
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.3091796770
Short name T210
Test name
Test status
Simulation time 94707422423 ps
CPU time 173.26 seconds
Started Jul 20 04:33:13 PM PDT 24
Finished Jul 20 04:36:08 PM PDT 24
Peak memory 191584 kb
Host smart-7c14ec17-0f6d-46ca-917a-6353126dc7bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091796770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.3091796770
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.206496053
Short name T19
Test name
Test status
Simulation time 4166843218 ps
CPU time 7.68 seconds
Started Jul 20 04:33:22 PM PDT 24
Finished Jul 20 04:33:36 PM PDT 24
Peak memory 183420 kb
Host smart-4dcc97ea-c3c8-4bf6-abf2-c6c713c06747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206496053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.206496053
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.3428191363
Short name T110
Test name
Test status
Simulation time 3261756198981 ps
CPU time 1479.13 seconds
Started Jul 20 04:32:32 PM PDT 24
Finished Jul 20 04:57:15 PM PDT 24
Peak memory 183380 kb
Host smart-71324afe-8aed-4b50-964d-0d14058d2448
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428191363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.3428191363
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.4014025895
Short name T396
Test name
Test status
Simulation time 129055506946 ps
CPU time 87.62 seconds
Started Jul 20 04:32:46 PM PDT 24
Finished Jul 20 04:34:15 PM PDT 24
Peak memory 183324 kb
Host smart-2735c148-ab30-4800-93cb-085e2ff66b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014025895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.4014025895
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.2722997039
Short name T48
Test name
Test status
Simulation time 86071057209 ps
CPU time 156.79 seconds
Started Jul 20 04:32:35 PM PDT 24
Finished Jul 20 04:35:17 PM PDT 24
Peak memory 191252 kb
Host smart-4082baee-1000-4792-ae27-5b379cab2cae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722997039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.2722997039
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.1051430835
Short name T226
Test name
Test status
Simulation time 277648727104 ps
CPU time 267.52 seconds
Started Jul 20 04:32:46 PM PDT 24
Finished Jul 20 04:37:16 PM PDT 24
Peak memory 191584 kb
Host smart-42b3442f-7fba-4a8e-9958-d303beb8fe28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051430835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.1051430835
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.1472323865
Short name T71
Test name
Test status
Simulation time 404319665203 ps
CPU time 528.93 seconds
Started Jul 20 04:32:46 PM PDT 24
Finished Jul 20 04:41:37 PM PDT 24
Peak memory 191576 kb
Host smart-a0cb450a-75a1-4611-8f57-b31f56233938
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472323865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
1472323865
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/50.rv_timer_random.2941607098
Short name T213
Test name
Test status
Simulation time 1057197526321 ps
CPU time 1292.66 seconds
Started Jul 20 04:33:13 PM PDT 24
Finished Jul 20 04:54:47 PM PDT 24
Peak memory 191648 kb
Host smart-d178af3f-2a8d-45c2-908a-d80195952371
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941607098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.2941607098
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.1722451050
Short name T4
Test name
Test status
Simulation time 118107204697 ps
CPU time 115.01 seconds
Started Jul 20 04:33:20 PM PDT 24
Finished Jul 20 04:35:22 PM PDT 24
Peak memory 191584 kb
Host smart-c94bf5ff-8798-4510-accd-d787cae617da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722451050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.1722451050
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.2471001610
Short name T232
Test name
Test status
Simulation time 672765026518 ps
CPU time 287.11 seconds
Started Jul 20 04:33:26 PM PDT 24
Finished Jul 20 04:38:21 PM PDT 24
Peak memory 191588 kb
Host smart-f714316a-ff87-4b7c-857a-dde84bb0c3db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471001610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.2471001610
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.1784510206
Short name T439
Test name
Test status
Simulation time 39762682907 ps
CPU time 64.28 seconds
Started Jul 20 04:33:21 PM PDT 24
Finished Jul 20 04:34:32 PM PDT 24
Peak memory 183436 kb
Host smart-70cf0400-678d-4b99-b4d5-da60393c7210
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784510206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.1784510206
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.2516290060
Short name T124
Test name
Test status
Simulation time 54132325135 ps
CPU time 299.53 seconds
Started Jul 20 04:33:24 PM PDT 24
Finished Jul 20 04:38:30 PM PDT 24
Peak memory 183440 kb
Host smart-1635cf4a-6157-4c07-bedc-9d0a75f81d41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516290060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.2516290060
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.396452484
Short name T401
Test name
Test status
Simulation time 199600058515 ps
CPU time 148.23 seconds
Started Jul 20 04:33:06 PM PDT 24
Finished Jul 20 04:35:35 PM PDT 24
Peak memory 191580 kb
Host smart-c148dea3-a010-494e-b3d6-4cff53e85114
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396452484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.396452484
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.4279923494
Short name T358
Test name
Test status
Simulation time 77724648387 ps
CPU time 204.96 seconds
Started Jul 20 04:33:22 PM PDT 24
Finished Jul 20 04:36:54 PM PDT 24
Peak memory 191620 kb
Host smart-1e210e46-0e20-40ad-9c8d-57bd42d172b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279923494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.4279923494
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.3701246094
Short name T249
Test name
Test status
Simulation time 51920349767 ps
CPU time 164.36 seconds
Started Jul 20 04:33:32 PM PDT 24
Finished Jul 20 04:36:25 PM PDT 24
Peak memory 191640 kb
Host smart-5874b415-2ddf-4879-85a2-fde14ace6aef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701246094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.3701246094
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.3537365925
Short name T274
Test name
Test status
Simulation time 523870884908 ps
CPU time 236.85 seconds
Started Jul 20 04:33:18 PM PDT 24
Finished Jul 20 04:37:20 PM PDT 24
Peak memory 191628 kb
Host smart-72c3dd03-c1bb-4243-a712-03c824aa8220
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537365925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.3537365925
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.2209996843
Short name T229
Test name
Test status
Simulation time 110515186965 ps
CPU time 100.44 seconds
Started Jul 20 04:33:01 PM PDT 24
Finished Jul 20 04:34:42 PM PDT 24
Peak memory 183424 kb
Host smart-8bb35329-5be3-48bc-9240-109b060ceb6b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209996843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.2209996843
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.4087921414
Short name T380
Test name
Test status
Simulation time 56297134442 ps
CPU time 76.21 seconds
Started Jul 20 04:32:44 PM PDT 24
Finished Jul 20 04:34:01 PM PDT 24
Peak memory 183332 kb
Host smart-915244a3-436f-453a-b7ca-710fc750b224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087921414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.4087921414
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.2699995278
Short name T294
Test name
Test status
Simulation time 198412940374 ps
CPU time 725.38 seconds
Started Jul 20 04:32:50 PM PDT 24
Finished Jul 20 04:44:56 PM PDT 24
Peak memory 191548 kb
Host smart-92087b97-3703-4f5d-9957-79701b41e684
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699995278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.2699995278
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.4212022185
Short name T147
Test name
Test status
Simulation time 7895510982 ps
CPU time 10.29 seconds
Started Jul 20 04:32:53 PM PDT 24
Finished Jul 20 04:33:03 PM PDT 24
Peak memory 191612 kb
Host smart-4ae2c336-d0c7-4a35-b270-040990c70171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212022185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.4212022185
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.461115588
Short name T142
Test name
Test status
Simulation time 530094945729 ps
CPU time 1897.29 seconds
Started Jul 20 04:32:36 PM PDT 24
Finished Jul 20 05:04:16 PM PDT 24
Peak memory 191712 kb
Host smart-f32d8718-c232-4a59-8d9f-d1b344d378fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461115588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.461115588
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/60.rv_timer_random.3582258298
Short name T24
Test name
Test status
Simulation time 75956236801 ps
CPU time 35.88 seconds
Started Jul 20 04:33:14 PM PDT 24
Finished Jul 20 04:33:52 PM PDT 24
Peak memory 193744 kb
Host smart-aedd4540-119e-4ec6-95f5-4b278f2b245c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582258298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.3582258298
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.3170132007
Short name T303
Test name
Test status
Simulation time 126366689032 ps
CPU time 106.38 seconds
Started Jul 20 04:33:19 PM PDT 24
Finished Jul 20 04:35:12 PM PDT 24
Peak memory 190776 kb
Host smart-638de9be-3993-4160-be1c-42ee515254ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170132007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.3170132007
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.2019482081
Short name T74
Test name
Test status
Simulation time 30850713031 ps
CPU time 47.98 seconds
Started Jul 20 04:33:18 PM PDT 24
Finished Jul 20 04:34:11 PM PDT 24
Peak memory 183296 kb
Host smart-f48ec95a-2f45-49f6-8865-d3eb0d273c87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019482081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.2019482081
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.1145311576
Short name T296
Test name
Test status
Simulation time 1003826564408 ps
CPU time 235.16 seconds
Started Jul 20 04:33:27 PM PDT 24
Finished Jul 20 04:37:30 PM PDT 24
Peak memory 191632 kb
Host smart-284100f2-ebd3-42fc-9cc1-83d23f5cddcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145311576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.1145311576
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.3765548480
Short name T176
Test name
Test status
Simulation time 350765846972 ps
CPU time 288.45 seconds
Started Jul 20 04:33:17 PM PDT 24
Finished Jul 20 04:38:09 PM PDT 24
Peak memory 191576 kb
Host smart-fcfc6d4a-abeb-4059-9041-60d3898ffee3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765548480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.3765548480
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.1384151338
Short name T310
Test name
Test status
Simulation time 68777256700 ps
CPU time 479.1 seconds
Started Jul 20 04:33:18 PM PDT 24
Finished Jul 20 04:41:23 PM PDT 24
Peak memory 191628 kb
Host smart-428f5af0-a4bf-4319-8185-67df5d4ff9db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384151338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.1384151338
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.2578713650
Short name T207
Test name
Test status
Simulation time 48518214795 ps
CPU time 153.37 seconds
Started Jul 20 04:33:24 PM PDT 24
Finished Jul 20 04:36:05 PM PDT 24
Peak memory 183384 kb
Host smart-8baa5db7-50f4-4c48-8bbc-3dd3f12c8dfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578713650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.2578713650
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.1062968836
Short name T63
Test name
Test status
Simulation time 191231720383 ps
CPU time 106.06 seconds
Started Jul 20 04:33:16 PM PDT 24
Finished Jul 20 04:35:07 PM PDT 24
Peak memory 183436 kb
Host smart-2948acd4-b832-4c62-810f-3a44096d61fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062968836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.1062968836
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.3033490590
Short name T183
Test name
Test status
Simulation time 45302869575 ps
CPU time 67.71 seconds
Started Jul 20 04:33:18 PM PDT 24
Finished Jul 20 04:34:31 PM PDT 24
Peak memory 191680 kb
Host smart-887cf13b-9975-4b65-9461-bae08886479c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033490590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.3033490590
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.4073447825
Short name T41
Test name
Test status
Simulation time 125671909432 ps
CPU time 229.06 seconds
Started Jul 20 04:32:46 PM PDT 24
Finished Jul 20 04:36:37 PM PDT 24
Peak memory 183368 kb
Host smart-fe2e2d78-e702-44af-a0f8-eb0b4723c24a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073447825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.4073447825
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.1243924883
Short name T80
Test name
Test status
Simulation time 96753783079 ps
CPU time 114.11 seconds
Started Jul 20 04:32:37 PM PDT 24
Finished Jul 20 04:34:34 PM PDT 24
Peak memory 183356 kb
Host smart-112df04f-672f-40b0-b1a9-f070bdc84e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243924883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.1243924883
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.4273742184
Short name T314
Test name
Test status
Simulation time 181603104873 ps
CPU time 1975.9 seconds
Started Jul 20 04:33:09 PM PDT 24
Finished Jul 20 05:06:06 PM PDT 24
Peak memory 191592 kb
Host smart-98d19c9d-8062-4c81-be0a-fe34d6a067df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273742184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.4273742184
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.854006363
Short name T211
Test name
Test status
Simulation time 42243372241 ps
CPU time 34.44 seconds
Started Jul 20 04:32:50 PM PDT 24
Finished Jul 20 04:33:25 PM PDT 24
Peak memory 183376 kb
Host smart-cb7f3d79-a522-426e-926c-abd01809e7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854006363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.854006363
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.3913529293
Short name T180
Test name
Test status
Simulation time 76875184450 ps
CPU time 133.65 seconds
Started Jul 20 04:33:18 PM PDT 24
Finished Jul 20 04:35:38 PM PDT 24
Peak memory 191584 kb
Host smart-3838a64f-3b53-4b45-828a-b0b448bc1028
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913529293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.3913529293
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.2325873887
Short name T170
Test name
Test status
Simulation time 299368972662 ps
CPU time 606.63 seconds
Started Jul 20 04:33:15 PM PDT 24
Finished Jul 20 04:43:24 PM PDT 24
Peak memory 191632 kb
Host smart-c23fb069-e0c1-4987-8fdf-2e0b87cb2fdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325873887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.2325873887
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.2240429858
Short name T441
Test name
Test status
Simulation time 54150552662 ps
CPU time 70.36 seconds
Started Jul 20 04:33:18 PM PDT 24
Finished Jul 20 04:34:34 PM PDT 24
Peak memory 183220 kb
Host smart-a9ac13d2-12fa-4046-83e9-fc371c5babb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240429858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.2240429858
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.2812901547
Short name T173
Test name
Test status
Simulation time 92665483737 ps
CPU time 987.95 seconds
Started Jul 20 04:33:12 PM PDT 24
Finished Jul 20 04:49:42 PM PDT 24
Peak memory 191568 kb
Host smart-cd04f2d2-8f2e-446e-ac23-9047e885691e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812901547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.2812901547
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.3547164052
Short name T325
Test name
Test status
Simulation time 322362023436 ps
CPU time 1086.45 seconds
Started Jul 20 04:33:26 PM PDT 24
Finished Jul 20 04:51:40 PM PDT 24
Peak memory 191588 kb
Host smart-7bd5c18f-f193-4831-9533-ae178882898f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547164052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.3547164052
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.3663118329
Short name T26
Test name
Test status
Simulation time 854115238539 ps
CPU time 716.51 seconds
Started Jul 20 04:33:18 PM PDT 24
Finished Jul 20 04:45:20 PM PDT 24
Peak memory 191584 kb
Host smart-5643c954-ae3f-46a1-9e67-347cea4a8ba3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663118329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.3663118329
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.1887742736
Short name T250
Test name
Test status
Simulation time 1673569195081 ps
CPU time 1141.49 seconds
Started Jul 20 04:33:18 PM PDT 24
Finished Jul 20 04:52:25 PM PDT 24
Peak memory 191624 kb
Host smart-38c38d1f-c687-445e-bd90-23dc06aa5e51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887742736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.1887742736
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.1013394826
Short name T397
Test name
Test status
Simulation time 23606876186 ps
CPU time 43.8 seconds
Started Jul 20 04:33:04 PM PDT 24
Finished Jul 20 04:33:49 PM PDT 24
Peak memory 183376 kb
Host smart-27a0f125-f562-47ed-b344-46b3b80a441d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013394826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.1013394826
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.4059006631
Short name T424
Test name
Test status
Simulation time 321467969037 ps
CPU time 554.5 seconds
Started Jul 20 04:32:41 PM PDT 24
Finished Jul 20 04:41:58 PM PDT 24
Peak memory 183420 kb
Host smart-502d1cb1-67b4-4c28-b4c7-70ad29eaa9ee
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059006631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.4059006631
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.1541433933
Short name T389
Test name
Test status
Simulation time 56892537727 ps
CPU time 86.69 seconds
Started Jul 20 04:32:31 PM PDT 24
Finished Jul 20 04:34:06 PM PDT 24
Peak memory 183432 kb
Host smart-395f7ddf-b51c-4c76-ad0f-4a5f0b76d7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541433933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.1541433933
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.1590183416
Short name T218
Test name
Test status
Simulation time 28993116816 ps
CPU time 30.81 seconds
Started Jul 20 04:32:39 PM PDT 24
Finished Jul 20 04:33:13 PM PDT 24
Peak memory 183424 kb
Host smart-4bc56aa9-f202-4f3e-8dd9-5b0931564eb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590183416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.1590183416
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.2884007043
Short name T247
Test name
Test status
Simulation time 752724490778 ps
CPU time 324.16 seconds
Started Jul 20 04:32:56 PM PDT 24
Finished Jul 20 04:38:21 PM PDT 24
Peak memory 191628 kb
Host smart-7f43213b-ea72-49fd-8274-4337864dae87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884007043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.2884007043
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.913718587
Short name T217
Test name
Test status
Simulation time 56667123927 ps
CPU time 96.63 seconds
Started Jul 20 04:33:20 PM PDT 24
Finished Jul 20 04:35:02 PM PDT 24
Peak memory 191532 kb
Host smart-21c25362-9349-40e8-8469-de5881180ea9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913718587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.913718587
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.1813563256
Short name T222
Test name
Test status
Simulation time 63100934348 ps
CPU time 68.78 seconds
Started Jul 20 04:33:11 PM PDT 24
Finished Jul 20 04:34:20 PM PDT 24
Peak memory 191636 kb
Host smart-4ba3e6f4-7584-4f9f-a304-9ef21754ac77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813563256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.1813563256
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.2393809108
Short name T254
Test name
Test status
Simulation time 24679596771 ps
CPU time 40.8 seconds
Started Jul 20 04:33:28 PM PDT 24
Finished Jul 20 04:34:16 PM PDT 24
Peak memory 183388 kb
Host smart-2319656e-1c4c-44d6-950f-84a4bfcf7bb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393809108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.2393809108
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.1691915328
Short name T57
Test name
Test status
Simulation time 391169519019 ps
CPU time 594.49 seconds
Started Jul 20 04:33:18 PM PDT 24
Finished Jul 20 04:43:17 PM PDT 24
Peak memory 191584 kb
Host smart-0ed0b7d0-0013-492d-9804-002510d8342b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691915328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.1691915328
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.1468488028
Short name T446
Test name
Test status
Simulation time 351647918242 ps
CPU time 513.11 seconds
Started Jul 20 04:33:18 PM PDT 24
Finished Jul 20 04:41:56 PM PDT 24
Peak memory 191596 kb
Host smart-c14fe95b-7e7a-4296-abf5-e48537391927
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468488028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.1468488028
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.1458609554
Short name T339
Test name
Test status
Simulation time 90360584651 ps
CPU time 162.04 seconds
Started Jul 20 04:33:21 PM PDT 24
Finished Jul 20 04:36:09 PM PDT 24
Peak memory 191580 kb
Host smart-ca46f406-6bb8-4c61-9a77-0c052224e64a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458609554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.1458609554
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.3194323795
Short name T152
Test name
Test status
Simulation time 182846475359 ps
CPU time 66.52 seconds
Started Jul 20 04:33:29 PM PDT 24
Finished Jul 20 04:34:43 PM PDT 24
Peak memory 194868 kb
Host smart-bf167491-5b65-47e9-9492-5c86cb13bdd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194323795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.3194323795
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.2430083282
Short name T235
Test name
Test status
Simulation time 539788751046 ps
CPU time 387.97 seconds
Started Jul 20 04:33:22 PM PDT 24
Finished Jul 20 04:39:57 PM PDT 24
Peak memory 191580 kb
Host smart-b679bb4d-bcef-4d4d-98fa-c266a4bbf22e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430083282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.2430083282
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.2387189672
Short name T443
Test name
Test status
Simulation time 9222365099 ps
CPU time 180.24 seconds
Started Jul 20 04:33:20 PM PDT 24
Finished Jul 20 04:36:27 PM PDT 24
Peak memory 183440 kb
Host smart-6f43be1a-1f4f-45ff-9ec7-0c1b4808f7cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387189672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.2387189672
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.338504225
Short name T337
Test name
Test status
Simulation time 260879265645 ps
CPU time 138.86 seconds
Started Jul 20 04:33:19 PM PDT 24
Finished Jul 20 04:35:44 PM PDT 24
Peak memory 191600 kb
Host smart-f573b5d8-7f30-419c-8ebc-387bd48818b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338504225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.338504225
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.4111830010
Short name T299
Test name
Test status
Simulation time 304101756380 ps
CPU time 541.24 seconds
Started Jul 20 04:32:38 PM PDT 24
Finished Jul 20 04:41:43 PM PDT 24
Peak memory 183480 kb
Host smart-560a8ec9-9b60-4a9f-a3f5-6e16dec45336
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111830010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.4111830010
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.1686403091
Short name T378
Test name
Test status
Simulation time 179358172429 ps
CPU time 66.1 seconds
Started Jul 20 04:32:46 PM PDT 24
Finished Jul 20 04:33:55 PM PDT 24
Peak memory 183392 kb
Host smart-7dba1948-1117-44a7-9d22-0e0511da9f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686403091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.1686403091
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.3710612104
Short name T233
Test name
Test status
Simulation time 46028497830 ps
CPU time 77.97 seconds
Started Jul 20 04:32:46 PM PDT 24
Finished Jul 20 04:34:06 PM PDT 24
Peak memory 183400 kb
Host smart-83f483f5-7a96-4e42-b23a-23929cc8623a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710612104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.3710612104
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.2342636158
Short name T430
Test name
Test status
Simulation time 69938345 ps
CPU time 0.54 seconds
Started Jul 20 04:32:39 PM PDT 24
Finished Jul 20 04:32:42 PM PDT 24
Peak memory 183104 kb
Host smart-5f8a7849-ce47-4269-b555-52cb32d9d55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342636158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.2342636158
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.836282044
Short name T244
Test name
Test status
Simulation time 1583418332948 ps
CPU time 415.86 seconds
Started Jul 20 04:32:35 PM PDT 24
Finished Jul 20 04:39:34 PM PDT 24
Peak memory 191580 kb
Host smart-f91f193c-a79b-4d59-a9a5-d5a6fab3aef9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836282044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.836282044
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/90.rv_timer_random.1336168530
Short name T331
Test name
Test status
Simulation time 40239747670 ps
CPU time 296 seconds
Started Jul 20 04:33:29 PM PDT 24
Finished Jul 20 04:38:33 PM PDT 24
Peak memory 191588 kb
Host smart-0320a7b0-ae93-4eeb-ac2c-d9a0f413374b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336168530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.1336168530
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.642040070
Short name T445
Test name
Test status
Simulation time 59487055540 ps
CPU time 260.08 seconds
Started Jul 20 04:33:15 PM PDT 24
Finished Jul 20 04:37:37 PM PDT 24
Peak memory 183428 kb
Host smart-00581b45-2c8b-41f9-b613-ee5fec2db9c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642040070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.642040070
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.1497313513
Short name T199
Test name
Test status
Simulation time 64294684063 ps
CPU time 40.22 seconds
Started Jul 20 04:33:17 PM PDT 24
Finished Jul 20 04:34:02 PM PDT 24
Peak memory 183376 kb
Host smart-7de09428-b630-42b6-b02a-2fea7a1e8f9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497313513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.1497313513
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.72528854
Short name T10
Test name
Test status
Simulation time 74468565418 ps
CPU time 116.65 seconds
Started Jul 20 04:33:17 PM PDT 24
Finished Jul 20 04:35:18 PM PDT 24
Peak memory 191636 kb
Host smart-356e56b3-91fc-43fa-9b72-bc7c09a2b684
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72528854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.72528854
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.1108185990
Short name T61
Test name
Test status
Simulation time 33618503694 ps
CPU time 156.39 seconds
Started Jul 20 04:33:17 PM PDT 24
Finished Jul 20 04:35:59 PM PDT 24
Peak memory 183380 kb
Host smart-ad65e23a-4042-4127-9e28-a27a4c8bd916
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108185990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.1108185990
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.3783416541
Short name T436
Test name
Test status
Simulation time 998266759287 ps
CPU time 394.32 seconds
Started Jul 20 04:33:12 PM PDT 24
Finished Jul 20 04:39:47 PM PDT 24
Peak memory 191636 kb
Host smart-e2ae9968-5d20-48f9-8e17-fc2727445a7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783416541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.3783416541
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.2210712031
Short name T150
Test name
Test status
Simulation time 117790440150 ps
CPU time 1849.8 seconds
Started Jul 20 04:33:31 PM PDT 24
Finished Jul 20 05:04:29 PM PDT 24
Peak memory 191632 kb
Host smart-ad1772cf-a4a5-4ace-9238-fcbcd497dcd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210712031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.2210712031
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.4271676181
Short name T305
Test name
Test status
Simulation time 15844070170 ps
CPU time 16.47 seconds
Started Jul 20 04:33:19 PM PDT 24
Finished Jul 20 04:33:41 PM PDT 24
Peak memory 183344 kb
Host smart-6ab1058d-c86c-4a8c-a021-93c2641cd4e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271676181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.4271676181
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.3230526314
Short name T42
Test name
Test status
Simulation time 446016400909 ps
CPU time 776.13 seconds
Started Jul 20 04:33:24 PM PDT 24
Finished Jul 20 04:46:28 PM PDT 24
Peak memory 191636 kb
Host smart-8ab28d22-280c-468c-8a3e-1c901bcb1451
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230526314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.3230526314
Directory /workspace/98.rv_timer_random/latest
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