Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
1121 |
1 |
|
T31 |
11 |
|
T32 |
30 |
|
T33 |
10 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
625 |
1 |
|
T31 |
7 |
|
T32 |
10 |
|
T33 |
4 |
auto[1] |
496 |
1 |
|
T31 |
4 |
|
T32 |
20 |
|
T33 |
6 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
422 |
1 |
|
T31 |
1 |
|
T32 |
8 |
|
T33 |
1 |
auto[1] |
699 |
1 |
|
T31 |
10 |
|
T32 |
22 |
|
T33 |
9 |
Summary for Variable cp_intr_test
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_test
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
636 |
1 |
|
T31 |
5 |
|
T32 |
14 |
|
T33 |
1 |
auto[1] |
485 |
1 |
|
T31 |
6 |
|
T32 |
16 |
|
T33 |
9 |
Summary for Cross intr_test_cg_cc
Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for intr_test_cg_cc
Bins
cp_intr | cp_intr_test | cp_intr_en | cp_intr_state | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
auto[0] |
246 |
1 |
|
T31 |
1 |
|
T33 |
1 |
|
T11 |
3 |
all_values[0] |
auto[0] |
auto[0] |
auto[1] |
112 |
1 |
|
T31 |
2 |
|
T32 |
1 |
|
T47 |
2 |
all_values[0] |
auto[0] |
auto[1] |
auto[0] |
176 |
1 |
|
T32 |
8 |
|
T11 |
4 |
|
T109 |
4 |
all_values[0] |
auto[0] |
auto[1] |
auto[1] |
102 |
1 |
|
T31 |
2 |
|
T32 |
5 |
|
T149 |
2 |
all_values[0] |
auto[1] |
auto[0] |
auto[1] |
267 |
1 |
|
T31 |
4 |
|
T32 |
9 |
|
T33 |
3 |
all_values[0] |
auto[1] |
auto[1] |
auto[1] |
218 |
1 |
|
T31 |
2 |
|
T32 |
7 |
|
T33 |
6 |
User Defined Cross Bins for intr_test_cg_cc
Excluded/Illegal bins
NAME | COUNT | STATUS |
test_1_state_0 |
0 |
Illegal |