Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.61 99.36 98.73 100.00 100.00 100.00 99.55


Total test records in report: 578
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T506 /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.540865060 Jul 21 05:55:25 PM PDT 24 Jul 21 05:55:26 PM PDT 24 142047105 ps
T507 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.4278084996 Jul 21 05:55:26 PM PDT 24 Jul 21 05:55:27 PM PDT 24 11344008 ps
T508 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.727779145 Jul 21 05:54:58 PM PDT 24 Jul 21 05:55:01 PM PDT 24 240424965 ps
T509 /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.3711573777 Jul 21 05:55:05 PM PDT 24 Jul 21 05:55:07 PM PDT 24 41409184 ps
T510 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.190143656 Jul 21 05:55:38 PM PDT 24 Jul 21 05:55:39 PM PDT 24 25117489 ps
T511 /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.269527338 Jul 21 05:54:51 PM PDT 24 Jul 21 05:54:52 PM PDT 24 12550481 ps
T512 /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.3693541811 Jul 21 05:55:04 PM PDT 24 Jul 21 05:55:06 PM PDT 24 794721893 ps
T513 /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.3115318953 Jul 21 05:55:08 PM PDT 24 Jul 21 05:55:09 PM PDT 24 12852552 ps
T514 /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.2450503809 Jul 21 05:55:02 PM PDT 24 Jul 21 05:55:03 PM PDT 24 37940941 ps
T515 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.3572172024 Jul 21 05:55:28 PM PDT 24 Jul 21 05:55:29 PM PDT 24 24195403 ps
T90 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.4290059030 Jul 21 05:54:58 PM PDT 24 Jul 21 05:55:00 PM PDT 24 15580612 ps
T516 /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.1618952311 Jul 21 05:55:16 PM PDT 24 Jul 21 05:55:18 PM PDT 24 62885878 ps
T517 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.1119099184 Jul 21 05:55:03 PM PDT 24 Jul 21 05:55:04 PM PDT 24 14803181 ps
T518 /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3514671151 Jul 21 05:54:56 PM PDT 24 Jul 21 05:54:59 PM PDT 24 42197165 ps
T519 /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.2330656942 Jul 21 05:55:03 PM PDT 24 Jul 21 05:55:04 PM PDT 24 31553675 ps
T520 /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.1467832492 Jul 21 05:55:18 PM PDT 24 Jul 21 05:55:19 PM PDT 24 118453305 ps
T521 /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.1963926355 Jul 21 05:54:57 PM PDT 24 Jul 21 05:55:00 PM PDT 24 274444490 ps
T522 /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.3782069947 Jul 21 05:55:01 PM PDT 24 Jul 21 05:55:03 PM PDT 24 150347377 ps
T523 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.1504443255 Jul 21 05:55:31 PM PDT 24 Jul 21 05:55:32 PM PDT 24 18866893 ps
T524 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.3156066105 Jul 21 05:55:15 PM PDT 24 Jul 21 05:55:17 PM PDT 24 193772081 ps
T525 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.750656844 Jul 21 05:55:10 PM PDT 24 Jul 21 05:55:13 PM PDT 24 142771774 ps
T91 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.1342578819 Jul 21 05:55:16 PM PDT 24 Jul 21 05:55:18 PM PDT 24 40388329 ps
T526 /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.1060605380 Jul 21 05:55:23 PM PDT 24 Jul 21 05:55:24 PM PDT 24 65525825 ps
T527 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.3512689907 Jul 21 05:55:22 PM PDT 24 Jul 21 05:55:23 PM PDT 24 178225804 ps
T528 /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.4049467254 Jul 21 05:55:03 PM PDT 24 Jul 21 05:55:05 PM PDT 24 39531702 ps
T529 /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.1921747020 Jul 21 05:55:25 PM PDT 24 Jul 21 05:55:26 PM PDT 24 211255989 ps
T530 /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.513254774 Jul 21 05:55:26 PM PDT 24 Jul 21 05:55:27 PM PDT 24 79277497 ps
T92 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.3528214147 Jul 21 05:55:10 PM PDT 24 Jul 21 05:55:11 PM PDT 24 46753708 ps
T531 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.2833675666 Jul 21 05:55:34 PM PDT 24 Jul 21 05:55:35 PM PDT 24 11599755 ps
T532 /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.2622282344 Jul 21 05:55:31 PM PDT 24 Jul 21 05:55:32 PM PDT 24 13782528 ps
T533 /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.3725613158 Jul 21 05:55:14 PM PDT 24 Jul 21 05:55:15 PM PDT 24 36931742 ps
T534 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.3753702978 Jul 21 05:55:29 PM PDT 24 Jul 21 05:55:30 PM PDT 24 48731808 ps
T535 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3397606229 Jul 21 05:55:35 PM PDT 24 Jul 21 05:55:36 PM PDT 24 12369055 ps
T536 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3649556123 Jul 21 05:55:21 PM PDT 24 Jul 21 05:55:22 PM PDT 24 38848500 ps
T537 /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.977969254 Jul 21 05:55:17 PM PDT 24 Jul 21 05:55:18 PM PDT 24 37130391 ps
T538 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.977176682 Jul 21 05:55:17 PM PDT 24 Jul 21 05:55:20 PM PDT 24 382650833 ps
T539 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.914645324 Jul 21 05:55:23 PM PDT 24 Jul 21 05:55:24 PM PDT 24 13364672 ps
T540 /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.924445997 Jul 21 05:54:50 PM PDT 24 Jul 21 05:54:53 PM PDT 24 2054392062 ps
T541 /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.2440353379 Jul 21 05:54:58 PM PDT 24 Jul 21 05:55:00 PM PDT 24 40599656 ps
T542 /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.142882392 Jul 21 05:54:55 PM PDT 24 Jul 21 05:54:57 PM PDT 24 842955476 ps
T543 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.1879284848 Jul 21 05:55:30 PM PDT 24 Jul 21 05:55:31 PM PDT 24 32675192 ps
T544 /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.3469867043 Jul 21 05:55:14 PM PDT 24 Jul 21 05:55:15 PM PDT 24 11799725 ps
T545 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.1199465797 Jul 21 05:55:10 PM PDT 24 Jul 21 05:55:12 PM PDT 24 34926728 ps
T93 /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.3317654979 Jul 21 05:54:56 PM PDT 24 Jul 21 05:55:00 PM PDT 24 431785400 ps
T546 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.695468652 Jul 21 05:55:35 PM PDT 24 Jul 21 05:55:36 PM PDT 24 46080119 ps
T547 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.1207718426 Jul 21 05:55:02 PM PDT 24 Jul 21 05:55:03 PM PDT 24 16930837 ps
T548 /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.3717792621 Jul 21 05:55:04 PM PDT 24 Jul 21 05:55:06 PM PDT 24 310774869 ps
T549 /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.562760444 Jul 21 05:55:18 PM PDT 24 Jul 21 05:55:20 PM PDT 24 72758750 ps
T550 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.1535106520 Jul 21 05:55:26 PM PDT 24 Jul 21 05:55:27 PM PDT 24 62099629 ps
T551 /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.3318281001 Jul 21 05:54:56 PM PDT 24 Jul 21 05:54:58 PM PDT 24 18657414 ps
T552 /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.3221090163 Jul 21 05:55:08 PM PDT 24 Jul 21 05:55:09 PM PDT 24 39766810 ps
T553 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.2674121288 Jul 21 05:55:20 PM PDT 24 Jul 21 05:55:22 PM PDT 24 62670168 ps
T554 /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.1143183299 Jul 21 05:55:04 PM PDT 24 Jul 21 05:55:05 PM PDT 24 84639599 ps
T555 /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.3579085869 Jul 21 05:55:23 PM PDT 24 Jul 21 05:55:24 PM PDT 24 23917355 ps
T556 /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2133209812 Jul 21 05:55:27 PM PDT 24 Jul 21 05:55:28 PM PDT 24 15604095 ps
T557 /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.1036995604 Jul 21 05:54:57 PM PDT 24 Jul 21 05:55:00 PM PDT 24 446998694 ps
T558 /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.2040050888 Jul 21 05:55:09 PM PDT 24 Jul 21 05:55:11 PM PDT 24 26384217 ps
T559 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.70766169 Jul 21 05:55:21 PM PDT 24 Jul 21 05:55:23 PM PDT 24 21330905 ps
T560 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.4251134278 Jul 21 05:55:02 PM PDT 24 Jul 21 05:55:04 PM PDT 24 83683284 ps
T561 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3549531811 Jul 21 05:55:05 PM PDT 24 Jul 21 05:55:08 PM PDT 24 96243478 ps
T562 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.891081210 Jul 21 05:55:20 PM PDT 24 Jul 21 05:55:22 PM PDT 24 49446150 ps
T563 /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.3872346935 Jul 21 05:55:16 PM PDT 24 Jul 21 05:55:18 PM PDT 24 359807561 ps
T564 /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.3501508216 Jul 21 05:55:19 PM PDT 24 Jul 21 05:55:20 PM PDT 24 26069758 ps
T565 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1336730051 Jul 21 05:55:18 PM PDT 24 Jul 21 05:55:19 PM PDT 24 613875776 ps
T566 /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.4168105053 Jul 21 05:55:10 PM PDT 24 Jul 21 05:55:11 PM PDT 24 14931450 ps
T94 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1409825199 Jul 21 05:54:51 PM PDT 24 Jul 21 05:54:52 PM PDT 24 16644107 ps
T567 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.4020290569 Jul 21 05:55:09 PM PDT 24 Jul 21 05:55:10 PM PDT 24 11337681 ps
T568 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.443951500 Jul 21 05:55:02 PM PDT 24 Jul 21 05:55:03 PM PDT 24 75064619 ps
T569 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.2723895146 Jul 21 05:54:58 PM PDT 24 Jul 21 05:55:00 PM PDT 24 54069314 ps
T570 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.322726885 Jul 21 05:55:16 PM PDT 24 Jul 21 05:55:18 PM PDT 24 97167836 ps
T571 /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.4216491770 Jul 21 05:55:28 PM PDT 24 Jul 21 05:55:29 PM PDT 24 42287252 ps
T572 /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1179062026 Jul 21 05:55:16 PM PDT 24 Jul 21 05:55:17 PM PDT 24 24659939 ps
T573 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.908179402 Jul 21 05:54:56 PM PDT 24 Jul 21 05:54:57 PM PDT 24 117597589 ps
T574 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.368440216 Jul 21 05:55:10 PM PDT 24 Jul 21 05:55:11 PM PDT 24 34609895 ps
T575 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3138584927 Jul 21 05:55:15 PM PDT 24 Jul 21 05:55:16 PM PDT 24 81755311 ps
T576 /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.4045350169 Jul 21 05:54:50 PM PDT 24 Jul 21 05:54:51 PM PDT 24 33330111 ps
T577 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.884135800 Jul 21 05:54:43 PM PDT 24 Jul 21 05:54:45 PM PDT 24 78876105 ps
T578 /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.2977044918 Jul 21 05:55:20 PM PDT 24 Jul 21 05:55:21 PM PDT 24 279958189 ps

Test location /workspace/coverage/default/9.rv_timer_random.2617778952
Short name T2
Test name
Test status
Simulation time 745867752709 ps
CPU time 591.49 seconds
Started Jul 21 04:24:00 PM PDT 24
Finished Jul 21 04:33:52 PM PDT 24
Peak memory 191508 kb
Host smart-1ad08f4a-9d3a-43ab-ac90-f86ebb384e59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617778952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.2617778952
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all_with_rand_reset.719976651
Short name T12
Test name
Test status
Simulation time 41354818764 ps
CPU time 73.22 seconds
Started Jul 21 04:20:57 PM PDT 24
Finished Jul 21 04:22:11 PM PDT 24
Peak memory 198052 kb
Host smart-3dd82620-3127-401f-9d83-6dfef6bcdd7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719976651 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all_with_rand_reset.719976651
Directory /workspace/8.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.4126860276
Short name T23
Test name
Test status
Simulation time 1419096319033 ps
CPU time 609.37 seconds
Started Jul 21 04:19:54 PM PDT 24
Finished Jul 21 04:30:03 PM PDT 24
Peak memory 191512 kb
Host smart-f6e4230f-4fc9-4550-836f-f54b6f5c3e25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126860276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
4126860276
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.3224326244
Short name T14
Test name
Test status
Simulation time 460016643 ps
CPU time 0.92 seconds
Started Jul 21 04:22:45 PM PDT 24
Finished Jul 21 04:22:48 PM PDT 24
Peak memory 212104 kb
Host smart-c697dc6f-1d43-41c4-80f4-be0db7d32f99
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224326244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.3224326244
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.4109065679
Short name T130
Test name
Test status
Simulation time 1179629647100 ps
CPU time 2274.49 seconds
Started Jul 21 04:23:26 PM PDT 24
Finished Jul 21 05:01:21 PM PDT 24
Peak memory 191224 kb
Host smart-6e821fc9-8a4d-4baa-881a-222c96b2a907
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109065679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
4109065679
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.2142262894
Short name T168
Test name
Test status
Simulation time 1266015561357 ps
CPU time 2687.52 seconds
Started Jul 21 04:23:50 PM PDT 24
Finished Jul 21 05:08:38 PM PDT 24
Peak memory 190208 kb
Host smart-2063b0a2-6103-4ef0-90d8-6cd15b3d1de0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142262894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
2142262894
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.130945742
Short name T258
Test name
Test status
Simulation time 9529429597122 ps
CPU time 5309.55 seconds
Started Jul 21 04:22:57 PM PDT 24
Finished Jul 21 05:51:28 PM PDT 24
Peak memory 191544 kb
Host smart-f12c98e9-d47a-4c35-8eb9-b531de20cd61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130945742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all.
130945742
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.1192616274
Short name T73
Test name
Test status
Simulation time 665449113319 ps
CPU time 2019.46 seconds
Started Jul 21 04:23:05 PM PDT 24
Finished Jul 21 04:56:46 PM PDT 24
Peak memory 191516 kb
Host smart-802c20d0-df39-4747-92f4-1ae77744f866
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192616274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.1192616274
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.1571589742
Short name T116
Test name
Test status
Simulation time 499125975424 ps
CPU time 1326.58 seconds
Started Jul 21 04:23:17 PM PDT 24
Finished Jul 21 04:45:24 PM PDT 24
Peak memory 190572 kb
Host smart-dd6ed258-cfb0-4711-b8a2-fad2d14aa558
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571589742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.1571589742
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1598382329
Short name T29
Test name
Test status
Simulation time 61344355 ps
CPU time 0.59 seconds
Started Jul 21 05:55:18 PM PDT 24
Finished Jul 21 05:55:20 PM PDT 24
Peak memory 182608 kb
Host smart-f8d3050b-b72f-4d2c-8ea2-714149d57337
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598382329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.1598382329
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.3844859447
Short name T190
Test name
Test status
Simulation time 3057280210088 ps
CPU time 9590.14 seconds
Started Jul 21 04:21:13 PM PDT 24
Finished Jul 21 07:01:04 PM PDT 24
Peak memory 191632 kb
Host smart-50ec10a8-4cfa-461b-8af0-d52cef53e055
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844859447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.3844859447
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.3099603674
Short name T109
Test name
Test status
Simulation time 2709072759066 ps
CPU time 1339.51 seconds
Started Jul 21 04:19:20 PM PDT 24
Finished Jul 21 04:41:40 PM PDT 24
Peak memory 191700 kb
Host smart-10181bb3-be04-487a-b1de-15b7bbb56ca4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099603674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
3099603674
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.3015289041
Short name T152
Test name
Test status
Simulation time 3061455609054 ps
CPU time 3552.33 seconds
Started Jul 21 04:22:48 PM PDT 24
Finished Jul 21 05:22:02 PM PDT 24
Peak memory 188728 kb
Host smart-01a39614-352b-425f-ab66-63012ca3d7f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015289041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.3015289041
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.2429805511
Short name T69
Test name
Test status
Simulation time 549141118469 ps
CPU time 1164.07 seconds
Started Jul 21 04:21:46 PM PDT 24
Finished Jul 21 04:41:11 PM PDT 24
Peak memory 191592 kb
Host smart-ef1598e0-8913-498c-8640-28fad6a2555c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429805511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.2429805511
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.14712162
Short name T476
Test name
Test status
Simulation time 99046250 ps
CPU time 1.34 seconds
Started Jul 21 05:55:16 PM PDT 24
Finished Jul 21 05:55:18 PM PDT 24
Peak memory 195152 kb
Host smart-991dee2e-cc30-4bf0-945a-e0ea4ae42ca8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14712162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_int
g_err.14712162
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.3216988012
Short name T185
Test name
Test status
Simulation time 1887562993377 ps
CPU time 921.48 seconds
Started Jul 21 04:22:38 PM PDT 24
Finished Jul 21 04:38:00 PM PDT 24
Peak memory 190564 kb
Host smart-01ec8cf3-b6e0-4c17-88db-17e59ac07dc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216988012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
3216988012
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.1484059666
Short name T66
Test name
Test status
Simulation time 1839349437996 ps
CPU time 1164.14 seconds
Started Jul 21 04:22:58 PM PDT 24
Finished Jul 21 04:42:23 PM PDT 24
Peak memory 194396 kb
Host smart-61b4b78d-f84b-4286-bc23-9ffc9a99d05a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484059666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
1484059666
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/50.rv_timer_random.322380720
Short name T229
Test name
Test status
Simulation time 127571191297 ps
CPU time 577.68 seconds
Started Jul 21 04:21:14 PM PDT 24
Finished Jul 21 04:30:52 PM PDT 24
Peak memory 183348 kb
Host smart-b6f0b9ea-fa85-43b8-97d0-f8f058f7ec8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322380720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.322380720
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.1883541520
Short name T65
Test name
Test status
Simulation time 1782426876271 ps
CPU time 1355.2 seconds
Started Jul 21 04:19:38 PM PDT 24
Finished Jul 21 04:42:14 PM PDT 24
Peak memory 191568 kb
Host smart-a8a31a00-5dfc-451d-bfdf-05f3516546f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883541520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.1883541520
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/183.rv_timer_random.4013950547
Short name T58
Test name
Test status
Simulation time 167762155775 ps
CPU time 365.72 seconds
Started Jul 21 04:23:40 PM PDT 24
Finished Jul 21 04:29:46 PM PDT 24
Peak memory 191512 kb
Host smart-d477eb7f-fd93-43e2-b6d0-6bd1c62ed348
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013950547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.4013950547
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.4250769124
Short name T199
Test name
Test status
Simulation time 235804845623 ps
CPU time 3406.04 seconds
Started Jul 21 04:23:26 PM PDT 24
Finished Jul 21 05:20:13 PM PDT 24
Peak memory 191284 kb
Host smart-15c14add-d30b-4197-a960-f43add23bc50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250769124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.4250769124
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/147.rv_timer_random.544960876
Short name T137
Test name
Test status
Simulation time 164012811907 ps
CPU time 598.77 seconds
Started Jul 21 04:23:28 PM PDT 24
Finished Jul 21 04:33:27 PM PDT 24
Peak memory 191540 kb
Host smart-262a0159-a9cb-4e5b-9203-b50fd04f5305
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544960876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.544960876
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.2991980166
Short name T191
Test name
Test status
Simulation time 779670078934 ps
CPU time 332.72 seconds
Started Jul 21 04:20:38 PM PDT 24
Finished Jul 21 04:26:11 PM PDT 24
Peak memory 194416 kb
Host smart-1270ac96-91b7-4f39-9c94-f907c701fdbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991980166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.2991980166
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.1525916385
Short name T47
Test name
Test status
Simulation time 804239410894 ps
CPU time 441.09 seconds
Started Jul 21 04:23:20 PM PDT 24
Finished Jul 21 04:30:42 PM PDT 24
Peak memory 191300 kb
Host smart-892ee602-ec6c-4a76-8236-8dd83cc6e63c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525916385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.1525916385
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.2428985231
Short name T206
Test name
Test status
Simulation time 1110904722522 ps
CPU time 2772.22 seconds
Started Jul 21 04:21:26 PM PDT 24
Finished Jul 21 05:07:39 PM PDT 24
Peak memory 191560 kb
Host smart-7bdd15a8-e47a-4bc0-bdcd-96e4964777a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428985231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.2428985231
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.3967418042
Short name T180
Test name
Test status
Simulation time 448666186204 ps
CPU time 811.59 seconds
Started Jul 21 04:20:50 PM PDT 24
Finished Jul 21 04:34:22 PM PDT 24
Peak memory 197452 kb
Host smart-766b0a3a-b8e1-4834-8396-0eff901eb0e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967418042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.3967418042
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/180.rv_timer_random.3655380247
Short name T195
Test name
Test status
Simulation time 742298546864 ps
CPU time 368.31 seconds
Started Jul 21 04:24:47 PM PDT 24
Finished Jul 21 04:30:55 PM PDT 24
Peak memory 191268 kb
Host smart-bdfb705f-f4ca-4f57-b710-d300305d5ae2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655380247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.3655380247
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random.107562030
Short name T200
Test name
Test status
Simulation time 126160704354 ps
CPU time 262.79 seconds
Started Jul 21 04:19:39 PM PDT 24
Finished Jul 21 04:24:02 PM PDT 24
Peak memory 191612 kb
Host smart-0063e0ac-2a4b-497b-a7aa-cb620e37d99d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107562030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.107562030
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.687517757
Short name T127
Test name
Test status
Simulation time 877530652773 ps
CPU time 417.66 seconds
Started Jul 21 04:23:03 PM PDT 24
Finished Jul 21 04:30:01 PM PDT 24
Peak memory 191328 kb
Host smart-e58d249c-b10b-4bf2-bbd5-279770a6801a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687517757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all.
687517757
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.1412702559
Short name T68
Test name
Test status
Simulation time 2741813962722 ps
CPU time 1300.39 seconds
Started Jul 21 04:21:28 PM PDT 24
Finished Jul 21 04:43:09 PM PDT 24
Peak memory 191952 kb
Host smart-de106d9f-97ad-43ee-b038-008368d88bbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412702559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.1412702559
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/198.rv_timer_random.3179584102
Short name T222
Test name
Test status
Simulation time 819215378395 ps
CPU time 1161.97 seconds
Started Jul 21 04:23:41 PM PDT 24
Finished Jul 21 04:43:04 PM PDT 24
Peak memory 191512 kb
Host smart-96e3cf28-c699-4980-bd76-25082ce9b663
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179584102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.3179584102
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random.3880747943
Short name T184
Test name
Test status
Simulation time 619169940205 ps
CPU time 555.83 seconds
Started Jul 21 04:19:12 PM PDT 24
Finished Jul 21 04:28:29 PM PDT 24
Peak memory 191580 kb
Host smart-82263eec-5189-4ae1-9bab-54afeab94675
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880747943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.3880747943
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.335951388
Short name T277
Test name
Test status
Simulation time 216427155702 ps
CPU time 343.36 seconds
Started Jul 21 04:24:46 PM PDT 24
Finished Jul 21 04:30:30 PM PDT 24
Peak memory 191256 kb
Host smart-a731dec9-cf25-4c0c-a74d-7d336e6633c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335951388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.335951388
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random.490130873
Short name T294
Test name
Test status
Simulation time 174985534075 ps
CPU time 1018.39 seconds
Started Jul 21 04:20:31 PM PDT 24
Finished Jul 21 04:37:30 PM PDT 24
Peak memory 191940 kb
Host smart-832a3db1-c41c-4798-9eb5-c74edcb583eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490130873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.490130873
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random.401107419
Short name T215
Test name
Test status
Simulation time 352543351042 ps
CPU time 1400.23 seconds
Started Jul 21 04:23:40 PM PDT 24
Finished Jul 21 04:47:00 PM PDT 24
Peak memory 191256 kb
Host smart-0957cfab-a5f6-4f24-8bbd-44be98523b6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401107419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.401107419
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.1306287868
Short name T203
Test name
Test status
Simulation time 251359926993 ps
CPU time 490.51 seconds
Started Jul 21 04:22:00 PM PDT 24
Finished Jul 21 04:30:10 PM PDT 24
Peak memory 191736 kb
Host smart-3b73ed71-d486-4f77-869e-8e584b22d55f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306287868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.1306287868
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.2763104075
Short name T113
Test name
Test status
Simulation time 783723019682 ps
CPU time 393.17 seconds
Started Jul 21 04:19:20 PM PDT 24
Finished Jul 21 04:25:54 PM PDT 24
Peak memory 183488 kb
Host smart-eccf8dd2-72f7-4c46-9a82-df612eb61d9c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763104075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.2763104075
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.4160155578
Short name T183
Test name
Test status
Simulation time 313651072308 ps
CPU time 857.86 seconds
Started Jul 21 04:20:26 PM PDT 24
Finished Jul 21 04:34:45 PM PDT 24
Peak memory 196104 kb
Host smart-7a50b05b-60bd-458c-a468-2a058faabe8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160155578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.4160155578
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_random.379756996
Short name T167
Test name
Test status
Simulation time 1801689431920 ps
CPU time 945.26 seconds
Started Jul 21 04:22:52 PM PDT 24
Finished Jul 21 04:38:38 PM PDT 24
Peak memory 190492 kb
Host smart-b05124b0-48ae-4162-acf5-ed073350475f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379756996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.379756996
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.1620705344
Short name T337
Test name
Test status
Simulation time 281390806115 ps
CPU time 476.08 seconds
Started Jul 21 04:22:50 PM PDT 24
Finished Jul 21 04:30:47 PM PDT 24
Peak memory 183284 kb
Host smart-13438156-fefa-4010-a452-316f9ad9c070
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620705344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.1620705344
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_random.423807266
Short name T262
Test name
Test status
Simulation time 89708511509 ps
CPU time 269.04 seconds
Started Jul 21 04:23:21 PM PDT 24
Finished Jul 21 04:27:51 PM PDT 24
Peak memory 191292 kb
Host smart-aba2f3e3-a011-4fe4-be4d-5169e2fbec9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423807266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.423807266
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.2981635228
Short name T71
Test name
Test status
Simulation time 545537995485 ps
CPU time 464.23 seconds
Started Jul 21 04:22:52 PM PDT 24
Finished Jul 21 04:30:37 PM PDT 24
Peak memory 195448 kb
Host smart-d0ec8938-905b-42b0-9d7d-b78a8c8832f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981635228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.2981635228
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.2504897647
Short name T316
Test name
Test status
Simulation time 1493797443176 ps
CPU time 816.82 seconds
Started Jul 21 04:23:16 PM PDT 24
Finished Jul 21 04:36:53 PM PDT 24
Peak memory 183088 kb
Host smart-61196465-f4a0-4784-8713-2f8d038f1575
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504897647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.2504897647
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/109.rv_timer_random.1930654593
Short name T230
Test name
Test status
Simulation time 359819649542 ps
CPU time 641.27 seconds
Started Jul 21 04:22:42 PM PDT 24
Finished Jul 21 04:33:24 PM PDT 24
Peak memory 191588 kb
Host smart-5d790730-d6ab-4b40-871d-1d65899f7716
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930654593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.1930654593
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/170.rv_timer_random.1618560643
Short name T252
Test name
Test status
Simulation time 96660136492 ps
CPU time 159.9 seconds
Started Jul 21 04:23:25 PM PDT 24
Finished Jul 21 04:26:06 PM PDT 24
Peak memory 191544 kb
Host smart-94320b48-9690-4ae6-bd75-cc7a597c43b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618560643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.1618560643
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.3579368795
Short name T295
Test name
Test status
Simulation time 572981656226 ps
CPU time 372.04 seconds
Started Jul 21 04:23:27 PM PDT 24
Finished Jul 21 04:29:39 PM PDT 24
Peak memory 191612 kb
Host smart-357185aa-1a2f-4294-88ea-03232d24dc65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579368795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.3579368795
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.1295903124
Short name T55
Test name
Test status
Simulation time 406029621360 ps
CPU time 615.21 seconds
Started Jul 21 04:22:46 PM PDT 24
Finished Jul 21 04:33:03 PM PDT 24
Peak memory 191224 kb
Host smart-7a30f4a2-2885-4f3f-8145-cf0bac935e4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295903124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.1295903124
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.3878136010
Short name T97
Test name
Test status
Simulation time 65405881 ps
CPU time 0.69 seconds
Started Jul 21 05:54:50 PM PDT 24
Finished Jul 21 05:54:51 PM PDT 24
Peak memory 191796 kb
Host smart-0e37877d-be20-4bca-a307-9aa4c8338b88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878136010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.3878136010
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1409825199
Short name T94
Test name
Test status
Simulation time 16644107 ps
CPU time 0.56 seconds
Started Jul 21 05:54:51 PM PDT 24
Finished Jul 21 05:54:52 PM PDT 24
Peak memory 182496 kb
Host smart-d5b4caa7-9c04-4358-92ed-3ae9e8c02aa1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409825199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.1409825199
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.2368897987
Short name T166
Test name
Test status
Simulation time 88011255112 ps
CPU time 123.23 seconds
Started Jul 21 04:19:11 PM PDT 24
Finished Jul 21 04:21:14 PM PDT 24
Peak memory 191512 kb
Host smart-34017cb5-db2a-4cb6-ac1e-b541073130dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368897987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.2368897987
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_random.1646144580
Short name T267
Test name
Test status
Simulation time 1369089638419 ps
CPU time 1286.38 seconds
Started Jul 21 04:23:07 PM PDT 24
Finished Jul 21 04:44:35 PM PDT 24
Peak memory 191476 kb
Host smart-3d4ad5ac-91ae-4267-9fd9-f4ad3e18d238
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646144580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.1646144580
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.135880587
Short name T283
Test name
Test status
Simulation time 158543431813 ps
CPU time 432.35 seconds
Started Jul 21 04:22:47 PM PDT 24
Finished Jul 21 04:30:00 PM PDT 24
Peak memory 191584 kb
Host smart-8e3e11f6-a199-4fd8-8f7e-39e79534529c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135880587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.135880587
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.4216026882
Short name T237
Test name
Test status
Simulation time 158623567767 ps
CPU time 86.6 seconds
Started Jul 21 04:23:25 PM PDT 24
Finished Jul 21 04:24:52 PM PDT 24
Peak memory 191540 kb
Host smart-6ac86681-736e-416a-9c4d-df80b36eeae1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216026882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.4216026882
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.2898957588
Short name T268
Test name
Test status
Simulation time 83437062940 ps
CPU time 293 seconds
Started Jul 21 04:23:25 PM PDT 24
Finished Jul 21 04:28:19 PM PDT 24
Peak memory 195088 kb
Host smart-84ddc5ff-1877-4f91-a23d-d41922005c05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898957588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.2898957588
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.1466145947
Short name T123
Test name
Test status
Simulation time 1005911253361 ps
CPU time 510.15 seconds
Started Jul 21 04:22:39 PM PDT 24
Finished Jul 21 04:31:10 PM PDT 24
Peak memory 181480 kb
Host smart-e10b4a43-3871-4664-801d-1c9ae8e31314
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466145947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.1466145947
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/172.rv_timer_random.2322355496
Short name T160
Test name
Test status
Simulation time 70177193427 ps
CPU time 356.27 seconds
Started Jul 21 04:23:28 PM PDT 24
Finished Jul 21 04:29:24 PM PDT 24
Peak memory 191632 kb
Host smart-ec908421-fbda-47d7-a3cb-ecabf4491706
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322355496 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.2322355496
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.2041791465
Short name T101
Test name
Test status
Simulation time 960174449941 ps
CPU time 432.93 seconds
Started Jul 21 04:23:39 PM PDT 24
Finished Jul 21 04:30:52 PM PDT 24
Peak memory 191568 kb
Host smart-828358dc-12c5-49ac-8fac-10be7ad8be46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041791465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.2041791465
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random.1629933087
Short name T176
Test name
Test status
Simulation time 5042039459 ps
CPU time 26.37 seconds
Started Jul 21 04:20:15 PM PDT 24
Finished Jul 21 04:20:42 PM PDT 24
Peak memory 193828 kb
Host smart-0e11fd38-0b4a-4ea4-afe8-eddfd6ebb757
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629933087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.1629933087
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.1008966110
Short name T213
Test name
Test status
Simulation time 2599032754106 ps
CPU time 1508.68 seconds
Started Jul 21 04:19:52 PM PDT 24
Finished Jul 21 04:45:01 PM PDT 24
Peak memory 183344 kb
Host smart-bee54102-ad9f-4768-8de8-fc57ce6e0cd3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008966110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.1008966110
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.3683521176
Short name T3
Test name
Test status
Simulation time 583990233923 ps
CPU time 302.58 seconds
Started Jul 21 04:23:18 PM PDT 24
Finished Jul 21 04:28:22 PM PDT 24
Peak memory 183260 kb
Host smart-56cf30d7-7a5d-4327-8775-c6001dce660d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683521176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.3683521176
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.1862975450
Short name T155
Test name
Test status
Simulation time 149099565927 ps
CPU time 215.8 seconds
Started Jul 21 04:23:18 PM PDT 24
Finished Jul 21 04:26:55 PM PDT 24
Peak memory 183348 kb
Host smart-a64eb3c6-f423-4fa3-9b24-6ba49af4becd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862975450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.1862975450
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.3745611452
Short name T287
Test name
Test status
Simulation time 518937690415 ps
CPU time 774.46 seconds
Started Jul 21 04:23:26 PM PDT 24
Finished Jul 21 04:36:21 PM PDT 24
Peak memory 183024 kb
Host smart-1335b5e9-4c14-4eca-9c11-40e03c57402c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745611452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.3745611452
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.2712971134
Short name T340
Test name
Test status
Simulation time 45685658982 ps
CPU time 22.43 seconds
Started Jul 21 04:22:48 PM PDT 24
Finished Jul 21 04:23:12 PM PDT 24
Peak memory 180596 kb
Host smart-55d2802e-6060-4228-8275-4554a6fb4db6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712971134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.2712971134
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.3710393068
Short name T150
Test name
Test status
Simulation time 1057642389766 ps
CPU time 585.91 seconds
Started Jul 21 04:21:03 PM PDT 24
Finished Jul 21 04:30:50 PM PDT 24
Peak memory 191948 kb
Host smart-e07d5e07-110a-4a17-8a7c-1970c9b2669e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710393068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.3710393068
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.2182662353
Short name T151
Test name
Test status
Simulation time 102338570054 ps
CPU time 52.05 seconds
Started Jul 21 04:23:05 PM PDT 24
Finished Jul 21 04:23:58 PM PDT 24
Peak memory 183312 kb
Host smart-cf86cd04-ef63-45ea-ad8c-25747cb64369
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182662353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.2182662353
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.1353306362
Short name T158
Test name
Test status
Simulation time 1790041885868 ps
CPU time 1188.35 seconds
Started Jul 21 04:23:18 PM PDT 24
Finished Jul 21 04:43:07 PM PDT 24
Peak memory 189952 kb
Host smart-1e5de4e7-9ddf-4ea9-a41b-0c36201660bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353306362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.1353306362
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_random.4001035978
Short name T197
Test name
Test status
Simulation time 415320420291 ps
CPU time 597.12 seconds
Started Jul 21 04:19:03 PM PDT 24
Finished Jul 21 04:29:00 PM PDT 24
Peak memory 191568 kb
Host smart-cd4f500c-eab7-4e43-bc86-532a401540e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001035978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.4001035978
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.1852719721
Short name T187
Test name
Test status
Simulation time 100357478630 ps
CPU time 137.83 seconds
Started Jul 21 04:22:34 PM PDT 24
Finished Jul 21 04:24:53 PM PDT 24
Peak memory 190716 kb
Host smart-ef57d2ba-4c90-4176-b82c-160f1d816e56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852719721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.1852719721
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.1993762374
Short name T133
Test name
Test status
Simulation time 524063436159 ps
CPU time 1149.86 seconds
Started Jul 21 04:22:46 PM PDT 24
Finished Jul 21 04:41:57 PM PDT 24
Peak memory 191212 kb
Host smart-d6baba80-eb5a-484b-8d4e-4e97fd93e0ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993762374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.1993762374
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.1751163969
Short name T240
Test name
Test status
Simulation time 448074431526 ps
CPU time 488.02 seconds
Started Jul 21 04:23:31 PM PDT 24
Finished Jul 21 04:31:40 PM PDT 24
Peak memory 190744 kb
Host smart-0411eb37-94f4-4cfb-896e-efdb547eaf9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751163969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.1751163969
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.2057888516
Short name T504
Test name
Test status
Simulation time 257541420 ps
CPU time 1.13 seconds
Started Jul 21 05:54:50 PM PDT 24
Finished Jul 21 05:54:51 PM PDT 24
Peak memory 194824 kb
Host smart-29b4edc0-c065-4741-95b1-cb0783873d15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057888516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.2057888516
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.3982498533
Short name T271
Test name
Test status
Simulation time 180555374170 ps
CPU time 173.4 seconds
Started Jul 21 04:18:08 PM PDT 24
Finished Jul 21 04:21:02 PM PDT 24
Peak memory 191232 kb
Host smart-75faa156-6f0c-4db3-98e4-19f298768743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982498533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.3982498533
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.3159629047
Short name T354
Test name
Test status
Simulation time 373043093102 ps
CPU time 484.64 seconds
Started Jul 21 04:23:26 PM PDT 24
Finished Jul 21 04:31:31 PM PDT 24
Peak memory 191284 kb
Host smart-7767bb21-2085-424c-a5cd-ddc889c5bf01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159629047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
3159629047
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.2835333775
Short name T249
Test name
Test status
Simulation time 119929347716 ps
CPU time 285.8 seconds
Started Jul 21 04:22:53 PM PDT 24
Finished Jul 21 04:27:40 PM PDT 24
Peak memory 191272 kb
Host smart-2788541d-c638-430b-99fd-4ab8d97b7f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835333775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.2835333775
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/100.rv_timer_random.3416067259
Short name T77
Test name
Test status
Simulation time 117189789293 ps
CPU time 436.23 seconds
Started Jul 21 04:22:21 PM PDT 24
Finished Jul 21 04:29:38 PM PDT 24
Peak memory 191632 kb
Host smart-f4241ddc-950d-467c-9583-e57379ab7cc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416067259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.3416067259
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.3142857084
Short name T186
Test name
Test status
Simulation time 54593749863 ps
CPU time 94.03 seconds
Started Jul 21 04:23:45 PM PDT 24
Finished Jul 21 04:25:20 PM PDT 24
Peak memory 190424 kb
Host smart-00795ff1-217e-49be-890b-eac2ac2f384d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142857084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.3142857084
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/110.rv_timer_random.2287012177
Short name T159
Test name
Test status
Simulation time 472184010254 ps
CPU time 753.94 seconds
Started Jul 21 04:22:42 PM PDT 24
Finished Jul 21 04:35:17 PM PDT 24
Peak memory 191780 kb
Host smart-e6a7c4fc-e98f-4c96-a3d7-fce3e6c2ff81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287012177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.2287012177
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.291320775
Short name T305
Test name
Test status
Simulation time 490019899766 ps
CPU time 717.98 seconds
Started Jul 21 04:22:43 PM PDT 24
Finished Jul 21 04:34:42 PM PDT 24
Peak memory 193728 kb
Host smart-23567258-cb7c-4449-8a4f-9f062d18db46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291320775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.291320775
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.3431860514
Short name T312
Test name
Test status
Simulation time 184048456019 ps
CPU time 169.28 seconds
Started Jul 21 04:22:54 PM PDT 24
Finished Jul 21 04:25:45 PM PDT 24
Peak memory 195236 kb
Host smart-a7f7b7dc-c00b-48a9-aa83-b0f04cb7e63d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431860514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.3431860514
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.1429493642
Short name T297
Test name
Test status
Simulation time 157754194704 ps
CPU time 742.18 seconds
Started Jul 21 04:23:01 PM PDT 24
Finished Jul 21 04:35:23 PM PDT 24
Peak memory 183536 kb
Host smart-fb6696f1-1f41-4ef6-9e8d-d3498169bbc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429493642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.1429493642
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.4122483795
Short name T171
Test name
Test status
Simulation time 100458476271 ps
CPU time 149.11 seconds
Started Jul 21 04:24:31 PM PDT 24
Finished Jul 21 04:27:01 PM PDT 24
Peak memory 191572 kb
Host smart-61567bed-f4db-46f8-8e20-dc6b8e8b42f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122483795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.4122483795
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random.652157370
Short name T235
Test name
Test status
Simulation time 752288527116 ps
CPU time 1363.94 seconds
Started Jul 21 04:23:40 PM PDT 24
Finished Jul 21 04:46:24 PM PDT 24
Peak memory 191256 kb
Host smart-6e935dc6-62d4-4784-99c2-6655edd6b264
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652157370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.652157370
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random.2126589087
Short name T320
Test name
Test status
Simulation time 228854914131 ps
CPU time 204.53 seconds
Started Jul 21 04:20:11 PM PDT 24
Finished Jul 21 04:23:36 PM PDT 24
Peak memory 191540 kb
Host smart-58f4d5d1-755f-4978-ac16-af2f695ff651
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126589087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.2126589087
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.3235142815
Short name T149
Test name
Test status
Simulation time 856015627178 ps
CPU time 1378.25 seconds
Started Jul 21 04:22:39 PM PDT 24
Finished Jul 21 04:45:39 PM PDT 24
Peak memory 191220 kb
Host smart-850449a9-2829-4ed3-985f-9f6eed102047
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235142815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.3235142815
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/153.rv_timer_random.4145406683
Short name T46
Test name
Test status
Simulation time 625921964184 ps
CPU time 755.74 seconds
Started Jul 21 04:23:29 PM PDT 24
Finished Jul 21 04:36:05 PM PDT 24
Peak memory 191552 kb
Host smart-da685980-e4e2-4608-b38d-38db9ec3764b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145406683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.4145406683
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.3722979741
Short name T328
Test name
Test status
Simulation time 122749586417 ps
CPU time 1285.93 seconds
Started Jul 21 04:23:28 PM PDT 24
Finished Jul 21 04:44:54 PM PDT 24
Peak memory 191524 kb
Host smart-96878d4d-d5e0-41d7-bf84-eb1ccebc17b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722979741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.3722979741
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.1371202968
Short name T278
Test name
Test status
Simulation time 125451468665 ps
CPU time 104.17 seconds
Started Jul 21 04:23:39 PM PDT 24
Finished Jul 21 04:25:23 PM PDT 24
Peak memory 191492 kb
Host smart-e4f19012-88d6-47f3-9449-46eba54eec4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371202968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.1371202968
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.1704774858
Short name T350
Test name
Test status
Simulation time 402340804702 ps
CPU time 440.4 seconds
Started Jul 21 04:19:50 PM PDT 24
Finished Jul 21 04:27:11 PM PDT 24
Peak memory 194096 kb
Host smart-2336b029-9bb2-46ca-b8fb-35353b698809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704774858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.1704774858
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/194.rv_timer_random.1398038290
Short name T256
Test name
Test status
Simulation time 643826117155 ps
CPU time 242.11 seconds
Started Jul 21 04:23:34 PM PDT 24
Finished Jul 21 04:27:37 PM PDT 24
Peak memory 191504 kb
Host smart-bcc9dd76-6c2c-4a27-a441-2fafc3cfc40a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398038290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.1398038290
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random.3517107906
Short name T306
Test name
Test status
Simulation time 2019748763430 ps
CPU time 1310.48 seconds
Started Jul 21 04:23:07 PM PDT 24
Finished Jul 21 04:44:58 PM PDT 24
Peak memory 191400 kb
Host smart-e0cad258-2b2c-41c8-ba34-f96d8b6f4976
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517107906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.3517107906
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.3222360528
Short name T170
Test name
Test status
Simulation time 50120478012 ps
CPU time 97.91 seconds
Started Jul 21 04:23:26 PM PDT 24
Finished Jul 21 04:25:04 PM PDT 24
Peak memory 183200 kb
Host smart-93097358-b2b9-4f09-b999-9faef45c692b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222360528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.3222360528
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.3599815434
Short name T221
Test name
Test status
Simulation time 3045144405466 ps
CPU time 1113.86 seconds
Started Jul 21 04:22:58 PM PDT 24
Finished Jul 21 04:41:32 PM PDT 24
Peak memory 191260 kb
Host smart-a2d849b3-959b-47cf-a01c-9d66dbd9013e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599815434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
3599815434
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.173332172
Short name T62
Test name
Test status
Simulation time 78863329141 ps
CPU time 35.06 seconds
Started Jul 21 04:23:01 PM PDT 24
Finished Jul 21 04:23:37 PM PDT 24
Peak memory 183060 kb
Host smart-13ad196c-cec0-45a7-a47c-5b7a08aede1c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173332172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.rv_timer_cfg_update_on_fly.173332172
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3453154948
Short name T494
Test name
Test status
Simulation time 121352364 ps
CPU time 0.84 seconds
Started Jul 21 05:54:54 PM PDT 24
Finished Jul 21 05:54:56 PM PDT 24
Peak memory 192388 kb
Host smart-1241369d-2f42-4d5a-9839-5d8a31d2bddf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453154948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.3453154948
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3892609479
Short name T52
Test name
Test status
Simulation time 425095312 ps
CPU time 3.73 seconds
Started Jul 21 05:54:51 PM PDT 24
Finished Jul 21 05:54:55 PM PDT 24
Peak memory 190912 kb
Host smart-e61bb328-9968-4913-a554-c8403ef61542
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892609479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.3892609479
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.1080741780
Short name T465
Test name
Test status
Simulation time 66533369 ps
CPU time 0.59 seconds
Started Jul 21 05:54:43 PM PDT 24
Finished Jul 21 05:54:44 PM PDT 24
Peak memory 182584 kb
Host smart-92d67c41-69a6-4830-9ec2-b710dcf7c433
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080741780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.1080741780
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.1558702211
Short name T478
Test name
Test status
Simulation time 79365144 ps
CPU time 1.06 seconds
Started Jul 21 05:54:50 PM PDT 24
Finished Jul 21 05:54:51 PM PDT 24
Peak memory 197276 kb
Host smart-4da5b264-4bef-4487-abb0-f2fee1fdf538
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558702211 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.1558702211
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.269527338
Short name T511
Test name
Test status
Simulation time 12550481 ps
CPU time 0.54 seconds
Started Jul 21 05:54:51 PM PDT 24
Finished Jul 21 05:54:52 PM PDT 24
Peak memory 182616 kb
Host smart-3ed0117e-d64e-49bd-ab01-3f1cb2aedea9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269527338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.269527338
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.3985108582
Short name T454
Test name
Test status
Simulation time 11482162 ps
CPU time 0.54 seconds
Started Jul 21 05:54:41 PM PDT 24
Finished Jul 21 05:54:42 PM PDT 24
Peak memory 182420 kb
Host smart-b5906a56-7fb8-45e5-a91a-db30074685dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985108582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.3985108582
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2581305370
Short name T490
Test name
Test status
Simulation time 51740595 ps
CPU time 1.05 seconds
Started Jul 21 05:54:45 PM PDT 24
Finished Jul 21 05:54:47 PM PDT 24
Peak memory 197240 kb
Host smart-b6e18c52-2bc8-45cc-9d20-faf311b21b22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581305370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.2581305370
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.884135800
Short name T577
Test name
Test status
Simulation time 78876105 ps
CPU time 1.08 seconds
Started Jul 21 05:54:43 PM PDT 24
Finished Jul 21 05:54:45 PM PDT 24
Peak memory 195184 kb
Host smart-c632d41c-d2ba-4b05-a8dc-29de83e48af4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884135800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_int
g_err.884135800
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.1502649499
Short name T28
Test name
Test status
Simulation time 15153052 ps
CPU time 0.62 seconds
Started Jul 21 05:54:50 PM PDT 24
Finished Jul 21 05:54:52 PM PDT 24
Peak memory 182540 kb
Host smart-cbc91afd-9b8a-4c1e-b2c6-f81c2604273c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502649499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.1502649499
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.924445997
Short name T540
Test name
Test status
Simulation time 2054392062 ps
CPU time 2.46 seconds
Started Jul 21 05:54:50 PM PDT 24
Finished Jul 21 05:54:53 PM PDT 24
Peak memory 190860 kb
Host smart-9db1d6ad-dfd9-4dc9-b623-c3bdd2970c89
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924445997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_b
ash.924445997
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.960536839
Short name T474
Test name
Test status
Simulation time 25788757 ps
CPU time 0.68 seconds
Started Jul 21 05:54:58 PM PDT 24
Finished Jul 21 05:55:00 PM PDT 24
Peak memory 194052 kb
Host smart-d081bb02-fab0-4cb6-af2b-f62e67d511cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960536839 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.960536839
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.2771327228
Short name T86
Test name
Test status
Simulation time 35874092 ps
CPU time 0.57 seconds
Started Jul 21 05:54:49 PM PDT 24
Finished Jul 21 05:54:50 PM PDT 24
Peak memory 182628 kb
Host smart-fa33ea23-5d8f-4f7d-8108-22be2fb668d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771327228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.2771327228
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.4045350169
Short name T576
Test name
Test status
Simulation time 33330111 ps
CPU time 0.52 seconds
Started Jul 21 05:54:50 PM PDT 24
Finished Jul 21 05:54:51 PM PDT 24
Peak memory 181952 kb
Host smart-da7b4ace-53bc-471c-85cd-349324ad7d9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045350169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.4045350169
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.3158576769
Short name T99
Test name
Test status
Simulation time 85364333 ps
CPU time 0.65 seconds
Started Jul 21 05:54:58 PM PDT 24
Finished Jul 21 05:55:00 PM PDT 24
Peak memory 191904 kb
Host smart-f86e315e-b997-4a38-9633-78a52363e3af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158576769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.3158576769
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.831054891
Short name T461
Test name
Test status
Simulation time 225520161 ps
CPU time 2.26 seconds
Started Jul 21 05:54:49 PM PDT 24
Finished Jul 21 05:54:51 PM PDT 24
Peak memory 197296 kb
Host smart-47425c67-9c06-4776-becd-bd04a83ef37b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831054891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.831054891
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.1199465797
Short name T545
Test name
Test status
Simulation time 34926728 ps
CPU time 0.93 seconds
Started Jul 21 05:55:10 PM PDT 24
Finished Jul 21 05:55:12 PM PDT 24
Peak memory 196580 kb
Host smart-e0f83f63-ff4c-4710-8659-d6e4135f477d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199465797 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.1199465797
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.3528214147
Short name T92
Test name
Test status
Simulation time 46753708 ps
CPU time 0.59 seconds
Started Jul 21 05:55:10 PM PDT 24
Finished Jul 21 05:55:11 PM PDT 24
Peak memory 182592 kb
Host smart-5ac9415b-3301-47f1-a049-237450666dc0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528214147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.3528214147
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.4020290569
Short name T567
Test name
Test status
Simulation time 11337681 ps
CPU time 0.56 seconds
Started Jul 21 05:55:09 PM PDT 24
Finished Jul 21 05:55:10 PM PDT 24
Peak memory 182412 kb
Host smart-1e45d644-effe-47b3-9b2a-2a5894d639f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020290569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.4020290569
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.3709482247
Short name T489
Test name
Test status
Simulation time 144091816 ps
CPU time 0.8 seconds
Started Jul 21 05:55:09 PM PDT 24
Finished Jul 21 05:55:10 PM PDT 24
Peak memory 191516 kb
Host smart-da9761e0-a2f5-4531-aa9a-81eeb0153244
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709482247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.3709482247
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.123855413
Short name T451
Test name
Test status
Simulation time 763871512 ps
CPU time 0.99 seconds
Started Jul 21 05:55:08 PM PDT 24
Finished Jul 21 05:55:09 PM PDT 24
Peak memory 196896 kb
Host smart-998974cc-2af0-4520-aea8-73e11b717212
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123855413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.123855413
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.293101269
Short name T25
Test name
Test status
Simulation time 586927197 ps
CPU time 0.8 seconds
Started Jul 21 05:55:09 PM PDT 24
Finished Jul 21 05:55:10 PM PDT 24
Peak memory 193528 kb
Host smart-8395e22f-f85c-4dad-b4ef-f6394b99f8d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293101269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_in
tg_err.293101269
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.3501508216
Short name T564
Test name
Test status
Simulation time 26069758 ps
CPU time 0.79 seconds
Started Jul 21 05:55:19 PM PDT 24
Finished Jul 21 05:55:20 PM PDT 24
Peak memory 194896 kb
Host smart-4c5b1e10-5c15-490c-ae8a-b5ea30731e58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501508216 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.3501508216
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.3221090163
Short name T552
Test name
Test status
Simulation time 39766810 ps
CPU time 0.55 seconds
Started Jul 21 05:55:08 PM PDT 24
Finished Jul 21 05:55:09 PM PDT 24
Peak memory 182640 kb
Host smart-ccd69b90-5574-4211-91fa-34a244f9ef18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221090163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.3221090163
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.4168105053
Short name T566
Test name
Test status
Simulation time 14931450 ps
CPU time 0.57 seconds
Started Jul 21 05:55:10 PM PDT 24
Finished Jul 21 05:55:11 PM PDT 24
Peak memory 182512 kb
Host smart-32fc948f-450c-46e0-ab3b-20e30e4c1b25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168105053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.4168105053
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.977969254
Short name T537
Test name
Test status
Simulation time 37130391 ps
CPU time 0.62 seconds
Started Jul 21 05:55:17 PM PDT 24
Finished Jul 21 05:55:18 PM PDT 24
Peak memory 191524 kb
Host smart-63e1e18e-0d05-484b-bb0c-c6f865a52152
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977969254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_ti
mer_same_csr_outstanding.977969254
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.750656844
Short name T525
Test name
Test status
Simulation time 142771774 ps
CPU time 2.49 seconds
Started Jul 21 05:55:10 PM PDT 24
Finished Jul 21 05:55:13 PM PDT 24
Peak memory 197324 kb
Host smart-4f37ec44-0921-4e04-ac24-2cd211a8b827
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750656844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.750656844
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3933428453
Short name T27
Test name
Test status
Simulation time 51749205 ps
CPU time 0.84 seconds
Started Jul 21 05:55:09 PM PDT 24
Finished Jul 21 05:55:11 PM PDT 24
Peak memory 193512 kb
Host smart-cbf0b304-3359-4327-9c3b-9508650be3e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933428453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.3933428453
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3421692236
Short name T463
Test name
Test status
Simulation time 18884899 ps
CPU time 0.66 seconds
Started Jul 21 05:55:17 PM PDT 24
Finished Jul 21 05:55:18 PM PDT 24
Peak memory 193520 kb
Host smart-4fdc10cf-e55e-4ee8-bcbd-f4fa0c9e20c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421692236 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.3421692236
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.3758420584
Short name T484
Test name
Test status
Simulation time 52708080 ps
CPU time 0.55 seconds
Started Jul 21 05:55:19 PM PDT 24
Finished Jul 21 05:55:20 PM PDT 24
Peak memory 182488 kb
Host smart-16c1be2c-3201-4748-8072-70ae1997e806
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758420584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.3758420584
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3138584927
Short name T575
Test name
Test status
Simulation time 81755311 ps
CPU time 0.69 seconds
Started Jul 21 05:55:15 PM PDT 24
Finished Jul 21 05:55:16 PM PDT 24
Peak memory 191544 kb
Host smart-efa86a62-3bc8-49dd-a7e6-33c794488864
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138584927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.3138584927
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.1618952311
Short name T516
Test name
Test status
Simulation time 62885878 ps
CPU time 0.98 seconds
Started Jul 21 05:55:16 PM PDT 24
Finished Jul 21 05:55:18 PM PDT 24
Peak memory 196388 kb
Host smart-6adc75f9-e6d1-4f61-a646-39d85d9d9d2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618952311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.1618952311
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.3156066105
Short name T524
Test name
Test status
Simulation time 193772081 ps
CPU time 1.09 seconds
Started Jul 21 05:55:15 PM PDT 24
Finished Jul 21 05:55:17 PM PDT 24
Peak memory 195088 kb
Host smart-4a377a08-3d33-429d-8de0-d1483231dade
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156066105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.3156066105
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.562760444
Short name T549
Test name
Test status
Simulation time 72758750 ps
CPU time 0.88 seconds
Started Jul 21 05:55:18 PM PDT 24
Finished Jul 21 05:55:20 PM PDT 24
Peak memory 196884 kb
Host smart-c4615d43-4e42-4e93-8bca-0048d4a36790
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562760444 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.562760444
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.1342578819
Short name T91
Test name
Test status
Simulation time 40388329 ps
CPU time 0.52 seconds
Started Jul 21 05:55:16 PM PDT 24
Finished Jul 21 05:55:18 PM PDT 24
Peak memory 182436 kb
Host smart-768dda35-6257-41ed-9a61-91384bd00a36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342578819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.1342578819
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.2830557833
Short name T464
Test name
Test status
Simulation time 112878339 ps
CPU time 0.53 seconds
Started Jul 21 05:55:15 PM PDT 24
Finished Jul 21 05:55:16 PM PDT 24
Peak memory 182012 kb
Host smart-6b2874f0-f3a1-4622-ab52-ddb3fe513517
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830557833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.2830557833
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1336730051
Short name T565
Test name
Test status
Simulation time 613875776 ps
CPU time 0.81 seconds
Started Jul 21 05:55:18 PM PDT 24
Finished Jul 21 05:55:19 PM PDT 24
Peak memory 193212 kb
Host smart-c5add02d-7a99-4189-8742-7979ae2777c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336730051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.1336730051
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.977176682
Short name T538
Test name
Test status
Simulation time 382650833 ps
CPU time 2.92 seconds
Started Jul 21 05:55:17 PM PDT 24
Finished Jul 21 05:55:20 PM PDT 24
Peak memory 197336 kb
Host smart-3cc9db8f-ce20-47e6-b665-21639be30a09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977176682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.977176682
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.3872346935
Short name T563
Test name
Test status
Simulation time 359807561 ps
CPU time 0.9 seconds
Started Jul 21 05:55:16 PM PDT 24
Finished Jul 21 05:55:18 PM PDT 24
Peak memory 193632 kb
Host smart-8b680499-31ce-4692-a7e5-e837798957bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872346935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.3872346935
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.1467832492
Short name T520
Test name
Test status
Simulation time 118453305 ps
CPU time 0.9 seconds
Started Jul 21 05:55:18 PM PDT 24
Finished Jul 21 05:55:19 PM PDT 24
Peak memory 196440 kb
Host smart-7a88ca6c-41c6-4e36-905b-b6ffbf756968
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467832492 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.1467832492
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3217099226
Short name T473
Test name
Test status
Simulation time 28046138 ps
CPU time 0.62 seconds
Started Jul 21 05:55:19 PM PDT 24
Finished Jul 21 05:55:20 PM PDT 24
Peak memory 182616 kb
Host smart-d6d040ee-79bd-4108-887a-fc46fc56ef4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217099226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.3217099226
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.3725613158
Short name T533
Test name
Test status
Simulation time 36931742 ps
CPU time 0.54 seconds
Started Jul 21 05:55:14 PM PDT 24
Finished Jul 21 05:55:15 PM PDT 24
Peak memory 182536 kb
Host smart-3f071531-d88e-4168-b01d-e115053ca952
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725613158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.3725613158
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.2997090301
Short name T63
Test name
Test status
Simulation time 61814146 ps
CPU time 0.61 seconds
Started Jul 21 05:55:19 PM PDT 24
Finished Jul 21 05:55:20 PM PDT 24
Peak memory 191820 kb
Host smart-c8866373-6a00-4bc6-9329-e76b8396e465
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997090301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.2997090301
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.1034978692
Short name T475
Test name
Test status
Simulation time 50064781 ps
CPU time 0.96 seconds
Started Jul 21 05:55:16 PM PDT 24
Finished Jul 21 05:55:18 PM PDT 24
Peak memory 195776 kb
Host smart-d3b80d74-d12f-426b-961a-d5a3b477c579
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034978692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.1034978692
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.1409940301
Short name T499
Test name
Test status
Simulation time 475704688 ps
CPU time 1.27 seconds
Started Jul 21 05:55:18 PM PDT 24
Finished Jul 21 05:55:19 PM PDT 24
Peak memory 182952 kb
Host smart-2cd12474-1e18-4c8c-8f3a-bb51d40269a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409940301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.1409940301
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1179062026
Short name T572
Test name
Test status
Simulation time 24659939 ps
CPU time 1.1 seconds
Started Jul 21 05:55:16 PM PDT 24
Finished Jul 21 05:55:17 PM PDT 24
Peak memory 197324 kb
Host smart-d99bc4bd-ceb9-4e8c-9af8-9faf92f155b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179062026 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.1179062026
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.3469867043
Short name T544
Test name
Test status
Simulation time 11799725 ps
CPU time 0.57 seconds
Started Jul 21 05:55:14 PM PDT 24
Finished Jul 21 05:55:15 PM PDT 24
Peak memory 182616 kb
Host smart-cda2cd95-d9ac-483d-9fb3-be4046d43c3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469867043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.3469867043
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.3168190346
Short name T492
Test name
Test status
Simulation time 43968926 ps
CPU time 0.52 seconds
Started Jul 21 05:55:15 PM PDT 24
Finished Jul 21 05:55:16 PM PDT 24
Peak memory 181884 kb
Host smart-499eaf30-e27b-4051-bb39-8dae7c3b0c78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168190346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.3168190346
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.1440905550
Short name T96
Test name
Test status
Simulation time 56778212 ps
CPU time 0.6 seconds
Started Jul 21 05:55:16 PM PDT 24
Finished Jul 21 05:55:17 PM PDT 24
Peak memory 191824 kb
Host smart-5229af18-7e4b-4ee0-8134-3460f199dc7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440905550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.1440905550
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.3309069407
Short name T459
Test name
Test status
Simulation time 426920270 ps
CPU time 2 seconds
Started Jul 21 05:55:16 PM PDT 24
Finished Jul 21 05:55:19 PM PDT 24
Peak memory 197288 kb
Host smart-681dc3ae-ab2f-45de-a06d-65878895a7d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309069407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.3309069407
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.322726885
Short name T570
Test name
Test status
Simulation time 97167836 ps
CPU time 1.13 seconds
Started Jul 21 05:55:16 PM PDT 24
Finished Jul 21 05:55:18 PM PDT 24
Peak memory 194864 kb
Host smart-c24e488c-573e-434a-94f9-947f5f65f707
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322726885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_in
tg_err.322726885
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.1921747020
Short name T529
Test name
Test status
Simulation time 211255989 ps
CPU time 0.72 seconds
Started Jul 21 05:55:25 PM PDT 24
Finished Jul 21 05:55:26 PM PDT 24
Peak memory 194372 kb
Host smart-3d39d8db-4150-4ff0-b7c1-74e625b4e4a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921747020 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.1921747020
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.1159617001
Short name T87
Test name
Test status
Simulation time 35171959 ps
CPU time 0.58 seconds
Started Jul 21 05:55:19 PM PDT 24
Finished Jul 21 05:55:20 PM PDT 24
Peak memory 182600 kb
Host smart-1727264b-48bf-4cfd-875b-72aefe93d1eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159617001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.1159617001
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.4000351093
Short name T496
Test name
Test status
Simulation time 46334937 ps
CPU time 0.61 seconds
Started Jul 21 05:55:16 PM PDT 24
Finished Jul 21 05:55:18 PM PDT 24
Peak memory 182508 kb
Host smart-56278958-f7be-4d84-9604-cbba896bbc1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000351093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.4000351093
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1537911808
Short name T502
Test name
Test status
Simulation time 55147798 ps
CPU time 0.77 seconds
Started Jul 21 05:55:21 PM PDT 24
Finished Jul 21 05:55:22 PM PDT 24
Peak memory 193336 kb
Host smart-66d28ae6-9f3f-47b1-9fb6-eb4d381cbcac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537911808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.1537911808
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.540865060
Short name T506
Test name
Test status
Simulation time 142047105 ps
CPU time 1.08 seconds
Started Jul 21 05:55:25 PM PDT 24
Finished Jul 21 05:55:26 PM PDT 24
Peak memory 197280 kb
Host smart-c2d5b44f-1558-430d-80bf-0d324c4dc827
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540865060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.540865060
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.70766169
Short name T559
Test name
Test status
Simulation time 21330905 ps
CPU time 0.92 seconds
Started Jul 21 05:55:21 PM PDT 24
Finished Jul 21 05:55:23 PM PDT 24
Peak memory 197012 kb
Host smart-67ba8763-fec3-485b-9245-669d4f4228d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70766169 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.70766169
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.891081210
Short name T562
Test name
Test status
Simulation time 49446150 ps
CPU time 0.58 seconds
Started Jul 21 05:55:20 PM PDT 24
Finished Jul 21 05:55:22 PM PDT 24
Peak memory 182604 kb
Host smart-fe7a3037-891a-4b02-9136-0aea170336e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891081210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.891081210
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.914645324
Short name T539
Test name
Test status
Simulation time 13364672 ps
CPU time 0.64 seconds
Started Jul 21 05:55:23 PM PDT 24
Finished Jul 21 05:55:24 PM PDT 24
Peak memory 182472 kb
Host smart-dbbf5ac3-0dd7-4384-8072-0f22626b5813
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914645324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.914645324
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.535905312
Short name T100
Test name
Test status
Simulation time 45247582 ps
CPU time 0.71 seconds
Started Jul 21 05:55:21 PM PDT 24
Finished Jul 21 05:55:22 PM PDT 24
Peak memory 193184 kb
Host smart-af9536df-e54e-40b5-990a-9aee4bbc2070
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535905312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_ti
mer_same_csr_outstanding.535905312
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.3168673943
Short name T468
Test name
Test status
Simulation time 664194424 ps
CPU time 2.72 seconds
Started Jul 21 05:55:23 PM PDT 24
Finished Jul 21 05:55:26 PM PDT 24
Peak memory 197296 kb
Host smart-bd2ca822-c081-45be-a48f-377f6e4c85c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168673943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.3168673943
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.2977044918
Short name T578
Test name
Test status
Simulation time 279958189 ps
CPU time 1.04 seconds
Started Jul 21 05:55:20 PM PDT 24
Finished Jul 21 05:55:21 PM PDT 24
Peak memory 183076 kb
Host smart-be6e6c4a-0835-409f-8f01-81a609c9c972
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977044918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.2977044918
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3649556123
Short name T536
Test name
Test status
Simulation time 38848500 ps
CPU time 0.71 seconds
Started Jul 21 05:55:21 PM PDT 24
Finished Jul 21 05:55:22 PM PDT 24
Peak memory 194232 kb
Host smart-b47cebe0-efc1-4374-84d6-673c521806dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649556123 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.3649556123
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.2916167330
Short name T498
Test name
Test status
Simulation time 52377934 ps
CPU time 0.61 seconds
Started Jul 21 05:55:21 PM PDT 24
Finished Jul 21 05:55:22 PM PDT 24
Peak memory 182600 kb
Host smart-dcab9ed5-067d-4461-b6fb-cd41c2eedef4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916167330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.2916167330
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.3511758231
Short name T482
Test name
Test status
Simulation time 18194288 ps
CPU time 0.55 seconds
Started Jul 21 05:55:22 PM PDT 24
Finished Jul 21 05:55:23 PM PDT 24
Peak memory 182168 kb
Host smart-2e6cbcdf-5c5f-47e0-ae10-fed48b07627d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511758231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.3511758231
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1984483229
Short name T50
Test name
Test status
Simulation time 45634075 ps
CPU time 0.62 seconds
Started Jul 21 05:55:22 PM PDT 24
Finished Jul 21 05:55:23 PM PDT 24
Peak memory 191912 kb
Host smart-3ee77940-00b2-4971-863c-2b781093cd43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984483229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.1984483229
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3181250837
Short name T487
Test name
Test status
Simulation time 309753192 ps
CPU time 1.62 seconds
Started Jul 21 05:55:23 PM PDT 24
Finished Jul 21 05:55:25 PM PDT 24
Peak memory 197336 kb
Host smart-ea49d468-e34a-424d-b878-56e5603742e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181250837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.3181250837
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.3512689907
Short name T527
Test name
Test status
Simulation time 178225804 ps
CPU time 0.88 seconds
Started Jul 21 05:55:22 PM PDT 24
Finished Jul 21 05:55:23 PM PDT 24
Peak memory 193696 kb
Host smart-d31fe791-e462-44c4-8c47-56d3663efd3c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512689907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.3512689907
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.2674121288
Short name T553
Test name
Test status
Simulation time 62670168 ps
CPU time 0.82 seconds
Started Jul 21 05:55:20 PM PDT 24
Finished Jul 21 05:55:22 PM PDT 24
Peak memory 195104 kb
Host smart-c222f412-4bfb-402c-ad33-7aab5e911310
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674121288 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.2674121288
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.3579085869
Short name T555
Test name
Test status
Simulation time 23917355 ps
CPU time 0.6 seconds
Started Jul 21 05:55:23 PM PDT 24
Finished Jul 21 05:55:24 PM PDT 24
Peak memory 182644 kb
Host smart-eb4e6c69-aa96-4c34-8dd2-e9641e80b70e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579085869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.3579085869
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.1535106520
Short name T550
Test name
Test status
Simulation time 62099629 ps
CPU time 0.53 seconds
Started Jul 21 05:55:26 PM PDT 24
Finished Jul 21 05:55:27 PM PDT 24
Peak memory 181924 kb
Host smart-4bdc3e75-7914-4c00-b1ad-5c919a511d4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535106520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.1535106520
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.990195366
Short name T98
Test name
Test status
Simulation time 58618274 ps
CPU time 0.59 seconds
Started Jul 21 05:55:20 PM PDT 24
Finished Jul 21 05:55:21 PM PDT 24
Peak memory 191308 kb
Host smart-a2d1b770-1d3c-4989-b1ba-5be6ad3a6126
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990195366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_ti
mer_same_csr_outstanding.990195366
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3934572493
Short name T455
Test name
Test status
Simulation time 841810775 ps
CPU time 3.25 seconds
Started Jul 21 05:55:20 PM PDT 24
Finished Jul 21 05:55:24 PM PDT 24
Peak memory 197248 kb
Host smart-d514f840-b5d5-4b69-89df-8f9e7c7f8a01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934572493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.3934572493
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1623808522
Short name T26
Test name
Test status
Simulation time 258716738 ps
CPU time 1.05 seconds
Started Jul 21 05:55:20 PM PDT 24
Finished Jul 21 05:55:21 PM PDT 24
Peak memory 195096 kb
Host smart-e252de0a-a3da-4631-9c47-ad4e8d5ce008
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623808522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.1623808522
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.3096634987
Short name T81
Test name
Test status
Simulation time 26001697 ps
CPU time 0.71 seconds
Started Jul 21 05:55:02 PM PDT 24
Finished Jul 21 05:55:03 PM PDT 24
Peak memory 182520 kb
Host smart-692928b8-217c-46e9-98bb-80e3aace8953
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096634987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.3096634987
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.727779145
Short name T508
Test name
Test status
Simulation time 240424965 ps
CPU time 2.2 seconds
Started Jul 21 05:54:58 PM PDT 24
Finished Jul 21 05:55:01 PM PDT 24
Peak memory 182868 kb
Host smart-0f4cdad8-87cd-4b71-9865-4eaf9bb6b873
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727779145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_b
ash.727779145
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.1432831037
Short name T51
Test name
Test status
Simulation time 14535146 ps
CPU time 0.56 seconds
Started Jul 21 05:54:55 PM PDT 24
Finished Jul 21 05:54:56 PM PDT 24
Peak memory 182656 kb
Host smart-4cc0da23-aa28-498f-a245-594fd9937039
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432831037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.1432831037
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.908179402
Short name T573
Test name
Test status
Simulation time 117597589 ps
CPU time 0.83 seconds
Started Jul 21 05:54:56 PM PDT 24
Finished Jul 21 05:54:57 PM PDT 24
Peak memory 196196 kb
Host smart-826855a1-a4d5-4d6f-9789-6deeff2074b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908179402 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.908179402
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.4290059030
Short name T90
Test name
Test status
Simulation time 15580612 ps
CPU time 0.57 seconds
Started Jul 21 05:54:58 PM PDT 24
Finished Jul 21 05:55:00 PM PDT 24
Peak memory 182628 kb
Host smart-4e364cae-c061-4583-9dc5-0968c918c1cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290059030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.4290059030
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.1402694007
Short name T503
Test name
Test status
Simulation time 18902446 ps
CPU time 0.57 seconds
Started Jul 21 05:54:55 PM PDT 24
Finished Jul 21 05:54:56 PM PDT 24
Peak memory 182468 kb
Host smart-1664e552-7902-443e-b093-42751e02ece9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402694007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.1402694007
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.3318281001
Short name T551
Test name
Test status
Simulation time 18657414 ps
CPU time 0.77 seconds
Started Jul 21 05:54:56 PM PDT 24
Finished Jul 21 05:54:58 PM PDT 24
Peak memory 193404 kb
Host smart-6c3789da-90e7-4265-9fad-170785bb8bdd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318281001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.3318281001
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.2801066956
Short name T457
Test name
Test status
Simulation time 189581548 ps
CPU time 1.11 seconds
Started Jul 21 05:54:57 PM PDT 24
Finished Jul 21 05:54:59 PM PDT 24
Peak memory 197268 kb
Host smart-0ae871e6-605a-4ce3-ab71-48916db196f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801066956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.2801066956
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.142882392
Short name T542
Test name
Test status
Simulation time 842955476 ps
CPU time 1.31 seconds
Started Jul 21 05:54:55 PM PDT 24
Finished Jul 21 05:54:57 PM PDT 24
Peak memory 183008 kb
Host smart-1c1410a1-c36f-4789-b4a2-ddf1f4570415
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142882392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_int
g_err.142882392
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.3753891365
Short name T483
Test name
Test status
Simulation time 15537101 ps
CPU time 0.58 seconds
Started Jul 21 05:55:21 PM PDT 24
Finished Jul 21 05:55:22 PM PDT 24
Peak memory 182496 kb
Host smart-6e4bd386-1e46-4872-b74c-07824654690b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753891365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.3753891365
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.3438816809
Short name T486
Test name
Test status
Simulation time 40543038 ps
CPU time 0.57 seconds
Started Jul 21 05:55:25 PM PDT 24
Finished Jul 21 05:55:26 PM PDT 24
Peak memory 182448 kb
Host smart-7316369d-8bf3-4827-987c-9dce1abf4459
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438816809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.3438816809
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.665629838
Short name T466
Test name
Test status
Simulation time 13224015 ps
CPU time 0.55 seconds
Started Jul 21 05:55:23 PM PDT 24
Finished Jul 21 05:55:24 PM PDT 24
Peak memory 182492 kb
Host smart-04b52034-95b7-458f-bb62-ba6ce4afeb6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665629838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.665629838
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.1060605380
Short name T526
Test name
Test status
Simulation time 65525825 ps
CPU time 0.57 seconds
Started Jul 21 05:55:23 PM PDT 24
Finished Jul 21 05:55:24 PM PDT 24
Peak memory 182480 kb
Host smart-5ce10416-a345-4c8d-84e0-a2cc32ed92fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060605380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.1060605380
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2133209812
Short name T556
Test name
Test status
Simulation time 15604095 ps
CPU time 0.55 seconds
Started Jul 21 05:55:27 PM PDT 24
Finished Jul 21 05:55:28 PM PDT 24
Peak memory 182060 kb
Host smart-570cb990-6a02-408a-8e3c-caa8116c5459
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133209812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.2133209812
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.4216491770
Short name T571
Test name
Test status
Simulation time 42287252 ps
CPU time 0.52 seconds
Started Jul 21 05:55:28 PM PDT 24
Finished Jul 21 05:55:29 PM PDT 24
Peak memory 182464 kb
Host smart-dcba7ecb-8690-490c-896f-9191ed696f16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216491770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.4216491770
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1938170623
Short name T491
Test name
Test status
Simulation time 74368174 ps
CPU time 0.56 seconds
Started Jul 21 05:55:32 PM PDT 24
Finished Jul 21 05:55:33 PM PDT 24
Peak memory 182128 kb
Host smart-bc2d7a8c-be7c-40dc-953f-a61efa0bf7c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938170623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.1938170623
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.1109527320
Short name T497
Test name
Test status
Simulation time 34479854 ps
CPU time 0.54 seconds
Started Jul 21 05:55:37 PM PDT 24
Finished Jul 21 05:55:38 PM PDT 24
Peak memory 182528 kb
Host smart-1e92f1c3-89f8-43bd-a17a-0f472b7f44b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109527320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.1109527320
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2781242830
Short name T480
Test name
Test status
Simulation time 15637833 ps
CPU time 0.55 seconds
Started Jul 21 05:55:34 PM PDT 24
Finished Jul 21 05:55:34 PM PDT 24
Peak memory 182532 kb
Host smart-77cf2755-8cef-4118-b6c0-34e6bb93eafd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781242830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.2781242830
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.695468652
Short name T546
Test name
Test status
Simulation time 46080119 ps
CPU time 0.55 seconds
Started Jul 21 05:55:35 PM PDT 24
Finished Jul 21 05:55:36 PM PDT 24
Peak memory 182476 kb
Host smart-ef7351e3-f6ea-4545-b54e-c79fc3703eb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695468652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.695468652
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.2872490355
Short name T88
Test name
Test status
Simulation time 89136832 ps
CPU time 0.7 seconds
Started Jul 21 05:54:58 PM PDT 24
Finished Jul 21 05:55:00 PM PDT 24
Peak memory 192084 kb
Host smart-0c9a7960-da39-4f89-b0f1-9ee6d956060d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872490355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.2872490355
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.3317654979
Short name T93
Test name
Test status
Simulation time 431785400 ps
CPU time 3.68 seconds
Started Jul 21 05:54:56 PM PDT 24
Finished Jul 21 05:55:00 PM PDT 24
Peak memory 193192 kb
Host smart-41cb65a2-06b7-4a88-b21f-3df03927f6d3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317654979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.3317654979
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.939363169
Short name T82
Test name
Test status
Simulation time 16238809 ps
CPU time 0.58 seconds
Started Jul 21 05:54:55 PM PDT 24
Finished Jul 21 05:54:56 PM PDT 24
Peak memory 191904 kb
Host smart-486ce92c-6805-488b-ac0c-ffd7b55a2f9c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939363169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_re
set.939363169
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.164864716
Short name T495
Test name
Test status
Simulation time 16914757 ps
CPU time 0.8 seconds
Started Jul 21 05:54:58 PM PDT 24
Finished Jul 21 05:55:00 PM PDT 24
Peak memory 195812 kb
Host smart-0dbe7797-1d5e-4da1-8f6c-c1add37a644e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164864716 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.164864716
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.2723895146
Short name T569
Test name
Test status
Simulation time 54069314 ps
CPU time 0.57 seconds
Started Jul 21 05:54:58 PM PDT 24
Finished Jul 21 05:55:00 PM PDT 24
Peak memory 182552 kb
Host smart-dd2b78a7-484c-4334-8958-38286e547636
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723895146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.2723895146
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.172588058
Short name T493
Test name
Test status
Simulation time 13601080 ps
CPU time 0.53 seconds
Started Jul 21 05:54:58 PM PDT 24
Finished Jul 21 05:54:59 PM PDT 24
Peak memory 182484 kb
Host smart-63eba924-1f2a-48a5-8f66-b3b651481e79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172588058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.172588058
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.2440353379
Short name T541
Test name
Test status
Simulation time 40599656 ps
CPU time 0.62 seconds
Started Jul 21 05:54:58 PM PDT 24
Finished Jul 21 05:55:00 PM PDT 24
Peak memory 191416 kb
Host smart-418bd0d4-2d67-4e7b-af6b-5916e9a0c2f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440353379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.2440353379
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3514671151
Short name T518
Test name
Test status
Simulation time 42197165 ps
CPU time 1.95 seconds
Started Jul 21 05:54:56 PM PDT 24
Finished Jul 21 05:54:59 PM PDT 24
Peak memory 197300 kb
Host smart-97a7855c-122f-43e4-b169-88a6e5588ea8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514671151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.3514671151
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.1036995604
Short name T557
Test name
Test status
Simulation time 446998694 ps
CPU time 1.14 seconds
Started Jul 21 05:54:57 PM PDT 24
Finished Jul 21 05:55:00 PM PDT 24
Peak memory 182968 kb
Host smart-523c34cf-1e32-4d9f-985f-3d9ae909fd59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036995604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.1036995604
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.513254774
Short name T530
Test name
Test status
Simulation time 79277497 ps
CPU time 0.54 seconds
Started Jul 21 05:55:26 PM PDT 24
Finished Jul 21 05:55:27 PM PDT 24
Peak memory 181896 kb
Host smart-3bb06cc6-2de8-4e27-adb8-6f09f63d6977
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513254774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.513254774
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.3362036941
Short name T477
Test name
Test status
Simulation time 40274487 ps
CPU time 0.55 seconds
Started Jul 21 05:55:34 PM PDT 24
Finished Jul 21 05:55:35 PM PDT 24
Peak memory 182440 kb
Host smart-b2de2b3f-2a6e-426d-a455-9399df57beeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362036941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.3362036941
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.3753702978
Short name T534
Test name
Test status
Simulation time 48731808 ps
CPU time 0.6 seconds
Started Jul 21 05:55:29 PM PDT 24
Finished Jul 21 05:55:30 PM PDT 24
Peak memory 182392 kb
Host smart-218c96ec-0e88-464a-a34a-ed30159bfe82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753702978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.3753702978
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3397606229
Short name T535
Test name
Test status
Simulation time 12369055 ps
CPU time 0.55 seconds
Started Jul 21 05:55:35 PM PDT 24
Finished Jul 21 05:55:36 PM PDT 24
Peak memory 181980 kb
Host smart-82af0829-994f-4118-9f5f-9543eeb84a64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397606229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.3397606229
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.3706745991
Short name T469
Test name
Test status
Simulation time 11572802 ps
CPU time 0.55 seconds
Started Jul 21 05:55:30 PM PDT 24
Finished Jul 21 05:55:31 PM PDT 24
Peak memory 182144 kb
Host smart-11b4c46e-87b9-47d3-a1da-87ca3bfa638b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706745991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.3706745991
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.3572172024
Short name T515
Test name
Test status
Simulation time 24195403 ps
CPU time 0.55 seconds
Started Jul 21 05:55:28 PM PDT 24
Finished Jul 21 05:55:29 PM PDT 24
Peak memory 182504 kb
Host smart-fcd5c9a5-7c2b-4a58-9732-a2b6f025ff11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572172024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.3572172024
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.48229950
Short name T456
Test name
Test status
Simulation time 28879960 ps
CPU time 0.54 seconds
Started Jul 21 05:55:31 PM PDT 24
Finished Jul 21 05:55:31 PM PDT 24
Peak memory 181932 kb
Host smart-b1cc52fc-a952-4fe6-86c5-9d5b758c4946
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48229950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.48229950
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.3796224699
Short name T453
Test name
Test status
Simulation time 23482893 ps
CPU time 0.58 seconds
Started Jul 21 05:55:31 PM PDT 24
Finished Jul 21 05:55:32 PM PDT 24
Peak memory 182492 kb
Host smart-b6f07e95-cda4-40e1-9889-75b0d4e3d5cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796224699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.3796224699
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.3174018165
Short name T501
Test name
Test status
Simulation time 16042009 ps
CPU time 0.58 seconds
Started Jul 21 05:55:30 PM PDT 24
Finished Jul 21 05:55:31 PM PDT 24
Peak memory 182580 kb
Host smart-9298a2bb-c062-47e0-8cd6-d397f3794f70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174018165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.3174018165
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.2759627318
Short name T452
Test name
Test status
Simulation time 33490057 ps
CPU time 0.54 seconds
Started Jul 21 05:55:28 PM PDT 24
Finished Jul 21 05:55:28 PM PDT 24
Peak memory 182464 kb
Host smart-8b1283d9-d8ac-4c78-aaba-a5ae2b7a275b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759627318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.2759627318
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.2373061435
Short name T54
Test name
Test status
Simulation time 37584262 ps
CPU time 0.81 seconds
Started Jul 21 05:55:00 PM PDT 24
Finished Jul 21 05:55:01 PM PDT 24
Peak memory 182592 kb
Host smart-536422f9-b87f-4f08-bf6a-9ce926b3f0f7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373061435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.2373061435
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.1963926355
Short name T521
Test name
Test status
Simulation time 274444490 ps
CPU time 1.4 seconds
Started Jul 21 05:54:57 PM PDT 24
Finished Jul 21 05:55:00 PM PDT 24
Peak memory 192420 kb
Host smart-77cb026a-f66f-494c-ad41-5eb369e712ad
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963926355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.1963926355
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.1647041038
Short name T83
Test name
Test status
Simulation time 86333825 ps
CPU time 0.58 seconds
Started Jul 21 05:54:56 PM PDT 24
Finished Jul 21 05:54:58 PM PDT 24
Peak memory 182580 kb
Host smart-d10a1ad5-5732-4503-b8c0-52b416b961c1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647041038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.1647041038
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.4049467254
Short name T528
Test name
Test status
Simulation time 39531702 ps
CPU time 0.92 seconds
Started Jul 21 05:55:03 PM PDT 24
Finished Jul 21 05:55:05 PM PDT 24
Peak memory 197104 kb
Host smart-07f8e254-df10-43a1-9032-567e5c2c646a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049467254 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.4049467254
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.1180469562
Short name T89
Test name
Test status
Simulation time 53502037 ps
CPU time 0.59 seconds
Started Jul 21 05:54:58 PM PDT 24
Finished Jul 21 05:54:59 PM PDT 24
Peak memory 182588 kb
Host smart-7c4159ab-c8ae-4440-bf75-79940c5380ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180469562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.1180469562
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.3677539805
Short name T485
Test name
Test status
Simulation time 17248129 ps
CPU time 0.56 seconds
Started Jul 21 05:54:56 PM PDT 24
Finished Jul 21 05:54:58 PM PDT 24
Peak memory 182524 kb
Host smart-0289f61b-cff8-4103-baf9-7d632eff7e8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677539805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.3677539805
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.3711573777
Short name T509
Test name
Test status
Simulation time 41409184 ps
CPU time 0.83 seconds
Started Jul 21 05:55:05 PM PDT 24
Finished Jul 21 05:55:07 PM PDT 24
Peak memory 193344 kb
Host smart-505bdb34-ff8e-48ad-a772-638d1a2fb3c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711573777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.3711573777
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2491679630
Short name T500
Test name
Test status
Simulation time 256597331 ps
CPU time 1.65 seconds
Started Jul 21 05:54:59 PM PDT 24
Finished Jul 21 05:55:02 PM PDT 24
Peak memory 197312 kb
Host smart-7e641929-2daf-4120-893b-d222c28fba9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491679630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.2491679630
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.3805884357
Short name T106
Test name
Test status
Simulation time 407716757 ps
CPU time 1.09 seconds
Started Jul 21 05:54:57 PM PDT 24
Finished Jul 21 05:54:59 PM PDT 24
Peak memory 191424 kb
Host smart-c2048249-744f-47ae-8696-ed64450503ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805884357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.3805884357
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.3971198385
Short name T460
Test name
Test status
Simulation time 14476895 ps
CPU time 0.54 seconds
Started Jul 21 05:55:36 PM PDT 24
Finished Jul 21 05:55:37 PM PDT 24
Peak memory 181952 kb
Host smart-0e97f05a-9e2d-4a26-a703-c87d21ac1449
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971198385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.3971198385
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.2622282344
Short name T532
Test name
Test status
Simulation time 13782528 ps
CPU time 0.56 seconds
Started Jul 21 05:55:31 PM PDT 24
Finished Jul 21 05:55:32 PM PDT 24
Peak memory 181928 kb
Host smart-5e7823cb-d90c-4e68-8bea-d5da62d95335
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622282344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.2622282344
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.3440116354
Short name T458
Test name
Test status
Simulation time 23478149 ps
CPU time 0.54 seconds
Started Jul 21 05:55:27 PM PDT 24
Finished Jul 21 05:55:28 PM PDT 24
Peak memory 182092 kb
Host smart-daaa2219-ac55-41c7-acb4-135b29d0a10b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440116354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.3440116354
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.190143656
Short name T510
Test name
Test status
Simulation time 25117489 ps
CPU time 0.57 seconds
Started Jul 21 05:55:38 PM PDT 24
Finished Jul 21 05:55:39 PM PDT 24
Peak memory 182448 kb
Host smart-ba29eb7a-3bc6-44fa-beaf-6fe5d25fabe1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190143656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.190143656
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.2773608123
Short name T471
Test name
Test status
Simulation time 65634715 ps
CPU time 0.53 seconds
Started Jul 21 05:55:39 PM PDT 24
Finished Jul 21 05:55:40 PM PDT 24
Peak memory 181992 kb
Host smart-93bfba73-c225-473b-a689-0584aa6df16a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773608123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.2773608123
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.3368941412
Short name T462
Test name
Test status
Simulation time 19690362 ps
CPU time 0.57 seconds
Started Jul 21 05:55:28 PM PDT 24
Finished Jul 21 05:55:29 PM PDT 24
Peak memory 182448 kb
Host smart-7150363a-23e7-4aa7-b4b6-8dc3b56bbcf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368941412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.3368941412
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.1504443255
Short name T523
Test name
Test status
Simulation time 18866893 ps
CPU time 0.57 seconds
Started Jul 21 05:55:31 PM PDT 24
Finished Jul 21 05:55:32 PM PDT 24
Peak memory 181984 kb
Host smart-f3b5cae8-14c7-4672-9a0a-9dc05a41b73e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504443255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.1504443255
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.4278084996
Short name T507
Test name
Test status
Simulation time 11344008 ps
CPU time 0.55 seconds
Started Jul 21 05:55:26 PM PDT 24
Finished Jul 21 05:55:27 PM PDT 24
Peak memory 182392 kb
Host smart-458b66a0-7132-491d-950f-1eb31dffc58d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278084996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.4278084996
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.1879284848
Short name T543
Test name
Test status
Simulation time 32675192 ps
CPU time 0.57 seconds
Started Jul 21 05:55:30 PM PDT 24
Finished Jul 21 05:55:31 PM PDT 24
Peak memory 182460 kb
Host smart-2ca083cd-abf5-4851-b6e3-22f989d3545a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879284848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.1879284848
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.2833675666
Short name T531
Test name
Test status
Simulation time 11599755 ps
CPU time 0.57 seconds
Started Jul 21 05:55:34 PM PDT 24
Finished Jul 21 05:55:35 PM PDT 24
Peak memory 182384 kb
Host smart-5ca468d4-8ec7-46ba-9adf-992ad8fd9f9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833675666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.2833675666
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2031381281
Short name T53
Test name
Test status
Simulation time 83065053 ps
CPU time 0.79 seconds
Started Jul 21 05:55:04 PM PDT 24
Finished Jul 21 05:55:05 PM PDT 24
Peak memory 194544 kb
Host smart-1dc1f0f8-23ad-46b1-a6c9-33e5f619ad7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031381281 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.2031381281
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.1027857108
Short name T85
Test name
Test status
Simulation time 72270963 ps
CPU time 0.56 seconds
Started Jul 21 05:55:03 PM PDT 24
Finished Jul 21 05:55:04 PM PDT 24
Peak memory 182540 kb
Host smart-f00501f3-8e3a-4379-8e45-4ab7a619d1ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027857108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.1027857108
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.20543321
Short name T470
Test name
Test status
Simulation time 13372168 ps
CPU time 0.54 seconds
Started Jul 21 05:55:02 PM PDT 24
Finished Jul 21 05:55:03 PM PDT 24
Peak memory 181912 kb
Host smart-51f90a78-07fe-435a-9100-653b44a1ba9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20543321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.20543321
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.454066701
Short name T30
Test name
Test status
Simulation time 31496636 ps
CPU time 0.65 seconds
Started Jul 21 05:55:05 PM PDT 24
Finished Jul 21 05:55:06 PM PDT 24
Peak memory 191832 kb
Host smart-2b55b2a6-ffbc-4950-9d04-a3c2597ab08b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454066701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_tim
er_same_csr_outstanding.454066701
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.3717792621
Short name T548
Test name
Test status
Simulation time 310774869 ps
CPU time 1.94 seconds
Started Jul 21 05:55:04 PM PDT 24
Finished Jul 21 05:55:06 PM PDT 24
Peak memory 197336 kb
Host smart-3bbd36a1-e133-4f00-8dee-25b6aaa0449f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717792621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.3717792621
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.867447214
Short name T479
Test name
Test status
Simulation time 136256344 ps
CPU time 1.32 seconds
Started Jul 21 05:55:05 PM PDT 24
Finished Jul 21 05:55:07 PM PDT 24
Peak memory 195292 kb
Host smart-46c2cb19-2c8d-449e-85a2-decde9a3ad83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867447214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_int
g_err.867447214
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.2867295269
Short name T488
Test name
Test status
Simulation time 116949881 ps
CPU time 1.47 seconds
Started Jul 21 05:55:04 PM PDT 24
Finished Jul 21 05:55:06 PM PDT 24
Peak memory 197344 kb
Host smart-0874b08a-f65b-4473-984e-914b716e36e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867295269 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.2867295269
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.3094568552
Short name T84
Test name
Test status
Simulation time 37689400 ps
CPU time 0.56 seconds
Started Jul 21 05:55:09 PM PDT 24
Finished Jul 21 05:55:10 PM PDT 24
Peak memory 182768 kb
Host smart-8291175d-f307-4ef3-974e-6847cca0b0e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094568552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.3094568552
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.1119099184
Short name T517
Test name
Test status
Simulation time 14803181 ps
CPU time 0.52 seconds
Started Jul 21 05:55:03 PM PDT 24
Finished Jul 21 05:55:04 PM PDT 24
Peak memory 182172 kb
Host smart-3f66b24c-387d-45cc-8cde-519d724f489f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119099184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.1119099184
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.209816178
Short name T72
Test name
Test status
Simulation time 25549186 ps
CPU time 0.64 seconds
Started Jul 21 05:55:04 PM PDT 24
Finished Jul 21 05:55:05 PM PDT 24
Peak memory 192052 kb
Host smart-b4c10422-587e-4e2e-9f65-e024c0322e44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209816178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_tim
er_same_csr_outstanding.209816178
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.3693541811
Short name T512
Test name
Test status
Simulation time 794721893 ps
CPU time 1.3 seconds
Started Jul 21 05:55:04 PM PDT 24
Finished Jul 21 05:55:06 PM PDT 24
Peak memory 197348 kb
Host smart-38d0a7d5-d70f-47de-aabf-70931ef78e62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693541811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.3693541811
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.1421724212
Short name T105
Test name
Test status
Simulation time 164349444 ps
CPU time 1.06 seconds
Started Jul 21 05:55:01 PM PDT 24
Finished Jul 21 05:55:03 PM PDT 24
Peak memory 194464 kb
Host smart-37c44d39-f86d-4a1f-a49b-7cf0e52ec5cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421724212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.1421724212
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.4251134278
Short name T560
Test name
Test status
Simulation time 83683284 ps
CPU time 1.04 seconds
Started Jul 21 05:55:02 PM PDT 24
Finished Jul 21 05:55:04 PM PDT 24
Peak memory 197252 kb
Host smart-919499a6-4101-470e-b109-2826349fb734
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251134278 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.4251134278
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.3386409733
Short name T80
Test name
Test status
Simulation time 11372755 ps
CPU time 0.59 seconds
Started Jul 21 05:55:05 PM PDT 24
Finished Jul 21 05:55:06 PM PDT 24
Peak memory 182540 kb
Host smart-764498c3-bcad-4bd1-a3d4-2593c81bce7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386409733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.3386409733
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.3115318953
Short name T513
Test name
Test status
Simulation time 12852552 ps
CPU time 0.59 seconds
Started Jul 21 05:55:08 PM PDT 24
Finished Jul 21 05:55:09 PM PDT 24
Peak memory 182320 kb
Host smart-0616152b-efbc-4914-8515-3e897051722d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115318953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.3115318953
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.2330656942
Short name T519
Test name
Test status
Simulation time 31553675 ps
CPU time 0.79 seconds
Started Jul 21 05:55:03 PM PDT 24
Finished Jul 21 05:55:04 PM PDT 24
Peak memory 193228 kb
Host smart-cff81585-b11d-4d94-9e82-314e41b2dfa3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330656942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.2330656942
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.3635367537
Short name T467
Test name
Test status
Simulation time 329797001 ps
CPU time 1.87 seconds
Started Jul 21 05:55:02 PM PDT 24
Finished Jul 21 05:55:04 PM PDT 24
Peak memory 197308 kb
Host smart-fb712781-22f0-432e-93c8-d7b12c45daf1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635367537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.3635367537
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.3782069947
Short name T522
Test name
Test status
Simulation time 150347377 ps
CPU time 1.09 seconds
Started Jul 21 05:55:01 PM PDT 24
Finished Jul 21 05:55:03 PM PDT 24
Peak memory 195008 kb
Host smart-205f0347-1d9f-446b-83e2-909ecc597fa2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782069947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.3782069947
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.443951500
Short name T568
Test name
Test status
Simulation time 75064619 ps
CPU time 0.93 seconds
Started Jul 21 05:55:02 PM PDT 24
Finished Jul 21 05:55:03 PM PDT 24
Peak memory 195808 kb
Host smart-4f9b4436-a132-4620-8d26-ab53fde92bda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443951500 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.443951500
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.1207718426
Short name T547
Test name
Test status
Simulation time 16930837 ps
CPU time 0.6 seconds
Started Jul 21 05:55:02 PM PDT 24
Finished Jul 21 05:55:03 PM PDT 24
Peak memory 182600 kb
Host smart-90f73479-88a7-4b2d-a7bb-a81ac38482c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207718426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.1207718426
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.2450503809
Short name T514
Test name
Test status
Simulation time 37940941 ps
CPU time 0.56 seconds
Started Jul 21 05:55:02 PM PDT 24
Finished Jul 21 05:55:03 PM PDT 24
Peak memory 182360 kb
Host smart-590bac02-0892-4d2e-9817-c58e3ad94523
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450503809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.2450503809
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.1790384017
Short name T95
Test name
Test status
Simulation time 74232589 ps
CPU time 0.8 seconds
Started Jul 21 05:55:03 PM PDT 24
Finished Jul 21 05:55:04 PM PDT 24
Peak memory 193436 kb
Host smart-f054057f-bbc8-45e8-a626-97b63891b82f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790384017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.1790384017
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3549531811
Short name T561
Test name
Test status
Simulation time 96243478 ps
CPU time 2.14 seconds
Started Jul 21 05:55:05 PM PDT 24
Finished Jul 21 05:55:08 PM PDT 24
Peak memory 197332 kb
Host smart-a9c2e3bd-84e4-4e1b-a79a-5e1810cf9f50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549531811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.3549531811
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.1143183299
Short name T554
Test name
Test status
Simulation time 84639599 ps
CPU time 1.14 seconds
Started Jul 21 05:55:04 PM PDT 24
Finished Jul 21 05:55:05 PM PDT 24
Peak memory 195120 kb
Host smart-fec20352-34be-4eb8-a827-ff60563aec7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143183299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.1143183299
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3066683165
Short name T505
Test name
Test status
Simulation time 76415832 ps
CPU time 1 seconds
Started Jul 21 05:55:12 PM PDT 24
Finished Jul 21 05:55:13 PM PDT 24
Peak memory 197412 kb
Host smart-21f91849-f129-4b3d-a620-58cf96454691
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066683165 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.3066683165
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.368440216
Short name T574
Test name
Test status
Simulation time 34609895 ps
CPU time 0.55 seconds
Started Jul 21 05:55:10 PM PDT 24
Finished Jul 21 05:55:11 PM PDT 24
Peak memory 182588 kb
Host smart-b3b63215-883c-4b17-9a30-2987356f7ab9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368440216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.368440216
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.2717384802
Short name T481
Test name
Test status
Simulation time 15699563 ps
CPU time 0.52 seconds
Started Jul 21 05:55:02 PM PDT 24
Finished Jul 21 05:55:03 PM PDT 24
Peak memory 181944 kb
Host smart-cfea3db0-df5a-410d-ac1d-9e4c5310146e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717384802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.2717384802
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.2040050888
Short name T558
Test name
Test status
Simulation time 26384217 ps
CPU time 0.7 seconds
Started Jul 21 05:55:09 PM PDT 24
Finished Jul 21 05:55:11 PM PDT 24
Peak memory 192928 kb
Host smart-1ce5b11b-d072-4c81-be13-5e5a0b995b66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040050888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.2040050888
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.1649327047
Short name T472
Test name
Test status
Simulation time 219695162 ps
CPU time 1.29 seconds
Started Jul 21 05:55:02 PM PDT 24
Finished Jul 21 05:55:03 PM PDT 24
Peak memory 197196 kb
Host smart-41bb86c4-302f-45e7-86fe-689b83a318f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649327047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.1649327047
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3661798412
Short name T107
Test name
Test status
Simulation time 869291639 ps
CPU time 1.79 seconds
Started Jul 21 05:55:04 PM PDT 24
Finished Jul 21 05:55:06 PM PDT 24
Peak memory 195100 kb
Host smart-c887b4c7-32ca-4a10-b64b-1b77690db278
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661798412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.3661798412
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.3681520513
Short name T394
Test name
Test status
Simulation time 37826479981 ps
CPU time 58.81 seconds
Started Jul 21 04:19:16 PM PDT 24
Finished Jul 21 04:20:15 PM PDT 24
Peak memory 183444 kb
Host smart-25907d7e-866a-4ad7-b30f-cc797998d0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681520513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.3681520513
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.86005132
Short name T411
Test name
Test status
Simulation time 20154224255 ps
CPU time 68.97 seconds
Started Jul 21 04:18:06 PM PDT 24
Finished Jul 21 04:19:16 PM PDT 24
Peak memory 182996 kb
Host smart-c05ba902-cdeb-4b4b-8b96-79763a33a2df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86005132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.86005132
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.3703266441
Short name T8
Test name
Test status
Simulation time 38011468 ps
CPU time 0.75 seconds
Started Jul 21 04:19:16 PM PDT 24
Finished Jul 21 04:19:17 PM PDT 24
Peak memory 213388 kb
Host smart-69b0cd9a-4e00-47b2-a15c-b3e4b059a0f1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703266441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.3703266441
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all_with_rand_reset.3216617396
Short name T34
Test name
Test status
Simulation time 47124661779 ps
CPU time 523.05 seconds
Started Jul 21 04:18:08 PM PDT 24
Finished Jul 21 04:26:52 PM PDT 24
Peak memory 197780 kb
Host smart-df895bd6-243c-4abe-914c-28df3b1b36ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216617396 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all_with_rand_reset.3216617396
Directory /workspace/0.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.3851322515
Short name T301
Test name
Test status
Simulation time 290761470651 ps
CPU time 313.94 seconds
Started Jul 21 04:19:34 PM PDT 24
Finished Jul 21 04:24:48 PM PDT 24
Peak memory 183396 kb
Host smart-052e3650-70af-492f-bacf-3b442308574a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851322515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.3851322515
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.777102006
Short name T393
Test name
Test status
Simulation time 75317929737 ps
CPU time 54.27 seconds
Started Jul 21 04:23:26 PM PDT 24
Finished Jul 21 04:24:20 PM PDT 24
Peak memory 183064 kb
Host smart-c3b7f366-b6ef-4efb-9223-0034baf09ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777102006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.777102006
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.1731940987
Short name T182
Test name
Test status
Simulation time 90483859630 ps
CPU time 108.78 seconds
Started Jul 21 04:22:45 PM PDT 24
Finished Jul 21 04:24:36 PM PDT 24
Peak memory 190520 kb
Host smart-ff252cf8-8d6c-4001-b6e5-e25cff1c0e7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731940987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.1731940987
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.2841203288
Short name T275
Test name
Test status
Simulation time 154468556344 ps
CPU time 277.28 seconds
Started Jul 21 04:22:41 PM PDT 24
Finished Jul 21 04:27:19 PM PDT 24
Peak memory 182488 kb
Host smart-0ed20967-596e-4a47-a3b7-0db77c2463ac
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841203288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.2841203288
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.2275272034
Short name T431
Test name
Test status
Simulation time 83311177852 ps
CPU time 32.37 seconds
Started Jul 21 04:22:54 PM PDT 24
Finished Jul 21 04:23:28 PM PDT 24
Peak memory 183244 kb
Host smart-6993fa46-33db-4b39-b01b-57393abbef5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275272034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.2275272034
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/101.rv_timer_random.54639952
Short name T323
Test name
Test status
Simulation time 74810884218 ps
CPU time 67.85 seconds
Started Jul 21 04:22:20 PM PDT 24
Finished Jul 21 04:23:28 PM PDT 24
Peak memory 191636 kb
Host smart-4ab3d52c-7017-407c-a1c9-9433e2e8364d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54639952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.54639952
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.1383026706
Short name T78
Test name
Test status
Simulation time 162111726194 ps
CPU time 90.26 seconds
Started Jul 21 04:22:22 PM PDT 24
Finished Jul 21 04:23:53 PM PDT 24
Peak memory 183456 kb
Host smart-48fe6b1c-3e7c-43e2-8b15-116be748e126
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383026706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.1383026706
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.1165227331
Short name T334
Test name
Test status
Simulation time 345807519008 ps
CPU time 130.25 seconds
Started Jul 21 04:22:26 PM PDT 24
Finished Jul 21 04:24:37 PM PDT 24
Peak memory 191652 kb
Host smart-01b8ef09-78fa-45dd-b005-39eac0e73285
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165227331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.1165227331
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.4265304147
Short name T1
Test name
Test status
Simulation time 127597395871 ps
CPU time 307.76 seconds
Started Jul 21 04:23:33 PM PDT 24
Finished Jul 21 04:28:41 PM PDT 24
Peak memory 191264 kb
Host smart-b1be38c9-7abf-4b60-b9f2-fe5c73d5212b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265304147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.4265304147
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.1681542095
Short name T233
Test name
Test status
Simulation time 230259745609 ps
CPU time 206.24 seconds
Started Jul 21 04:23:45 PM PDT 24
Finished Jul 21 04:27:12 PM PDT 24
Peak memory 190340 kb
Host smart-72adae69-ad84-47c9-9555-39c6238e7a29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681542095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.1681542095
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.3884851372
Short name T162
Test name
Test status
Simulation time 130968987694 ps
CPU time 174.12 seconds
Started Jul 21 04:23:56 PM PDT 24
Finished Jul 21 04:26:50 PM PDT 24
Peak memory 191284 kb
Host smart-fe1eef42-8509-4bd4-89ff-5588cdf5a2dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884851372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.3884851372
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.3972489633
Short name T325
Test name
Test status
Simulation time 195713258034 ps
CPU time 107.88 seconds
Started Jul 21 04:22:35 PM PDT 24
Finished Jul 21 04:24:23 PM PDT 24
Peak memory 183376 kb
Host smart-ffff1424-8760-4014-a5e7-6d08874427b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972489633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.3972489633
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.1897828766
Short name T135
Test name
Test status
Simulation time 794938290174 ps
CPU time 468.38 seconds
Started Jul 21 04:19:01 PM PDT 24
Finished Jul 21 04:26:50 PM PDT 24
Peak memory 183344 kb
Host smart-1a155a3c-684e-461e-b130-5a7a6c820053
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897828766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.1897828766
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.1908206924
Short name T366
Test name
Test status
Simulation time 144083333263 ps
CPU time 60.89 seconds
Started Jul 21 04:19:45 PM PDT 24
Finished Jul 21 04:20:46 PM PDT 24
Peak memory 183400 kb
Host smart-303376e6-b697-49e0-97a8-1f888a6f87c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908206924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.1908206924
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.955893218
Short name T120
Test name
Test status
Simulation time 27297663777 ps
CPU time 181.6 seconds
Started Jul 21 04:22:53 PM PDT 24
Finished Jul 21 04:25:57 PM PDT 24
Peak memory 182524 kb
Host smart-84e71a3e-a123-4e35-9f34-e0d9bf98d65f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955893218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.955893218
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.1196477724
Short name T254
Test name
Test status
Simulation time 53395644381 ps
CPU time 163.75 seconds
Started Jul 21 04:22:51 PM PDT 24
Finished Jul 21 04:25:36 PM PDT 24
Peak memory 183064 kb
Host smart-bcef9233-2742-45da-9f05-c75e9cdcbd44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196477724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.1196477724
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.3483732882
Short name T64
Test name
Test status
Simulation time 227013986238 ps
CPU time 395.97 seconds
Started Jul 21 04:23:00 PM PDT 24
Finished Jul 21 04:29:37 PM PDT 24
Peak memory 195224 kb
Host smart-743f1647-00a1-4bc7-b628-5715b6cc8ed2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483732882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.3483732882
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/112.rv_timer_random.2043065712
Short name T427
Test name
Test status
Simulation time 27815804874 ps
CPU time 53.2 seconds
Started Jul 21 04:22:40 PM PDT 24
Finished Jul 21 04:23:34 PM PDT 24
Peak memory 191588 kb
Host smart-2f2841d8-5a08-48ae-955a-ad7885e05e6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043065712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.2043065712
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.374172062
Short name T257
Test name
Test status
Simulation time 780849804407 ps
CPU time 2245.78 seconds
Started Jul 21 04:22:41 PM PDT 24
Finished Jul 21 05:00:07 PM PDT 24
Peak memory 191612 kb
Host smart-73c8ddaa-d3d6-48ec-8482-d408facb38b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374172062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.374172062
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.335217769
Short name T331
Test name
Test status
Simulation time 252846430310 ps
CPU time 1000.15 seconds
Started Jul 21 04:23:56 PM PDT 24
Finished Jul 21 04:40:37 PM PDT 24
Peak memory 191296 kb
Host smart-f47f2e02-87dd-4d17-b073-9fe11bc1db29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335217769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.335217769
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.3242720777
Short name T289
Test name
Test status
Simulation time 71956844380 ps
CPU time 116.19 seconds
Started Jul 21 04:23:56 PM PDT 24
Finished Jul 21 04:25:53 PM PDT 24
Peak memory 191292 kb
Host smart-7bd3d658-938c-4e90-a406-23056ee33183
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242720777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.3242720777
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.4073673936
Short name T115
Test name
Test status
Simulation time 95415210861 ps
CPU time 87.95 seconds
Started Jul 21 04:24:15 PM PDT 24
Finished Jul 21 04:25:43 PM PDT 24
Peak memory 183104 kb
Host smart-f56bb3a9-0487-4c14-9d63-85607321f1a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073673936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.4073673936
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.3671685101
Short name T111
Test name
Test status
Simulation time 187619461473 ps
CPU time 389.43 seconds
Started Jul 21 04:22:53 PM PDT 24
Finished Jul 21 04:29:24 PM PDT 24
Peak memory 191656 kb
Host smart-333072be-28ec-4ceb-82e1-5d4a8f494c29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671685101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.3671685101
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.738772464
Short name T156
Test name
Test status
Simulation time 144214304329 ps
CPU time 130.53 seconds
Started Jul 21 04:19:01 PM PDT 24
Finished Jul 21 04:21:12 PM PDT 24
Peak memory 183388 kb
Host smart-44e5e639-0e61-4cef-bef7-c6cdce66a81e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738772464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.rv_timer_cfg_update_on_fly.738772464
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.183858688
Short name T430
Test name
Test status
Simulation time 348033838558 ps
CPU time 243.5 seconds
Started Jul 21 04:22:45 PM PDT 24
Finished Jul 21 04:26:50 PM PDT 24
Peak memory 181360 kb
Host smart-4577f0e6-de61-4278-aafa-b25865b05713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183858688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.183858688
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.3867851784
Short name T161
Test name
Test status
Simulation time 129411207280 ps
CPU time 514.13 seconds
Started Jul 21 04:23:01 PM PDT 24
Finished Jul 21 04:31:35 PM PDT 24
Peak memory 191264 kb
Host smart-7ed5afab-58df-4927-bb39-5cc141dbdbb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867851784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.3867851784
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.2392503864
Short name T355
Test name
Test status
Simulation time 46142051351 ps
CPU time 271.05 seconds
Started Jul 21 04:23:01 PM PDT 24
Finished Jul 21 04:27:33 PM PDT 24
Peak memory 183076 kb
Host smart-620c5e24-5169-4db6-9c03-edb8a22cde79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392503864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.2392503864
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.2022126532
Short name T345
Test name
Test status
Simulation time 190033093054 ps
CPU time 328.19 seconds
Started Jul 21 04:23:40 PM PDT 24
Finished Jul 21 04:29:09 PM PDT 24
Peak memory 183072 kb
Host smart-3a20a91d-1547-45f6-b34d-9462ece8940a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022126532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.2022126532
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/120.rv_timer_random.263374105
Short name T174
Test name
Test status
Simulation time 80337674204 ps
CPU time 313.3 seconds
Started Jul 21 04:23:56 PM PDT 24
Finished Jul 21 04:29:10 PM PDT 24
Peak memory 191300 kb
Host smart-dc0bd676-ee3c-4d11-9132-3161c5defca5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263374105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.263374105
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.1782620868
Short name T344
Test name
Test status
Simulation time 17392198092 ps
CPU time 22.97 seconds
Started Jul 21 04:24:33 PM PDT 24
Finished Jul 21 04:24:56 PM PDT 24
Peak memory 191572 kb
Host smart-85dca5d7-f00a-46bf-bc0e-1a44404057b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782620868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.1782620868
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.464702000
Short name T227
Test name
Test status
Simulation time 35049800738 ps
CPU time 28.42 seconds
Started Jul 21 04:22:53 PM PDT 24
Finished Jul 21 04:23:24 PM PDT 24
Peak memory 183572 kb
Host smart-e938f2d4-7f89-4ab1-863a-cbf73c5a268a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464702000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.464702000
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.2925904157
Short name T214
Test name
Test status
Simulation time 150165529029 ps
CPU time 225.38 seconds
Started Jul 21 04:23:01 PM PDT 24
Finished Jul 21 04:26:47 PM PDT 24
Peak memory 191780 kb
Host smart-d8e9b6fe-a7fd-48d8-82d6-e83b0e3ed2d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925904157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.2925904157
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.1617972535
Short name T448
Test name
Test status
Simulation time 30463275531 ps
CPU time 34.43 seconds
Started Jul 21 04:23:00 PM PDT 24
Finished Jul 21 04:23:35 PM PDT 24
Peak memory 183440 kb
Host smart-6bff64ab-4d26-48ec-b179-4323063adca9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617972535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.1617972535
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.3643333235
Short name T165
Test name
Test status
Simulation time 339519899836 ps
CPU time 110.61 seconds
Started Jul 21 04:23:00 PM PDT 24
Finished Jul 21 04:24:51 PM PDT 24
Peak memory 191644 kb
Host smart-376dccb9-71c5-4d87-97b7-fc418974a54b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643333235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.3643333235
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.1318187665
Short name T172
Test name
Test status
Simulation time 71586564511 ps
CPU time 111.37 seconds
Started Jul 21 04:23:00 PM PDT 24
Finished Jul 21 04:24:51 PM PDT 24
Peak memory 191656 kb
Host smart-1b397bcd-f84d-4dd9-9661-a5df1c21d2e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318187665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.1318187665
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.137727081
Short name T281
Test name
Test status
Simulation time 14654526550 ps
CPU time 30.66 seconds
Started Jul 21 04:24:32 PM PDT 24
Finished Jul 21 04:25:03 PM PDT 24
Peak memory 183064 kb
Host smart-382088e0-5aaa-4305-97b1-37b2a802ce09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137727081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.137727081
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.1226339432
Short name T309
Test name
Test status
Simulation time 1106251306041 ps
CPU time 556.64 seconds
Started Jul 21 04:19:39 PM PDT 24
Finished Jul 21 04:28:56 PM PDT 24
Peak memory 183320 kb
Host smart-bfc0ec3e-a209-473f-afc6-dbbd48b9b008
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226339432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.1226339432
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.708245913
Short name T49
Test name
Test status
Simulation time 50923329782 ps
CPU time 69.58 seconds
Started Jul 21 04:23:40 PM PDT 24
Finished Jul 21 04:24:50 PM PDT 24
Peak memory 183088 kb
Host smart-8dc86067-35fc-412b-918f-8a721e655802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708245913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.708245913
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.290729712
Short name T141
Test name
Test status
Simulation time 37061253210 ps
CPU time 34.75 seconds
Started Jul 21 04:23:19 PM PDT 24
Finished Jul 21 04:23:55 PM PDT 24
Peak memory 193812 kb
Host smart-d427976f-f345-421e-998d-d60a87751e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290729712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.290729712
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.2361700944
Short name T332
Test name
Test status
Simulation time 304385105008 ps
CPU time 228.88 seconds
Started Jul 21 04:23:30 PM PDT 24
Finished Jul 21 04:27:19 PM PDT 24
Peak memory 191588 kb
Host smart-cb52cd35-2010-4ab3-ba68-049f93a2e19f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361700944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.2361700944
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.775832324
Short name T154
Test name
Test status
Simulation time 45166634262 ps
CPU time 501.87 seconds
Started Jul 21 04:23:14 PM PDT 24
Finished Jul 21 04:31:37 PM PDT 24
Peak memory 183580 kb
Host smart-d5959523-5f1d-45bd-af77-3965fcc82945
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775832324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.775832324
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.345209307
Short name T143
Test name
Test status
Simulation time 576172071665 ps
CPU time 96.66 seconds
Started Jul 21 04:23:22 PM PDT 24
Finished Jul 21 04:24:59 PM PDT 24
Peak memory 191556 kb
Host smart-951acfb9-5b8e-4238-97f9-8f2cf4ce8195
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345209307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.345209307
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.776978264
Short name T285
Test name
Test status
Simulation time 123824720240 ps
CPU time 1637 seconds
Started Jul 21 04:23:16 PM PDT 24
Finished Jul 21 04:50:34 PM PDT 24
Peak memory 191572 kb
Host smart-ae64e8cb-88af-4dca-aedd-e07ed037899e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776978264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.776978264
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.3762247150
Short name T438
Test name
Test status
Simulation time 43915568426 ps
CPU time 258.21 seconds
Started Jul 21 04:23:22 PM PDT 24
Finished Jul 21 04:27:41 PM PDT 24
Peak memory 183356 kb
Host smart-87801f98-ea78-401d-b774-42c2e1229e7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762247150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.3762247150
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.3293087936
Short name T144
Test name
Test status
Simulation time 29059831848 ps
CPU time 44.97 seconds
Started Jul 21 04:23:17 PM PDT 24
Finished Jul 21 04:24:02 PM PDT 24
Peak memory 183368 kb
Host smart-2ee4b161-fe34-487f-a611-8114728f6b81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293087936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.3293087936
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.4171467114
Short name T164
Test name
Test status
Simulation time 702355430165 ps
CPU time 730.84 seconds
Started Jul 21 04:24:32 PM PDT 24
Finished Jul 21 04:36:43 PM PDT 24
Peak memory 191564 kb
Host smart-bccbc4b8-df05-4763-bf92-d03d9f0054d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171467114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.4171467114
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.2508776348
Short name T270
Test name
Test status
Simulation time 218778197396 ps
CPU time 547.69 seconds
Started Jul 21 04:23:14 PM PDT 24
Finished Jul 21 04:32:22 PM PDT 24
Peak memory 191620 kb
Host smart-421de8f7-2408-4793-bab8-aba53fa00e64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508776348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.2508776348
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.3759496898
Short name T347
Test name
Test status
Simulation time 82913997983 ps
CPU time 70.22 seconds
Started Jul 21 04:24:32 PM PDT 24
Finished Jul 21 04:25:43 PM PDT 24
Peak memory 183372 kb
Host smart-dd05b0b0-b38d-47f7-a443-973931851c92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759496898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.3759496898
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.1146312859
Short name T300
Test name
Test status
Simulation time 148719926892 ps
CPU time 1295.29 seconds
Started Jul 21 04:23:30 PM PDT 24
Finished Jul 21 04:45:05 PM PDT 24
Peak memory 191588 kb
Host smart-320b8dbc-dd56-4cf2-9708-7279d687eb82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146312859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.1146312859
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.3746588116
Short name T419
Test name
Test status
Simulation time 846970496052 ps
CPU time 458.23 seconds
Started Jul 21 04:20:32 PM PDT 24
Finished Jul 21 04:28:10 PM PDT 24
Peak memory 183436 kb
Host smart-b242701f-89f2-4ff1-9617-a3fb7af29b47
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746588116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.3746588116
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.2106237006
Short name T368
Test name
Test status
Simulation time 323647524983 ps
CPU time 181.35 seconds
Started Jul 21 04:22:25 PM PDT 24
Finished Jul 21 04:25:27 PM PDT 24
Peak memory 183492 kb
Host smart-4c4a70fe-bd7e-4b10-b06f-9667bc57c394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106237006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.2106237006
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.287686188
Short name T317
Test name
Test status
Simulation time 91020661878 ps
CPU time 86.04 seconds
Started Jul 21 04:22:48 PM PDT 24
Finished Jul 21 04:24:15 PM PDT 24
Peak memory 180344 kb
Host smart-63a9119d-294a-47a5-aed0-7b1d797cdc8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287686188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.287686188
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.4215218048
Short name T9
Test name
Test status
Simulation time 102134626989 ps
CPU time 206.11 seconds
Started Jul 21 04:21:30 PM PDT 24
Finished Jul 21 04:24:56 PM PDT 24
Peak memory 183504 kb
Host smart-68979631-0e28-44aa-96c7-c2abfb069c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215218048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.4215218048
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/140.rv_timer_random.3439159257
Short name T145
Test name
Test status
Simulation time 190574102191 ps
CPU time 120.78 seconds
Started Jul 21 04:24:23 PM PDT 24
Finished Jul 21 04:26:24 PM PDT 24
Peak memory 190764 kb
Host smart-058a6f82-fa2b-4d6d-b5ec-9dea07bbe6bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439159257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.3439159257
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.1590694064
Short name T360
Test name
Test status
Simulation time 80064346310 ps
CPU time 34.01 seconds
Started Jul 21 04:23:30 PM PDT 24
Finished Jul 21 04:24:04 PM PDT 24
Peak memory 183388 kb
Host smart-d4597d0c-c694-41a3-9a62-2b2bbd5cbfb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590694064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.1590694064
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.2906111978
Short name T153
Test name
Test status
Simulation time 209939729776 ps
CPU time 97.79 seconds
Started Jul 21 04:23:32 PM PDT 24
Finished Jul 21 04:25:10 PM PDT 24
Peak memory 191432 kb
Host smart-29580763-40cb-4d59-867d-e857da54980c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906111978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.2906111978
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.265246819
Short name T341
Test name
Test status
Simulation time 470125637543 ps
CPU time 164.79 seconds
Started Jul 21 04:23:23 PM PDT 24
Finished Jul 21 04:26:08 PM PDT 24
Peak memory 191580 kb
Host smart-9e97483f-6376-454f-908e-696b35b7cb02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265246819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.265246819
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.3103354494
Short name T343
Test name
Test status
Simulation time 97388711229 ps
CPU time 595.81 seconds
Started Jul 21 04:23:28 PM PDT 24
Finished Jul 21 04:33:24 PM PDT 24
Peak memory 193644 kb
Host smart-1372a2fc-6182-4a84-be34-e483aa1006d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103354494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.3103354494
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.3362299510
Short name T357
Test name
Test status
Simulation time 167630210714 ps
CPU time 112.63 seconds
Started Jul 21 04:23:14 PM PDT 24
Finished Jul 21 04:25:07 PM PDT 24
Peak memory 191556 kb
Host smart-9247ef88-fbc4-4f16-b971-cae1061877af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362299510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.3362299510
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.3237744950
Short name T140
Test name
Test status
Simulation time 352210953 ps
CPU time 0.71 seconds
Started Jul 21 04:23:13 PM PDT 24
Finished Jul 21 04:23:14 PM PDT 24
Peak memory 183504 kb
Host smart-e2219700-d852-4acc-8f28-b8f50bc661de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237744950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.3237744950
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.3131996696
Short name T426
Test name
Test status
Simulation time 74352153783 ps
CPU time 331.96 seconds
Started Jul 21 04:23:28 PM PDT 24
Finished Jul 21 04:29:00 PM PDT 24
Peak memory 191592 kb
Host smart-e6f393fb-ca2e-47b6-8294-bc12870d1da4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131996696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.3131996696
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.528793928
Short name T416
Test name
Test status
Simulation time 46004260538 ps
CPU time 80.35 seconds
Started Jul 21 04:23:17 PM PDT 24
Finished Jul 21 04:24:38 PM PDT 24
Peak memory 191580 kb
Host smart-a7f81aad-43ba-4cf2-b399-9485f1a51e83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528793928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.528793928
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.159389238
Short name T236
Test name
Test status
Simulation time 173707093541 ps
CPU time 92.56 seconds
Started Jul 21 04:23:04 PM PDT 24
Finished Jul 21 04:24:37 PM PDT 24
Peak memory 182260 kb
Host smart-3bfe9bc0-b8fb-4bad-8977-80b91fceaf10
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159389238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.rv_timer_cfg_update_on_fly.159389238
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.3995786785
Short name T398
Test name
Test status
Simulation time 654247235533 ps
CPU time 186.91 seconds
Started Jul 21 04:23:56 PM PDT 24
Finished Jul 21 04:27:04 PM PDT 24
Peak memory 183092 kb
Host smart-1f259fdf-4334-4d0f-80fe-bbdf58f64388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995786785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.3995786785
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.3717874182
Short name T225
Test name
Test status
Simulation time 149421030899 ps
CPU time 337.56 seconds
Started Jul 21 04:23:17 PM PDT 24
Finished Jul 21 04:28:55 PM PDT 24
Peak memory 193840 kb
Host smart-8983486a-0b91-440d-99d5-e0479c8b1676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717874182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.3717874182
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/150.rv_timer_random.1751772336
Short name T146
Test name
Test status
Simulation time 325466286232 ps
CPU time 354.74 seconds
Started Jul 21 04:23:30 PM PDT 24
Finished Jul 21 04:29:25 PM PDT 24
Peak memory 194984 kb
Host smart-b84f7f17-63f4-43b2-b70a-e8a4481cf3e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751772336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.1751772336
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.897475628
Short name T44
Test name
Test status
Simulation time 303637658378 ps
CPU time 1525.01 seconds
Started Jul 21 04:23:28 PM PDT 24
Finished Jul 21 04:48:54 PM PDT 24
Peak memory 193644 kb
Host smart-340c9abc-94d5-4110-a954-7ab4e727b200
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897475628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.897475628
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.432694200
Short name T324
Test name
Test status
Simulation time 102501744989 ps
CPU time 419.63 seconds
Started Jul 21 04:23:29 PM PDT 24
Finished Jul 21 04:30:30 PM PDT 24
Peak memory 191588 kb
Host smart-bffe82f0-f798-4d7e-a608-2a219c8045f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432694200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.432694200
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.3266428120
Short name T326
Test name
Test status
Simulation time 51275665552 ps
CPU time 49.05 seconds
Started Jul 21 04:23:25 PM PDT 24
Finished Jul 21 04:24:14 PM PDT 24
Peak memory 183340 kb
Host smart-89fd8ee9-cbe1-409e-bc41-bfc1c93db542
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266428120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.3266428120
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.3534588839
Short name T264
Test name
Test status
Simulation time 548472175518 ps
CPU time 281.21 seconds
Started Jul 21 04:23:29 PM PDT 24
Finished Jul 21 04:28:11 PM PDT 24
Peak memory 191148 kb
Host smart-24835301-0c12-4d9b-a4e6-a16d10508439
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534588839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.3534588839
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.3192273698
Short name T342
Test name
Test status
Simulation time 1057475482551 ps
CPU time 244.29 seconds
Started Jul 21 04:23:28 PM PDT 24
Finished Jul 21 04:27:33 PM PDT 24
Peak memory 191592 kb
Host smart-5bcbb6e6-acd2-480d-9636-ca07f99131fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192273698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.3192273698
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.2628332455
Short name T175
Test name
Test status
Simulation time 302316140551 ps
CPU time 248.82 seconds
Started Jul 21 04:23:29 PM PDT 24
Finished Jul 21 04:27:38 PM PDT 24
Peak memory 195100 kb
Host smart-322be1e5-8880-42ea-b059-88414af1bea7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628332455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.2628332455
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.3328315273
Short name T376
Test name
Test status
Simulation time 235506728286 ps
CPU time 98.77 seconds
Started Jul 21 04:22:39 PM PDT 24
Finished Jul 21 04:24:19 PM PDT 24
Peak memory 181100 kb
Host smart-f1376ab7-8732-41a1-a2b6-6c400c875efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328315273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.3328315273
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.3150212607
Short name T346
Test name
Test status
Simulation time 32529274159 ps
CPU time 15.73 seconds
Started Jul 21 04:22:39 PM PDT 24
Finished Jul 21 04:22:56 PM PDT 24
Peak memory 181264 kb
Host smart-979826d6-e4ec-498e-bc3f-2ee9724ec9a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150212607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.3150212607
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.205694668
Short name T274
Test name
Test status
Simulation time 7008069686 ps
CPU time 11.51 seconds
Started Jul 21 04:19:26 PM PDT 24
Finished Jul 21 04:19:38 PM PDT 24
Peak memory 183372 kb
Host smart-0d15b2ab-c617-4a3e-81ec-e8015bd57da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205694668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.205694668
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.3779338604
Short name T251
Test name
Test status
Simulation time 232747422272 ps
CPU time 150.58 seconds
Started Jul 21 04:23:29 PM PDT 24
Finished Jul 21 04:26:00 PM PDT 24
Peak memory 191552 kb
Host smart-f8df4167-6c59-467a-9477-63c5740fb544
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779338604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.3779338604
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.885922192
Short name T238
Test name
Test status
Simulation time 745355036408 ps
CPU time 442.57 seconds
Started Jul 21 04:23:32 PM PDT 24
Finished Jul 21 04:30:55 PM PDT 24
Peak memory 191468 kb
Host smart-cd199475-155d-4300-b1d8-8692c7f21846
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885922192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.885922192
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.3596988559
Short name T349
Test name
Test status
Simulation time 439261609225 ps
CPU time 641.64 seconds
Started Jul 21 04:23:30 PM PDT 24
Finished Jul 21 04:34:12 PM PDT 24
Peak memory 191588 kb
Host smart-5668cc6b-5b12-4e42-836a-3a9291234d24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596988559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.3596988559
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.1708224981
Short name T386
Test name
Test status
Simulation time 43519717328 ps
CPU time 71.77 seconds
Started Jul 21 04:23:29 PM PDT 24
Finished Jul 21 04:24:41 PM PDT 24
Peak memory 183056 kb
Host smart-b05d69fa-50f3-4187-a5b8-f1bb779efa82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708224981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.1708224981
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.135277518
Short name T351
Test name
Test status
Simulation time 106951707259 ps
CPU time 917.75 seconds
Started Jul 21 04:23:22 PM PDT 24
Finished Jul 21 04:38:40 PM PDT 24
Peak memory 183336 kb
Host smart-74e96485-59d8-44f0-af89-62c55fa68ef3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135277518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.135277518
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.3665245057
Short name T314
Test name
Test status
Simulation time 107833544807 ps
CPU time 41.94 seconds
Started Jul 21 04:23:40 PM PDT 24
Finished Jul 21 04:24:23 PM PDT 24
Peak memory 183312 kb
Host smart-112aa81d-1262-4c6c-821c-8962787f9b08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665245057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.3665245057
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.175935322
Short name T108
Test name
Test status
Simulation time 103010763305 ps
CPU time 209.72 seconds
Started Jul 21 04:23:40 PM PDT 24
Finished Jul 21 04:27:10 PM PDT 24
Peak memory 195152 kb
Host smart-25519d90-3396-4000-b607-ff16be9b8be2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175935322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.175935322
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.1439669904
Short name T61
Test name
Test status
Simulation time 270552811474 ps
CPU time 1555.38 seconds
Started Jul 21 04:24:47 PM PDT 24
Finished Jul 21 04:50:43 PM PDT 24
Peak memory 183036 kb
Host smart-eb399ee1-c2a6-4729-8818-0a701d502ad0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439669904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.1439669904
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.136029904
Short name T330
Test name
Test status
Simulation time 100833277929 ps
CPU time 81.53 seconds
Started Jul 21 04:23:34 PM PDT 24
Finished Jul 21 04:24:56 PM PDT 24
Peak memory 183356 kb
Host smart-77e9f288-b306-46c2-b0c7-eeff0b6215fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136029904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.136029904
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.3989439681
Short name T408
Test name
Test status
Simulation time 953090133265 ps
CPU time 399.49 seconds
Started Jul 21 04:19:15 PM PDT 24
Finished Jul 21 04:25:55 PM PDT 24
Peak memory 183380 kb
Host smart-a983e6cc-720e-4865-8801-60f3c3009ddf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989439681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.3989439681
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.341294823
Short name T381
Test name
Test status
Simulation time 578565988109 ps
CPU time 239.15 seconds
Started Jul 21 04:23:24 PM PDT 24
Finished Jul 21 04:27:24 PM PDT 24
Peak memory 182800 kb
Host smart-126f8399-979d-4ec4-b98f-d401d5900d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341294823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.341294823
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.4081714939
Short name T373
Test name
Test status
Simulation time 17492511 ps
CPU time 0.52 seconds
Started Jul 21 04:23:24 PM PDT 24
Finished Jul 21 04:23:25 PM PDT 24
Peak memory 182512 kb
Host smart-e3aba3db-3135-4d8f-a790-c732e650ce4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081714939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.4081714939
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/171.rv_timer_random.2264177495
Short name T284
Test name
Test status
Simulation time 495872235894 ps
CPU time 170.16 seconds
Started Jul 21 04:24:47 PM PDT 24
Finished Jul 21 04:27:38 PM PDT 24
Peak memory 191268 kb
Host smart-ad1704f6-1997-4a44-877e-3490a29a3f7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264177495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.2264177495
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.2763548333
Short name T299
Test name
Test status
Simulation time 59899031799 ps
CPU time 111.78 seconds
Started Jul 21 04:24:47 PM PDT 24
Finished Jul 21 04:26:39 PM PDT 24
Peak memory 191264 kb
Host smart-4949168d-ea7d-4f93-a1be-2122bff7c72f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763548333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.2763548333
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.519103539
Short name T205
Test name
Test status
Simulation time 69154727641 ps
CPU time 356.41 seconds
Started Jul 21 04:24:46 PM PDT 24
Finished Jul 21 04:30:43 PM PDT 24
Peak memory 191264 kb
Host smart-75c5f34a-b93a-4ed4-ac31-7b540ff815a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519103539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.519103539
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.4126552651
Short name T121
Test name
Test status
Simulation time 68898537830 ps
CPU time 1362.34 seconds
Started Jul 21 04:23:39 PM PDT 24
Finished Jul 21 04:46:22 PM PDT 24
Peak memory 191512 kb
Host smart-b7dafa01-bb26-4d2b-8e5e-9566c306b8bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126552651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.4126552651
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.498357310
Short name T435
Test name
Test status
Simulation time 125020169131 ps
CPU time 80.44 seconds
Started Jul 21 04:23:35 PM PDT 24
Finished Jul 21 04:24:55 PM PDT 24
Peak memory 183348 kb
Host smart-bb62f184-10e5-4306-b17f-c4342a27bb1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498357310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.498357310
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.674821877
Short name T429
Test name
Test status
Simulation time 2704925806 ps
CPU time 1.83 seconds
Started Jul 21 04:22:52 PM PDT 24
Finished Jul 21 04:22:55 PM PDT 24
Peak memory 182696 kb
Host smart-de00fec8-0456-4448-b5d5-38f1457e9a6a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674821877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.rv_timer_cfg_update_on_fly.674821877
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.765026438
Short name T389
Test name
Test status
Simulation time 31713227822 ps
CPU time 50.14 seconds
Started Jul 21 04:23:07 PM PDT 24
Finished Jul 21 04:23:58 PM PDT 24
Peak memory 183276 kb
Host smart-eae2737c-9b0e-4d7c-a63a-a5d9a1ed5f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765026438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.765026438
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.3425778399
Short name T276
Test name
Test status
Simulation time 569060683773 ps
CPU time 366.49 seconds
Started Jul 21 04:20:11 PM PDT 24
Finished Jul 21 04:26:18 PM PDT 24
Peak memory 191532 kb
Host smart-df81112c-8b1c-4f61-a69b-f26aa5fca5de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425778399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.3425778399
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.3874645625
Short name T38
Test name
Test status
Simulation time 214066787593 ps
CPU time 1484.31 seconds
Started Jul 21 04:19:39 PM PDT 24
Finished Jul 21 04:44:24 PM PDT 24
Peak memory 208308 kb
Host smart-f53ead89-d985-4836-ae57-0246c67dfc5f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874645625 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all_with_rand_reset.3874645625
Directory /workspace/18.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/181.rv_timer_random.434689609
Short name T147
Test name
Test status
Simulation time 53506491208 ps
CPU time 90.19 seconds
Started Jul 21 04:23:39 PM PDT 24
Finished Jul 21 04:25:09 PM PDT 24
Peak memory 191508 kb
Host smart-a5433f5c-48ac-4f33-9ca1-4954a21a7cc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434689609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.434689609
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.4235854205
Short name T425
Test name
Test status
Simulation time 578258601161 ps
CPU time 336.19 seconds
Started Jul 21 04:23:28 PM PDT 24
Finished Jul 21 04:29:05 PM PDT 24
Peak memory 192668 kb
Host smart-c3f3de83-4089-4fd3-a1ed-434268baf23c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235854205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.4235854205
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.1563068130
Short name T192
Test name
Test status
Simulation time 493618674237 ps
CPU time 332.08 seconds
Started Jul 21 04:23:40 PM PDT 24
Finished Jul 21 04:29:12 PM PDT 24
Peak memory 191504 kb
Host smart-aa19924a-f163-4120-b127-caa557e87555
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563068130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.1563068130
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.3611333469
Short name T363
Test name
Test status
Simulation time 230332626948 ps
CPU time 131.48 seconds
Started Jul 21 04:24:47 PM PDT 24
Finished Jul 21 04:26:59 PM PDT 24
Peak memory 191260 kb
Host smart-0bdd0bd7-a0b2-404a-8672-fce9f9fc7359
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611333469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.3611333469
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.3124602529
Short name T76
Test name
Test status
Simulation time 225884068815 ps
CPU time 301.79 seconds
Started Jul 21 04:23:32 PM PDT 24
Finished Jul 21 04:28:34 PM PDT 24
Peak memory 183344 kb
Host smart-7b618a9d-efca-464a-bb8d-59ec706ed0c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124602529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.3124602529
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.490543033
Short name T280
Test name
Test status
Simulation time 541840268858 ps
CPU time 283.55 seconds
Started Jul 21 04:23:30 PM PDT 24
Finished Jul 21 04:28:15 PM PDT 24
Peak memory 191516 kb
Host smart-3d0b0c76-9685-4af6-be4d-b38566c24831
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490543033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.490543033
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.1687907925
Short name T139
Test name
Test status
Simulation time 148742491928 ps
CPU time 135.1 seconds
Started Jul 21 04:23:39 PM PDT 24
Finished Jul 21 04:25:55 PM PDT 24
Peak memory 191516 kb
Host smart-e121551a-16e6-440b-a605-3b0e01b9817c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687907925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.1687907925
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.141691277
Short name T436
Test name
Test status
Simulation time 30880804256 ps
CPU time 48.87 seconds
Started Jul 21 04:23:30 PM PDT 24
Finished Jul 21 04:24:19 PM PDT 24
Peak memory 183316 kb
Host smart-9f08b3d5-ba25-4d49-9237-726b3d408c43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141691277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.141691277
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.3453860035
Short name T219
Test name
Test status
Simulation time 735381088612 ps
CPU time 1180.44 seconds
Started Jul 21 04:23:06 PM PDT 24
Finished Jul 21 04:42:48 PM PDT 24
Peak memory 182476 kb
Host smart-262e5e28-11e2-4ffb-bd0a-45f316be0cd1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453860035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.3453860035
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.1554045729
Short name T391
Test name
Test status
Simulation time 8676209250 ps
CPU time 12.27 seconds
Started Jul 21 04:19:32 PM PDT 24
Finished Jul 21 04:19:45 PM PDT 24
Peak memory 182984 kb
Host smart-7737ecda-9c1e-4fb9-a928-b23ee03dd31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554045729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.1554045729
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.399365033
Short name T377
Test name
Test status
Simulation time 211607779 ps
CPU time 0.7 seconds
Started Jul 21 04:19:56 PM PDT 24
Finished Jul 21 04:19:57 PM PDT 24
Peak memory 191940 kb
Host smart-10fe9cca-a4c9-4743-82b6-6446e9845be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399365033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.399365033
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.99111138
Short name T56
Test name
Test status
Simulation time 1130191782200 ps
CPU time 1051.05 seconds
Started Jul 21 04:19:50 PM PDT 24
Finished Jul 21 04:37:21 PM PDT 24
Peak memory 191628 kb
Host smart-caa9c058-2d28-4800-bed5-2ad25aee1e8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99111138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all.99111138
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all_with_rand_reset.3454998596
Short name T37
Test name
Test status
Simulation time 13543156325 ps
CPU time 109.07 seconds
Started Jul 21 04:23:06 PM PDT 24
Finished Jul 21 04:24:56 PM PDT 24
Peak memory 197656 kb
Host smart-273be153-527e-41da-adb5-acb02832765c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454998596 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all_with_rand_reset.3454998596
Directory /workspace/19.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.254860973
Short name T449
Test name
Test status
Simulation time 92951768704 ps
CPU time 38.15 seconds
Started Jul 21 04:23:34 PM PDT 24
Finished Jul 21 04:24:13 PM PDT 24
Peak memory 183356 kb
Host smart-2ea3bc0d-7324-4cc8-b114-e18cd1af3e7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254860973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.254860973
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.478821125
Short name T263
Test name
Test status
Simulation time 152420187907 ps
CPU time 267.27 seconds
Started Jul 21 04:23:30 PM PDT 24
Finished Jul 21 04:27:58 PM PDT 24
Peak memory 191516 kb
Host smart-b762a892-e5ac-42f9-996c-a4bc108ff996
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478821125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.478821125
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.3739815047
Short name T226
Test name
Test status
Simulation time 9646707948 ps
CPU time 15.36 seconds
Started Jul 21 04:24:46 PM PDT 24
Finished Jul 21 04:25:01 PM PDT 24
Peak memory 183060 kb
Host smart-3df1a888-6852-423f-bd27-a1cfc959832e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739815047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.3739815047
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.541521110
Short name T421
Test name
Test status
Simulation time 72915103802 ps
CPU time 265.16 seconds
Started Jul 21 04:24:46 PM PDT 24
Finished Jul 21 04:29:11 PM PDT 24
Peak memory 191264 kb
Host smart-c51c2ea2-91c2-444f-b4a3-8c039bacfb4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541521110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.541521110
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.2471946906
Short name T269
Test name
Test status
Simulation time 610602356873 ps
CPU time 728.85 seconds
Started Jul 21 04:23:42 PM PDT 24
Finished Jul 21 04:35:51 PM PDT 24
Peak memory 191500 kb
Host smart-a687db22-ce92-4069-bd26-bafb9f5d7a8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471946906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.2471946906
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.2936180006
Short name T198
Test name
Test status
Simulation time 334694753724 ps
CPU time 261.69 seconds
Started Jul 21 04:23:38 PM PDT 24
Finished Jul 21 04:28:00 PM PDT 24
Peak memory 191540 kb
Host smart-64c402df-27aa-4623-a69a-1cdc1d628b58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936180006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.2936180006
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.4121816474
Short name T194
Test name
Test status
Simulation time 193838043402 ps
CPU time 354.49 seconds
Started Jul 21 04:23:39 PM PDT 24
Finished Jul 21 04:29:34 PM PDT 24
Peak memory 191540 kb
Host smart-6ccccf0a-6331-4265-86cd-ae95eb9d5649
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121816474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.4121816474
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.1014751225
Short name T59
Test name
Test status
Simulation time 156242983362 ps
CPU time 269.57 seconds
Started Jul 21 04:22:45 PM PDT 24
Finished Jul 21 04:27:16 PM PDT 24
Peak memory 181652 kb
Host smart-f16e2baf-7953-4f01-b4ae-b76117547bb2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014751225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.1014751225
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.1976610737
Short name T10
Test name
Test status
Simulation time 242755849333 ps
CPU time 102.35 seconds
Started Jul 21 04:19:35 PM PDT 24
Finished Jul 21 04:21:17 PM PDT 24
Peak memory 183348 kb
Host smart-b47472f1-d238-4810-910e-baf6b2d1619d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976610737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.1976610737
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.3041146352
Short name T239
Test name
Test status
Simulation time 146080060658 ps
CPU time 1294.9 seconds
Started Jul 21 04:22:45 PM PDT 24
Finished Jul 21 04:44:22 PM PDT 24
Peak memory 189884 kb
Host smart-dcc4f4e7-b630-4eba-90cb-51d07a652adf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041146352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.3041146352
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.1380639793
Short name T338
Test name
Test status
Simulation time 373137196730 ps
CPU time 87.34 seconds
Started Jul 21 04:23:34 PM PDT 24
Finished Jul 21 04:25:02 PM PDT 24
Peak memory 183192 kb
Host smart-f28cf6dd-6061-4f71-9989-d1c2d8897e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380639793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.1380639793
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.3293492812
Short name T16
Test name
Test status
Simulation time 56803251 ps
CPU time 0.84 seconds
Started Jul 21 04:23:31 PM PDT 24
Finished Jul 21 04:23:33 PM PDT 24
Peak memory 213540 kb
Host smart-62610c7e-efce-40b8-b1c7-f0162793a42e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293492812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.3293492812
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.1882273892
Short name T5
Test name
Test status
Simulation time 241179199997 ps
CPU time 109.51 seconds
Started Jul 21 04:22:54 PM PDT 24
Finished Jul 21 04:24:45 PM PDT 24
Peak memory 183260 kb
Host smart-1d72625d-4df6-4d04-8bee-ddc12b1396ee
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882273892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.1882273892
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.1212643912
Short name T404
Test name
Test status
Simulation time 447150693619 ps
CPU time 188 seconds
Started Jul 21 04:22:52 PM PDT 24
Finished Jul 21 04:26:01 PM PDT 24
Peak memory 182968 kb
Host smart-c22103dd-7073-48fa-8700-8efc5476a51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212643912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.1212643912
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.2692507979
Short name T210
Test name
Test status
Simulation time 288364417482 ps
CPU time 457.61 seconds
Started Jul 21 04:23:11 PM PDT 24
Finished Jul 21 04:30:50 PM PDT 24
Peak memory 190724 kb
Host smart-0490d5ae-bbcc-4b56-9d4b-741538af8955
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692507979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.2692507979
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.878262660
Short name T218
Test name
Test status
Simulation time 215750203590 ps
CPU time 139.38 seconds
Started Jul 21 04:23:24 PM PDT 24
Finished Jul 21 04:25:44 PM PDT 24
Peak memory 183068 kb
Host smart-9441639a-b364-488e-a0d5-9d10db3889e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878262660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.878262660
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all_with_rand_reset.4237765377
Short name T13
Test name
Test status
Simulation time 147355668846 ps
CPU time 1112.21 seconds
Started Jul 21 04:20:16 PM PDT 24
Finished Jul 21 04:38:49 PM PDT 24
Peak memory 213572 kb
Host smart-274f1207-d973-40a1-9ddb-e351519fd8ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237765377 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all_with_rand_reset.4237765377
Directory /workspace/20.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.3927101373
Short name T244
Test name
Test status
Simulation time 38683051173 ps
CPU time 18.79 seconds
Started Jul 21 04:20:56 PM PDT 24
Finished Jul 21 04:21:15 PM PDT 24
Peak memory 183408 kb
Host smart-782fd419-c540-4427-8a76-a59453d34c6b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927101373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.3927101373
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.1007473725
Short name T4
Test name
Test status
Simulation time 445505920535 ps
CPU time 337.56 seconds
Started Jul 21 04:19:39 PM PDT 24
Finished Jul 21 04:25:17 PM PDT 24
Peak memory 183396 kb
Host smart-b47a18c0-0c05-4f1b-9556-71e60deab38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007473725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.1007473725
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.3794749030
Short name T261
Test name
Test status
Simulation time 284219331430 ps
CPU time 454.92 seconds
Started Jul 21 04:20:15 PM PDT 24
Finished Jul 21 04:27:50 PM PDT 24
Peak memory 191524 kb
Host smart-6753860e-8224-434f-b2d7-03e6abf4cdd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794749030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.3794749030
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.2563711645
Short name T250
Test name
Test status
Simulation time 571375937623 ps
CPU time 841.54 seconds
Started Jul 21 04:23:06 PM PDT 24
Finished Jul 21 04:37:08 PM PDT 24
Peak memory 183172 kb
Host smart-0689a2e5-5134-4f15-8aca-26d805367989
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563711645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.2563711645
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.1832825152
Short name T57
Test name
Test status
Simulation time 293022069589 ps
CPU time 119.19 seconds
Started Jul 21 04:23:05 PM PDT 24
Finished Jul 21 04:25:05 PM PDT 24
Peak memory 183288 kb
Host smart-a1dffa75-ed80-4663-961f-f760b2ba4703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832825152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.1832825152
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.576464509
Short name T446
Test name
Test status
Simulation time 317658695112 ps
CPU time 1737.75 seconds
Started Jul 21 04:22:57 PM PDT 24
Finished Jul 21 04:51:56 PM PDT 24
Peak memory 183312 kb
Host smart-4a20eb31-ff87-4e81-89bf-52287944fd47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576464509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.576464509
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.3002503064
Short name T41
Test name
Test status
Simulation time 414448869136 ps
CPU time 75.07 seconds
Started Jul 21 04:22:01 PM PDT 24
Finished Jul 21 04:23:16 PM PDT 24
Peak memory 183388 kb
Host smart-9b711b8d-595d-4a24-8fe7-2c23dbcc38d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002503064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.3002503064
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all_with_rand_reset.2519757787
Short name T11
Test name
Test status
Simulation time 16066291107 ps
CPU time 119.92 seconds
Started Jul 21 04:20:15 PM PDT 24
Finished Jul 21 04:22:15 PM PDT 24
Peak memory 198060 kb
Host smart-747daf45-15d4-482f-8682-354d1671ed9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519757787 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all_with_rand_reset.2519757787
Directory /workspace/22.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.192051370
Short name T293
Test name
Test status
Simulation time 49655742790 ps
CPU time 23.37 seconds
Started Jul 21 04:19:49 PM PDT 24
Finished Jul 21 04:20:13 PM PDT 24
Peak memory 183432 kb
Host smart-04f9da1a-539e-4746-bb46-f89a4d928ca5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192051370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.rv_timer_cfg_update_on_fly.192051370
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.2395106700
Short name T380
Test name
Test status
Simulation time 197113597784 ps
CPU time 140.52 seconds
Started Jul 21 04:23:05 PM PDT 24
Finished Jul 21 04:25:26 PM PDT 24
Peak memory 183280 kb
Host smart-73bc6485-d48f-4d83-bc13-c1a3fc700cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395106700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.2395106700
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.3918984244
Short name T310
Test name
Test status
Simulation time 36028949239 ps
CPU time 51.75 seconds
Started Jul 21 04:23:09 PM PDT 24
Finished Jul 21 04:24:01 PM PDT 24
Peak memory 194992 kb
Host smart-2d4bf34d-d876-44ce-825f-cff21f77449b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918984244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.3918984244
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.294261628
Short name T75
Test name
Test status
Simulation time 81997531 ps
CPU time 0.57 seconds
Started Jul 21 04:23:24 PM PDT 24
Finished Jul 21 04:23:25 PM PDT 24
Peak memory 183136 kb
Host smart-82f6330a-22fa-4402-ab1c-05d10861f452
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294261628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all.
294261628
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.687823606
Short name T282
Test name
Test status
Simulation time 636308205728 ps
CPU time 291.81 seconds
Started Jul 21 04:23:23 PM PDT 24
Finished Jul 21 04:28:15 PM PDT 24
Peak memory 183276 kb
Host smart-aa38acae-e056-4f3c-8f19-a1d8b254f665
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687823606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.rv_timer_cfg_update_on_fly.687823606
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.808999498
Short name T407
Test name
Test status
Simulation time 111693389507 ps
CPU time 78.89 seconds
Started Jul 21 04:19:42 PM PDT 24
Finished Jul 21 04:21:01 PM PDT 24
Peak memory 183356 kb
Host smart-b74aea11-d7d4-4ecd-9981-bfea7a9fdb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808999498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.808999498
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.1466555683
Short name T217
Test name
Test status
Simulation time 60635603912 ps
CPU time 504.16 seconds
Started Jul 21 04:23:08 PM PDT 24
Finished Jul 21 04:31:33 PM PDT 24
Peak memory 191512 kb
Host smart-993d714d-ecd2-483f-af0f-131c81100259
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466555683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.1466555683
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.2630838639
Short name T142
Test name
Test status
Simulation time 87565910463 ps
CPU time 462.15 seconds
Started Jul 21 04:23:32 PM PDT 24
Finished Jul 21 04:31:15 PM PDT 24
Peak memory 191276 kb
Host smart-c8bac09b-3a3f-4533-aecd-a844f00561f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630838639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.2630838639
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.1039654680
Short name T356
Test name
Test status
Simulation time 275864853993 ps
CPU time 106.12 seconds
Started Jul 21 04:19:49 PM PDT 24
Finished Jul 21 04:21:36 PM PDT 24
Peak memory 194732 kb
Host smart-4260d930-981f-4da6-9ae4-30d60574dba9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039654680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.1039654680
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.2784754698
Short name T279
Test name
Test status
Simulation time 510196218531 ps
CPU time 258.74 seconds
Started Jul 21 04:23:11 PM PDT 24
Finished Jul 21 04:27:30 PM PDT 24
Peak memory 181836 kb
Host smart-61f3be19-9076-41b7-9d3e-9f9d798a680b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784754698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.2784754698
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.16975728
Short name T60
Test name
Test status
Simulation time 118893502211 ps
CPU time 186.83 seconds
Started Jul 21 04:23:20 PM PDT 24
Finished Jul 21 04:26:27 PM PDT 24
Peak memory 183096 kb
Host smart-edcfe117-5772-46ed-af4a-a4ccc90f9b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16975728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.16975728
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.2972215894
Short name T117
Test name
Test status
Simulation time 325198930081 ps
CPU time 155.68 seconds
Started Jul 21 04:19:41 PM PDT 24
Finished Jul 21 04:22:17 PM PDT 24
Peak memory 191612 kb
Host smart-c6c5ba43-4bd5-4981-b3c2-8601e7cafbba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972215894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.2972215894
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.1671377141
Short name T390
Test name
Test status
Simulation time 1473182326 ps
CPU time 1.94 seconds
Started Jul 21 04:22:48 PM PDT 24
Finished Jul 21 04:22:51 PM PDT 24
Peak memory 192088 kb
Host smart-b275edc4-6940-4eab-8a59-3c53b70073ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671377141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.1671377141
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.2378271893
Short name T388
Test name
Test status
Simulation time 38231504433 ps
CPU time 31.9 seconds
Started Jul 21 04:19:52 PM PDT 24
Finished Jul 21 04:20:24 PM PDT 24
Peak memory 183388 kb
Host smart-48a3a4e4-a581-459b-8837-c00d5d313f72
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378271893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.2378271893
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.856186646
Short name T383
Test name
Test status
Simulation time 921599622743 ps
CPU time 394.6 seconds
Started Jul 21 04:22:12 PM PDT 24
Finished Jul 21 04:28:47 PM PDT 24
Peak memory 183436 kb
Host smart-904d4078-1814-4bf1-9a6d-fbefe98b954d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856186646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.856186646
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.3662039229
Short name T303
Test name
Test status
Simulation time 239755712214 ps
CPU time 1730.73 seconds
Started Jul 21 04:20:32 PM PDT 24
Finished Jul 21 04:49:23 PM PDT 24
Peak memory 191632 kb
Host smart-652eb348-912b-4548-81b1-509d27cc4198
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662039229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.3662039229
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.3895222561
Short name T74
Test name
Test status
Simulation time 224130727754 ps
CPU time 240.39 seconds
Started Jul 21 04:19:48 PM PDT 24
Finished Jul 21 04:23:49 PM PDT 24
Peak memory 195012 kb
Host smart-fc480bdd-5a3e-4b91-a6b6-31d6ed394151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895222561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.3895222561
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.1369001466
Short name T418
Test name
Test status
Simulation time 255909489202 ps
CPU time 352.89 seconds
Started Jul 21 04:23:37 PM PDT 24
Finished Jul 21 04:29:30 PM PDT 24
Peak memory 195132 kb
Host smart-572b5e83-3042-4f93-8d53-d6759488acf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369001466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.1369001466
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.1206020377
Short name T246
Test name
Test status
Simulation time 10591802857 ps
CPU time 5.75 seconds
Started Jul 21 04:22:54 PM PDT 24
Finished Jul 21 04:23:02 PM PDT 24
Peak memory 182148 kb
Host smart-1e008761-6b34-45b2-96d7-d895eca48cc6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206020377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.1206020377
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.662052215
Short name T382
Test name
Test status
Simulation time 47741301725 ps
CPU time 65.31 seconds
Started Jul 21 04:22:45 PM PDT 24
Finished Jul 21 04:23:52 PM PDT 24
Peak memory 181572 kb
Host smart-3eaf0d58-2180-4b59-a0bc-65fc9e6bb947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662052215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.662052215
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.3021938555
Short name T329
Test name
Test status
Simulation time 96441009433 ps
CPU time 349.16 seconds
Started Jul 21 04:20:30 PM PDT 24
Finished Jul 21 04:26:19 PM PDT 24
Peak memory 191944 kb
Host smart-7d858ea9-025d-40be-a943-72a3d056a0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021938555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.3021938555
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.3795768824
Short name T441
Test name
Test status
Simulation time 924446754770 ps
CPU time 352.34 seconds
Started Jul 21 04:23:19 PM PDT 24
Finished Jul 21 04:29:12 PM PDT 24
Peak memory 195748 kb
Host smart-b31f4199-0f6f-4a15-8a17-f935d3111fcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795768824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.3795768824
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.1275902361
Short name T372
Test name
Test status
Simulation time 62608378114 ps
CPU time 79.97 seconds
Started Jul 21 04:20:15 PM PDT 24
Finished Jul 21 04:21:35 PM PDT 24
Peak memory 183276 kb
Host smart-50fe748b-664e-4f00-a4ca-9655659daa74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275902361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.1275902361
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.1879549010
Short name T265
Test name
Test status
Simulation time 284743733590 ps
CPU time 198.16 seconds
Started Jul 21 04:21:01 PM PDT 24
Finished Jul 21 04:24:19 PM PDT 24
Peak memory 191632 kb
Host smart-8d74741a-c5f4-4fa5-9624-f564ad574555
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879549010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.1879549010
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.2219424901
Short name T131
Test name
Test status
Simulation time 85715251968 ps
CPU time 549.2 seconds
Started Jul 21 04:23:15 PM PDT 24
Finished Jul 21 04:32:25 PM PDT 24
Peak memory 190772 kb
Host smart-c607521a-4164-497c-af61-f05221456072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219424901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.2219424901
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.1112927574
Short name T231
Test name
Test status
Simulation time 1449620671469 ps
CPU time 1070.71 seconds
Started Jul 21 04:22:39 PM PDT 24
Finished Jul 21 04:40:31 PM PDT 24
Peak memory 189776 kb
Host smart-60d44d7a-bd24-494f-b818-7ae6d3533d09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112927574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.1112927574
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all_with_rand_reset.3679443435
Short name T39
Test name
Test status
Simulation time 19231333594 ps
CPU time 201.07 seconds
Started Jul 21 04:19:59 PM PDT 24
Finished Jul 21 04:23:20 PM PDT 24
Peak memory 206144 kb
Host smart-16ddc071-75db-4e0b-ad82-d48f5838d820
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679443435 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all_with_rand_reset.3679443435
Directory /workspace/28.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.443167512
Short name T444
Test name
Test status
Simulation time 217128037004 ps
CPU time 170.68 seconds
Started Jul 21 04:23:25 PM PDT 24
Finished Jul 21 04:26:17 PM PDT 24
Peak memory 183072 kb
Host smart-5e66c8b9-4e23-4be7-98da-c1c14f7f7863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443167512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.443167512
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.3521607477
Short name T442
Test name
Test status
Simulation time 45032952899 ps
CPU time 237.21 seconds
Started Jul 21 04:22:39 PM PDT 24
Finished Jul 21 04:26:37 PM PDT 24
Peak memory 183024 kb
Host smart-a2f71fef-ef04-4bd8-871e-f6e8cd210844
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521607477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.3521607477
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.1225343628
Short name T348
Test name
Test status
Simulation time 100078695364 ps
CPU time 305.93 seconds
Started Jul 21 04:22:51 PM PDT 24
Finished Jul 21 04:27:58 PM PDT 24
Peak memory 183320 kb
Host smart-82d8bffa-4b48-4c7f-8b4e-997dcc0d788d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225343628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.1225343628
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.791697786
Short name T440
Test name
Test status
Simulation time 3704397986870 ps
CPU time 634.71 seconds
Started Jul 21 04:22:49 PM PDT 24
Finished Jul 21 04:33:24 PM PDT 24
Peak memory 194764 kb
Host smart-539ef959-c2d0-45cf-bd21-d46c9b21ca86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791697786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all.
791697786
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.4221638225
Short name T119
Test name
Test status
Simulation time 91056473895 ps
CPU time 163.3 seconds
Started Jul 21 04:22:58 PM PDT 24
Finished Jul 21 04:25:42 PM PDT 24
Peak memory 182888 kb
Host smart-53db5d3b-872f-4661-9ff4-2580414ab96f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221638225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.4221638225
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.1840057485
Short name T42
Test name
Test status
Simulation time 119627589090 ps
CPU time 96.03 seconds
Started Jul 21 04:22:50 PM PDT 24
Finished Jul 21 04:24:27 PM PDT 24
Peak memory 183320 kb
Host smart-87a55f32-5a30-4a7b-b2f6-1f66bcbb365b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840057485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.1840057485
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.2727571678
Short name T302
Test name
Test status
Simulation time 230675017013 ps
CPU time 228.74 seconds
Started Jul 21 04:21:09 PM PDT 24
Finished Jul 21 04:24:58 PM PDT 24
Peak memory 193536 kb
Host smart-4e7fe481-09e5-49ae-955b-dd49ce54a88d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727571678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.2727571678
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.1684603870
Short name T409
Test name
Test status
Simulation time 101012543726 ps
CPU time 50.26 seconds
Started Jul 21 04:19:35 PM PDT 24
Finished Jul 21 04:20:25 PM PDT 24
Peak memory 191580 kb
Host smart-0b16b083-0496-4e07-8f6e-4f11e13a189b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684603870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.1684603870
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.10286580
Short name T15
Test name
Test status
Simulation time 161047802 ps
CPU time 0.89 seconds
Started Jul 21 04:20:05 PM PDT 24
Finished Jul 21 04:20:06 PM PDT 24
Peak memory 214768 kb
Host smart-57092de1-ca83-4f4f-867c-0d68a486d79a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10286580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.10286580
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.2460980221
Short name T362
Test name
Test status
Simulation time 8052397696 ps
CPU time 13.29 seconds
Started Jul 21 04:23:08 PM PDT 24
Finished Jul 21 04:23:22 PM PDT 24
Peak memory 183228 kb
Host smart-f041bc84-4813-4e50-a09f-7ed85fc5141b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460980221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.2460980221
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.2012004367
Short name T424
Test name
Test status
Simulation time 226702584647 ps
CPU time 177.79 seconds
Started Jul 21 04:21:22 PM PDT 24
Finished Jul 21 04:24:20 PM PDT 24
Peak memory 183404 kb
Host smart-ae00c66f-a94d-4952-914b-2209e4fa5596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012004367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.2012004367
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.468796316
Short name T188
Test name
Test status
Simulation time 92384840858 ps
CPU time 153.87 seconds
Started Jul 21 04:20:30 PM PDT 24
Finished Jul 21 04:23:04 PM PDT 24
Peak memory 183452 kb
Host smart-d273b7a0-eb71-4801-9b32-facd2e254741
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468796316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.468796316
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.1897567853
Short name T114
Test name
Test status
Simulation time 14633807817 ps
CPU time 38.56 seconds
Started Jul 21 04:21:42 PM PDT 24
Finished Jul 21 04:22:21 PM PDT 24
Peak memory 183568 kb
Host smart-c2686d1f-33c6-49a6-ae74-a78537767819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897567853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.1897567853
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.4202649864
Short name T102
Test name
Test status
Simulation time 730522246263 ps
CPU time 380.96 seconds
Started Jul 21 04:22:48 PM PDT 24
Finished Jul 21 04:29:10 PM PDT 24
Peak memory 180480 kb
Host smart-ec43e342-b5b5-4f32-ab4c-7ce1117babdd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202649864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.4202649864
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_random.2226929208
Short name T361
Test name
Test status
Simulation time 614156901294 ps
CPU time 264.71 seconds
Started Jul 21 04:22:49 PM PDT 24
Finished Jul 21 04:27:14 PM PDT 24
Peak memory 191220 kb
Host smart-3c60adc9-68dc-47d6-b8be-340d1bcb8aaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226929208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.2226929208
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.950317231
Short name T125
Test name
Test status
Simulation time 40363264670 ps
CPU time 43.56 seconds
Started Jul 21 04:23:20 PM PDT 24
Finished Jul 21 04:24:05 PM PDT 24
Peak memory 191312 kb
Host smart-cd0f3f4f-e190-4671-80ed-1447f8296363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950317231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.950317231
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.457798687
Short name T169
Test name
Test status
Simulation time 170466468839 ps
CPU time 1995.23 seconds
Started Jul 21 04:23:21 PM PDT 24
Finished Jul 21 04:56:37 PM PDT 24
Peak memory 195024 kb
Host smart-f61f0b17-bc0c-44fd-a114-5cce52e54588
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457798687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all.
457798687
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.194993866
Short name T432
Test name
Test status
Simulation time 112241521195 ps
CPU time 184.95 seconds
Started Jul 21 04:23:03 PM PDT 24
Finished Jul 21 04:26:08 PM PDT 24
Peak memory 183036 kb
Host smart-bd2d966c-e373-458e-bacd-fa6b34b4c3ad
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194993866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.rv_timer_cfg_update_on_fly.194993866
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.3621165234
Short name T375
Test name
Test status
Simulation time 599516058665 ps
CPU time 275.82 seconds
Started Jul 21 04:23:07 PM PDT 24
Finished Jul 21 04:27:44 PM PDT 24
Peak memory 183328 kb
Host smart-ea989395-6661-44dd-9353-71f6953bbb05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621165234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.3621165234
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.1647982589
Short name T224
Test name
Test status
Simulation time 15939810148 ps
CPU time 15.04 seconds
Started Jul 21 04:20:07 PM PDT 24
Finished Jul 21 04:20:22 PM PDT 24
Peak memory 191696 kb
Host smart-f7d524b6-bf42-4c7a-9797-747391b7f82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647982589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.1647982589
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.898043598
Short name T33
Test name
Test status
Simulation time 427156383765 ps
CPU time 960.2 seconds
Started Jul 21 04:23:12 PM PDT 24
Finished Jul 21 04:39:13 PM PDT 24
Peak memory 195244 kb
Host smart-a8b81fda-eba9-4318-88fc-71ea0017225f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898043598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all.
898043598
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.371468665
Short name T189
Test name
Test status
Simulation time 5228141006602 ps
CPU time 1113.32 seconds
Started Jul 21 04:23:22 PM PDT 24
Finished Jul 21 04:41:55 PM PDT 24
Peak memory 183100 kb
Host smart-882d2b65-3d31-4693-b346-d5fd7af2c2df
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371468665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.rv_timer_cfg_update_on_fly.371468665
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.2649009220
Short name T367
Test name
Test status
Simulation time 111664771753 ps
CPU time 148.97 seconds
Started Jul 21 04:23:21 PM PDT 24
Finished Jul 21 04:25:51 PM PDT 24
Peak memory 183116 kb
Host smart-4e683b2a-1742-4364-9bca-e5d4154909ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649009220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.2649009220
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.176492506
Short name T18
Test name
Test status
Simulation time 266084501 ps
CPU time 1 seconds
Started Jul 21 04:20:16 PM PDT 24
Finished Jul 21 04:20:17 PM PDT 24
Peak memory 183200 kb
Host smart-5de6b44e-f1f9-41a6-94ec-9e2b20b0a4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176492506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.176492506
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.3005389057
Short name T260
Test name
Test status
Simulation time 238582981010 ps
CPU time 397.69 seconds
Started Jul 21 04:20:10 PM PDT 24
Finished Jul 21 04:26:48 PM PDT 24
Peak memory 183532 kb
Host smart-c3868920-37bf-4c1a-8522-c7289d9470c7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005389057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.3005389057
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.3520077748
Short name T392
Test name
Test status
Simulation time 788942448521 ps
CPU time 298.19 seconds
Started Jul 21 04:22:51 PM PDT 24
Finished Jul 21 04:27:50 PM PDT 24
Peak memory 183368 kb
Host smart-06ab200c-0f0e-4605-afbe-3a3bc62a2925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520077748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.3520077748
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.1456163556
Short name T24
Test name
Test status
Simulation time 5930666323 ps
CPU time 5.06 seconds
Started Jul 21 04:20:14 PM PDT 24
Finished Jul 21 04:20:19 PM PDT 24
Peak memory 183440 kb
Host smart-df8453dc-c85f-4991-8d62-fabac5f49821
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456163556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.1456163556
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.268779066
Short name T437
Test name
Test status
Simulation time 93946465288 ps
CPU time 83.3 seconds
Started Jul 21 04:21:00 PM PDT 24
Finished Jul 21 04:22:23 PM PDT 24
Peak memory 183416 kb
Host smart-689f3a86-9d35-40a5-ae34-74558a7e9776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268779066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.268779066
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.3540788284
Short name T136
Test name
Test status
Simulation time 437455169156 ps
CPU time 346.09 seconds
Started Jul 21 04:23:07 PM PDT 24
Finished Jul 21 04:28:55 PM PDT 24
Peak memory 190216 kb
Host smart-e093939a-0402-4bf7-a4cd-9b4561e56814
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540788284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.3540788284
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.1766313636
Short name T19
Test name
Test status
Simulation time 26605993587 ps
CPU time 11.57 seconds
Started Jul 21 04:20:23 PM PDT 24
Finished Jul 21 04:20:35 PM PDT 24
Peak memory 183740 kb
Host smart-c4e2eecb-5323-482a-af74-0e293b13baad
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766313636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.1766313636
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.1883457362
Short name T48
Test name
Test status
Simulation time 213993148567 ps
CPU time 174.35 seconds
Started Jul 21 04:22:57 PM PDT 24
Finished Jul 21 04:25:51 PM PDT 24
Peak memory 183340 kb
Host smart-09b57fb6-1870-407c-8572-25cfbec2ef51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883457362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.1883457362
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.1432396622
Short name T148
Test name
Test status
Simulation time 181027780063 ps
CPU time 121.63 seconds
Started Jul 21 04:22:55 PM PDT 24
Finished Jul 21 04:24:58 PM PDT 24
Peak memory 183336 kb
Host smart-7a311eaf-80ef-4e01-9f79-d4e8f160677a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432396622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.1432396622
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.2255009409
Short name T403
Test name
Test status
Simulation time 38456674 ps
CPU time 0.52 seconds
Started Jul 21 04:22:54 PM PDT 24
Finished Jul 21 04:22:56 PM PDT 24
Peak memory 183072 kb
Host smart-1ca33f51-88de-425c-a700-285dc850c2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255009409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.2255009409
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.2507931372
Short name T79
Test name
Test status
Simulation time 189395782254 ps
CPU time 289.99 seconds
Started Jul 21 04:22:54 PM PDT 24
Finished Jul 21 04:27:46 PM PDT 24
Peak memory 182164 kb
Host smart-4fc87a95-0e6f-437b-9e39-f2dbd27cea36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507931372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.2507931372
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.329806946
Short name T118
Test name
Test status
Simulation time 334690326751 ps
CPU time 593.63 seconds
Started Jul 21 04:23:18 PM PDT 24
Finished Jul 21 04:33:13 PM PDT 24
Peak memory 191564 kb
Host smart-4755a5be-2086-4b20-ad25-6bfefaaebf47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329806946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.329806946
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.3247807609
Short name T126
Test name
Test status
Simulation time 121654547723 ps
CPU time 88.02 seconds
Started Jul 21 04:23:05 PM PDT 24
Finished Jul 21 04:24:34 PM PDT 24
Peak memory 183300 kb
Host smart-cc233c53-4ece-4c6e-8fb7-e17cecbf9a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247807609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.3247807609
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.824077319
Short name T67
Test name
Test status
Simulation time 561057049969 ps
CPU time 140.11 seconds
Started Jul 21 04:20:27 PM PDT 24
Finished Jul 21 04:22:47 PM PDT 24
Peak memory 183420 kb
Host smart-bc7a9dab-4378-4244-96e6-5f13df9b48ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824077319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all.
824077319
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.19409554
Short name T134
Test name
Test status
Simulation time 1252396162695 ps
CPU time 616.58 seconds
Started Jul 21 04:20:29 PM PDT 24
Finished Jul 21 04:30:45 PM PDT 24
Peak memory 183432 kb
Host smart-b7113d7c-469d-46d1-a0f5-86863b0f1975
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19409554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.rv_timer_cfg_update_on_fly.19409554
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.3105733952
Short name T439
Test name
Test status
Simulation time 128589694570 ps
CPU time 208.95 seconds
Started Jul 21 04:20:32 PM PDT 24
Finished Jul 21 04:24:01 PM PDT 24
Peak memory 183428 kb
Host smart-f4aecd25-48ab-4dcd-bb1c-eb97ad10ecba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105733952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.3105733952
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.3176424598
Short name T7
Test name
Test status
Simulation time 5402411405 ps
CPU time 9.43 seconds
Started Jul 21 04:20:32 PM PDT 24
Finished Jul 21 04:20:42 PM PDT 24
Peak memory 183432 kb
Host smart-3470be7e-d954-42f2-9110-97e21969a4bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176424598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.3176424598
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.2832731536
Short name T412
Test name
Test status
Simulation time 60667114249 ps
CPU time 37.86 seconds
Started Jul 21 04:23:18 PM PDT 24
Finished Jul 21 04:23:57 PM PDT 24
Peak memory 191528 kb
Host smart-85d3b1cf-f6f2-41d9-a0cd-43e2554540ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832731536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.2832731536
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.213737124
Short name T288
Test name
Test status
Simulation time 15598752889 ps
CPU time 14.24 seconds
Started Jul 21 04:20:36 PM PDT 24
Finished Jul 21 04:20:50 PM PDT 24
Peak memory 183488 kb
Host smart-cba8050a-7fe4-4120-9120-56f42cf918e0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213737124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.rv_timer_cfg_update_on_fly.213737124
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.260125868
Short name T364
Test name
Test status
Simulation time 40055508852 ps
CPU time 15.01 seconds
Started Jul 21 04:22:53 PM PDT 24
Finished Jul 21 04:23:10 PM PDT 24
Peak memory 183012 kb
Host smart-dd429f63-959f-4dc2-88db-49c45d89751e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260125868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.260125868
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.1263021391
Short name T296
Test name
Test status
Simulation time 105140907501 ps
CPU time 102.59 seconds
Started Jul 21 04:23:12 PM PDT 24
Finished Jul 21 04:24:55 PM PDT 24
Peak memory 191272 kb
Host smart-6a3375a9-70ac-4088-b3a4-d1d1761c381d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263021391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.1263021391
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.105006297
Short name T378
Test name
Test status
Simulation time 17085066607 ps
CPU time 157.57 seconds
Started Jul 21 04:23:18 PM PDT 24
Finished Jul 21 04:25:56 PM PDT 24
Peak memory 183352 kb
Host smart-1a755e56-2aac-4b57-8dea-6ed141622871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105006297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.105006297
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.812609027
Short name T31
Test name
Test status
Simulation time 531879352263 ps
CPU time 1098.05 seconds
Started Jul 21 04:20:40 PM PDT 24
Finished Jul 21 04:38:59 PM PDT 24
Peak memory 191600 kb
Host smart-70a83e48-fa3e-48cf-89c7-2f1492f8d90c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812609027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all.
812609027
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.3498447546
Short name T379
Test name
Test status
Simulation time 94139425221 ps
CPU time 38.52 seconds
Started Jul 21 04:23:18 PM PDT 24
Finished Jul 21 04:23:57 PM PDT 24
Peak memory 183356 kb
Host smart-16451f2b-5cc6-4b21-9b73-66fe719ebbd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498447546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.3498447546
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.329482871
Short name T396
Test name
Test status
Simulation time 42522285449 ps
CPU time 74.39 seconds
Started Jul 21 04:23:12 PM PDT 24
Finished Jul 21 04:24:27 PM PDT 24
Peak memory 183000 kb
Host smart-8a528afd-2431-4561-b59b-0f4a147fbf2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329482871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.329482871
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.2785214371
Short name T22
Test name
Test status
Simulation time 358263290 ps
CPU time 3.36 seconds
Started Jul 21 04:23:13 PM PDT 24
Finished Jul 21 04:23:17 PM PDT 24
Peak memory 192268 kb
Host smart-6842d737-8fde-4a67-ab00-5e187979fe0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785214371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.2785214371
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all_with_rand_reset.3679156790
Short name T35
Test name
Test status
Simulation time 11352180704 ps
CPU time 69.44 seconds
Started Jul 21 04:23:12 PM PDT 24
Finished Jul 21 04:24:22 PM PDT 24
Peak memory 197232 kb
Host smart-d5d33768-311e-487a-aec9-ba72baaa50ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679156790 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all_with_rand_reset.3679156790
Directory /workspace/39.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.684051948
Short name T422
Test name
Test status
Simulation time 91303707509 ps
CPU time 153.42 seconds
Started Jul 21 04:22:50 PM PDT 24
Finished Jul 21 04:25:25 PM PDT 24
Peak memory 183332 kb
Host smart-9a6e3a30-037d-4947-8ecb-9b29ffa1c122
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684051948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.rv_timer_cfg_update_on_fly.684051948
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.2243254104
Short name T399
Test name
Test status
Simulation time 269790237040 ps
CPU time 95.91 seconds
Started Jul 21 04:23:24 PM PDT 24
Finished Jul 21 04:25:01 PM PDT 24
Peak memory 182724 kb
Host smart-453b7af8-61b9-4fde-8719-ed5ce44ddf93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243254104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.2243254104
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.2744708758
Short name T181
Test name
Test status
Simulation time 655069422131 ps
CPU time 323.87 seconds
Started Jul 21 04:19:39 PM PDT 24
Finished Jul 21 04:25:03 PM PDT 24
Peak memory 191600 kb
Host smart-a93001f0-db43-4f9e-a9b7-7af2450ef304
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744708758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.2744708758
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.2781625396
Short name T371
Test name
Test status
Simulation time 611028016 ps
CPU time 1.1 seconds
Started Jul 21 04:20:03 PM PDT 24
Finished Jul 21 04:20:04 PM PDT 24
Peak memory 183300 kb
Host smart-f606d86f-5c9c-4a5a-9b54-f1453f5ac4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781625396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.2781625396
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.3330408277
Short name T17
Test name
Test status
Simulation time 112154274 ps
CPU time 0.83 seconds
Started Jul 21 04:19:18 PM PDT 24
Finished Jul 21 04:19:19 PM PDT 24
Peak memory 213640 kb
Host smart-81b30cec-8da9-405b-bfcf-7f8ce6ea443e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330408277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.3330408277
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.2765991956
Short name T335
Test name
Test status
Simulation time 245905981116 ps
CPU time 331.2 seconds
Started Jul 21 04:23:18 PM PDT 24
Finished Jul 21 04:28:50 PM PDT 24
Peak memory 183340 kb
Host smart-19f69aa8-f659-4ff9-a944-1e9c6476f49c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765991956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.2765991956
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.3276547120
Short name T395
Test name
Test status
Simulation time 30463000098 ps
CPU time 42.89 seconds
Started Jul 21 04:23:32 PM PDT 24
Finished Jul 21 04:24:16 PM PDT 24
Peak memory 183064 kb
Host smart-9367e8c3-4244-4aef-b5e9-3ed6349232cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276547120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.3276547120
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.3869078927
Short name T333
Test name
Test status
Simulation time 103312894561 ps
CPU time 91.75 seconds
Started Jul 21 04:20:33 PM PDT 24
Finished Jul 21 04:22:05 PM PDT 24
Peak memory 193832 kb
Host smart-7dc8b069-e768-472c-9941-bca93e9c11a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869078927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.3869078927
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.248981289
Short name T21
Test name
Test status
Simulation time 1015789122 ps
CPU time 2.74 seconds
Started Jul 21 04:23:12 PM PDT 24
Finished Jul 21 04:23:15 PM PDT 24
Peak memory 182268 kb
Host smart-3a597473-de12-462f-adef-654f5634a348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248981289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.248981289
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.3632082722
Short name T216
Test name
Test status
Simulation time 658583721269 ps
CPU time 529.62 seconds
Started Jul 21 04:20:45 PM PDT 24
Finished Jul 21 04:29:35 PM PDT 24
Peak memory 183528 kb
Host smart-755284c2-ca7a-40eb-b2b3-495297053afc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632082722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.3632082722
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_random.3149495113
Short name T420
Test name
Test status
Simulation time 21356225410 ps
CPU time 35.62 seconds
Started Jul 21 04:23:18 PM PDT 24
Finished Jul 21 04:23:55 PM PDT 24
Peak memory 183368 kb
Host smart-f87df15b-ea25-4291-9a62-b4845761d7a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149495113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.3149495113
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.2931383683
Short name T228
Test name
Test status
Simulation time 92517325365 ps
CPU time 940.01 seconds
Started Jul 21 04:22:45 PM PDT 24
Finished Jul 21 04:38:27 PM PDT 24
Peak memory 189664 kb
Host smart-0af531ef-80c0-4fff-8eb9-56aff3236ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931383683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.2931383683
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.142344407
Short name T193
Test name
Test status
Simulation time 70065190432 ps
CPU time 22.44 seconds
Started Jul 21 04:23:02 PM PDT 24
Finished Jul 21 04:23:25 PM PDT 24
Peak memory 183064 kb
Host smart-1ef2ea38-3863-499d-88b9-3d859c1953bc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142344407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.rv_timer_cfg_update_on_fly.142344407
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.1093565658
Short name T365
Test name
Test status
Simulation time 86730422413 ps
CPU time 128.15 seconds
Started Jul 21 04:24:17 PM PDT 24
Finished Jul 21 04:26:25 PM PDT 24
Peak memory 183180 kb
Host smart-d2f197c3-debe-4088-a220-aedcfb7e153f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093565658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.1093565658
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.78553891
Short name T352
Test name
Test status
Simulation time 70000888230 ps
CPU time 126.51 seconds
Started Jul 21 04:22:45 PM PDT 24
Finished Jul 21 04:24:53 PM PDT 24
Peak memory 190516 kb
Host smart-3026f1b8-2b50-4358-9fed-52838ce3f7dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78553891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.78553891
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.2042045718
Short name T434
Test name
Test status
Simulation time 211434536 ps
CPU time 0.79 seconds
Started Jul 21 04:21:47 PM PDT 24
Finished Jul 21 04:21:48 PM PDT 24
Peak memory 183172 kb
Host smart-cef08022-8288-4e85-a500-7d4040dd6313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042045718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.2042045718
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all_with_rand_reset.1013089993
Short name T104
Test name
Test status
Simulation time 47511482473 ps
CPU time 259.21 seconds
Started Jul 21 04:22:52 PM PDT 24
Finished Jul 21 04:27:14 PM PDT 24
Peak memory 205448 kb
Host smart-7d16340e-c9f9-44aa-99b4-669301dd56cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013089993 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all_with_rand_reset.1013089993
Directory /workspace/42.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.3278783934
Short name T374
Test name
Test status
Simulation time 64731972338 ps
CPU time 87.43 seconds
Started Jul 21 04:20:47 PM PDT 24
Finished Jul 21 04:22:15 PM PDT 24
Peak memory 183420 kb
Host smart-ed634371-bd3f-4c55-92d1-45c175f52547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278783934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.3278783934
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.1361875942
Short name T157
Test name
Test status
Simulation time 276047920700 ps
CPU time 132.16 seconds
Started Jul 21 04:20:51 PM PDT 24
Finished Jul 21 04:23:03 PM PDT 24
Peak memory 191560 kb
Host smart-1cc09289-2308-49bb-815f-367035c92fd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361875942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.1361875942
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.4243486710
Short name T401
Test name
Test status
Simulation time 550143897 ps
CPU time 1.77 seconds
Started Jul 21 04:20:53 PM PDT 24
Finished Jul 21 04:20:55 PM PDT 24
Peak memory 183504 kb
Host smart-c6c07099-0467-4709-928c-262b2f6dae20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243486710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.4243486710
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.2753663648
Short name T163
Test name
Test status
Simulation time 298915193332 ps
CPU time 258.19 seconds
Started Jul 21 04:23:20 PM PDT 24
Finished Jul 21 04:27:39 PM PDT 24
Peak memory 183340 kb
Host smart-ee2ff15e-53ce-4e98-bd44-4a817b454706
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753663648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.2753663648
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.3188949531
Short name T385
Test name
Test status
Simulation time 377472638820 ps
CPU time 128.15 seconds
Started Jul 21 04:23:27 PM PDT 24
Finished Jul 21 04:25:35 PM PDT 24
Peak memory 183044 kb
Host smart-ee888784-4b9d-42c3-a0fa-0833f10f697d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188949531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.3188949531
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.1865160067
Short name T220
Test name
Test status
Simulation time 375064617893 ps
CPU time 179.62 seconds
Started Jul 21 04:21:48 PM PDT 24
Finished Jul 21 04:24:47 PM PDT 24
Peak memory 191560 kb
Host smart-0c7c3c00-65b6-4b4a-8fd6-4ed87fe7bfc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865160067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.1865160067
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.3302768191
Short name T443
Test name
Test status
Simulation time 31149314010 ps
CPU time 143.59 seconds
Started Jul 21 04:23:18 PM PDT 24
Finished Jul 21 04:25:42 PM PDT 24
Peak memory 181880 kb
Host smart-f1ccc44e-2171-4022-bce1-b5145ff00861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302768191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.3302768191
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.3982252444
Short name T6
Test name
Test status
Simulation time 154063058898 ps
CPU time 1932.77 seconds
Started Jul 21 04:23:28 PM PDT 24
Finished Jul 21 04:55:41 PM PDT 24
Peak memory 191232 kb
Host smart-3d8bfc9b-c5a1-4c01-8687-f21d1d41caf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982252444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.3982252444
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.420822088
Short name T40
Test name
Test status
Simulation time 25513836940 ps
CPU time 200.25 seconds
Started Jul 21 04:20:57 PM PDT 24
Finished Jul 21 04:24:18 PM PDT 24
Peak memory 206216 kb
Host smart-e372d2e5-2dca-49ef-a190-652638095efd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420822088 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.420822088
Directory /workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.778203699
Short name T223
Test name
Test status
Simulation time 2241130860468 ps
CPU time 1035.87 seconds
Started Jul 21 04:22:49 PM PDT 24
Finished Jul 21 04:40:06 PM PDT 24
Peak memory 183340 kb
Host smart-dcf38580-493c-4237-a99f-c0fcaf8c2630
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778203699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.rv_timer_cfg_update_on_fly.778203699
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.2496249485
Short name T397
Test name
Test status
Simulation time 466315066801 ps
CPU time 172.31 seconds
Started Jul 21 04:23:26 PM PDT 24
Finished Jul 21 04:26:19 PM PDT 24
Peak memory 183044 kb
Host smart-923ab810-23b2-4f48-b7ed-e9c645a208ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496249485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.2496249485
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.2525146855
Short name T245
Test name
Test status
Simulation time 72603432015 ps
CPU time 127.34 seconds
Started Jul 21 04:20:56 PM PDT 24
Finished Jul 21 04:23:04 PM PDT 24
Peak memory 195152 kb
Host smart-5076e114-31ad-4b77-aa55-217163448f2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525146855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.2525146855
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.178158013
Short name T445
Test name
Test status
Simulation time 189709186834 ps
CPU time 105.3 seconds
Started Jul 21 04:22:49 PM PDT 24
Finished Jul 21 04:24:35 PM PDT 24
Peak memory 183340 kb
Host smart-705c6ac6-8e21-47b4-bf20-c7f72cc0f94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178158013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.178158013
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.1411523461
Short name T70
Test name
Test status
Simulation time 822633173596 ps
CPU time 353.96 seconds
Started Jul 21 04:21:22 PM PDT 24
Finished Jul 21 04:27:17 PM PDT 24
Peak memory 191592 kb
Host smart-0ff0206d-7262-485a-afe5-e229e6668ff3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411523461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.1411523461
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.2229973571
Short name T370
Test name
Test status
Simulation time 295825804441 ps
CPU time 117.43 seconds
Started Jul 21 04:20:55 PM PDT 24
Finished Jul 21 04:22:53 PM PDT 24
Peak memory 183492 kb
Host smart-568f1329-0a83-4595-9100-3c3a04d2bf3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229973571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.2229973571
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.2487307860
Short name T417
Test name
Test status
Simulation time 170123764007 ps
CPU time 62.03 seconds
Started Jul 21 04:22:50 PM PDT 24
Finished Jul 21 04:23:53 PM PDT 24
Peak memory 183356 kb
Host smart-07d3d6c8-6689-4166-ae47-c6ba3cf5ca2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487307860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.2487307860
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.4083991232
Short name T322
Test name
Test status
Simulation time 35216081538 ps
CPU time 71.56 seconds
Started Jul 21 04:23:26 PM PDT 24
Finished Jul 21 04:24:38 PM PDT 24
Peak memory 194168 kb
Host smart-1becc305-373e-409c-b77e-96f88f240e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083991232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.4083991232
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.371448859
Short name T179
Test name
Test status
Simulation time 1091392634604 ps
CPU time 855.1 seconds
Started Jul 21 04:21:09 PM PDT 24
Finished Jul 21 04:35:24 PM PDT 24
Peak memory 191588 kb
Host smart-6df9ada9-4969-4ebb-a377-bdac5f0a4ced
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371448859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all.
371448859
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.2949688762
Short name T387
Test name
Test status
Simulation time 427221717036 ps
CPU time 149.03 seconds
Started Jul 21 04:22:49 PM PDT 24
Finished Jul 21 04:25:19 PM PDT 24
Peak memory 183040 kb
Host smart-a9ded220-8c3c-4839-af33-550f55320a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949688762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.2949688762
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.1936370759
Short name T405
Test name
Test status
Simulation time 158047090489 ps
CPU time 82.29 seconds
Started Jul 21 04:21:02 PM PDT 24
Finished Jul 21 04:22:25 PM PDT 24
Peak memory 183580 kb
Host smart-049894a4-f1ea-40a5-aea1-f0cc5bf55b32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936370759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.1936370759
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.4161256729
Short name T336
Test name
Test status
Simulation time 92651129342 ps
CPU time 98.89 seconds
Started Jul 21 04:23:31 PM PDT 24
Finished Jul 21 04:25:10 PM PDT 24
Peak memory 191568 kb
Host smart-34c1986a-ed81-4db1-a505-f3237d59c737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161256729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.4161256729
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.3370017687
Short name T321
Test name
Test status
Simulation time 28777996962 ps
CPU time 28.75 seconds
Started Jul 21 04:22:53 PM PDT 24
Finished Jul 21 04:23:23 PM PDT 24
Peak memory 182812 kb
Host smart-7497045f-d8d5-41a4-b3c1-2cd74592792d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370017687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.3370017687
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.1586098239
Short name T369
Test name
Test status
Simulation time 512974485907 ps
CPU time 67.25 seconds
Started Jul 21 04:23:31 PM PDT 24
Finished Jul 21 04:24:38 PM PDT 24
Peak memory 183368 kb
Host smart-a6ba8db8-7dca-44a4-8b87-fd2e50972cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586098239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.1586098239
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.130052978
Short name T353
Test name
Test status
Simulation time 535285494483 ps
CPU time 247.35 seconds
Started Jul 21 04:21:01 PM PDT 24
Finished Jul 21 04:25:08 PM PDT 24
Peak memory 191616 kb
Host smart-0342686b-b4f9-4d17-8b3b-9a4828ea495b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130052978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.130052978
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.3334323461
Short name T292
Test name
Test status
Simulation time 116943224938 ps
CPU time 716.56 seconds
Started Jul 21 04:23:04 PM PDT 24
Finished Jul 21 04:35:01 PM PDT 24
Peak memory 191364 kb
Host smart-e08dbac3-f806-42f6-81d0-51f2da82da3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334323461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.3334323461
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.3719343820
Short name T327
Test name
Test status
Simulation time 245685833241 ps
CPU time 614.17 seconds
Started Jul 21 04:21:14 PM PDT 24
Finished Jul 21 04:31:29 PM PDT 24
Peak memory 191948 kb
Host smart-c50dc84c-3c94-47d0-9798-6f2487649d12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719343820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.3719343820
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.3012665334
Short name T415
Test name
Test status
Simulation time 494018027840 ps
CPU time 175.61 seconds
Started Jul 21 04:21:09 PM PDT 24
Finished Jul 21 04:24:05 PM PDT 24
Peak memory 183420 kb
Host smart-0e11c3b9-af80-41f4-9d20-ed8a092df357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012665334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.3012665334
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.873328366
Short name T358
Test name
Test status
Simulation time 69394533180 ps
CPU time 32.88 seconds
Started Jul 21 04:21:18 PM PDT 24
Finished Jul 21 04:21:51 PM PDT 24
Peak memory 183496 kb
Host smart-9ff06b5e-6493-4d6d-8398-075509173841
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873328366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.873328366
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.97475924
Short name T406
Test name
Test status
Simulation time 21518043 ps
CPU time 0.56 seconds
Started Jul 21 04:21:10 PM PDT 24
Finished Jul 21 04:21:11 PM PDT 24
Peak memory 183144 kb
Host smart-3d114ca2-26d0-4c0b-8273-734e49f57f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97475924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.97475924
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.3284439989
Short name T178
Test name
Test status
Simulation time 81012333661 ps
CPU time 117.35 seconds
Started Jul 21 04:22:57 PM PDT 24
Finished Jul 21 04:24:56 PM PDT 24
Peak memory 182184 kb
Host smart-2356eac5-4bdf-491a-ac2e-aeb247c38d7d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284439989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.3284439989
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.2005989590
Short name T450
Test name
Test status
Simulation time 45496156540 ps
CPU time 61.46 seconds
Started Jul 21 04:23:58 PM PDT 24
Finished Jul 21 04:25:00 PM PDT 24
Peak memory 183156 kb
Host smart-8c86ccf7-fde0-46cb-805d-48cd49a4e363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005989590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.2005989590
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.302282569
Short name T400
Test name
Test status
Simulation time 23862450 ps
CPU time 0.52 seconds
Started Jul 21 04:23:58 PM PDT 24
Finished Jul 21 04:23:59 PM PDT 24
Peak memory 182808 kb
Host smart-5c4c7271-a54d-41c0-b6c1-b280139d3dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302282569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.302282569
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/51.rv_timer_random.1785813284
Short name T128
Test name
Test status
Simulation time 184592586718 ps
CPU time 867.29 seconds
Started Jul 21 04:22:54 PM PDT 24
Finished Jul 21 04:37:24 PM PDT 24
Peak memory 190324 kb
Host smart-478d27dc-1300-46c8-8dfd-2a1e677c9553
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785813284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.1785813284
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.2875994094
Short name T124
Test name
Test status
Simulation time 50811539891 ps
CPU time 23.52 seconds
Started Jul 21 04:23:26 PM PDT 24
Finished Jul 21 04:23:50 PM PDT 24
Peak memory 183024 kb
Host smart-225f0f17-93f7-4306-b1d5-eeb232a3d8e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875994094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.2875994094
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.3661481936
Short name T243
Test name
Test status
Simulation time 765698378196 ps
CPU time 608.59 seconds
Started Jul 21 04:22:54 PM PDT 24
Finished Jul 21 04:33:05 PM PDT 24
Peak memory 190364 kb
Host smart-481e34ab-f5e5-48ac-b221-bd33fc972bb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661481936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.3661481936
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.2506690661
Short name T201
Test name
Test status
Simulation time 65898447029 ps
CPU time 188.97 seconds
Started Jul 21 04:22:36 PM PDT 24
Finished Jul 21 04:25:46 PM PDT 24
Peak memory 189476 kb
Host smart-0e243ea9-79d4-4f68-a0cd-a50eedd56f8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506690661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.2506690661
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.262632333
Short name T272
Test name
Test status
Simulation time 326262444587 ps
CPU time 640.07 seconds
Started Jul 21 04:22:50 PM PDT 24
Finished Jul 21 04:33:32 PM PDT 24
Peak memory 191596 kb
Host smart-a65dcb1e-7c27-4234-a703-cd60dc83f1fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262632333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.262632333
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.4239732866
Short name T43
Test name
Test status
Simulation time 181947630134 ps
CPU time 1055.18 seconds
Started Jul 21 04:22:52 PM PDT 24
Finished Jul 21 04:40:28 PM PDT 24
Peak memory 191536 kb
Host smart-bd1f28f9-7e49-4259-ab80-57abeeae475c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239732866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.4239732866
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.3511079016
Short name T253
Test name
Test status
Simulation time 49040165134 ps
CPU time 80.23 seconds
Started Jul 21 04:22:36 PM PDT 24
Finished Jul 21 04:23:57 PM PDT 24
Peak memory 181516 kb
Host smart-199b497f-1ce0-4241-a06e-c5a8f860a7df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511079016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.3511079016
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.1289989100
Short name T207
Test name
Test status
Simulation time 349241867553 ps
CPU time 147.01 seconds
Started Jul 21 04:22:50 PM PDT 24
Finished Jul 21 04:25:18 PM PDT 24
Peak memory 191544 kb
Host smart-42d7fc34-0213-4497-af51-a0f4ffcb5142
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289989100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.1289989100
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.831881885
Short name T211
Test name
Test status
Simulation time 193095967652 ps
CPU time 287.44 seconds
Started Jul 21 04:23:07 PM PDT 24
Finished Jul 21 04:27:56 PM PDT 24
Peak memory 182012 kb
Host smart-775e73aa-406f-4e43-84b6-81a57f9381bd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831881885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.rv_timer_cfg_update_on_fly.831881885
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_random.221770404
Short name T428
Test name
Test status
Simulation time 48709751006 ps
CPU time 77.88 seconds
Started Jul 21 04:20:16 PM PDT 24
Finished Jul 21 04:21:34 PM PDT 24
Peak memory 183284 kb
Host smart-4a55be77-169b-41bc-bedf-b089c185df79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221770404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.221770404
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.1948719621
Short name T414
Test name
Test status
Simulation time 2698989914 ps
CPU time 6.3 seconds
Started Jul 21 04:20:15 PM PDT 24
Finished Jul 21 04:20:21 PM PDT 24
Peak memory 183420 kb
Host smart-99cfb745-a113-4261-ad55-0030618e9bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948719621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.1948719621
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.3113692329
Short name T177
Test name
Test status
Simulation time 115466264573 ps
CPU time 337.51 seconds
Started Jul 21 04:22:50 PM PDT 24
Finished Jul 21 04:28:29 PM PDT 24
Peak memory 191580 kb
Host smart-2f3e8827-b3e2-4b42-bbd2-b8b5da925434
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113692329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.3113692329
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.2290308653
Short name T359
Test name
Test status
Simulation time 754880517048 ps
CPU time 507.22 seconds
Started Jul 21 04:22:57 PM PDT 24
Finished Jul 21 04:31:25 PM PDT 24
Peak memory 191504 kb
Host smart-79c8956e-5c0d-44bb-8920-331076e9d214
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290308653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.2290308653
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.388493699
Short name T112
Test name
Test status
Simulation time 141663586694 ps
CPU time 127.38 seconds
Started Jul 21 04:23:00 PM PDT 24
Finished Jul 21 04:25:08 PM PDT 24
Peak memory 194444 kb
Host smart-8c937f60-e81b-481e-9be5-f83b2337c8f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388493699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.388493699
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.925656383
Short name T304
Test name
Test status
Simulation time 118481475637 ps
CPU time 61.71 seconds
Started Jul 21 04:22:45 PM PDT 24
Finished Jul 21 04:23:49 PM PDT 24
Peak memory 189580 kb
Host smart-d7fe4417-2413-41f9-8503-c29e83dd2539
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925656383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.925656383
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.874552175
Short name T122
Test name
Test status
Simulation time 550151076776 ps
CPU time 207.33 seconds
Started Jul 21 04:23:16 PM PDT 24
Finished Jul 21 04:26:44 PM PDT 24
Peak memory 191284 kb
Host smart-5400351c-8887-47ee-8ad1-86f48140bfcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874552175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.874552175
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.1291481791
Short name T110
Test name
Test status
Simulation time 122599176398 ps
CPU time 67.18 seconds
Started Jul 21 04:21:30 PM PDT 24
Finished Jul 21 04:22:37 PM PDT 24
Peak memory 183736 kb
Host smart-73b142fc-35ce-41ad-a11b-0bb4cd095600
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291481791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.1291481791
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.2029635383
Short name T209
Test name
Test status
Simulation time 120674493518 ps
CPU time 114.06 seconds
Started Jul 21 04:22:45 PM PDT 24
Finished Jul 21 04:24:41 PM PDT 24
Peak memory 189420 kb
Host smart-ded8bcc3-d4e9-4347-bddb-c7be6f137f26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029635383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.2029635383
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.936395169
Short name T298
Test name
Test status
Simulation time 382007597935 ps
CPU time 175.53 seconds
Started Jul 21 04:23:04 PM PDT 24
Finished Jul 21 04:26:00 PM PDT 24
Peak memory 191368 kb
Host smart-a85a91bb-2a59-44c9-9d09-38c5618d9c2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936395169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.936395169
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.1303952381
Short name T234
Test name
Test status
Simulation time 36194981622 ps
CPU time 55.16 seconds
Started Jul 21 04:23:05 PM PDT 24
Finished Jul 21 04:24:01 PM PDT 24
Peak memory 183308 kb
Host smart-8e3b8445-eb87-4d1d-b01c-12197a251bb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303952381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.1303952381
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.4290524962
Short name T423
Test name
Test status
Simulation time 121761350137 ps
CPU time 155.2 seconds
Started Jul 21 04:22:37 PM PDT 24
Finished Jul 21 04:25:14 PM PDT 24
Peak memory 182292 kb
Host smart-dbabc8ee-455c-4b8e-8428-ea5cc5ccf7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290524962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.4290524962
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.1384553122
Short name T173
Test name
Test status
Simulation time 1301581496311 ps
CPU time 502.45 seconds
Started Jul 21 04:23:16 PM PDT 24
Finished Jul 21 04:31:39 PM PDT 24
Peak memory 191296 kb
Host smart-8426cd2b-8832-41d2-8f6b-c1e8031c9006
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384553122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.1384553122
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.4153675803
Short name T129
Test name
Test status
Simulation time 121379031702 ps
CPU time 54.01 seconds
Started Jul 21 04:22:56 PM PDT 24
Finished Jul 21 04:23:50 PM PDT 24
Peak memory 191524 kb
Host smart-68639f87-0692-4d32-9e57-47e232bf0209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153675803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.4153675803
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.3417024535
Short name T32
Test name
Test status
Simulation time 1826682005207 ps
CPU time 1666.38 seconds
Started Jul 21 04:23:14 PM PDT 24
Finished Jul 21 04:51:01 PM PDT 24
Peak memory 191568 kb
Host smart-565a9ea3-0ac0-44bb-853e-6dddda093aa2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417024535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
3417024535
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/70.rv_timer_random.1528972295
Short name T273
Test name
Test status
Simulation time 208808835532 ps
CPU time 702.4 seconds
Started Jul 21 04:23:03 PM PDT 24
Finished Jul 21 04:34:46 PM PDT 24
Peak memory 191252 kb
Host smart-bb29c15f-5add-4c22-8d8a-2e495400c551
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528972295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.1528972295
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.1362845178
Short name T255
Test name
Test status
Simulation time 2858031020656 ps
CPU time 1544.53 seconds
Started Jul 21 04:23:05 PM PDT 24
Finished Jul 21 04:48:50 PM PDT 24
Peak memory 190804 kb
Host smart-f57f984c-9095-4729-b144-558266a59588
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362845178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.1362845178
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.1390697032
Short name T202
Test name
Test status
Simulation time 60399721389 ps
CPU time 276.24 seconds
Started Jul 21 04:23:04 PM PDT 24
Finished Jul 21 04:27:40 PM PDT 24
Peak memory 191272 kb
Host smart-a35354aa-6aaf-4d35-89ed-f24091d866a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390697032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.1390697032
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.722662863
Short name T413
Test name
Test status
Simulation time 40973345413 ps
CPU time 63.9 seconds
Started Jul 21 04:23:05 PM PDT 24
Finished Jul 21 04:24:09 PM PDT 24
Peak memory 183160 kb
Host smart-17c8fef0-11e6-47d9-8558-c266f4d6a38d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722662863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.722662863
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.600933096
Short name T433
Test name
Test status
Simulation time 265137489327 ps
CPU time 717.54 seconds
Started Jul 21 04:23:03 PM PDT 24
Finished Jul 21 04:35:01 PM PDT 24
Peak memory 191252 kb
Host smart-b6b76f3f-8516-4bea-bc99-886cf39172f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600933096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.600933096
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.3007515325
Short name T208
Test name
Test status
Simulation time 565564834612 ps
CPU time 2316.58 seconds
Started Jul 21 04:21:44 PM PDT 24
Finished Jul 21 05:00:21 PM PDT 24
Peak memory 191700 kb
Host smart-a6b631cf-4523-4174-8bc8-5d1aab818ca0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007515325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.3007515325
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.104440519
Short name T204
Test name
Test status
Simulation time 28811701350 ps
CPU time 47.62 seconds
Started Jul 21 04:23:07 PM PDT 24
Finished Jul 21 04:23:56 PM PDT 24
Peak memory 183112 kb
Host smart-72225f67-d6e3-4457-9a41-9609e4679634
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104440519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.104440519
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.3624720627
Short name T311
Test name
Test status
Simulation time 219554703443 ps
CPU time 84.62 seconds
Started Jul 21 04:23:07 PM PDT 24
Finished Jul 21 04:24:33 PM PDT 24
Peak memory 191316 kb
Host smart-4f91989b-3019-4bde-a097-3bf7668d1d1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624720627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.3624720627
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.3089232135
Short name T286
Test name
Test status
Simulation time 42316822303 ps
CPU time 73.79 seconds
Started Jul 21 04:21:57 PM PDT 24
Finished Jul 21 04:23:11 PM PDT 24
Peak memory 183444 kb
Host smart-fe34b2bd-448d-4147-a6f9-4658e118e91a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089232135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.3089232135
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.3490085737
Short name T290
Test name
Test status
Simulation time 96108708737 ps
CPU time 127.84 seconds
Started Jul 21 04:23:59 PM PDT 24
Finished Jul 21 04:26:07 PM PDT 24
Peak memory 191352 kb
Host smart-4151d9d9-6b04-44d9-8f98-28236c2d07cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490085737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.3490085737
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.1016690655
Short name T315
Test name
Test status
Simulation time 191574990322 ps
CPU time 300.76 seconds
Started Jul 21 04:21:51 PM PDT 24
Finished Jul 21 04:26:52 PM PDT 24
Peak memory 183576 kb
Host smart-beea16e7-2bd8-4161-8786-123cbb8a52ae
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016690655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.1016690655
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.1925755729
Short name T384
Test name
Test status
Simulation time 75778297559 ps
CPU time 114.52 seconds
Started Jul 21 04:22:54 PM PDT 24
Finished Jul 21 04:24:50 PM PDT 24
Peak memory 183300 kb
Host smart-dbd1be42-b746-4dc5-954d-ec4affb1d94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925755729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.1925755729
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.469704001
Short name T103
Test name
Test status
Simulation time 112061546758 ps
CPU time 161.53 seconds
Started Jul 21 04:23:01 PM PDT 24
Finished Jul 21 04:25:43 PM PDT 24
Peak memory 190764 kb
Host smart-d422c683-7d62-4e10-9a74-8fac16925b73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469704001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.469704001
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.93044192
Short name T247
Test name
Test status
Simulation time 206440380166 ps
CPU time 113.14 seconds
Started Jul 21 04:22:40 PM PDT 24
Finished Jul 21 04:24:35 PM PDT 24
Peak memory 194780 kb
Host smart-2dd0c6e1-c58a-415d-8741-f92f3adb1236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93044192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.93044192
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.4011967297
Short name T319
Test name
Test status
Simulation time 457760550249 ps
CPU time 230.6 seconds
Started Jul 21 04:23:06 PM PDT 24
Finished Jul 21 04:26:57 PM PDT 24
Peak memory 191392 kb
Host smart-e53900cb-8b71-47d9-8e38-e6b382cd83df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011967297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
4011967297
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/80.rv_timer_random.345105041
Short name T308
Test name
Test status
Simulation time 24846740959 ps
CPU time 52.03 seconds
Started Jul 21 04:23:59 PM PDT 24
Finished Jul 21 04:24:51 PM PDT 24
Peak memory 183156 kb
Host smart-84f3797c-0163-42f7-842b-cdd627bdcf51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345105041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.345105041
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.1749074096
Short name T241
Test name
Test status
Simulation time 1341352274456 ps
CPU time 1227.64 seconds
Started Jul 21 04:23:49 PM PDT 24
Finished Jul 21 04:44:18 PM PDT 24
Peak memory 189784 kb
Host smart-31d48f34-2eb7-4aff-836d-a5db521aab9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749074096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.1749074096
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.1962319056
Short name T232
Test name
Test status
Simulation time 746738520029 ps
CPU time 655.82 seconds
Started Jul 21 04:21:51 PM PDT 24
Finished Jul 21 04:32:47 PM PDT 24
Peak memory 191620 kb
Host smart-84c1de18-4053-496f-886b-adfc9dce340b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962319056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.1962319056
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.3048015589
Short name T212
Test name
Test status
Simulation time 110910518526 ps
CPU time 167.68 seconds
Started Jul 21 04:21:52 PM PDT 24
Finished Jul 21 04:24:40 PM PDT 24
Peak memory 191584 kb
Host smart-c7916911-b050-4737-904b-9dda5f6c1697
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048015589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.3048015589
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.2781188370
Short name T318
Test name
Test status
Simulation time 427334547316 ps
CPU time 568.42 seconds
Started Jul 21 04:23:50 PM PDT 24
Finished Jul 21 04:33:19 PM PDT 24
Peak memory 190420 kb
Host smart-cf2937d1-a049-47ee-85e9-b1fd68f6ef1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781188370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.2781188370
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.1962666065
Short name T339
Test name
Test status
Simulation time 231334729859 ps
CPU time 1015.82 seconds
Started Jul 21 04:23:58 PM PDT 24
Finished Jul 21 04:40:54 PM PDT 24
Peak memory 191316 kb
Host smart-b3a23986-ba59-4cc0-b4a5-0b104b5ee38e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962666065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.1962666065
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.1723321724
Short name T20
Test name
Test status
Simulation time 205974657738 ps
CPU time 348.98 seconds
Started Jul 21 04:23:49 PM PDT 24
Finished Jul 21 04:29:39 PM PDT 24
Peak memory 189972 kb
Host smart-d91988c3-a040-4d50-982b-ef031177e7f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723321724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.1723321724
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.1260221717
Short name T266
Test name
Test status
Simulation time 252278595849 ps
CPU time 319.2 seconds
Started Jul 21 04:24:00 PM PDT 24
Finished Jul 21 04:29:20 PM PDT 24
Peak memory 191488 kb
Host smart-2c677865-dd8c-4109-a88e-ad22b6f9c60f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260221717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.1260221717
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.2545058661
Short name T307
Test name
Test status
Simulation time 134940912927 ps
CPU time 1552.59 seconds
Started Jul 21 04:23:49 PM PDT 24
Finished Jul 21 04:49:43 PM PDT 24
Peak memory 190144 kb
Host smart-a14890ae-63fd-4293-8f63-78c0241670b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545058661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.2545058661
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.3397631068
Short name T242
Test name
Test status
Simulation time 645340460168 ps
CPU time 321.57 seconds
Started Jul 21 04:22:58 PM PDT 24
Finished Jul 21 04:28:20 PM PDT 24
Peak memory 183296 kb
Host smart-bee0acb3-9435-4af6-94a6-f1506e011001
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397631068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.3397631068
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.1064622284
Short name T402
Test name
Test status
Simulation time 106571416718 ps
CPU time 140.38 seconds
Started Jul 21 04:22:58 PM PDT 24
Finished Jul 21 04:25:19 PM PDT 24
Peak memory 183300 kb
Host smart-391912f5-2a7e-4783-a9fd-e83132ac9239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064622284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.1064622284
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.3382076482
Short name T447
Test name
Test status
Simulation time 297035335128 ps
CPU time 173.54 seconds
Started Jul 21 04:22:53 PM PDT 24
Finished Jul 21 04:25:49 PM PDT 24
Peak memory 183216 kb
Host smart-17f1ec97-ba3e-46ef-a6f1-b0b3a8ee99c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382076482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.3382076482
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all_with_rand_reset.2424885889
Short name T36
Test name
Test status
Simulation time 770656599509 ps
CPU time 1696.8 seconds
Started Jul 21 04:22:52 PM PDT 24
Finished Jul 21 04:51:11 PM PDT 24
Peak memory 214504 kb
Host smart-2462c09f-a22b-403e-b325-6116f8741836
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424885889 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all_with_rand_reset.2424885889
Directory /workspace/9.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.2887084562
Short name T132
Test name
Test status
Simulation time 412248939248 ps
CPU time 202.45 seconds
Started Jul 21 04:22:07 PM PDT 24
Finished Jul 21 04:25:30 PM PDT 24
Peak memory 191620 kb
Host smart-5e8c91ae-f2c0-4119-a9c3-a81100689485
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887084562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.2887084562
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.3805748145
Short name T248
Test name
Test status
Simulation time 91645551596 ps
CPU time 147.55 seconds
Started Jul 21 04:23:33 PM PDT 24
Finished Jul 21 04:26:01 PM PDT 24
Peak memory 191268 kb
Host smart-9f01597c-dbe1-44f6-bd33-612fa15bdd95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805748145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.3805748145
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.4079366459
Short name T410
Test name
Test status
Simulation time 179432224501 ps
CPU time 140.08 seconds
Started Jul 21 04:23:34 PM PDT 24
Finished Jul 21 04:25:55 PM PDT 24
Peak memory 191388 kb
Host smart-2e269771-3e18-44e5-86d2-75cef9a93d0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079366459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.4079366459
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.1157451409
Short name T259
Test name
Test status
Simulation time 92134676415 ps
CPU time 705.51 seconds
Started Jul 21 04:22:14 PM PDT 24
Finished Jul 21 04:34:00 PM PDT 24
Peak memory 191736 kb
Host smart-1277fca5-74a7-47c4-9f26-e92efa83728e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157451409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.1157451409
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.675884189
Short name T45
Test name
Test status
Simulation time 51640529215 ps
CPU time 79.12 seconds
Started Jul 21 04:23:25 PM PDT 24
Finished Jul 21 04:24:45 PM PDT 24
Peak memory 190196 kb
Host smart-8dc1d7b0-c6be-4980-b067-24c0f49a61ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675884189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.675884189
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.1234070199
Short name T196
Test name
Test status
Simulation time 69703057504 ps
CPU time 183.47 seconds
Started Jul 21 04:23:25 PM PDT 24
Finished Jul 21 04:26:29 PM PDT 24
Peak memory 190128 kb
Host smart-9ebd602d-90b5-4bd0-bff9-c1f289e1e550
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234070199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.1234070199
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.2800080807
Short name T313
Test name
Test status
Simulation time 398395162451 ps
CPU time 189.66 seconds
Started Jul 21 04:23:32 PM PDT 24
Finished Jul 21 04:26:42 PM PDT 24
Peak memory 193592 kb
Host smart-a6b812fe-486a-430a-8c0b-34f044d61997
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800080807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.2800080807
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.1796301744
Short name T291
Test name
Test status
Simulation time 118565798410 ps
CPU time 442.11 seconds
Started Jul 21 04:23:33 PM PDT 24
Finished Jul 21 04:30:56 PM PDT 24
Peak memory 191268 kb
Host smart-43432c4e-39ce-44cb-aea3-b21fdd832780
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796301744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.1796301744
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.1843081217
Short name T138
Test name
Test status
Simulation time 143958400924 ps
CPU time 323.34 seconds
Started Jul 21 04:22:21 PM PDT 24
Finished Jul 21 04:27:45 PM PDT 24
Peak memory 191736 kb
Host smart-a824d090-d87a-4b36-8c09-eb7969019406
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843081217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.1843081217
Directory /workspace/99.rv_timer_random/latest
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