Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.62 99.36 98.73 100.00 100.00 100.00 99.66


Total test records in report: 577
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T505 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.3610349992 Jul 22 06:17:58 PM PDT 24 Jul 22 06:17:59 PM PDT 24 81209683 ps
T506 /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.2103778225 Jul 22 06:18:27 PM PDT 24 Jul 22 06:18:28 PM PDT 24 37991714 ps
T507 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.1781799347 Jul 22 06:18:01 PM PDT 24 Jul 22 06:18:02 PM PDT 24 45602583 ps
T508 /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.3214145342 Jul 22 06:17:43 PM PDT 24 Jul 22 06:17:45 PM PDT 24 58348219 ps
T509 /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.1576023645 Jul 22 06:17:55 PM PDT 24 Jul 22 06:17:59 PM PDT 24 397923286 ps
T510 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2596827337 Jul 22 06:17:42 PM PDT 24 Jul 22 06:17:43 PM PDT 24 27299456 ps
T105 /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.3344222030 Jul 22 06:17:42 PM PDT 24 Jul 22 06:17:45 PM PDT 24 173764722 ps
T511 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.1196766408 Jul 22 06:17:42 PM PDT 24 Jul 22 06:17:44 PM PDT 24 23032019 ps
T512 /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.481770522 Jul 22 06:17:43 PM PDT 24 Jul 22 06:17:44 PM PDT 24 13827960 ps
T513 /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.454639306 Jul 22 06:18:55 PM PDT 24 Jul 22 06:18:56 PM PDT 24 12036970 ps
T514 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.2431210717 Jul 22 06:18:03 PM PDT 24 Jul 22 06:18:06 PM PDT 24 59196280 ps
T515 /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.3166839713 Jul 22 06:18:11 PM PDT 24 Jul 22 06:18:12 PM PDT 24 118070245 ps
T115 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2681148070 Jul 22 06:18:20 PM PDT 24 Jul 22 06:18:22 PM PDT 24 651460262 ps
T516 /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2125147925 Jul 22 06:18:25 PM PDT 24 Jul 22 06:18:26 PM PDT 24 24117384 ps
T517 /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.401822205 Jul 22 06:18:02 PM PDT 24 Jul 22 06:18:04 PM PDT 24 29894557 ps
T518 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.400027303 Jul 22 06:18:25 PM PDT 24 Jul 22 06:18:26 PM PDT 24 22387482 ps
T519 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.1232440908 Jul 22 06:18:01 PM PDT 24 Jul 22 06:18:03 PM PDT 24 41780479 ps
T520 /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.1714023296 Jul 22 06:18:55 PM PDT 24 Jul 22 06:18:57 PM PDT 24 230069247 ps
T521 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3092096895 Jul 22 06:17:54 PM PDT 24 Jul 22 06:17:55 PM PDT 24 13711475 ps
T522 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.641620948 Jul 22 06:17:57 PM PDT 24 Jul 22 06:17:59 PM PDT 24 146166264 ps
T106 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1812314659 Jul 22 06:17:43 PM PDT 24 Jul 22 06:17:44 PM PDT 24 11375574 ps
T523 /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.3773035896 Jul 22 06:18:03 PM PDT 24 Jul 22 06:18:06 PM PDT 24 13114665 ps
T524 /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.1865893003 Jul 22 06:18:02 PM PDT 24 Jul 22 06:18:05 PM PDT 24 96083987 ps
T525 /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.294746712 Jul 22 06:17:41 PM PDT 24 Jul 22 06:17:42 PM PDT 24 15982100 ps
T526 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.1981122021 Jul 22 06:17:58 PM PDT 24 Jul 22 06:17:59 PM PDT 24 42844447 ps
T527 /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.2231822934 Jul 22 06:17:55 PM PDT 24 Jul 22 06:17:57 PM PDT 24 20622335 ps
T528 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.2749495208 Jul 22 06:17:35 PM PDT 24 Jul 22 06:17:37 PM PDT 24 258354590 ps
T529 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.233345017 Jul 22 06:18:01 PM PDT 24 Jul 22 06:18:04 PM PDT 24 239342457 ps
T116 /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.688757133 Jul 22 06:17:54 PM PDT 24 Jul 22 06:17:56 PM PDT 24 463840422 ps
T530 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.818185872 Jul 22 06:17:53 PM PDT 24 Jul 22 06:17:55 PM PDT 24 22456477 ps
T531 /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.2357673707 Jul 22 06:17:56 PM PDT 24 Jul 22 06:17:57 PM PDT 24 12875055 ps
T532 /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.3666184096 Jul 22 06:18:02 PM PDT 24 Jul 22 06:18:04 PM PDT 24 38966448 ps
T533 /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3847192978 Jul 22 06:17:55 PM PDT 24 Jul 22 06:17:57 PM PDT 24 30310838 ps
T534 /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.294026436 Jul 22 06:17:34 PM PDT 24 Jul 22 06:17:38 PM PDT 24 235904068 ps
T535 /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.2488409802 Jul 22 06:17:45 PM PDT 24 Jul 22 06:17:46 PM PDT 24 18406854 ps
T536 /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.3584004730 Jul 22 06:17:59 PM PDT 24 Jul 22 06:18:00 PM PDT 24 15180674 ps
T537 /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.214314557 Jul 22 06:17:46 PM PDT 24 Jul 22 06:17:48 PM PDT 24 17971464 ps
T538 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.3318658875 Jul 22 06:18:02 PM PDT 24 Jul 22 06:18:05 PM PDT 24 68747075 ps
T539 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.33413347 Jul 22 06:17:36 PM PDT 24 Jul 22 06:17:37 PM PDT 24 19327289 ps
T540 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.3737502396 Jul 22 06:18:24 PM PDT 24 Jul 22 06:18:24 PM PDT 24 13673426 ps
T541 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.1467087735 Jul 22 06:18:03 PM PDT 24 Jul 22 06:18:05 PM PDT 24 23384916 ps
T542 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.97834054 Jul 22 06:17:34 PM PDT 24 Jul 22 06:17:36 PM PDT 24 59350878 ps
T543 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.4085858637 Jul 22 06:17:36 PM PDT 24 Jul 22 06:17:38 PM PDT 24 30211521 ps
T544 /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.2766620568 Jul 22 06:17:43 PM PDT 24 Jul 22 06:17:45 PM PDT 24 213574443 ps
T545 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1422109517 Jul 22 06:18:28 PM PDT 24 Jul 22 06:18:29 PM PDT 24 35485878 ps
T546 /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.4269643855 Jul 22 06:17:36 PM PDT 24 Jul 22 06:17:39 PM PDT 24 117986432 ps
T547 /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.850047139 Jul 22 06:18:01 PM PDT 24 Jul 22 06:18:05 PM PDT 24 76333576 ps
T548 /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.767911173 Jul 22 06:17:44 PM PDT 24 Jul 22 06:17:45 PM PDT 24 119829715 ps
T549 /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.4120291153 Jul 22 06:17:56 PM PDT 24 Jul 22 06:17:59 PM PDT 24 534743718 ps
T550 /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.3989906430 Jul 22 06:17:56 PM PDT 24 Jul 22 06:17:58 PM PDT 24 32476027 ps
T551 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.923803305 Jul 22 06:17:46 PM PDT 24 Jul 22 06:17:47 PM PDT 24 12426570 ps
T552 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.3465623142 Jul 22 06:17:58 PM PDT 24 Jul 22 06:17:59 PM PDT 24 155524314 ps
T553 /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.1554145482 Jul 22 06:17:42 PM PDT 24 Jul 22 06:17:43 PM PDT 24 13034350 ps
T554 /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.173441869 Jul 22 06:18:02 PM PDT 24 Jul 22 06:18:05 PM PDT 24 327448681 ps
T555 /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.446567664 Jul 22 06:18:00 PM PDT 24 Jul 22 06:18:03 PM PDT 24 92547102 ps
T556 /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.3895525103 Jul 22 06:18:00 PM PDT 24 Jul 22 06:18:04 PM PDT 24 254618412 ps
T557 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.1284865743 Jul 22 06:18:01 PM PDT 24 Jul 22 06:18:03 PM PDT 24 21345249 ps
T558 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.2071890919 Jul 22 06:17:56 PM PDT 24 Jul 22 06:17:57 PM PDT 24 13490376 ps
T559 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2919080162 Jul 22 06:18:01 PM PDT 24 Jul 22 06:18:03 PM PDT 24 14971651 ps
T560 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.2145358135 Jul 22 06:18:44 PM PDT 24 Jul 22 06:18:46 PM PDT 24 426746060 ps
T561 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.2469494844 Jul 22 06:18:03 PM PDT 24 Jul 22 06:18:06 PM PDT 24 49582500 ps
T562 /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.1241100933 Jul 22 06:18:02 PM PDT 24 Jul 22 06:18:05 PM PDT 24 34868580 ps
T563 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.471745492 Jul 22 06:17:55 PM PDT 24 Jul 22 06:17:56 PM PDT 24 80155484 ps
T564 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.3702697127 Jul 22 06:17:59 PM PDT 24 Jul 22 06:18:00 PM PDT 24 76021235 ps
T565 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.523727666 Jul 22 06:17:57 PM PDT 24 Jul 22 06:17:59 PM PDT 24 171994167 ps
T566 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1449423427 Jul 22 06:17:45 PM PDT 24 Jul 22 06:17:48 PM PDT 24 59666785 ps
T567 /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.3614292362 Jul 22 06:17:56 PM PDT 24 Jul 22 06:17:58 PM PDT 24 22027505 ps
T568 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3333412773 Jul 22 06:17:45 PM PDT 24 Jul 22 06:17:46 PM PDT 24 41788407 ps
T569 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.3748884469 Jul 22 06:18:02 PM PDT 24 Jul 22 06:18:05 PM PDT 24 14245200 ps
T570 /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.3868107367 Jul 22 06:18:02 PM PDT 24 Jul 22 06:18:04 PM PDT 24 10881703 ps
T571 /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.4025427592 Jul 22 06:18:55 PM PDT 24 Jul 22 06:18:56 PM PDT 24 14207671 ps
T572 /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.435057092 Jul 22 06:18:19 PM PDT 24 Jul 22 06:18:20 PM PDT 24 132548383 ps
T573 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.2424780313 Jul 22 06:18:04 PM PDT 24 Jul 22 06:18:06 PM PDT 24 131184163 ps
T574 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1128134368 Jul 22 06:18:03 PM PDT 24 Jul 22 06:18:06 PM PDT 24 21061850 ps
T575 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.392433252 Jul 22 06:17:55 PM PDT 24 Jul 22 06:17:56 PM PDT 24 113809436 ps
T576 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.1535855661 Jul 22 06:18:02 PM PDT 24 Jul 22 06:18:04 PM PDT 24 17001601 ps
T577 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.2128624820 Jul 22 06:17:54 PM PDT 24 Jul 22 06:17:56 PM PDT 24 95548107 ps

Test location /workspace/coverage/default/41.rv_timer_random.1227164833
Short name T8
Test name
Test status
Simulation time 17605960653 ps
CPU time 90.27 seconds
Started Jul 22 07:00:20 PM PDT 24
Finished Jul 22 07:02:06 PM PDT 24
Peak memory 183660 kb
Host smart-cbb74132-e678-4f4f-9015-83c77188987e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227164833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.1227164833
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all_with_rand_reset.4229181312
Short name T12
Test name
Test status
Simulation time 127706011658 ps
CPU time 1010.2 seconds
Started Jul 22 07:00:16 PM PDT 24
Finished Jul 22 07:17:22 PM PDT 24
Peak memory 206516 kb
Host smart-eb58c661-9afb-44e7-b238-8d2fed75b4be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229181312 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all_with_rand_reset.4229181312
Directory /workspace/33.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.1652586725
Short name T11
Test name
Test status
Simulation time 658919209935 ps
CPU time 2316.57 seconds
Started Jul 22 07:00:21 PM PDT 24
Finished Jul 22 07:39:14 PM PDT 24
Peak memory 191780 kb
Host smart-a6800b0f-6f20-4702-a0fa-8a3c0521a4b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652586725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.1652586725
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.3427219571
Short name T125
Test name
Test status
Simulation time 6149083467205 ps
CPU time 5557.29 seconds
Started Jul 22 06:59:35 PM PDT 24
Finished Jul 22 08:32:30 PM PDT 24
Peak memory 191748 kb
Host smart-940f050a-7b9e-407e-8e70-1a9a2b37a693
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427219571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
3427219571
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.2717934587
Short name T28
Test name
Test status
Simulation time 77525628 ps
CPU time 1.11 seconds
Started Jul 22 06:17:44 PM PDT 24
Finished Jul 22 06:17:45 PM PDT 24
Peak memory 194652 kb
Host smart-8ed3894f-a1d2-407d-b7e8-81dc9c8d877c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717934587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.2717934587
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.3670164096
Short name T22
Test name
Test status
Simulation time 2109723823324 ps
CPU time 2189.6 seconds
Started Jul 22 06:59:37 PM PDT 24
Finished Jul 22 07:36:23 PM PDT 24
Peak memory 196536 kb
Host smart-1e559ed1-da9c-41c7-a1cf-ab697dea22e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670164096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
3670164096
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.4141136679
Short name T210
Test name
Test status
Simulation time 1321300392062 ps
CPU time 2934.37 seconds
Started Jul 22 07:00:09 PM PDT 24
Finished Jul 22 07:49:17 PM PDT 24
Peak memory 191752 kb
Host smart-c5ce6511-e7f6-47c1-bac1-b5c05435dbac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141136679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.4141136679
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.1291663698
Short name T63
Test name
Test status
Simulation time 3691659185535 ps
CPU time 980.46 seconds
Started Jul 22 07:00:00 PM PDT 24
Finished Jul 22 07:16:29 PM PDT 24
Peak memory 191816 kb
Host smart-a3fef56a-0888-4334-95a7-f81cf33657b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291663698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.1291663698
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.768598799
Short name T50
Test name
Test status
Simulation time 63335287 ps
CPU time 0.82 seconds
Started Jul 22 06:17:43 PM PDT 24
Finished Jul 22 06:17:44 PM PDT 24
Peak memory 192648 kb
Host smart-18ae26a6-83e6-41fe-a23a-c7e6589e5c4b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768598799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alias
ing.768598799
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.968175136
Short name T267
Test name
Test status
Simulation time 2010827719248 ps
CPU time 1388.66 seconds
Started Jul 22 07:00:12 PM PDT 24
Finished Jul 22 07:23:35 PM PDT 24
Peak memory 191776 kb
Host smart-75b46cbe-fd6a-4a33-93f8-8758675f5c24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968175136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all.
968175136
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.2320622850
Short name T69
Test name
Test status
Simulation time 557921464355 ps
CPU time 1305.68 seconds
Started Jul 22 07:00:08 PM PDT 24
Finished Jul 22 07:22:07 PM PDT 24
Peak memory 191840 kb
Host smart-4ab6de35-b96b-4842-b559-2187273f0f05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320622850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.2320622850
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.1829054599
Short name T213
Test name
Test status
Simulation time 812372841352 ps
CPU time 1199.12 seconds
Started Jul 22 07:00:23 PM PDT 24
Finished Jul 22 07:20:38 PM PDT 24
Peak memory 195788 kb
Host smart-670032c9-afae-4223-8d6c-8358abf7244a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829054599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.1829054599
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.51243995
Short name T241
Test name
Test status
Simulation time 3077452648789 ps
CPU time 2502.55 seconds
Started Jul 22 07:01:57 PM PDT 24
Finished Jul 22 07:43:42 PM PDT 24
Peak memory 195936 kb
Host smart-59002e71-27b6-4271-be06-709e70cc6014
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51243995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all.51243995
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.940448208
Short name T24
Test name
Test status
Simulation time 1797277134146 ps
CPU time 2430.34 seconds
Started Jul 22 06:59:50 PM PDT 24
Finished Jul 22 07:40:32 PM PDT 24
Peak memory 191796 kb
Host smart-d62492a1-e58f-4a08-a288-e78f2cdf1346
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940448208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all.
940448208
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.674316309
Short name T308
Test name
Test status
Simulation time 2119140602290 ps
CPU time 1774.07 seconds
Started Jul 22 06:59:47 PM PDT 24
Finished Jul 22 07:29:33 PM PDT 24
Peak memory 191808 kb
Host smart-70051f54-3ac9-4724-ac47-02fcf2f0b020
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674316309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all.
674316309
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.1821051890
Short name T209
Test name
Test status
Simulation time 1370313012612 ps
CPU time 1254.18 seconds
Started Jul 22 06:59:33 PM PDT 24
Finished Jul 22 07:20:44 PM PDT 24
Peak memory 191780 kb
Host smart-7cf305be-7720-4ae3-9e3f-1bdbd64e139b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821051890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
1821051890
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.2326655798
Short name T18
Test name
Test status
Simulation time 356819390 ps
CPU time 0.84 seconds
Started Jul 22 06:59:29 PM PDT 24
Finished Jul 22 06:59:46 PM PDT 24
Peak memory 214504 kb
Host smart-9baed4f5-8923-43e5-8efb-a955b54c03e1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326655798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.2326655798
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.213409543
Short name T156
Test name
Test status
Simulation time 600558454123 ps
CPU time 3486.6 seconds
Started Jul 22 07:00:22 PM PDT 24
Finished Jul 22 07:58:45 PM PDT 24
Peak memory 191816 kb
Host smart-343b2572-4016-4369-baed-6254a04ba470
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213409543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all.
213409543
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.4174091614
Short name T68
Test name
Test status
Simulation time 1083025674114 ps
CPU time 671.16 seconds
Started Jul 22 07:00:29 PM PDT 24
Finished Jul 22 07:11:54 PM PDT 24
Peak memory 191784 kb
Host smart-e42ef82a-4882-4475-881c-a052d81543ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174091614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.4174091614
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.3776015695
Short name T254
Test name
Test status
Simulation time 1782404768424 ps
CPU time 2660.85 seconds
Started Jul 22 07:00:11 PM PDT 24
Finished Jul 22 07:44:47 PM PDT 24
Peak memory 191784 kb
Host smart-6da7c422-0e3c-49e3-8ea9-c7bb9f8506fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776015695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.3776015695
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/110.rv_timer_random.821508947
Short name T77
Test name
Test status
Simulation time 584373030355 ps
CPU time 1143.93 seconds
Started Jul 22 07:00:52 PM PDT 24
Finished Jul 22 07:20:02 PM PDT 24
Peak memory 191720 kb
Host smart-ac953d14-2d72-459b-b019-82d6c1ad8bbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821508947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.821508947
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.825402555
Short name T91
Test name
Test status
Simulation time 542288804452 ps
CPU time 760.35 seconds
Started Jul 22 07:01:56 PM PDT 24
Finished Jul 22 07:14:39 PM PDT 24
Peak memory 191840 kb
Host smart-41ba099a-c5e5-4032-95d9-4bfb6a1f94cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825402555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.825402555
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.1543101398
Short name T123
Test name
Test status
Simulation time 164755024572 ps
CPU time 249.49 seconds
Started Jul 22 07:01:26 PM PDT 24
Finished Jul 22 07:05:39 PM PDT 24
Peak memory 195264 kb
Host smart-10fb6852-9fb2-4928-ac55-a2602e0071f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543101398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.1543101398
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.310309974
Short name T293
Test name
Test status
Simulation time 1234526177986 ps
CPU time 1077.06 seconds
Started Jul 22 07:00:02 PM PDT 24
Finished Jul 22 07:18:08 PM PDT 24
Peak memory 183548 kb
Host smart-661c2733-906a-4653-a91d-7fe2991abb56
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310309974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.rv_timer_cfg_update_on_fly.310309974
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_random.2254049389
Short name T172
Test name
Test status
Simulation time 125650063645 ps
CPU time 230.77 seconds
Started Jul 22 07:00:11 PM PDT 24
Finished Jul 22 07:04:16 PM PDT 24
Peak memory 191832 kb
Host smart-94eb17f7-4f7b-43c0-bdfe-9258c240d875
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254049389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.2254049389
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.3848712238
Short name T228
Test name
Test status
Simulation time 379450354527 ps
CPU time 505.2 seconds
Started Jul 22 07:01:21 PM PDT 24
Finished Jul 22 07:09:48 PM PDT 24
Peak memory 191836 kb
Host smart-f0d3a626-2101-4d2b-8b8a-25726c6ebb2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848712238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.3848712238
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.1381408901
Short name T87
Test name
Test status
Simulation time 118552241810 ps
CPU time 198.58 seconds
Started Jul 22 07:01:25 PM PDT 24
Finished Jul 22 07:04:47 PM PDT 24
Peak memory 195196 kb
Host smart-da433566-22a0-4006-b461-302cf8e5a4db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381408901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.1381408901
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.1739125264
Short name T185
Test name
Test status
Simulation time 198724463758 ps
CPU time 652.88 seconds
Started Jul 22 07:03:57 PM PDT 24
Finished Jul 22 07:14:53 PM PDT 24
Peak memory 191788 kb
Host smart-04574db4-f58e-4e52-abd9-5aa49a84dd17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739125264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.1739125264
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.1671934153
Short name T59
Test name
Test status
Simulation time 1095364992267 ps
CPU time 543.57 seconds
Started Jul 22 07:00:02 PM PDT 24
Finished Jul 22 07:09:15 PM PDT 24
Peak memory 183536 kb
Host smart-b9bc092e-5151-4702-96b0-cbf22eeb0e19
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671934153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.1671934153
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.3140948807
Short name T184
Test name
Test status
Simulation time 2063155375281 ps
CPU time 1739.92 seconds
Started Jul 22 06:59:51 PM PDT 24
Finished Jul 22 07:29:02 PM PDT 24
Peak memory 191728 kb
Host smart-548498b5-8617-4102-8967-c8865b9c4646
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140948807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.3140948807
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/137.rv_timer_random.166368403
Short name T163
Test name
Test status
Simulation time 572491329867 ps
CPU time 236.33 seconds
Started Jul 22 07:01:12 PM PDT 24
Finished Jul 22 07:05:12 PM PDT 24
Peak memory 191832 kb
Host smart-91f2655e-84b2-4e0b-a19d-1c19719bdf96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166368403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.166368403
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.919516112
Short name T319
Test name
Test status
Simulation time 270548591589 ps
CPU time 371.34 seconds
Started Jul 22 07:01:36 PM PDT 24
Finished Jul 22 07:07:50 PM PDT 24
Peak memory 195416 kb
Host smart-62160c45-ed09-4a84-a9c4-db065590d24a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919516112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.919516112
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random.3905499899
Short name T335
Test name
Test status
Simulation time 617570805072 ps
CPU time 201.65 seconds
Started Jul 22 06:59:32 PM PDT 24
Finished Jul 22 07:03:10 PM PDT 24
Peak memory 191784 kb
Host smart-43f3182d-22dd-4e1f-a457-eddd94d48853
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905499899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.3905499899
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.749123967
Short name T169
Test name
Test status
Simulation time 1074297468816 ps
CPU time 1711.89 seconds
Started Jul 22 07:00:57 PM PDT 24
Finished Jul 22 07:29:33 PM PDT 24
Peak memory 191788 kb
Host smart-1bfc51fa-3081-44bb-9283-7ca2f10cfe5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749123967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all.
749123967
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_random.1566086114
Short name T119
Test name
Test status
Simulation time 1825311563159 ps
CPU time 421.34 seconds
Started Jul 22 07:00:32 PM PDT 24
Finished Jul 22 07:07:47 PM PDT 24
Peak memory 191792 kb
Host smart-c5966d59-2821-42a1-b5ae-065ba5f51f2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566086114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.1566086114
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.664089524
Short name T226
Test name
Test status
Simulation time 71399327908 ps
CPU time 216.77 seconds
Started Jul 22 07:00:43 PM PDT 24
Finished Jul 22 07:04:29 PM PDT 24
Peak memory 191780 kb
Host smart-9e3ae487-5f94-49fb-8e54-38d19851fd0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664089524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.664089524
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.1237118336
Short name T100
Test name
Test status
Simulation time 148375140927 ps
CPU time 528.96 seconds
Started Jul 22 07:00:53 PM PDT 24
Finished Jul 22 07:09:47 PM PDT 24
Peak memory 191784 kb
Host smart-75d908b3-35b2-4f99-be1a-6aeb4cf3b599
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237118336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.1237118336
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.2569063866
Short name T27
Test name
Test status
Simulation time 663725744468 ps
CPU time 200.38 seconds
Started Jul 22 06:59:49 PM PDT 24
Finished Jul 22 07:03:21 PM PDT 24
Peak memory 196308 kb
Host smart-0c58c424-d242-418b-a542-0f59c00a8dbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569063866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.2569063866
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.3627539682
Short name T175
Test name
Test status
Simulation time 1910080725857 ps
CPU time 1088.4 seconds
Started Jul 22 06:59:36 PM PDT 24
Finished Jul 22 07:18:01 PM PDT 24
Peak memory 191772 kb
Host smart-49775dce-4212-46df-8303-27c3baa05dda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627539682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
3627539682
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/80.rv_timer_random.3237440380
Short name T188
Test name
Test status
Simulation time 606844972850 ps
CPU time 340.1 seconds
Started Jul 22 07:00:42 PM PDT 24
Finished Jul 22 07:06:32 PM PDT 24
Peak memory 191768 kb
Host smart-9b900bbd-ec98-41fc-a28f-dbb1f4a653c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237440380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.3237440380
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random.2478406289
Short name T160
Test name
Test status
Simulation time 184823269412 ps
CPU time 347.62 seconds
Started Jul 22 06:59:30 PM PDT 24
Finished Jul 22 07:05:34 PM PDT 24
Peak memory 191764 kb
Host smart-d8940196-711f-450a-9408-ae45da3cd9c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478406289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.2478406289
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.4242518092
Short name T104
Test name
Test status
Simulation time 169982226792 ps
CPU time 255.53 seconds
Started Jul 22 07:02:47 PM PDT 24
Finished Jul 22 07:07:04 PM PDT 24
Peak memory 191784 kb
Host smart-f4a92773-1d47-4fb6-bbdc-85769ad86283
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242518092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.4242518092
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.3163621534
Short name T230
Test name
Test status
Simulation time 251502619812 ps
CPU time 237.21 seconds
Started Jul 22 07:01:56 PM PDT 24
Finished Jul 22 07:05:56 PM PDT 24
Peak memory 191788 kb
Host smart-5696310f-acaf-4890-b3e5-4428fd6c6595
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163621534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.3163621534
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random.651773766
Short name T131
Test name
Test status
Simulation time 315726207646 ps
CPU time 3044.7 seconds
Started Jul 22 07:00:07 PM PDT 24
Finished Jul 22 07:51:04 PM PDT 24
Peak memory 191748 kb
Host smart-d6a9e13d-5a08-4387-abb9-7f613d875080
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651773766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.651773766
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.1196444247
Short name T126
Test name
Test status
Simulation time 163567422677 ps
CPU time 81.25 seconds
Started Jul 22 06:59:33 PM PDT 24
Finished Jul 22 07:01:11 PM PDT 24
Peak memory 191728 kb
Host smart-37e772cf-5111-4b0e-8697-996a93d37a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196444247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.1196444247
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/53.rv_timer_random.829276039
Short name T141
Test name
Test status
Simulation time 581084811243 ps
CPU time 559.1 seconds
Started Jul 22 07:02:16 PM PDT 24
Finished Jul 22 07:11:38 PM PDT 24
Peak memory 191720 kb
Host smart-7b267b6b-660b-4e64-a213-501e6e2f9d06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829276039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.829276039
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.2585678756
Short name T271
Test name
Test status
Simulation time 286660344607 ps
CPU time 889.73 seconds
Started Jul 22 07:00:43 PM PDT 24
Finished Jul 22 07:15:42 PM PDT 24
Peak memory 191776 kb
Host smart-becf5f01-9643-4b5d-ba87-1debf33e93d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585678756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.2585678756
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.335825733
Short name T109
Test name
Test status
Simulation time 19335606 ps
CPU time 0.6 seconds
Started Jul 22 06:17:35 PM PDT 24
Finished Jul 22 06:17:37 PM PDT 24
Peak memory 191088 kb
Host smart-389e9106-9d5c-41b4-9946-f415f7b0631f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335825733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_tim
er_same_csr_outstanding.335825733
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/106.rv_timer_random.2587537289
Short name T206
Test name
Test status
Simulation time 552992402559 ps
CPU time 255.41 seconds
Started Jul 22 07:01:35 PM PDT 24
Finished Jul 22 07:05:54 PM PDT 24
Peak memory 191800 kb
Host smart-18521a13-a5fc-4c88-92d5-b2168485ddbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587537289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.2587537289
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random.674105524
Short name T191
Test name
Test status
Simulation time 625807943594 ps
CPU time 2830.13 seconds
Started Jul 22 06:59:47 PM PDT 24
Finished Jul 22 07:47:09 PM PDT 24
Peak memory 191708 kb
Host smart-7c6f02c0-ddc3-42a8-ab61-cce8af4cf86a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674105524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.674105524
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.3754466305
Short name T99
Test name
Test status
Simulation time 897763574207 ps
CPU time 1389.47 seconds
Started Jul 22 07:00:58 PM PDT 24
Finished Jul 22 07:24:12 PM PDT 24
Peak memory 191780 kb
Host smart-8399de5e-bea8-4962-bab3-8d35b5731dfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754466305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.3754466305
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.697119424
Short name T55
Test name
Test status
Simulation time 218702200924 ps
CPU time 117.65 seconds
Started Jul 22 06:59:50 PM PDT 24
Finished Jul 22 07:01:59 PM PDT 24
Peak memory 183536 kb
Host smart-fe6fc941-185d-4c2e-ad45-675769c9b6c8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697119424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.rv_timer_cfg_update_on_fly.697119424
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/131.rv_timer_random.240618402
Short name T273
Test name
Test status
Simulation time 44288205233 ps
CPU time 237.74 seconds
Started Jul 22 07:01:10 PM PDT 24
Finished Jul 22 07:05:11 PM PDT 24
Peak memory 183580 kb
Host smart-2c5a2ca1-38e5-461d-b9b8-6746d69ab8b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240618402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.240618402
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.734990006
Short name T238
Test name
Test status
Simulation time 476212738482 ps
CPU time 537.61 seconds
Started Jul 22 07:01:12 PM PDT 24
Finished Jul 22 07:10:13 PM PDT 24
Peak memory 191812 kb
Host smart-5bf4d272-9bd2-4d5f-9363-5d91af132184
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734990006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.734990006
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.632918681
Short name T248
Test name
Test status
Simulation time 183087061633 ps
CPU time 116.2 seconds
Started Jul 22 07:01:25 PM PDT 24
Finished Jul 22 07:03:25 PM PDT 24
Peak memory 191732 kb
Host smart-85066311-8955-4a11-a1d5-86ac6a83a61d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632918681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.632918681
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/160.rv_timer_random.3445997219
Short name T164
Test name
Test status
Simulation time 231138131419 ps
CPU time 124.65 seconds
Started Jul 22 07:02:45 PM PDT 24
Finished Jul 22 07:04:51 PM PDT 24
Peak memory 191784 kb
Host smart-c25ed431-af6a-42a8-a541-52587dfb5f57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445997219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.3445997219
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/180.rv_timer_random.1579668977
Short name T315
Test name
Test status
Simulation time 40757796200 ps
CPU time 347.72 seconds
Started Jul 22 07:01:37 PM PDT 24
Finished Jul 22 07:07:27 PM PDT 24
Peak memory 191768 kb
Host smart-9d1f00b7-ebbb-435e-90ce-d3cf6aef7977
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579668977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.1579668977
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.1043177279
Short name T314
Test name
Test status
Simulation time 218939432980 ps
CPU time 93.53 seconds
Started Jul 22 07:01:36 PM PDT 24
Finished Jul 22 07:03:12 PM PDT 24
Peak memory 183572 kb
Host smart-4ae322eb-46fd-45a8-b209-a76702b49dfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043177279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.1043177279
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.1778949515
Short name T296
Test name
Test status
Simulation time 572422993522 ps
CPU time 536.58 seconds
Started Jul 22 07:01:36 PM PDT 24
Finished Jul 22 07:10:35 PM PDT 24
Peak memory 191836 kb
Host smart-4376f03b-8cf6-46a8-b2db-dacfaf667d4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778949515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.1778949515
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.3671912016
Short name T298
Test name
Test status
Simulation time 41504119443 ps
CPU time 289.34 seconds
Started Jul 22 07:00:00 PM PDT 24
Finished Jul 22 07:04:58 PM PDT 24
Peak memory 183608 kb
Host smart-944e1bb3-5110-48a9-8204-84198a523f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671912016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.3671912016
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.457223085
Short name T65
Test name
Test status
Simulation time 354814354969 ps
CPU time 315.03 seconds
Started Jul 22 07:00:19 PM PDT 24
Finished Jul 22 07:05:50 PM PDT 24
Peak memory 191736 kb
Host smart-ce752009-e814-4b64-a8c8-7801abd27de5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457223085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.
457223085
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.101175737
Short name T306
Test name
Test status
Simulation time 206889674804 ps
CPU time 278.52 seconds
Started Jul 22 07:00:21 PM PDT 24
Finished Jul 22 07:05:15 PM PDT 24
Peak memory 191772 kb
Host smart-0f0c22a4-90f1-4f73-98ee-bd1511c30abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101175737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.101175737
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_random.3366165691
Short name T265
Test name
Test status
Simulation time 106710012213 ps
CPU time 163.94 seconds
Started Jul 22 07:00:21 PM PDT 24
Finished Jul 22 07:03:22 PM PDT 24
Peak memory 192976 kb
Host smart-160fdbe0-0fe0-4e67-b2f9-b8ba68f2a427
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366165691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.3366165691
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.1751359876
Short name T197
Test name
Test status
Simulation time 1444791651800 ps
CPU time 901.61 seconds
Started Jul 22 07:00:35 PM PDT 24
Finished Jul 22 07:15:50 PM PDT 24
Peak memory 191804 kb
Host smart-9bab0003-d58b-49af-904d-53d09d26d86d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751359876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.1751359876
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/50.rv_timer_random.1001725257
Short name T252
Test name
Test status
Simulation time 155897415447 ps
CPU time 2614.85 seconds
Started Jul 22 07:00:30 PM PDT 24
Finished Jul 22 07:44:19 PM PDT 24
Peak memory 191776 kb
Host smart-8bb5d3ba-5f22-42f6-bdaf-85121bbc9e02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001725257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.1001725257
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.2145358135
Short name T560
Test name
Test status
Simulation time 426746060 ps
CPU time 1.11 seconds
Started Jul 22 06:18:44 PM PDT 24
Finished Jul 22 06:18:46 PM PDT 24
Peak memory 182852 kb
Host smart-128883cd-7968-4618-a07e-787f18c13f8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145358135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.2145358135
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/109.rv_timer_random.4219493448
Short name T2
Test name
Test status
Simulation time 1966882124209 ps
CPU time 390.12 seconds
Started Jul 22 07:01:21 PM PDT 24
Finished Jul 22 07:07:53 PM PDT 24
Peak memory 191844 kb
Host smart-9c8a4061-f192-4211-ac15-9ec6601cc70c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219493448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.4219493448
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.3091906888
Short name T170
Test name
Test status
Simulation time 76144729267 ps
CPU time 271.08 seconds
Started Jul 22 07:00:54 PM PDT 24
Finished Jul 22 07:05:29 PM PDT 24
Peak memory 191700 kb
Host smart-eea0ff92-fdc8-42be-9657-54a520a5723a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091906888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.3091906888
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/120.rv_timer_random.1693910644
Short name T150
Test name
Test status
Simulation time 196015352207 ps
CPU time 108.83 seconds
Started Jul 22 07:00:54 PM PDT 24
Finished Jul 22 07:02:47 PM PDT 24
Peak memory 183588 kb
Host smart-b2a42c96-9f89-4c52-a758-cdd71d3d666f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693910644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.1693910644
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.458335918
Short name T236
Test name
Test status
Simulation time 112308301172 ps
CPU time 151.56 seconds
Started Jul 22 07:01:13 PM PDT 24
Finished Jul 22 07:03:48 PM PDT 24
Peak memory 194124 kb
Host smart-8a77da06-653f-4450-a0ba-4cc131f1555d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458335918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.458335918
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/140.rv_timer_random.2396951739
Short name T357
Test name
Test status
Simulation time 190413600563 ps
CPU time 551.89 seconds
Started Jul 22 07:01:11 PM PDT 24
Finished Jul 22 07:10:27 PM PDT 24
Peak memory 191772 kb
Host smart-56d6ca40-ea4d-4270-831c-7d626a44520f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396951739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.2396951739
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.2615578305
Short name T118
Test name
Test status
Simulation time 467004741272 ps
CPU time 1513.94 seconds
Started Jul 22 07:01:11 PM PDT 24
Finished Jul 22 07:26:29 PM PDT 24
Peak memory 191848 kb
Host smart-36ddf2bd-b475-4b13-8e51-1b619d061b17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615578305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.2615578305
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.355750530
Short name T260
Test name
Test status
Simulation time 347454037125 ps
CPU time 227.12 seconds
Started Jul 22 07:01:23 PM PDT 24
Finished Jul 22 07:05:14 PM PDT 24
Peak memory 191756 kb
Host smart-930e8b8c-e57c-4d9a-8e0c-efc232605bc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355750530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.355750530
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.3233961915
Short name T84
Test name
Test status
Simulation time 901920600528 ps
CPU time 872.95 seconds
Started Jul 22 06:59:59 PM PDT 24
Finished Jul 22 07:14:41 PM PDT 24
Peak memory 183552 kb
Host smart-def7e7ec-ba8b-4ce1-9984-6276c15b204c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233961915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.3233961915
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/154.rv_timer_random.1938630010
Short name T318
Test name
Test status
Simulation time 215049369289 ps
CPU time 95.06 seconds
Started Jul 22 07:02:47 PM PDT 24
Finished Jul 22 07:04:23 PM PDT 24
Peak memory 191784 kb
Host smart-8fc98874-c3cb-450e-80a9-e62fcccfa060
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938630010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.1938630010
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.2161362101
Short name T214
Test name
Test status
Simulation time 154080267991 ps
CPU time 265.23 seconds
Started Jul 22 06:59:51 PM PDT 24
Finished Jul 22 07:04:28 PM PDT 24
Peak memory 183516 kb
Host smart-e245e59d-b57f-4796-94b2-09f668b36299
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161362101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.2161362101
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_random.1715308227
Short name T165
Test name
Test status
Simulation time 1018994964859 ps
CPU time 522.55 seconds
Started Jul 22 06:59:54 PM PDT 24
Finished Jul 22 07:08:47 PM PDT 24
Peak memory 191852 kb
Host smart-7c7696da-1c92-47c0-8525-80dadb0c4e35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715308227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.1715308227
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.3265381034
Short name T158
Test name
Test status
Simulation time 87285521402 ps
CPU time 84.7 seconds
Started Jul 22 07:01:30 PM PDT 24
Finished Jul 22 07:02:57 PM PDT 24
Peak memory 183584 kb
Host smart-76af2c97-8b5a-4f34-bdb4-0d25ff6c33da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265381034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.3265381034
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random.650686114
Short name T327
Test name
Test status
Simulation time 113070031169 ps
CPU time 120.81 seconds
Started Jul 22 07:00:02 PM PDT 24
Finished Jul 22 07:02:11 PM PDT 24
Peak memory 191740 kb
Host smart-907f2e7f-36b6-4dd2-8e32-3fc8dc066494
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650686114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.650686114
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.3120846868
Short name T279
Test name
Test status
Simulation time 2492117518437 ps
CPU time 1048.9 seconds
Started Jul 22 06:59:58 PM PDT 24
Finished Jul 22 07:17:36 PM PDT 24
Peak memory 191780 kb
Host smart-786704a2-ebd7-4bd8-abf3-46c099b675f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120846868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.3120846868
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/181.rv_timer_random.1075686689
Short name T239
Test name
Test status
Simulation time 101293627681 ps
CPU time 171.11 seconds
Started Jul 22 07:01:35 PM PDT 24
Finished Jul 22 07:04:29 PM PDT 24
Peak memory 191792 kb
Host smart-1b899f16-5374-40f1-98be-3bd2ac39b370
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075686689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.1075686689
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random.3180540043
Short name T347
Test name
Test status
Simulation time 250672106983 ps
CPU time 109.51 seconds
Started Jul 22 06:59:34 PM PDT 24
Finished Jul 22 07:01:40 PM PDT 24
Peak memory 194216 kb
Host smart-3df5296a-2518-4a8d-8292-82a6daf5d92a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180540043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.3180540043
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.3168874625
Short name T295
Test name
Test status
Simulation time 1538760177757 ps
CPU time 2333.02 seconds
Started Jul 22 07:00:07 PM PDT 24
Finished Jul 22 07:39:12 PM PDT 24
Peak memory 191796 kb
Host smart-56d18da6-99d6-4e7b-8c86-2d1b0bfe1f2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168874625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.3168874625
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_random.92302468
Short name T244
Test name
Test status
Simulation time 928193882086 ps
CPU time 358.96 seconds
Started Jul 22 06:59:58 PM PDT 24
Finished Jul 22 07:06:06 PM PDT 24
Peak memory 191784 kb
Host smart-1d7cef75-c281-43f5-b270-2fad78be8209
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92302468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.92302468
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.2491734564
Short name T33
Test name
Test status
Simulation time 158901258425 ps
CPU time 239.71 seconds
Started Jul 22 07:00:00 PM PDT 24
Finished Jul 22 07:04:08 PM PDT 24
Peak memory 191784 kb
Host smart-03a57e3d-4958-41b6-8f5a-c5804cb0d674
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491734564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.2491734564
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_random.229542813
Short name T20
Test name
Test status
Simulation time 203376786885 ps
CPU time 181.39 seconds
Started Jul 22 07:00:07 PM PDT 24
Finished Jul 22 07:03:21 PM PDT 24
Peak memory 191784 kb
Host smart-6c14695c-ac9c-48e4-b1da-e208370b28d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229542813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.229542813
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.3826677151
Short name T149
Test name
Test status
Simulation time 2442827883046 ps
CPU time 1620.89 seconds
Started Jul 22 07:00:04 PM PDT 24
Finished Jul 22 07:27:14 PM PDT 24
Peak memory 191792 kb
Host smart-e7047b3b-5456-4479-b3fc-12d639b7cb9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826677151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.3826677151
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.599927631
Short name T325
Test name
Test status
Simulation time 515238969402 ps
CPU time 427.11 seconds
Started Jul 22 07:00:18 PM PDT 24
Finished Jul 22 07:07:41 PM PDT 24
Peak memory 183540 kb
Host smart-a29a42c4-ea67-4764-b578-d7740008e028
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599927631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.rv_timer_cfg_update_on_fly.599927631
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_random.4230145661
Short name T299
Test name
Test status
Simulation time 402008415086 ps
CPU time 805.79 seconds
Started Jul 22 07:00:13 PM PDT 24
Finished Jul 22 07:13:54 PM PDT 24
Peak memory 191788 kb
Host smart-d382b08e-fdf0-4a10-b6a2-fde4d86a54ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230145661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.4230145661
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.2835202589
Short name T331
Test name
Test status
Simulation time 420696107345 ps
CPU time 385.66 seconds
Started Jul 22 07:00:09 PM PDT 24
Finished Jul 22 07:06:49 PM PDT 24
Peak memory 183584 kb
Host smart-7492aed8-0033-4eb0-bdc4-a3946485bff0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835202589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.2835202589
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_random.406228486
Short name T234
Test name
Test status
Simulation time 66152138163 ps
CPU time 97.88 seconds
Started Jul 22 07:00:30 PM PDT 24
Finished Jul 22 07:02:21 PM PDT 24
Peak memory 191776 kb
Host smart-f8647f2c-1a08-4c50-b45d-7d0158dc4a28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406228486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.406228486
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.301420970
Short name T324
Test name
Test status
Simulation time 189762917034 ps
CPU time 89.98 seconds
Started Jul 22 07:00:40 PM PDT 24
Finished Jul 22 07:02:20 PM PDT 24
Peak memory 183600 kb
Host smart-b6c152d1-465b-48be-b640-70bd2128416b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301420970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.301420970
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/55.rv_timer_random.1459512457
Short name T211
Test name
Test status
Simulation time 187133802300 ps
CPU time 168.97 seconds
Started Jul 22 07:02:16 PM PDT 24
Finished Jul 22 07:05:07 PM PDT 24
Peak memory 191524 kb
Host smart-fe1c89c7-49b2-4581-b585-76bafe3218e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459512457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.1459512457
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.2209586754
Short name T72
Test name
Test status
Simulation time 1698053278810 ps
CPU time 525.93 seconds
Started Jul 22 07:00:34 PM PDT 24
Finished Jul 22 07:09:33 PM PDT 24
Peak memory 191808 kb
Host smart-641eef0c-0a55-4df7-9476-3132a9db0ee1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209586754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.2209586754
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.4020444715
Short name T74
Test name
Test status
Simulation time 78116135600 ps
CPU time 121.34 seconds
Started Jul 22 07:00:05 PM PDT 24
Finished Jul 22 07:02:16 PM PDT 24
Peak memory 195556 kb
Host smart-42cf18d4-09bc-4033-a5d1-e6d69a5f32fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020444715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
4020444715
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/76.rv_timer_random.1738504471
Short name T152
Test name
Test status
Simulation time 505822041218 ps
CPU time 602.62 seconds
Started Jul 22 07:00:42 PM PDT 24
Finished Jul 22 07:10:54 PM PDT 24
Peak memory 191784 kb
Host smart-f78fd0e0-f7b9-40a7-9b3c-b839b768bb4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738504471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.1738504471
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.3705244221
Short name T168
Test name
Test status
Simulation time 468687046652 ps
CPU time 255.46 seconds
Started Jul 22 07:00:47 PM PDT 24
Finished Jul 22 07:05:10 PM PDT 24
Peak memory 191784 kb
Host smart-c32dbf9a-3253-41f1-984a-21a4da82badd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705244221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.3705244221
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.806125687
Short name T470
Test name
Test status
Simulation time 89315454 ps
CPU time 0.6 seconds
Started Jul 22 06:17:35 PM PDT 24
Finished Jul 22 06:17:36 PM PDT 24
Peak memory 182572 kb
Host smart-286bd95d-7c5b-474f-9c4e-9dbb3b5cc99e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806125687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alias
ing.806125687
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.1343734031
Short name T82
Test name
Test status
Simulation time 89954956 ps
CPU time 3.25 seconds
Started Jul 22 06:17:34 PM PDT 24
Finished Jul 22 06:17:38 PM PDT 24
Peak memory 193612 kb
Host smart-432d4a35-3881-4a6c-8a6e-ac7db546b3d8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343734031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.1343734031
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.2433161659
Short name T483
Test name
Test status
Simulation time 13421800 ps
CPU time 0.55 seconds
Started Jul 22 06:18:44 PM PDT 24
Finished Jul 22 06:18:45 PM PDT 24
Peak memory 182088 kb
Host smart-df3c6e4c-73f9-415e-91b7-29edfdbd7a92
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433161659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.2433161659
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.578472909
Short name T44
Test name
Test status
Simulation time 143221698 ps
CPU time 0.94 seconds
Started Jul 22 06:18:27 PM PDT 24
Finished Jul 22 06:18:29 PM PDT 24
Peak memory 196680 kb
Host smart-d7633f5a-00f2-44d9-8e7a-d6f564008a19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578472909 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.578472909
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.3868107367
Short name T570
Test name
Test status
Simulation time 10881703 ps
CPU time 0.54 seconds
Started Jul 22 06:18:02 PM PDT 24
Finished Jul 22 06:18:04 PM PDT 24
Peak memory 182408 kb
Host smart-24c69c53-0063-4d95-8354-51e2ba5c9064
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868107367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.3868107367
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.4201881501
Short name T495
Test name
Test status
Simulation time 43924077 ps
CPU time 0.54 seconds
Started Jul 22 06:17:33 PM PDT 24
Finished Jul 22 06:17:35 PM PDT 24
Peak memory 181952 kb
Host smart-5c7673a1-dde6-4552-93fe-40051b4bdf99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201881501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.4201881501
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.233345017
Short name T529
Test name
Test status
Simulation time 239342457 ps
CPU time 1.92 seconds
Started Jul 22 06:18:01 PM PDT 24
Finished Jul 22 06:18:04 PM PDT 24
Peak memory 197260 kb
Host smart-745fd547-e1c6-49c2-8a36-d209355ad204
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233345017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.233345017
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.97834054
Short name T542
Test name
Test status
Simulation time 59350878 ps
CPU time 0.6 seconds
Started Jul 22 06:17:34 PM PDT 24
Finished Jul 22 06:17:36 PM PDT 24
Peak memory 182548 kb
Host smart-d963c561-6461-4c72-a3c7-afd79c13c0ec
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97834054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_aliasi
ng.97834054
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.294026436
Short name T534
Test name
Test status
Simulation time 235904068 ps
CPU time 2.26 seconds
Started Jul 22 06:17:34 PM PDT 24
Finished Jul 22 06:17:38 PM PDT 24
Peak memory 193584 kb
Host smart-63703aea-8558-429d-89f0-59257c92e6d8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294026436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_b
ash.294026436
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1422109517
Short name T545
Test name
Test status
Simulation time 35485878 ps
CPU time 0.6 seconds
Started Jul 22 06:18:28 PM PDT 24
Finished Jul 22 06:18:29 PM PDT 24
Peak memory 191724 kb
Host smart-5b270106-982b-4724-8b05-c833abe05757
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422109517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.1422109517
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.4085858637
Short name T543
Test name
Test status
Simulation time 30211521 ps
CPU time 0.85 seconds
Started Jul 22 06:17:36 PM PDT 24
Finished Jul 22 06:17:38 PM PDT 24
Peak memory 196724 kb
Host smart-1cd4377e-b48f-455d-bf93-b832af686773
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085858637 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.4085858637
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.1647027901
Short name T113
Test name
Test status
Simulation time 44224677 ps
CPU time 0.55 seconds
Started Jul 22 06:17:34 PM PDT 24
Finished Jul 22 06:17:36 PM PDT 24
Peak memory 182576 kb
Host smart-ecad7e5b-349f-4037-a10a-36614afd3740
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647027901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.1647027901
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.3666184096
Short name T532
Test name
Test status
Simulation time 38966448 ps
CPU time 0.51 seconds
Started Jul 22 06:18:02 PM PDT 24
Finished Jul 22 06:18:04 PM PDT 24
Peak memory 181956 kb
Host smart-934dcc49-0bbc-482a-b0f8-29dd0b873cfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666184096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.3666184096
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.2147506231
Short name T107
Test name
Test status
Simulation time 62442132 ps
CPU time 0.6 seconds
Started Jul 22 06:17:34 PM PDT 24
Finished Jul 22 06:17:36 PM PDT 24
Peak memory 191828 kb
Host smart-e2350f17-1792-4fdf-8831-7eaee45a92b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147506231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.2147506231
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.4269643855
Short name T546
Test name
Test status
Simulation time 117986432 ps
CPU time 2.33 seconds
Started Jul 22 06:17:36 PM PDT 24
Finished Jul 22 06:17:39 PM PDT 24
Peak memory 197244 kb
Host smart-f6215ebd-a6fa-4a56-b65c-34ddffe55e10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269643855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.4269643855
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.2749495208
Short name T528
Test name
Test status
Simulation time 258354590 ps
CPU time 1.02 seconds
Started Jul 22 06:17:35 PM PDT 24
Finished Jul 22 06:17:37 PM PDT 24
Peak memory 183196 kb
Host smart-5f829288-e2b0-4be7-b649-49c550ded0da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749495208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.2749495208
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.2217831094
Short name T492
Test name
Test status
Simulation time 47521343 ps
CPU time 0.79 seconds
Started Jul 22 06:17:57 PM PDT 24
Finished Jul 22 06:17:59 PM PDT 24
Peak memory 195960 kb
Host smart-96c3b46a-1edb-456a-a42c-dc1164c2f847
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217831094 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.2217831094
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.818185872
Short name T530
Test name
Test status
Simulation time 22456477 ps
CPU time 0.58 seconds
Started Jul 22 06:17:53 PM PDT 24
Finished Jul 22 06:17:55 PM PDT 24
Peak memory 182580 kb
Host smart-48ac5d68-27c9-49d3-9a4f-4832cb5cb5df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818185872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.818185872
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.2071890919
Short name T558
Test name
Test status
Simulation time 13490376 ps
CPU time 0.6 seconds
Started Jul 22 06:17:56 PM PDT 24
Finished Jul 22 06:17:57 PM PDT 24
Peak memory 182440 kb
Host smart-16e488dc-9d52-411b-a379-c820f83f5074
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071890919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.2071890919
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.4106123691
Short name T111
Test name
Test status
Simulation time 32129549 ps
CPU time 0.71 seconds
Started Jul 22 06:18:27 PM PDT 24
Finished Jul 22 06:18:28 PM PDT 24
Peak memory 192140 kb
Host smart-7e4148a0-8de9-48d0-bdda-19e192f04316
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106123691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.4106123691
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.2145223348
Short name T488
Test name
Test status
Simulation time 81180514 ps
CPU time 1.93 seconds
Started Jul 22 06:17:54 PM PDT 24
Finished Jul 22 06:17:56 PM PDT 24
Peak memory 197324 kb
Host smart-7ac428c5-393a-4b31-8c30-73cb86c4d40e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145223348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.2145223348
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1114965552
Short name T29
Test name
Test status
Simulation time 154704745 ps
CPU time 1.07 seconds
Started Jul 22 06:18:44 PM PDT 24
Finished Jul 22 06:18:46 PM PDT 24
Peak memory 194640 kb
Host smart-ef3d790d-57e5-4c1c-ad3d-bd15ceabc8d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114965552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.1114965552
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.1323917994
Short name T61
Test name
Test status
Simulation time 152019485 ps
CPU time 0.93 seconds
Started Jul 22 06:17:53 PM PDT 24
Finished Jul 22 06:17:55 PM PDT 24
Peak memory 197208 kb
Host smart-ca461d75-03fc-4538-9c0a-4859d2d8fb84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323917994 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.1323917994
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.3389010852
Short name T500
Test name
Test status
Simulation time 21794050 ps
CPU time 0.54 seconds
Started Jul 22 06:19:06 PM PDT 24
Finished Jul 22 06:19:08 PM PDT 24
Peak memory 182608 kb
Host smart-4acd132f-81c9-4ec4-bc50-6eaa27838879
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389010852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.3389010852
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.3316400708
Short name T469
Test name
Test status
Simulation time 35624007 ps
CPU time 0.54 seconds
Started Jul 22 06:17:56 PM PDT 24
Finished Jul 22 06:17:57 PM PDT 24
Peak memory 181980 kb
Host smart-ef0f6370-3e54-4317-834c-b52453e2b5b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316400708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.3316400708
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.2231822934
Short name T527
Test name
Test status
Simulation time 20622335 ps
CPU time 0.6 seconds
Started Jul 22 06:17:55 PM PDT 24
Finished Jul 22 06:17:57 PM PDT 24
Peak memory 191812 kb
Host smart-da3a5e1d-d88b-4088-a400-95d237fbde0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231822934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.2231822934
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.2128624820
Short name T577
Test name
Test status
Simulation time 95548107 ps
CPU time 2.1 seconds
Started Jul 22 06:17:54 PM PDT 24
Finished Jul 22 06:17:56 PM PDT 24
Peak memory 197320 kb
Host smart-3aad9a1c-7374-42bb-b143-c10b4901e8ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128624820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.2128624820
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.688757133
Short name T116
Test name
Test status
Simulation time 463840422 ps
CPU time 1.57 seconds
Started Jul 22 06:17:54 PM PDT 24
Finished Jul 22 06:17:56 PM PDT 24
Peak memory 194912 kb
Host smart-f4d748d7-8df2-42db-ac49-0e7a207899eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688757133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_in
tg_err.688757133
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.641620948
Short name T522
Test name
Test status
Simulation time 146166264 ps
CPU time 0.86 seconds
Started Jul 22 06:17:57 PM PDT 24
Finished Jul 22 06:17:59 PM PDT 24
Peak memory 197100 kb
Host smart-209c7348-ed2e-4dce-932c-74f87a5f5260
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641620948 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.641620948
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.985694334
Short name T94
Test name
Test status
Simulation time 14617149 ps
CPU time 0.59 seconds
Started Jul 22 06:17:56 PM PDT 24
Finished Jul 22 06:17:57 PM PDT 24
Peak memory 182572 kb
Host smart-3adeba4a-d3db-494a-91c9-c6201f4eedc5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985694334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.985694334
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.3465623142
Short name T552
Test name
Test status
Simulation time 155524314 ps
CPU time 0.58 seconds
Started Jul 22 06:17:58 PM PDT 24
Finished Jul 22 06:17:59 PM PDT 24
Peak memory 182252 kb
Host smart-53c4c0ec-9625-4703-9235-8fbd9a171749
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465623142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.3465623142
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.2796051974
Short name T81
Test name
Test status
Simulation time 26285603 ps
CPU time 0.7 seconds
Started Jul 22 06:17:56 PM PDT 24
Finished Jul 22 06:17:58 PM PDT 24
Peak memory 192036 kb
Host smart-f609013d-7ab9-4a3f-8b5f-2e2afb3f4f0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796051974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.2796051974
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.1674007100
Short name T471
Test name
Test status
Simulation time 360045624 ps
CPU time 1.96 seconds
Started Jul 22 06:17:55 PM PDT 24
Finished Jul 22 06:17:58 PM PDT 24
Peak memory 197328 kb
Host smart-c19da326-bdfa-4d48-bb43-1e363b494522
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674007100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.1674007100
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.2098601642
Short name T498
Test name
Test status
Simulation time 83422516 ps
CPU time 0.78 seconds
Started Jul 22 06:17:53 PM PDT 24
Finished Jul 22 06:17:54 PM PDT 24
Peak memory 193028 kb
Host smart-e104ff99-320d-4b72-9b42-fba84e6c2120
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098601642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.2098601642
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.3614292362
Short name T567
Test name
Test status
Simulation time 22027505 ps
CPU time 0.67 seconds
Started Jul 22 06:17:56 PM PDT 24
Finished Jul 22 06:17:58 PM PDT 24
Peak memory 194440 kb
Host smart-6d27c5ee-dffb-4e8e-ace8-baf53a593cd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614292362 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.3614292362
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3148858356
Short name T95
Test name
Test status
Simulation time 12003458 ps
CPU time 0.58 seconds
Started Jul 22 06:17:55 PM PDT 24
Finished Jul 22 06:17:56 PM PDT 24
Peak memory 182556 kb
Host smart-54b60d46-e160-4233-88ce-b6b84f0d0377
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148858356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.3148858356
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3092096895
Short name T521
Test name
Test status
Simulation time 13711475 ps
CPU time 0.52 seconds
Started Jul 22 06:17:54 PM PDT 24
Finished Jul 22 06:17:55 PM PDT 24
Peak memory 181920 kb
Host smart-85b68fc4-3d63-4666-8aee-cd552edd4843
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092096895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.3092096895
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.471745492
Short name T563
Test name
Test status
Simulation time 80155484 ps
CPU time 0.91 seconds
Started Jul 22 06:17:55 PM PDT 24
Finished Jul 22 06:17:56 PM PDT 24
Peak memory 193196 kb
Host smart-3146a6b2-584a-4a0c-88f3-f93b82810ae6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471745492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_ti
mer_same_csr_outstanding.471745492
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.3981757823
Short name T477
Test name
Test status
Simulation time 42442569 ps
CPU time 2 seconds
Started Jul 22 06:18:33 PM PDT 24
Finished Jul 22 06:18:35 PM PDT 24
Peak memory 197292 kb
Host smart-45b6c284-8f66-4efe-a533-bbacd07a9e9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981757823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.3981757823
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.3910999507
Short name T47
Test name
Test status
Simulation time 430259670 ps
CPU time 1.36 seconds
Started Jul 22 06:17:53 PM PDT 24
Finished Jul 22 06:17:55 PM PDT 24
Peak memory 195100 kb
Host smart-fab2f4c3-e1ec-4bcf-8c0c-4c47c776a49f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910999507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.3910999507
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.3166839713
Short name T515
Test name
Test status
Simulation time 118070245 ps
CPU time 0.88 seconds
Started Jul 22 06:18:11 PM PDT 24
Finished Jul 22 06:18:12 PM PDT 24
Peak memory 196716 kb
Host smart-7ec9e13e-dbe7-4df8-9005-acb48b75f879
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166839713 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.3166839713
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.2999259884
Short name T456
Test name
Test status
Simulation time 43535982 ps
CPU time 0.58 seconds
Started Jul 22 06:18:55 PM PDT 24
Finished Jul 22 06:18:57 PM PDT 24
Peak memory 182552 kb
Host smart-47ceb1c7-b9b9-495f-84d3-04280a91f38f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999259884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.2999259884
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.454639306
Short name T513
Test name
Test status
Simulation time 12036970 ps
CPU time 0.53 seconds
Started Jul 22 06:18:55 PM PDT 24
Finished Jul 22 06:18:56 PM PDT 24
Peak memory 182140 kb
Host smart-3464e930-5f6e-47ea-897d-8861d3e23fd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454639306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.454639306
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.4025427592
Short name T571
Test name
Test status
Simulation time 14207671 ps
CPU time 0.59 seconds
Started Jul 22 06:18:55 PM PDT 24
Finished Jul 22 06:18:56 PM PDT 24
Peak memory 191520 kb
Host smart-6736a862-f3c8-4d58-8936-f734d6a77683
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025427592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.4025427592
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.1576023645
Short name T509
Test name
Test status
Simulation time 397923286 ps
CPU time 3.23 seconds
Started Jul 22 06:17:55 PM PDT 24
Finished Jul 22 06:17:59 PM PDT 24
Peak memory 197312 kb
Host smart-3423bcc6-a5d8-4811-ad84-51bde0e45bd5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576023645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.1576023645
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.3610349992
Short name T505
Test name
Test status
Simulation time 81209683 ps
CPU time 1.12 seconds
Started Jul 22 06:17:58 PM PDT 24
Finished Jul 22 06:17:59 PM PDT 24
Peak memory 194768 kb
Host smart-7378576d-0f25-48eb-a2ba-870349ca21fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610349992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.3610349992
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.2931605764
Short name T482
Test name
Test status
Simulation time 65419389 ps
CPU time 0.88 seconds
Started Jul 22 06:18:01 PM PDT 24
Finished Jul 22 06:18:02 PM PDT 24
Peak memory 196716 kb
Host smart-dc9255e4-cfa1-4b78-943d-ebd4d287a031
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931605764 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.2931605764
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.1665267184
Short name T48
Test name
Test status
Simulation time 84150038 ps
CPU time 0.58 seconds
Started Jul 22 06:18:01 PM PDT 24
Finished Jul 22 06:18:03 PM PDT 24
Peak memory 182580 kb
Host smart-65288d48-e026-4579-9482-2563d796ee60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665267184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.1665267184
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.145606321
Short name T448
Test name
Test status
Simulation time 14171932 ps
CPU time 0.58 seconds
Started Jul 22 06:18:02 PM PDT 24
Finished Jul 22 06:18:04 PM PDT 24
Peak memory 181532 kb
Host smart-646fac0c-f800-4ddb-9331-f9c46b3f36e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145606321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.145606321
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.2424780313
Short name T573
Test name
Test status
Simulation time 131184163 ps
CPU time 0.68 seconds
Started Jul 22 06:18:04 PM PDT 24
Finished Jul 22 06:18:06 PM PDT 24
Peak memory 191548 kb
Host smart-288848e6-5d78-45db-9b18-4c1b17a1c695
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424780313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.2424780313
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.3630879208
Short name T454
Test name
Test status
Simulation time 61462172 ps
CPU time 1.58 seconds
Started Jul 22 06:17:58 PM PDT 24
Finished Jul 22 06:18:00 PM PDT 24
Peak memory 197284 kb
Host smart-802e6bc9-6664-4c99-aa1c-dc4223612292
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630879208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.3630879208
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1545525067
Short name T60
Test name
Test status
Simulation time 91774124 ps
CPU time 1.17 seconds
Started Jul 22 06:18:01 PM PDT 24
Finished Jul 22 06:18:04 PM PDT 24
Peak memory 194912 kb
Host smart-642bd036-1e38-4f20-af07-a35aa89adb5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545525067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.1545525067
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.1865893003
Short name T524
Test name
Test status
Simulation time 96083987 ps
CPU time 1.11 seconds
Started Jul 22 06:18:02 PM PDT 24
Finished Jul 22 06:18:05 PM PDT 24
Peak memory 197344 kb
Host smart-6e601520-91b3-4a55-b250-9a00935327e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865893003 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.1865893003
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.1587002039
Short name T93
Test name
Test status
Simulation time 13628015 ps
CPU time 0.62 seconds
Started Jul 22 06:18:02 PM PDT 24
Finished Jul 22 06:18:04 PM PDT 24
Peak memory 182244 kb
Host smart-f52ae659-9edc-4e0d-ad9f-4d0bb7888d3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587002039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.1587002039
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.4274843294
Short name T464
Test name
Test status
Simulation time 50045039 ps
CPU time 0.57 seconds
Started Jul 22 06:18:01 PM PDT 24
Finished Jul 22 06:18:02 PM PDT 24
Peak memory 182436 kb
Host smart-dfb6fdd5-1829-4b2d-8406-e21ac6574359
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274843294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.4274843294
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.3625480203
Short name T108
Test name
Test status
Simulation time 14591832 ps
CPU time 0.63 seconds
Started Jul 22 06:18:03 PM PDT 24
Finished Jul 22 06:18:05 PM PDT 24
Peak memory 191376 kb
Host smart-cc65b111-0932-4cd7-a8ef-ee5c70a12e9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625480203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.3625480203
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.446567664
Short name T555
Test name
Test status
Simulation time 92547102 ps
CPU time 2.16 seconds
Started Jul 22 06:18:00 PM PDT 24
Finished Jul 22 06:18:03 PM PDT 24
Peak memory 197260 kb
Host smart-1511a14f-f261-4726-9962-ae49aa7e8b77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446567664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.446567664
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.173441869
Short name T554
Test name
Test status
Simulation time 327448681 ps
CPU time 0.79 seconds
Started Jul 22 06:18:02 PM PDT 24
Finished Jul 22 06:18:05 PM PDT 24
Peak memory 182868 kb
Host smart-b1bf4920-2fd8-4cb1-9622-f6579b7e9535
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173441869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_in
tg_err.173441869
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.623047834
Short name T494
Test name
Test status
Simulation time 67058936 ps
CPU time 0.63 seconds
Started Jul 22 06:18:25 PM PDT 24
Finished Jul 22 06:18:26 PM PDT 24
Peak memory 193568 kb
Host smart-2ea4b016-161a-4490-be0a-022c4f111888
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623047834 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.623047834
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.1604849680
Short name T112
Test name
Test status
Simulation time 10494085 ps
CPU time 0.52 seconds
Started Jul 22 06:18:00 PM PDT 24
Finished Jul 22 06:18:01 PM PDT 24
Peak memory 182176 kb
Host smart-a47aab46-71e4-46e3-9898-85ddb0a57135
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604849680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.1604849680
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3393277218
Short name T449
Test name
Test status
Simulation time 56150506 ps
CPU time 0.55 seconds
Started Jul 22 06:18:24 PM PDT 24
Finished Jul 22 06:18:25 PM PDT 24
Peak memory 182444 kb
Host smart-c88f6734-0b8f-4ebe-bf81-514126446574
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393277218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.3393277218
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.3904469488
Short name T43
Test name
Test status
Simulation time 56465380 ps
CPU time 0.6 seconds
Started Jul 22 06:18:03 PM PDT 24
Finished Jul 22 06:18:05 PM PDT 24
Peak memory 191128 kb
Host smart-65846d07-13a2-4f0e-8ab3-c1e606d2b27c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904469488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.3904469488
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.3895525103
Short name T556
Test name
Test status
Simulation time 254618412 ps
CPU time 3.16 seconds
Started Jul 22 06:18:00 PM PDT 24
Finished Jul 22 06:18:04 PM PDT 24
Peak memory 197252 kb
Host smart-12ceb62d-4a7c-49c9-9959-ac1d235a41d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895525103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.3895525103
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3321486197
Short name T30
Test name
Test status
Simulation time 119214586 ps
CPU time 1.43 seconds
Started Jul 22 06:18:03 PM PDT 24
Finished Jul 22 06:18:06 PM PDT 24
Peak memory 195316 kb
Host smart-8f7cbcd6-72ab-42ef-8268-acff6a7f2de2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321486197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.3321486197
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.2693358547
Short name T31
Test name
Test status
Simulation time 107902701 ps
CPU time 0.84 seconds
Started Jul 22 06:18:01 PM PDT 24
Finished Jul 22 06:18:03 PM PDT 24
Peak memory 196856 kb
Host smart-0fd787f4-f552-4e14-ac5d-2b5f3ef3b251
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693358547 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.2693358547
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.3474559887
Short name T45
Test name
Test status
Simulation time 47758749 ps
CPU time 0.54 seconds
Started Jul 22 06:18:02 PM PDT 24
Finished Jul 22 06:18:04 PM PDT 24
Peak memory 182596 kb
Host smart-5ad10a90-a417-4561-a792-301362209700
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474559887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.3474559887
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.523994163
Short name T462
Test name
Test status
Simulation time 28341789 ps
CPU time 0.55 seconds
Started Jul 22 06:18:00 PM PDT 24
Finished Jul 22 06:18:02 PM PDT 24
Peak memory 182420 kb
Host smart-542e7893-4cdd-4764-82ab-4674264368f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523994163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.523994163
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.401822205
Short name T517
Test name
Test status
Simulation time 29894557 ps
CPU time 0.61 seconds
Started Jul 22 06:18:02 PM PDT 24
Finished Jul 22 06:18:04 PM PDT 24
Peak memory 191744 kb
Host smart-937844ae-0813-403d-b8f4-690743ced1bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401822205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_ti
mer_same_csr_outstanding.401822205
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3210753993
Short name T461
Test name
Test status
Simulation time 44531739 ps
CPU time 1.04 seconds
Started Jul 22 06:17:57 PM PDT 24
Finished Jul 22 06:17:59 PM PDT 24
Peak memory 197212 kb
Host smart-e9767b63-906d-4ece-bbde-2711faf7f0e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210753993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.3210753993
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.3702697127
Short name T564
Test name
Test status
Simulation time 76021235 ps
CPU time 0.8 seconds
Started Jul 22 06:17:59 PM PDT 24
Finished Jul 22 06:18:00 PM PDT 24
Peak memory 193600 kb
Host smart-7cbe63d0-331a-4b41-bd8e-2bd0382c2923
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702697127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.3702697127
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.1232440908
Short name T519
Test name
Test status
Simulation time 41780479 ps
CPU time 0.73 seconds
Started Jul 22 06:18:01 PM PDT 24
Finished Jul 22 06:18:03 PM PDT 24
Peak memory 195064 kb
Host smart-86066a8a-aead-45c9-8856-4369bb08e71b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232440908 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.1232440908
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.2103778225
Short name T506
Test name
Test status
Simulation time 37991714 ps
CPU time 0.57 seconds
Started Jul 22 06:18:27 PM PDT 24
Finished Jul 22 06:18:28 PM PDT 24
Peak memory 182600 kb
Host smart-9abf98af-33fa-4c4e-a830-c1d9597ea16d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103778225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.2103778225
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.3748884469
Short name T569
Test name
Test status
Simulation time 14245200 ps
CPU time 0.56 seconds
Started Jul 22 06:18:02 PM PDT 24
Finished Jul 22 06:18:05 PM PDT 24
Peak memory 182484 kb
Host smart-449b3c67-85b6-4d87-8b32-a8417d48fd57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748884469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.3748884469
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2125147925
Short name T516
Test name
Test status
Simulation time 24117384 ps
CPU time 0.7 seconds
Started Jul 22 06:18:25 PM PDT 24
Finished Jul 22 06:18:26 PM PDT 24
Peak memory 191512 kb
Host smart-ceb232f7-5cb5-4bf0-aaa2-7ef3c666d708
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125147925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.2125147925
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.850047139
Short name T547
Test name
Test status
Simulation time 76333576 ps
CPU time 2.05 seconds
Started Jul 22 06:18:01 PM PDT 24
Finished Jul 22 06:18:05 PM PDT 24
Peak memory 197312 kb
Host smart-6cadbf35-6a1b-4be4-9dd0-e684d640d46a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850047139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.850047139
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.3894946052
Short name T468
Test name
Test status
Simulation time 42346915 ps
CPU time 0.8 seconds
Started Jul 22 06:18:01 PM PDT 24
Finished Jul 22 06:18:02 PM PDT 24
Peak memory 193368 kb
Host smart-f0ce6cc0-9404-4fa9-b2b0-531f92e0b511
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894946052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.3894946052
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.1730951717
Short name T83
Test name
Test status
Simulation time 387768204 ps
CPU time 0.81 seconds
Started Jul 22 06:17:43 PM PDT 24
Finished Jul 22 06:17:44 PM PDT 24
Peak memory 182600 kb
Host smart-2fd9264a-2126-4de1-836f-a2de9812f913
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730951717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.1730951717
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1911116882
Short name T473
Test name
Test status
Simulation time 133082646 ps
CPU time 1.47 seconds
Started Jul 22 06:17:43 PM PDT 24
Finished Jul 22 06:17:46 PM PDT 24
Peak memory 192604 kb
Host smart-92e6b71f-dc7e-433c-9200-79ff5ed93e4b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911116882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.1911116882
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.481770522
Short name T512
Test name
Test status
Simulation time 13827960 ps
CPU time 0.54 seconds
Started Jul 22 06:17:43 PM PDT 24
Finished Jul 22 06:17:44 PM PDT 24
Peak memory 182072 kb
Host smart-911f461b-779f-4b19-81a9-a73d5e49f3b8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481770522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_re
set.481770522
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.2256162971
Short name T486
Test name
Test status
Simulation time 64010522 ps
CPU time 0.8 seconds
Started Jul 22 06:17:43 PM PDT 24
Finished Jul 22 06:17:44 PM PDT 24
Peak memory 196256 kb
Host smart-f154da37-f96a-4e05-8569-65139323a66d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256162971 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.2256162971
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.378910483
Short name T501
Test name
Test status
Simulation time 10904403 ps
CPU time 0.57 seconds
Started Jul 22 06:17:42 PM PDT 24
Finished Jul 22 06:17:43 PM PDT 24
Peak memory 182596 kb
Host smart-0b146275-7d09-44e4-8269-0802fd9ad0bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378910483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.378910483
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.33413347
Short name T539
Test name
Test status
Simulation time 19327289 ps
CPU time 0.54 seconds
Started Jul 22 06:17:36 PM PDT 24
Finished Jul 22 06:17:37 PM PDT 24
Peak memory 182484 kb
Host smart-14cd4cc8-9888-4c09-8a6d-f5eccdc5003b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33413347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.33413347
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.767911173
Short name T548
Test name
Test status
Simulation time 119829715 ps
CPU time 0.68 seconds
Started Jul 22 06:17:44 PM PDT 24
Finished Jul 22 06:17:45 PM PDT 24
Peak memory 191532 kb
Host smart-8ef02c54-1ba5-4c77-96ad-c34457d3994d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767911173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_tim
er_same_csr_outstanding.767911173
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.351118996
Short name T452
Test name
Test status
Simulation time 48147648 ps
CPU time 1.35 seconds
Started Jul 22 06:18:02 PM PDT 24
Finished Jul 22 06:18:05 PM PDT 24
Peak memory 197316 kb
Host smart-2cef9294-7aa4-4bf9-812f-2d35ae48b6b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351118996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.351118996
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.1990079897
Short name T487
Test name
Test status
Simulation time 98512108 ps
CPU time 1.36 seconds
Started Jul 22 06:17:34 PM PDT 24
Finished Jul 22 06:17:36 PM PDT 24
Peak memory 195364 kb
Host smart-dd311561-37af-4953-8f81-95b03fa9ccfc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990079897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.1990079897
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.1781799347
Short name T507
Test name
Test status
Simulation time 45602583 ps
CPU time 0.57 seconds
Started Jul 22 06:18:01 PM PDT 24
Finished Jul 22 06:18:02 PM PDT 24
Peak memory 182464 kb
Host smart-6ce462e7-af33-4db6-8169-a3809c3c30e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781799347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.1781799347
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.407937001
Short name T463
Test name
Test status
Simulation time 41497908 ps
CPU time 0.54 seconds
Started Jul 22 06:18:04 PM PDT 24
Finished Jul 22 06:18:06 PM PDT 24
Peak memory 182472 kb
Host smart-38a9cde5-fccd-40bd-ade5-516645d6ca93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407937001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.407937001
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.854603929
Short name T458
Test name
Test status
Simulation time 50803616 ps
CPU time 0.55 seconds
Started Jul 22 06:17:59 PM PDT 24
Finished Jul 22 06:18:00 PM PDT 24
Peak memory 182516 kb
Host smart-38f93ad6-af0b-4e6f-ae07-2e5ca8a70d12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854603929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.854603929
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.3670135447
Short name T467
Test name
Test status
Simulation time 48257094 ps
CPU time 0.54 seconds
Started Jul 22 06:18:07 PM PDT 24
Finished Jul 22 06:18:08 PM PDT 24
Peak memory 182604 kb
Host smart-7c82dc8b-f0f0-49a5-8a3c-7f699b89ca8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670135447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.3670135447
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2874198796
Short name T484
Test name
Test status
Simulation time 27489966 ps
CPU time 0.51 seconds
Started Jul 22 06:18:12 PM PDT 24
Finished Jul 22 06:18:13 PM PDT 24
Peak memory 181924 kb
Host smart-b898f50c-199c-4ac3-8df2-e505db3cc5a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874198796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.2874198796
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.3219091055
Short name T502
Test name
Test status
Simulation time 39882755 ps
CPU time 0.56 seconds
Started Jul 22 06:18:04 PM PDT 24
Finished Jul 22 06:18:06 PM PDT 24
Peak memory 181960 kb
Host smart-1f42ffa3-2cfa-494f-b8c1-787b8c1ee29a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219091055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.3219091055
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.3982613903
Short name T489
Test name
Test status
Simulation time 56784727 ps
CPU time 0.56 seconds
Started Jul 22 06:18:01 PM PDT 24
Finished Jul 22 06:18:03 PM PDT 24
Peak memory 182492 kb
Host smart-0287b60c-338d-437f-8b08-b92b788165f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982613903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.3982613903
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.1535855661
Short name T576
Test name
Test status
Simulation time 17001601 ps
CPU time 0.55 seconds
Started Jul 22 06:18:02 PM PDT 24
Finished Jul 22 06:18:04 PM PDT 24
Peak memory 182220 kb
Host smart-14e7534f-f61a-49ef-8fb0-78de863b400b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535855661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.1535855661
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2919080162
Short name T559
Test name
Test status
Simulation time 14971651 ps
CPU time 0.56 seconds
Started Jul 22 06:18:01 PM PDT 24
Finished Jul 22 06:18:03 PM PDT 24
Peak memory 182552 kb
Host smart-82e0b033-4ece-4170-8cb7-8d3b2d417d65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919080162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.2919080162
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.4011787263
Short name T465
Test name
Test status
Simulation time 24285776 ps
CPU time 0.55 seconds
Started Jul 22 06:18:24 PM PDT 24
Finished Jul 22 06:18:25 PM PDT 24
Peak memory 182460 kb
Host smart-23f82892-0eb4-4089-a4e7-3e773c0ffcb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011787263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.4011787263
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.1355081568
Short name T475
Test name
Test status
Simulation time 17147393 ps
CPU time 0.7 seconds
Started Jul 22 06:17:46 PM PDT 24
Finished Jul 22 06:17:47 PM PDT 24
Peak memory 182592 kb
Host smart-1a443fbb-bc68-407c-bf02-a60d89f8e91a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355081568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.1355081568
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.2930608655
Short name T32
Test name
Test status
Simulation time 142511698 ps
CPU time 1.48 seconds
Started Jul 22 06:17:42 PM PDT 24
Finished Jul 22 06:17:44 PM PDT 24
Peak memory 190896 kb
Host smart-dda55ccd-7b25-4178-887f-39bf56111aba
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930608655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.2930608655
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.4182354914
Short name T459
Test name
Test status
Simulation time 16190639 ps
CPU time 0.62 seconds
Started Jul 22 06:17:42 PM PDT 24
Finished Jul 22 06:17:43 PM PDT 24
Peak memory 182116 kb
Host smart-eb50ea39-5a70-4ffb-8e59-31dc82e89cba
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182354914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.4182354914
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.1196766408
Short name T511
Test name
Test status
Simulation time 23032019 ps
CPU time 1.02 seconds
Started Jul 22 06:17:42 PM PDT 24
Finished Jul 22 06:17:44 PM PDT 24
Peak memory 197232 kb
Host smart-50f6363e-b58e-4cbc-9bd9-3daed3e74ff4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196766408 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.1196766408
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.3659547009
Short name T114
Test name
Test status
Simulation time 15165344 ps
CPU time 0.57 seconds
Started Jul 22 06:17:43 PM PDT 24
Finished Jul 22 06:17:44 PM PDT 24
Peak memory 191780 kb
Host smart-9a3130c4-68e2-4691-8b3d-df0a22438bce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659547009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.3659547009
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.1554145482
Short name T553
Test name
Test status
Simulation time 13034350 ps
CPU time 0.53 seconds
Started Jul 22 06:17:42 PM PDT 24
Finished Jul 22 06:17:43 PM PDT 24
Peak memory 181736 kb
Host smart-00612510-9680-42c6-94bd-162604bec4a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554145482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.1554145482
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.214314557
Short name T537
Test name
Test status
Simulation time 17971464 ps
CPU time 0.71 seconds
Started Jul 22 06:17:46 PM PDT 24
Finished Jul 22 06:17:48 PM PDT 24
Peak memory 191568 kb
Host smart-ec83d1ef-0bd6-4fe7-9071-9e6060f107df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214314557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_tim
er_same_csr_outstanding.214314557
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.1938514609
Short name T62
Test name
Test status
Simulation time 71618095 ps
CPU time 1.04 seconds
Started Jul 22 06:17:41 PM PDT 24
Finished Jul 22 06:17:43 PM PDT 24
Peak memory 197200 kb
Host smart-1901306f-8976-4f1c-bbd3-969c7f3ae161
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938514609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.1938514609
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.3510250386
Short name T474
Test name
Test status
Simulation time 15334440 ps
CPU time 0.62 seconds
Started Jul 22 06:18:01 PM PDT 24
Finished Jul 22 06:18:03 PM PDT 24
Peak memory 182388 kb
Host smart-90216e13-373e-42a1-a64b-526702a3d025
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510250386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.3510250386
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.3773035896
Short name T523
Test name
Test status
Simulation time 13114665 ps
CPU time 0.58 seconds
Started Jul 22 06:18:03 PM PDT 24
Finished Jul 22 06:18:06 PM PDT 24
Peak memory 182424 kb
Host smart-599e1ccc-a7b0-4102-899b-3263a2d1f5fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773035896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.3773035896
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.3478082465
Short name T457
Test name
Test status
Simulation time 218436829 ps
CPU time 0.58 seconds
Started Jul 22 06:18:01 PM PDT 24
Finished Jul 22 06:18:03 PM PDT 24
Peak memory 182416 kb
Host smart-31fafe4b-3e9a-4111-ae06-7347b49c8636
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478082465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.3478082465
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.2431210717
Short name T514
Test name
Test status
Simulation time 59196280 ps
CPU time 0.59 seconds
Started Jul 22 06:18:03 PM PDT 24
Finished Jul 22 06:18:06 PM PDT 24
Peak memory 182484 kb
Host smart-ed02e210-645c-4ab1-bf5c-2ebdcb8f1af1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431210717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.2431210717
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.3318658875
Short name T538
Test name
Test status
Simulation time 68747075 ps
CPU time 0.57 seconds
Started Jul 22 06:18:02 PM PDT 24
Finished Jul 22 06:18:05 PM PDT 24
Peak memory 182276 kb
Host smart-8606a765-f261-47d5-b626-5379901a4667
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318658875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.3318658875
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.400027303
Short name T518
Test name
Test status
Simulation time 22387482 ps
CPU time 0.52 seconds
Started Jul 22 06:18:25 PM PDT 24
Finished Jul 22 06:18:26 PM PDT 24
Peak memory 181932 kb
Host smart-7e1a4ffe-2da1-4418-ac20-9d29022dbfcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400027303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.400027303
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.844239149
Short name T451
Test name
Test status
Simulation time 13726850 ps
CPU time 0.62 seconds
Started Jul 22 06:18:01 PM PDT 24
Finished Jul 22 06:18:02 PM PDT 24
Peak memory 181984 kb
Host smart-0b2e248c-89af-4370-95d7-10be87c04c83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844239149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.844239149
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.3584004730
Short name T536
Test name
Test status
Simulation time 15180674 ps
CPU time 0.54 seconds
Started Jul 22 06:17:59 PM PDT 24
Finished Jul 22 06:18:00 PM PDT 24
Peak memory 182460 kb
Host smart-7dc5f207-4d79-4249-9f90-ef77a8020d60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584004730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.3584004730
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.2323471518
Short name T455
Test name
Test status
Simulation time 13287620 ps
CPU time 0.54 seconds
Started Jul 22 06:18:00 PM PDT 24
Finished Jul 22 06:18:01 PM PDT 24
Peak memory 182468 kb
Host smart-35b42e90-4ff8-41bc-8de6-6050950de57f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323471518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.2323471518
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.2843088859
Short name T476
Test name
Test status
Simulation time 28347324 ps
CPU time 0.55 seconds
Started Jul 22 06:18:04 PM PDT 24
Finished Jul 22 06:18:06 PM PDT 24
Peak memory 182156 kb
Host smart-d7c32eb5-1731-4ac4-ae42-b291dddaf5ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843088859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.2843088859
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.3344222030
Short name T105
Test name
Test status
Simulation time 173764722 ps
CPU time 3.08 seconds
Started Jul 22 06:17:42 PM PDT 24
Finished Jul 22 06:17:45 PM PDT 24
Peak memory 182832 kb
Host smart-053f632d-1887-4c5f-8b7b-384f75c054e4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344222030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.3344222030
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.923803305
Short name T551
Test name
Test status
Simulation time 12426570 ps
CPU time 0.55 seconds
Started Jul 22 06:17:46 PM PDT 24
Finished Jul 22 06:17:47 PM PDT 24
Peak memory 182584 kb
Host smart-d4b1c277-db92-4f1d-a8f6-95e819a71f11
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923803305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_re
set.923803305
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.4092181229
Short name T49
Test name
Test status
Simulation time 24979084 ps
CPU time 0.72 seconds
Started Jul 22 06:18:20 PM PDT 24
Finished Jul 22 06:18:21 PM PDT 24
Peak memory 195192 kb
Host smart-0e36df6f-d137-4ed7-83cb-4fe8838a8e03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092181229 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.4092181229
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2596827337
Short name T510
Test name
Test status
Simulation time 27299456 ps
CPU time 0.53 seconds
Started Jul 22 06:17:42 PM PDT 24
Finished Jul 22 06:17:43 PM PDT 24
Peak memory 182556 kb
Host smart-15727fa3-ac60-464e-b958-b9311ed77002
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596827337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.2596827337
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.294746712
Short name T525
Test name
Test status
Simulation time 15982100 ps
CPU time 0.57 seconds
Started Jul 22 06:17:41 PM PDT 24
Finished Jul 22 06:17:42 PM PDT 24
Peak memory 182480 kb
Host smart-852a9d23-ca3c-400d-b864-83b683b1e28f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294746712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.294746712
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.3214145342
Short name T508
Test name
Test status
Simulation time 58348219 ps
CPU time 0.61 seconds
Started Jul 22 06:17:43 PM PDT 24
Finished Jul 22 06:17:45 PM PDT 24
Peak memory 191944 kb
Host smart-545c5211-75bf-4810-bace-04ff5cafda3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214145342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.3214145342
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1449423427
Short name T566
Test name
Test status
Simulation time 59666785 ps
CPU time 2.42 seconds
Started Jul 22 06:17:45 PM PDT 24
Finished Jul 22 06:17:48 PM PDT 24
Peak memory 197364 kb
Host smart-75e3432d-5f54-41ed-9061-d36b154fa892
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449423427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.1449423427
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2681148070
Short name T115
Test name
Test status
Simulation time 651460262 ps
CPU time 1.28 seconds
Started Jul 22 06:18:20 PM PDT 24
Finished Jul 22 06:18:22 PM PDT 24
Peak memory 195152 kb
Host smart-c71582fa-3806-42e9-a612-adb9b33009ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681148070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.2681148070
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.3528533997
Short name T450
Test name
Test status
Simulation time 24594734 ps
CPU time 0.56 seconds
Started Jul 22 06:18:02 PM PDT 24
Finished Jul 22 06:18:05 PM PDT 24
Peak memory 182500 kb
Host smart-1f11c664-0cdc-4b54-baf5-98c99b0c236a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528533997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.3528533997
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.1241100933
Short name T562
Test name
Test status
Simulation time 34868580 ps
CPU time 0.52 seconds
Started Jul 22 06:18:02 PM PDT 24
Finished Jul 22 06:18:05 PM PDT 24
Peak memory 182484 kb
Host smart-055f9253-5522-4fb9-9e95-807546444a87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241100933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.1241100933
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.428576667
Short name T496
Test name
Test status
Simulation time 33599763 ps
CPU time 0.62 seconds
Started Jul 22 06:18:05 PM PDT 24
Finished Jul 22 06:18:06 PM PDT 24
Peak memory 182440 kb
Host smart-6b193af4-d410-49ca-90bd-01edf7df053e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428576667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.428576667
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.50718316
Short name T485
Test name
Test status
Simulation time 37541994 ps
CPU time 0.53 seconds
Started Jul 22 06:18:24 PM PDT 24
Finished Jul 22 06:18:24 PM PDT 24
Peak memory 182476 kb
Host smart-ffb59189-82f5-46e0-a140-df8cf6bcc577
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50718316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.50718316
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.2187623500
Short name T478
Test name
Test status
Simulation time 20075548 ps
CPU time 0.57 seconds
Started Jul 22 06:18:24 PM PDT 24
Finished Jul 22 06:18:25 PM PDT 24
Peak memory 182480 kb
Host smart-6a524b3e-3c36-41f5-89d3-d6238a5765e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187623500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.2187623500
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1128134368
Short name T574
Test name
Test status
Simulation time 21061850 ps
CPU time 0.57 seconds
Started Jul 22 06:18:03 PM PDT 24
Finished Jul 22 06:18:06 PM PDT 24
Peak memory 181936 kb
Host smart-a7283a08-d05a-4b7a-9239-24b3ac8b6821
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128134368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.1128134368
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.1284865743
Short name T557
Test name
Test status
Simulation time 21345249 ps
CPU time 0.56 seconds
Started Jul 22 06:18:01 PM PDT 24
Finished Jul 22 06:18:03 PM PDT 24
Peak memory 182488 kb
Host smart-b3888d99-a6ed-405e-a343-9902dd663d71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284865743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.1284865743
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.3737502396
Short name T540
Test name
Test status
Simulation time 13673426 ps
CPU time 0.54 seconds
Started Jul 22 06:18:24 PM PDT 24
Finished Jul 22 06:18:24 PM PDT 24
Peak memory 182432 kb
Host smart-696b6280-5e75-4689-9521-26d8aea6f86a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737502396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.3737502396
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.1467087735
Short name T541
Test name
Test status
Simulation time 23384916 ps
CPU time 0.55 seconds
Started Jul 22 06:18:03 PM PDT 24
Finished Jul 22 06:18:05 PM PDT 24
Peak memory 182108 kb
Host smart-6d65ef1a-9454-4130-b582-a83b896e4814
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467087735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.1467087735
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.2469494844
Short name T561
Test name
Test status
Simulation time 49582500 ps
CPU time 0.53 seconds
Started Jul 22 06:18:03 PM PDT 24
Finished Jul 22 06:18:06 PM PDT 24
Peak memory 181948 kb
Host smart-34bd3550-c129-41b3-afd6-738bc1ff2bae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469494844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.2469494844
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2193888397
Short name T460
Test name
Test status
Simulation time 37627793 ps
CPU time 0.99 seconds
Started Jul 22 06:17:47 PM PDT 24
Finished Jul 22 06:17:48 PM PDT 24
Peak memory 197216 kb
Host smart-0837622d-58e5-41d7-80a5-398d7807b901
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193888397 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.2193888397
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.178883147
Short name T503
Test name
Test status
Simulation time 118398691 ps
CPU time 0.54 seconds
Started Jul 22 06:18:44 PM PDT 24
Finished Jul 22 06:18:45 PM PDT 24
Peak memory 182556 kb
Host smart-a71f6915-f475-4123-9b59-e50630a9e30b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178883147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.178883147
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.3409584916
Short name T466
Test name
Test status
Simulation time 43565648 ps
CPU time 0.55 seconds
Started Jul 22 06:17:46 PM PDT 24
Finished Jul 22 06:17:46 PM PDT 24
Peak memory 181956 kb
Host smart-68daa725-f346-46a3-9452-f89021f7c321
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409584916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.3409584916
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.3727410053
Short name T110
Test name
Test status
Simulation time 48822369 ps
CPU time 0.69 seconds
Started Jul 22 06:17:44 PM PDT 24
Finished Jul 22 06:17:46 PM PDT 24
Peak memory 191548 kb
Host smart-6a1db2f7-2e9d-4593-b35b-5b108d8c7d09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727410053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.3727410053
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.3054279670
Short name T46
Test name
Test status
Simulation time 110442835 ps
CPU time 1.93 seconds
Started Jul 22 06:17:46 PM PDT 24
Finished Jul 22 06:17:49 PM PDT 24
Peak memory 197312 kb
Host smart-3e2f83d5-ad45-415d-a393-76f6a264a0b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054279670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.3054279670
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3333412773
Short name T568
Test name
Test status
Simulation time 41788407 ps
CPU time 0.81 seconds
Started Jul 22 06:17:45 PM PDT 24
Finished Jul 22 06:17:46 PM PDT 24
Peak memory 193124 kb
Host smart-d223e68a-b6ce-4229-910a-9517ec4cf01e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333412773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.3333412773
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.2964081083
Short name T499
Test name
Test status
Simulation time 86024881 ps
CPU time 1.09 seconds
Started Jul 22 06:17:43 PM PDT 24
Finished Jul 22 06:17:45 PM PDT 24
Peak memory 197352 kb
Host smart-48329864-ab13-4ea1-8d39-42e9eea6795d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964081083 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.2964081083
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1812314659
Short name T106
Test name
Test status
Simulation time 11375574 ps
CPU time 0.59 seconds
Started Jul 22 06:17:43 PM PDT 24
Finished Jul 22 06:17:44 PM PDT 24
Peak memory 182588 kb
Host smart-a2d99b81-b34f-455a-99a1-4252b4828eb1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812314659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.1812314659
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.1385947930
Short name T453
Test name
Test status
Simulation time 19246283 ps
CPU time 0.53 seconds
Started Jul 22 06:17:46 PM PDT 24
Finished Jul 22 06:17:47 PM PDT 24
Peak memory 182140 kb
Host smart-fea69d25-2294-44f0-a491-e73f97ddb99b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385947930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.1385947930
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.2488409802
Short name T535
Test name
Test status
Simulation time 18406854 ps
CPU time 0.6 seconds
Started Jul 22 06:17:45 PM PDT 24
Finished Jul 22 06:17:46 PM PDT 24
Peak memory 191780 kb
Host smart-05f5ed76-6c64-4a86-821d-8cc28f3afb3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488409802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.2488409802
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.2903173297
Short name T493
Test name
Test status
Simulation time 274942125 ps
CPU time 1.82 seconds
Started Jul 22 06:17:42 PM PDT 24
Finished Jul 22 06:17:44 PM PDT 24
Peak memory 197308 kb
Host smart-51865abb-bdc0-4a6a-b02d-247328ae2189
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903173297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.2903173297
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.2766620568
Short name T544
Test name
Test status
Simulation time 213574443 ps
CPU time 1.09 seconds
Started Jul 22 06:17:43 PM PDT 24
Finished Jul 22 06:17:45 PM PDT 24
Peak memory 193976 kb
Host smart-26421565-7107-4d8c-a75a-163a5133d0e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766620568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.2766620568
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.392433252
Short name T575
Test name
Test status
Simulation time 113809436 ps
CPU time 0.9 seconds
Started Jul 22 06:17:55 PM PDT 24
Finished Jul 22 06:17:56 PM PDT 24
Peak memory 196736 kb
Host smart-3fd87b45-e68d-4ac5-a819-12b9f7cb8bcf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392433252 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.392433252
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.2357673707
Short name T531
Test name
Test status
Simulation time 12875055 ps
CPU time 0.58 seconds
Started Jul 22 06:17:56 PM PDT 24
Finished Jul 22 06:17:57 PM PDT 24
Peak memory 182428 kb
Host smart-ef408806-24f5-4743-b51b-72ad9aa8fc85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357673707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.2357673707
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.3989906430
Short name T550
Test name
Test status
Simulation time 32476027 ps
CPU time 0.52 seconds
Started Jul 22 06:17:56 PM PDT 24
Finished Jul 22 06:17:58 PM PDT 24
Peak memory 182160 kb
Host smart-c8d19990-ea61-46dd-bfc3-51aa421b4282
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989906430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.3989906430
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.1714023296
Short name T520
Test name
Test status
Simulation time 230069247 ps
CPU time 0.59 seconds
Started Jul 22 06:18:55 PM PDT 24
Finished Jul 22 06:18:57 PM PDT 24
Peak memory 191012 kb
Host smart-9e2b5edb-0d85-44cc-ad6c-2dbf0fc3fbc0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714023296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.1714023296
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.1041928843
Short name T504
Test name
Test status
Simulation time 96533144 ps
CPU time 1.92 seconds
Started Jul 22 06:17:40 PM PDT 24
Finished Jul 22 06:17:42 PM PDT 24
Peak memory 197292 kb
Host smart-42c58029-b9ab-42df-bd13-fce4fe7b623a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041928843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.1041928843
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.2288250436
Short name T491
Test name
Test status
Simulation time 77201217 ps
CPU time 1.06 seconds
Started Jul 22 06:17:54 PM PDT 24
Finished Jul 22 06:17:56 PM PDT 24
Peak memory 183188 kb
Host smart-00d3d199-7c95-4270-994c-5d039f5d26a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288250436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.2288250436
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.523727666
Short name T565
Test name
Test status
Simulation time 171994167 ps
CPU time 0.87 seconds
Started Jul 22 06:17:57 PM PDT 24
Finished Jul 22 06:17:59 PM PDT 24
Peak memory 196712 kb
Host smart-d0f0777a-d0f3-4215-aa9b-b94b1f2099b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523727666 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.523727666
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.2979861395
Short name T80
Test name
Test status
Simulation time 14567436 ps
CPU time 0.57 seconds
Started Jul 22 06:17:56 PM PDT 24
Finished Jul 22 06:17:58 PM PDT 24
Peak memory 182600 kb
Host smart-ddaa193b-181f-403a-a7a6-33af6fee0489
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979861395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.2979861395
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.1745722684
Short name T480
Test name
Test status
Simulation time 14380620 ps
CPU time 0.58 seconds
Started Jul 22 06:17:56 PM PDT 24
Finished Jul 22 06:17:57 PM PDT 24
Peak memory 182456 kb
Host smart-fa9dd677-4b06-4b12-85e2-64fd3b577b98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745722684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.1745722684
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.1981122021
Short name T526
Test name
Test status
Simulation time 42844447 ps
CPU time 0.67 seconds
Started Jul 22 06:17:58 PM PDT 24
Finished Jul 22 06:17:59 PM PDT 24
Peak memory 191532 kb
Host smart-156d0c87-c2d1-4282-96fc-686719608553
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981122021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.1981122021
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.96643654
Short name T472
Test name
Test status
Simulation time 783791928 ps
CPU time 2.4 seconds
Started Jul 22 06:17:54 PM PDT 24
Finished Jul 22 06:17:57 PM PDT 24
Peak memory 197340 kb
Host smart-596bf6d7-fa88-4ab7-a556-0a544716299d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96643654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.96643654
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.435057092
Short name T572
Test name
Test status
Simulation time 132548383 ps
CPU time 0.84 seconds
Started Jul 22 06:18:19 PM PDT 24
Finished Jul 22 06:18:20 PM PDT 24
Peak memory 193152 kb
Host smart-1173d54f-1d47-49c6-bbe3-27da0d1309b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435057092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_int
g_err.435057092
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3847192978
Short name T533
Test name
Test status
Simulation time 30310838 ps
CPU time 0.75 seconds
Started Jul 22 06:17:55 PM PDT 24
Finished Jul 22 06:17:57 PM PDT 24
Peak memory 195500 kb
Host smart-9f1ef7c8-f261-443c-80a2-30cb5645aea3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847192978 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.3847192978
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.515222705
Short name T490
Test name
Test status
Simulation time 25600861 ps
CPU time 0.63 seconds
Started Jul 22 06:17:57 PM PDT 24
Finished Jul 22 06:17:59 PM PDT 24
Peak memory 182608 kb
Host smart-26427ab1-46a7-4b04-83d3-0e9a7595107b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515222705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.515222705
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.3926590998
Short name T479
Test name
Test status
Simulation time 42620782 ps
CPU time 0.55 seconds
Started Jul 22 06:17:55 PM PDT 24
Finished Jul 22 06:17:56 PM PDT 24
Peak memory 182544 kb
Host smart-48cb186d-e990-48a7-915b-423d2971a512
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926590998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.3926590998
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.2547580836
Short name T497
Test name
Test status
Simulation time 31517831 ps
CPU time 0.76 seconds
Started Jul 22 06:18:16 PM PDT 24
Finished Jul 22 06:18:17 PM PDT 24
Peak memory 193356 kb
Host smart-527d3686-e8a8-4b0b-a1f5-24c5ba65305c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547580836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.2547580836
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.4120291153
Short name T549
Test name
Test status
Simulation time 534743718 ps
CPU time 2.24 seconds
Started Jul 22 06:17:56 PM PDT 24
Finished Jul 22 06:17:59 PM PDT 24
Peak memory 197304 kb
Host smart-2f5ea830-5c11-4ddc-a752-75ae52f8e1ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120291153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.4120291153
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.1970774471
Short name T481
Test name
Test status
Simulation time 436013606 ps
CPU time 1.11 seconds
Started Jul 22 06:17:54 PM PDT 24
Finished Jul 22 06:17:56 PM PDT 24
Peak memory 194744 kb
Host smart-b9043429-9eae-417b-bb62-7fe4dff8bace
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970774471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.1970774471
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.219088448
Short name T409
Test name
Test status
Simulation time 293630459101 ps
CPU time 238.35 seconds
Started Jul 22 06:59:25 PM PDT 24
Finished Jul 22 07:03:41 PM PDT 24
Peak memory 183604 kb
Host smart-c13873ee-7d51-4fcd-9332-0122496a6e35
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219088448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.rv_timer_cfg_update_on_fly.219088448
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.450529473
Short name T368
Test name
Test status
Simulation time 97824964550 ps
CPU time 139.71 seconds
Started Jul 22 07:00:32 PM PDT 24
Finished Jul 22 07:03:05 PM PDT 24
Peak memory 183544 kb
Host smart-e542efba-361d-4cee-8455-88640cbaf979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450529473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.450529473
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.2620120651
Short name T269
Test name
Test status
Simulation time 155567960957 ps
CPU time 76.13 seconds
Started Jul 22 06:59:25 PM PDT 24
Finished Jul 22 07:00:58 PM PDT 24
Peak memory 191780 kb
Host smart-9d090d9e-f4b0-419d-a05c-f3082991c6c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620120651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.2620120651
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.2128035737
Short name T374
Test name
Test status
Simulation time 229732465 ps
CPU time 0.84 seconds
Started Jul 22 06:59:29 PM PDT 24
Finished Jul 22 06:59:46 PM PDT 24
Peak memory 191984 kb
Host smart-4c8541b5-9de5-48d8-be33-aa41dec54755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128035737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.2128035737
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.1738263239
Short name T64
Test name
Test status
Simulation time 44760468778 ps
CPU time 60.44 seconds
Started Jul 22 06:59:23 PM PDT 24
Finished Jul 22 07:00:39 PM PDT 24
Peak memory 195284 kb
Host smart-88ba1b8a-fcb0-43d6-87ec-bbf07d3a638a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738263239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
1738263239
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.1435874111
Short name T142
Test name
Test status
Simulation time 802990122626 ps
CPU time 413.39 seconds
Started Jul 22 07:00:33 PM PDT 24
Finished Jul 22 07:07:40 PM PDT 24
Peak memory 183532 kb
Host smart-95757168-d0d2-4bb6-b3af-d4630e01720f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435874111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.1435874111
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.3106365227
Short name T382
Test name
Test status
Simulation time 84494162642 ps
CPU time 63.27 seconds
Started Jul 22 06:59:30 PM PDT 24
Finished Jul 22 07:00:50 PM PDT 24
Peak memory 183584 kb
Host smart-e278f14b-d73b-4061-9cc7-fa51aaea1010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106365227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.3106365227
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.2051484674
Short name T187
Test name
Test status
Simulation time 32789043953 ps
CPU time 45.82 seconds
Started Jul 22 06:59:30 PM PDT 24
Finished Jul 22 07:00:32 PM PDT 24
Peak memory 183424 kb
Host smart-f91028bc-ed87-4e89-85ae-e1eee84e2da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051484674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.2051484674
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.3908841269
Short name T19
Test name
Test status
Simulation time 38536234 ps
CPU time 0.75 seconds
Started Jul 22 06:59:24 PM PDT 24
Finished Jul 22 06:59:40 PM PDT 24
Peak memory 214564 kb
Host smart-8ed46aa2-9cbf-4504-9891-95aa133f5f35
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908841269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.3908841269
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.3433068941
Short name T375
Test name
Test status
Simulation time 1469863115363 ps
CPU time 587.74 seconds
Started Jul 22 06:59:23 PM PDT 24
Finished Jul 22 07:09:27 PM PDT 24
Peak memory 196180 kb
Host smart-78e62a62-f16b-4920-b652-c6085eda558d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433068941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
3433068941
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.1032163805
Short name T272
Test name
Test status
Simulation time 68496350288 ps
CPU time 38.67 seconds
Started Jul 22 06:59:42 PM PDT 24
Finished Jul 22 07:00:35 PM PDT 24
Peak memory 183640 kb
Host smart-c593f64e-e2e7-4aae-bada-2c63b403ee44
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032163805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.1032163805
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.286492121
Short name T424
Test name
Test status
Simulation time 61476037823 ps
CPU time 85.26 seconds
Started Jul 22 06:59:34 PM PDT 24
Finished Jul 22 07:01:15 PM PDT 24
Peak memory 183588 kb
Host smart-db14bdb8-435f-4e07-8f32-8a3fd14b3878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286492121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.286492121
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.1974905308
Short name T137
Test name
Test status
Simulation time 430654428881 ps
CPU time 300.16 seconds
Started Jul 22 07:01:00 PM PDT 24
Finished Jul 22 07:06:03 PM PDT 24
Peak memory 191776 kb
Host smart-ef5c8fe5-e691-4b55-8fba-55b7f557deac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974905308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.1974905308
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.3571791462
Short name T285
Test name
Test status
Simulation time 278754783008 ps
CPU time 111.21 seconds
Started Jul 22 06:59:41 PM PDT 24
Finished Jul 22 07:01:47 PM PDT 24
Peak memory 195140 kb
Host smart-703982d4-51bc-432e-8146-6d8a504e032e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571791462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.3571791462
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.3689972167
Short name T34
Test name
Test status
Simulation time 2261967067238 ps
CPU time 977.76 seconds
Started Jul 22 06:59:49 PM PDT 24
Finished Jul 22 07:16:18 PM PDT 24
Peak memory 191836 kb
Host smart-205145f0-3dac-4066-b3b0-7c32479b1f89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689972167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.3689972167
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/100.rv_timer_random.2248499680
Short name T178
Test name
Test status
Simulation time 238192876845 ps
CPU time 102.95 seconds
Started Jul 22 07:00:59 PM PDT 24
Finished Jul 22 07:02:45 PM PDT 24
Peak memory 191780 kb
Host smart-4b2e2b5e-c4c9-4675-96c9-a0c6590765fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248499680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.2248499680
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.3670341128
Short name T196
Test name
Test status
Simulation time 8391520927 ps
CPU time 13.01 seconds
Started Jul 22 07:00:54 PM PDT 24
Finished Jul 22 07:01:12 PM PDT 24
Peak memory 183656 kb
Host smart-b8f22224-1ab1-4148-9a5f-e8c60cdef636
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670341128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.3670341128
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.1891206530
Short name T433
Test name
Test status
Simulation time 109019396892 ps
CPU time 533.2 seconds
Started Jul 22 07:00:59 PM PDT 24
Finished Jul 22 07:09:56 PM PDT 24
Peak memory 191772 kb
Host smart-15c7e383-39d4-4ac0-9800-f180c5796761
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891206530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.1891206530
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.2336628703
Short name T344
Test name
Test status
Simulation time 1561664899 ps
CPU time 3.18 seconds
Started Jul 22 07:02:35 PM PDT 24
Finished Jul 22 07:02:40 PM PDT 24
Peak memory 183320 kb
Host smart-fc2cbc38-c2ff-465c-9742-b77463f15a95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336628703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.2336628703
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.784400417
Short name T225
Test name
Test status
Simulation time 79422167117 ps
CPU time 120 seconds
Started Jul 22 07:00:55 PM PDT 24
Finished Jul 22 07:03:00 PM PDT 24
Peak memory 191724 kb
Host smart-f2cfeb84-8776-457a-a1a1-9bc0d61b46b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784400417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.784400417
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.2250135627
Short name T404
Test name
Test status
Simulation time 107442176936 ps
CPU time 61.2 seconds
Started Jul 22 07:00:53 PM PDT 24
Finished Jul 22 07:01:59 PM PDT 24
Peak memory 183572 kb
Host smart-1ac95b9c-df8b-470c-95c8-4b0b5caf78ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250135627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.2250135627
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.2058192717
Short name T414
Test name
Test status
Simulation time 28025467620 ps
CPU time 47.55 seconds
Started Jul 22 07:01:35 PM PDT 24
Finished Jul 22 07:02:26 PM PDT 24
Peak memory 183592 kb
Host smart-c4bb43ce-4c46-42bb-97af-19e56c9e9adc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058192717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.2058192717
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.4026936900
Short name T245
Test name
Test status
Simulation time 146259683934 ps
CPU time 255.15 seconds
Started Jul 22 06:59:48 PM PDT 24
Finished Jul 22 07:04:15 PM PDT 24
Peak memory 183620 kb
Host smart-d7e3e311-de7c-4a4d-9a4c-5d2837dd9ae6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026936900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.4026936900
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.1182851542
Short name T373
Test name
Test status
Simulation time 280602108039 ps
CPU time 182.65 seconds
Started Jul 22 06:59:50 PM PDT 24
Finished Jul 22 07:03:05 PM PDT 24
Peak memory 183600 kb
Host smart-53c23da0-4503-407a-8ada-66a6ed06892e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182851542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.1182851542
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.238089724
Short name T338
Test name
Test status
Simulation time 422342643002 ps
CPU time 989 seconds
Started Jul 22 06:59:51 PM PDT 24
Finished Jul 22 07:16:31 PM PDT 24
Peak memory 195224 kb
Host smart-5abee26e-5b74-4f09-b3d3-a68edd12c780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238089724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.238089724
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/111.rv_timer_random.3463821539
Short name T161
Test name
Test status
Simulation time 255005714841 ps
CPU time 582.48 seconds
Started Jul 22 07:00:55 PM PDT 24
Finished Jul 22 07:10:42 PM PDT 24
Peak memory 191832 kb
Host smart-e5e7106c-c334-4ced-bf09-4258f14287d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463821539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.3463821539
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.2385573347
Short name T130
Test name
Test status
Simulation time 113462262812 ps
CPU time 383.12 seconds
Started Jul 22 07:01:35 PM PDT 24
Finished Jul 22 07:08:01 PM PDT 24
Peak memory 191792 kb
Host smart-d88c0e6f-8d97-44d4-abfe-bdf859ac6daf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385573347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.2385573347
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.1725465323
Short name T176
Test name
Test status
Simulation time 9080979107 ps
CPU time 27 seconds
Started Jul 22 07:00:52 PM PDT 24
Finished Jul 22 07:01:25 PM PDT 24
Peak memory 183572 kb
Host smart-fd785271-9f16-4c52-adb0-dd3a770b0838
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725465323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.1725465323
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.3063461818
Short name T218
Test name
Test status
Simulation time 169945801820 ps
CPU time 66.08 seconds
Started Jul 22 07:00:55 PM PDT 24
Finished Jul 22 07:02:06 PM PDT 24
Peak memory 191768 kb
Host smart-e6f28db4-ab9d-4b98-b9be-431559a2d4dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063461818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.3063461818
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.3376100911
Short name T250
Test name
Test status
Simulation time 83656264510 ps
CPU time 108.71 seconds
Started Jul 22 07:00:54 PM PDT 24
Finished Jul 22 07:02:47 PM PDT 24
Peak memory 191820 kb
Host smart-6259d0f3-efe6-4840-bb2e-5fa196e44887
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376100911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.3376100911
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.2750178714
Short name T221
Test name
Test status
Simulation time 64929388770 ps
CPU time 35.56 seconds
Started Jul 22 07:00:53 PM PDT 24
Finished Jul 22 07:01:34 PM PDT 24
Peak memory 191852 kb
Host smart-a8102854-0820-4dfc-b614-e4f3b656c707
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750178714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.2750178714
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.118192938
Short name T316
Test name
Test status
Simulation time 940674053814 ps
CPU time 555.58 seconds
Started Jul 22 06:59:49 PM PDT 24
Finished Jul 22 07:09:16 PM PDT 24
Peak memory 183564 kb
Host smart-ec4c75c4-7873-40fb-bbac-e347f91c9df7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118192938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.rv_timer_cfg_update_on_fly.118192938
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.4265988362
Short name T86
Test name
Test status
Simulation time 6163797901 ps
CPU time 6.1 seconds
Started Jul 22 06:59:50 PM PDT 24
Finished Jul 22 07:00:07 PM PDT 24
Peak memory 183464 kb
Host smart-22f8f7c2-64a2-4ba0-9abf-a46dbe9a9e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265988362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.4265988362
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.2644780223
Short name T73
Test name
Test status
Simulation time 63571258560 ps
CPU time 48.94 seconds
Started Jul 22 06:59:50 PM PDT 24
Finished Jul 22 07:00:51 PM PDT 24
Peak memory 183592 kb
Host smart-c5421171-fc3e-44fb-83ac-07f4b1d91dd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644780223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.2644780223
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.3338489940
Short name T350
Test name
Test status
Simulation time 193273177625 ps
CPU time 188.75 seconds
Started Jul 22 06:59:49 PM PDT 24
Finished Jul 22 07:03:09 PM PDT 24
Peak memory 191780 kb
Host smart-b751c1c3-2bfb-43cd-b071-0b2c035de8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338489940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.3338489940
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/121.rv_timer_random.271286382
Short name T159
Test name
Test status
Simulation time 83610165408 ps
CPU time 56.07 seconds
Started Jul 22 07:00:55 PM PDT 24
Finished Jul 22 07:01:55 PM PDT 24
Peak memory 191712 kb
Host smart-50694c0e-8be3-4380-8492-4690da07169b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271286382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.271286382
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.3376332070
Short name T132
Test name
Test status
Simulation time 986495417630 ps
CPU time 1018.35 seconds
Started Jul 22 07:00:55 PM PDT 24
Finished Jul 22 07:17:58 PM PDT 24
Peak memory 191784 kb
Host smart-317abc33-23aa-4736-92fb-e871d2a45931
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376332070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.3376332070
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.2950123148
Short name T124
Test name
Test status
Simulation time 134024938196 ps
CPU time 256.98 seconds
Started Jul 22 07:00:53 PM PDT 24
Finished Jul 22 07:05:15 PM PDT 24
Peak memory 191676 kb
Host smart-538a356b-1fa2-4914-bb14-781a705529c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950123148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.2950123148
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.3936391225
Short name T334
Test name
Test status
Simulation time 148444044864 ps
CPU time 139.95 seconds
Started Jul 22 07:01:02 PM PDT 24
Finished Jul 22 07:03:24 PM PDT 24
Peak memory 191788 kb
Host smart-902af2f9-a853-43e8-a63b-2c7182cadd5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936391225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.3936391225
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.632343301
Short name T76
Test name
Test status
Simulation time 84292052578 ps
CPU time 74.35 seconds
Started Jul 22 07:00:55 PM PDT 24
Finished Jul 22 07:02:14 PM PDT 24
Peak memory 183524 kb
Host smart-a7ca7e5a-3ea4-4e45-810b-c15ffc400745
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632343301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.632343301
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.3430666343
Short name T231
Test name
Test status
Simulation time 120875827578 ps
CPU time 426.77 seconds
Started Jul 22 07:00:59 PM PDT 24
Finished Jul 22 07:08:09 PM PDT 24
Peak memory 195392 kb
Host smart-26a7ae88-4371-41cc-8694-18d09c7d3906
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430666343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.3430666343
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.3107668783
Short name T204
Test name
Test status
Simulation time 406283957708 ps
CPU time 151.45 seconds
Started Jul 22 07:01:09 PM PDT 24
Finished Jul 22 07:03:43 PM PDT 24
Peak memory 191768 kb
Host smart-118fd335-b639-470d-9cf2-ca883113d225
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107668783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.3107668783
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.2839560304
Short name T208
Test name
Test status
Simulation time 159395344134 ps
CPU time 130.17 seconds
Started Jul 22 07:01:11 PM PDT 24
Finished Jul 22 07:03:25 PM PDT 24
Peak memory 191784 kb
Host smart-e657a50f-17f4-498e-8b15-78d0d28eeda4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839560304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.2839560304
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.2801989035
Short name T400
Test name
Test status
Simulation time 48643997606 ps
CPU time 33.42 seconds
Started Jul 22 07:00:04 PM PDT 24
Finished Jul 22 07:00:47 PM PDT 24
Peak memory 183572 kb
Host smart-c6148069-902f-4593-aa2d-92a613b79c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801989035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.2801989035
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.1898929695
Short name T195
Test name
Test status
Simulation time 29140012866 ps
CPU time 49.25 seconds
Started Jul 22 06:59:52 PM PDT 24
Finished Jul 22 07:00:52 PM PDT 24
Peak memory 183584 kb
Host smart-487d9ee4-04ba-49c5-8e84-bcbba9e87fc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898929695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.1898929695
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.3384845513
Short name T122
Test name
Test status
Simulation time 70488028047 ps
CPU time 318.34 seconds
Started Jul 22 06:59:51 PM PDT 24
Finished Jul 22 07:05:21 PM PDT 24
Peak memory 191796 kb
Host smart-c7eb08e3-b296-4d4b-a306-fe67ebac3ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384845513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.3384845513
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.2140808114
Short name T276
Test name
Test status
Simulation time 959631608836 ps
CPU time 265.16 seconds
Started Jul 22 07:02:03 PM PDT 24
Finished Jul 22 07:06:30 PM PDT 24
Peak memory 191800 kb
Host smart-8b2a15a7-7fa8-400f-bf6d-254c77f59d06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140808114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.2140808114
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.2721085789
Short name T89
Test name
Test status
Simulation time 73542338711 ps
CPU time 1176.44 seconds
Started Jul 22 07:02:32 PM PDT 24
Finished Jul 22 07:22:11 PM PDT 24
Peak memory 191776 kb
Host smart-3fea463e-3ca4-4dc0-be28-e5cf0868b0dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721085789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.2721085789
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.4253363363
Short name T205
Test name
Test status
Simulation time 66305526917 ps
CPU time 316.2 seconds
Started Jul 22 07:01:11 PM PDT 24
Finished Jul 22 07:06:31 PM PDT 24
Peak memory 191748 kb
Host smart-b29b560a-0903-40b8-b33b-ef050c1bbb0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253363363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.4253363363
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.527812865
Short name T128
Test name
Test status
Simulation time 369624785254 ps
CPU time 457.71 seconds
Started Jul 22 07:01:12 PM PDT 24
Finished Jul 22 07:08:54 PM PDT 24
Peak memory 191784 kb
Host smart-0276e221-4cae-4564-b2f2-f12aedaa2069
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527812865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.527812865
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.806626237
Short name T42
Test name
Test status
Simulation time 20382371797 ps
CPU time 187.6 seconds
Started Jul 22 07:01:11 PM PDT 24
Finished Jul 22 07:04:23 PM PDT 24
Peak memory 183648 kb
Host smart-eda36eca-a3b5-4fa6-a48c-180de3f72daa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806626237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.806626237
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.870447772
Short name T200
Test name
Test status
Simulation time 165974180519 ps
CPU time 846.21 seconds
Started Jul 22 07:01:10 PM PDT 24
Finished Jul 22 07:15:20 PM PDT 24
Peak memory 191776 kb
Host smart-a3247006-b03b-41a4-ae8c-70cdd7d31559
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870447772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.870447772
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.132142835
Short name T57
Test name
Test status
Simulation time 408849415481 ps
CPU time 1370.82 seconds
Started Jul 22 07:01:10 PM PDT 24
Finished Jul 22 07:24:04 PM PDT 24
Peak memory 191780 kb
Host smart-0b3532d3-bc17-4658-b370-1f453a13143a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132142835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.132142835
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.3905955201
Short name T240
Test name
Test status
Simulation time 538901841657 ps
CPU time 907.49 seconds
Started Jul 22 06:59:50 PM PDT 24
Finished Jul 22 07:15:09 PM PDT 24
Peak memory 183628 kb
Host smart-5add4145-05d8-4e32-a102-95b2102bf8a3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905955201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.3905955201
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.2895572395
Short name T1
Test name
Test status
Simulation time 32052901331 ps
CPU time 42.6 seconds
Started Jul 22 06:59:50 PM PDT 24
Finished Jul 22 07:00:44 PM PDT 24
Peak memory 183536 kb
Host smart-3c0406d4-e058-445a-b99d-9908efdd9d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895572395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.2895572395
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.2314719348
Short name T97
Test name
Test status
Simulation time 148835121617 ps
CPU time 1106.23 seconds
Started Jul 22 06:59:49 PM PDT 24
Finished Jul 22 07:18:27 PM PDT 24
Peak memory 191764 kb
Host smart-573d51c9-25ef-4b29-a7c2-efaf17cf09b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314719348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.2314719348
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.3120769390
Short name T401
Test name
Test status
Simulation time 5126757488 ps
CPU time 9.59 seconds
Started Jul 22 06:59:52 PM PDT 24
Finished Jul 22 07:00:13 PM PDT 24
Peak memory 191752 kb
Host smart-a35879e7-7628-4103-b365-134740f7c0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120769390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.3120769390
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/142.rv_timer_random.615622025
Short name T354
Test name
Test status
Simulation time 100026049493 ps
CPU time 187.25 seconds
Started Jul 22 07:01:24 PM PDT 24
Finished Jul 22 07:04:35 PM PDT 24
Peak memory 191792 kb
Host smart-58448802-3f6c-4b3d-9e2d-35ebd506c7fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615622025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.615622025
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.2776636635
Short name T127
Test name
Test status
Simulation time 840768651675 ps
CPU time 179.68 seconds
Started Jul 22 07:01:24 PM PDT 24
Finished Jul 22 07:04:27 PM PDT 24
Peak memory 191776 kb
Host smart-5c9fe359-6233-47c4-9bdb-328830568abd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776636635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.2776636635
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.3074083489
Short name T261
Test name
Test status
Simulation time 90678047022 ps
CPU time 267.11 seconds
Started Jul 22 07:01:23 PM PDT 24
Finished Jul 22 07:05:54 PM PDT 24
Peak memory 183508 kb
Host smart-057a6736-bfbf-4f84-89d8-71aaac576af4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074083489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.3074083489
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.3003740141
Short name T75
Test name
Test status
Simulation time 457965527338 ps
CPU time 156.91 seconds
Started Jul 22 07:02:35 PM PDT 24
Finished Jul 22 07:05:14 PM PDT 24
Peak memory 193816 kb
Host smart-3d006615-e8f0-4bc8-8f49-f33892a7d32d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003740141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.3003740141
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.3743940731
Short name T151
Test name
Test status
Simulation time 123292294098 ps
CPU time 206.59 seconds
Started Jul 22 07:02:27 PM PDT 24
Finished Jul 22 07:05:59 PM PDT 24
Peak memory 191732 kb
Host smart-286e6b7b-840f-4171-8dca-6258832fe16e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743940731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.3743940731
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.3204141738
Short name T202
Test name
Test status
Simulation time 177803132800 ps
CPU time 258.5 seconds
Started Jul 22 07:01:23 PM PDT 24
Finished Jul 22 07:05:46 PM PDT 24
Peak memory 191820 kb
Host smart-436d96e3-451c-4aa5-820f-709a57713407
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204141738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.3204141738
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.1924963969
Short name T133
Test name
Test status
Simulation time 15033511499 ps
CPU time 31.63 seconds
Started Jul 22 07:01:24 PM PDT 24
Finished Jul 22 07:02:00 PM PDT 24
Peak memory 183600 kb
Host smart-d8f97a90-0ae1-45f9-9874-e705f766827b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924963969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.1924963969
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.1659274259
Short name T383
Test name
Test status
Simulation time 30934394598 ps
CPU time 13.89 seconds
Started Jul 22 06:59:51 PM PDT 24
Finished Jul 22 07:00:16 PM PDT 24
Peak memory 183592 kb
Host smart-d4c79d45-8a0e-4d30-96d5-0c1ce04ecf21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659274259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.1659274259
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.643831358
Short name T395
Test name
Test status
Simulation time 17738797247 ps
CPU time 54.86 seconds
Started Jul 22 06:59:52 PM PDT 24
Finished Jul 22 07:00:58 PM PDT 24
Peak memory 183548 kb
Host smart-e3e6a1fc-4541-43cb-9a28-2bbf400b46d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643831358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.643831358
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.4202151740
Short name T388
Test name
Test status
Simulation time 36748280 ps
CPU time 0.52 seconds
Started Jul 22 06:59:59 PM PDT 24
Finished Jul 22 07:00:08 PM PDT 24
Peak memory 182960 kb
Host smart-fc54bbcc-a829-46ed-816f-88f24fe0fef5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202151740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.4202151740
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/150.rv_timer_random.1056267079
Short name T320
Test name
Test status
Simulation time 162486207962 ps
CPU time 1111.17 seconds
Started Jul 22 07:01:25 PM PDT 24
Finished Jul 22 07:20:00 PM PDT 24
Peak memory 191832 kb
Host smart-23e578d1-8380-4e6b-aea6-96e12cea094d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056267079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.1056267079
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.2882850530
Short name T355
Test name
Test status
Simulation time 328318896494 ps
CPU time 824.02 seconds
Started Jul 22 07:01:24 PM PDT 24
Finished Jul 22 07:15:12 PM PDT 24
Peak memory 191784 kb
Host smart-00c41927-b747-4224-9653-5938d25c65de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882850530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.2882850530
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.2856958512
Short name T286
Test name
Test status
Simulation time 400921889512 ps
CPU time 203.02 seconds
Started Jul 22 07:01:23 PM PDT 24
Finished Jul 22 07:04:50 PM PDT 24
Peak memory 191820 kb
Host smart-425605b6-92b4-4096-8432-88ab2a263b8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856958512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.2856958512
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.1363959599
Short name T328
Test name
Test status
Simulation time 205558282021 ps
CPU time 128 seconds
Started Jul 22 07:01:25 PM PDT 24
Finished Jul 22 07:03:37 PM PDT 24
Peak memory 191772 kb
Host smart-70a7eeae-6788-42ad-a9a3-4871b8159cd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363959599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.1363959599
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.3891812480
Short name T385
Test name
Test status
Simulation time 84709874090 ps
CPU time 80.46 seconds
Started Jul 22 07:01:25 PM PDT 24
Finished Jul 22 07:02:49 PM PDT 24
Peak memory 183536 kb
Host smart-7af25d1a-4314-4b64-ada9-00ce7921ceaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891812480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.3891812480
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.2085922200
Short name T322
Test name
Test status
Simulation time 256949073790 ps
CPU time 385.24 seconds
Started Jul 22 07:01:25 PM PDT 24
Finished Jul 22 07:07:54 PM PDT 24
Peak memory 183548 kb
Host smart-7d978f06-eee8-4e35-9bde-dd721da0b857
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085922200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.2085922200
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.2674709227
Short name T429
Test name
Test status
Simulation time 39661438970 ps
CPU time 325.5 seconds
Started Jul 22 07:01:24 PM PDT 24
Finished Jul 22 07:06:53 PM PDT 24
Peak memory 183552 kb
Host smart-c658d66e-49c9-4f75-aabc-16ee46028c25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674709227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.2674709227
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.4275378132
Short name T371
Test name
Test status
Simulation time 178735801126 ps
CPU time 249.85 seconds
Started Jul 22 07:00:03 PM PDT 24
Finished Jul 22 07:04:21 PM PDT 24
Peak memory 183600 kb
Host smart-652b758b-d7f7-4ed6-bd21-80ecd148f5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275378132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.4275378132
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.1006125172
Short name T432
Test name
Test status
Simulation time 322223333 ps
CPU time 0.97 seconds
Started Jul 22 06:59:51 PM PDT 24
Finished Jul 22 07:00:04 PM PDT 24
Peak memory 183532 kb
Host smart-6a6cff1a-2265-4081-a2cb-0b574abb3f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006125172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.1006125172
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.2462570525
Short name T162
Test name
Test status
Simulation time 649854132481 ps
CPU time 1264.39 seconds
Started Jul 22 07:00:13 PM PDT 24
Finished Jul 22 07:21:33 PM PDT 24
Peak memory 191784 kb
Host smart-84d1007a-21f8-4765-a3d4-46431f758a63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462570525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.2462570525
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/161.rv_timer_random.316246123
Short name T237
Test name
Test status
Simulation time 91087308769 ps
CPU time 572.24 seconds
Started Jul 22 07:01:25 PM PDT 24
Finished Jul 22 07:11:01 PM PDT 24
Peak memory 183588 kb
Host smart-17ed30b5-4f20-43a1-b962-930cc89e646d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316246123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.316246123
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.78211273
Short name T219
Test name
Test status
Simulation time 153341181548 ps
CPU time 120.99 seconds
Started Jul 22 07:01:24 PM PDT 24
Finished Jul 22 07:03:29 PM PDT 24
Peak memory 191788 kb
Host smart-17c479da-ea74-4a00-a372-a09c5f4b6b86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78211273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.78211273
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.3814778102
Short name T294
Test name
Test status
Simulation time 78465018627 ps
CPU time 46.13 seconds
Started Jul 22 07:01:25 PM PDT 24
Finished Jul 22 07:02:15 PM PDT 24
Peak memory 191788 kb
Host smart-a3ca6ff8-5370-4e8d-97c3-7ba99d869b9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814778102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.3814778102
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.4287436344
Short name T229
Test name
Test status
Simulation time 160413672334 ps
CPU time 402.34 seconds
Started Jul 22 07:02:14 PM PDT 24
Finished Jul 22 07:08:59 PM PDT 24
Peak memory 191800 kb
Host smart-a3355b08-7d9d-4a2d-9ffc-8ee320c2d498
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287436344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.4287436344
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.1804462790
Short name T180
Test name
Test status
Simulation time 65459828350 ps
CPU time 37.87 seconds
Started Jul 22 07:03:57 PM PDT 24
Finished Jul 22 07:04:37 PM PDT 24
Peak memory 183588 kb
Host smart-a6b8222a-8367-494a-95c2-de4f95b84ffa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804462790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.1804462790
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.2814081932
Short name T215
Test name
Test status
Simulation time 72793410839 ps
CPU time 101.23 seconds
Started Jul 22 07:01:25 PM PDT 24
Finished Jul 22 07:03:10 PM PDT 24
Peak memory 195448 kb
Host smart-73bf791c-c1e1-46f4-b0ea-a8a2fd1611d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814081932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.2814081932
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.3224170142
Short name T41
Test name
Test status
Simulation time 73514615206 ps
CPU time 36.44 seconds
Started Jul 22 06:59:58 PM PDT 24
Finished Jul 22 07:00:44 PM PDT 24
Peak memory 183552 kb
Host smart-b3553489-9d77-445d-8a19-cefa8b61ed4d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224170142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.3224170142
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.171951178
Short name T377
Test name
Test status
Simulation time 189127384301 ps
CPU time 272.24 seconds
Started Jul 22 06:59:59 PM PDT 24
Finished Jul 22 07:04:40 PM PDT 24
Peak memory 183544 kb
Host smart-40e34a83-a285-4602-bbc5-3f3ff61fdfab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171951178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.171951178
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.2936297784
Short name T259
Test name
Test status
Simulation time 187367611535 ps
CPU time 113.14 seconds
Started Jul 22 06:59:59 PM PDT 24
Finished Jul 22 07:02:01 PM PDT 24
Peak memory 191784 kb
Host smart-41d651c6-f40b-4cf8-937a-45af607712a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936297784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.2936297784
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.3903367688
Short name T359
Test name
Test status
Simulation time 37480113529 ps
CPU time 1045.16 seconds
Started Jul 22 07:00:19 PM PDT 24
Finished Jul 22 07:18:00 PM PDT 24
Peak memory 191760 kb
Host smart-45c3b9e4-41a0-4b60-bef6-f1476353ce50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903367688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.3903367688
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.1603189788
Short name T71
Test name
Test status
Simulation time 2489921860123 ps
CPU time 681.25 seconds
Started Jul 22 06:59:58 PM PDT 24
Finished Jul 22 07:11:28 PM PDT 24
Peak memory 191712 kb
Host smart-cbf28e18-90ec-4156-ab76-50e375ab0fce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603189788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.1603189788
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/170.rv_timer_random.2773133519
Short name T227
Test name
Test status
Simulation time 173262576628 ps
CPU time 142.02 seconds
Started Jul 22 07:03:57 PM PDT 24
Finished Jul 22 07:06:22 PM PDT 24
Peak memory 195328 kb
Host smart-f7988259-0b90-423d-869c-cb42fd71ea44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773133519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.2773133519
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.2224300083
Short name T287
Test name
Test status
Simulation time 192806256162 ps
CPU time 61.23 seconds
Started Jul 22 07:01:30 PM PDT 24
Finished Jul 22 07:02:34 PM PDT 24
Peak memory 183584 kb
Host smart-f06f9b42-3f78-4060-ae15-708d1ec184db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224300083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.2224300083
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.874761656
Short name T307
Test name
Test status
Simulation time 211636205896 ps
CPU time 204.36 seconds
Started Jul 22 07:01:30 PM PDT 24
Finished Jul 22 07:04:57 PM PDT 24
Peak memory 191784 kb
Host smart-99ad76cc-339e-41af-ac2c-6d3c42f433b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874761656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.874761656
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.3442549292
Short name T442
Test name
Test status
Simulation time 563486503442 ps
CPU time 1360.43 seconds
Started Jul 22 07:04:06 PM PDT 24
Finished Jul 22 07:26:52 PM PDT 24
Peak memory 191788 kb
Host smart-9e0fa61a-b977-4bde-a06f-8a6732eff3db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442549292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.3442549292
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.2949423965
Short name T52
Test name
Test status
Simulation time 328140966756 ps
CPU time 1481.8 seconds
Started Jul 22 07:02:47 PM PDT 24
Finished Jul 22 07:27:30 PM PDT 24
Peak memory 191776 kb
Host smart-52438e1a-5974-4083-a400-aa2b5942a436
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949423965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.2949423965
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.4160556631
Short name T179
Test name
Test status
Simulation time 539645142230 ps
CPU time 411.81 seconds
Started Jul 22 07:01:35 PM PDT 24
Finished Jul 22 07:08:29 PM PDT 24
Peak memory 191752 kb
Host smart-842e5f5f-7d74-4cd8-929c-b7bc4500b6fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160556631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.4160556631
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.806113983
Short name T390
Test name
Test status
Simulation time 11942611012 ps
CPU time 12.19 seconds
Started Jul 22 07:01:42 PM PDT 24
Finished Jul 22 07:01:56 PM PDT 24
Peak memory 183584 kb
Host smart-010f6757-4491-436d-9a4d-6b9de07414a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806113983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.806113983
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.4028119651
Short name T216
Test name
Test status
Simulation time 280962382561 ps
CPU time 109.27 seconds
Started Jul 22 07:01:36 PM PDT 24
Finished Jul 22 07:03:27 PM PDT 24
Peak memory 191776 kb
Host smart-95ebbde0-bc06-4e0d-ac87-5bb076c6022d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028119651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.4028119651
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.1731658472
Short name T289
Test name
Test status
Simulation time 97135874028 ps
CPU time 455.82 seconds
Started Jul 22 07:01:56 PM PDT 24
Finished Jul 22 07:09:35 PM PDT 24
Peak memory 191776 kb
Host smart-502b2ac8-14b5-4fdb-8065-7aae55a8ec4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731658472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.1731658472
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.1578945043
Short name T193
Test name
Test status
Simulation time 6788294753 ps
CPU time 8.38 seconds
Started Jul 22 07:00:17 PM PDT 24
Finished Jul 22 07:00:41 PM PDT 24
Peak memory 183592 kb
Host smart-ea37928a-d289-4a45-8a78-93921485f54d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578945043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.1578945043
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.278432587
Short name T402
Test name
Test status
Simulation time 150387229123 ps
CPU time 203.63 seconds
Started Jul 22 07:00:02 PM PDT 24
Finished Jul 22 07:03:34 PM PDT 24
Peak memory 183480 kb
Host smart-aface093-d02c-4fa1-a3b6-a8acda41d501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278432587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.278432587
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.1353420854
Short name T384
Test name
Test status
Simulation time 123851404 ps
CPU time 1.68 seconds
Started Jul 22 06:59:58 PM PDT 24
Finished Jul 22 07:00:09 PM PDT 24
Peak memory 183568 kb
Host smart-67c21fe1-de82-43c4-b910-4826a0f53dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353420854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.1353420854
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/182.rv_timer_random.3769366115
Short name T343
Test name
Test status
Simulation time 297432010535 ps
CPU time 397.43 seconds
Started Jul 22 07:01:38 PM PDT 24
Finished Jul 22 07:08:19 PM PDT 24
Peak memory 191844 kb
Host smart-97ec80b4-fe59-4047-9ecc-59ece27303bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769366115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.3769366115
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.1720308204
Short name T277
Test name
Test status
Simulation time 87351441159 ps
CPU time 40.08 seconds
Started Jul 22 07:01:36 PM PDT 24
Finished Jul 22 07:02:19 PM PDT 24
Peak memory 183528 kb
Host smart-ea860f7a-489b-4269-9884-4ab51927c257
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720308204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.1720308204
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.1422075646
Short name T280
Test name
Test status
Simulation time 66579357526 ps
CPU time 64.76 seconds
Started Jul 22 07:01:36 PM PDT 24
Finished Jul 22 07:02:43 PM PDT 24
Peak memory 183580 kb
Host smart-686f1888-0644-4a5d-8cdf-4a20a0ce38ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422075646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.1422075646
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.1385587120
Short name T4
Test name
Test status
Simulation time 74817542012 ps
CPU time 98.66 seconds
Started Jul 22 07:01:41 PM PDT 24
Finished Jul 22 07:03:21 PM PDT 24
Peak memory 191784 kb
Host smart-8220ce7c-870a-4636-9cfb-3ad50ea65fa8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385587120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.1385587120
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.2810046371
Short name T362
Test name
Test status
Simulation time 152089064378 ps
CPU time 118.04 seconds
Started Jul 22 07:00:19 PM PDT 24
Finished Jul 22 07:02:33 PM PDT 24
Peak memory 183552 kb
Host smart-0a4a19d9-ee1c-464a-858a-cab0ddf551e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810046371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.2810046371
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.3296259793
Short name T232
Test name
Test status
Simulation time 99542207585 ps
CPU time 184.13 seconds
Started Jul 22 06:59:58 PM PDT 24
Finished Jul 22 07:03:11 PM PDT 24
Peak memory 191776 kb
Host smart-2470a224-8f13-4398-b6e4-373d82ace48c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296259793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.3296259793
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.2830547436
Short name T444
Test name
Test status
Simulation time 161601229 ps
CPU time 1.58 seconds
Started Jul 22 06:59:58 PM PDT 24
Finished Jul 22 07:00:09 PM PDT 24
Peak memory 191712 kb
Host smart-821e8116-5f0c-4ed4-8655-9d0e3dfd1685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830547436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.2830547436
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.1795655320
Short name T220
Test name
Test status
Simulation time 2369760983474 ps
CPU time 1221.76 seconds
Started Jul 22 07:00:01 PM PDT 24
Finished Jul 22 07:20:32 PM PDT 24
Peak memory 191676 kb
Host smart-5a1f332f-32fe-4f33-9c26-c1cc51885bba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795655320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.1795655320
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/190.rv_timer_random.2279029278
Short name T143
Test name
Test status
Simulation time 173581598042 ps
CPU time 90.07 seconds
Started Jul 22 07:01:37 PM PDT 24
Finished Jul 22 07:03:10 PM PDT 24
Peak memory 183524 kb
Host smart-bcbf8eab-dbf9-4089-928a-c52e1a050e2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279029278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.2279029278
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.1616513693
Short name T23
Test name
Test status
Simulation time 86702218677 ps
CPU time 146.51 seconds
Started Jul 22 07:01:35 PM PDT 24
Finished Jul 22 07:04:04 PM PDT 24
Peak memory 191780 kb
Host smart-b45ca4d6-4604-4837-8466-225fd478ce4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616513693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.1616513693
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.383892616
Short name T283
Test name
Test status
Simulation time 108176281547 ps
CPU time 181.5 seconds
Started Jul 22 07:01:56 PM PDT 24
Finished Jul 22 07:05:00 PM PDT 24
Peak memory 191716 kb
Host smart-53ae8924-fbbe-4670-b6ed-94f0f877bf7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383892616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.383892616
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.4150027707
Short name T249
Test name
Test status
Simulation time 170975396289 ps
CPU time 334.68 seconds
Started Jul 22 07:01:42 PM PDT 24
Finished Jul 22 07:07:18 PM PDT 24
Peak memory 191776 kb
Host smart-c3a6d121-50fc-4674-8187-d352f605cd1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150027707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.4150027707
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.3356394367
Short name T292
Test name
Test status
Simulation time 294569945246 ps
CPU time 179.72 seconds
Started Jul 22 07:01:37 PM PDT 24
Finished Jul 22 07:04:39 PM PDT 24
Peak memory 191760 kb
Host smart-466331d8-9eb2-437c-8898-cbaadd7ebe7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356394367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.3356394367
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.1428024588
Short name T264
Test name
Test status
Simulation time 29438704276 ps
CPU time 44.75 seconds
Started Jul 22 07:01:42 PM PDT 24
Finished Jul 22 07:02:28 PM PDT 24
Peak memory 191784 kb
Host smart-1827e56e-3592-48b8-b1a8-998c075c75d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428024588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.1428024588
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.1991655576
Short name T297
Test name
Test status
Simulation time 138948002535 ps
CPU time 841.64 seconds
Started Jul 22 07:01:37 PM PDT 24
Finished Jul 22 07:15:42 PM PDT 24
Peak memory 194732 kb
Host smart-6b76ebd9-fd82-4c9c-b3da-911b6fb72c89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991655576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.1991655576
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.471773949
Short name T345
Test name
Test status
Simulation time 94285114582 ps
CPU time 71.58 seconds
Started Jul 22 07:04:40 PM PDT 24
Finished Jul 22 07:05:54 PM PDT 24
Peak memory 191740 kb
Host smart-3eb63d20-1741-4eaf-a9e6-de4525065a2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471773949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.471773949
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.4050449383
Short name T284
Test name
Test status
Simulation time 680478586767 ps
CPU time 2343.19 seconds
Started Jul 22 07:01:49 PM PDT 24
Finished Jul 22 07:40:55 PM PDT 24
Peak memory 191792 kb
Host smart-28f33d45-c070-41a7-86b1-2eb8352c9e6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050449383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.4050449383
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.1699724684
Short name T430
Test name
Test status
Simulation time 132218948568 ps
CPU time 113.15 seconds
Started Jul 22 06:59:31 PM PDT 24
Finished Jul 22 07:01:41 PM PDT 24
Peak memory 183576 kb
Host smart-dea35f5b-f307-4680-8a45-21132fa7c401
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699724684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.1699724684
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.3998198410
Short name T412
Test name
Test status
Simulation time 409874382071 ps
CPU time 154.18 seconds
Started Jul 22 06:59:34 PM PDT 24
Finished Jul 22 07:02:25 PM PDT 24
Peak memory 183576 kb
Host smart-895100bf-8b1b-4423-a26d-d98783f4436d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998198410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.3998198410
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.2302397550
Short name T207
Test name
Test status
Simulation time 28897358731 ps
CPU time 46.2 seconds
Started Jul 22 06:59:33 PM PDT 24
Finished Jul 22 07:00:36 PM PDT 24
Peak memory 195456 kb
Host smart-d45fabff-e10e-4f62-b6f7-c3c917275d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302397550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.2302397550
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.4200516173
Short name T16
Test name
Test status
Simulation time 145922074 ps
CPU time 0.77 seconds
Started Jul 22 06:59:34 PM PDT 24
Finished Jul 22 06:59:51 PM PDT 24
Peak memory 213812 kb
Host smart-f2d1d88a-378c-4759-9472-8dc56f35021a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200516173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.4200516173
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.3128457079
Short name T146
Test name
Test status
Simulation time 596107156144 ps
CPU time 330.92 seconds
Started Jul 22 07:00:00 PM PDT 24
Finished Jul 22 07:05:40 PM PDT 24
Peak memory 183584 kb
Host smart-39573fd8-2d94-41ce-9287-ebacbf478983
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128457079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.3128457079
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.2587530627
Short name T421
Test name
Test status
Simulation time 112634836942 ps
CPU time 142.71 seconds
Started Jul 22 07:00:19 PM PDT 24
Finished Jul 22 07:02:57 PM PDT 24
Peak memory 183552 kb
Host smart-de811585-6e94-492e-837b-85e40b55908d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587530627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.2587530627
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.1035337267
Short name T301
Test name
Test status
Simulation time 78766070872 ps
CPU time 120.83 seconds
Started Jul 22 06:59:59 PM PDT 24
Finished Jul 22 07:02:08 PM PDT 24
Peak memory 191856 kb
Host smart-31a1d6b7-3f21-454f-b033-7f90c10b9e46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035337267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.1035337267
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.3408079599
Short name T365
Test name
Test status
Simulation time 217169052 ps
CPU time 0.54 seconds
Started Jul 22 07:00:32 PM PDT 24
Finished Jul 22 07:00:47 PM PDT 24
Peak memory 183168 kb
Host smart-ffb3b8b0-3aea-4328-bc02-6a0f2e25bc29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408079599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.3408079599
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.1758212447
Short name T336
Test name
Test status
Simulation time 648858102342 ps
CPU time 328.31 seconds
Started Jul 22 07:00:00 PM PDT 24
Finished Jul 22 07:05:37 PM PDT 24
Peak memory 183572 kb
Host smart-d9b77c91-5ac3-4d30-9a7f-7a887459f8f7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758212447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.1758212447
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.3263080764
Short name T447
Test name
Test status
Simulation time 713516811789 ps
CPU time 262.42 seconds
Started Jul 22 07:01:25 PM PDT 24
Finished Jul 22 07:05:51 PM PDT 24
Peak memory 183572 kb
Host smart-703530ea-24bd-458d-8b9f-1be9071e1b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263080764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.3263080764
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.3559327190
Short name T6
Test name
Test status
Simulation time 62187050500 ps
CPU time 179.52 seconds
Started Jul 22 06:59:57 PM PDT 24
Finished Jul 22 07:03:06 PM PDT 24
Peak memory 191804 kb
Host smart-478a4b66-199e-41ed-b010-ac1065e649f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559327190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.3559327190
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.905631509
Short name T270
Test name
Test status
Simulation time 2087245823435 ps
CPU time 517.08 seconds
Started Jul 22 06:59:59 PM PDT 24
Finished Jul 22 07:08:45 PM PDT 24
Peak memory 183544 kb
Host smart-4a73a3c4-8e4a-4553-9b07-26d7aaffac8c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905631509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.rv_timer_cfg_update_on_fly.905631509
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.2488225144
Short name T394
Test name
Test status
Simulation time 213083325864 ps
CPU time 100.03 seconds
Started Jul 22 07:00:14 PM PDT 24
Finished Jul 22 07:02:10 PM PDT 24
Peak memory 183572 kb
Host smart-ea200005-cd29-4b37-99a9-cf197ef386b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488225144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.2488225144
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.3478151663
Short name T222
Test name
Test status
Simulation time 554437627354 ps
CPU time 251.9 seconds
Started Jul 22 07:00:18 PM PDT 24
Finished Jul 22 07:04:46 PM PDT 24
Peak memory 191732 kb
Host smart-6d3ad002-a7d0-4de6-83d3-0779b9b5f686
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478151663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.3478151663
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.1338634298
Short name T53
Test name
Test status
Simulation time 44872727 ps
CPU time 0.83 seconds
Started Jul 22 06:59:59 PM PDT 24
Finished Jul 22 07:00:09 PM PDT 24
Peak memory 192288 kb
Host smart-610c372b-70e0-4bb9-9b21-23aab6d1bfc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338634298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.1338634298
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.44786488
Short name T70
Test name
Test status
Simulation time 983994872994 ps
CPU time 594.49 seconds
Started Jul 22 07:00:11 PM PDT 24
Finished Jul 22 07:10:21 PM PDT 24
Peak memory 191780 kb
Host smart-c8808ab8-65e3-49c0-98d0-cfb91499ec32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44786488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all.44786488
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.1984621952
Short name T303
Test name
Test status
Simulation time 901015789438 ps
CPU time 420.27 seconds
Started Jul 22 07:00:02 PM PDT 24
Finished Jul 22 07:07:11 PM PDT 24
Peak memory 183564 kb
Host smart-aa6a256e-2c24-4057-b047-9fca60a08146
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984621952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.1984621952
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.1171173690
Short name T417
Test name
Test status
Simulation time 218562316235 ps
CPU time 41.51 seconds
Started Jul 22 07:00:02 PM PDT 24
Finished Jul 22 07:00:53 PM PDT 24
Peak memory 183468 kb
Host smart-6aba95eb-e1b4-4b6c-aa47-70e9bb3b3c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171173690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.1171173690
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.4101693062
Short name T194
Test name
Test status
Simulation time 66949859320 ps
CPU time 100.59 seconds
Started Jul 22 07:00:08 PM PDT 24
Finished Jul 22 07:02:02 PM PDT 24
Peak memory 183600 kb
Host smart-7f446e93-f6c0-4530-94a1-b78487056e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101693062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.4101693062
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.2264481153
Short name T348
Test name
Test status
Simulation time 9253254275 ps
CPU time 14.6 seconds
Started Jul 22 07:00:03 PM PDT 24
Finished Jul 22 07:00:26 PM PDT 24
Peak memory 183540 kb
Host smart-b2506eb4-179b-4ef0-959b-a0e48287e5cc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264481153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.2264481153
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.1615541906
Short name T366
Test name
Test status
Simulation time 195418560557 ps
CPU time 160.91 seconds
Started Jul 22 07:00:07 PM PDT 24
Finished Jul 22 07:03:01 PM PDT 24
Peak memory 183600 kb
Host smart-fef86697-c7a7-4526-b766-3cc30a94fa30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615541906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.1615541906
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.598375694
Short name T153
Test name
Test status
Simulation time 113645230683 ps
CPU time 452.04 seconds
Started Jul 22 07:00:00 PM PDT 24
Finished Jul 22 07:07:41 PM PDT 24
Peak memory 191772 kb
Host smart-6b75e7c2-db37-40f3-a674-7c5dfb265630
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598375694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.598375694
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.3953403889
Short name T186
Test name
Test status
Simulation time 673252022806 ps
CPU time 551.84 seconds
Started Jul 22 07:00:07 PM PDT 24
Finished Jul 22 07:09:32 PM PDT 24
Peak memory 183584 kb
Host smart-88d5e216-acb9-4ed6-8368-f1f17292ecae
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953403889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.3953403889
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.1003187135
Short name T372
Test name
Test status
Simulation time 542657894735 ps
CPU time 215.36 seconds
Started Jul 22 07:00:07 PM PDT 24
Finished Jul 22 07:03:54 PM PDT 24
Peak memory 183608 kb
Host smart-051314ac-3e9f-4e0f-9e42-fa6639c9adc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003187135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.1003187135
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.708322801
Short name T356
Test name
Test status
Simulation time 1194650201546 ps
CPU time 487.58 seconds
Started Jul 22 07:00:00 PM PDT 24
Finished Jul 22 07:08:16 PM PDT 24
Peak memory 191796 kb
Host smart-282d970f-bcfc-411a-87b5-20a51776fdc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708322801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.708322801
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.3163556187
Short name T443
Test name
Test status
Simulation time 2748048456 ps
CPU time 21.88 seconds
Started Jul 22 07:00:10 PM PDT 24
Finished Jul 22 07:00:47 PM PDT 24
Peak memory 191800 kb
Host smart-f1bf9969-4b8f-4a42-b3c0-f10258387544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163556187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.3163556187
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.1532357883
Short name T181
Test name
Test status
Simulation time 838931001697 ps
CPU time 1087.57 seconds
Started Jul 22 07:00:09 PM PDT 24
Finished Jul 22 07:18:30 PM PDT 24
Peak memory 196340 kb
Host smart-9f879ac9-277c-4010-90ba-b8bae2c89dc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532357883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.1532357883
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.3492553358
Short name T305
Test name
Test status
Simulation time 261174897109 ps
CPU time 387.13 seconds
Started Jul 22 06:59:57 PM PDT 24
Finished Jul 22 07:06:33 PM PDT 24
Peak memory 183572 kb
Host smart-ca6bf24d-f33c-4479-a767-fdc8d3ab377e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492553358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.3492553358
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.602295481
Short name T397
Test name
Test status
Simulation time 424987905468 ps
CPU time 120.25 seconds
Started Jul 22 06:59:58 PM PDT 24
Finished Jul 22 07:02:08 PM PDT 24
Peak memory 183576 kb
Host smart-98527217-3851-46ea-935b-58c38ec3cc81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602295481 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.602295481
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.2520866975
Short name T268
Test name
Test status
Simulation time 23698142844 ps
CPU time 37.53 seconds
Started Jul 22 07:00:09 PM PDT 24
Finished Jul 22 07:00:59 PM PDT 24
Peak memory 183412 kb
Host smart-26fa6208-fc66-44e6-a861-9d203d43071c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520866975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.2520866975
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.395849582
Short name T441
Test name
Test status
Simulation time 14991518316 ps
CPU time 12.84 seconds
Started Jul 22 07:00:04 PM PDT 24
Finished Jul 22 07:00:27 PM PDT 24
Peak memory 183492 kb
Host smart-854fa917-fcb5-46f4-825f-60a80e35894b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395849582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.395849582
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.895407757
Short name T189
Test name
Test status
Simulation time 569061539858 ps
CPU time 624.22 seconds
Started Jul 22 07:00:02 PM PDT 24
Finished Jul 22 07:10:35 PM PDT 24
Peak memory 183464 kb
Host smart-8dabd621-1bd2-4837-a095-ddb6f4d6eed6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895407757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.rv_timer_cfg_update_on_fly.895407757
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.3731610901
Short name T387
Test name
Test status
Simulation time 107319415133 ps
CPU time 165.84 seconds
Started Jul 22 07:00:02 PM PDT 24
Finished Jul 22 07:02:57 PM PDT 24
Peak memory 183488 kb
Host smart-6ba00c21-2966-4150-9d36-459b94291409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731610901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.3731610901
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.3873566054
Short name T281
Test name
Test status
Simulation time 507589000706 ps
CPU time 442.09 seconds
Started Jul 22 07:00:32 PM PDT 24
Finished Jul 22 07:08:08 PM PDT 24
Peak memory 191776 kb
Host smart-6ba29e61-75a2-41cb-be86-0b958c973976
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873566054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.3873566054
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.1000385077
Short name T247
Test name
Test status
Simulation time 306122233116 ps
CPU time 104.19 seconds
Started Jul 22 07:00:08 PM PDT 24
Finished Jul 22 07:02:05 PM PDT 24
Peak memory 195160 kb
Host smart-9a1a384a-f275-4a1e-af57-1d3ce633a1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000385077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.1000385077
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.481277738
Short name T437
Test name
Test status
Simulation time 48865282 ps
CPU time 0.57 seconds
Started Jul 22 07:00:18 PM PDT 24
Finished Jul 22 07:00:35 PM PDT 24
Peak memory 183304 kb
Host smart-e45e2b8a-eec0-4174-a668-081882642b5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481277738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all.
481277738
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all_with_rand_reset.2166248426
Short name T38
Test name
Test status
Simulation time 59603856439 ps
CPU time 512.72 seconds
Started Jul 22 07:00:07 PM PDT 24
Finished Jul 22 07:08:51 PM PDT 24
Peak memory 206476 kb
Host smart-6eac08ec-c1b1-4c1e-b345-1af085af7b4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166248426 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all_with_rand_reset.2166248426
Directory /workspace/27.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.3252827725
Short name T369
Test name
Test status
Simulation time 110590893628 ps
CPU time 47.15 seconds
Started Jul 22 07:00:04 PM PDT 24
Finished Jul 22 07:01:01 PM PDT 24
Peak memory 183576 kb
Host smart-b94ca1ce-98ac-4b5f-b0f8-179e74a20dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252827725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.3252827725
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.4001695696
Short name T317
Test name
Test status
Simulation time 47084246019 ps
CPU time 38.8 seconds
Started Jul 22 07:00:19 PM PDT 24
Finished Jul 22 07:01:14 PM PDT 24
Peak memory 183540 kb
Host smart-3ca94b67-aeea-48e0-b989-c030d72c6be7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001695696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.4001695696
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.3721127249
Short name T360
Test name
Test status
Simulation time 217989516 ps
CPU time 0.66 seconds
Started Jul 22 07:00:19 PM PDT 24
Finished Jul 22 07:00:35 PM PDT 24
Peak memory 183328 kb
Host smart-7cce82ac-0826-4c48-a204-bef7297d83f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721127249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.3721127249
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.1734888143
Short name T420
Test name
Test status
Simulation time 202670333878 ps
CPU time 188.94 seconds
Started Jul 22 07:00:07 PM PDT 24
Finished Jul 22 07:03:29 PM PDT 24
Peak memory 183532 kb
Host smart-5966188c-be90-4ef8-8d66-1f18198ba2d9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734888143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.1734888143
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.1056973075
Short name T392
Test name
Test status
Simulation time 547656946382 ps
CPU time 182.98 seconds
Started Jul 22 07:00:10 PM PDT 24
Finished Jul 22 07:03:28 PM PDT 24
Peak memory 183652 kb
Host smart-44b5869e-1690-4885-bcd4-aa27f4327f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056973075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.1056973075
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.77745126
Short name T446
Test name
Test status
Simulation time 16255490326 ps
CPU time 7.43 seconds
Started Jul 22 07:00:57 PM PDT 24
Finished Jul 22 07:01:09 PM PDT 24
Peak memory 183584 kb
Host smart-964f8fcf-8de5-4922-a07a-ac56aec4577b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77745126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.77745126
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.422268706
Short name T282
Test name
Test status
Simulation time 25072714507 ps
CPU time 41.17 seconds
Started Jul 22 07:00:10 PM PDT 24
Finished Jul 22 07:01:06 PM PDT 24
Peak memory 183528 kb
Host smart-f47671a2-4fd3-452c-8e41-e5a7cff4b585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422268706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.422268706
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all_with_rand_reset.3386329010
Short name T13
Test name
Test status
Simulation time 34327274089 ps
CPU time 268.18 seconds
Started Jul 22 07:00:08 PM PDT 24
Finished Jul 22 07:04:50 PM PDT 24
Peak memory 198284 kb
Host smart-1b44677e-03e5-43b2-92aa-f38d3374bab7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386329010 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all_with_rand_reset.3386329010
Directory /workspace/29.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.535617116
Short name T351
Test name
Test status
Simulation time 200002359441 ps
CPU time 298.41 seconds
Started Jul 22 06:59:35 PM PDT 24
Finished Jul 22 07:04:50 PM PDT 24
Peak memory 183588 kb
Host smart-fbeff4e9-1ad6-4cdb-ac8d-4d321687bda4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535617116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.rv_timer_cfg_update_on_fly.535617116
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.2269831734
Short name T379
Test name
Test status
Simulation time 195048420377 ps
CPU time 80.06 seconds
Started Jul 22 06:59:35 PM PDT 24
Finished Jul 22 07:01:12 PM PDT 24
Peak memory 183600 kb
Host smart-08238154-420e-4dac-881b-4b3df10f4ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269831734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.2269831734
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.3943941300
Short name T88
Test name
Test status
Simulation time 26218325961 ps
CPU time 15.39 seconds
Started Jul 22 06:59:41 PM PDT 24
Finished Jul 22 07:00:11 PM PDT 24
Peak memory 191860 kb
Host smart-02c22765-7d5b-4efc-9563-919e28b18f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943941300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.3943941300
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.1259393374
Short name T17
Test name
Test status
Simulation time 68611477 ps
CPU time 0.83 seconds
Started Jul 22 06:59:37 PM PDT 24
Finished Jul 22 06:59:54 PM PDT 24
Peak memory 214524 kb
Host smart-9f17d8cb-f20d-4595-801d-b45e99b6de05
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259393374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.1259393374
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.2843713918
Short name T339
Test name
Test status
Simulation time 1220031274184 ps
CPU time 923.03 seconds
Started Jul 22 07:00:33 PM PDT 24
Finished Jul 22 07:16:10 PM PDT 24
Peak memory 191740 kb
Host smart-513ed465-7a32-4344-94f8-65dce7ec2725
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843713918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
2843713918
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all_with_rand_reset.3764128463
Short name T35
Test name
Test status
Simulation time 89739927332 ps
CPU time 396.43 seconds
Started Jul 22 06:59:38 PM PDT 24
Finished Jul 22 07:06:30 PM PDT 24
Peak memory 206488 kb
Host smart-57e8dafd-50e7-471f-9c80-2fff9175e9a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764128463 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all_with_rand_reset.3764128463
Directory /workspace/3.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.3999576882
Short name T341
Test name
Test status
Simulation time 308380579505 ps
CPU time 553.95 seconds
Started Jul 22 07:00:08 PM PDT 24
Finished Jul 22 07:09:35 PM PDT 24
Peak memory 183560 kb
Host smart-b591f1cf-5732-4f32-87e9-a7601957230b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999576882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.3999576882
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.13978816
Short name T419
Test name
Test status
Simulation time 713478282912 ps
CPU time 143.87 seconds
Started Jul 22 07:00:11 PM PDT 24
Finished Jul 22 07:02:49 PM PDT 24
Peak memory 183584 kb
Host smart-3a715851-0406-4ea8-b89c-1f081217f8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13978816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.13978816
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.531522950
Short name T311
Test name
Test status
Simulation time 190802759682 ps
CPU time 166.49 seconds
Started Jul 22 07:00:07 PM PDT 24
Finished Jul 22 07:03:06 PM PDT 24
Peak memory 191780 kb
Host smart-91924290-137e-4c1e-a8c0-87598e442ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531522950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.531522950
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.3726290891
Short name T67
Test name
Test status
Simulation time 321557599343 ps
CPU time 871.61 seconds
Started Jul 22 07:00:13 PM PDT 24
Finished Jul 22 07:15:01 PM PDT 24
Peak memory 191836 kb
Host smart-c221473c-d953-4f67-8c37-dc302ce444df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726290891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.3726290891
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.1692908011
Short name T9
Test name
Test status
Simulation time 43836980350 ps
CPU time 22.76 seconds
Started Jul 22 07:00:09 PM PDT 24
Finished Jul 22 07:00:46 PM PDT 24
Peak memory 183568 kb
Host smart-7a9c700d-6633-4621-996c-b535eeac2f1b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692908011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.1692908011
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.626399246
Short name T364
Test name
Test status
Simulation time 70479794748 ps
CPU time 101.04 seconds
Started Jul 22 07:00:08 PM PDT 24
Finished Jul 22 07:02:01 PM PDT 24
Peak memory 183612 kb
Host smart-d9846e5e-697e-4ba9-8894-833c06e99baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626399246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.626399246
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.3120366799
Short name T103
Test name
Test status
Simulation time 100511207722 ps
CPU time 39.81 seconds
Started Jul 22 07:00:07 PM PDT 24
Finished Jul 22 07:01:00 PM PDT 24
Peak memory 183592 kb
Host smart-df7ed3ae-ea67-43d1-a903-ed7d94a8e6b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120366799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.3120366799
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.1353320212
Short name T380
Test name
Test status
Simulation time 541939793 ps
CPU time 0.76 seconds
Started Jul 22 07:00:08 PM PDT 24
Finished Jul 22 07:00:22 PM PDT 24
Peak memory 183368 kb
Host smart-429f175f-3116-43a4-af84-2769a558c50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353320212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.1353320212
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all_with_rand_reset.1376007734
Short name T37
Test name
Test status
Simulation time 87369408006 ps
CPU time 117.75 seconds
Started Jul 22 07:00:10 PM PDT 24
Finished Jul 22 07:02:23 PM PDT 24
Peak memory 198232 kb
Host smart-a51a13a7-3951-479e-a25b-a7e1cc015421
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376007734 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all_with_rand_reset.1376007734
Directory /workspace/31.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.3742468781
Short name T217
Test name
Test status
Simulation time 1801446440947 ps
CPU time 826.8 seconds
Started Jul 22 07:00:57 PM PDT 24
Finished Jul 22 07:14:48 PM PDT 24
Peak memory 183576 kb
Host smart-507ad161-d068-4ec5-bb9e-a788e206ddb5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742468781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.3742468781
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.3448966408
Short name T25
Test name
Test status
Simulation time 23221770927 ps
CPU time 32.1 seconds
Started Jul 22 07:00:57 PM PDT 24
Finished Jul 22 07:01:33 PM PDT 24
Peak memory 183440 kb
Host smart-cbf21657-926d-4200-9aac-3bbd9a321af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448966408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.3448966408
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.2117464837
Short name T235
Test name
Test status
Simulation time 25837062693 ps
CPU time 44.76 seconds
Started Jul 22 07:00:11 PM PDT 24
Finished Jul 22 07:01:11 PM PDT 24
Peak memory 183596 kb
Host smart-e1be68e6-b581-4b91-b3f4-90408c67a349
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117464837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.2117464837
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.1306868102
Short name T56
Test name
Test status
Simulation time 100110617688 ps
CPU time 189.08 seconds
Started Jul 22 07:00:14 PM PDT 24
Finished Jul 22 07:03:39 PM PDT 24
Peak memory 183564 kb
Host smart-a43987d5-7764-4902-ba06-89376cbde41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306868102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.1306868102
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.2746097125
Short name T224
Test name
Test status
Simulation time 174521054481 ps
CPU time 99.94 seconds
Started Jul 22 07:00:57 PM PDT 24
Finished Jul 22 07:02:41 PM PDT 24
Peak memory 183580 kb
Host smart-e625c050-3242-4ada-af74-9cd56478a461
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746097125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.2746097125
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.4142250121
Short name T367
Test name
Test status
Simulation time 430190142734 ps
CPU time 331.25 seconds
Started Jul 22 07:00:10 PM PDT 24
Finished Jul 22 07:05:56 PM PDT 24
Peak memory 183660 kb
Host smart-695b2d93-43de-4372-9bf8-af4bc3d61a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142250121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.4142250121
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.15726818
Short name T223
Test name
Test status
Simulation time 73711723955 ps
CPU time 74.88 seconds
Started Jul 22 07:00:10 PM PDT 24
Finished Jul 22 07:01:39 PM PDT 24
Peak memory 183540 kb
Host smart-86f454cf-73ac-4066-9de1-983fdaf7bdaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15726818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.15726818
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.800248949
Short name T431
Test name
Test status
Simulation time 1348183874871 ps
CPU time 590.3 seconds
Started Jul 22 07:00:09 PM PDT 24
Finished Jul 22 07:10:12 PM PDT 24
Peak memory 191776 kb
Host smart-1e71c18c-ca43-4483-93b7-4dc523f52997
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800248949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all.
800248949
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.2950753428
Short name T121
Test name
Test status
Simulation time 561533984340 ps
CPU time 290.39 seconds
Started Jul 22 07:00:10 PM PDT 24
Finished Jul 22 07:05:15 PM PDT 24
Peak memory 183652 kb
Host smart-5ede5435-6e03-4fc0-a85b-575d26ca9a46
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950753428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.2950753428
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.2257703019
Short name T389
Test name
Test status
Simulation time 559897936571 ps
CPU time 177.45 seconds
Started Jul 22 07:00:13 PM PDT 24
Finished Jul 22 07:03:26 PM PDT 24
Peak memory 183636 kb
Host smart-755cb5c8-5464-44f5-9982-9b11d2671bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257703019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.2257703019
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.1588140476
Short name T212
Test name
Test status
Simulation time 206045492085 ps
CPU time 146.19 seconds
Started Jul 22 07:00:08 PM PDT 24
Finished Jul 22 07:02:47 PM PDT 24
Peak memory 191772 kb
Host smart-1b875667-8e90-4e01-b235-c4577f552326
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588140476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.1588140476
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.2488130621
Short name T393
Test name
Test status
Simulation time 32112213 ps
CPU time 0.54 seconds
Started Jul 22 07:00:07 PM PDT 24
Finished Jul 22 07:00:21 PM PDT 24
Peak memory 183312 kb
Host smart-33328f6f-0872-4625-be45-e8fac854ba47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488130621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.2488130621
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.3020180444
Short name T154
Test name
Test status
Simulation time 237586820625 ps
CPU time 414.64 seconds
Started Jul 22 07:00:10 PM PDT 24
Finished Jul 22 07:07:19 PM PDT 24
Peak memory 191832 kb
Host smart-fede0064-e3fc-42d4-9dbb-3c71eea5fa4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020180444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.3020180444
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.3184878698
Short name T425
Test name
Test status
Simulation time 204202218759 ps
CPU time 254.05 seconds
Started Jul 22 07:00:09 PM PDT 24
Finished Jul 22 07:04:36 PM PDT 24
Peak memory 183516 kb
Host smart-0a261111-aba6-4245-8d1e-9863f5044437
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184878698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.3184878698
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.1541849465
Short name T102
Test name
Test status
Simulation time 155470607927 ps
CPU time 233.63 seconds
Started Jul 22 07:00:09 PM PDT 24
Finished Jul 22 07:04:17 PM PDT 24
Peak memory 183576 kb
Host smart-b030e2ac-1a93-4eac-a3a8-03e4b45c88b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541849465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.1541849465
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.1523017688
Short name T352
Test name
Test status
Simulation time 621913124212 ps
CPU time 955.61 seconds
Started Jul 22 07:00:11 PM PDT 24
Finished Jul 22 07:16:21 PM PDT 24
Peak memory 191784 kb
Host smart-132c5d71-47a0-49ef-9b52-08cd14fdd880
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523017688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.1523017688
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.1723491761
Short name T258
Test name
Test status
Simulation time 26457469480 ps
CPU time 365.49 seconds
Started Jul 22 07:00:57 PM PDT 24
Finished Jul 22 07:07:07 PM PDT 24
Peak memory 191584 kb
Host smart-d39cb159-9f69-4bb6-b018-59decfca0f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723491761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.1723491761
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.3308558271
Short name T413
Test name
Test status
Simulation time 35826592673 ps
CPU time 51.59 seconds
Started Jul 22 07:00:10 PM PDT 24
Finished Jul 22 07:01:16 PM PDT 24
Peak memory 183468 kb
Host smart-f6fd6735-f3a0-4647-9c40-dfae2470b450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308558271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.3308558271
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.3722955319
Short name T157
Test name
Test status
Simulation time 97951983484 ps
CPU time 89.02 seconds
Started Jul 22 07:00:11 PM PDT 24
Finished Jul 22 07:01:54 PM PDT 24
Peak memory 183600 kb
Host smart-9b9d49f6-0f0a-425a-b5e6-e89be255c986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722955319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.3722955319
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.301291112
Short name T174
Test name
Test status
Simulation time 789037448194 ps
CPU time 484.52 seconds
Started Jul 22 07:00:12 PM PDT 24
Finished Jul 22 07:08:31 PM PDT 24
Peak memory 195568 kb
Host smart-40b172f2-dc5b-4509-aa27-701759208e11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301291112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all.
301291112
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.4120685572
Short name T203
Test name
Test status
Simulation time 447422573906 ps
CPU time 220.11 seconds
Started Jul 22 07:00:13 PM PDT 24
Finished Jul 22 07:04:09 PM PDT 24
Peak memory 183604 kb
Host smart-fbe5fb06-78f9-4c52-a12d-205132ec2702
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120685572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.4120685572
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.1904054357
Short name T376
Test name
Test status
Simulation time 85466858916 ps
CPU time 117.35 seconds
Started Jul 22 07:00:11 PM PDT 24
Finished Jul 22 07:02:23 PM PDT 24
Peak memory 183584 kb
Host smart-7e489c47-4bec-415d-827f-8627bda117bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904054357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.1904054357
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.3857543624
Short name T256
Test name
Test status
Simulation time 107374047557 ps
CPU time 1435.49 seconds
Started Jul 22 07:00:10 PM PDT 24
Finished Jul 22 07:24:21 PM PDT 24
Peak memory 191840 kb
Host smart-21f8e90f-204f-457d-ab6b-0010e38a07e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857543624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.3857543624
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.957953927
Short name T78
Test name
Test status
Simulation time 1112500679 ps
CPU time 1.07 seconds
Started Jul 22 07:00:22 PM PDT 24
Finished Jul 22 07:00:39 PM PDT 24
Peak memory 193464 kb
Host smart-3370588b-2612-4f34-8b23-ab7c5396bb00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957953927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.957953927
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.726556235
Short name T278
Test name
Test status
Simulation time 433683564042 ps
CPU time 216.44 seconds
Started Jul 22 07:00:21 PM PDT 24
Finished Jul 22 07:04:14 PM PDT 24
Peak memory 183544 kb
Host smart-f0ee6b44-3566-4816-b0af-5d05ac82cf81
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726556235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.rv_timer_cfg_update_on_fly.726556235
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.2607432058
Short name T361
Test name
Test status
Simulation time 289688128001 ps
CPU time 189.12 seconds
Started Jul 22 07:00:20 PM PDT 24
Finished Jul 22 07:03:45 PM PDT 24
Peak memory 183596 kb
Host smart-672156ad-a532-47eb-9233-e085ea44f7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607432058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.2607432058
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.764928562
Short name T147
Test name
Test status
Simulation time 274871610978 ps
CPU time 156.72 seconds
Started Jul 22 07:00:20 PM PDT 24
Finished Jul 22 07:03:12 PM PDT 24
Peak memory 191776 kb
Host smart-9b7b0b76-2ed1-4ce0-85c7-92a90649a1c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764928562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.764928562
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.602651545
Short name T51
Test name
Test status
Simulation time 48237267592 ps
CPU time 72.96 seconds
Started Jul 22 07:00:19 PM PDT 24
Finished Jul 22 07:01:48 PM PDT 24
Peak memory 192440 kb
Host smart-7b565d9e-2d5c-4069-a859-9032b1279e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602651545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.602651545
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all_with_rand_reset.739397298
Short name T14
Test name
Test status
Simulation time 56196241316 ps
CPU time 231.1 seconds
Started Jul 22 07:00:19 PM PDT 24
Finished Jul 22 07:04:26 PM PDT 24
Peak memory 206444 kb
Host smart-d17f6992-859b-42a9-93ba-1ac45255de6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739397298 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all_with_rand_reset.739397298
Directory /workspace/38.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.2932106659
Short name T155
Test name
Test status
Simulation time 293255536 ps
CPU time 1.02 seconds
Started Jul 22 07:00:22 PM PDT 24
Finished Jul 22 07:00:39 PM PDT 24
Peak memory 183368 kb
Host smart-45de661a-603f-4c90-a603-6698bbe5cec4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932106659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.2932106659
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.1922874772
Short name T399
Test name
Test status
Simulation time 91582323819 ps
CPU time 75.81 seconds
Started Jul 22 07:00:18 PM PDT 24
Finished Jul 22 07:01:50 PM PDT 24
Peak memory 183596 kb
Host smart-e5ad59c5-c621-4f67-9aac-855102902145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922874772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.1922874772
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.3371397052
Short name T21
Test name
Test status
Simulation time 301157200578 ps
CPU time 208.41 seconds
Started Jul 22 07:00:19 PM PDT 24
Finished Jul 22 07:04:03 PM PDT 24
Peak memory 191832 kb
Host smart-e431aa10-5bc4-4812-aa1c-f253452c4c12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371397052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.3371397052
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.3908839543
Short name T435
Test name
Test status
Simulation time 175172887 ps
CPU time 3.85 seconds
Started Jul 22 07:00:21 PM PDT 24
Finished Jul 22 07:00:41 PM PDT 24
Peak memory 183468 kb
Host smart-bc4686e3-22c1-4eee-ae72-2c8dfea5fe77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908839543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.3908839543
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.107251192
Short name T300
Test name
Test status
Simulation time 2171897369929 ps
CPU time 997.8 seconds
Started Jul 22 07:00:22 PM PDT 24
Finished Jul 22 07:17:16 PM PDT 24
Peak memory 191780 kb
Host smart-6e6400b5-b7a1-4f1d-8dff-d43bb36ada1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107251192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all.
107251192
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.1042550561
Short name T340
Test name
Test status
Simulation time 219419337593 ps
CPU time 98.36 seconds
Started Jul 22 07:00:33 PM PDT 24
Finished Jul 22 07:02:25 PM PDT 24
Peak memory 183532 kb
Host smart-aa59e09f-ef4c-4c7a-9a74-17fb31689ab5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042550561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.1042550561
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.2138516123
Short name T363
Test name
Test status
Simulation time 58754472861 ps
CPU time 82.31 seconds
Started Jul 22 06:59:35 PM PDT 24
Finished Jul 22 07:01:14 PM PDT 24
Peak memory 183544 kb
Host smart-466200da-6fa9-4245-993f-5a048c33f446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138516123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.2138516123
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.2403013993
Short name T54
Test name
Test status
Simulation time 417413451 ps
CPU time 0.72 seconds
Started Jul 22 07:00:14 PM PDT 24
Finished Jul 22 07:00:30 PM PDT 24
Peak memory 183340 kb
Host smart-46ba1c71-57d1-4936-87b6-f64bcba3b509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403013993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.2403013993
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.125775512
Short name T15
Test name
Test status
Simulation time 33009555 ps
CPU time 0.75 seconds
Started Jul 22 06:59:35 PM PDT 24
Finished Jul 22 06:59:52 PM PDT 24
Peak memory 213796 kb
Host smart-9cbfc172-c29a-410b-903a-acbab3d3a30e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125775512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.125775512
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all_with_rand_reset.2889738993
Short name T40
Test name
Test status
Simulation time 90799120651 ps
CPU time 397.05 seconds
Started Jul 22 06:59:32 PM PDT 24
Finished Jul 22 07:06:26 PM PDT 24
Peak memory 206504 kb
Host smart-38042892-da17-4ff6-bf54-764cb800be70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889738993 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all_with_rand_reset.2889738993
Directory /workspace/4.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.3778323164
Short name T201
Test name
Test status
Simulation time 201562285044 ps
CPU time 315.94 seconds
Started Jul 22 07:00:18 PM PDT 24
Finished Jul 22 07:05:51 PM PDT 24
Peak memory 183576 kb
Host smart-45bd4e48-dd4a-4dbf-806e-4b78f27592ab
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778323164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.3778323164
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.2613278657
Short name T445
Test name
Test status
Simulation time 158295275879 ps
CPU time 118.2 seconds
Started Jul 22 07:00:19 PM PDT 24
Finished Jul 22 07:02:33 PM PDT 24
Peak memory 183632 kb
Host smart-c7fb9c04-eb68-41da-be8c-23cbbd1d0f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613278657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.2613278657
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.2630134651
Short name T199
Test name
Test status
Simulation time 271572876794 ps
CPU time 1753.76 seconds
Started Jul 22 07:00:21 PM PDT 24
Finished Jul 22 07:29:52 PM PDT 24
Peak memory 191704 kb
Host smart-97952d07-30ea-420a-8d2f-a5f10125fad7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630134651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.2630134651
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.1583385669
Short name T407
Test name
Test status
Simulation time 97366803275 ps
CPU time 230.36 seconds
Started Jul 22 07:00:39 PM PDT 24
Finished Jul 22 07:04:40 PM PDT 24
Peak memory 191756 kb
Host smart-4dc5aabc-480e-432f-a898-37ad7184a95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583385669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.1583385669
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.1375862578
Short name T403
Test name
Test status
Simulation time 2516003039513 ps
CPU time 841.41 seconds
Started Jul 22 07:00:19 PM PDT 24
Finished Jul 22 07:14:36 PM PDT 24
Peak memory 195044 kb
Host smart-eef1a7c5-fc25-4e48-9479-6d4dbb246030
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375862578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.1375862578
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.612801847
Short name T177
Test name
Test status
Simulation time 651257373868 ps
CPU time 373.45 seconds
Started Jul 22 07:00:20 PM PDT 24
Finished Jul 22 07:06:49 PM PDT 24
Peak memory 183588 kb
Host smart-369d149b-3ae9-4f05-8b69-6ab0077c552b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612801847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.rv_timer_cfg_update_on_fly.612801847
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.2364574121
Short name T438
Test name
Test status
Simulation time 146055373670 ps
CPU time 223.56 seconds
Started Jul 22 07:00:19 PM PDT 24
Finished Jul 22 07:04:19 PM PDT 24
Peak memory 183576 kb
Host smart-d2a017ef-3e93-4dfe-a343-8e1c437cb74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364574121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.2364574121
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.3602481320
Short name T10
Test name
Test status
Simulation time 80656715357 ps
CPU time 111.23 seconds
Started Jul 22 07:00:19 PM PDT 24
Finished Jul 22 07:02:27 PM PDT 24
Peak memory 183572 kb
Host smart-cf651d0f-782c-4542-8594-4e77d076fe19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602481320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.3602481320
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.2325853029
Short name T309
Test name
Test status
Simulation time 1296361856455 ps
CPU time 808.09 seconds
Started Jul 22 07:00:21 PM PDT 24
Finished Jul 22 07:14:05 PM PDT 24
Peak memory 183568 kb
Host smart-bd6eff31-234d-4c18-84ca-9af4fe3f42ef
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325853029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.2325853029
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.1359632495
Short name T428
Test name
Test status
Simulation time 117097513377 ps
CPU time 174.34 seconds
Started Jul 22 07:00:20 PM PDT 24
Finished Jul 22 07:03:30 PM PDT 24
Peak memory 183592 kb
Host smart-c2f58cdf-41a1-4890-8229-15d8b51513cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359632495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.1359632495
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.357465191
Short name T266
Test name
Test status
Simulation time 237274720189 ps
CPU time 213.73 seconds
Started Jul 22 07:00:39 PM PDT 24
Finished Jul 22 07:04:24 PM PDT 24
Peak memory 191740 kb
Host smart-bc057bb4-35a3-4c2c-b753-236bdffdf7f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357465191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.357465191
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.2236240135
Short name T323
Test name
Test status
Simulation time 161066744192 ps
CPU time 516.33 seconds
Started Jul 22 07:00:21 PM PDT 24
Finished Jul 22 07:09:14 PM PDT 24
Peak memory 183616 kb
Host smart-5a06e105-60b0-4f64-bf8e-7a22fd0fd491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236240135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.2236240135
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.3869003673
Short name T349
Test name
Test status
Simulation time 303310232768 ps
CPU time 148.68 seconds
Started Jul 22 07:00:19 PM PDT 24
Finished Jul 22 07:03:03 PM PDT 24
Peak memory 183556 kb
Host smart-b8e3138d-1a34-455e-b759-254c4eb2ac7b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869003673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.3869003673
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.1964825055
Short name T391
Test name
Test status
Simulation time 21140277028 ps
CPU time 31.04 seconds
Started Jul 22 07:00:22 PM PDT 24
Finished Jul 22 07:01:09 PM PDT 24
Peak memory 183576 kb
Host smart-933196a8-cb82-493d-9715-06aab5e5f121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964825055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.1964825055
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.3772711519
Short name T330
Test name
Test status
Simulation time 2526710347 ps
CPU time 4.66 seconds
Started Jul 22 07:00:21 PM PDT 24
Finished Jul 22 07:00:42 PM PDT 24
Peak memory 183596 kb
Host smart-15898704-3e75-43dc-a327-21e2056a4c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772711519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.3772711519
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.3345769990
Short name T58
Test name
Test status
Simulation time 383054926538 ps
CPU time 194.21 seconds
Started Jul 22 07:00:30 PM PDT 24
Finished Jul 22 07:03:58 PM PDT 24
Peak memory 183500 kb
Host smart-8e38ce1f-20b3-4e5a-85c2-04d3fa0eb48e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345769990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.3345769990
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.2440356601
Short name T405
Test name
Test status
Simulation time 139779846993 ps
CPU time 201.14 seconds
Started Jul 22 07:00:34 PM PDT 24
Finished Jul 22 07:04:08 PM PDT 24
Peak memory 183620 kb
Host smart-a955c182-ed1e-4eb9-9eef-4f4428c6ba65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440356601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.2440356601
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.778457742
Short name T242
Test name
Test status
Simulation time 561482097617 ps
CPU time 857.93 seconds
Started Jul 22 07:00:34 PM PDT 24
Finished Jul 22 07:15:05 PM PDT 24
Peak memory 191808 kb
Host smart-d720e88c-f8b8-4f4d-88ab-23746cfff5e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778457742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all.
778457742
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.1535253608
Short name T39
Test name
Test status
Simulation time 118788020668 ps
CPU time 291.42 seconds
Started Jul 22 07:00:31 PM PDT 24
Finished Jul 22 07:05:36 PM PDT 24
Peak memory 206540 kb
Host smart-a4f7343d-35bc-4a19-8fec-546d05cd6351
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535253608 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.1535253608
Directory /workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.1564522817
Short name T398
Test name
Test status
Simulation time 97421417839 ps
CPU time 85.62 seconds
Started Jul 22 07:00:36 PM PDT 24
Finished Jul 22 07:02:14 PM PDT 24
Peak memory 183576 kb
Host smart-2d55233f-a68c-4179-8d03-2187f9e2d06a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564522817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.1564522817
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.2620892483
Short name T411
Test name
Test status
Simulation time 77265259057 ps
CPU time 121.82 seconds
Started Jul 22 07:00:30 PM PDT 24
Finished Jul 22 07:02:45 PM PDT 24
Peak memory 183592 kb
Host smart-2f67f613-affe-4743-800b-2735dd726368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620892483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.2620892483
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.1560951690
Short name T140
Test name
Test status
Simulation time 47675297509 ps
CPU time 77.78 seconds
Started Jul 22 07:00:44 PM PDT 24
Finished Jul 22 07:02:11 PM PDT 24
Peak memory 183476 kb
Host smart-e643ca61-9031-4901-aafc-73a18e7c1d8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560951690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.1560951690
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.3166534379
Short name T415
Test name
Test status
Simulation time 151675672584 ps
CPU time 117.56 seconds
Started Jul 22 07:00:28 PM PDT 24
Finished Jul 22 07:02:40 PM PDT 24
Peak memory 183584 kb
Host smart-5a657d41-1559-4bf5-bf55-5101bfa05351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166534379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.3166534379
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.3715625187
Short name T5
Test name
Test status
Simulation time 80185521843 ps
CPU time 137.56 seconds
Started Jul 22 07:02:16 PM PDT 24
Finished Jul 22 07:04:36 PM PDT 24
Peak memory 183336 kb
Host smart-aea7fa35-9c8e-4cf8-8581-f8e4f9e75212
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715625187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.3715625187
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.3191705253
Short name T101
Test name
Test status
Simulation time 483221199491 ps
CPU time 212.01 seconds
Started Jul 22 07:01:18 PM PDT 24
Finished Jul 22 07:04:52 PM PDT 24
Peak memory 183592 kb
Host smart-e2d30ef3-31db-4503-8623-46d1ee48dc36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191705253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.3191705253
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.236592269
Short name T183
Test name
Test status
Simulation time 162595558337 ps
CPU time 244.11 seconds
Started Jul 22 07:01:56 PM PDT 24
Finished Jul 22 07:06:03 PM PDT 24
Peak memory 193816 kb
Host smart-5033cc7b-bd17-4e5d-b236-b18bdc9d5f20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236592269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.236592269
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.1330926689
Short name T422
Test name
Test status
Simulation time 169824873358 ps
CPU time 34.85 seconds
Started Jul 22 07:00:30 PM PDT 24
Finished Jul 22 07:01:19 PM PDT 24
Peak memory 183644 kb
Host smart-8ab37437-51eb-4705-b09b-fb385c6ea2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330926689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.1330926689
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.3657904963
Short name T406
Test name
Test status
Simulation time 205363056561 ps
CPU time 309.38 seconds
Started Jul 22 07:00:38 PM PDT 24
Finished Jul 22 07:05:59 PM PDT 24
Peak memory 196252 kb
Host smart-4914b4b8-2f80-40fd-9858-7ca96ddba9b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657904963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.3657904963
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all_with_rand_reset.138696799
Short name T36
Test name
Test status
Simulation time 135020886514 ps
CPU time 380.57 seconds
Started Jul 22 07:01:18 PM PDT 24
Finished Jul 22 07:07:40 PM PDT 24
Peak memory 206528 kb
Host smart-7a709822-8d87-4ba2-84ee-b9a114dfc957
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138696799 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all_with_rand_reset.138696799
Directory /workspace/46.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.1018824259
Short name T85
Test name
Test status
Simulation time 449707201731 ps
CPU time 641.69 seconds
Started Jul 22 07:01:18 PM PDT 24
Finished Jul 22 07:12:02 PM PDT 24
Peak memory 183412 kb
Host smart-c3452bea-e099-4ca7-98ce-f5dd51b7b561
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018824259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.1018824259
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.2570286149
Short name T370
Test name
Test status
Simulation time 182490741619 ps
CPU time 235.92 seconds
Started Jul 22 07:00:30 PM PDT 24
Finished Jul 22 07:04:39 PM PDT 24
Peak memory 183592 kb
Host smart-e324eedd-faf3-4439-9b3e-2c16819efe13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570286149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.2570286149
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.2497599061
Short name T192
Test name
Test status
Simulation time 292132736608 ps
CPU time 213.18 seconds
Started Jul 22 07:00:35 PM PDT 24
Finished Jul 22 07:04:21 PM PDT 24
Peak memory 191780 kb
Host smart-176868e9-c3f5-4fa2-bc19-a81598dd56ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497599061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.2497599061
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.1930659260
Short name T312
Test name
Test status
Simulation time 57354654674 ps
CPU time 330.19 seconds
Started Jul 22 07:00:35 PM PDT 24
Finished Jul 22 07:06:18 PM PDT 24
Peak memory 191756 kb
Host smart-5f3a0b38-fb63-47cd-89cd-606507cc9519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930659260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.1930659260
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.3784780859
Short name T26
Test name
Test status
Simulation time 267644669337 ps
CPU time 131.28 seconds
Started Jul 22 07:00:30 PM PDT 24
Finished Jul 22 07:02:55 PM PDT 24
Peak memory 183560 kb
Host smart-7b513e2f-6780-47ac-ba08-88e117dfaff1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784780859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.3784780859
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.4068105694
Short name T139
Test name
Test status
Simulation time 276450424753 ps
CPU time 426.21 seconds
Started Jul 22 07:02:16 PM PDT 24
Finished Jul 22 07:09:25 PM PDT 24
Peak memory 183512 kb
Host smart-187e262c-83fe-4fe4-a595-e1ba3d3fafd5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068105694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.4068105694
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.2688184003
Short name T436
Test name
Test status
Simulation time 138188082945 ps
CPU time 181.85 seconds
Started Jul 22 07:02:16 PM PDT 24
Finished Jul 22 07:05:20 PM PDT 24
Peak memory 183384 kb
Host smart-4ef21a3d-6a61-41b1-9f8e-eb6067f7385f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688184003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.2688184003
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.1174428431
Short name T439
Test name
Test status
Simulation time 50131218761 ps
CPU time 193 seconds
Started Jul 22 07:00:30 PM PDT 24
Finished Jul 22 07:03:56 PM PDT 24
Peak memory 194932 kb
Host smart-36f80cad-4852-4048-8da9-90d3ab542630
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174428431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.1174428431
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.2587816496
Short name T427
Test name
Test status
Simulation time 117201213 ps
CPU time 0.52 seconds
Started Jul 22 07:00:35 PM PDT 24
Finished Jul 22 07:00:49 PM PDT 24
Peak memory 183352 kb
Host smart-def9b45d-a0a0-42d0-8793-291afb71875d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587816496 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.2587816496
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.846036175
Short name T440
Test name
Test status
Simulation time 104772097770 ps
CPU time 82.58 seconds
Started Jul 22 07:01:18 PM PDT 24
Finished Jul 22 07:02:43 PM PDT 24
Peak memory 183424 kb
Host smart-5cffc818-4501-4a1d-86b7-c1fdfb5eb911
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846036175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all.
846036175
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.1508150737
Short name T253
Test name
Test status
Simulation time 299383283861 ps
CPU time 68.27 seconds
Started Jul 22 07:00:35 PM PDT 24
Finished Jul 22 07:01:56 PM PDT 24
Peak memory 183572 kb
Host smart-59e7d891-3789-461d-956a-fd0a81634785
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508150737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.1508150737
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.4207624962
Short name T3
Test name
Test status
Simulation time 116253198456 ps
CPU time 157.69 seconds
Started Jul 22 07:00:38 PM PDT 24
Finished Jul 22 07:03:27 PM PDT 24
Peak memory 183564 kb
Host smart-b39d5872-c744-4d58-9b8a-dd8821a39785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207624962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.4207624962
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.3678489662
Short name T386
Test name
Test status
Simulation time 1422381763 ps
CPU time 1.89 seconds
Started Jul 22 07:00:32 PM PDT 24
Finished Jul 22 07:00:47 PM PDT 24
Peak memory 191748 kb
Host smart-e8581e10-1e24-49ec-9e22-81381d7997cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678489662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.3678489662
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.1411681953
Short name T416
Test name
Test status
Simulation time 656184425144 ps
CPU time 271.68 seconds
Started Jul 22 06:59:32 PM PDT 24
Finished Jul 22 07:04:20 PM PDT 24
Peak memory 183576 kb
Host smart-a631e16d-aee2-4c77-9ad3-e5fc8ce411c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411681953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.1411681953
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.737064932
Short name T418
Test name
Test status
Simulation time 184277370171 ps
CPU time 200.06 seconds
Started Jul 22 07:01:01 PM PDT 24
Finished Jul 22 07:04:23 PM PDT 24
Peak memory 191632 kb
Host smart-5d93883d-4df6-4058-a111-613c2d5ee736
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737064932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.737064932
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.1047667047
Short name T66
Test name
Test status
Simulation time 280505754020 ps
CPU time 346.17 seconds
Started Jul 22 06:59:31 PM PDT 24
Finished Jul 22 07:05:34 PM PDT 24
Peak memory 195004 kb
Host smart-3dbfc0d1-3823-4224-ac2d-ffb5273d73a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047667047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
1047667047
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/51.rv_timer_random.2086477737
Short name T117
Test name
Test status
Simulation time 126883477301 ps
CPU time 71.29 seconds
Started Jul 22 07:00:36 PM PDT 24
Finished Jul 22 07:02:00 PM PDT 24
Peak memory 191760 kb
Host smart-8305baa7-ba42-4397-8ba2-e51e85e7ed40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086477737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.2086477737
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.405674252
Short name T304
Test name
Test status
Simulation time 198866273749 ps
CPU time 386.67 seconds
Started Jul 22 07:00:32 PM PDT 24
Finished Jul 22 07:07:12 PM PDT 24
Peak memory 183580 kb
Host smart-53ea0a65-fa74-4180-9faa-4a82c849a812
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405674252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.405674252
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.4162065311
Short name T290
Test name
Test status
Simulation time 196202212330 ps
CPU time 986.14 seconds
Started Jul 22 07:00:30 PM PDT 24
Finished Jul 22 07:17:10 PM PDT 24
Peak memory 183580 kb
Host smart-1de9206a-de9f-47be-b417-01b92b048c01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162065311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.4162065311
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.654567178
Short name T426
Test name
Test status
Simulation time 68521996306 ps
CPU time 61.53 seconds
Started Jul 22 07:00:32 PM PDT 24
Finished Jul 22 07:01:48 PM PDT 24
Peak memory 191792 kb
Host smart-d84d695b-e411-4df3-aee5-74b71e501310
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654567178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.654567178
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.791863091
Short name T243
Test name
Test status
Simulation time 231165294019 ps
CPU time 258.25 seconds
Started Jul 22 07:00:34 PM PDT 24
Finished Jul 22 07:05:05 PM PDT 24
Peak memory 191784 kb
Host smart-dce341ce-559a-4e5a-87c7-e5f0849eee2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791863091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.791863091
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.1781811644
Short name T310
Test name
Test status
Simulation time 680097281872 ps
CPU time 284.3 seconds
Started Jul 22 07:00:37 PM PDT 24
Finished Jul 22 07:05:33 PM PDT 24
Peak memory 191768 kb
Host smart-02aed4cb-27b7-4af1-845f-59da6e1def31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781811644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.1781811644
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.843162313
Short name T337
Test name
Test status
Simulation time 399911736393 ps
CPU time 330.55 seconds
Started Jul 22 06:59:37 PM PDT 24
Finished Jul 22 07:05:24 PM PDT 24
Peak memory 183584 kb
Host smart-086549a3-eead-4212-b7ac-1c7651c6ae99
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843162313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.rv_timer_cfg_update_on_fly.843162313
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.3092574549
Short name T378
Test name
Test status
Simulation time 13760687181 ps
CPU time 6.37 seconds
Started Jul 22 06:59:38 PM PDT 24
Finished Jul 22 07:00:00 PM PDT 24
Peak memory 183576 kb
Host smart-0de3154e-942c-4fd2-8b01-5908c700c4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092574549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.3092574549
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.2694465722
Short name T291
Test name
Test status
Simulation time 91209168588 ps
CPU time 807.23 seconds
Started Jul 22 06:59:37 PM PDT 24
Finished Jul 22 07:13:21 PM PDT 24
Peak memory 191776 kb
Host smart-c8bd9ea7-4383-442e-93c2-731a92324ff3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694465722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.2694465722
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.235068299
Short name T342
Test name
Test status
Simulation time 574362828196 ps
CPU time 92.65 seconds
Started Jul 22 07:00:13 PM PDT 24
Finished Jul 22 07:02:01 PM PDT 24
Peak memory 191784 kb
Host smart-2347082b-bc0b-4d45-831b-b285a72eb4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235068299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.235068299
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.2046584566
Short name T182
Test name
Test status
Simulation time 340129069468 ps
CPU time 769.25 seconds
Started Jul 22 07:02:16 PM PDT 24
Finished Jul 22 07:15:08 PM PDT 24
Peak memory 191544 kb
Host smart-f8dc7906-cd85-4ee9-9c90-1e12843a7823
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046584566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.2046584566
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.2663623321
Short name T313
Test name
Test status
Simulation time 189108394214 ps
CPU time 443.04 seconds
Started Jul 22 07:00:32 PM PDT 24
Finished Jul 22 07:08:09 PM PDT 24
Peak memory 191796 kb
Host smart-ef661ade-2192-4f62-936f-cb7c458cb25e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663623321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.2663623321
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.3714093315
Short name T79
Test name
Test status
Simulation time 259522107583 ps
CPU time 182.17 seconds
Started Jul 22 07:01:57 PM PDT 24
Finished Jul 22 07:05:01 PM PDT 24
Peak memory 191776 kb
Host smart-b1a56fbe-1a14-4bb2-b3e9-e6d72f47e613
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714093315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.3714093315
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.265541614
Short name T198
Test name
Test status
Simulation time 78694078468 ps
CPU time 500.68 seconds
Started Jul 22 07:00:44 PM PDT 24
Finished Jul 22 07:09:14 PM PDT 24
Peak memory 191772 kb
Host smart-9bf87b4e-582f-412f-a23c-e2d159752b2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265541614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.265541614
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.2715791685
Short name T96
Test name
Test status
Simulation time 83493786577 ps
CPU time 121.71 seconds
Started Jul 22 07:00:42 PM PDT 24
Finished Jul 22 07:02:54 PM PDT 24
Peak memory 191776 kb
Host smart-420e8f39-8c28-42a3-b280-f5b6460b1282
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715791685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.2715791685
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.1323588549
Short name T90
Test name
Test status
Simulation time 712010156298 ps
CPU time 373.71 seconds
Started Jul 22 07:01:18 PM PDT 24
Finished Jul 22 07:07:34 PM PDT 24
Peak memory 191788 kb
Host smart-892e2345-45d7-4c8b-9a29-0e821601bf5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323588549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.1323588549
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.2186974574
Short name T144
Test name
Test status
Simulation time 79098167934 ps
CPU time 108.53 seconds
Started Jul 22 07:00:44 PM PDT 24
Finished Jul 22 07:02:42 PM PDT 24
Peak memory 191648 kb
Host smart-4de956e9-1d86-44c2-b7fc-6b7b6d5950e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186974574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.2186974574
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.1800851838
Short name T167
Test name
Test status
Simulation time 105063746383 ps
CPU time 182.97 seconds
Started Jul 22 07:00:36 PM PDT 24
Finished Jul 22 07:03:52 PM PDT 24
Peak memory 191768 kb
Host smart-169d9273-cdde-4e72-be8e-5cab8781561d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800851838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.1800851838
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.3615117321
Short name T262
Test name
Test status
Simulation time 3834738550506 ps
CPU time 1018.27 seconds
Started Jul 22 06:59:34 PM PDT 24
Finished Jul 22 07:16:49 PM PDT 24
Peak memory 183556 kb
Host smart-0e95cac8-b5b0-4f60-b275-2bf7e19c9758
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615117321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.3615117321
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.361721141
Short name T410
Test name
Test status
Simulation time 197066049558 ps
CPU time 173.5 seconds
Started Jul 22 06:59:33 PM PDT 24
Finished Jul 22 07:02:43 PM PDT 24
Peak memory 183564 kb
Host smart-624d5c85-4859-4a65-901a-ff2b84ecb746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361721141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.361721141
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.1349393810
Short name T263
Test name
Test status
Simulation time 15357070861 ps
CPU time 128.28 seconds
Started Jul 22 06:59:34 PM PDT 24
Finished Jul 22 07:01:59 PM PDT 24
Peak memory 183576 kb
Host smart-332a8815-31f4-458a-991f-5e097d303989
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349393810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.1349393810
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.4205133400
Short name T246
Test name
Test status
Simulation time 45889577733 ps
CPU time 78.11 seconds
Started Jul 22 07:01:00 PM PDT 24
Finished Jul 22 07:02:21 PM PDT 24
Peak memory 191784 kb
Host smart-192ee870-801a-4bb7-af4f-de5ac53729fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205133400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.4205133400
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.2676920891
Short name T120
Test name
Test status
Simulation time 507866858721 ps
CPU time 1583.46 seconds
Started Jul 22 07:00:35 PM PDT 24
Finished Jul 22 07:27:12 PM PDT 24
Peak memory 191800 kb
Host smart-bcadc029-e0f9-46f0-9fb0-896229e95283
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676920891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.2676920891
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.1621811228
Short name T302
Test name
Test status
Simulation time 146215294345 ps
CPU time 485.49 seconds
Started Jul 22 07:00:34 PM PDT 24
Finished Jul 22 07:08:52 PM PDT 24
Peak memory 191788 kb
Host smart-b69fea46-13f2-44ae-9e16-3f57543364b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621811228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.1621811228
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.1219800246
Short name T332
Test name
Test status
Simulation time 1651068519373 ps
CPU time 594.28 seconds
Started Jul 22 07:01:18 PM PDT 24
Finished Jul 22 07:11:15 PM PDT 24
Peak memory 191788 kb
Host smart-bf88cc42-60d0-4636-bb82-8529c85f8ecc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219800246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.1219800246
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.3409633713
Short name T255
Test name
Test status
Simulation time 406452121625 ps
CPU time 671.82 seconds
Started Jul 22 07:01:18 PM PDT 24
Finished Jul 22 07:12:32 PM PDT 24
Peak memory 191788 kb
Host smart-513ff71e-4da4-49a3-862c-ec7bdd694409
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409633713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.3409633713
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.1795293673
Short name T358
Test name
Test status
Simulation time 982734564995 ps
CPU time 641.06 seconds
Started Jul 22 07:00:40 PM PDT 24
Finished Jul 22 07:11:31 PM PDT 24
Peak memory 191776 kb
Host smart-35fe0075-daab-4b32-94fa-55973ff2b654
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795293673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.1795293673
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.4172133323
Short name T136
Test name
Test status
Simulation time 496783620416 ps
CPU time 118.32 seconds
Started Jul 22 07:00:32 PM PDT 24
Finished Jul 22 07:02:44 PM PDT 24
Peak memory 183580 kb
Host smart-9f7ff3fc-29e1-4b41-96bb-7f3280b2ea51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172133323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.4172133323
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.264946015
Short name T233
Test name
Test status
Simulation time 29455563829 ps
CPU time 45.89 seconds
Started Jul 22 07:00:41 PM PDT 24
Finished Jul 22 07:01:37 PM PDT 24
Peak memory 195284 kb
Host smart-e83ca656-5263-42d1-9da3-ae9c5844d339
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264946015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.264946015
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.1243617635
Short name T346
Test name
Test status
Simulation time 373280170604 ps
CPU time 205.08 seconds
Started Jul 22 07:02:54 PM PDT 24
Finished Jul 22 07:06:22 PM PDT 24
Peak memory 191752 kb
Host smart-a9d5ecfc-af79-4f0a-8bcb-439afdc6f8b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243617635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.1243617635
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.1492346970
Short name T408
Test name
Test status
Simulation time 135000409955 ps
CPU time 388.24 seconds
Started Jul 22 07:02:54 PM PDT 24
Finished Jul 22 07:09:25 PM PDT 24
Peak memory 191760 kb
Host smart-8a17e626-cd34-4821-88b6-9a7f52a20435
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492346970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.1492346970
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.3569239743
Short name T171
Test name
Test status
Simulation time 276430222259 ps
CPU time 449.61 seconds
Started Jul 22 06:59:38 PM PDT 24
Finished Jul 22 07:07:24 PM PDT 24
Peak memory 183552 kb
Host smart-2819480d-93c5-494e-88f1-59f7a42c2a65
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569239743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.3569239743
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.841852405
Short name T434
Test name
Test status
Simulation time 715125391143 ps
CPU time 118.36 seconds
Started Jul 22 06:59:32 PM PDT 24
Finished Jul 22 07:01:47 PM PDT 24
Peak memory 183628 kb
Host smart-a6e21ed6-2503-4987-bd66-fefbf4b485e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841852405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.841852405
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.3803150971
Short name T190
Test name
Test status
Simulation time 1953788322063 ps
CPU time 671.61 seconds
Started Jul 22 06:59:36 PM PDT 24
Finished Jul 22 07:11:04 PM PDT 24
Peak memory 191824 kb
Host smart-dd3727a6-f53a-407f-a5d8-18acc4723607
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803150971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.3803150971
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.4193837720
Short name T423
Test name
Test status
Simulation time 26621053986 ps
CPU time 41.36 seconds
Started Jul 22 06:59:34 PM PDT 24
Finished Jul 22 07:00:32 PM PDT 24
Peak memory 183592 kb
Host smart-480ced7c-a3aa-4e33-8e61-c41f67c249f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193837720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.4193837720
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/81.rv_timer_random.973508268
Short name T145
Test name
Test status
Simulation time 17621623163 ps
CPU time 144.24 seconds
Started Jul 22 07:00:42 PM PDT 24
Finished Jul 22 07:03:16 PM PDT 24
Peak memory 183664 kb
Host smart-d619ee0a-81d2-4246-8bc7-12911fb62f08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973508268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.973508268
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.3205347291
Short name T98
Test name
Test status
Simulation time 204763481401 ps
CPU time 2039.67 seconds
Started Jul 22 07:00:44 PM PDT 24
Finished Jul 22 07:34:53 PM PDT 24
Peak memory 195320 kb
Host smart-d5b48952-d7a1-4926-97bd-460d0ffb08d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205347291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.3205347291
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.246406840
Short name T333
Test name
Test status
Simulation time 178464021577 ps
CPU time 149.34 seconds
Started Jul 22 07:00:51 PM PDT 24
Finished Jul 22 07:03:26 PM PDT 24
Peak memory 191780 kb
Host smart-f4feb44b-5148-4daa-88dc-c2be02431e1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246406840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.246406840
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.979704976
Short name T288
Test name
Test status
Simulation time 183559174509 ps
CPU time 97.94 seconds
Started Jul 22 07:00:41 PM PDT 24
Finished Jul 22 07:02:29 PM PDT 24
Peak memory 183568 kb
Host smart-6640dd49-447f-42ef-be6e-064cc35ff3a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979704976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.979704976
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.407504699
Short name T135
Test name
Test status
Simulation time 228066996897 ps
CPU time 113.54 seconds
Started Jul 22 07:00:41 PM PDT 24
Finished Jul 22 07:02:45 PM PDT 24
Peak memory 191680 kb
Host smart-123a4cad-bc2b-4a74-885f-750b0e8610ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407504699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.407504699
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.2946445077
Short name T7
Test name
Test status
Simulation time 48991559650 ps
CPU time 76.06 seconds
Started Jul 22 07:00:57 PM PDT 24
Finished Jul 22 07:02:18 PM PDT 24
Peak memory 191788 kb
Host smart-904db28d-bbad-4965-a7fc-71069f2d9d24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946445077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.2946445077
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.3727094085
Short name T148
Test name
Test status
Simulation time 394190236326 ps
CPU time 442.51 seconds
Started Jul 22 07:00:50 PM PDT 24
Finished Jul 22 07:08:18 PM PDT 24
Peak memory 191776 kb
Host smart-f67b96eb-c81d-454d-a8a6-7abeb6c9d162
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727094085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.3727094085
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.166078963
Short name T326
Test name
Test status
Simulation time 520445366189 ps
CPU time 106.97 seconds
Started Jul 22 07:00:47 PM PDT 24
Finished Jul 22 07:02:41 PM PDT 24
Peak memory 183564 kb
Host smart-4d3d62bc-7f55-4087-a76f-500f94b711bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166078963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.166078963
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.2536355095
Short name T257
Test name
Test status
Simulation time 115778499845 ps
CPU time 641.03 seconds
Started Jul 22 07:00:42 PM PDT 24
Finished Jul 22 07:11:33 PM PDT 24
Peak memory 191776 kb
Host smart-36068db8-c8c4-456e-8796-00570467abd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536355095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.2536355095
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.2328015640
Short name T274
Test name
Test status
Simulation time 4092372344419 ps
CPU time 1037.1 seconds
Started Jul 22 06:59:42 PM PDT 24
Finished Jul 22 07:17:13 PM PDT 24
Peak memory 183644 kb
Host smart-4807e09d-8cab-4c0e-bd12-807bce555074
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328015640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.2328015640
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.3932594868
Short name T381
Test name
Test status
Simulation time 85919482528 ps
CPU time 50.63 seconds
Started Jul 22 06:59:35 PM PDT 24
Finished Jul 22 07:00:43 PM PDT 24
Peak memory 183588 kb
Host smart-d67eb27a-0794-481a-8638-a639c65d528e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932594868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.3932594868
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.2127191849
Short name T138
Test name
Test status
Simulation time 482028083927 ps
CPU time 118.16 seconds
Started Jul 22 06:59:34 PM PDT 24
Finished Jul 22 07:01:49 PM PDT 24
Peak memory 191872 kb
Host smart-20410ac0-b996-4b0d-a227-92b09dce6905
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127191849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.2127191849
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.174951154
Short name T396
Test name
Test status
Simulation time 727510626 ps
CPU time 1.89 seconds
Started Jul 22 06:59:33 PM PDT 24
Finished Jul 22 06:59:51 PM PDT 24
Peak memory 183620 kb
Host smart-c1a15685-e7d3-445d-b382-6fee2ebdc077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174951154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.174951154
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.1459218519
Short name T92
Test name
Test status
Simulation time 59831846 ps
CPU time 0.54 seconds
Started Jul 22 06:59:41 PM PDT 24
Finished Jul 22 06:59:56 PM PDT 24
Peak memory 183412 kb
Host smart-2e715986-0281-4308-a872-06886908b91d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459218519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
1459218519
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/90.rv_timer_random.3020251123
Short name T134
Test name
Test status
Simulation time 55511575947 ps
CPU time 85.48 seconds
Started Jul 22 07:00:50 PM PDT 24
Finished Jul 22 07:02:21 PM PDT 24
Peak memory 191788 kb
Host smart-145fd14c-8b78-4da7-a114-a2e0f21c89b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020251123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.3020251123
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.1559361336
Short name T321
Test name
Test status
Simulation time 19992418190 ps
CPU time 34.93 seconds
Started Jul 22 07:02:35 PM PDT 24
Finished Jul 22 07:03:12 PM PDT 24
Peak memory 183512 kb
Host smart-6142f44e-16f1-449f-b9ce-2b2d42821940
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559361336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.1559361336
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.2860928908
Short name T129
Test name
Test status
Simulation time 177868820813 ps
CPU time 112.99 seconds
Started Jul 22 07:00:45 PM PDT 24
Finished Jul 22 07:02:47 PM PDT 24
Peak memory 183584 kb
Host smart-b8fd75e4-ed5c-4aee-ae4e-c4757360e897
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860928908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.2860928908
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.714845056
Short name T275
Test name
Test status
Simulation time 55855057486 ps
CPU time 84.46 seconds
Started Jul 22 07:00:52 PM PDT 24
Finished Jul 22 07:02:21 PM PDT 24
Peak memory 191780 kb
Host smart-975628ec-3333-489d-ad24-515f8a4390e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714845056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.714845056
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.3026988997
Short name T166
Test name
Test status
Simulation time 332744573132 ps
CPU time 723.56 seconds
Started Jul 22 07:00:50 PM PDT 24
Finished Jul 22 07:12:59 PM PDT 24
Peak memory 191784 kb
Host smart-f9d84a0d-5f0e-41b8-90e8-0fda96499d60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026988997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.3026988997
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.2870124681
Short name T251
Test name
Test status
Simulation time 59165153680 ps
CPU time 972.79 seconds
Started Jul 22 07:00:40 PM PDT 24
Finished Jul 22 07:17:04 PM PDT 24
Peak memory 191844 kb
Host smart-9a1f928d-cb35-4f4f-86a5-a2f498770330
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870124681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.2870124681
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.1943528964
Short name T353
Test name
Test status
Simulation time 34561678652 ps
CPU time 54.39 seconds
Started Jul 22 07:00:50 PM PDT 24
Finished Jul 22 07:01:50 PM PDT 24
Peak memory 195404 kb
Host smart-74d96789-d13f-49ef-8749-dbc3074e05eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943528964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.1943528964
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.3546219576
Short name T173
Test name
Test status
Simulation time 148783637502 ps
CPU time 459.49 seconds
Started Jul 22 07:00:55 PM PDT 24
Finished Jul 22 07:08:39 PM PDT 24
Peak memory 191824 kb
Host smart-bbcd8489-716d-4379-8deb-434da6987b65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546219576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.3546219576
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.3808607080
Short name T329
Test name
Test status
Simulation time 12908733697 ps
CPU time 21.04 seconds
Started Jul 22 07:01:20 PM PDT 24
Finished Jul 22 07:01:43 PM PDT 24
Peak memory 183644 kb
Host smart-583669a6-c7a5-47d9-9d0b-94903c90b1cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808607080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.3808607080
Directory /workspace/99.rv_timer_random/latest
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