Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.62 99.36 98.73 100.00 100.00 100.00 99.66


Total test records in report: 580
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T506 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.4124351949 Jul 23 05:33:19 PM PDT 24 Jul 23 05:33:23 PM PDT 24 157899552 ps
T507 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.3518122993 Jul 23 05:33:20 PM PDT 24 Jul 23 05:33:23 PM PDT 24 198237524 ps
T508 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.3324813896 Jul 23 05:33:41 PM PDT 24 Jul 23 05:33:42 PM PDT 24 46177189 ps
T509 /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.222614072 Jul 23 05:34:07 PM PDT 24 Jul 23 05:34:09 PM PDT 24 28814871 ps
T510 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.3721880182 Jul 23 05:33:25 PM PDT 24 Jul 23 05:33:28 PM PDT 24 37269686 ps
T511 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3473604626 Jul 23 05:33:47 PM PDT 24 Jul 23 05:33:48 PM PDT 24 68926058 ps
T512 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.587130842 Jul 23 05:33:57 PM PDT 24 Jul 23 05:34:00 PM PDT 24 13378346 ps
T513 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.739304596 Jul 23 05:34:06 PM PDT 24 Jul 23 05:34:07 PM PDT 24 38970780 ps
T514 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.3165323606 Jul 23 05:33:27 PM PDT 24 Jul 23 05:33:31 PM PDT 24 386931391 ps
T515 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.3491885203 Jul 23 05:33:51 PM PDT 24 Jul 23 05:33:53 PM PDT 24 63435395 ps
T82 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.2669275673 Jul 23 05:33:33 PM PDT 24 Jul 23 05:33:35 PM PDT 24 302678828 ps
T69 /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.4200111090 Jul 23 05:33:33 PM PDT 24 Jul 23 05:33:35 PM PDT 24 24304952 ps
T516 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.2958974561 Jul 23 05:34:08 PM PDT 24 Jul 23 05:34:10 PM PDT 24 50537996 ps
T517 /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1228345448 Jul 23 05:33:57 PM PDT 24 Jul 23 05:33:58 PM PDT 24 25232786 ps
T518 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.2892674255 Jul 23 05:33:47 PM PDT 24 Jul 23 05:33:49 PM PDT 24 27361812 ps
T519 /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.4249127045 Jul 23 05:33:49 PM PDT 24 Jul 23 05:33:51 PM PDT 24 22947285 ps
T520 /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.2475883666 Jul 23 05:33:52 PM PDT 24 Jul 23 05:33:54 PM PDT 24 38901953 ps
T521 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.3419695773 Jul 23 05:33:49 PM PDT 24 Jul 23 05:33:52 PM PDT 24 24321163 ps
T522 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.4068310146 Jul 23 05:34:10 PM PDT 24 Jul 23 05:34:12 PM PDT 24 37616034 ps
T523 /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.3159904152 Jul 23 05:33:45 PM PDT 24 Jul 23 05:33:46 PM PDT 24 21509681 ps
T524 /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3894074062 Jul 23 05:33:57 PM PDT 24 Jul 23 05:34:01 PM PDT 24 28134122 ps
T525 /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.1225758740 Jul 23 05:33:33 PM PDT 24 Jul 23 05:33:35 PM PDT 24 50136376 ps
T526 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.2744479721 Jul 23 05:34:07 PM PDT 24 Jul 23 05:34:09 PM PDT 24 47202345 ps
T527 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.621285451 Jul 23 05:33:26 PM PDT 24 Jul 23 05:33:31 PM PDT 24 192376558 ps
T528 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.1693051231 Jul 23 05:33:32 PM PDT 24 Jul 23 05:33:34 PM PDT 24 33779888 ps
T529 /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.1587121941 Jul 23 05:33:58 PM PDT 24 Jul 23 05:34:01 PM PDT 24 11474995 ps
T530 /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.2698772521 Jul 23 05:34:06 PM PDT 24 Jul 23 05:34:08 PM PDT 24 13891917 ps
T531 /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.1036543612 Jul 23 05:33:49 PM PDT 24 Jul 23 05:33:51 PM PDT 24 27096571 ps
T532 /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.3090270172 Jul 23 05:33:27 PM PDT 24 Jul 23 05:33:30 PM PDT 24 13984326 ps
T533 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.11497010 Jul 23 05:33:51 PM PDT 24 Jul 23 05:33:53 PM PDT 24 41210552 ps
T534 /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.1377644775 Jul 23 05:33:58 PM PDT 24 Jul 23 05:34:01 PM PDT 24 40584298 ps
T535 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.2816047429 Jul 23 05:33:51 PM PDT 24 Jul 23 05:33:53 PM PDT 24 24935006 ps
T536 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.2885800184 Jul 23 05:33:27 PM PDT 24 Jul 23 05:33:30 PM PDT 24 20603517 ps
T537 /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.3844450627 Jul 23 05:33:32 PM PDT 24 Jul 23 05:33:34 PM PDT 24 126485669 ps
T538 /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.2370100052 Jul 23 05:33:26 PM PDT 24 Jul 23 05:33:30 PM PDT 24 19949233 ps
T539 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1655984310 Jul 23 05:33:26 PM PDT 24 Jul 23 05:33:30 PM PDT 24 118909389 ps
T540 /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.1409237743 Jul 23 05:33:58 PM PDT 24 Jul 23 05:34:01 PM PDT 24 125080828 ps
T541 /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.2978069375 Jul 23 05:33:24 PM PDT 24 Jul 23 05:33:27 PM PDT 24 50127531 ps
T542 /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.184727525 Jul 23 05:33:31 PM PDT 24 Jul 23 05:33:33 PM PDT 24 89719165 ps
T543 /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.294908564 Jul 23 05:33:41 PM PDT 24 Jul 23 05:33:42 PM PDT 24 229605752 ps
T544 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1122388258 Jul 23 05:34:05 PM PDT 24 Jul 23 05:34:07 PM PDT 24 44553670 ps
T545 /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3730403774 Jul 23 05:33:24 PM PDT 24 Jul 23 05:33:26 PM PDT 24 511088668 ps
T546 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.1885782460 Jul 23 05:33:43 PM PDT 24 Jul 23 05:33:45 PM PDT 24 298773642 ps
T83 /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.3731895988 Jul 23 05:33:31 PM PDT 24 Jul 23 05:33:33 PM PDT 24 50946702 ps
T547 /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.4013379490 Jul 23 05:33:42 PM PDT 24 Jul 23 05:33:43 PM PDT 24 26944883 ps
T548 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2604690669 Jul 23 05:34:04 PM PDT 24 Jul 23 05:34:05 PM PDT 24 19262236 ps
T549 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.243913071 Jul 23 05:33:42 PM PDT 24 Jul 23 05:33:43 PM PDT 24 43439237 ps
T550 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.43207606 Jul 23 05:34:04 PM PDT 24 Jul 23 05:34:05 PM PDT 24 18214621 ps
T551 /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.2546624490 Jul 23 05:33:52 PM PDT 24 Jul 23 05:33:54 PM PDT 24 117930675 ps
T552 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1959545092 Jul 23 05:33:57 PM PDT 24 Jul 23 05:34:00 PM PDT 24 197447779 ps
T553 /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.3433884319 Jul 23 05:33:36 PM PDT 24 Jul 23 05:33:38 PM PDT 24 39157578 ps
T554 /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.2844680550 Jul 23 05:33:50 PM PDT 24 Jul 23 05:33:54 PM PDT 24 520659957 ps
T555 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.1603765952 Jul 23 05:33:27 PM PDT 24 Jul 23 05:33:31 PM PDT 24 100456749 ps
T556 /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2959483725 Jul 23 05:33:48 PM PDT 24 Jul 23 05:33:50 PM PDT 24 26494464 ps
T557 /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.1233377418 Jul 23 05:33:26 PM PDT 24 Jul 23 05:33:32 PM PDT 24 3057889901 ps
T558 /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.1226601299 Jul 23 05:33:58 PM PDT 24 Jul 23 05:34:02 PM PDT 24 41423209 ps
T559 /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.24992688 Jul 23 05:34:05 PM PDT 24 Jul 23 05:34:07 PM PDT 24 16037044 ps
T560 /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.295012727 Jul 23 05:33:26 PM PDT 24 Jul 23 05:33:30 PM PDT 24 99549673 ps
T561 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.199898598 Jul 23 05:33:26 PM PDT 24 Jul 23 05:33:29 PM PDT 24 59754426 ps
T562 /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.2832660868 Jul 23 05:33:33 PM PDT 24 Jul 23 05:33:35 PM PDT 24 153709501 ps
T563 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.2068640563 Jul 23 05:33:57 PM PDT 24 Jul 23 05:34:00 PM PDT 24 36992568 ps
T564 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.120788057 Jul 23 05:33:58 PM PDT 24 Jul 23 05:34:01 PM PDT 24 81989985 ps
T565 /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.604867320 Jul 23 05:34:06 PM PDT 24 Jul 23 05:34:09 PM PDT 24 93405348 ps
T566 /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.836026556 Jul 23 05:33:32 PM PDT 24 Jul 23 05:33:34 PM PDT 24 11050657 ps
T567 /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2241681214 Jul 23 05:34:07 PM PDT 24 Jul 23 05:34:09 PM PDT 24 11092904 ps
T568 /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.732994181 Jul 23 05:33:26 PM PDT 24 Jul 23 05:33:30 PM PDT 24 25818954 ps
T569 /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1181825214 Jul 23 05:33:49 PM PDT 24 Jul 23 05:33:52 PM PDT 24 91425563 ps
T570 /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3896683882 Jul 23 05:33:52 PM PDT 24 Jul 23 05:33:54 PM PDT 24 111390435 ps
T571 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.4081073008 Jul 23 05:33:57 PM PDT 24 Jul 23 05:34:00 PM PDT 24 31576880 ps
T572 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.1373626653 Jul 23 05:33:43 PM PDT 24 Jul 23 05:33:44 PM PDT 24 125019699 ps
T573 /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.4077149463 Jul 23 05:34:06 PM PDT 24 Jul 23 05:34:08 PM PDT 24 38925484 ps
T574 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.702280304 Jul 23 05:33:51 PM PDT 24 Jul 23 05:33:53 PM PDT 24 120586962 ps
T575 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.1906223576 Jul 23 05:33:49 PM PDT 24 Jul 23 05:33:51 PM PDT 24 197583152 ps
T71 /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3375442483 Jul 23 05:33:24 PM PDT 24 Jul 23 05:33:25 PM PDT 24 46043637 ps
T70 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.1251076561 Jul 23 05:33:24 PM PDT 24 Jul 23 05:33:25 PM PDT 24 63253434 ps
T576 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.700852686 Jul 23 05:33:57 PM PDT 24 Jul 23 05:34:00 PM PDT 24 43754132 ps
T577 /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.4184685575 Jul 23 05:33:26 PM PDT 24 Jul 23 05:33:29 PM PDT 24 20387558 ps
T578 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.1425868496 Jul 23 05:33:47 PM PDT 24 Jul 23 05:33:49 PM PDT 24 17977476 ps
T579 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.252509297 Jul 23 05:34:08 PM PDT 24 Jul 23 05:34:10 PM PDT 24 91538764 ps
T580 /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.2379157303 Jul 23 05:33:41 PM PDT 24 Jul 23 05:33:42 PM PDT 24 16769556 ps

Test location /workspace/coverage/default/13.rv_timer_random_reset.2575531117
Short name T3
Test name
Test status
Simulation time 36660116856 ps
CPU time 1419.86 seconds
Started Jul 23 05:34:33 PM PDT 24
Finished Jul 23 05:58:14 PM PDT 24
Peak memory 183576 kb
Host smart-f4515595-7550-44ae-aeb7-7fef2bd64de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575531117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.2575531117
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all_with_rand_reset.2900784707
Short name T13
Test name
Test status
Simulation time 169069448568 ps
CPU time 523.47 seconds
Started Jul 23 05:35:46 PM PDT 24
Finished Jul 23 05:44:30 PM PDT 24
Peak memory 206472 kb
Host smart-fe775b07-d275-44e0-8166-06fc989498f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900784707 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all_with_rand_reset.2900784707
Directory /workspace/42.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.106191949
Short name T5
Test name
Test status
Simulation time 2595457659062 ps
CPU time 1624.43 seconds
Started Jul 23 05:36:00 PM PDT 24
Finished Jul 23 06:03:06 PM PDT 24
Peak memory 191796 kb
Host smart-3f9fedfb-cf9e-4944-b8c6-a959a174edd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106191949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all.
106191949
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.1857045711
Short name T136
Test name
Test status
Simulation time 1107724781303 ps
CPU time 1764.06 seconds
Started Jul 23 05:34:43 PM PDT 24
Finished Jul 23 06:04:08 PM PDT 24
Peak memory 191740 kb
Host smart-4b9d728c-2dc7-48e4-9b06-5da799e2ddca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857045711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.1857045711
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3435806528
Short name T27
Test name
Test status
Simulation time 97744323 ps
CPU time 1.08 seconds
Started Jul 23 05:33:56 PM PDT 24
Finished Jul 23 05:33:58 PM PDT 24
Peak memory 195340 kb
Host smart-2e1ba223-5080-4308-abad-6ffb6bd42a0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435806528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.3435806528
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.3149518053
Short name T92
Test name
Test status
Simulation time 3016681668107 ps
CPU time 2726.96 seconds
Started Jul 23 05:36:18 PM PDT 24
Finished Jul 23 06:21:48 PM PDT 24
Peak memory 196224 kb
Host smart-13d537ae-7166-445b-966d-b7f41839216e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149518053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.3149518053
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.1057516411
Short name T132
Test name
Test status
Simulation time 896753999854 ps
CPU time 1980.75 seconds
Started Jul 23 05:34:51 PM PDT 24
Finished Jul 23 06:07:53 PM PDT 24
Peak memory 191772 kb
Host smart-14e28417-a3bb-4fbb-bd53-86f4dbfcee07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057516411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.1057516411
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.1507468674
Short name T189
Test name
Test status
Simulation time 3694440202902 ps
CPU time 2105.54 seconds
Started Jul 23 05:34:31 PM PDT 24
Finished Jul 23 06:09:38 PM PDT 24
Peak memory 197932 kb
Host smart-2b4cf606-2312-4074-8e4e-d4b8fa1fad67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507468674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.1507468674
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.4127660040
Short name T145
Test name
Test status
Simulation time 542407333468 ps
CPU time 2467.36 seconds
Started Jul 23 05:34:23 PM PDT 24
Finished Jul 23 06:15:31 PM PDT 24
Peak memory 191712 kb
Host smart-1f1f40b3-88b8-4d9a-aa7b-2dccd0c93013
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127660040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.4127660040
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.2893227721
Short name T16
Test name
Test status
Simulation time 82551765 ps
CPU time 0.96 seconds
Started Jul 23 05:34:08 PM PDT 24
Finished Jul 23 05:34:11 PM PDT 24
Peak memory 214928 kb
Host smart-ca2e46e6-987b-4dce-9a9e-f9ae1a8798f9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893227721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.2893227721
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/151.rv_timer_random.792021870
Short name T222
Test name
Test status
Simulation time 117436579037 ps
CPU time 232.93 seconds
Started Jul 23 05:37:36 PM PDT 24
Finished Jul 23 05:41:30 PM PDT 24
Peak memory 191756 kb
Host smart-9630ec75-dcff-45fc-ac5f-b4968693cf76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792021870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.792021870
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.1770841387
Short name T102
Test name
Test status
Simulation time 540757478898 ps
CPU time 439.96 seconds
Started Jul 23 05:38:15 PM PDT 24
Finished Jul 23 05:45:37 PM PDT 24
Peak memory 191736 kb
Host smart-bf3ebe91-50a3-4496-b60b-141894a5a6ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770841387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.1770841387
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.754769196
Short name T93
Test name
Test status
Simulation time 1496630232906 ps
CPU time 681.52 seconds
Started Jul 23 05:34:12 PM PDT 24
Finished Jul 23 05:45:35 PM PDT 24
Peak memory 195452 kb
Host smart-2e1a07be-62ed-4fde-8152-f81526f3a551
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754769196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.754769196
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.2354249925
Short name T96
Test name
Test status
Simulation time 843401608396 ps
CPU time 1022.47 seconds
Started Jul 23 05:34:51 PM PDT 24
Finished Jul 23 05:51:55 PM PDT 24
Peak memory 191756 kb
Host smart-543e59ff-5435-4671-b545-2891dc09c755
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354249925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.2354249925
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.1423275706
Short name T152
Test name
Test status
Simulation time 790398533773 ps
CPU time 4142.26 seconds
Started Jul 23 05:34:35 PM PDT 24
Finished Jul 23 06:43:38 PM PDT 24
Peak memory 191748 kb
Host smart-c85d7f59-b5c5-4a38-af0f-0e2834d712e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423275706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.1423275706
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.668827836
Short name T67
Test name
Test status
Simulation time 14870749 ps
CPU time 0.76 seconds
Started Jul 23 05:33:25 PM PDT 24
Finished Jul 23 05:33:28 PM PDT 24
Peak memory 182936 kb
Host smart-e7e64d37-26ae-44b5-9482-1e35144edaef
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668827836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alias
ing.668827836
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.847989347
Short name T53
Test name
Test status
Simulation time 538519904023 ps
CPU time 1062.77 seconds
Started Jul 23 05:34:09 PM PDT 24
Finished Jul 23 05:51:53 PM PDT 24
Peak memory 191876 kb
Host smart-cc26cc57-0f73-4936-95f3-4dfcb951b68b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847989347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.847989347
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.453513258
Short name T277
Test name
Test status
Simulation time 616377346642 ps
CPU time 1122.88 seconds
Started Jul 23 05:34:44 PM PDT 24
Finished Jul 23 05:53:28 PM PDT 24
Peak memory 194932 kb
Host smart-45ccb0e3-7cd9-4543-96d7-8931f508b755
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453513258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all.
453513258
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.328799453
Short name T148
Test name
Test status
Simulation time 177994218153 ps
CPU time 271.07 seconds
Started Jul 23 05:34:56 PM PDT 24
Finished Jul 23 05:39:27 PM PDT 24
Peak memory 191696 kb
Host smart-9c1d6331-a841-4ba5-9794-023f39f44620
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328799453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all.
328799453
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.1893937841
Short name T113
Test name
Test status
Simulation time 892425700123 ps
CPU time 2690.52 seconds
Started Jul 23 05:35:17 PM PDT 24
Finished Jul 23 06:20:09 PM PDT 24
Peak memory 191632 kb
Host smart-46871908-e6a7-49f2-9148-962a57c9d009
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893937841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.1893937841
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_random.2720657141
Short name T144
Test name
Test status
Simulation time 425388211660 ps
CPU time 202.9 seconds
Started Jul 23 05:35:34 PM PDT 24
Finished Jul 23 05:38:58 PM PDT 24
Peak memory 194936 kb
Host smart-abe411b2-85c4-4e19-b8a3-4d07c8404e0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720657141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.2720657141
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.1584672449
Short name T181
Test name
Test status
Simulation time 603542629260 ps
CPU time 3659.95 seconds
Started Jul 23 05:34:14 PM PDT 24
Finished Jul 23 06:35:15 PM PDT 24
Peak memory 191716 kb
Host smart-435f1e26-619c-4827-87f4-40adc72a9e5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584672449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
1584672449
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/66.rv_timer_random.4012076779
Short name T22
Test name
Test status
Simulation time 193028866007 ps
CPU time 838.19 seconds
Started Jul 23 05:36:34 PM PDT 24
Finished Jul 23 05:50:33 PM PDT 24
Peak memory 183564 kb
Host smart-0f1bb461-b2ca-43ed-91e5-08c94516a2e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012076779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.4012076779
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.4113751628
Short name T186
Test name
Test status
Simulation time 194230773172 ps
CPU time 329.87 seconds
Started Jul 23 05:36:43 PM PDT 24
Finished Jul 23 05:42:13 PM PDT 24
Peak memory 191724 kb
Host smart-7aac0e9a-1c83-4778-a95c-28b6d381149b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113751628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.4113751628
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.3059046790
Short name T209
Test name
Test status
Simulation time 406101986437 ps
CPU time 862.6 seconds
Started Jul 23 05:36:08 PM PDT 24
Finished Jul 23 05:50:31 PM PDT 24
Peak memory 196200 kb
Host smart-28727f08-0b36-4048-b164-ffe8ce62746a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059046790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.3059046790
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/82.rv_timer_random.3142529352
Short name T284
Test name
Test status
Simulation time 159977058991 ps
CPU time 508.69 seconds
Started Jul 23 05:36:50 PM PDT 24
Finished Jul 23 05:45:20 PM PDT 24
Peak memory 183588 kb
Host smart-6390e2f1-878f-498b-8a60-bf944ba69954
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142529352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.3142529352
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.3872591900
Short name T220
Test name
Test status
Simulation time 635653421496 ps
CPU time 2495.49 seconds
Started Jul 23 05:37:26 PM PDT 24
Finished Jul 23 06:19:03 PM PDT 24
Peak memory 191700 kb
Host smart-b5ab392f-c504-45d1-97da-7c304c0c948a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872591900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.3872591900
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.120413926
Short name T198
Test name
Test status
Simulation time 1445738421485 ps
CPU time 342.91 seconds
Started Jul 23 05:37:45 PM PDT 24
Finished Jul 23 05:43:28 PM PDT 24
Peak memory 191776 kb
Host smart-f11e1baf-25b1-49a7-8cc8-92436f3cc3ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120413926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.120413926
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.1111322994
Short name T95
Test name
Test status
Simulation time 172088059024 ps
CPU time 283.45 seconds
Started Jul 23 05:34:12 PM PDT 24
Finished Jul 23 05:38:57 PM PDT 24
Peak memory 196544 kb
Host smart-c54c0aef-f243-4b64-bca5-dd774f92519c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111322994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
1111322994
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.686517598
Short name T326
Test name
Test status
Simulation time 91900268905 ps
CPU time 300.58 seconds
Started Jul 23 05:35:34 PM PDT 24
Finished Jul 23 05:40:35 PM PDT 24
Peak memory 191768 kb
Host smart-6fe8dec7-86f9-4e93-a38e-b2b8b7eb5b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686517598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.686517598
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/58.rv_timer_random.494830088
Short name T1
Test name
Test status
Simulation time 175290911993 ps
CPU time 163.06 seconds
Started Jul 23 05:36:35 PM PDT 24
Finished Jul 23 05:39:19 PM PDT 24
Peak memory 191784 kb
Host smart-71bb3237-1f28-4e75-86f5-7b7eb7ff3a58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494830088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.494830088
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.13526254
Short name T320
Test name
Test status
Simulation time 192844907342 ps
CPU time 424.38 seconds
Started Jul 23 05:37:01 PM PDT 24
Finished Jul 23 05:44:06 PM PDT 24
Peak memory 191788 kb
Host smart-b7a0ef64-a4a5-46d3-bf59-71ae7d02e4a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13526254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.13526254
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.4232496847
Short name T52
Test name
Test status
Simulation time 203036977316 ps
CPU time 266.76 seconds
Started Jul 23 05:36:18 PM PDT 24
Finished Jul 23 05:40:47 PM PDT 24
Peak memory 195904 kb
Host smart-64a2bb73-302f-4cc5-8eab-f3507ac010f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232496847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.4232496847
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/11.rv_timer_random.3089658415
Short name T85
Test name
Test status
Simulation time 232113390462 ps
CPU time 123.43 seconds
Started Jul 23 05:34:24 PM PDT 24
Finished Jul 23 05:36:28 PM PDT 24
Peak memory 191736 kb
Host smart-f0abc147-6c9e-4914-8197-0a57fd69dae6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089658415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.3089658415
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.652353159
Short name T292
Test name
Test status
Simulation time 376624199923 ps
CPU time 1392.41 seconds
Started Jul 23 05:37:18 PM PDT 24
Finished Jul 23 06:00:33 PM PDT 24
Peak memory 192928 kb
Host smart-f211eb37-b5c6-4429-b884-e5ff5900cb19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652353159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.652353159
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random.1656881819
Short name T161
Test name
Test status
Simulation time 114589592087 ps
CPU time 108.37 seconds
Started Jul 23 05:34:34 PM PDT 24
Finished Jul 23 05:36:24 PM PDT 24
Peak memory 195676 kb
Host smart-9057edd6-cd4d-48a2-ad5a-a1be13d2851b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656881819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.1656881819
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.3570840465
Short name T99
Test name
Test status
Simulation time 339059072763 ps
CPU time 623.87 seconds
Started Jul 23 05:38:08 PM PDT 24
Finished Jul 23 05:48:33 PM PDT 24
Peak memory 191700 kb
Host smart-235f5008-d177-4298-9e85-f34eba2eaf71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570840465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.3570840465
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.1162821155
Short name T348
Test name
Test status
Simulation time 801608533329 ps
CPU time 925.8 seconds
Started Jul 23 05:35:07 PM PDT 24
Finished Jul 23 05:50:33 PM PDT 24
Peak memory 191672 kb
Host smart-5cdf5a2c-c9dd-4f51-9f4f-0d1943536c5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162821155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.1162821155
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/52.rv_timer_random.2880811594
Short name T114
Test name
Test status
Simulation time 64672761445 ps
CPU time 95.61 seconds
Started Jul 23 05:36:24 PM PDT 24
Finished Jul 23 05:38:01 PM PDT 24
Peak memory 191796 kb
Host smart-65a86ef4-967d-4459-9328-16b9154b5d10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880811594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.2880811594
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.3528554008
Short name T107
Test name
Test status
Simulation time 2079296442485 ps
CPU time 1104.48 seconds
Started Jul 23 05:37:35 PM PDT 24
Finished Jul 23 05:56:01 PM PDT 24
Peak memory 191628 kb
Host smart-f79700ca-7f22-4b28-a450-799bb20bf588
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528554008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.3528554008
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.3021673330
Short name T207
Test name
Test status
Simulation time 212975190573 ps
CPU time 1484.04 seconds
Started Jul 23 05:37:35 PM PDT 24
Finished Jul 23 06:02:20 PM PDT 24
Peak memory 191744 kb
Host smart-61aedf85-b7a1-489d-96b9-6952d398d434
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021673330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.3021673330
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.1628245988
Short name T215
Test name
Test status
Simulation time 427546415202 ps
CPU time 154.76 seconds
Started Jul 23 05:37:45 PM PDT 24
Finished Jul 23 05:40:20 PM PDT 24
Peak memory 191800 kb
Host smart-4ab5a7c4-8ca0-49e3-b217-8d50582e4f1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628245988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.1628245988
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.857400723
Short name T196
Test name
Test status
Simulation time 324184011500 ps
CPU time 341.39 seconds
Started Jul 23 05:34:42 PM PDT 24
Finished Jul 23 05:40:24 PM PDT 24
Peak memory 195732 kb
Host smart-8954b30c-6b26-4495-994f-fc7c09cf6e05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857400723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all.
857400723
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.1886537319
Short name T108
Test name
Test status
Simulation time 281746347540 ps
CPU time 290.76 seconds
Started Jul 23 05:34:54 PM PDT 24
Finished Jul 23 05:39:45 PM PDT 24
Peak memory 191688 kb
Host smart-c2e664d3-3b21-4385-9b34-dbf1849fc948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886537319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.1886537319
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.1615269442
Short name T188
Test name
Test status
Simulation time 428459977777 ps
CPU time 689.06 seconds
Started Jul 23 05:35:01 PM PDT 24
Finished Jul 23 05:46:30 PM PDT 24
Peak memory 191856 kb
Host smart-e1763dc9-78ae-4166-82c9-dccb4a014200
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615269442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.1615269442
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.401088851
Short name T175
Test name
Test status
Simulation time 67474207354 ps
CPU time 109.83 seconds
Started Jul 23 05:35:18 PM PDT 24
Finished Jul 23 05:37:09 PM PDT 24
Peak memory 183464 kb
Host smart-a3cacfb2-f0a8-428a-a907-05a23427c980
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401088851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.rv_timer_cfg_update_on_fly.401088851
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.2469094329
Short name T345
Test name
Test status
Simulation time 1807331471412 ps
CPU time 795.15 seconds
Started Jul 23 05:36:00 PM PDT 24
Finished Jul 23 05:49:16 PM PDT 24
Peak memory 183576 kb
Host smart-3de517f8-cee9-48fd-b500-e935008f2061
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469094329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.2469094329
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/65.rv_timer_random.1570161756
Short name T106
Test name
Test status
Simulation time 239946949420 ps
CPU time 442.76 seconds
Started Jul 23 05:36:34 PM PDT 24
Finished Jul 23 05:43:57 PM PDT 24
Peak memory 191772 kb
Host smart-5c93ead1-ee8d-4a7c-b367-92c2b4b093ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570161756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.1570161756
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/70.rv_timer_random.280768538
Short name T104
Test name
Test status
Simulation time 416846734213 ps
CPU time 792.63 seconds
Started Jul 23 05:36:44 PM PDT 24
Finished Jul 23 05:49:57 PM PDT 24
Peak memory 191764 kb
Host smart-3a29577f-a02b-49db-b384-433833d9722c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280768538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.280768538
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.1925724756
Short name T155
Test name
Test status
Simulation time 247939295465 ps
CPU time 485.86 seconds
Started Jul 23 05:36:42 PM PDT 24
Finished Jul 23 05:44:48 PM PDT 24
Peak memory 191748 kb
Host smart-16f8c4e1-6f1c-4c01-92cb-3f47093263a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925724756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.1925724756
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.2856566541
Short name T141
Test name
Test status
Simulation time 247170114259 ps
CPU time 205.99 seconds
Started Jul 23 05:36:52 PM PDT 24
Finished Jul 23 05:40:19 PM PDT 24
Peak memory 191728 kb
Host smart-f85c28f2-602e-40f4-a6bd-c5d971d52c7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856566541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.2856566541
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random.315931686
Short name T242
Test name
Test status
Simulation time 125123489036 ps
CPU time 200.99 seconds
Started Jul 23 05:34:15 PM PDT 24
Finished Jul 23 05:37:38 PM PDT 24
Peak memory 191776 kb
Host smart-d17392dd-7df4-459a-9f09-2204a505b38a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315931686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.315931686
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.2520811882
Short name T129
Test name
Test status
Simulation time 73361133327 ps
CPU time 281.43 seconds
Started Jul 23 05:37:27 PM PDT 24
Finished Jul 23 05:42:09 PM PDT 24
Peak memory 191780 kb
Host smart-8f562bcf-4039-4400-bf68-7733b74d733e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520811882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.2520811882
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.2587744878
Short name T173
Test name
Test status
Simulation time 611921091843 ps
CPU time 388.58 seconds
Started Jul 23 05:37:43 PM PDT 24
Finished Jul 23 05:44:12 PM PDT 24
Peak memory 195304 kb
Host smart-bab31798-b454-4d38-91a7-216352fd384c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587744878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.2587744878
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.3258368172
Short name T153
Test name
Test status
Simulation time 351967817522 ps
CPU time 577.28 seconds
Started Jul 23 05:38:24 PM PDT 24
Finished Jul 23 05:48:02 PM PDT 24
Peak memory 191800 kb
Host smart-4fff8242-662b-4d0b-803f-9ecbdf8e867b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258368172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.3258368172
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.2579029602
Short name T8
Test name
Test status
Simulation time 55827725314 ps
CPU time 197.16 seconds
Started Jul 23 05:35:32 PM PDT 24
Finished Jul 23 05:38:50 PM PDT 24
Peak memory 191768 kb
Host smart-cfbd9e0b-c574-4af6-9945-b785b0c4d781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579029602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.2579029602
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_random.4085348552
Short name T262
Test name
Test status
Simulation time 2138527330632 ps
CPU time 838.75 seconds
Started Jul 23 05:35:59 PM PDT 24
Finished Jul 23 05:49:58 PM PDT 24
Peak memory 191748 kb
Host smart-fbec16d0-322a-4683-a6b3-b88fa3c66bbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085348552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.4085348552
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.1581462451
Short name T187
Test name
Test status
Simulation time 376124326576 ps
CPU time 227.44 seconds
Started Jul 23 05:36:08 PM PDT 24
Finished Jul 23 05:39:57 PM PDT 24
Peak memory 183548 kb
Host smart-0dba3d01-e87d-42c0-b907-76279ab85ebd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581462451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.1581462451
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/75.rv_timer_random.2365347902
Short name T230
Test name
Test status
Simulation time 536147115985 ps
CPU time 687.65 seconds
Started Jul 23 05:36:43 PM PDT 24
Finished Jul 23 05:48:11 PM PDT 24
Peak memory 194312 kb
Host smart-587034b7-d7ac-4a2c-ae6a-1e0a52e9929a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365347902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.2365347902
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.890264653
Short name T312
Test name
Test status
Simulation time 188205174205 ps
CPU time 183.1 seconds
Started Jul 23 05:36:49 PM PDT 24
Finished Jul 23 05:39:54 PM PDT 24
Peak memory 191668 kb
Host smart-8a792405-03d3-46bb-892f-934ff984f610
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890264653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.890264653
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.2440183620
Short name T343
Test name
Test status
Simulation time 204057809278 ps
CPU time 720.17 seconds
Started Jul 23 05:37:01 PM PDT 24
Finished Jul 23 05:49:02 PM PDT 24
Peak memory 191784 kb
Host smart-827280de-a43c-4256-9511-0cd68e75c7f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440183620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.2440183620
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.3181168087
Short name T194
Test name
Test status
Simulation time 59266519993 ps
CPU time 63.74 seconds
Started Jul 23 05:36:59 PM PDT 24
Finished Jul 23 05:38:04 PM PDT 24
Peak memory 195388 kb
Host smart-6cfc9bf9-faa8-4170-a39f-3bc1f0e7a322
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181168087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.3181168087
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.714488647
Short name T76
Test name
Test status
Simulation time 57845597 ps
CPU time 0.81 seconds
Started Jul 23 05:33:19 PM PDT 24
Finished Jul 23 05:33:22 PM PDT 24
Peak memory 193520 kb
Host smart-8d1c1626-4dc1-4af4-ba2c-f89f8bdb1740
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714488647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_tim
er_same_csr_outstanding.714488647
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/176.rv_timer_random.1678471977
Short name T216
Test name
Test status
Simulation time 382333603724 ps
CPU time 364.53 seconds
Started Jul 23 05:38:03 PM PDT 24
Finished Jul 23 05:44:09 PM PDT 24
Peak memory 195648 kb
Host smart-661b73a1-f2e7-4a71-96e7-586ce8e08d19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678471977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.1678471977
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.2809456825
Short name T101
Test name
Test status
Simulation time 91225862321 ps
CPU time 77.54 seconds
Started Jul 23 05:38:16 PM PDT 24
Finished Jul 23 05:39:34 PM PDT 24
Peak memory 191744 kb
Host smart-6311b3d4-03b1-4c97-91e6-203dbb94393f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809456825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.2809456825
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.111995633
Short name T88
Test name
Test status
Simulation time 667848070293 ps
CPU time 535.08 seconds
Started Jul 23 05:38:24 PM PDT 24
Finished Jul 23 05:47:19 PM PDT 24
Peak memory 191700 kb
Host smart-8e65fe17-e348-404a-a655-188c9d5b3615
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111995633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.111995633
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.3634359224
Short name T178
Test name
Test status
Simulation time 4957237215325 ps
CPU time 1007.47 seconds
Started Jul 23 05:34:51 PM PDT 24
Finished Jul 23 05:51:39 PM PDT 24
Peak memory 191740 kb
Host smart-d0a50728-0013-43d9-b623-57408644627c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634359224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.3634359224
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.4010514233
Short name T301
Test name
Test status
Simulation time 85067914474 ps
CPU time 130.77 seconds
Started Jul 23 05:35:24 PM PDT 24
Finished Jul 23 05:37:36 PM PDT 24
Peak memory 191816 kb
Host smart-c2076d72-b0f8-4f14-852c-cf8ed4025c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010514233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.4010514233
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.3311220259
Short name T317
Test name
Test status
Simulation time 637749460989 ps
CPU time 599.85 seconds
Started Jul 23 05:35:46 PM PDT 24
Finished Jul 23 05:45:46 PM PDT 24
Peak memory 183500 kb
Host smart-8243dadc-b66d-45d2-9de1-32a17056b83e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311220259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.3311220259
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_random.1573737568
Short name T151
Test name
Test status
Simulation time 660558294429 ps
CPU time 604.77 seconds
Started Jul 23 05:35:45 PM PDT 24
Finished Jul 23 05:45:51 PM PDT 24
Peak memory 191772 kb
Host smart-be935ed1-758a-450f-9ad6-12be6b6cc94d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573737568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.1573737568
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.1906223576
Short name T575
Test name
Test status
Simulation time 197583152 ps
CPU time 1.3 seconds
Started Jul 23 05:33:49 PM PDT 24
Finished Jul 23 05:33:51 PM PDT 24
Peak memory 195396 kb
Host smart-afad3f7a-69fd-42cb-a14f-c132169ed9c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906223576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.1906223576
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.1842119334
Short name T4
Test name
Test status
Simulation time 68709493219 ps
CPU time 110.25 seconds
Started Jul 23 05:34:06 PM PDT 24
Finished Jul 23 05:35:58 PM PDT 24
Peak memory 183564 kb
Host smart-c675471c-ff91-4aef-9be2-b0b2158fa1b7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842119334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.1842119334
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.2750318042
Short name T267
Test name
Test status
Simulation time 333018385602 ps
CPU time 524.11 seconds
Started Jul 23 05:34:25 PM PDT 24
Finished Jul 23 05:43:10 PM PDT 24
Peak memory 183772 kb
Host smart-d2cf023f-dc7a-42ba-b1fe-bcf347dd4258
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750318042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.2750318042
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/100.rv_timer_random.1993012871
Short name T227
Test name
Test status
Simulation time 239225346081 ps
CPU time 218.37 seconds
Started Jul 23 05:37:00 PM PDT 24
Finished Jul 23 05:40:39 PM PDT 24
Peak memory 191788 kb
Host smart-f7d120b8-c851-4082-8b17-6a13bc4e28f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993012871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.1993012871
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.3941397163
Short name T89
Test name
Test status
Simulation time 78425925578 ps
CPU time 107.59 seconds
Started Jul 23 05:37:00 PM PDT 24
Finished Jul 23 05:38:49 PM PDT 24
Peak memory 195256 kb
Host smart-67fcae6d-7541-4563-9a18-f58a5c2d037f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941397163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.3941397163
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.1133219636
Short name T225
Test name
Test status
Simulation time 301758634965 ps
CPU time 562.34 seconds
Started Jul 23 05:37:12 PM PDT 24
Finished Jul 23 05:46:35 PM PDT 24
Peak memory 191772 kb
Host smart-7d64eaf3-0361-4768-b472-4f326199e9a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133219636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.1133219636
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.1670732982
Short name T208
Test name
Test status
Simulation time 90437808256 ps
CPU time 312.44 seconds
Started Jul 23 05:37:11 PM PDT 24
Finished Jul 23 05:42:24 PM PDT 24
Peak memory 191788 kb
Host smart-1cc36500-3366-4ac3-9261-9c673b519b9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670732982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.1670732982
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.3739846483
Short name T229
Test name
Test status
Simulation time 94896299954 ps
CPU time 118.29 seconds
Started Jul 23 05:37:10 PM PDT 24
Finished Jul 23 05:39:09 PM PDT 24
Peak memory 191752 kb
Host smart-45ac51d7-3526-431b-933d-d208651bfc1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739846483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.3739846483
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.2180498878
Short name T340
Test name
Test status
Simulation time 9181357892 ps
CPU time 15.15 seconds
Started Jul 23 05:34:24 PM PDT 24
Finished Jul 23 05:34:40 PM PDT 24
Peak memory 183564 kb
Host smart-e8f12ef8-3ec6-4ebf-b710-ba93aac72231
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180498878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.2180498878
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/113.rv_timer_random.1800397796
Short name T135
Test name
Test status
Simulation time 8093738330 ps
CPU time 65.33 seconds
Started Jul 23 05:37:10 PM PDT 24
Finished Jul 23 05:38:16 PM PDT 24
Peak memory 183576 kb
Host smart-0543beee-8fcb-4e55-b06a-2b66d4fabaa2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800397796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.1800397796
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.3695236844
Short name T436
Test name
Test status
Simulation time 58450018308 ps
CPU time 34.53 seconds
Started Jul 23 05:34:30 PM PDT 24
Finished Jul 23 05:35:05 PM PDT 24
Peak memory 183600 kb
Host smart-4cfc421e-384e-439c-81bc-2d529c511677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695236844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.3695236844
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/129.rv_timer_random.846420522
Short name T293
Test name
Test status
Simulation time 98765400983 ps
CPU time 291.32 seconds
Started Jul 23 05:37:19 PM PDT 24
Finished Jul 23 05:42:12 PM PDT 24
Peak memory 194932 kb
Host smart-7ef2d002-1b1c-4113-89dd-609848dead89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846420522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.846420522
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/130.rv_timer_random.2186777098
Short name T167
Test name
Test status
Simulation time 280286614332 ps
CPU time 198.19 seconds
Started Jul 23 05:37:18 PM PDT 24
Finished Jul 23 05:40:38 PM PDT 24
Peak memory 191768 kb
Host smart-b5872221-ef46-4e4a-88b8-3e7097f9f47c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186777098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.2186777098
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.3615732182
Short name T255
Test name
Test status
Simulation time 1633512075223 ps
CPU time 438.52 seconds
Started Jul 23 05:37:19 PM PDT 24
Finished Jul 23 05:44:39 PM PDT 24
Peak memory 191772 kb
Host smart-9aa3c5c2-e7bf-4c55-aaf6-fb8992e10290
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615732182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.3615732182
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.3800195344
Short name T98
Test name
Test status
Simulation time 759307075261 ps
CPU time 2269.67 seconds
Started Jul 23 05:37:24 PM PDT 24
Finished Jul 23 06:15:15 PM PDT 24
Peak memory 191636 kb
Host smart-46499271-e864-4125-a3ea-fb335df68a68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800195344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.3800195344
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.1075126892
Short name T254
Test name
Test status
Simulation time 99174868219 ps
CPU time 153.39 seconds
Started Jul 23 05:37:36 PM PDT 24
Finished Jul 23 05:40:10 PM PDT 24
Peak memory 191784 kb
Host smart-a2a7db10-d916-4d49-a772-7cb57fe5c15f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075126892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.1075126892
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.2046319130
Short name T351
Test name
Test status
Simulation time 48022985749 ps
CPU time 70.33 seconds
Started Jul 23 05:37:33 PM PDT 24
Finished Jul 23 05:38:44 PM PDT 24
Peak memory 183592 kb
Host smart-be92924a-a6a0-462b-a856-b4dbc61dc843
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046319130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.2046319130
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.1068556240
Short name T273
Test name
Test status
Simulation time 118469824136 ps
CPU time 182.78 seconds
Started Jul 23 05:37:43 PM PDT 24
Finished Jul 23 05:40:47 PM PDT 24
Peak memory 195260 kb
Host smart-9d09000f-8e49-40c1-92df-8ddb84919dc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068556240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.1068556240
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/170.rv_timer_random.3901426937
Short name T416
Test name
Test status
Simulation time 102452378515 ps
CPU time 1502.22 seconds
Started Jul 23 05:37:54 PM PDT 24
Finished Jul 23 06:02:57 PM PDT 24
Peak memory 191984 kb
Host smart-c260bf45-3797-4ce5-a140-528c99042da7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901426937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.3901426937
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.3011581889
Short name T115
Test name
Test status
Simulation time 166178768803 ps
CPU time 145.09 seconds
Started Jul 23 05:37:59 PM PDT 24
Finished Jul 23 05:40:25 PM PDT 24
Peak memory 191756 kb
Host smart-64a2da83-161d-4895-80ad-8af854441128
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011581889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.3011581889
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.3469180820
Short name T131
Test name
Test status
Simulation time 1654394176816 ps
CPU time 669.23 seconds
Started Jul 23 05:38:07 PM PDT 24
Finished Jul 23 05:49:17 PM PDT 24
Peak memory 191636 kb
Host smart-e271c9af-87b8-4936-a73e-c079a33e8640
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469180820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.3469180820
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.1994308354
Short name T180
Test name
Test status
Simulation time 286755857124 ps
CPU time 2205.15 seconds
Started Jul 23 05:34:46 PM PDT 24
Finished Jul 23 06:11:32 PM PDT 24
Peak memory 183364 kb
Host smart-711e0bf7-269f-4ff8-9375-51ef0f38433a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994308354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.1994308354
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.1510636607
Short name T110
Test name
Test status
Simulation time 41069422904 ps
CPU time 59.83 seconds
Started Jul 23 05:34:41 PM PDT 24
Finished Jul 23 05:35:42 PM PDT 24
Peak memory 183584 kb
Host smart-cb840075-6dd8-46c5-a179-b6136e71d6a2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510636607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.1510636607
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.1760071258
Short name T191
Test name
Test status
Simulation time 756848068171 ps
CPU time 1058.4 seconds
Started Jul 23 05:34:47 PM PDT 24
Finished Jul 23 05:52:26 PM PDT 24
Peak memory 183540 kb
Host smart-3b545a2a-e74c-46ae-8580-5f443f8ca39a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760071258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.1760071258
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.4120244098
Short name T358
Test name
Test status
Simulation time 113364409861 ps
CPU time 60.14 seconds
Started Jul 23 05:34:50 PM PDT 24
Finished Jul 23 05:35:51 PM PDT 24
Peak memory 183572 kb
Host smart-274a9a0e-f855-4e0c-8268-5989110b2857
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120244098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.4120244098
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.2616284876
Short name T156
Test name
Test status
Simulation time 1316351543616 ps
CPU time 587.49 seconds
Started Jul 23 05:34:51 PM PDT 24
Finished Jul 23 05:44:40 PM PDT 24
Peak memory 183528 kb
Host smart-d61c3f6c-7867-4046-b3db-39dee1458511
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616284876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.2616284876
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.2769660127
Short name T158
Test name
Test status
Simulation time 4376868709920 ps
CPU time 1614.48 seconds
Started Jul 23 05:35:03 PM PDT 24
Finished Jul 23 06:01:58 PM PDT 24
Peak memory 195736 kb
Host smart-e2af753e-c672-4e66-a832-9cf8b296fa6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769660127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.2769660127
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/79.rv_timer_random.2838339322
Short name T291
Test name
Test status
Simulation time 46189271448 ps
CPU time 69.06 seconds
Started Jul 23 05:36:45 PM PDT 24
Finished Jul 23 05:37:54 PM PDT 24
Peak memory 191788 kb
Host smart-4d8f9749-9855-4269-a9d0-04d0dc1c0d8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838339322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.2838339322
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.1911619299
Short name T231
Test name
Test status
Simulation time 36290635951 ps
CPU time 202.19 seconds
Started Jul 23 05:34:24 PM PDT 24
Finished Jul 23 05:37:47 PM PDT 24
Peak memory 183608 kb
Host smart-08f01cda-f4dc-4a61-9239-a5ded1c628e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911619299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.1911619299
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/84.rv_timer_random.1538322726
Short name T169
Test name
Test status
Simulation time 259526911955 ps
CPU time 556.64 seconds
Started Jul 23 05:36:50 PM PDT 24
Finished Jul 23 05:46:08 PM PDT 24
Peak memory 191764 kb
Host smart-2989e8fe-66fd-4a78-9498-cb2e26197235
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538322726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.1538322726
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.1089741027
Short name T485
Test name
Test status
Simulation time 15173789 ps
CPU time 0.6 seconds
Started Jul 23 05:33:16 PM PDT 24
Finished Jul 23 05:33:17 PM PDT 24
Peak memory 182956 kb
Host smart-3a9da595-2606-42bc-9f48-a06c20b4b01b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089741027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.1089741027
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3974669802
Short name T45
Test name
Test status
Simulation time 293710474 ps
CPU time 1.61 seconds
Started Jul 23 05:33:19 PM PDT 24
Finished Jul 23 05:33:23 PM PDT 24
Peak memory 192120 kb
Host smart-f5749740-2e4c-4cac-8035-c72c0be938d9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974669802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.3974669802
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.3258696728
Short name T505
Test name
Test status
Simulation time 176357308 ps
CPU time 0.53 seconds
Started Jul 23 05:33:19 PM PDT 24
Finished Jul 23 05:33:22 PM PDT 24
Peak memory 182604 kb
Host smart-15ea7dd2-7cfb-46da-92a2-fbbcd9a9a78e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258696728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.3258696728
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.557978560
Short name T467
Test name
Test status
Simulation time 79675690 ps
CPU time 0.71 seconds
Started Jul 23 05:33:17 PM PDT 24
Finished Jul 23 05:33:18 PM PDT 24
Peak memory 194940 kb
Host smart-2d7383ee-7bab-4d58-a1e3-e7ed20202e83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557978560 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.557978560
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.1417910587
Short name T64
Test name
Test status
Simulation time 44154774 ps
CPU time 0.55 seconds
Started Jul 23 05:33:19 PM PDT 24
Finished Jul 23 05:33:21 PM PDT 24
Peak memory 183176 kb
Host smart-405834aa-7ec5-4c3e-a93a-f3a92cf2aa99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417910587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.1417910587
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.2647572541
Short name T474
Test name
Test status
Simulation time 16794374 ps
CPU time 0.6 seconds
Started Jul 23 05:33:19 PM PDT 24
Finished Jul 23 05:33:22 PM PDT 24
Peak memory 182688 kb
Host smart-790b8434-f098-4cd1-a92d-a80841297843
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647572541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.2647572541
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.721402393
Short name T481
Test name
Test status
Simulation time 69045212 ps
CPU time 3.68 seconds
Started Jul 23 05:33:19 PM PDT 24
Finished Jul 23 05:33:26 PM PDT 24
Peak memory 197760 kb
Host smart-9d7f55ab-43ed-4682-af26-580a40cbfc32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721402393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.721402393
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.3518122993
Short name T507
Test name
Test status
Simulation time 198237524 ps
CPU time 1.41 seconds
Started Jul 23 05:33:20 PM PDT 24
Finished Jul 23 05:33:23 PM PDT 24
Peak memory 194552 kb
Host smart-38716e96-4c0c-49b2-a1fa-e0314104e349
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518122993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.3518122993
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.667101209
Short name T484
Test name
Test status
Simulation time 397861121 ps
CPU time 1.52 seconds
Started Jul 23 05:33:25 PM PDT 24
Finished Jul 23 05:33:29 PM PDT 24
Peak memory 193008 kb
Host smart-ad114f18-2df7-4be7-9b9b-5bdfcd05964d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667101209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_b
ash.667101209
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.3721880182
Short name T510
Test name
Test status
Simulation time 37269686 ps
CPU time 0.56 seconds
Started Jul 23 05:33:25 PM PDT 24
Finished Jul 23 05:33:28 PM PDT 24
Peak memory 182944 kb
Host smart-7ddb225c-cb9b-4713-87a1-1843ded797b2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721880182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.3721880182
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.2509346567
Short name T486
Test name
Test status
Simulation time 39350669 ps
CPU time 1.09 seconds
Started Jul 23 05:33:27 PM PDT 24
Finished Jul 23 05:33:30 PM PDT 24
Peak memory 197588 kb
Host smart-7439c78f-6776-4d36-8347-16d28f694bc7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509346567 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.2509346567
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.1916917794
Short name T482
Test name
Test status
Simulation time 38439992 ps
CPU time 0.63 seconds
Started Jul 23 05:33:26 PM PDT 24
Finished Jul 23 05:33:30 PM PDT 24
Peak memory 182960 kb
Host smart-1a0c2880-de73-4e70-ada7-2fe009b689f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916917794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.1916917794
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.732994181
Short name T568
Test name
Test status
Simulation time 25818954 ps
CPU time 0.57 seconds
Started Jul 23 05:33:26 PM PDT 24
Finished Jul 23 05:33:30 PM PDT 24
Peak memory 182732 kb
Host smart-50b85de1-ce82-47b5-ae1d-5cb2fc461a91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732994181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.732994181
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.2370100052
Short name T538
Test name
Test status
Simulation time 19949233 ps
CPU time 0.62 seconds
Started Jul 23 05:33:26 PM PDT 24
Finished Jul 23 05:33:30 PM PDT 24
Peak memory 191788 kb
Host smart-f61cda79-5084-4c92-99f4-6ff9c906708f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370100052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.2370100052
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.2776821413
Short name T489
Test name
Test status
Simulation time 148420930 ps
CPU time 1.55 seconds
Started Jul 23 05:33:18 PM PDT 24
Finished Jul 23 05:33:21 PM PDT 24
Peak memory 197512 kb
Host smart-2bf2905a-7eb6-4786-ba64-cafc3e5cc50a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776821413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.2776821413
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.4124351949
Short name T506
Test name
Test status
Simulation time 157899552 ps
CPU time 0.82 seconds
Started Jul 23 05:33:19 PM PDT 24
Finished Jul 23 05:33:23 PM PDT 24
Peak memory 183516 kb
Host smart-43e907a8-9383-4563-aa72-b369b97eaf66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124351949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.4124351949
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.988804095
Short name T477
Test name
Test status
Simulation time 16139438 ps
CPU time 0.69 seconds
Started Jul 23 05:33:48 PM PDT 24
Finished Jul 23 05:33:50 PM PDT 24
Peak memory 194200 kb
Host smart-c1bb1945-47c4-4621-bbc0-40b6ef0cad9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988804095 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.988804095
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.4144966766
Short name T60
Test name
Test status
Simulation time 15947391 ps
CPU time 0.59 seconds
Started Jul 23 05:33:48 PM PDT 24
Finished Jul 23 05:33:49 PM PDT 24
Peak memory 182988 kb
Host smart-a61620c8-e6b9-4ce4-beb6-a3b38b99179f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144966766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.4144966766
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.3419695773
Short name T521
Test name
Test status
Simulation time 24321163 ps
CPU time 0.59 seconds
Started Jul 23 05:33:49 PM PDT 24
Finished Jul 23 05:33:52 PM PDT 24
Peak memory 182756 kb
Host smart-5c78d5d8-404a-4a4a-8c25-c3287da28d55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419695773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.3419695773
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.4108062770
Short name T495
Test name
Test status
Simulation time 76311640 ps
CPU time 0.66 seconds
Started Jul 23 05:33:51 PM PDT 24
Finished Jul 23 05:33:53 PM PDT 24
Peak memory 192404 kb
Host smart-e3f0b51d-e3a9-4903-aa90-c3e72d03d0aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108062770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.4108062770
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1948981107
Short name T504
Test name
Test status
Simulation time 54159753 ps
CPU time 2.53 seconds
Started Jul 23 05:33:55 PM PDT 24
Finished Jul 23 05:33:58 PM PDT 24
Peak memory 197728 kb
Host smart-4765fdcc-bc57-4a56-803d-677071872a60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948981107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.1948981107
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1181825214
Short name T569
Test name
Test status
Simulation time 91425563 ps
CPU time 0.83 seconds
Started Jul 23 05:33:49 PM PDT 24
Finished Jul 23 05:33:52 PM PDT 24
Peak memory 183196 kb
Host smart-3315754a-4389-4157-8963-8863839b7982
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181825214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.1181825214
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.1721978875
Short name T483
Test name
Test status
Simulation time 51782156 ps
CPU time 0.67 seconds
Started Jul 23 05:33:50 PM PDT 24
Finished Jul 23 05:33:52 PM PDT 24
Peak memory 194508 kb
Host smart-7f05d200-cdcb-4c86-8078-e4e9eb5f94ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721978875 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.1721978875
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.1804478599
Short name T480
Test name
Test status
Simulation time 58424068 ps
CPU time 0.6 seconds
Started Jul 23 05:33:49 PM PDT 24
Finished Jul 23 05:33:52 PM PDT 24
Peak memory 182984 kb
Host smart-c9b03385-9696-4f10-813f-7ffe0eb1c229
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804478599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.1804478599
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.4249127045
Short name T519
Test name
Test status
Simulation time 22947285 ps
CPU time 0.52 seconds
Started Jul 23 05:33:49 PM PDT 24
Finished Jul 23 05:33:51 PM PDT 24
Peak memory 182336 kb
Host smart-7066dd23-741a-48da-92f2-1311623a8758
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249127045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.4249127045
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3896683882
Short name T570
Test name
Test status
Simulation time 111390435 ps
CPU time 0.65 seconds
Started Jul 23 05:33:52 PM PDT 24
Finished Jul 23 05:33:54 PM PDT 24
Peak memory 191980 kb
Host smart-c1586da2-8f78-4d61-8161-34577b8d8adc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896683882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.3896683882
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.1199354767
Short name T461
Test name
Test status
Simulation time 214874979 ps
CPU time 3.08 seconds
Started Jul 23 05:33:50 PM PDT 24
Finished Jul 23 05:33:55 PM PDT 24
Peak memory 197728 kb
Host smart-dfab2844-65b1-4a45-bf6a-e1e2c208ad04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199354767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.1199354767
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3199592192
Short name T84
Test name
Test status
Simulation time 613691457 ps
CPU time 1.13 seconds
Started Jul 23 05:33:51 PM PDT 24
Finished Jul 23 05:33:53 PM PDT 24
Peak memory 194340 kb
Host smart-c9e9849b-854c-44ab-9a0b-d26e6486bb48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199592192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.3199592192
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3473604626
Short name T511
Test name
Test status
Simulation time 68926058 ps
CPU time 0.86 seconds
Started Jul 23 05:33:47 PM PDT 24
Finished Jul 23 05:33:48 PM PDT 24
Peak memory 196696 kb
Host smart-9278f5c8-f453-42ae-ad96-2dd9a495bb44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473604626 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.3473604626
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.3491885203
Short name T515
Test name
Test status
Simulation time 63435395 ps
CPU time 0.6 seconds
Started Jul 23 05:33:51 PM PDT 24
Finished Jul 23 05:33:53 PM PDT 24
Peak memory 182960 kb
Host smart-2bb1e5bd-fc60-482b-9ad5-947c9959e481
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491885203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.3491885203
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.2816047429
Short name T535
Test name
Test status
Simulation time 24935006 ps
CPU time 0.56 seconds
Started Jul 23 05:33:51 PM PDT 24
Finished Jul 23 05:33:53 PM PDT 24
Peak memory 182512 kb
Host smart-20e1bc92-3a7c-4df6-ae3c-3d5997c6588c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816047429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.2816047429
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.11497010
Short name T533
Test name
Test status
Simulation time 41210552 ps
CPU time 0.63 seconds
Started Jul 23 05:33:51 PM PDT 24
Finished Jul 23 05:33:53 PM PDT 24
Peak memory 192300 kb
Host smart-ba22697b-fbf6-4865-9ed8-813ebd6a91cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11497010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_tim
er_same_csr_outstanding.11497010
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.2844680550
Short name T554
Test name
Test status
Simulation time 520659957 ps
CPU time 2.34 seconds
Started Jul 23 05:33:50 PM PDT 24
Finished Jul 23 05:33:54 PM PDT 24
Peak memory 197712 kb
Host smart-36b277fd-f444-4db6-a2e5-61c85b23c7c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844680550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.2844680550
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2959483725
Short name T556
Test name
Test status
Simulation time 26494464 ps
CPU time 1.13 seconds
Started Jul 23 05:33:48 PM PDT 24
Finished Jul 23 05:33:50 PM PDT 24
Peak memory 197740 kb
Host smart-8575421b-8c25-4ba4-b264-b1fa910bdf2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959483725 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.2959483725
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.1425868496
Short name T578
Test name
Test status
Simulation time 17977476 ps
CPU time 0.59 seconds
Started Jul 23 05:33:47 PM PDT 24
Finished Jul 23 05:33:49 PM PDT 24
Peak memory 182892 kb
Host smart-c3ace329-3a32-43dd-81f8-40f458e80181
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425868496 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.1425868496
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.2950533287
Short name T472
Test name
Test status
Simulation time 43483749 ps
CPU time 0.54 seconds
Started Jul 23 05:33:50 PM PDT 24
Finished Jul 23 05:33:52 PM PDT 24
Peak memory 182844 kb
Host smart-92f1ecb3-9bd7-4f8c-adf6-45c7fe760cc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950533287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.2950533287
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.2435008480
Short name T78
Test name
Test status
Simulation time 14936943 ps
CPU time 0.63 seconds
Started Jul 23 05:33:50 PM PDT 24
Finished Jul 23 05:33:53 PM PDT 24
Peak memory 193288 kb
Host smart-5dd0147d-e888-4190-8ad1-19b030ca8597
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435008480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.2435008480
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.3757242575
Short name T466
Test name
Test status
Simulation time 111316467 ps
CPU time 2.29 seconds
Started Jul 23 05:33:50 PM PDT 24
Finished Jul 23 05:33:54 PM PDT 24
Peak memory 197736 kb
Host smart-408153e1-123d-4dac-9527-f4e53fb12555
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757242575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.3757242575
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.2838038750
Short name T47
Test name
Test status
Simulation time 547289178 ps
CPU time 1.09 seconds
Started Jul 23 05:33:50 PM PDT 24
Finished Jul 23 05:33:53 PM PDT 24
Peak memory 193896 kb
Host smart-29d5005c-1d24-4e90-8957-7ef13088189a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838038750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.2838038750
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.1409237743
Short name T540
Test name
Test status
Simulation time 125080828 ps
CPU time 0.71 seconds
Started Jul 23 05:33:58 PM PDT 24
Finished Jul 23 05:34:01 PM PDT 24
Peak memory 195084 kb
Host smart-1b66e7a0-70c2-445a-81a8-3ce28f15c65d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409237743 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.1409237743
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.2696137720
Short name T468
Test name
Test status
Simulation time 15125189 ps
CPU time 0.59 seconds
Started Jul 23 05:33:57 PM PDT 24
Finished Jul 23 05:33:58 PM PDT 24
Peak memory 182948 kb
Host smart-db4b1e90-1ed9-4c31-a8f2-4be2c622d69c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696137720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.2696137720
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.2546624490
Short name T551
Test name
Test status
Simulation time 117930675 ps
CPU time 0.56 seconds
Started Jul 23 05:33:52 PM PDT 24
Finished Jul 23 05:33:54 PM PDT 24
Peak memory 182924 kb
Host smart-c2373fe8-a28b-491b-be01-319cc8afe286
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546624490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.2546624490
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.2185316668
Short name T73
Test name
Test status
Simulation time 12851558 ps
CPU time 0.63 seconds
Started Jul 23 05:34:01 PM PDT 24
Finished Jul 23 05:34:03 PM PDT 24
Peak memory 192232 kb
Host smart-64f107f8-ed22-4d85-8298-001f22eb9288
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185316668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.2185316668
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.910338412
Short name T494
Test name
Test status
Simulation time 161309816 ps
CPU time 2.28 seconds
Started Jul 23 05:33:48 PM PDT 24
Finished Jul 23 05:33:51 PM PDT 24
Peak memory 197736 kb
Host smart-d9276550-d994-4d15-aa8f-e5b9ae091f2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910338412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.910338412
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.702280304
Short name T574
Test name
Test status
Simulation time 120586962 ps
CPU time 0.91 seconds
Started Jul 23 05:33:51 PM PDT 24
Finished Jul 23 05:33:53 PM PDT 24
Peak memory 193844 kb
Host smart-180db57b-390f-4c09-b0e0-84cfee410747
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702280304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_in
tg_err.702280304
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1228345448
Short name T517
Test name
Test status
Simulation time 25232786 ps
CPU time 0.83 seconds
Started Jul 23 05:33:57 PM PDT 24
Finished Jul 23 05:33:58 PM PDT 24
Peak memory 194956 kb
Host smart-ce3f8223-8c7a-436c-a6e9-db777766ce0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228345448 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.1228345448
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.1274449771
Short name T55
Test name
Test status
Simulation time 19132127 ps
CPU time 0.55 seconds
Started Jul 23 05:33:57 PM PDT 24
Finished Jul 23 05:33:58 PM PDT 24
Peak memory 182840 kb
Host smart-78a976ec-759a-4402-868f-ae7441a116ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274449771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.1274449771
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.587130842
Short name T512
Test name
Test status
Simulation time 13378346 ps
CPU time 0.57 seconds
Started Jul 23 05:33:57 PM PDT 24
Finished Jul 23 05:34:00 PM PDT 24
Peak memory 182864 kb
Host smart-7fc5bb6c-66c1-440c-b6dd-2351afd21da0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587130842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.587130842
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.3259266551
Short name T502
Test name
Test status
Simulation time 20783402 ps
CPU time 0.64 seconds
Started Jul 23 05:33:58 PM PDT 24
Finished Jul 23 05:34:01 PM PDT 24
Peak memory 191924 kb
Host smart-aa9c1b5d-6e05-493e-bcea-462295843c2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259266551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.3259266551
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.2068640563
Short name T563
Test name
Test status
Simulation time 36992568 ps
CPU time 1.01 seconds
Started Jul 23 05:33:57 PM PDT 24
Finished Jul 23 05:34:00 PM PDT 24
Peak memory 194272 kb
Host smart-c6a7e70a-7655-4f24-b63a-1ba9612d078a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068640563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.2068640563
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.520676042
Short name T503
Test name
Test status
Simulation time 69937275 ps
CPU time 0.97 seconds
Started Jul 23 05:33:58 PM PDT 24
Finished Jul 23 05:34:01 PM PDT 24
Peak memory 197168 kb
Host smart-68807cdd-5c0f-4e87-895a-ba5898bcc17b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520676042 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.520676042
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.3052951930
Short name T42
Test name
Test status
Simulation time 42919052 ps
CPU time 0.62 seconds
Started Jul 23 05:34:00 PM PDT 24
Finished Jul 23 05:34:02 PM PDT 24
Peak memory 183004 kb
Host smart-589283ee-84f3-432d-8690-08d9898d8a31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052951930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.3052951930
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.1587121941
Short name T529
Test name
Test status
Simulation time 11474995 ps
CPU time 0.55 seconds
Started Jul 23 05:33:58 PM PDT 24
Finished Jul 23 05:34:01 PM PDT 24
Peak memory 182920 kb
Host smart-e16ccd1b-84a9-407c-9595-1c1eaf592ad0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587121941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.1587121941
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.700852686
Short name T576
Test name
Test status
Simulation time 43754132 ps
CPU time 0.68 seconds
Started Jul 23 05:33:57 PM PDT 24
Finished Jul 23 05:34:00 PM PDT 24
Peak memory 191844 kb
Host smart-f6281f0f-ef7f-4ecc-a34b-272ffd52a521
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700852686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_ti
mer_same_csr_outstanding.700852686
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3894074062
Short name T524
Test name
Test status
Simulation time 28134122 ps
CPU time 1.36 seconds
Started Jul 23 05:33:57 PM PDT 24
Finished Jul 23 05:34:01 PM PDT 24
Peak memory 197728 kb
Host smart-d34ef04e-3da0-4d1a-912a-0cbbeac40809
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894074062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.3894074062
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2376336082
Short name T44
Test name
Test status
Simulation time 49841594 ps
CPU time 0.84 seconds
Started Jul 23 05:33:58 PM PDT 24
Finished Jul 23 05:34:01 PM PDT 24
Peak memory 194188 kb
Host smart-e8c56fb6-19c1-4dba-a898-c2e146b03fc5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376336082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.2376336082
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.120788057
Short name T564
Test name
Test status
Simulation time 81989985 ps
CPU time 0.94 seconds
Started Jul 23 05:33:58 PM PDT 24
Finished Jul 23 05:34:01 PM PDT 24
Peak memory 197080 kb
Host smart-b3faff6b-2af3-46d9-b4d0-d7fd4a768f97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120788057 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.120788057
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.3056946741
Short name T59
Test name
Test status
Simulation time 15490895 ps
CPU time 0.65 seconds
Started Jul 23 05:33:57 PM PDT 24
Finished Jul 23 05:34:00 PM PDT 24
Peak memory 182968 kb
Host smart-7d052755-4449-4292-bf8c-37ff8104ffd5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056946741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.3056946741
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.4081073008
Short name T571
Test name
Test status
Simulation time 31576880 ps
CPU time 0.55 seconds
Started Jul 23 05:33:57 PM PDT 24
Finished Jul 23 05:34:00 PM PDT 24
Peak memory 182876 kb
Host smart-1c233ca9-1e45-45de-a7a5-a8e7e7585a30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081073008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.4081073008
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.1377644775
Short name T534
Test name
Test status
Simulation time 40584298 ps
CPU time 0.64 seconds
Started Jul 23 05:33:58 PM PDT 24
Finished Jul 23 05:34:01 PM PDT 24
Peak memory 191684 kb
Host smart-493bbd01-1861-4acc-b4ff-8cf6d82fae28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377644775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.1377644775
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.1719317297
Short name T469
Test name
Test status
Simulation time 414922221 ps
CPU time 2.06 seconds
Started Jul 23 05:33:58 PM PDT 24
Finished Jul 23 05:34:02 PM PDT 24
Peak memory 197576 kb
Host smart-d5316379-be09-49b8-b2b1-f8b8943bead8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719317297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.1719317297
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.1172838917
Short name T28
Test name
Test status
Simulation time 81451121 ps
CPU time 1.12 seconds
Started Jul 23 05:33:58 PM PDT 24
Finished Jul 23 05:34:01 PM PDT 24
Peak memory 195020 kb
Host smart-17632503-ac86-4bde-a851-aff36c49ac13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172838917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.1172838917
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3447349480
Short name T43
Test name
Test status
Simulation time 54712531 ps
CPU time 0.75 seconds
Started Jul 23 05:33:57 PM PDT 24
Finished Jul 23 05:34:00 PM PDT 24
Peak memory 195392 kb
Host smart-e06946c7-9fa0-43c8-b979-1c880034f9cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447349480 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.3447349480
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.230197770
Short name T61
Test name
Test status
Simulation time 45926674 ps
CPU time 0.55 seconds
Started Jul 23 05:33:57 PM PDT 24
Finished Jul 23 05:34:00 PM PDT 24
Peak memory 182948 kb
Host smart-9b82aec6-c0d5-4b32-b89a-b946970f24a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230197770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.230197770
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.1182654235
Short name T496
Test name
Test status
Simulation time 24725677 ps
CPU time 0.52 seconds
Started Jul 23 05:33:56 PM PDT 24
Finished Jul 23 05:33:57 PM PDT 24
Peak memory 182328 kb
Host smart-66359d76-36f3-40b4-a974-58b9cc699c88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182654235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.1182654235
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1752655738
Short name T74
Test name
Test status
Simulation time 12013414 ps
CPU time 0.61 seconds
Started Jul 23 05:33:57 PM PDT 24
Finished Jul 23 05:33:59 PM PDT 24
Peak memory 192272 kb
Host smart-5eafb286-af7c-4ef7-90bb-79ac703893ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752655738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.1752655738
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.161209818
Short name T491
Test name
Test status
Simulation time 134548788 ps
CPU time 1.59 seconds
Started Jul 23 05:33:56 PM PDT 24
Finished Jul 23 05:33:59 PM PDT 24
Peak memory 197716 kb
Host smart-a411c742-6484-497e-b71f-f5d1a3115cdd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161209818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.161209818
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.2037759252
Short name T26
Test name
Test status
Simulation time 301514973 ps
CPU time 1.12 seconds
Started Jul 23 05:33:58 PM PDT 24
Finished Jul 23 05:34:02 PM PDT 24
Peak memory 183448 kb
Host smart-1baaa227-0e41-4b9d-9260-fc7bad2ae825
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037759252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.2037759252
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.4286534988
Short name T488
Test name
Test status
Simulation time 317629250 ps
CPU time 1.59 seconds
Started Jul 23 05:34:05 PM PDT 24
Finished Jul 23 05:34:07 PM PDT 24
Peak memory 197704 kb
Host smart-4ef14dea-61a8-4002-8135-a65ae8afea31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286534988 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.4286534988
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.2728493944
Short name T57
Test name
Test status
Simulation time 21259693 ps
CPU time 0.54 seconds
Started Jul 23 05:33:58 PM PDT 24
Finished Jul 23 05:34:01 PM PDT 24
Peak memory 183004 kb
Host smart-999aebfc-adde-4f9c-93a1-b5c6ba506d0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728493944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.2728493944
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.4283290344
Short name T478
Test name
Test status
Simulation time 32861060 ps
CPU time 0.53 seconds
Started Jul 23 05:33:57 PM PDT 24
Finished Jul 23 05:33:59 PM PDT 24
Peak memory 182240 kb
Host smart-bf19a456-c9af-479f-a788-3beab9431af5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283290344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.4283290344
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.604867320
Short name T565
Test name
Test status
Simulation time 93405348 ps
CPU time 0.67 seconds
Started Jul 23 05:34:06 PM PDT 24
Finished Jul 23 05:34:09 PM PDT 24
Peak memory 191920 kb
Host smart-6cc6d443-c52e-4f0b-949d-bec03b23aa8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604867320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_ti
mer_same_csr_outstanding.604867320
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.1226601299
Short name T558
Test name
Test status
Simulation time 41423209 ps
CPU time 1.98 seconds
Started Jul 23 05:33:58 PM PDT 24
Finished Jul 23 05:34:02 PM PDT 24
Peak memory 197692 kb
Host smart-b9c58ea2-9c2d-4404-9461-3eef71516e88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226601299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.1226601299
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1959545092
Short name T552
Test name
Test status
Simulation time 197447779 ps
CPU time 1.31 seconds
Started Jul 23 05:33:57 PM PDT 24
Finished Jul 23 05:34:00 PM PDT 24
Peak memory 195572 kb
Host smart-33cb5871-b4da-4d19-ae93-18b7878921c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959545092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.1959545092
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.3046465237
Short name T56
Test name
Test status
Simulation time 25947655 ps
CPU time 0.7 seconds
Started Jul 23 05:33:27 PM PDT 24
Finished Jul 23 05:33:30 PM PDT 24
Peak memory 192520 kb
Host smart-5f431742-e979-4282-8ca7-2367398f8540
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046465237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.3046465237
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1411628220
Short name T29
Test name
Test status
Simulation time 284990154 ps
CPU time 3.49 seconds
Started Jul 23 05:33:26 PM PDT 24
Finished Jul 23 05:33:32 PM PDT 24
Peak memory 192620 kb
Host smart-934a46bd-26a6-49c4-80ff-0ec962fa390e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411628220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.1411628220
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.2281878022
Short name T65
Test name
Test status
Simulation time 36541571 ps
CPU time 0.6 seconds
Started Jul 23 05:33:29 PM PDT 24
Finished Jul 23 05:33:31 PM PDT 24
Peak memory 182832 kb
Host smart-d5263e16-c935-45cc-9b44-aa92d9dafe0f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281878022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.2281878022
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.199898598
Short name T561
Test name
Test status
Simulation time 59754426 ps
CPU time 0.69 seconds
Started Jul 23 05:33:26 PM PDT 24
Finished Jul 23 05:33:29 PM PDT 24
Peak memory 194100 kb
Host smart-a5853fd7-fcae-4c08-a665-e5d9dde37001
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199898598 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.199898598
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.2885800184
Short name T536
Test name
Test status
Simulation time 20603517 ps
CPU time 0.54 seconds
Started Jul 23 05:33:27 PM PDT 24
Finished Jul 23 05:33:30 PM PDT 24
Peak memory 182760 kb
Host smart-51e035bc-20dd-4d4b-aa86-81ab248c127b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885800184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.2885800184
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.1976994079
Short name T457
Test name
Test status
Simulation time 18596000 ps
CPU time 0.57 seconds
Started Jul 23 05:33:28 PM PDT 24
Finished Jul 23 05:33:31 PM PDT 24
Peak memory 182720 kb
Host smart-b2ffb0fd-6115-4e0c-bcc4-ec4486e3751a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976994079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.1976994079
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.4184685575
Short name T577
Test name
Test status
Simulation time 20387558 ps
CPU time 0.63 seconds
Started Jul 23 05:33:26 PM PDT 24
Finished Jul 23 05:33:29 PM PDT 24
Peak memory 191804 kb
Host smart-1c24fda5-8530-4a40-b4c4-fc0341b15631
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184685575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.4184685575
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.621285451
Short name T527
Test name
Test status
Simulation time 192376558 ps
CPU time 3.09 seconds
Started Jul 23 05:33:26 PM PDT 24
Finished Jul 23 05:33:31 PM PDT 24
Peak memory 197748 kb
Host smart-9091cc94-93a6-472f-b495-99f36655a04e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621285451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.621285451
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.3731895988
Short name T83
Test name
Test status
Simulation time 50946702 ps
CPU time 0.84 seconds
Started Jul 23 05:33:31 PM PDT 24
Finished Jul 23 05:33:33 PM PDT 24
Peak memory 194048 kb
Host smart-bcd1eb6d-d2de-4abb-8f89-d8e0e653cde2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731895988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.3731895988
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.3056458521
Short name T462
Test name
Test status
Simulation time 18078471 ps
CPU time 0.59 seconds
Started Jul 23 05:34:07 PM PDT 24
Finished Jul 23 05:34:09 PM PDT 24
Peak memory 182840 kb
Host smart-3306f6b8-41d6-4634-b5e2-329184cc0f1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056458521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.3056458521
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.2917322498
Short name T465
Test name
Test status
Simulation time 24849254 ps
CPU time 0.54 seconds
Started Jul 23 05:34:06 PM PDT 24
Finished Jul 23 05:34:08 PM PDT 24
Peak memory 182312 kb
Host smart-0db9b38e-7f6a-4f3d-9efe-d2cfdab0dc6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917322498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.2917322498
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.2898731698
Short name T473
Test name
Test status
Simulation time 30075337 ps
CPU time 0.53 seconds
Started Jul 23 05:34:09 PM PDT 24
Finished Jul 23 05:34:11 PM PDT 24
Peak memory 182272 kb
Host smart-b5842fb8-c228-4afd-a7c8-2f32d13324b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898731698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.2898731698
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.222614072
Short name T509
Test name
Test status
Simulation time 28814871 ps
CPU time 0.56 seconds
Started Jul 23 05:34:07 PM PDT 24
Finished Jul 23 05:34:09 PM PDT 24
Peak memory 182336 kb
Host smart-ea3968b2-e0ef-44d5-995b-99ccf5b63fbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222614072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.222614072
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2241681214
Short name T567
Test name
Test status
Simulation time 11092904 ps
CPU time 0.55 seconds
Started Jul 23 05:34:07 PM PDT 24
Finished Jul 23 05:34:09 PM PDT 24
Peak memory 182892 kb
Host smart-f7075b1d-cd61-4b4c-9f69-0ecfd4e5080c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241681214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.2241681214
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.2614578919
Short name T475
Test name
Test status
Simulation time 15573861 ps
CPU time 0.56 seconds
Started Jul 23 05:34:07 PM PDT 24
Finished Jul 23 05:34:10 PM PDT 24
Peak memory 182796 kb
Host smart-5f25f5f1-b495-416a-b0e3-a4d9de79fe14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614578919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.2614578919
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.2408885809
Short name T464
Test name
Test status
Simulation time 53728882 ps
CPU time 0.56 seconds
Started Jul 23 05:34:07 PM PDT 24
Finished Jul 23 05:34:10 PM PDT 24
Peak memory 182852 kb
Host smart-0eaeffa3-e91a-4c72-a5ca-6f1c3796dca1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408885809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.2408885809
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.4154267391
Short name T499
Test name
Test status
Simulation time 51042072 ps
CPU time 0.54 seconds
Started Jul 23 05:34:02 PM PDT 24
Finished Jul 23 05:34:03 PM PDT 24
Peak memory 182344 kb
Host smart-f8614996-2472-4e89-9388-c5566fc3ed4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154267391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.4154267391
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1122388258
Short name T544
Test name
Test status
Simulation time 44553670 ps
CPU time 0.53 seconds
Started Jul 23 05:34:05 PM PDT 24
Finished Jul 23 05:34:07 PM PDT 24
Peak memory 182924 kb
Host smart-aa866419-7d8d-4969-9a97-668259f09cae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122388258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.1122388258
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.87072188
Short name T455
Test name
Test status
Simulation time 29908150 ps
CPU time 0.57 seconds
Started Jul 23 05:34:06 PM PDT 24
Finished Jul 23 05:34:07 PM PDT 24
Peak memory 182724 kb
Host smart-f68e387a-df75-49a5-81f9-d0034b05bacf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87072188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.87072188
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.1251076561
Short name T70
Test name
Test status
Simulation time 63253434 ps
CPU time 0.68 seconds
Started Jul 23 05:33:24 PM PDT 24
Finished Jul 23 05:33:25 PM PDT 24
Peak memory 192144 kb
Host smart-3d00e0bf-f061-44c3-b13b-f8b5101d4dd1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251076561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.1251076561
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.1233377418
Short name T557
Test name
Test status
Simulation time 3057889901 ps
CPU time 3.54 seconds
Started Jul 23 05:33:26 PM PDT 24
Finished Jul 23 05:33:32 PM PDT 24
Peak memory 191304 kb
Host smart-464184a0-d19c-4d0b-8b42-759f10d23e67
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233377418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.1233377418
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3375442483
Short name T71
Test name
Test status
Simulation time 46043637 ps
CPU time 0.57 seconds
Started Jul 23 05:33:24 PM PDT 24
Finished Jul 23 05:33:25 PM PDT 24
Peak memory 182956 kb
Host smart-b01a1d2a-8428-4b34-9d4b-dcafdf8c6816
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375442483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.3375442483
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.1603765952
Short name T555
Test name
Test status
Simulation time 100456749 ps
CPU time 1.3 seconds
Started Jul 23 05:33:27 PM PDT 24
Finished Jul 23 05:33:31 PM PDT 24
Peak memory 197756 kb
Host smart-d942599b-822d-4a8c-b7fd-e5cdd1e61819
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603765952 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.1603765952
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.2773867321
Short name T492
Test name
Test status
Simulation time 17666800 ps
CPU time 0.55 seconds
Started Jul 23 05:33:27 PM PDT 24
Finished Jul 23 05:33:30 PM PDT 24
Peak memory 182728 kb
Host smart-fea39412-bba4-45a9-a0cc-0df57dee0faa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773867321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.2773867321
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.3090270172
Short name T532
Test name
Test status
Simulation time 13984326 ps
CPU time 0.55 seconds
Started Jul 23 05:33:27 PM PDT 24
Finished Jul 23 05:33:30 PM PDT 24
Peak memory 182272 kb
Host smart-ac0921e9-d6c4-4d3f-87ba-f4a26fccf9bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090270172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.3090270172
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.1693532734
Short name T72
Test name
Test status
Simulation time 69300414 ps
CPU time 0.83 seconds
Started Jul 23 05:33:26 PM PDT 24
Finished Jul 23 05:33:29 PM PDT 24
Peak memory 193620 kb
Host smart-a3f6bec5-97b3-4fd9-b5dd-b15aee77f093
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693532734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.1693532734
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3730403774
Short name T545
Test name
Test status
Simulation time 511088668 ps
CPU time 1.68 seconds
Started Jul 23 05:33:24 PM PDT 24
Finished Jul 23 05:33:26 PM PDT 24
Peak memory 197684 kb
Host smart-e73325d8-ef60-4bec-92d8-9097cf3003a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730403774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.3730403774
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.2978069375
Short name T541
Test name
Test status
Simulation time 50127531 ps
CPU time 0.81 seconds
Started Jul 23 05:33:24 PM PDT 24
Finished Jul 23 05:33:27 PM PDT 24
Peak memory 193776 kb
Host smart-16b5d769-5c5e-4485-8326-44c66e97e478
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978069375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.2978069375
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.2071545445
Short name T471
Test name
Test status
Simulation time 14628177 ps
CPU time 0.53 seconds
Started Jul 23 05:34:05 PM PDT 24
Finished Jul 23 05:34:06 PM PDT 24
Peak memory 182264 kb
Host smart-4f3b3d47-5d22-4285-ad26-573b2c0f5603
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071545445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.2071545445
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.2698772521
Short name T530
Test name
Test status
Simulation time 13891917 ps
CPU time 0.55 seconds
Started Jul 23 05:34:06 PM PDT 24
Finished Jul 23 05:34:08 PM PDT 24
Peak memory 182312 kb
Host smart-d44d9e38-38e1-41e6-b43b-0fdc56182c4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698772521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.2698772521
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.3251418435
Short name T459
Test name
Test status
Simulation time 15001201 ps
CPU time 0.56 seconds
Started Jul 23 05:34:06 PM PDT 24
Finished Jul 23 05:34:08 PM PDT 24
Peak memory 182716 kb
Host smart-3c1fd448-25e1-4c38-9cc4-f39c0f6603a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251418435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.3251418435
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.244753346
Short name T463
Test name
Test status
Simulation time 17295750 ps
CPU time 0.56 seconds
Started Jul 23 05:34:08 PM PDT 24
Finished Jul 23 05:34:10 PM PDT 24
Peak memory 182888 kb
Host smart-e3acf725-5aa9-40ff-9bc5-952585206d52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244753346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.244753346
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.3781221548
Short name T456
Test name
Test status
Simulation time 104905885 ps
CPU time 0.56 seconds
Started Jul 23 05:34:06 PM PDT 24
Finished Jul 23 05:34:08 PM PDT 24
Peak memory 182880 kb
Host smart-603ece69-1e62-4827-9de9-daa8bc4c03ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781221548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.3781221548
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.385889704
Short name T487
Test name
Test status
Simulation time 58244861 ps
CPU time 0.58 seconds
Started Jul 23 05:34:04 PM PDT 24
Finished Jul 23 05:34:05 PM PDT 24
Peak memory 182860 kb
Host smart-4a5d0222-442c-4ea7-b761-dc132707e9c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385889704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.385889704
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.939228113
Short name T501
Test name
Test status
Simulation time 17541341 ps
CPU time 0.54 seconds
Started Jul 23 05:34:08 PM PDT 24
Finished Jul 23 05:34:11 PM PDT 24
Peak memory 182840 kb
Host smart-8178a9f0-72f4-49d3-82a3-6713f6525b2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939228113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.939228113
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.2491824759
Short name T498
Test name
Test status
Simulation time 17971548 ps
CPU time 0.55 seconds
Started Jul 23 05:34:08 PM PDT 24
Finished Jul 23 05:34:11 PM PDT 24
Peak memory 182836 kb
Host smart-69890a14-00a2-427e-b93c-340ef0e3a09d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491824759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.2491824759
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.4077149463
Short name T573
Test name
Test status
Simulation time 38925484 ps
CPU time 0.54 seconds
Started Jul 23 05:34:06 PM PDT 24
Finished Jul 23 05:34:08 PM PDT 24
Peak memory 182864 kb
Host smart-ca20e37f-c66f-4b3b-a6f3-37da9d0cbd68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077149463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.4077149463
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.24992688
Short name T559
Test name
Test status
Simulation time 16037044 ps
CPU time 0.54 seconds
Started Jul 23 05:34:05 PM PDT 24
Finished Jul 23 05:34:07 PM PDT 24
Peak memory 182372 kb
Host smart-f7572ff7-c8ce-4636-b68c-da846852a7b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24992688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.24992688
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1864713022
Short name T490
Test name
Test status
Simulation time 26099476 ps
CPU time 0.72 seconds
Started Jul 23 05:33:31 PM PDT 24
Finished Jul 23 05:33:33 PM PDT 24
Peak memory 183000 kb
Host smart-8b01e547-b14c-4574-a5c9-ba30c54360b5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864713022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.1864713022
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.295012727
Short name T560
Test name
Test status
Simulation time 99549673 ps
CPU time 1.53 seconds
Started Jul 23 05:33:26 PM PDT 24
Finished Jul 23 05:33:30 PM PDT 24
Peak memory 191212 kb
Host smart-13262512-cfc6-4976-860b-5cf00266fd83
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295012727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_b
ash.295012727
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.456691701
Short name T470
Test name
Test status
Simulation time 41309237 ps
CPU time 0.54 seconds
Started Jul 23 05:33:27 PM PDT 24
Finished Jul 23 05:33:30 PM PDT 24
Peak memory 182532 kb
Host smart-228e6b70-03c3-492f-a37a-c010ca52daa0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456691701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_re
set.456691701
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.2567050004
Short name T48
Test name
Test status
Simulation time 103606391 ps
CPU time 0.71 seconds
Started Jul 23 05:33:25 PM PDT 24
Finished Jul 23 05:33:29 PM PDT 24
Peak memory 195724 kb
Host smart-1819322e-cbbc-4373-afd7-96c946a9108d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567050004 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.2567050004
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2667085093
Short name T58
Test name
Test status
Simulation time 55682538 ps
CPU time 0.6 seconds
Started Jul 23 05:33:25 PM PDT 24
Finished Jul 23 05:33:28 PM PDT 24
Peak memory 182848 kb
Host smart-052e8456-84e7-48b4-bddd-f0e78069f9a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667085093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.2667085093
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.184727525
Short name T542
Test name
Test status
Simulation time 89719165 ps
CPU time 0.56 seconds
Started Jul 23 05:33:31 PM PDT 24
Finished Jul 23 05:33:33 PM PDT 24
Peak memory 182936 kb
Host smart-c41e1b5e-2f21-4933-bee3-252e814e1b8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184727525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.184727525
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.2833834421
Short name T41
Test name
Test status
Simulation time 34023888 ps
CPU time 0.8 seconds
Started Jul 23 05:33:31 PM PDT 24
Finished Jul 23 05:33:33 PM PDT 24
Peak memory 194288 kb
Host smart-244be567-8e7c-4c09-acbd-ff830853231c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833834421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.2833834421
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1655984310
Short name T539
Test name
Test status
Simulation time 118909389 ps
CPU time 1.4 seconds
Started Jul 23 05:33:26 PM PDT 24
Finished Jul 23 05:33:30 PM PDT 24
Peak memory 197692 kb
Host smart-4441bc6f-496f-48cd-b7ea-fa91bef3234e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655984310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.1655984310
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.3165323606
Short name T514
Test name
Test status
Simulation time 386931391 ps
CPU time 1.1 seconds
Started Jul 23 05:33:27 PM PDT 24
Finished Jul 23 05:33:31 PM PDT 24
Peak memory 195184 kb
Host smart-20bdd2f7-da14-4de2-95fa-260c3c6f1c11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165323606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.3165323606
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.328452610
Short name T479
Test name
Test status
Simulation time 16693145 ps
CPU time 0.6 seconds
Started Jul 23 05:34:07 PM PDT 24
Finished Jul 23 05:34:09 PM PDT 24
Peak memory 182828 kb
Host smart-4da33759-ea02-4933-9f90-e234e8133c97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328452610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.328452610
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.1550478419
Short name T458
Test name
Test status
Simulation time 18278039 ps
CPU time 0.57 seconds
Started Jul 23 05:34:08 PM PDT 24
Finished Jul 23 05:34:10 PM PDT 24
Peak memory 182812 kb
Host smart-1c37186b-fcbc-465f-8b5d-a4b2d8f4a4d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550478419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.1550478419
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.2727017876
Short name T493
Test name
Test status
Simulation time 21935552 ps
CPU time 0.56 seconds
Started Jul 23 05:34:08 PM PDT 24
Finished Jul 23 05:34:11 PM PDT 24
Peak memory 182824 kb
Host smart-c8f7a5ca-9836-4811-9cc6-ec6f65cf1a5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727017876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.2727017876
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.2744479721
Short name T526
Test name
Test status
Simulation time 47202345 ps
CPU time 0.55 seconds
Started Jul 23 05:34:07 PM PDT 24
Finished Jul 23 05:34:09 PM PDT 24
Peak memory 182824 kb
Host smart-a5117ed8-b1c7-4ae4-8cc9-7c21faa334a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744479721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.2744479721
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.4068310146
Short name T522
Test name
Test status
Simulation time 37616034 ps
CPU time 0.58 seconds
Started Jul 23 05:34:10 PM PDT 24
Finished Jul 23 05:34:12 PM PDT 24
Peak memory 182812 kb
Host smart-8ce35d05-4b77-4c7e-aa90-4392ea341445
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068310146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.4068310146
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.252509297
Short name T579
Test name
Test status
Simulation time 91538764 ps
CPU time 0.55 seconds
Started Jul 23 05:34:08 PM PDT 24
Finished Jul 23 05:34:10 PM PDT 24
Peak memory 182872 kb
Host smart-3e15c7ca-f5ba-4262-a8aa-8dbff9cf0515
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252509297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.252509297
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.43207606
Short name T550
Test name
Test status
Simulation time 18214621 ps
CPU time 0.56 seconds
Started Jul 23 05:34:04 PM PDT 24
Finished Jul 23 05:34:05 PM PDT 24
Peak memory 182864 kb
Host smart-ff759ec8-161d-48f1-8019-c59b3d80da59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43207606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.43207606
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2604690669
Short name T548
Test name
Test status
Simulation time 19262236 ps
CPU time 0.64 seconds
Started Jul 23 05:34:04 PM PDT 24
Finished Jul 23 05:34:05 PM PDT 24
Peak memory 182896 kb
Host smart-f5a596b2-1208-45ad-9621-58f7fbe87d04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604690669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.2604690669
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.2958974561
Short name T516
Test name
Test status
Simulation time 50537996 ps
CPU time 0.57 seconds
Started Jul 23 05:34:08 PM PDT 24
Finished Jul 23 05:34:10 PM PDT 24
Peak memory 182824 kb
Host smart-76cd3632-26f0-483d-8c51-e7b28f15d232
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958974561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.2958974561
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.739304596
Short name T513
Test name
Test status
Simulation time 38970780 ps
CPU time 0.52 seconds
Started Jul 23 05:34:06 PM PDT 24
Finished Jul 23 05:34:07 PM PDT 24
Peak memory 182280 kb
Host smart-743bb025-f407-4b19-b258-91d2c46b2f2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739304596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.739304596
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.1693051231
Short name T528
Test name
Test status
Simulation time 33779888 ps
CPU time 0.96 seconds
Started Jul 23 05:33:32 PM PDT 24
Finished Jul 23 05:33:34 PM PDT 24
Peak memory 196928 kb
Host smart-6c359074-af1b-4f7c-922e-439a7ef0551b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693051231 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.1693051231
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.4200111090
Short name T69
Test name
Test status
Simulation time 24304952 ps
CPU time 0.58 seconds
Started Jul 23 05:33:33 PM PDT 24
Finished Jul 23 05:33:35 PM PDT 24
Peak memory 182992 kb
Host smart-31787845-ee65-4b46-ae51-4355324f6409
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200111090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.4200111090
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.836026556
Short name T566
Test name
Test status
Simulation time 11050657 ps
CPU time 0.52 seconds
Started Jul 23 05:33:32 PM PDT 24
Finished Jul 23 05:33:34 PM PDT 24
Peak memory 182844 kb
Host smart-d2f54cb4-a011-4684-9cd8-ec061c78f96a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836026556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.836026556
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.3844450627
Short name T537
Test name
Test status
Simulation time 126485669 ps
CPU time 0.78 seconds
Started Jul 23 05:33:32 PM PDT 24
Finished Jul 23 05:33:34 PM PDT 24
Peak memory 191892 kb
Host smart-49c82569-3f1e-4002-9d10-8c0b63df933e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844450627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.3844450627
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.3884731901
Short name T46
Test name
Test status
Simulation time 80636193 ps
CPU time 1.32 seconds
Started Jul 23 05:33:33 PM PDT 24
Finished Jul 23 05:33:35 PM PDT 24
Peak memory 197660 kb
Host smart-b3585d0f-d7f2-4d33-a5a6-ea8e927f04ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884731901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.3884731901
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.2669275673
Short name T82
Test name
Test status
Simulation time 302678828 ps
CPU time 1.08 seconds
Started Jul 23 05:33:33 PM PDT 24
Finished Jul 23 05:33:35 PM PDT 24
Peak memory 195172 kb
Host smart-fbd9046c-8b60-4b96-bada-0a8a3f1331f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669275673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.2669275673
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.1225758740
Short name T525
Test name
Test status
Simulation time 50136376 ps
CPU time 0.7 seconds
Started Jul 23 05:33:33 PM PDT 24
Finished Jul 23 05:33:35 PM PDT 24
Peak memory 195488 kb
Host smart-0d42d3ae-4b89-4067-93ed-0faa6bcd122f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225758740 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.1225758740
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1054173648
Short name T66
Test name
Test status
Simulation time 19661817 ps
CPU time 0.53 seconds
Started Jul 23 05:33:36 PM PDT 24
Finished Jul 23 05:33:37 PM PDT 24
Peak memory 182536 kb
Host smart-002d4624-fa36-4886-87d3-59f71bc1609e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054173648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.1054173648
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.2776018564
Short name T460
Test name
Test status
Simulation time 32083398 ps
CPU time 0.54 seconds
Started Jul 23 05:33:35 PM PDT 24
Finished Jul 23 05:33:36 PM PDT 24
Peak memory 182832 kb
Host smart-76f848c3-1313-4c9d-b0d5-9a1b0e3331d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776018564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.2776018564
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.3433884319
Short name T553
Test name
Test status
Simulation time 39157578 ps
CPU time 0.77 seconds
Started Jul 23 05:33:36 PM PDT 24
Finished Jul 23 05:33:38 PM PDT 24
Peak memory 193512 kb
Host smart-8f163647-67c8-4796-8b63-081c29cf1766
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433884319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.3433884319
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.2832660868
Short name T562
Test name
Test status
Simulation time 153709501 ps
CPU time 1.59 seconds
Started Jul 23 05:33:33 PM PDT 24
Finished Jul 23 05:33:35 PM PDT 24
Peak memory 197712 kb
Host smart-6569e51d-6fec-4684-94ff-1f583f50cb51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832660868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.2832660868
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.1929928843
Short name T81
Test name
Test status
Simulation time 198207674 ps
CPU time 1.38 seconds
Started Jul 23 05:33:33 PM PDT 24
Finished Jul 23 05:33:36 PM PDT 24
Peak memory 195656 kb
Host smart-f228bad1-9b08-4feb-a09a-ae048792fa61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929928843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.1929928843
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.1373626653
Short name T572
Test name
Test status
Simulation time 125019699 ps
CPU time 0.84 seconds
Started Jul 23 05:33:43 PM PDT 24
Finished Jul 23 05:33:44 PM PDT 24
Peak memory 196992 kb
Host smart-8378c676-87cc-4814-bafa-ab3691dced4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373626653 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.1373626653
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.3159904152
Short name T523
Test name
Test status
Simulation time 21509681 ps
CPU time 0.56 seconds
Started Jul 23 05:33:45 PM PDT 24
Finished Jul 23 05:33:46 PM PDT 24
Peak memory 183008 kb
Host smart-12ae0b3b-b23d-4b16-a76b-a2f996096ef0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159904152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.3159904152
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.2379157303
Short name T580
Test name
Test status
Simulation time 16769556 ps
CPU time 0.62 seconds
Started Jul 23 05:33:41 PM PDT 24
Finished Jul 23 05:33:42 PM PDT 24
Peak memory 182808 kb
Host smart-ad78c2c6-dc71-4526-8f13-d2d93c17f5f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379157303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.2379157303
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3615787124
Short name T75
Test name
Test status
Simulation time 45806086 ps
CPU time 0.66 seconds
Started Jul 23 05:33:40 PM PDT 24
Finished Jul 23 05:33:42 PM PDT 24
Peak memory 192652 kb
Host smart-5f847fdc-68ae-4069-a562-0574d1f31657
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615787124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.3615787124
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.2623741239
Short name T476
Test name
Test status
Simulation time 53892105 ps
CPU time 1.27 seconds
Started Jul 23 05:33:41 PM PDT 24
Finished Jul 23 05:33:43 PM PDT 24
Peak memory 197724 kb
Host smart-de12b665-46c2-48a8-92cd-d22dc1cf4294
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623741239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.2623741239
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.294908564
Short name T543
Test name
Test status
Simulation time 229605752 ps
CPU time 1.08 seconds
Started Jul 23 05:33:41 PM PDT 24
Finished Jul 23 05:33:42 PM PDT 24
Peak memory 195164 kb
Host smart-85dae643-c51e-4494-a9dd-c1b610c9e9ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294908564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_int
g_err.294908564
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.4278621541
Short name T500
Test name
Test status
Simulation time 23855802 ps
CPU time 0.72 seconds
Started Jul 23 05:33:45 PM PDT 24
Finished Jul 23 05:33:46 PM PDT 24
Peak memory 195100 kb
Host smart-78ee6f4c-500e-441e-99eb-2a855cd6a9c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278621541 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.4278621541
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.3324813896
Short name T508
Test name
Test status
Simulation time 46177189 ps
CPU time 0.58 seconds
Started Jul 23 05:33:41 PM PDT 24
Finished Jul 23 05:33:42 PM PDT 24
Peak memory 182924 kb
Host smart-278eec01-77bc-42d0-81b7-13f09917aac1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324813896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.3324813896
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.4013379490
Short name T547
Test name
Test status
Simulation time 26944883 ps
CPU time 0.54 seconds
Started Jul 23 05:33:42 PM PDT 24
Finished Jul 23 05:33:43 PM PDT 24
Peak memory 182312 kb
Host smart-3bb06e0a-648f-4798-988c-5c4449558971
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013379490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.4013379490
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.243913071
Short name T549
Test name
Test status
Simulation time 43439237 ps
CPU time 0.62 seconds
Started Jul 23 05:33:42 PM PDT 24
Finished Jul 23 05:33:43 PM PDT 24
Peak memory 192172 kb
Host smart-32617505-724f-45f8-97e9-7c5f5c50a68b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243913071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_tim
er_same_csr_outstanding.243913071
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.2892674255
Short name T518
Test name
Test status
Simulation time 27361812 ps
CPU time 1.39 seconds
Started Jul 23 05:33:47 PM PDT 24
Finished Jul 23 05:33:49 PM PDT 24
Peak memory 197612 kb
Host smart-231a8332-d81c-4314-9e8d-66c4d85717d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892674255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.2892674255
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.1159260232
Short name T80
Test name
Test status
Simulation time 290423482 ps
CPU time 1.16 seconds
Started Jul 23 05:33:44 PM PDT 24
Finished Jul 23 05:33:46 PM PDT 24
Peak memory 195136 kb
Host smart-78eeb639-c262-4a87-85f9-c3601135e521
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159260232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.1159260232
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.2475883666
Short name T520
Test name
Test status
Simulation time 38901953 ps
CPU time 0.63 seconds
Started Jul 23 05:33:52 PM PDT 24
Finished Jul 23 05:33:54 PM PDT 24
Peak memory 193644 kb
Host smart-39bba478-496d-4bdc-8e9c-4d7e8ca9cf60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475883666 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.2475883666
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.945958718
Short name T68
Test name
Test status
Simulation time 36904955 ps
CPU time 0.55 seconds
Started Jul 23 05:33:49 PM PDT 24
Finished Jul 23 05:33:51 PM PDT 24
Peak memory 182948 kb
Host smart-42d29640-361b-418f-848a-c889f5f3d0b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945958718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.945958718
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.1036543612
Short name T531
Test name
Test status
Simulation time 27096571 ps
CPU time 0.56 seconds
Started Jul 23 05:33:49 PM PDT 24
Finished Jul 23 05:33:51 PM PDT 24
Peak memory 182396 kb
Host smart-fa58f55f-1096-41ec-9eb0-8c75a604b46c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036543612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.1036543612
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.3369311137
Short name T77
Test name
Test status
Simulation time 272079356 ps
CPU time 0.8 seconds
Started Jul 23 05:33:50 PM PDT 24
Finished Jul 23 05:33:53 PM PDT 24
Peak memory 193808 kb
Host smart-235edf5f-fdff-4433-89ed-73347e1db96c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369311137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.3369311137
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.4099118415
Short name T497
Test name
Test status
Simulation time 222756755 ps
CPU time 1.44 seconds
Started Jul 23 05:33:42 PM PDT 24
Finished Jul 23 05:33:45 PM PDT 24
Peak memory 197584 kb
Host smart-531cd2be-a426-4514-bd52-a3662cdba6cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099118415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.4099118415
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.1885782460
Short name T546
Test name
Test status
Simulation time 298773642 ps
CPU time 1.09 seconds
Started Jul 23 05:33:43 PM PDT 24
Finished Jul 23 05:33:45 PM PDT 24
Peak memory 183436 kb
Host smart-1f6c8f8a-8a9c-4a33-8bfc-eb2135e887c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885782460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.1885782460
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_random.3226749176
Short name T39
Test name
Test status
Simulation time 69979716453 ps
CPU time 73.33 seconds
Started Jul 23 05:34:08 PM PDT 24
Finished Jul 23 05:35:23 PM PDT 24
Peak memory 183600 kb
Host smart-140d2c4e-cfb6-414c-9545-a299695f72e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226749176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.3226749176
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.1184131005
Short name T205
Test name
Test status
Simulation time 121848978406 ps
CPU time 84.81 seconds
Started Jul 23 05:34:09 PM PDT 24
Finished Jul 23 05:35:35 PM PDT 24
Peak memory 191784 kb
Host smart-5cda48fa-fb9a-4f4f-a841-1e491ad3859c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184131005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.1184131005
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.282771814
Short name T295
Test name
Test status
Simulation time 156269777984 ps
CPU time 235.51 seconds
Started Jul 23 05:34:15 PM PDT 24
Finished Jul 23 05:38:13 PM PDT 24
Peak memory 183532 kb
Host smart-15f5d01a-55cc-498b-a3ea-a827637620b3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282771814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.rv_timer_cfg_update_on_fly.282771814
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.2506946664
Short name T11
Test name
Test status
Simulation time 43750727780 ps
CPU time 170.21 seconds
Started Jul 23 05:34:16 PM PDT 24
Finished Jul 23 05:37:08 PM PDT 24
Peak memory 191788 kb
Host smart-5725f1a1-fbf3-4cfb-a3d7-a7b0f530f4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506946664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.2506946664
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.3360992486
Short name T18
Test name
Test status
Simulation time 229847919 ps
CPU time 0.84 seconds
Started Jul 23 05:34:19 PM PDT 24
Finished Jul 23 05:34:20 PM PDT 24
Peak memory 213928 kb
Host smart-d9caa87e-0509-4924-a28d-2af31a0c0c46
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360992486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.3360992486
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.3408297897
Short name T308
Test name
Test status
Simulation time 315524003557 ps
CPU time 302.54 seconds
Started Jul 23 05:34:15 PM PDT 24
Finished Jul 23 05:39:19 PM PDT 24
Peak memory 183536 kb
Host smart-fd624a86-f2c7-44ec-a76b-57fc8d4d58ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408297897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
3408297897
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.1765388966
Short name T408
Test name
Test status
Simulation time 122476504493 ps
CPU time 85.87 seconds
Started Jul 23 05:34:23 PM PDT 24
Finished Jul 23 05:35:50 PM PDT 24
Peak memory 183608 kb
Host smart-05cb381f-f2d5-4739-945e-22cffdfea608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765388966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.1765388966
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.4034634253
Short name T121
Test name
Test status
Simulation time 598192601651 ps
CPU time 958.46 seconds
Started Jul 23 05:34:24 PM PDT 24
Finished Jul 23 05:50:23 PM PDT 24
Peak memory 191640 kb
Host smart-5e4283ed-3dd7-49fd-9e5d-0610498f20b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034634253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.4034634253
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.1114741301
Short name T454
Test name
Test status
Simulation time 38582991 ps
CPU time 0.53 seconds
Started Jul 23 05:34:25 PM PDT 24
Finished Jul 23 05:34:26 PM PDT 24
Peak memory 183316 kb
Host smart-79f7a314-7702-4071-8d86-fd0dcbcc0f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114741301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.1114741301
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/102.rv_timer_random.2147673814
Short name T184
Test name
Test status
Simulation time 293311287613 ps
CPU time 184.63 seconds
Started Jul 23 05:36:59 PM PDT 24
Finished Jul 23 05:40:04 PM PDT 24
Peak memory 195168 kb
Host smart-5d9dc891-a823-4f51-a457-501b5dbdcca0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147673814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.2147673814
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.3455833985
Short name T335
Test name
Test status
Simulation time 408185806011 ps
CPU time 403.58 seconds
Started Jul 23 05:37:01 PM PDT 24
Finished Jul 23 05:43:46 PM PDT 24
Peak memory 191732 kb
Host smart-a0eca016-b245-421e-95d0-af286459b829
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455833985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.3455833985
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.1360588845
Short name T138
Test name
Test status
Simulation time 554174386971 ps
CPU time 333.86 seconds
Started Jul 23 05:37:11 PM PDT 24
Finished Jul 23 05:42:45 PM PDT 24
Peak memory 191744 kb
Host smart-e9e6c258-b4fb-4d80-a62a-c296ec56e9ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360588845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.1360588845
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.3490013453
Short name T235
Test name
Test status
Simulation time 154876968708 ps
CPU time 581.87 seconds
Started Jul 23 05:37:10 PM PDT 24
Finished Jul 23 05:46:52 PM PDT 24
Peak memory 191704 kb
Host smart-66cad8bb-5f70-4214-8a29-2c75e3baa3ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490013453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.3490013453
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.2360595941
Short name T430
Test name
Test status
Simulation time 140085125125 ps
CPU time 183.6 seconds
Started Jul 23 05:34:28 PM PDT 24
Finished Jul 23 05:37:32 PM PDT 24
Peak memory 183580 kb
Host smart-8ed01887-4901-4e6a-b0c8-ff5830afad73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360595941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.2360595941
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.2477923939
Short name T183
Test name
Test status
Simulation time 101438768662 ps
CPU time 199.26 seconds
Started Jul 23 05:34:23 PM PDT 24
Finished Jul 23 05:37:43 PM PDT 24
Peak memory 191804 kb
Host smart-8984b67c-d71e-49a5-808f-98f976dabdbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477923939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.2477923939
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.530347267
Short name T444
Test name
Test status
Simulation time 72415179068 ps
CPU time 102.2 seconds
Started Jul 23 05:34:24 PM PDT 24
Finished Jul 23 05:36:07 PM PDT 24
Peak memory 191776 kb
Host smart-14f6e50d-842c-4460-b435-b386ba21c790
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530347267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all.
530347267
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all_with_rand_reset.3745134456
Short name T14
Test name
Test status
Simulation time 93192190193 ps
CPU time 225.27 seconds
Started Jul 23 05:34:24 PM PDT 24
Finished Jul 23 05:38:10 PM PDT 24
Peak memory 198296 kb
Host smart-3aa76b82-4bf3-490d-b842-9504e6b79579
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745134456 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all_with_rand_reset.3745134456
Directory /workspace/11.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.rv_timer_random.168063835
Short name T282
Test name
Test status
Simulation time 41012798128 ps
CPU time 779.08 seconds
Started Jul 23 05:37:11 PM PDT 24
Finished Jul 23 05:50:11 PM PDT 24
Peak memory 183508 kb
Host smart-165fcb4c-6fd3-4335-89c2-1f0640f0e9a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168063835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.168063835
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.1692335265
Short name T130
Test name
Test status
Simulation time 78186695983 ps
CPU time 141.41 seconds
Started Jul 23 05:37:10 PM PDT 24
Finished Jul 23 05:39:32 PM PDT 24
Peak memory 191740 kb
Host smart-04ebfcfd-b367-447c-b487-58f164f0117c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692335265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.1692335265
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.3910422721
Short name T127
Test name
Test status
Simulation time 236250340959 ps
CPU time 1733.7 seconds
Started Jul 23 05:37:10 PM PDT 24
Finished Jul 23 06:06:04 PM PDT 24
Peak memory 191792 kb
Host smart-34e2667e-fedd-46ba-a667-9cf354c76ccf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910422721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.3910422721
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.3296165486
Short name T233
Test name
Test status
Simulation time 417602388806 ps
CPU time 2180.42 seconds
Started Jul 23 05:37:09 PM PDT 24
Finished Jul 23 06:13:31 PM PDT 24
Peak memory 191744 kb
Host smart-11a58452-e2ed-44fe-97fa-3ba1025c0d9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296165486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.3296165486
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.2926854429
Short name T392
Test name
Test status
Simulation time 87296786832 ps
CPU time 290.11 seconds
Started Jul 23 05:37:10 PM PDT 24
Finished Jul 23 05:42:01 PM PDT 24
Peak memory 183528 kb
Host smart-40bb44b7-1de4-4143-b0e1-dbda7e6aa509
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926854429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.2926854429
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.1851865414
Short name T252
Test name
Test status
Simulation time 97310981386 ps
CPU time 44.67 seconds
Started Jul 23 05:37:12 PM PDT 24
Finished Jul 23 05:37:58 PM PDT 24
Peak memory 183592 kb
Host smart-15f00846-9e2d-4f4f-b7b4-4e88ec0c5ce1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851865414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.1851865414
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.2531690047
Short name T133
Test name
Test status
Simulation time 105712474677 ps
CPU time 785.64 seconds
Started Jul 23 05:37:12 PM PDT 24
Finished Jul 23 05:50:18 PM PDT 24
Peak memory 191780 kb
Host smart-dc4f4b69-a62d-49b1-9b6c-2bf61e07b13b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531690047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.2531690047
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.1527544241
Short name T200
Test name
Test status
Simulation time 15222666453 ps
CPU time 22.81 seconds
Started Jul 23 05:37:12 PM PDT 24
Finished Jul 23 05:37:36 PM PDT 24
Peak memory 183404 kb
Host smart-0db19602-d8ba-461b-b087-e7cfdbcf625f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527544241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.1527544241
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.3741690705
Short name T226
Test name
Test status
Simulation time 86444067375 ps
CPU time 75.86 seconds
Started Jul 23 05:37:10 PM PDT 24
Finished Jul 23 05:38:27 PM PDT 24
Peak memory 183588 kb
Host smart-fc1db3ab-0d1c-4681-b406-8ea4cb70110e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741690705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.3741690705
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.553380920
Short name T314
Test name
Test status
Simulation time 384034611430 ps
CPU time 222.7 seconds
Started Jul 23 05:34:32 PM PDT 24
Finished Jul 23 05:38:16 PM PDT 24
Peak memory 183524 kb
Host smart-3a11e90f-e9de-4162-9ab0-5869bc98e4c6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553380920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.rv_timer_cfg_update_on_fly.553380920
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.923784423
Short name T382
Test name
Test status
Simulation time 288265120812 ps
CPU time 118.39 seconds
Started Jul 23 05:34:31 PM PDT 24
Finished Jul 23 05:36:31 PM PDT 24
Peak memory 183608 kb
Host smart-f546b133-8d91-4672-a6cf-42cb07e94882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923784423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.923784423
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.2551543740
Short name T236
Test name
Test status
Simulation time 55435866496 ps
CPU time 106.16 seconds
Started Jul 23 05:34:37 PM PDT 24
Finished Jul 23 05:36:23 PM PDT 24
Peak memory 191732 kb
Host smart-58e23f70-d468-475f-bdf2-a3d5b352a852
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551543740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.2551543740
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.2341216340
Short name T367
Test name
Test status
Simulation time 1281954293820 ps
CPU time 477.83 seconds
Started Jul 23 05:34:33 PM PDT 24
Finished Jul 23 05:42:32 PM PDT 24
Peak memory 183556 kb
Host smart-f9cf04e1-f906-4d40-b86b-34ea72b13b55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341216340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.2341216340
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all_with_rand_reset.873056446
Short name T79
Test name
Test status
Simulation time 65723021732 ps
CPU time 549.87 seconds
Started Jul 23 05:34:33 PM PDT 24
Finished Jul 23 05:43:44 PM PDT 24
Peak memory 198144 kb
Host smart-d224ecc0-e8b1-4583-a7f0-2f82a113eb44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873056446 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all_with_rand_reset.873056446
Directory /workspace/12.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.rv_timer_random.2506941870
Short name T122
Test name
Test status
Simulation time 260490508044 ps
CPU time 481.28 seconds
Started Jul 23 05:37:20 PM PDT 24
Finished Jul 23 05:45:22 PM PDT 24
Peak memory 191780 kb
Host smart-f9aceb59-086b-4c37-b19e-b801d8261005
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506941870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.2506941870
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.3019933219
Short name T331
Test name
Test status
Simulation time 59057027285 ps
CPU time 17.03 seconds
Started Jul 23 05:37:18 PM PDT 24
Finished Jul 23 05:37:37 PM PDT 24
Peak memory 183532 kb
Host smart-e36a5af3-8540-45f6-ade1-963c4921b053
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019933219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.3019933219
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.1369093103
Short name T296
Test name
Test status
Simulation time 139825026374 ps
CPU time 682.21 seconds
Started Jul 23 05:37:18 PM PDT 24
Finished Jul 23 05:48:42 PM PDT 24
Peak memory 191780 kb
Host smart-bd3de28d-aa8d-47d1-9958-4e9df8f8f87b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369093103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.1369093103
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.3316583838
Short name T120
Test name
Test status
Simulation time 94182472813 ps
CPU time 170.14 seconds
Started Jul 23 05:37:19 PM PDT 24
Finished Jul 23 05:40:11 PM PDT 24
Peak memory 191756 kb
Host smart-27b67b0a-ab94-4c7e-b036-593a1141552e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316583838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.3316583838
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.2083781016
Short name T2
Test name
Test status
Simulation time 293370003820 ps
CPU time 302.88 seconds
Started Jul 23 05:37:18 PM PDT 24
Finished Jul 23 05:42:23 PM PDT 24
Peak memory 191744 kb
Host smart-32d74f7d-3dda-4538-bf17-9035e998482f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083781016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.2083781016
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.1395140939
Short name T94
Test name
Test status
Simulation time 17769340655 ps
CPU time 26.02 seconds
Started Jul 23 05:37:18 PM PDT 24
Finished Jul 23 05:37:46 PM PDT 24
Peak memory 183552 kb
Host smart-5074d4e1-179a-4889-9a2f-471afded074e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395140939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.1395140939
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.1974017763
Short name T275
Test name
Test status
Simulation time 1312488070462 ps
CPU time 1742.46 seconds
Started Jul 23 05:37:17 PM PDT 24
Finished Jul 23 06:06:21 PM PDT 24
Peak memory 191760 kb
Host smart-519cd1a0-f4d0-4985-81b8-1bf58099f665
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974017763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.1974017763
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.527593146
Short name T307
Test name
Test status
Simulation time 165503398156 ps
CPU time 1406.88 seconds
Started Jul 23 05:37:18 PM PDT 24
Finished Jul 23 06:00:46 PM PDT 24
Peak memory 183596 kb
Host smart-b7322a83-7cbd-4bb4-b6e7-764bd2777c8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527593146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.527593146
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.355330293
Short name T288
Test name
Test status
Simulation time 43913548850 ps
CPU time 17.58 seconds
Started Jul 23 05:34:36 PM PDT 24
Finished Jul 23 05:34:55 PM PDT 24
Peak memory 183584 kb
Host smart-3137fc36-c943-4251-b5aa-2bd5bdfd0ba9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355330293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.rv_timer_cfg_update_on_fly.355330293
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.2724873892
Short name T390
Test name
Test status
Simulation time 93348399830 ps
CPU time 134.06 seconds
Started Jul 23 05:34:31 PM PDT 24
Finished Jul 23 05:36:46 PM PDT 24
Peak memory 183520 kb
Host smart-b86cb0f3-1e58-4a53-a59e-118336e48144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724873892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.2724873892
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.2455894902
Short name T432
Test name
Test status
Simulation time 329294345703 ps
CPU time 463.06 seconds
Started Jul 23 05:34:33 PM PDT 24
Finished Jul 23 05:42:17 PM PDT 24
Peak memory 191632 kb
Host smart-56fdae30-3bd8-4728-90e0-2f1c352401d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455894902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.2455894902
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all_with_rand_reset.2869869183
Short name T36
Test name
Test status
Simulation time 13091425267 ps
CPU time 117.45 seconds
Started Jul 23 05:34:37 PM PDT 24
Finished Jul 23 05:36:35 PM PDT 24
Peak memory 198248 kb
Host smart-16b13750-582f-4fe1-a939-ebd0492acc18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869869183 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all_with_rand_reset.2869869183
Directory /workspace/13.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/131.rv_timer_random.813960070
Short name T250
Test name
Test status
Simulation time 60383518038 ps
CPU time 78.66 seconds
Started Jul 23 05:37:20 PM PDT 24
Finished Jul 23 05:38:40 PM PDT 24
Peak memory 194004 kb
Host smart-c407a317-e009-41b5-8220-447c6183909b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813960070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.813960070
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.2091081017
Short name T204
Test name
Test status
Simulation time 111660817089 ps
CPU time 947.73 seconds
Started Jul 23 05:37:25 PM PDT 24
Finished Jul 23 05:53:14 PM PDT 24
Peak memory 191744 kb
Host smart-615a7248-7b4a-4edc-b89f-eb7c09a64bfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091081017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.2091081017
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.2203120943
Short name T281
Test name
Test status
Simulation time 109741230292 ps
CPU time 54.98 seconds
Started Jul 23 05:37:27 PM PDT 24
Finished Jul 23 05:38:22 PM PDT 24
Peak memory 191788 kb
Host smart-11a69822-59dc-4a65-9bdc-259c5c867e65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203120943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.2203120943
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.3225154153
Short name T21
Test name
Test status
Simulation time 84210457738 ps
CPU time 293.06 seconds
Started Jul 23 05:37:26 PM PDT 24
Finished Jul 23 05:42:20 PM PDT 24
Peak memory 191700 kb
Host smart-0f9ffdc4-086b-4e4d-af21-ff88e48ff16c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225154153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.3225154153
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.4176464430
Short name T287
Test name
Test status
Simulation time 50941224287 ps
CPU time 81.14 seconds
Started Jul 23 05:37:26 PM PDT 24
Finished Jul 23 05:38:48 PM PDT 24
Peak memory 183496 kb
Host smart-f17950fc-00d2-40ed-b4d6-a8bec00d3cb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176464430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.4176464430
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.785792307
Short name T359
Test name
Test status
Simulation time 10290382647 ps
CPU time 9.66 seconds
Started Jul 23 05:34:34 PM PDT 24
Finished Jul 23 05:34:45 PM PDT 24
Peak memory 183584 kb
Host smart-eb36a61f-44d5-4984-a880-e0b7a936e446
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785792307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.rv_timer_cfg_update_on_fly.785792307
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.3540451058
Short name T445
Test name
Test status
Simulation time 825415364704 ps
CPU time 182.69 seconds
Started Jul 23 05:34:31 PM PDT 24
Finished Jul 23 05:37:35 PM PDT 24
Peak memory 183572 kb
Host smart-0e160cf6-3676-4edb-8860-bad85b70131f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540451058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.3540451058
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.2205337157
Short name T166
Test name
Test status
Simulation time 148464617623 ps
CPU time 1919.76 seconds
Started Jul 23 05:34:36 PM PDT 24
Finished Jul 23 06:06:37 PM PDT 24
Peak memory 191632 kb
Host smart-2eb53a1d-303d-4963-a0ec-25200e5d643e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205337157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.2205337157
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.3552141317
Short name T260
Test name
Test status
Simulation time 44088511713 ps
CPU time 312.78 seconds
Started Jul 23 05:34:31 PM PDT 24
Finished Jul 23 05:39:45 PM PDT 24
Peak memory 191780 kb
Host smart-3138d21c-82b3-4efa-96ff-4125662891c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552141317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.3552141317
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.2380123946
Short name T272
Test name
Test status
Simulation time 186141410576 ps
CPU time 1892.99 seconds
Started Jul 23 05:34:33 PM PDT 24
Finished Jul 23 06:06:08 PM PDT 24
Peak memory 183540 kb
Host smart-e0d7c3a6-baaa-41a1-a63c-2ebeefffb6ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380123946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.2380123946
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/140.rv_timer_random.1550140650
Short name T328
Test name
Test status
Simulation time 56351646974 ps
CPU time 46.72 seconds
Started Jul 23 05:37:25 PM PDT 24
Finished Jul 23 05:38:12 PM PDT 24
Peak memory 191764 kb
Host smart-ff697d7b-5f73-4c52-9a4f-c77040e468a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550140650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.1550140650
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.453924768
Short name T319
Test name
Test status
Simulation time 2377283381627 ps
CPU time 710.32 seconds
Started Jul 23 05:37:34 PM PDT 24
Finished Jul 23 05:49:25 PM PDT 24
Peak memory 191792 kb
Host smart-ab77d100-f231-400b-a3c7-59302ccc42a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453924768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.453924768
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.1712580819
Short name T385
Test name
Test status
Simulation time 1379502977 ps
CPU time 2.79 seconds
Started Jul 23 05:37:36 PM PDT 24
Finished Jul 23 05:37:39 PM PDT 24
Peak memory 183368 kb
Host smart-1c31af4d-bb15-40be-9afe-f6c27114925e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712580819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.1712580819
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.590152097
Short name T202
Test name
Test status
Simulation time 56295454503 ps
CPU time 77.28 seconds
Started Jul 23 05:37:35 PM PDT 24
Finished Jul 23 05:38:53 PM PDT 24
Peak memory 183496 kb
Host smart-94b8e123-3eec-41b1-9688-e8cd14ce3e4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590152097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.590152097
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.2060749642
Short name T219
Test name
Test status
Simulation time 402554305060 ps
CPU time 131.39 seconds
Started Jul 23 05:37:36 PM PDT 24
Finished Jul 23 05:39:48 PM PDT 24
Peak memory 191756 kb
Host smart-36633969-82ff-4e11-aa24-ff02686a4d63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060749642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.2060749642
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.3657047003
Short name T346
Test name
Test status
Simulation time 285233176800 ps
CPU time 542.91 seconds
Started Jul 23 05:37:35 PM PDT 24
Finished Jul 23 05:46:39 PM PDT 24
Peak memory 191788 kb
Host smart-c1f3077e-ae15-4572-a6a3-eedf467eb90e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657047003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.3657047003
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.2989676274
Short name T232
Test name
Test status
Simulation time 528261358856 ps
CPU time 210.03 seconds
Started Jul 23 05:34:30 PM PDT 24
Finished Jul 23 05:38:01 PM PDT 24
Peak memory 183512 kb
Host smart-63794332-1eec-4511-97a4-b17a19fb7d43
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989676274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.2989676274
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.2975446790
Short name T376
Test name
Test status
Simulation time 114573527520 ps
CPU time 135.47 seconds
Started Jul 23 05:34:34 PM PDT 24
Finished Jul 23 05:36:50 PM PDT 24
Peak memory 183584 kb
Host smart-7bea3a56-2584-43f1-ad95-9878d9cf743a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975446790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.2975446790
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.22572785
Short name T192
Test name
Test status
Simulation time 122762829029 ps
CPU time 123.32 seconds
Started Jul 23 05:34:35 PM PDT 24
Finished Jul 23 05:36:39 PM PDT 24
Peak memory 191748 kb
Host smart-dd90d453-cd0b-465e-8311-7a802be8f4f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22572785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.22572785
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.3146583363
Short name T221
Test name
Test status
Simulation time 23598257990 ps
CPU time 15.7 seconds
Started Jul 23 05:34:35 PM PDT 24
Finished Jul 23 05:34:51 PM PDT 24
Peak memory 183496 kb
Host smart-2ec21acd-f2c9-424b-b494-57be97a203c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146583363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.3146583363
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.433303432
Short name T448
Test name
Test status
Simulation time 67508973973 ps
CPU time 86.64 seconds
Started Jul 23 05:34:31 PM PDT 24
Finished Jul 23 05:35:59 PM PDT 24
Peak memory 183572 kb
Host smart-d8537085-ca3c-43aa-b686-b31a0e9d29bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433303432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all.
433303432
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/150.rv_timer_random.2753925952
Short name T297
Test name
Test status
Simulation time 152387891555 ps
CPU time 299.42 seconds
Started Jul 23 05:37:35 PM PDT 24
Finished Jul 23 05:42:35 PM PDT 24
Peak memory 183512 kb
Host smart-9b25bd80-6114-45f3-bb4d-9cfc2c692bab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753925952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.2753925952
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.3483826917
Short name T421
Test name
Test status
Simulation time 9864485650 ps
CPU time 5.95 seconds
Started Jul 23 05:37:45 PM PDT 24
Finished Jul 23 05:37:51 PM PDT 24
Peak memory 183776 kb
Host smart-13ea96a6-1204-4821-b324-6b7172ea903a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483826917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.3483826917
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.2172404594
Short name T305
Test name
Test status
Simulation time 10896765727 ps
CPU time 18.43 seconds
Started Jul 23 05:37:43 PM PDT 24
Finished Jul 23 05:38:02 PM PDT 24
Peak memory 183568 kb
Host smart-56fe9665-9f39-4afd-858e-3f1a29a76d62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172404594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.2172404594
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.2790948843
Short name T97
Test name
Test status
Simulation time 149820307415 ps
CPU time 116.16 seconds
Started Jul 23 05:37:43 PM PDT 24
Finished Jul 23 05:39:40 PM PDT 24
Peak memory 193640 kb
Host smart-3b84a8c8-0f1a-4768-9c1d-5c8176ca6635
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790948843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.2790948843
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.1137226022
Short name T241
Test name
Test status
Simulation time 42319681245 ps
CPU time 80.7 seconds
Started Jul 23 05:37:46 PM PDT 24
Finished Jul 23 05:39:07 PM PDT 24
Peak memory 191808 kb
Host smart-4845fee8-7fd0-44ae-a4db-1ad512af883c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137226022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.1137226022
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.2321829571
Short name T199
Test name
Test status
Simulation time 232814556677 ps
CPU time 120.07 seconds
Started Jul 23 05:34:34 PM PDT 24
Finished Jul 23 05:36:35 PM PDT 24
Peak memory 183572 kb
Host smart-884fb75b-0b96-4db9-b3e8-22190d97846d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321829571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.2321829571
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_random.1398580963
Short name T228
Test name
Test status
Simulation time 334456546730 ps
CPU time 294.58 seconds
Started Jul 23 05:34:32 PM PDT 24
Finished Jul 23 05:39:27 PM PDT 24
Peak memory 191772 kb
Host smart-fc51da9d-2b4c-4705-81b2-b7e0f2fb3936
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398580963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.1398580963
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.2642863667
Short name T438
Test name
Test status
Simulation time 2497034326 ps
CPU time 2.09 seconds
Started Jul 23 05:34:33 PM PDT 24
Finished Jul 23 05:34:37 PM PDT 24
Peak memory 183532 kb
Host smart-e5df1d6c-6cc7-488a-8bcc-fa1497cd962b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642863667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.2642863667
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.3891159599
Short name T366
Test name
Test status
Simulation time 1989225517152 ps
CPU time 581.84 seconds
Started Jul 23 05:34:30 PM PDT 24
Finished Jul 23 05:44:12 PM PDT 24
Peak memory 191772 kb
Host smart-e7eb5fdc-21b9-414c-b31b-95ef92be9025
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891159599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.3891159599
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all_with_rand_reset.3482178015
Short name T426
Test name
Test status
Simulation time 76044319884 ps
CPU time 235.75 seconds
Started Jul 23 05:34:33 PM PDT 24
Finished Jul 23 05:38:29 PM PDT 24
Peak memory 206488 kb
Host smart-92b6533c-0a22-452f-ba1a-87caacc47efa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482178015 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all_with_rand_reset.3482178015
Directory /workspace/16.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.39608711
Short name T103
Test name
Test status
Simulation time 320825811960 ps
CPU time 840.96 seconds
Started Jul 23 05:37:45 PM PDT 24
Finished Jul 23 05:51:47 PM PDT 24
Peak memory 191668 kb
Host smart-af7559d5-9724-44a9-928e-68fdae43fa9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39608711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.39608711
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.4083533461
Short name T338
Test name
Test status
Simulation time 64506854638 ps
CPU time 122.46 seconds
Started Jul 23 05:37:46 PM PDT 24
Finished Jul 23 05:39:50 PM PDT 24
Peak memory 191808 kb
Host smart-187187ee-4141-4d1d-bc9b-f47dcdc34c58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083533461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.4083533461
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.2700744485
Short name T323
Test name
Test status
Simulation time 265089071406 ps
CPU time 280.55 seconds
Started Jul 23 05:37:44 PM PDT 24
Finished Jul 23 05:42:26 PM PDT 24
Peak memory 191664 kb
Host smart-b25be87c-d3c9-4893-a0b0-31c0958ccee9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700744485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.2700744485
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.3437902360
Short name T111
Test name
Test status
Simulation time 387091086364 ps
CPU time 2083.67 seconds
Started Jul 23 05:37:51 PM PDT 24
Finished Jul 23 06:12:36 PM PDT 24
Peak memory 191788 kb
Host smart-a0676ef0-318f-4c0d-a7f3-8b3262d6d08f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437902360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.3437902360
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.84025737
Short name T357
Test name
Test status
Simulation time 49965893038 ps
CPU time 82.97 seconds
Started Jul 23 05:37:52 PM PDT 24
Finished Jul 23 05:39:15 PM PDT 24
Peak memory 183580 kb
Host smart-197bdc32-a590-49c5-8304-5c145c731993
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84025737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.84025737
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.1876821811
Short name T325
Test name
Test status
Simulation time 172456508124 ps
CPU time 3303.13 seconds
Started Jul 23 05:37:52 PM PDT 24
Finished Jul 23 06:32:56 PM PDT 24
Peak memory 192656 kb
Host smart-8e1dacb2-b081-4786-a554-cfde1feeef10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876821811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.1876821811
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.3937681689
Short name T142
Test name
Test status
Simulation time 273352866670 ps
CPU time 163.97 seconds
Started Jul 23 05:37:53 PM PDT 24
Finished Jul 23 05:40:38 PM PDT 24
Peak memory 191692 kb
Host smart-4e514331-ad34-423e-938c-9e7c2214c5ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937681689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.3937681689
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.481333528
Short name T294
Test name
Test status
Simulation time 503304512596 ps
CPU time 207.17 seconds
Started Jul 23 05:37:50 PM PDT 24
Finished Jul 23 05:41:18 PM PDT 24
Peak memory 193808 kb
Host smart-142f1a32-f30e-48a6-9658-e899884d3329
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481333528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.481333528
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.4278479014
Short name T162
Test name
Test status
Simulation time 152167616575 ps
CPU time 241.16 seconds
Started Jul 23 05:37:52 PM PDT 24
Finished Jul 23 05:41:53 PM PDT 24
Peak memory 191800 kb
Host smart-c70055b1-1959-4740-8c45-5b26acd1976d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278479014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.4278479014
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.1118297299
Short name T289
Test name
Test status
Simulation time 1903540363 ps
CPU time 4.83 seconds
Started Jul 23 05:37:53 PM PDT 24
Finished Jul 23 05:37:59 PM PDT 24
Peak memory 183436 kb
Host smart-3df0fdd7-e65b-464f-b564-15e20e36bc8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118297299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.1118297299
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.1929996178
Short name T116
Test name
Test status
Simulation time 492851596183 ps
CPU time 263.38 seconds
Started Jul 23 05:34:31 PM PDT 24
Finished Jul 23 05:38:55 PM PDT 24
Peak memory 183584 kb
Host smart-dfd31699-e21e-4652-bdf6-9f57a266ff89
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929996178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.1929996178
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.3842209956
Short name T407
Test name
Test status
Simulation time 98013892944 ps
CPU time 78.24 seconds
Started Jul 23 05:34:36 PM PDT 24
Finished Jul 23 05:35:55 PM PDT 24
Peak memory 183600 kb
Host smart-3e2d6acf-f017-485c-a300-ae01782a672b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842209956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.3842209956
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.2087459645
Short name T265
Test name
Test status
Simulation time 578876884830 ps
CPU time 444.41 seconds
Started Jul 23 05:34:31 PM PDT 24
Finished Jul 23 05:41:56 PM PDT 24
Peak memory 191768 kb
Host smart-0f291ac9-14c5-4825-a115-01e579998bc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087459645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.2087459645
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.2198922311
Short name T389
Test name
Test status
Simulation time 66659507 ps
CPU time 0.62 seconds
Started Jul 23 05:34:38 PM PDT 24
Finished Jul 23 05:34:40 PM PDT 24
Peak memory 183296 kb
Host smart-c1e9c096-402b-4a22-895e-e89c746bc131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198922311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.2198922311
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/171.rv_timer_random.112568125
Short name T37
Test name
Test status
Simulation time 191324514746 ps
CPU time 86.89 seconds
Started Jul 23 05:38:02 PM PDT 24
Finished Jul 23 05:39:30 PM PDT 24
Peak memory 191640 kb
Host smart-e0619f5a-9af7-468c-a1ec-9542fcf9be30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112568125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.112568125
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.959676125
Short name T182
Test name
Test status
Simulation time 263641420567 ps
CPU time 231.93 seconds
Started Jul 23 05:38:01 PM PDT 24
Finished Jul 23 05:41:55 PM PDT 24
Peak memory 191784 kb
Host smart-44ffa0ab-f618-4d3d-b76b-cdbccabae5ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959676125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.959676125
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.3708133971
Short name T193
Test name
Test status
Simulation time 89221981100 ps
CPU time 137.56 seconds
Started Jul 23 05:38:02 PM PDT 24
Finished Jul 23 05:40:21 PM PDT 24
Peak memory 191752 kb
Host smart-4fd62d90-a7a2-4549-91c7-eea185f077a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708133971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.3708133971
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.4160857569
Short name T318
Test name
Test status
Simulation time 362442176071 ps
CPU time 520.59 seconds
Started Jul 23 05:38:01 PM PDT 24
Finished Jul 23 05:46:43 PM PDT 24
Peak memory 191712 kb
Host smart-d0bee263-777c-45c9-a184-92104be263c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160857569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.4160857569
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.1425226733
Short name T86
Test name
Test status
Simulation time 371106317809 ps
CPU time 400.45 seconds
Started Jul 23 05:38:01 PM PDT 24
Finished Jul 23 05:44:43 PM PDT 24
Peak memory 191668 kb
Host smart-843f5f6b-d25d-42ee-85b9-03e87541f925
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425226733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.1425226733
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.1202273068
Short name T344
Test name
Test status
Simulation time 24809320590 ps
CPU time 38.27 seconds
Started Jul 23 05:38:02 PM PDT 24
Finished Jul 23 05:38:42 PM PDT 24
Peak memory 183544 kb
Host smart-1ff21b3d-6111-4e87-b673-9cf3e7dfdcef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202273068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.1202273068
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.4262251298
Short name T334
Test name
Test status
Simulation time 126402433608 ps
CPU time 1239.24 seconds
Started Jul 23 05:38:07 PM PDT 24
Finished Jul 23 05:58:47 PM PDT 24
Peak memory 191776 kb
Host smart-16a35127-2a3b-459f-8859-43b2ba4be485
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262251298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.4262251298
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.1029143153
Short name T276
Test name
Test status
Simulation time 84392555174 ps
CPU time 133.49 seconds
Started Jul 23 05:34:35 PM PDT 24
Finished Jul 23 05:36:49 PM PDT 24
Peak memory 183536 kb
Host smart-227656ef-ca20-4541-87d8-d8fa18bc1a7a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029143153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.1029143153
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.3977521642
Short name T383
Test name
Test status
Simulation time 469856552722 ps
CPU time 204.94 seconds
Started Jul 23 05:34:33 PM PDT 24
Finished Jul 23 05:37:59 PM PDT 24
Peak memory 183588 kb
Host smart-a75d65d3-13e7-4f87-abf1-958096547eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977521642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.3977521642
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.1878343098
Short name T347
Test name
Test status
Simulation time 324573124780 ps
CPU time 351.04 seconds
Started Jul 23 05:34:38 PM PDT 24
Finished Jul 23 05:40:29 PM PDT 24
Peak memory 191732 kb
Host smart-b28e4dca-5c44-4952-ba6d-c9124233d5e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878343098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.1878343098
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.2367448272
Short name T394
Test name
Test status
Simulation time 461913163 ps
CPU time 0.62 seconds
Started Jul 23 05:34:38 PM PDT 24
Finished Jul 23 05:34:39 PM PDT 24
Peak memory 183196 kb
Host smart-93072363-f8df-40fd-9f2d-80f1188c75c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367448272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.2367448272
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/180.rv_timer_random.2924525615
Short name T174
Test name
Test status
Simulation time 82585318304 ps
CPU time 173.76 seconds
Started Jul 23 05:38:08 PM PDT 24
Finished Jul 23 05:41:02 PM PDT 24
Peak memory 191744 kb
Host smart-4c41e8a2-e277-4e46-b0dc-a80723317658
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924525615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.2924525615
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.2903859208
Short name T247
Test name
Test status
Simulation time 623838947962 ps
CPU time 93.72 seconds
Started Jul 23 05:38:08 PM PDT 24
Finished Jul 23 05:39:42 PM PDT 24
Peak memory 183588 kb
Host smart-44071676-b2dc-4bc3-8b6d-cf7fb6bd6982
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903859208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.2903859208
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.249096975
Short name T62
Test name
Test status
Simulation time 65221070330 ps
CPU time 1166 seconds
Started Jul 23 05:38:16 PM PDT 24
Finished Jul 23 05:57:43 PM PDT 24
Peak memory 183440 kb
Host smart-151cd4fc-810a-4af3-844c-02e236a2c962
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249096975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.249096975
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.3708453797
Short name T177
Test name
Test status
Simulation time 171508779556 ps
CPU time 1639.78 seconds
Started Jul 23 05:38:16 PM PDT 24
Finished Jul 23 06:05:37 PM PDT 24
Peak memory 191772 kb
Host smart-f301c08a-2f83-486d-840e-3f3e540d22a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708453797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.3708453797
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.4180378314
Short name T118
Test name
Test status
Simulation time 40663784572 ps
CPU time 67.41 seconds
Started Jul 23 05:38:15 PM PDT 24
Finished Jul 23 05:39:24 PM PDT 24
Peak memory 191768 kb
Host smart-faaeac99-2aba-4fb8-940e-0b210803913b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180378314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.4180378314
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.2792503570
Short name T306
Test name
Test status
Simulation time 32592637466 ps
CPU time 47.42 seconds
Started Jul 23 05:38:15 PM PDT 24
Finished Jul 23 05:39:03 PM PDT 24
Peak memory 183596 kb
Host smart-f4bb63b8-427b-418c-9b25-be1fbd9541e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792503570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.2792503570
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.3050398843
Short name T240
Test name
Test status
Simulation time 379032393020 ps
CPU time 161.87 seconds
Started Jul 23 05:34:47 PM PDT 24
Finished Jul 23 05:37:29 PM PDT 24
Peak memory 183520 kb
Host smart-e57be8a3-9af2-4a45-b612-1cd763a727b5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050398843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.3050398843
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.3184537071
Short name T428
Test name
Test status
Simulation time 218567894894 ps
CPU time 120.18 seconds
Started Jul 23 05:34:41 PM PDT 24
Finished Jul 23 05:36:42 PM PDT 24
Peak memory 183608 kb
Host smart-bdb3456c-4e20-441d-befc-fcdddf4189d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184537071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.3184537071
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.301433912
Short name T147
Test name
Test status
Simulation time 176158479620 ps
CPU time 645.75 seconds
Started Jul 23 05:34:44 PM PDT 24
Finished Jul 23 05:45:31 PM PDT 24
Peak memory 191784 kb
Host smart-a46b41e8-5f27-40ec-a101-7e8e60420b19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301433912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.301433912
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/190.rv_timer_random.3546884968
Short name T25
Test name
Test status
Simulation time 123796526360 ps
CPU time 178.77 seconds
Started Jul 23 05:38:15 PM PDT 24
Finished Jul 23 05:41:16 PM PDT 24
Peak memory 191788 kb
Host smart-0574a907-f507-44c7-8231-126591c56114
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546884968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.3546884968
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.3960997101
Short name T453
Test name
Test status
Simulation time 121146614135 ps
CPU time 71.11 seconds
Started Jul 23 05:38:16 PM PDT 24
Finished Jul 23 05:39:28 PM PDT 24
Peak memory 183588 kb
Host smart-d521b2a8-eed6-4f86-96ae-e0f7feeac758
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960997101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.3960997101
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.44237438
Short name T214
Test name
Test status
Simulation time 315999599277 ps
CPU time 146.31 seconds
Started Jul 23 05:38:15 PM PDT 24
Finished Jul 23 05:40:43 PM PDT 24
Peak memory 191728 kb
Host smart-94182166-8aaa-47d9-b1f8-547ef7e682ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44237438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.44237438
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.2934244838
Short name T146
Test name
Test status
Simulation time 42604643381 ps
CPU time 69.31 seconds
Started Jul 23 05:38:16 PM PDT 24
Finished Jul 23 05:39:26 PM PDT 24
Peak memory 183572 kb
Host smart-a1ca8ea5-e7cc-4a95-8ea3-d6aa04767721
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934244838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.2934244838
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.3282960727
Short name T253
Test name
Test status
Simulation time 382483370688 ps
CPU time 179.69 seconds
Started Jul 23 05:38:17 PM PDT 24
Finished Jul 23 05:41:18 PM PDT 24
Peak memory 195220 kb
Host smart-872bdaca-a140-4cf3-ac3e-83260561c12f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282960727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.3282960727
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.750237363
Short name T100
Test name
Test status
Simulation time 75344435107 ps
CPU time 189.62 seconds
Started Jul 23 05:38:23 PM PDT 24
Finished Jul 23 05:41:33 PM PDT 24
Peak memory 191756 kb
Host smart-32ac90b2-0e65-4b65-a3be-ebf2dacbce71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750237363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.750237363
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.262620632
Short name T171
Test name
Test status
Simulation time 103315621369 ps
CPU time 277.86 seconds
Started Jul 23 05:38:23 PM PDT 24
Finished Jul 23 05:43:02 PM PDT 24
Peak memory 194924 kb
Host smart-1b1ad2e3-2edd-4b33-afe6-8faef27335cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262620632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.262620632
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.2195376011
Short name T126
Test name
Test status
Simulation time 169353399138 ps
CPU time 73.97 seconds
Started Jul 23 05:38:22 PM PDT 24
Finished Jul 23 05:39:37 PM PDT 24
Peak memory 191764 kb
Host smart-ce279f28-99db-4d86-ba23-533a439c8691
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195376011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.2195376011
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.1082214092
Short name T213
Test name
Test status
Simulation time 208713564726 ps
CPU time 316.3 seconds
Started Jul 23 05:34:16 PM PDT 24
Finished Jul 23 05:39:33 PM PDT 24
Peak memory 183524 kb
Host smart-34fb5668-4c61-4cea-91cc-4020d27b0287
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082214092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.1082214092
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.1657285338
Short name T415
Test name
Test status
Simulation time 136034323453 ps
CPU time 216.16 seconds
Started Jul 23 05:34:16 PM PDT 24
Finished Jul 23 05:37:53 PM PDT 24
Peak memory 183520 kb
Host smart-b688f932-8eb1-40c0-b4d5-2fc52d9f0f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657285338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.1657285338
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.3606656794
Short name T283
Test name
Test status
Simulation time 76164632371 ps
CPU time 121.66 seconds
Started Jul 23 05:34:12 PM PDT 24
Finished Jul 23 05:36:15 PM PDT 24
Peak memory 191768 kb
Host smart-4cd483a0-7c21-4de4-98d3-4433f9966551
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606656794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.3606656794
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.4076983880
Short name T365
Test name
Test status
Simulation time 428051544 ps
CPU time 0.82 seconds
Started Jul 23 05:34:14 PM PDT 24
Finished Jul 23 05:34:17 PM PDT 24
Peak memory 191988 kb
Host smart-ec00b8aa-9759-4e1d-ad68-acf2f8c223b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076983880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.4076983880
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.2670973
Short name T19
Test name
Test status
Simulation time 36377698 ps
CPU time 0.72 seconds
Started Jul 23 05:34:14 PM PDT 24
Finished Jul 23 05:34:16 PM PDT 24
Peak memory 213856 kb
Host smart-9dd03101-3ea4-4f32-99d9-623f30445d81
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.2670973
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all_with_rand_reset.942211092
Short name T34
Test name
Test status
Simulation time 93024152533 ps
CPU time 143.45 seconds
Started Jul 23 05:34:12 PM PDT 24
Finished Jul 23 05:36:37 PM PDT 24
Peak memory 206472 kb
Host smart-01deb344-9d9a-481f-b35c-18eb48e10c10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942211092 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all_with_rand_reset.942211092
Directory /workspace/2.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.1630331428
Short name T157
Test name
Test status
Simulation time 236249700097 ps
CPU time 416.8 seconds
Started Jul 23 05:34:45 PM PDT 24
Finished Jul 23 05:41:43 PM PDT 24
Peak memory 183572 kb
Host smart-dece606a-70be-4feb-8ec9-f5b0d527fe3c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630331428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.1630331428
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.1437555868
Short name T449
Test name
Test status
Simulation time 274637888048 ps
CPU time 53.32 seconds
Started Jul 23 05:34:44 PM PDT 24
Finished Jul 23 05:35:39 PM PDT 24
Peak memory 183580 kb
Host smart-c0c48fd0-b5ff-45df-a9e6-5c3a7b7a2759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437555868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.1437555868
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.2730331105
Short name T409
Test name
Test status
Simulation time 51256982105 ps
CPU time 53.75 seconds
Started Jul 23 05:34:44 PM PDT 24
Finished Jul 23 05:35:39 PM PDT 24
Peak memory 183580 kb
Host smart-c04f0c72-d0df-43da-8608-3326ee3c3275
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730331105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.2730331105
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.2271100273
Short name T353
Test name
Test status
Simulation time 150806591402 ps
CPU time 41.7 seconds
Started Jul 23 05:34:43 PM PDT 24
Finished Jul 23 05:35:25 PM PDT 24
Peak memory 183372 kb
Host smart-87670755-3452-4b9e-8445-a8cf62744410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271100273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.2271100273
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all_with_rand_reset.3245807763
Short name T35
Test name
Test status
Simulation time 264354803648 ps
CPU time 1783.66 seconds
Started Jul 23 05:34:44 PM PDT 24
Finished Jul 23 06:04:29 PM PDT 24
Peak memory 214540 kb
Host smart-f9433cda-15e8-4c05-9cb4-eb5d51288e0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245807763 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all_with_rand_reset.3245807763
Directory /workspace/20.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.446863248
Short name T139
Test name
Test status
Simulation time 42547611185 ps
CPU time 22.12 seconds
Started Jul 23 05:34:40 PM PDT 24
Finished Jul 23 05:35:03 PM PDT 24
Peak memory 183572 kb
Host smart-5f275085-4774-4190-8949-e7c26fc5994c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446863248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.rv_timer_cfg_update_on_fly.446863248
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.2410351121
Short name T7
Test name
Test status
Simulation time 420095907127 ps
CPU time 289.15 seconds
Started Jul 23 05:34:42 PM PDT 24
Finished Jul 23 05:39:32 PM PDT 24
Peak memory 183528 kb
Host smart-53723199-fd54-4894-8a56-d8b11a72580d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410351121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.2410351121
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.1611445928
Short name T211
Test name
Test status
Simulation time 275768798537 ps
CPU time 531.72 seconds
Started Jul 23 05:34:41 PM PDT 24
Finished Jul 23 05:43:33 PM PDT 24
Peak memory 191800 kb
Host smart-f1694f21-bc0b-448b-9b10-07b9d06cb12c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611445928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.1611445928
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.2849064595
Short name T303
Test name
Test status
Simulation time 13902119602 ps
CPU time 47.9 seconds
Started Jul 23 05:34:41 PM PDT 24
Finished Jul 23 05:35:30 PM PDT 24
Peak memory 183568 kb
Host smart-bbe8c3b7-27df-4a38-9860-64453c96cf3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849064595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.2849064595
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.3117472701
Short name T149
Test name
Test status
Simulation time 2423578671601 ps
CPU time 1092.73 seconds
Started Jul 23 05:34:41 PM PDT 24
Finished Jul 23 05:52:55 PM PDT 24
Peak memory 191772 kb
Host smart-b8c7d02f-c1e9-488a-aa85-7ebe8a1f5bd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117472701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.3117472701
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.3158210516
Short name T442
Test name
Test status
Simulation time 95547616995 ps
CPU time 81.83 seconds
Started Jul 23 05:34:42 PM PDT 24
Finished Jul 23 05:36:05 PM PDT 24
Peak memory 183564 kb
Host smart-00d12b7b-2e46-4bcd-8390-6c519d148b46
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158210516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.3158210516
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_random.4091447826
Short name T315
Test name
Test status
Simulation time 80514913381 ps
CPU time 64.92 seconds
Started Jul 23 05:34:41 PM PDT 24
Finished Jul 23 05:35:47 PM PDT 24
Peak memory 183572 kb
Host smart-bc1d8432-24aa-4069-8b37-d1a7e6c283d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091447826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.4091447826
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.2571262246
Short name T377
Test name
Test status
Simulation time 1424364680 ps
CPU time 1.04 seconds
Started Jul 23 05:34:46 PM PDT 24
Finished Jul 23 05:34:48 PM PDT 24
Peak memory 193352 kb
Host smart-8b43073e-f834-4bd2-b705-91e2eedf26b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571262246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.2571262246
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.3142647601
Short name T437
Test name
Test status
Simulation time 588110819268 ps
CPU time 252.8 seconds
Started Jul 23 05:34:41 PM PDT 24
Finished Jul 23 05:38:55 PM PDT 24
Peak memory 183568 kb
Host smart-536ccd7b-13df-4d26-af2e-350f3bd30f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142647601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.3142647601
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.2443000181
Short name T105
Test name
Test status
Simulation time 75131398145 ps
CPU time 59.68 seconds
Started Jul 23 05:34:44 PM PDT 24
Finished Jul 23 05:35:44 PM PDT 24
Peak memory 191672 kb
Host smart-d5a7784f-90d1-4458-a434-047377b07fd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443000181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.2443000181
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.2885603607
Short name T380
Test name
Test status
Simulation time 202014609 ps
CPU time 0.69 seconds
Started Jul 23 05:34:45 PM PDT 24
Finished Jul 23 05:34:46 PM PDT 24
Peak memory 191968 kb
Host smart-6f79eea6-f94d-41f2-90d6-7384da7e76b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885603607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.2885603607
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.968606660
Short name T51
Test name
Test status
Simulation time 489090726642 ps
CPU time 1012.71 seconds
Started Jul 23 05:34:40 PM PDT 24
Finished Jul 23 05:51:33 PM PDT 24
Peak memory 191808 kb
Host smart-47223916-8eb0-4671-8f68-04cb815b4a3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968606660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all.
968606660
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.2931130136
Short name T450
Test name
Test status
Simulation time 301111370981 ps
CPU time 231.24 seconds
Started Jul 23 05:34:44 PM PDT 24
Finished Jul 23 05:38:36 PM PDT 24
Peak memory 183580 kb
Host smart-c67bc2b0-3358-418d-bd88-094fec270a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931130136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.2931130136
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.1439720189
Short name T440
Test name
Test status
Simulation time 2780628567 ps
CPU time 4.38 seconds
Started Jul 23 05:34:41 PM PDT 24
Finished Jul 23 05:34:47 PM PDT 24
Peak memory 183388 kb
Host smart-679705ab-0155-469e-b8fa-73b68ada7e2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439720189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.1439720189
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.3588180665
Short name T429
Test name
Test status
Simulation time 55340085603 ps
CPU time 89.24 seconds
Started Jul 23 05:34:43 PM PDT 24
Finished Jul 23 05:36:13 PM PDT 24
Peak memory 195372 kb
Host smart-05f6f6e8-b555-45a7-92a1-252a88578502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588180665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.3588180665
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.4096145371
Short name T201
Test name
Test status
Simulation time 852034155414 ps
CPU time 710.17 seconds
Started Jul 23 05:34:45 PM PDT 24
Finished Jul 23 05:46:36 PM PDT 24
Peak memory 191784 kb
Host smart-3853ea94-945a-4300-ba5c-247e8ab8d694
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096145371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.4096145371
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.93158432
Short name T119
Test name
Test status
Simulation time 34327886581 ps
CPU time 15.35 seconds
Started Jul 23 05:34:41 PM PDT 24
Finished Jul 23 05:34:57 PM PDT 24
Peak memory 183572 kb
Host smart-79a38120-a7a9-48aa-afa3-4a22188b3552
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93158432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.rv_timer_cfg_update_on_fly.93158432
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.4286932854
Short name T443
Test name
Test status
Simulation time 699701946465 ps
CPU time 255.78 seconds
Started Jul 23 05:34:41 PM PDT 24
Finished Jul 23 05:38:58 PM PDT 24
Peak memory 183512 kb
Host smart-8fe6d75d-c4c8-49f2-a5f8-ecb463f5f117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286932854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.4286932854
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.2907840743
Short name T237
Test name
Test status
Simulation time 198760259010 ps
CPU time 165.2 seconds
Started Jul 23 05:34:41 PM PDT 24
Finished Jul 23 05:37:27 PM PDT 24
Peak memory 195368 kb
Host smart-b54e778e-dcf9-4b97-9d24-a49f1e4dce0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907840743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.2907840743
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.2977594444
Short name T399
Test name
Test status
Simulation time 327594069 ps
CPU time 0.88 seconds
Started Jul 23 05:34:42 PM PDT 24
Finished Jul 23 05:34:44 PM PDT 24
Peak memory 183552 kb
Host smart-860d074f-4e16-4627-9c15-05648cc761ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977594444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.2977594444
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.1129726574
Short name T369
Test name
Test status
Simulation time 289874744696 ps
CPU time 122.5 seconds
Started Jul 23 05:34:50 PM PDT 24
Finished Jul 23 05:36:54 PM PDT 24
Peak memory 183548 kb
Host smart-3b311436-c765-47a3-8c8a-987e65904f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129726574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.1129726574
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.3345040339
Short name T87
Test name
Test status
Simulation time 56299592720 ps
CPU time 47.33 seconds
Started Jul 23 05:34:54 PM PDT 24
Finished Jul 23 05:35:42 PM PDT 24
Peak memory 183500 kb
Host smart-51c43000-f1a5-43f6-9ad3-2556706d05a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345040339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.3345040339
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.1952822037
Short name T311
Test name
Test status
Simulation time 94045856640 ps
CPU time 483.75 seconds
Started Jul 23 05:34:54 PM PDT 24
Finished Jul 23 05:42:58 PM PDT 24
Peak memory 183604 kb
Host smart-60ee867f-19cb-4ee6-9020-4ae571b933dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952822037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.1952822037
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all_with_rand_reset.179831413
Short name T40
Test name
Test status
Simulation time 37069450100 ps
CPU time 205.49 seconds
Started Jul 23 05:34:51 PM PDT 24
Finished Jul 23 05:38:18 PM PDT 24
Peak memory 198280 kb
Host smart-c2117ab5-9133-43ec-9ca8-15fcac2c707b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179831413 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all_with_rand_reset.179831413
Directory /workspace/26.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.3244741895
Short name T269
Test name
Test status
Simulation time 515095133974 ps
CPU time 267.96 seconds
Started Jul 23 05:34:50 PM PDT 24
Finished Jul 23 05:39:19 PM PDT 24
Peak memory 183588 kb
Host smart-90ba204e-5714-4836-93a8-cc4171c40276
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244741895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.3244741895
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.3295745339
Short name T404
Test name
Test status
Simulation time 469396994145 ps
CPU time 172.98 seconds
Started Jul 23 05:34:51 PM PDT 24
Finished Jul 23 05:37:45 PM PDT 24
Peak memory 183576 kb
Host smart-9746f74e-a147-4fa6-a467-984b2123e1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295745339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.3295745339
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.1963439065
Short name T259
Test name
Test status
Simulation time 118458368910 ps
CPU time 579.95 seconds
Started Jul 23 05:34:51 PM PDT 24
Finished Jul 23 05:44:32 PM PDT 24
Peak memory 191660 kb
Host smart-caa850b3-4ec9-4b5a-b91a-8d6ce2dba5d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963439065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.1963439065
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.3534903138
Short name T38
Test name
Test status
Simulation time 43566277520 ps
CPU time 76.28 seconds
Started Jul 23 05:34:52 PM PDT 24
Finished Jul 23 05:36:09 PM PDT 24
Peak memory 183592 kb
Host smart-50102015-daa5-4783-8ded-dffadb1096f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534903138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.3534903138
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.1521934496
Short name T410
Test name
Test status
Simulation time 85649213793 ps
CPU time 81.17 seconds
Started Jul 23 05:34:49 PM PDT 24
Finished Jul 23 05:36:12 PM PDT 24
Peak memory 183524 kb
Host smart-34f8584b-4ca0-4be6-bc60-ad4b8d8d1b9f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521934496 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.1521934496
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.167985340
Short name T424
Test name
Test status
Simulation time 48160674501 ps
CPU time 74.75 seconds
Started Jul 23 05:35:00 PM PDT 24
Finished Jul 23 05:36:15 PM PDT 24
Peak memory 183524 kb
Host smart-4a95d04e-f61c-48c6-88b3-44b874f7b982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167985340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.167985340
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.3137953212
Short name T150
Test name
Test status
Simulation time 436515337129 ps
CPU time 463.45 seconds
Started Jul 23 05:34:52 PM PDT 24
Finished Jul 23 05:42:36 PM PDT 24
Peak memory 191748 kb
Host smart-5c0bf4cc-56f7-4f84-bf4b-fd07eb5bc27f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137953212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.3137953212
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.817253678
Short name T244
Test name
Test status
Simulation time 590896208174 ps
CPU time 1302.24 seconds
Started Jul 23 05:34:54 PM PDT 24
Finished Jul 23 05:56:37 PM PDT 24
Peak memory 191784 kb
Host smart-f446b927-bbcd-40fb-bd78-c76ecb91c785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817253678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.817253678
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.3150171897
Short name T342
Test name
Test status
Simulation time 172566023220 ps
CPU time 147.2 seconds
Started Jul 23 05:34:49 PM PDT 24
Finished Jul 23 05:37:18 PM PDT 24
Peak memory 183576 kb
Host smart-1e0fc858-7d00-44e2-a82a-d4ded4f1742c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150171897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.3150171897
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.2569077432
Short name T447
Test name
Test status
Simulation time 77567730554 ps
CPU time 105.94 seconds
Started Jul 23 05:34:49 PM PDT 24
Finished Jul 23 05:36:36 PM PDT 24
Peak memory 183536 kb
Host smart-10244d85-15e1-4ed0-bfaa-3c448bdfed1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569077432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.2569077432
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.2877662984
Short name T124
Test name
Test status
Simulation time 33667267100 ps
CPU time 38.08 seconds
Started Jul 23 05:34:51 PM PDT 24
Finished Jul 23 05:35:30 PM PDT 24
Peak memory 183320 kb
Host smart-990a34bc-49f0-4da9-b92a-eec136c9931f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877662984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.2877662984
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.3467191533
Short name T246
Test name
Test status
Simulation time 159066583563 ps
CPU time 763.87 seconds
Started Jul 23 05:34:51 PM PDT 24
Finished Jul 23 05:47:36 PM PDT 24
Peak memory 197216 kb
Host smart-0b72d4c0-36ed-4eea-9ee5-fdead6f2a01c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467191533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.3467191533
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.758200393
Short name T197
Test name
Test status
Simulation time 188404919643 ps
CPU time 295.91 seconds
Started Jul 23 05:34:16 PM PDT 24
Finished Jul 23 05:39:14 PM PDT 24
Peak memory 183604 kb
Host smart-cc4f40ff-93fc-4d62-972d-d5c46e2af00f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758200393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.rv_timer_cfg_update_on_fly.758200393
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.2005924383
Short name T405
Test name
Test status
Simulation time 50562654206 ps
CPU time 73.94 seconds
Started Jul 23 05:34:16 PM PDT 24
Finished Jul 23 05:35:31 PM PDT 24
Peak memory 183528 kb
Host smart-f3da247d-d576-45e0-a020-6576d6dc98a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005924383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.2005924383
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.811866453
Short name T387
Test name
Test status
Simulation time 132104993703 ps
CPU time 59.09 seconds
Started Jul 23 05:34:13 PM PDT 24
Finished Jul 23 05:35:13 PM PDT 24
Peak memory 183488 kb
Host smart-56394533-30e5-4932-a202-7836a376ccc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811866453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.811866453
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.4113657769
Short name T439
Test name
Test status
Simulation time 406737400 ps
CPU time 0.72 seconds
Started Jul 23 05:34:20 PM PDT 24
Finished Jul 23 05:34:21 PM PDT 24
Peak memory 183256 kb
Host smart-4d389db5-7789-4562-acba-9a00eb48d977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113657769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.4113657769
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.3340921474
Short name T17
Test name
Test status
Simulation time 124282646 ps
CPU time 0.86 seconds
Started Jul 23 05:34:16 PM PDT 24
Finished Jul 23 05:34:19 PM PDT 24
Peak memory 213828 kb
Host smart-6e944120-8281-46ff-8354-4196c1b881d3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340921474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.3340921474
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.4144104599
Short name T271
Test name
Test status
Simulation time 92383364816 ps
CPU time 134.34 seconds
Started Jul 23 05:34:50 PM PDT 24
Finished Jul 23 05:37:05 PM PDT 24
Peak memory 183432 kb
Host smart-87f1ac0d-c9b0-4095-b215-fb3cdb6ea310
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144104599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.4144104599
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.1902942958
Short name T9
Test name
Test status
Simulation time 29520045635 ps
CPU time 41.08 seconds
Started Jul 23 05:34:48 PM PDT 24
Finished Jul 23 05:35:30 PM PDT 24
Peak memory 183568 kb
Host smart-2ed0a283-0b8b-4e99-a3af-1b954af9fa45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902942958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.1902942958
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.2257983879
Short name T117
Test name
Test status
Simulation time 38753393892 ps
CPU time 108.78 seconds
Started Jul 23 05:34:50 PM PDT 24
Finished Jul 23 05:36:40 PM PDT 24
Peak memory 191764 kb
Host smart-d17c4715-6d5f-4006-9e82-7a8aa0f74ce4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257983879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.2257983879
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.2796241619
Short name T452
Test name
Test status
Simulation time 663231625 ps
CPU time 1.19 seconds
Started Jul 23 05:34:52 PM PDT 24
Finished Jul 23 05:34:54 PM PDT 24
Peak memory 183508 kb
Host smart-af85cad7-e207-431f-b90d-9d779d45ea36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796241619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.2796241619
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.1018506766
Short name T274
Test name
Test status
Simulation time 256148837939 ps
CPU time 386.51 seconds
Started Jul 23 05:34:49 PM PDT 24
Finished Jul 23 05:41:17 PM PDT 24
Peak memory 191792 kb
Host smart-88bc7729-656c-4884-b6f7-ccaabee840f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018506766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.1018506766
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.3791498921
Short name T398
Test name
Test status
Simulation time 184324960735 ps
CPU time 247.89 seconds
Started Jul 23 05:34:52 PM PDT 24
Finished Jul 23 05:39:01 PM PDT 24
Peak memory 183592 kb
Host smart-e6ef87f0-8c1e-4b46-bd8d-814fb415b330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791498921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.3791498921
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.1138890244
Short name T245
Test name
Test status
Simulation time 67522847662 ps
CPU time 57.36 seconds
Started Jul 23 05:34:48 PM PDT 24
Finished Jul 23 05:35:45 PM PDT 24
Peak memory 183528 kb
Host smart-f556c0ee-75be-4292-b847-880ffa9c9585
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138890244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.1138890244
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.4262944650
Short name T280
Test name
Test status
Simulation time 31517253738 ps
CPU time 29.88 seconds
Started Jul 23 05:34:50 PM PDT 24
Finished Jul 23 05:35:21 PM PDT 24
Peak memory 191776 kb
Host smart-566dd129-f20f-43f3-b08f-fd998c830c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262944650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.4262944650
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.2410121480
Short name T163
Test name
Test status
Simulation time 1583341329844 ps
CPU time 1057.07 seconds
Started Jul 23 05:34:53 PM PDT 24
Finished Jul 23 05:52:31 PM PDT 24
Peak memory 191732 kb
Host smart-3b8b4e49-2778-4d95-8c30-f270d1532cce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410121480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.2410121480
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.1343102656
Short name T63
Test name
Test status
Simulation time 27154174434 ps
CPU time 25.76 seconds
Started Jul 23 05:34:51 PM PDT 24
Finished Jul 23 05:35:18 PM PDT 24
Peak memory 183516 kb
Host smart-9e391d95-6526-420b-a306-bca614fc4aa8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343102656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.1343102656
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.260357502
Short name T435
Test name
Test status
Simulation time 667911928976 ps
CPU time 240.87 seconds
Started Jul 23 05:34:51 PM PDT 24
Finished Jul 23 05:38:53 PM PDT 24
Peak memory 183480 kb
Host smart-46b9a019-d338-44ee-add1-663972cb7672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260357502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.260357502
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.1618804844
Short name T363
Test name
Test status
Simulation time 129116398866 ps
CPU time 66.71 seconds
Started Jul 23 05:34:55 PM PDT 24
Finished Jul 23 05:36:02 PM PDT 24
Peak memory 183576 kb
Host smart-6f35f3e6-54c5-4986-9400-a6e89751acf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618804844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.1618804844
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.2696359415
Short name T362
Test name
Test status
Simulation time 175631186582 ps
CPU time 326.62 seconds
Started Jul 23 05:34:50 PM PDT 24
Finished Jul 23 05:40:18 PM PDT 24
Peak memory 183548 kb
Host smart-d0bc2bc9-77b3-4ef8-8357-77ace4a5f975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696359415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.2696359415
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.2690746766
Short name T433
Test name
Test status
Simulation time 827918692428 ps
CPU time 669.12 seconds
Started Jul 23 05:34:52 PM PDT 24
Finished Jul 23 05:46:02 PM PDT 24
Peak memory 191744 kb
Host smart-9503c46c-3457-4d47-a878-d2607df3458c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690746766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.2690746766
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all_with_rand_reset.218595642
Short name T32
Test name
Test status
Simulation time 235758884313 ps
CPU time 197.93 seconds
Started Jul 23 05:34:48 PM PDT 24
Finished Jul 23 05:38:07 PM PDT 24
Peak memory 206500 kb
Host smart-ae13a804-d3bb-4ae2-b758-562f8a858208
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218595642 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all_with_rand_reset.218595642
Directory /workspace/32.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.2700733822
Short name T258
Test name
Test status
Simulation time 95869133222 ps
CPU time 162.87 seconds
Started Jul 23 05:34:59 PM PDT 24
Finished Jul 23 05:37:43 PM PDT 24
Peak memory 183560 kb
Host smart-9670c55d-d8e8-4740-9994-9e55a2714d51
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700733822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.2700733822
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.779382811
Short name T373
Test name
Test status
Simulation time 472606375066 ps
CPU time 81.72 seconds
Started Jul 23 05:35:03 PM PDT 24
Finished Jul 23 05:36:25 PM PDT 24
Peak memory 183596 kb
Host smart-91e50391-0e23-4a75-bad6-a001aedcb580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779382811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.779382811
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.1663711406
Short name T266
Test name
Test status
Simulation time 130051026048 ps
CPU time 217.13 seconds
Started Jul 23 05:34:54 PM PDT 24
Finished Jul 23 05:38:31 PM PDT 24
Peak memory 191784 kb
Host smart-6e9bcb7d-e3c6-4d4d-86fb-b34f9f175cea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663711406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.1663711406
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.398915005
Short name T168
Test name
Test status
Simulation time 196928382615 ps
CPU time 136.94 seconds
Started Jul 23 05:35:04 PM PDT 24
Finished Jul 23 05:37:22 PM PDT 24
Peak memory 183540 kb
Host smart-aaf03e74-bd71-4390-9f92-ee185547b5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398915005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.398915005
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.3850998980
Short name T238
Test name
Test status
Simulation time 65591174068 ps
CPU time 33.19 seconds
Started Jul 23 05:35:02 PM PDT 24
Finished Jul 23 05:35:36 PM PDT 24
Peak memory 183420 kb
Host smart-ed1a46e4-cfc2-41cc-8f34-a59943a88781
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850998980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.3850998980
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.1752518573
Short name T379
Test name
Test status
Simulation time 65326321974 ps
CPU time 84.41 seconds
Started Jul 23 05:35:03 PM PDT 24
Finished Jul 23 05:36:28 PM PDT 24
Peak memory 183596 kb
Host smart-32feb8e7-7aea-45e1-83c7-42c7c35d8879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752518573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.1752518573
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.2091853019
Short name T298
Test name
Test status
Simulation time 417570650026 ps
CPU time 2471.98 seconds
Started Jul 23 05:35:02 PM PDT 24
Finished Jul 23 06:16:15 PM PDT 24
Peak memory 191776 kb
Host smart-eea174fb-19a8-46df-b71b-248f4ad160a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091853019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.2091853019
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.156454742
Short name T261
Test name
Test status
Simulation time 41216289692 ps
CPU time 58.24 seconds
Started Jul 23 05:35:01 PM PDT 24
Finished Jul 23 05:36:00 PM PDT 24
Peak memory 183596 kb
Host smart-33811d20-98f1-42d2-9f85-f660d44f6154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156454742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.156454742
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all_with_rand_reset.218722799
Short name T12
Test name
Test status
Simulation time 702680614515 ps
CPU time 749.12 seconds
Started Jul 23 05:35:00 PM PDT 24
Finished Jul 23 05:47:30 PM PDT 24
Peak memory 208096 kb
Host smart-8a110284-d87b-4810-a198-c0aef81ddc3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218722799 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all_with_rand_reset.218722799
Directory /workspace/34.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.4242179003
Short name T336
Test name
Test status
Simulation time 125838579386 ps
CPU time 106.72 seconds
Started Jul 23 05:35:09 PM PDT 24
Finished Jul 23 05:36:57 PM PDT 24
Peak memory 183584 kb
Host smart-448f092c-6577-4399-84a4-44b3537ac5ca
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242179003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.4242179003
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.3791475311
Short name T374
Test name
Test status
Simulation time 129797630189 ps
CPU time 196.97 seconds
Started Jul 23 05:35:08 PM PDT 24
Finished Jul 23 05:38:26 PM PDT 24
Peak memory 183544 kb
Host smart-f07f5ff2-e7ff-41ef-b432-b1ff9cbc5cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791475311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.3791475311
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.2025909261
Short name T256
Test name
Test status
Simulation time 5082251760 ps
CPU time 49.8 seconds
Started Jul 23 05:35:07 PM PDT 24
Finished Jul 23 05:35:58 PM PDT 24
Peak memory 183576 kb
Host smart-32667f3f-a141-4160-a128-939b54d74872
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025909261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.2025909261
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.1297997012
Short name T223
Test name
Test status
Simulation time 60618364461 ps
CPU time 302.15 seconds
Started Jul 23 05:35:08 PM PDT 24
Finished Jul 23 05:40:11 PM PDT 24
Peak memory 191792 kb
Host smart-82c636b6-00ee-445c-93b3-e2721706bc9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297997012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.1297997012
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.3583817278
Short name T372
Test name
Test status
Simulation time 109023067564 ps
CPU time 166.46 seconds
Started Jul 23 05:35:18 PM PDT 24
Finished Jul 23 05:38:05 PM PDT 24
Peak memory 183568 kb
Host smart-1d4304e4-b4f5-4e50-be1c-47e58e3258f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583817278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.3583817278
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.3839165655
Short name T400
Test name
Test status
Simulation time 75154914599 ps
CPU time 68.44 seconds
Started Jul 23 05:35:16 PM PDT 24
Finished Jul 23 05:36:26 PM PDT 24
Peak memory 183540 kb
Host smart-fb7b2af2-c755-4387-9f83-bc81470a0fa1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839165655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.3839165655
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.3006910057
Short name T364
Test name
Test status
Simulation time 60687671072 ps
CPU time 286.05 seconds
Started Jul 23 05:35:15 PM PDT 24
Finished Jul 23 05:40:01 PM PDT 24
Peak memory 195364 kb
Host smart-4ff512bf-3b60-4794-b6cf-c7e5aaa9c3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006910057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.3006910057
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.437703665
Short name T350
Test name
Test status
Simulation time 877105834918 ps
CPU time 475.16 seconds
Started Jul 23 05:35:31 PM PDT 24
Finished Jul 23 05:43:27 PM PDT 24
Peak memory 183552 kb
Host smart-4b8fbe9d-7b68-4515-b07d-0642f5e25174
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437703665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.rv_timer_cfg_update_on_fly.437703665
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.1434416564
Short name T393
Test name
Test status
Simulation time 8571586575 ps
CPU time 3.81 seconds
Started Jul 23 05:35:31 PM PDT 24
Finished Jul 23 05:35:35 PM PDT 24
Peak memory 183556 kb
Host smart-3e1f9990-4b4e-4e09-967c-aad2db72e2f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434416564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.1434416564
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.3349247656
Short name T90
Test name
Test status
Simulation time 266904448731 ps
CPU time 2300.75 seconds
Started Jul 23 05:35:16 PM PDT 24
Finished Jul 23 06:13:37 PM PDT 24
Peak memory 191744 kb
Host smart-ddfb25eb-23b4-48ba-99d1-fe67a22ff008
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349247656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.3349247656
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.1813613797
Short name T50
Test name
Test status
Simulation time 573514723735 ps
CPU time 439.19 seconds
Started Jul 23 05:35:26 PM PDT 24
Finished Jul 23 05:42:45 PM PDT 24
Peak memory 191636 kb
Host smart-e6cb79e7-8470-4e8d-b5c8-21cbd0830a7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813613797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.1813613797
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all_with_rand_reset.2997872091
Short name T31
Test name
Test status
Simulation time 126737451864 ps
CPU time 259.96 seconds
Started Jul 23 05:35:22 PM PDT 24
Finished Jul 23 05:39:43 PM PDT 24
Peak memory 206664 kb
Host smart-db264a79-3f9e-43e1-b750-a39659706f87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997872091 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all_with_rand_reset.2997872091
Directory /workspace/37.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.2683423050
Short name T355
Test name
Test status
Simulation time 34818698802 ps
CPU time 47.65 seconds
Started Jul 23 05:35:23 PM PDT 24
Finished Jul 23 05:36:12 PM PDT 24
Peak memory 183584 kb
Host smart-a8e7ab90-85d3-42f2-99e6-67c5f255096a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683423050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.2683423050
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.3211695329
Short name T397
Test name
Test status
Simulation time 289002791042 ps
CPU time 131.19 seconds
Started Jul 23 05:35:31 PM PDT 24
Finished Jul 23 05:37:43 PM PDT 24
Peak memory 183556 kb
Host smart-b7d20d9c-a44b-4841-a08e-eeae24049879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211695329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.3211695329
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.3451199765
Short name T179
Test name
Test status
Simulation time 83997385963 ps
CPU time 137.1 seconds
Started Jul 23 05:35:23 PM PDT 24
Finished Jul 23 05:37:42 PM PDT 24
Peak memory 191772 kb
Host smart-cec99827-fc54-49cf-82d5-9f1ae770cf30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451199765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.3451199765
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.1691252525
Short name T264
Test name
Test status
Simulation time 169038187090 ps
CPU time 125 seconds
Started Jul 23 05:35:23 PM PDT 24
Finished Jul 23 05:37:29 PM PDT 24
Peak memory 183548 kb
Host smart-f50676d6-ff1f-4985-bcab-0fcf515d089e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691252525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.1691252525
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.1489857232
Short name T418
Test name
Test status
Simulation time 467156459911 ps
CPU time 511.6 seconds
Started Jul 23 05:35:22 PM PDT 24
Finished Jul 23 05:43:55 PM PDT 24
Peak memory 196312 kb
Host smart-e3f17f1b-6ae1-4c0a-a7b2-983e7179d994
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489857232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.1489857232
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.2157374260
Short name T333
Test name
Test status
Simulation time 358305601743 ps
CPU time 576.74 seconds
Started Jul 23 05:35:24 PM PDT 24
Finished Jul 23 05:45:02 PM PDT 24
Peak memory 183588 kb
Host smart-aa767b30-60b4-49d1-9a77-8572c58291da
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157374260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.2157374260
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.102943120
Short name T422
Test name
Test status
Simulation time 911422294835 ps
CPU time 154.69 seconds
Started Jul 23 05:35:23 PM PDT 24
Finished Jul 23 05:37:59 PM PDT 24
Peak memory 183560 kb
Host smart-77d948bd-cc80-49b1-8210-59da0a155988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102943120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.102943120
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.719024104
Short name T285
Test name
Test status
Simulation time 126840207345 ps
CPU time 1104.86 seconds
Started Jul 23 05:35:23 PM PDT 24
Finished Jul 23 05:53:49 PM PDT 24
Peak memory 191800 kb
Host smart-90c73c46-aad1-432a-b355-e62676259b79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719024104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.719024104
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.1393031044
Short name T23
Test name
Test status
Simulation time 445569967937 ps
CPU time 560.38 seconds
Started Jul 23 05:35:34 PM PDT 24
Finished Jul 23 05:44:56 PM PDT 24
Peak memory 191760 kb
Host smart-cf212c18-aa54-4501-b06c-75cdb5564116
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393031044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.1393031044
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.3100402759
Short name T324
Test name
Test status
Simulation time 491464193995 ps
CPU time 775.42 seconds
Started Jul 23 05:34:16 PM PDT 24
Finished Jul 23 05:47:13 PM PDT 24
Peak memory 183504 kb
Host smart-62338f51-f82a-479f-a865-9e3069af238e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100402759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.3100402759
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.570309075
Short name T395
Test name
Test status
Simulation time 92809784302 ps
CPU time 26.35 seconds
Started Jul 23 05:34:16 PM PDT 24
Finished Jul 23 05:34:44 PM PDT 24
Peak memory 183584 kb
Host smart-7af63372-7389-4124-95ef-88b727740902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570309075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.570309075
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.862369278
Short name T185
Test name
Test status
Simulation time 420161801167 ps
CPU time 795.03 seconds
Started Jul 23 05:34:15 PM PDT 24
Finished Jul 23 05:47:31 PM PDT 24
Peak memory 191756 kb
Host smart-4c64ce66-6cac-49ec-b3a9-7c3655fc3cad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862369278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.862369278
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.2124911826
Short name T172
Test name
Test status
Simulation time 113607790746 ps
CPU time 43.16 seconds
Started Jul 23 05:34:12 PM PDT 24
Finished Jul 23 05:34:57 PM PDT 24
Peak memory 193496 kb
Host smart-2437d6c4-86bd-44c6-a51f-b63c9e453f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124911826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.2124911826
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.2506264383
Short name T15
Test name
Test status
Simulation time 89373398 ps
CPU time 0.91 seconds
Started Jul 23 05:34:15 PM PDT 24
Finished Jul 23 05:34:18 PM PDT 24
Peak memory 214980 kb
Host smart-b0e2a466-6d51-4543-9b06-0f1ce8713772
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506264383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.2506264383
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.1249593223
Short name T327
Test name
Test status
Simulation time 10262142138 ps
CPU time 15.15 seconds
Started Jul 23 05:35:34 PM PDT 24
Finished Jul 23 05:35:51 PM PDT 24
Peak memory 183372 kb
Host smart-a7116e52-1b1d-4d51-884b-fbf71a8f6d78
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249593223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.1249593223
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.916627370
Short name T371
Test name
Test status
Simulation time 43140999469 ps
CPU time 66.28 seconds
Started Jul 23 05:35:30 PM PDT 24
Finished Jul 23 05:36:37 PM PDT 24
Peak memory 183596 kb
Host smart-3b24f71e-bdd4-4d07-aa59-344dcf8b8c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916627370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.916627370
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.1787924992
Short name T206
Test name
Test status
Simulation time 397085603118 ps
CPU time 551.72 seconds
Started Jul 23 05:35:29 PM PDT 24
Finished Jul 23 05:44:41 PM PDT 24
Peak memory 191984 kb
Host smart-10ee3594-36dc-4c72-b0e2-cc1c801c33f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787924992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.1787924992
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.340536029
Short name T412
Test name
Test status
Simulation time 590157324925 ps
CPU time 320.56 seconds
Started Jul 23 05:35:37 PM PDT 24
Finished Jul 23 05:40:58 PM PDT 24
Peak memory 183584 kb
Host smart-2bad2cce-9634-4592-b03b-4850376d2cce
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340536029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.rv_timer_cfg_update_on_fly.340536029
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.2394195969
Short name T375
Test name
Test status
Simulation time 407577428037 ps
CPU time 98.03 seconds
Started Jul 23 05:35:37 PM PDT 24
Finished Jul 23 05:37:16 PM PDT 24
Peak memory 183528 kb
Host smart-6ebfbedd-a5ac-41d9-bdc6-843aa9f95901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394195969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.2394195969
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.1168853043
Short name T341
Test name
Test status
Simulation time 248524920118 ps
CPU time 174.61 seconds
Started Jul 23 05:35:37 PM PDT 24
Finished Jul 23 05:38:33 PM PDT 24
Peak memory 191776 kb
Host smart-ffb17ea9-4b12-4992-826c-ab33f7b6e673
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168853043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.1168853043
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.2159822616
Short name T332
Test name
Test status
Simulation time 31871353605 ps
CPU time 43.59 seconds
Started Jul 23 05:35:36 PM PDT 24
Finished Jul 23 05:36:21 PM PDT 24
Peak memory 191796 kb
Host smart-838aa5b7-d92c-4d15-914f-cb33c5ee4751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159822616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.2159822616
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.3496216992
Short name T137
Test name
Test status
Simulation time 1174652360921 ps
CPU time 1822.46 seconds
Started Jul 23 05:35:38 PM PDT 24
Finished Jul 23 06:06:02 PM PDT 24
Peak memory 191796 kb
Host smart-83147fdc-c75b-4847-b0bf-e6b5dd8baff5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496216992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.3496216992
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.2010481149
Short name T368
Test name
Test status
Simulation time 676508087031 ps
CPU time 164.71 seconds
Started Jul 23 05:35:43 PM PDT 24
Finished Jul 23 05:38:29 PM PDT 24
Peak memory 183584 kb
Host smart-50b561ee-f12b-4487-90bc-590341abfdb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010481149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.2010481149
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.828292776
Short name T176
Test name
Test status
Simulation time 50594926496 ps
CPU time 125.13 seconds
Started Jul 23 05:35:44 PM PDT 24
Finished Jul 23 05:37:50 PM PDT 24
Peak memory 194128 kb
Host smart-1322c34b-2c04-4b80-8d55-b355481578cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828292776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.828292776
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.1361700619
Short name T91
Test name
Test status
Simulation time 409108328731 ps
CPU time 205.48 seconds
Started Jul 23 05:35:54 PM PDT 24
Finished Jul 23 05:39:20 PM PDT 24
Peak memory 191796 kb
Host smart-5e9c5908-0140-47cc-87f4-0faff062e0fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361700619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.1361700619
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.3184598662
Short name T352
Test name
Test status
Simulation time 575133755940 ps
CPU time 317.73 seconds
Started Jul 23 05:36:01 PM PDT 24
Finished Jul 23 05:41:19 PM PDT 24
Peak memory 183548 kb
Host smart-5a5f72aa-ad32-4687-b82c-ac793768c5a0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184598662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.3184598662
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.2708438992
Short name T384
Test name
Test status
Simulation time 153553988048 ps
CPU time 61.61 seconds
Started Jul 23 05:36:01 PM PDT 24
Finished Jul 23 05:37:04 PM PDT 24
Peak memory 183488 kb
Host smart-4ab8d69e-13d8-483d-8519-ed5856a873b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708438992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.2708438992
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.4039200010
Short name T140
Test name
Test status
Simulation time 366430534239 ps
CPU time 195.57 seconds
Started Jul 23 05:36:01 PM PDT 24
Finished Jul 23 05:39:17 PM PDT 24
Peak memory 194208 kb
Host smart-0d0bf017-0853-4fdd-9010-0ee44d71bf75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039200010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.4039200010
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.679734281
Short name T425
Test name
Test status
Simulation time 71541681 ps
CPU time 0.67 seconds
Started Jul 23 05:36:01 PM PDT 24
Finished Jul 23 05:36:02 PM PDT 24
Peak memory 183332 kb
Host smart-9e85fbe2-d5e4-4bb7-85a1-4e7b400421b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679734281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.679734281
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.4208673863
Short name T403
Test name
Test status
Simulation time 91756591846 ps
CPU time 107.91 seconds
Started Jul 23 05:36:03 PM PDT 24
Finished Jul 23 05:37:51 PM PDT 24
Peak memory 183576 kb
Host smart-7eef9303-5517-4e95-82a9-a45e27546b84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208673863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.4208673863
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.2907307873
Short name T33
Test name
Test status
Simulation time 60910715215 ps
CPU time 130.96 seconds
Started Jul 23 05:36:00 PM PDT 24
Finished Jul 23 05:38:12 PM PDT 24
Peak memory 198144 kb
Host smart-56b4128c-52eb-4c3b-8c0e-d69a9c99f89b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907307873 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.2907307873
Directory /workspace/43.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.3802930328
Short name T10
Test name
Test status
Simulation time 130861883602 ps
CPU time 183.98 seconds
Started Jul 23 05:36:00 PM PDT 24
Finished Jul 23 05:39:05 PM PDT 24
Peak memory 183524 kb
Host smart-0ca6174f-889f-4ea7-a222-0dddcb637408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802930328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.3802930328
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.2197608665
Short name T313
Test name
Test status
Simulation time 29314311764 ps
CPU time 20.42 seconds
Started Jul 23 05:36:01 PM PDT 24
Finished Jul 23 05:36:22 PM PDT 24
Peak memory 183584 kb
Host smart-5c9679ec-ce8d-4197-9516-5a83c30a6faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197608665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.2197608665
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.4090478110
Short name T310
Test name
Test status
Simulation time 1229255041839 ps
CPU time 399.51 seconds
Started Jul 23 05:36:09 PM PDT 24
Finished Jul 23 05:42:49 PM PDT 24
Peak memory 183500 kb
Host smart-6403b96e-1cf7-434a-a900-7484848dc4c1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090478110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.4090478110
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.1179198171
Short name T411
Test name
Test status
Simulation time 85264906734 ps
CPU time 34.5 seconds
Started Jul 23 05:36:08 PM PDT 24
Finished Jul 23 05:36:43 PM PDT 24
Peak memory 183580 kb
Host smart-e23e54ba-41bb-40f5-bfe7-e7558e2f6549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179198171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.1179198171
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.1920698189
Short name T279
Test name
Test status
Simulation time 62375567605 ps
CPU time 947.83 seconds
Started Jul 23 05:36:02 PM PDT 24
Finished Jul 23 05:51:51 PM PDT 24
Peak memory 192272 kb
Host smart-71fb1363-902d-477a-9bb1-c58def08f6de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920698189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.1920698189
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.120682495
Short name T243
Test name
Test status
Simulation time 37278644520 ps
CPU time 61.5 seconds
Started Jul 23 05:36:07 PM PDT 24
Finished Jul 23 05:37:09 PM PDT 24
Peak memory 191688 kb
Host smart-9c788799-cbb3-4de4-a924-71d9217d8875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120682495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.120682495
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.4011193234
Short name T402
Test name
Test status
Simulation time 212007157897 ps
CPU time 577 seconds
Started Jul 23 05:36:09 PM PDT 24
Finished Jul 23 05:45:46 PM PDT 24
Peak memory 199484 kb
Host smart-12c95d09-7fd0-4a42-8f25-33410740ec5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011193234 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all_with_rand_reset.4011193234
Directory /workspace/45.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.1043388003
Short name T370
Test name
Test status
Simulation time 97781173128 ps
CPU time 118.43 seconds
Started Jul 23 05:36:10 PM PDT 24
Finished Jul 23 05:38:09 PM PDT 24
Peak memory 183572 kb
Host smart-3c98e519-7654-4d38-94e6-bba208f11481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043388003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.1043388003
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.3550515411
Short name T251
Test name
Test status
Simulation time 73794582664 ps
CPU time 106.02 seconds
Started Jul 23 05:36:08 PM PDT 24
Finished Jul 23 05:37:55 PM PDT 24
Peak memory 191756 kb
Host smart-89e80243-75cc-419f-bb8a-876e72444f2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550515411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.3550515411
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.182043303
Short name T160
Test name
Test status
Simulation time 64301105459 ps
CPU time 95.62 seconds
Started Jul 23 05:36:10 PM PDT 24
Finished Jul 23 05:37:46 PM PDT 24
Peak memory 183488 kb
Host smart-d5f95a08-dde2-47e5-9c37-dff2fc03700b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182043303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.182043303
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.4258311832
Short name T420
Test name
Test status
Simulation time 192887248145 ps
CPU time 299.12 seconds
Started Jul 23 05:36:09 PM PDT 24
Finished Jul 23 05:41:09 PM PDT 24
Peak memory 194976 kb
Host smart-17e177c0-01d6-4a4a-b855-04192e728cbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258311832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.4258311832
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all_with_rand_reset.1436437644
Short name T30
Test name
Test status
Simulation time 76384172283 ps
CPU time 344.65 seconds
Started Jul 23 05:36:08 PM PDT 24
Finished Jul 23 05:41:54 PM PDT 24
Peak memory 206468 kb
Host smart-cfb625b8-d434-4540-b231-db5d4c9d980c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436437644 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all_with_rand_reset.1436437644
Directory /workspace/46.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.4194068123
Short name T234
Test name
Test status
Simulation time 213255824408 ps
CPU time 57.03 seconds
Started Jul 23 05:36:17 PM PDT 24
Finished Jul 23 05:37:16 PM PDT 24
Peak memory 183420 kb
Host smart-992b160d-033e-4e60-893f-73e953566a8f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194068123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.4194068123
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.837431809
Short name T441
Test name
Test status
Simulation time 152893706233 ps
CPU time 240.71 seconds
Started Jul 23 05:36:17 PM PDT 24
Finished Jul 23 05:40:20 PM PDT 24
Peak memory 183548 kb
Host smart-ba94d5af-89df-4915-a3f6-6f82d312c6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837431809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.837431809
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.2430476821
Short name T302
Test name
Test status
Simulation time 88638247023 ps
CPU time 24.26 seconds
Started Jul 23 05:36:09 PM PDT 24
Finished Jul 23 05:36:34 PM PDT 24
Peak memory 183580 kb
Host smart-bed2004a-592e-42fe-b777-b3eefa527095
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430476821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.2430476821
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.732847322
Short name T414
Test name
Test status
Simulation time 133334310 ps
CPU time 0.55 seconds
Started Jul 23 05:36:19 PM PDT 24
Finished Jul 23 05:36:22 PM PDT 24
Peak memory 183364 kb
Host smart-e286ac98-9163-4431-82b9-d27e88a7ae10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732847322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.732847322
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.889588464
Short name T354
Test name
Test status
Simulation time 1984997714713 ps
CPU time 1103.16 seconds
Started Jul 23 05:36:18 PM PDT 24
Finished Jul 23 05:54:44 PM PDT 24
Peak memory 183576 kb
Host smart-7567df46-3836-4ff2-8b12-04455be35c14
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889588464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.rv_timer_cfg_update_on_fly.889588464
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.2542466080
Short name T427
Test name
Test status
Simulation time 25501836644 ps
CPU time 37.08 seconds
Started Jul 23 05:36:17 PM PDT 24
Finished Jul 23 05:36:56 PM PDT 24
Peak memory 183568 kb
Host smart-2559045e-08d3-49ea-ad77-84e414d04e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542466080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.2542466080
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.2903530937
Short name T309
Test name
Test status
Simulation time 46358035387 ps
CPU time 29.72 seconds
Started Jul 23 05:36:19 PM PDT 24
Finished Jul 23 05:36:51 PM PDT 24
Peak memory 183584 kb
Host smart-0d0a6cc1-a4a8-4526-b0dd-4b45f110b214
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903530937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.2903530937
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.2810724826
Short name T423
Test name
Test status
Simulation time 139948039 ps
CPU time 0.57 seconds
Started Jul 23 05:36:19 PM PDT 24
Finished Jul 23 05:36:22 PM PDT 24
Peak memory 183380 kb
Host smart-749fec25-72e8-4faf-947d-fb2ff798aca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810724826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.2810724826
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.3861657711
Short name T170
Test name
Test status
Simulation time 237758969926 ps
CPU time 358.93 seconds
Started Jul 23 05:36:25 PM PDT 24
Finished Jul 23 05:42:25 PM PDT 24
Peak memory 183564 kb
Host smart-2e6baa11-abad-4e2c-9118-811089d650ab
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861657711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.3861657711
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.1931000725
Short name T381
Test name
Test status
Simulation time 209428246013 ps
CPU time 100.44 seconds
Started Jul 23 05:36:24 PM PDT 24
Finished Jul 23 05:38:06 PM PDT 24
Peak memory 183588 kb
Host smart-715f0fe2-b4ed-4be0-9b28-332e814aef0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931000725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.1931000725
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.1849678897
Short name T349
Test name
Test status
Simulation time 179806977294 ps
CPU time 135.91 seconds
Started Jul 23 05:36:26 PM PDT 24
Finished Jul 23 05:38:44 PM PDT 24
Peak memory 183572 kb
Host smart-6b47dd08-9f75-4e63-82a7-28a61b14c638
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849678897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.1849678897
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.2442871748
Short name T112
Test name
Test status
Simulation time 112253972127 ps
CPU time 76.87 seconds
Started Jul 23 05:36:24 PM PDT 24
Finished Jul 23 05:37:42 PM PDT 24
Peak memory 191756 kb
Host smart-cf73653e-7b7f-4464-a002-60366cbb48f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442871748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.2442871748
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.2909954139
Short name T54
Test name
Test status
Simulation time 499632711747 ps
CPU time 1421.66 seconds
Started Jul 23 05:36:26 PM PDT 24
Finished Jul 23 06:00:09 PM PDT 24
Peak memory 191748 kb
Host smart-1bed2fab-277e-4002-a518-892d2493ec2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909954139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.2909954139
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.1052085866
Short name T6
Test name
Test status
Simulation time 57161368017 ps
CPU time 28.76 seconds
Started Jul 23 05:34:14 PM PDT 24
Finished Jul 23 05:34:44 PM PDT 24
Peak memory 183592 kb
Host smart-48e58d9f-79c2-4ca5-b205-5b4985eea3db
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052085866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.1052085866
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.4008227697
Short name T388
Test name
Test status
Simulation time 577049011790 ps
CPU time 169.64 seconds
Started Jul 23 05:34:16 PM PDT 24
Finished Jul 23 05:37:08 PM PDT 24
Peak memory 183452 kb
Host smart-79f19f68-a85b-49be-8637-9ddebb6beadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008227697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.4008227697
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.3139883148
Short name T451
Test name
Test status
Simulation time 698527169402 ps
CPU time 918.14 seconds
Started Jul 23 05:34:14 PM PDT 24
Finished Jul 23 05:49:34 PM PDT 24
Peak memory 191788 kb
Host smart-1b848d07-7793-4e90-906f-5b94ab957011
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139883148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.3139883148
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.2201879865
Short name T360
Test name
Test status
Simulation time 37933232081 ps
CPU time 136.28 seconds
Started Jul 23 05:34:12 PM PDT 24
Finished Jul 23 05:36:30 PM PDT 24
Peak memory 183584 kb
Host smart-edd1b97a-dfda-4a57-983a-1a48d058b79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201879865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.2201879865
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.1714106703
Short name T278
Test name
Test status
Simulation time 6171348311473 ps
CPU time 1557.16 seconds
Started Jul 23 05:34:12 PM PDT 24
Finished Jul 23 06:00:10 PM PDT 24
Peak memory 191736 kb
Host smart-7dade967-8266-46f7-82bc-ec7dabb7cdb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714106703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
1714106703
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/50.rv_timer_random.1061758681
Short name T406
Test name
Test status
Simulation time 39799972091 ps
CPU time 201.46 seconds
Started Jul 23 05:36:25 PM PDT 24
Finished Jul 23 05:39:49 PM PDT 24
Peak memory 183580 kb
Host smart-238fe39d-309e-4c64-a443-d826f0223e5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061758681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.1061758681
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.572558734
Short name T300
Test name
Test status
Simulation time 106403647116 ps
CPU time 90.02 seconds
Started Jul 23 05:36:26 PM PDT 24
Finished Jul 23 05:37:58 PM PDT 24
Peak memory 191784 kb
Host smart-23a3be59-4cc3-4abb-b61e-94a19bbf9f62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572558734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.572558734
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.1771574
Short name T290
Test name
Test status
Simulation time 61854257468 ps
CPU time 20.32 seconds
Started Jul 23 05:36:25 PM PDT 24
Finished Jul 23 05:36:48 PM PDT 24
Peak memory 183568 kb
Host smart-c0b28ed1-91fd-4be2-9662-33133c188738
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.1771574
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.3932069630
Short name T316
Test name
Test status
Simulation time 84575109948 ps
CPU time 116.36 seconds
Started Jul 23 05:36:26 PM PDT 24
Finished Jul 23 05:38:24 PM PDT 24
Peak memory 183588 kb
Host smart-56898ba8-546d-4989-9ceb-86f345233558
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932069630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.3932069630
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.1726932761
Short name T361
Test name
Test status
Simulation time 1019648727060 ps
CPU time 1794.4 seconds
Started Jul 23 05:36:26 PM PDT 24
Finished Jul 23 06:06:22 PM PDT 24
Peak memory 191772 kb
Host smart-1fe53e1a-4425-4f0e-b190-af8ec72dd642
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726932761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.1726932761
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.3919364048
Short name T356
Test name
Test status
Simulation time 78559961157 ps
CPU time 116.66 seconds
Started Jul 23 05:36:34 PM PDT 24
Finished Jul 23 05:38:32 PM PDT 24
Peak memory 191728 kb
Host smart-856bcac4-f488-496e-a651-cdd98e3adee3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919364048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.3919364048
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.281564409
Short name T134
Test name
Test status
Simulation time 80245662732 ps
CPU time 306.87 seconds
Started Jul 23 05:36:33 PM PDT 24
Finished Jul 23 05:41:41 PM PDT 24
Peak memory 191760 kb
Host smart-1ac2dcd0-1cda-4a2f-9a17-fed636dc7254
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281564409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.281564409
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.3039088775
Short name T123
Test name
Test status
Simulation time 29133709487 ps
CPU time 59.38 seconds
Started Jul 23 05:36:35 PM PDT 24
Finished Jul 23 05:37:35 PM PDT 24
Peak memory 183576 kb
Host smart-6b1253fe-c2df-489d-bec8-13556202a520
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039088775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.3039088775
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.3728537723
Short name T164
Test name
Test status
Simulation time 1928456259918 ps
CPU time 966.13 seconds
Started Jul 23 05:34:12 PM PDT 24
Finished Jul 23 05:50:19 PM PDT 24
Peak memory 183548 kb
Host smart-d7dd71a0-a444-459b-a86a-50d0fa573045
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728537723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.3728537723
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.581477114
Short name T391
Test name
Test status
Simulation time 49045790653 ps
CPU time 69.98 seconds
Started Jul 23 05:34:13 PM PDT 24
Finished Jul 23 05:35:24 PM PDT 24
Peak memory 183500 kb
Host smart-ddddf2c5-6596-49f3-8142-2a7b83700c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581477114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.581477114
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.659277969
Short name T125
Test name
Test status
Simulation time 113978351109 ps
CPU time 370.55 seconds
Started Jul 23 05:34:12 PM PDT 24
Finished Jul 23 05:40:23 PM PDT 24
Peak memory 191768 kb
Host smart-bc2d570a-28bd-41f2-b0a4-956200215149
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659277969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.659277969
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.3047413777
Short name T143
Test name
Test status
Simulation time 330475109590 ps
CPU time 482.31 seconds
Started Jul 23 05:34:13 PM PDT 24
Finished Jul 23 05:42:17 PM PDT 24
Peak memory 191740 kb
Host smart-f1def0bb-46b2-45b5-9651-94fbe5f868ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047413777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.3047413777
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.2004320359
Short name T401
Test name
Test status
Simulation time 87039683547 ps
CPU time 122.52 seconds
Started Jul 23 05:34:14 PM PDT 24
Finished Jul 23 05:36:18 PM PDT 24
Peak memory 183544 kb
Host smart-d6b47c52-912e-4932-be16-2bf6822aeb26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004320359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
2004320359
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/60.rv_timer_random.482678667
Short name T20
Test name
Test status
Simulation time 121599683733 ps
CPU time 302.12 seconds
Started Jul 23 05:36:35 PM PDT 24
Finished Jul 23 05:41:38 PM PDT 24
Peak memory 191796 kb
Host smart-0ce78ed5-7aad-4bfd-b3a2-f5207d3fe853
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482678667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.482678667
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.2121966144
Short name T239
Test name
Test status
Simulation time 412557551460 ps
CPU time 2886.46 seconds
Started Jul 23 05:36:34 PM PDT 24
Finished Jul 23 06:24:42 PM PDT 24
Peak memory 191776 kb
Host smart-add70787-3773-46ee-8683-627d150e8a1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121966144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.2121966144
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.4651718
Short name T413
Test name
Test status
Simulation time 183551091947 ps
CPU time 175.51 seconds
Started Jul 23 05:36:34 PM PDT 24
Finished Jul 23 05:39:30 PM PDT 24
Peak memory 191740 kb
Host smart-59f88c98-8299-4f9b-bb72-f6234501b250
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4651718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.4651718
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.3625559840
Short name T195
Test name
Test status
Simulation time 126056886774 ps
CPU time 118.61 seconds
Started Jul 23 05:36:35 PM PDT 24
Finished Jul 23 05:38:34 PM PDT 24
Peak memory 191800 kb
Host smart-ba9481a2-6d06-47fc-8da7-d280bd2f13a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625559840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.3625559840
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.1203068530
Short name T431
Test name
Test status
Simulation time 4934677894 ps
CPU time 18.47 seconds
Started Jul 23 05:36:34 PM PDT 24
Finished Jul 23 05:36:53 PM PDT 24
Peak memory 183544 kb
Host smart-6bcbd2da-f87e-46fe-999f-3a65e465148f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203068530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.1203068530
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.3983470681
Short name T299
Test name
Test status
Simulation time 118888335493 ps
CPU time 1355.82 seconds
Started Jul 23 05:36:35 PM PDT 24
Finished Jul 23 05:59:12 PM PDT 24
Peak memory 191744 kb
Host smart-0909aa9c-80a3-4f48-8d4e-8ef063cefa72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983470681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.3983470681
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.3875172524
Short name T249
Test name
Test status
Simulation time 52198675571 ps
CPU time 83.64 seconds
Started Jul 23 05:36:33 PM PDT 24
Finished Jul 23 05:37:57 PM PDT 24
Peak memory 191640 kb
Host smart-61cad961-be5e-4c50-8e3d-fd21580e1ce1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875172524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.3875172524
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.2396783287
Short name T339
Test name
Test status
Simulation time 256643442820 ps
CPU time 608.56 seconds
Started Jul 23 05:36:42 PM PDT 24
Finished Jul 23 05:46:51 PM PDT 24
Peak memory 191792 kb
Host smart-a81ded51-992e-4474-8de7-38e500895a18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396783287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.2396783287
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.1720926400
Short name T263
Test name
Test status
Simulation time 227211114058 ps
CPU time 339.32 seconds
Started Jul 23 05:34:14 PM PDT 24
Finished Jul 23 05:39:55 PM PDT 24
Peak memory 183532 kb
Host smart-558f1f00-6389-484d-b21f-79d9f8b83c2d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720926400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.1720926400
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.690151563
Short name T386
Test name
Test status
Simulation time 160762935904 ps
CPU time 206.05 seconds
Started Jul 23 05:34:14 PM PDT 24
Finished Jul 23 05:37:41 PM PDT 24
Peak memory 183532 kb
Host smart-8d50bb8a-7a1b-4056-a319-c8790f34498e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690151563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.690151563
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.1372267952
Short name T24
Test name
Test status
Simulation time 308735071599 ps
CPU time 527.54 seconds
Started Jul 23 05:34:15 PM PDT 24
Finished Jul 23 05:43:04 PM PDT 24
Peak memory 191740 kb
Host smart-d4e5fdd4-e8ce-48ba-90e8-d3f05f0737c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372267952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.1372267952
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.1209485520
Short name T304
Test name
Test status
Simulation time 13584116641 ps
CPU time 17.49 seconds
Started Jul 23 05:34:14 PM PDT 24
Finished Jul 23 05:34:33 PM PDT 24
Peak memory 183356 kb
Host smart-25fd08bb-9018-49d4-bd6a-f8b21b842052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209485520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.1209485520
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.3557209468
Short name T210
Test name
Test status
Simulation time 2025505123528 ps
CPU time 1301.94 seconds
Started Jul 23 05:34:20 PM PDT 24
Finished Jul 23 05:56:03 PM PDT 24
Peak memory 191764 kb
Host smart-c4def9f0-f5ce-4dc3-9db5-56334a21d531
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557209468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
3557209468
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/72.rv_timer_random.2015997951
Short name T419
Test name
Test status
Simulation time 88604286713 ps
CPU time 140.97 seconds
Started Jul 23 05:36:41 PM PDT 24
Finished Jul 23 05:39:03 PM PDT 24
Peak memory 191776 kb
Host smart-f5d48b53-6b61-4445-a487-9b1f5f7c1ef8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015997951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.2015997951
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.1964813836
Short name T218
Test name
Test status
Simulation time 55385117776 ps
CPU time 105.25 seconds
Started Jul 23 05:36:43 PM PDT 24
Finished Jul 23 05:38:29 PM PDT 24
Peak memory 191772 kb
Host smart-381a6f6c-788d-42ca-b8be-f8500a727461
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964813836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.1964813836
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.1415389668
Short name T257
Test name
Test status
Simulation time 178435532512 ps
CPU time 216.37 seconds
Started Jul 23 05:36:42 PM PDT 24
Finished Jul 23 05:40:19 PM PDT 24
Peak memory 191756 kb
Host smart-64bb52eb-5556-4fa4-b39f-d6a90fd505b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415389668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.1415389668
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.3147133393
Short name T417
Test name
Test status
Simulation time 52887195028 ps
CPU time 43.77 seconds
Started Jul 23 05:36:44 PM PDT 24
Finished Jul 23 05:37:28 PM PDT 24
Peak memory 183576 kb
Host smart-a66061e0-fe78-4066-947f-abecbcf7b4ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147133393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.3147133393
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.2150844601
Short name T330
Test name
Test status
Simulation time 952959381486 ps
CPU time 1598.98 seconds
Started Jul 23 05:36:45 PM PDT 24
Finished Jul 23 06:03:25 PM PDT 24
Peak memory 191672 kb
Host smart-ecd9cda0-8fcc-457a-8d61-031433235ac2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150844601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.2150844601
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.3991399897
Short name T322
Test name
Test status
Simulation time 185383227906 ps
CPU time 99.91 seconds
Started Jul 23 05:34:27 PM PDT 24
Finished Jul 23 05:36:07 PM PDT 24
Peak memory 183584 kb
Host smart-b23b0d6c-d176-472c-aa90-20ed95fca648
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991399897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.3991399897
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.1156443653
Short name T434
Test name
Test status
Simulation time 14440044208 ps
CPU time 20.01 seconds
Started Jul 23 05:34:22 PM PDT 24
Finished Jul 23 05:34:43 PM PDT 24
Peak memory 183540 kb
Host smart-15be8322-166d-4164-b69e-46c2e7fcfd08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156443653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.1156443653
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.2779656924
Short name T321
Test name
Test status
Simulation time 114381287045 ps
CPU time 162.07 seconds
Started Jul 23 05:34:25 PM PDT 24
Finished Jul 23 05:37:08 PM PDT 24
Peak memory 191812 kb
Host smart-0dab206f-79a8-4025-8a98-2b489222dfcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779656924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.2779656924
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.2037113220
Short name T217
Test name
Test status
Simulation time 2389017099876 ps
CPU time 1721.5 seconds
Started Jul 23 05:34:23 PM PDT 24
Finished Jul 23 06:03:05 PM PDT 24
Peak memory 191752 kb
Host smart-c7107a5d-4953-4378-a0e7-fac23d1a0b9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037113220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
2037113220
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/80.rv_timer_random.3255463717
Short name T286
Test name
Test status
Simulation time 632632649685 ps
CPU time 370.45 seconds
Started Jul 23 05:36:50 PM PDT 24
Finished Jul 23 05:43:02 PM PDT 24
Peak memory 191636 kb
Host smart-ce26e63e-fa86-46fc-aaa8-9328ba9bb0aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255463717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.3255463717
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.2805375029
Short name T396
Test name
Test status
Simulation time 166339941568 ps
CPU time 91.01 seconds
Started Jul 23 05:36:52 PM PDT 24
Finished Jul 23 05:38:24 PM PDT 24
Peak memory 183600 kb
Host smart-7bdb2ca9-d65a-4107-9710-dd6649750003
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805375029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.2805375029
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.3916064081
Short name T203
Test name
Test status
Simulation time 153649976204 ps
CPU time 158.53 seconds
Started Jul 23 05:36:52 PM PDT 24
Finished Jul 23 05:39:32 PM PDT 24
Peak memory 191728 kb
Host smart-6eb94804-07e4-46d9-9ad5-c6e794dddab5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916064081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.3916064081
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.2798133631
Short name T224
Test name
Test status
Simulation time 113647563764 ps
CPU time 403.45 seconds
Started Jul 23 05:36:50 PM PDT 24
Finished Jul 23 05:43:35 PM PDT 24
Peak memory 191768 kb
Host smart-5744b9b2-ee43-4f57-839e-7345d4c63805
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798133631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.2798133631
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.2090170665
Short name T159
Test name
Test status
Simulation time 897822790994 ps
CPU time 519.21 seconds
Started Jul 23 05:36:50 PM PDT 24
Finished Jul 23 05:45:30 PM PDT 24
Peak memory 191732 kb
Host smart-f10d27da-7054-424d-964a-a598cbd22ed7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090170665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.2090170665
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.2364312261
Short name T337
Test name
Test status
Simulation time 159182383318 ps
CPU time 128.9 seconds
Started Jul 23 05:36:51 PM PDT 24
Finished Jul 23 05:39:00 PM PDT 24
Peak memory 191776 kb
Host smart-e5b406ef-4948-4b84-8c24-b3a3df3bf9ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364312261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.2364312261
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.760182592
Short name T268
Test name
Test status
Simulation time 316793598395 ps
CPU time 288 seconds
Started Jul 23 05:34:25 PM PDT 24
Finished Jul 23 05:39:14 PM PDT 24
Peak memory 183572 kb
Host smart-cbd174e9-05af-45da-a8de-eb2634836885
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760182592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.rv_timer_cfg_update_on_fly.760182592
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.1646035784
Short name T378
Test name
Test status
Simulation time 62070222030 ps
CPU time 17.25 seconds
Started Jul 23 05:34:25 PM PDT 24
Finished Jul 23 05:34:43 PM PDT 24
Peak memory 183576 kb
Host smart-6055c3c9-7a89-4fd6-9645-68b655b0b4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646035784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.1646035784
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.98998040
Short name T212
Test name
Test status
Simulation time 130541229371 ps
CPU time 64.36 seconds
Started Jul 23 05:34:27 PM PDT 24
Finished Jul 23 05:35:32 PM PDT 24
Peak memory 183576 kb
Host smart-5ad37cc9-84f4-49ec-8cec-3a71a83bb679
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98998040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.98998040
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.3864239923
Short name T248
Test name
Test status
Simulation time 53569076351 ps
CPU time 86.09 seconds
Started Jul 23 05:34:25 PM PDT 24
Finished Jul 23 05:35:52 PM PDT 24
Peak memory 191752 kb
Host smart-54e96dea-306c-4df0-b478-15233b850de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864239923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.3864239923
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.2303918820
Short name T49
Test name
Test status
Simulation time 249320169112 ps
CPU time 373.58 seconds
Started Jul 23 05:34:23 PM PDT 24
Finished Jul 23 05:40:38 PM PDT 24
Peak memory 196188 kb
Host smart-4474a839-9077-4505-ab0b-14f1f3506045
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303918820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
2303918820
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/90.rv_timer_random.1383013168
Short name T109
Test name
Test status
Simulation time 87456451720 ps
CPU time 113.52 seconds
Started Jul 23 05:36:50 PM PDT 24
Finished Jul 23 05:38:45 PM PDT 24
Peak memory 191796 kb
Host smart-1422bbe3-62e0-414d-b61a-9a2279569e89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383013168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.1383013168
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.793742923
Short name T165
Test name
Test status
Simulation time 82302319940 ps
CPU time 62.19 seconds
Started Jul 23 05:36:48 PM PDT 24
Finished Jul 23 05:37:51 PM PDT 24
Peak memory 191724 kb
Host smart-34d546e8-2cbc-41e1-94fb-2a09390fddae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793742923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.793742923
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.3359544294
Short name T446
Test name
Test status
Simulation time 66682628020 ps
CPU time 629.69 seconds
Started Jul 23 05:36:53 PM PDT 24
Finished Jul 23 05:47:23 PM PDT 24
Peak memory 183576 kb
Host smart-a1616e15-47fb-4046-942d-f1110fccf215
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359544294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.3359544294
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.1047724795
Short name T190
Test name
Test status
Simulation time 1666949587841 ps
CPU time 467.25 seconds
Started Jul 23 05:37:00 PM PDT 24
Finished Jul 23 05:44:48 PM PDT 24
Peak memory 191752 kb
Host smart-37155258-6597-4d1b-85e8-57a477dfe177
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047724795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.1047724795
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.1723752279
Short name T270
Test name
Test status
Simulation time 97239263300 ps
CPU time 197.4 seconds
Started Jul 23 05:37:00 PM PDT 24
Finished Jul 23 05:40:18 PM PDT 24
Peak memory 191780 kb
Host smart-5ceb75b6-ed3d-4684-9ee6-96e8d42eec94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723752279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.1723752279
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.182122137
Short name T154
Test name
Test status
Simulation time 153199389794 ps
CPU time 706.9 seconds
Started Jul 23 05:37:00 PM PDT 24
Finished Jul 23 05:48:48 PM PDT 24
Peak memory 194332 kb
Host smart-8694f430-c053-46b0-878c-5fe4a0b40916
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182122137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.182122137
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.4181910436
Short name T329
Test name
Test status
Simulation time 1712673058939 ps
CPU time 1522.61 seconds
Started Jul 23 05:37:00 PM PDT 24
Finished Jul 23 06:02:24 PM PDT 24
Peak memory 191764 kb
Host smart-1eaf66a6-8087-4184-bf1c-daae1d1cd27e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181910436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.4181910436
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.1426709477
Short name T128
Test name
Test status
Simulation time 27857442482 ps
CPU time 24.67 seconds
Started Jul 23 05:37:02 PM PDT 24
Finished Jul 23 05:37:27 PM PDT 24
Peak memory 183576 kb
Host smart-ec960dcd-794b-435d-b64c-e136f4666455
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426709477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.1426709477
Directory /workspace/99.rv_timer_random/latest
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