Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
141040162 |
1 |
|
T1 |
29829 |
|
T2 |
99481 |
|
T3 |
34278 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
63923501 |
1 |
|
T1 |
19728 |
|
T2 |
99481 |
|
T3 |
30175 |
auto[1] |
77116661 |
1 |
|
T1 |
10101 |
|
T3 |
4103 |
|
T4 |
17430 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
141034359 |
1 |
|
T1 |
29818 |
|
T2 |
99477 |
|
T3 |
34274 |
auto[1] |
5803 |
1 |
|
T1 |
11 |
|
T2 |
4 |
|
T3 |
4 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for intr_cg_cc
Bins
cp_intr | cp_intr_en | cp_intr_state | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
63920596 |
1 |
|
T1 |
19725 |
|
T2 |
99477 |
|
T3 |
30173 |
all_values[0] |
auto[0] |
auto[1] |
2905 |
1 |
|
T1 |
3 |
|
T2 |
4 |
|
T3 |
2 |
all_values[0] |
auto[1] |
auto[0] |
77113763 |
1 |
|
T1 |
10093 |
|
T3 |
4101 |
|
T4 |
17428 |
all_values[0] |
auto[1] |
auto[1] |
2898 |
1 |
|
T1 |
8 |
|
T3 |
2 |
|
T4 |
2 |