Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.62 99.36 98.73 100.00 100.00 100.00 99.66


Total test records in report: 583
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T507 /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.492145562 Jul 24 04:21:18 PM PDT 24 Jul 24 04:21:20 PM PDT 24 363665405 ps
T508 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.3250145946 Jul 24 04:24:28 PM PDT 24 Jul 24 04:24:29 PM PDT 24 12230307 ps
T509 /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.897906301 Jul 24 04:25:05 PM PDT 24 Jul 24 04:25:07 PM PDT 24 26470922 ps
T105 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1461541164 Jul 24 04:23:41 PM PDT 24 Jul 24 04:23:42 PM PDT 24 56235787 ps
T510 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3296107179 Jul 24 04:22:19 PM PDT 24 Jul 24 04:22:20 PM PDT 24 27543170 ps
T511 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.1202976944 Jul 24 04:25:03 PM PDT 24 Jul 24 04:25:05 PM PDT 24 104961621 ps
T512 /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.149911311 Jul 24 04:25:27 PM PDT 24 Jul 24 04:25:29 PM PDT 24 44143443 ps
T115 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.636376966 Jul 24 04:25:46 PM PDT 24 Jul 24 04:25:48 PM PDT 24 219837802 ps
T513 /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1518784242 Jul 24 04:25:20 PM PDT 24 Jul 24 04:25:21 PM PDT 24 18046506 ps
T514 /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3282006034 Jul 24 04:25:30 PM PDT 24 Jul 24 04:25:32 PM PDT 24 21551316 ps
T515 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.1231328347 Jul 24 04:25:50 PM PDT 24 Jul 24 04:25:51 PM PDT 24 16397872 ps
T516 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.83956422 Jul 24 04:25:21 PM PDT 24 Jul 24 04:25:22 PM PDT 24 28237495 ps
T517 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.3947013076 Jul 24 04:25:55 PM PDT 24 Jul 24 04:25:56 PM PDT 24 13931577 ps
T518 /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1753055624 Jul 24 04:25:25 PM PDT 24 Jul 24 04:25:26 PM PDT 24 51211858 ps
T519 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.363408409 Jul 24 04:25:25 PM PDT 24 Jul 24 04:25:26 PM PDT 24 23161383 ps
T520 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.817786095 Jul 24 04:21:35 PM PDT 24 Jul 24 04:21:38 PM PDT 24 480631120 ps
T521 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.1386893764 Jul 24 04:25:31 PM PDT 24 Jul 24 04:25:34 PM PDT 24 55401745 ps
T522 /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.2393680242 Jul 24 04:25:38 PM PDT 24 Jul 24 04:25:40 PM PDT 24 56034843 ps
T523 /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.3805153063 Jul 24 04:25:09 PM PDT 24 Jul 24 04:25:10 PM PDT 24 22502873 ps
T524 /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.604078601 Jul 24 04:25:47 PM PDT 24 Jul 24 04:25:49 PM PDT 24 65795483 ps
T525 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.2792449486 Jul 24 04:25:41 PM PDT 24 Jul 24 04:25:43 PM PDT 24 16541310 ps
T526 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1116522933 Jul 24 04:25:21 PM PDT 24 Jul 24 04:25:22 PM PDT 24 48864866 ps
T527 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.3616015551 Jul 24 04:23:52 PM PDT 24 Jul 24 04:23:52 PM PDT 24 41215663 ps
T528 /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3142222563 Jul 24 04:25:40 PM PDT 24 Jul 24 04:25:41 PM PDT 24 65398689 ps
T529 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.480190792 Jul 24 04:25:42 PM PDT 24 Jul 24 04:25:43 PM PDT 24 14262971 ps
T530 /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.469077591 Jul 24 04:21:52 PM PDT 24 Jul 24 04:21:53 PM PDT 24 21350209 ps
T531 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.2690459196 Jul 24 04:25:20 PM PDT 24 Jul 24 04:25:21 PM PDT 24 83785116 ps
T106 /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.2098602639 Jul 24 04:25:55 PM PDT 24 Jul 24 04:25:56 PM PDT 24 11856573 ps
T532 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.3806939430 Jul 24 04:21:09 PM PDT 24 Jul 24 04:21:11 PM PDT 24 101896010 ps
T533 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.4125601177 Jul 24 04:25:49 PM PDT 24 Jul 24 04:25:50 PM PDT 24 24295443 ps
T534 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.2948816630 Jul 24 04:21:48 PM PDT 24 Jul 24 04:21:49 PM PDT 24 33084060 ps
T535 /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.2586318014 Jul 24 04:25:48 PM PDT 24 Jul 24 04:25:49 PM PDT 24 27203379 ps
T536 /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2606574402 Jul 24 04:25:46 PM PDT 24 Jul 24 04:25:47 PM PDT 24 191801125 ps
T537 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.2017942069 Jul 24 04:21:58 PM PDT 24 Jul 24 04:21:59 PM PDT 24 13431515 ps
T538 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3036384432 Jul 24 04:25:26 PM PDT 24 Jul 24 04:25:27 PM PDT 24 12115329 ps
T539 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.3475398790 Jul 24 04:23:41 PM PDT 24 Jul 24 04:23:43 PM PDT 24 58609000 ps
T540 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.4242097894 Jul 24 04:21:43 PM PDT 24 Jul 24 04:21:44 PM PDT 24 141075068 ps
T541 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.2927532624 Jul 24 04:25:44 PM PDT 24 Jul 24 04:25:45 PM PDT 24 72323528 ps
T542 /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.1007232396 Jul 24 04:25:31 PM PDT 24 Jul 24 04:25:32 PM PDT 24 30596143 ps
T107 /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.397270980 Jul 24 04:23:20 PM PDT 24 Jul 24 04:23:21 PM PDT 24 36535595 ps
T543 /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3956537464 Jul 24 04:21:12 PM PDT 24 Jul 24 04:21:13 PM PDT 24 16985609 ps
T544 /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.4019755014 Jul 24 04:25:41 PM PDT 24 Jul 24 04:25:44 PM PDT 24 144528290 ps
T545 /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.289608022 Jul 24 04:22:24 PM PDT 24 Jul 24 04:22:26 PM PDT 24 155409060 ps
T546 /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.1566245329 Jul 24 04:25:49 PM PDT 24 Jul 24 04:25:50 PM PDT 24 39895121 ps
T547 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.807676518 Jul 24 04:25:28 PM PDT 24 Jul 24 04:25:30 PM PDT 24 181813682 ps
T548 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.2603368553 Jul 24 04:22:30 PM PDT 24 Jul 24 04:22:31 PM PDT 24 40144168 ps
T549 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.2327647527 Jul 24 04:22:32 PM PDT 24 Jul 24 04:22:33 PM PDT 24 17612443 ps
T550 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.4220207603 Jul 24 04:24:02 PM PDT 24 Jul 24 04:24:04 PM PDT 24 391312073 ps
T551 /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.4281802180 Jul 24 04:25:21 PM PDT 24 Jul 24 04:25:23 PM PDT 24 90013584 ps
T552 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3271084484 Jul 24 04:25:41 PM PDT 24 Jul 24 04:25:42 PM PDT 24 13354150 ps
T553 /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.4091810398 Jul 24 04:24:18 PM PDT 24 Jul 24 04:24:20 PM PDT 24 35552698 ps
T554 /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.3095371579 Jul 24 04:21:59 PM PDT 24 Jul 24 04:22:00 PM PDT 24 52003882 ps
T555 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.2173415247 Jul 24 04:25:48 PM PDT 24 Jul 24 04:25:49 PM PDT 24 16278379 ps
T556 /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.885681607 Jul 24 04:23:41 PM PDT 24 Jul 24 04:23:42 PM PDT 24 145554945 ps
T557 /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.2125060042 Jul 24 04:24:02 PM PDT 24 Jul 24 04:24:03 PM PDT 24 95246539 ps
T558 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.2168704539 Jul 24 04:25:10 PM PDT 24 Jul 24 04:25:11 PM PDT 24 35874693 ps
T559 /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.2858783092 Jul 24 04:25:36 PM PDT 24 Jul 24 04:25:37 PM PDT 24 15716549 ps
T560 /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.1159978295 Jul 24 04:22:48 PM PDT 24 Jul 24 04:22:49 PM PDT 24 147289330 ps
T561 /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2244293148 Jul 24 04:25:30 PM PDT 24 Jul 24 04:25:32 PM PDT 24 109162350 ps
T562 /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3555403115 Jul 24 04:25:19 PM PDT 24 Jul 24 04:25:21 PM PDT 24 133385844 ps
T108 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.852342687 Jul 24 04:22:19 PM PDT 24 Jul 24 04:22:20 PM PDT 24 13997543 ps
T563 /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.4122881520 Jul 24 04:25:52 PM PDT 24 Jul 24 04:25:53 PM PDT 24 72910771 ps
T564 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1749279937 Jul 24 04:25:41 PM PDT 24 Jul 24 04:25:44 PM PDT 24 359315318 ps
T565 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.2117401387 Jul 24 04:25:20 PM PDT 24 Jul 24 04:25:21 PM PDT 24 26704352 ps
T566 /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.3106280437 Jul 24 04:25:21 PM PDT 24 Jul 24 04:25:23 PM PDT 24 120372508 ps
T109 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.616211376 Jul 24 04:22:02 PM PDT 24 Jul 24 04:22:06 PM PDT 24 182071422 ps
T567 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.154557782 Jul 24 04:25:41 PM PDT 24 Jul 24 04:25:44 PM PDT 24 36203477 ps
T568 /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.4256489201 Jul 24 04:25:45 PM PDT 24 Jul 24 04:25:49 PM PDT 24 131379717 ps
T569 /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.775095717 Jul 24 04:23:09 PM PDT 24 Jul 24 04:23:10 PM PDT 24 30554554 ps
T570 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2376290326 Jul 24 04:25:42 PM PDT 24 Jul 24 04:25:43 PM PDT 24 103941859 ps
T571 /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.2659380821 Jul 24 04:22:35 PM PDT 24 Jul 24 04:22:35 PM PDT 24 12931751 ps
T572 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.3704584631 Jul 24 04:22:04 PM PDT 24 Jul 24 04:22:06 PM PDT 24 654707644 ps
T573 /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.2433269595 Jul 24 04:22:32 PM PDT 24 Jul 24 04:22:34 PM PDT 24 25293078 ps
T574 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3885656182 Jul 24 04:21:12 PM PDT 24 Jul 24 04:21:13 PM PDT 24 94803781 ps
T575 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3663586030 Jul 24 04:25:41 PM PDT 24 Jul 24 04:25:42 PM PDT 24 11544105 ps
T576 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.960535017 Jul 24 04:25:46 PM PDT 24 Jul 24 04:25:49 PM PDT 24 582210706 ps
T577 /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.4097411564 Jul 24 04:21:52 PM PDT 24 Jul 24 04:21:52 PM PDT 24 39461144 ps
T578 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.3631347569 Jul 24 04:25:09 PM PDT 24 Jul 24 04:25:10 PM PDT 24 37906532 ps
T579 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.2439320730 Jul 24 04:21:58 PM PDT 24 Jul 24 04:21:59 PM PDT 24 20582728 ps
T580 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.2884391801 Jul 24 04:24:09 PM PDT 24 Jul 24 04:24:10 PM PDT 24 28395437 ps
T581 /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.3016017820 Jul 24 04:25:45 PM PDT 24 Jul 24 04:25:46 PM PDT 24 44938478 ps
T582 /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.1465497731 Jul 24 04:22:17 PM PDT 24 Jul 24 04:22:18 PM PDT 24 110826338 ps
T583 /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.2444563180 Jul 24 04:25:53 PM PDT 24 Jul 24 04:25:54 PM PDT 24 11953986 ps

Test location /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.523379016
Short name T6
Test name
Test status
Simulation time 49698258498 ps
CPU time 396.92 seconds
Started Jul 24 04:25:26 PM PDT 24
Finished Jul 24 04:32:04 PM PDT 24
Peak memory 204852 kb
Host smart-f62e8449-44ae-4b09-b2e4-d526b39864ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523379016 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.523379016
Directory /workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.692877200
Short name T5
Test name
Test status
Simulation time 3138207595405 ps
CPU time 4948.91 seconds
Started Jul 24 04:25:43 PM PDT 24
Finished Jul 24 05:48:13 PM PDT 24
Peak memory 191464 kb
Host smart-55f92346-834e-4b20-807c-8efad485947c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692877200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all.
692877200
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.488597604
Short name T13
Test name
Test status
Simulation time 275245184 ps
CPU time 0.94 seconds
Started Jul 24 04:25:16 PM PDT 24
Finished Jul 24 04:25:17 PM PDT 24
Peak memory 216004 kb
Host smart-48736386-2915-4e21-bc86-cc96351fde99
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488597604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.488597604
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.1939929090
Short name T154
Test name
Test status
Simulation time 671400481260 ps
CPU time 1583.53 seconds
Started Jul 24 04:23:35 PM PDT 24
Finished Jul 24 04:49:58 PM PDT 24
Peak memory 197456 kb
Host smart-2425b86d-e129-4b5e-8bd7-e4ce29c9d82e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939929090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.1939929090
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.2657759875
Short name T119
Test name
Test status
Simulation time 524090647182 ps
CPU time 1450.51 seconds
Started Jul 24 04:25:58 PM PDT 24
Finished Jul 24 04:50:09 PM PDT 24
Peak memory 197660 kb
Host smart-a32d603a-ebd9-4453-bd85-fe722842e548
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657759875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.2657759875
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.2149104231
Short name T177
Test name
Test status
Simulation time 1133883272984 ps
CPU time 6744.69 seconds
Started Jul 24 04:22:01 PM PDT 24
Finished Jul 24 06:14:27 PM PDT 24
Peak memory 191584 kb
Host smart-803d0abc-f50f-4612-bc16-431cc1d394dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149104231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.2149104231
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all_with_rand_reset.2335647528
Short name T46
Test name
Test status
Simulation time 106826529268 ps
CPU time 784.77 seconds
Started Jul 24 04:23:05 PM PDT 24
Finished Jul 24 04:36:10 PM PDT 24
Peak memory 208712 kb
Host smart-bdc13960-7bbe-45b5-a8a0-4a212e90a65a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335647528 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all_with_rand_reset.2335647528
Directory /workspace/31.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.2142900734
Short name T143
Test name
Test status
Simulation time 1595982584268 ps
CPU time 4937.06 seconds
Started Jul 24 04:25:25 PM PDT 24
Finished Jul 24 05:47:43 PM PDT 24
Peak memory 191540 kb
Host smart-c86c55a4-839f-4b1e-92b3-0e6f404b53fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142900734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.2142900734
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.154417570
Short name T247
Test name
Test status
Simulation time 564052821711 ps
CPU time 923.14 seconds
Started Jul 24 04:25:05 PM PDT 24
Finished Jul 24 04:40:29 PM PDT 24
Peak memory 190596 kb
Host smart-6d7b8a45-24aa-4ef1-879f-74aa6438b7c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154417570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.154417570
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.3208476020
Short name T172
Test name
Test status
Simulation time 536205746000 ps
CPU time 2361.14 seconds
Started Jul 24 04:25:28 PM PDT 24
Finished Jul 24 05:04:50 PM PDT 24
Peak memory 196196 kb
Host smart-50b68031-938d-4626-8d7d-34850337440a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208476020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.3208476020
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/171.rv_timer_random.1545906657
Short name T139
Test name
Test status
Simulation time 151336883948 ps
CPU time 290.83 seconds
Started Jul 24 04:26:09 PM PDT 24
Finished Jul 24 04:31:00 PM PDT 24
Peak memory 191496 kb
Host smart-a0d68387-b740-4def-aaf6-2e3644a63ad8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545906657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.1545906657
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.3292976084
Short name T313
Test name
Test status
Simulation time 2838227701008 ps
CPU time 3732.07 seconds
Started Jul 24 04:23:13 PM PDT 24
Finished Jul 24 05:25:26 PM PDT 24
Peak memory 191992 kb
Host smart-29ca0461-34c2-4a8e-b870-8adb95d9ffb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292976084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.3292976084
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.1769239222
Short name T88
Test name
Test status
Simulation time 4451717460108 ps
CPU time 2136.1 seconds
Started Jul 24 04:24:29 PM PDT 24
Finished Jul 24 05:00:06 PM PDT 24
Peak memory 191560 kb
Host smart-b54770fc-0e84-408b-b4db-fda26389d92a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769239222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.1769239222
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.21695050
Short name T53
Test name
Test status
Simulation time 645767338 ps
CPU time 1.34 seconds
Started Jul 24 04:25:27 PM PDT 24
Finished Jul 24 04:25:29 PM PDT 24
Peak memory 193484 kb
Host smart-1da467f9-f133-4ea0-b022-b579d71628f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21695050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_intg
_err.21695050
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.2422418499
Short name T60
Test name
Test status
Simulation time 318942962133 ps
CPU time 1905.85 seconds
Started Jul 24 04:25:07 PM PDT 24
Finished Jul 24 04:56:53 PM PDT 24
Peak memory 191164 kb
Host smart-17ceba9e-4fd2-4607-82f1-2fb6358683f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422418499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
2422418499
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.4190567435
Short name T102
Test name
Test status
Simulation time 13536094 ps
CPU time 0.56 seconds
Started Jul 24 04:25:25 PM PDT 24
Finished Jul 24 04:25:26 PM PDT 24
Peak memory 181744 kb
Host smart-4f7ca989-11ed-4f7c-bcb6-8266dc9a28ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190567435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.4190567435
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.775432047
Short name T69
Test name
Test status
Simulation time 244899868672 ps
CPU time 976.6 seconds
Started Jul 24 04:25:10 PM PDT 24
Finished Jul 24 04:41:27 PM PDT 24
Peak memory 191208 kb
Host smart-18f0e16e-5fa9-443d-9427-ccd5f546be23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775432047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all.
775432047
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.1946516431
Short name T213
Test name
Test status
Simulation time 724892452604 ps
CPU time 510.38 seconds
Started Jul 24 04:22:16 PM PDT 24
Finished Jul 24 04:30:47 PM PDT 24
Peak memory 195552 kb
Host smart-31265787-f2e8-48dd-8bf5-fc32683437dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946516431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
1946516431
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.668095297
Short name T209
Test name
Test status
Simulation time 915770700694 ps
CPU time 763.33 seconds
Started Jul 24 04:25:30 PM PDT 24
Finished Jul 24 04:38:15 PM PDT 24
Peak memory 189492 kb
Host smart-974fd298-bb49-4134-9d9d-4e03db5424a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668095297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all.
668095297
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_random.2664680257
Short name T218
Test name
Test status
Simulation time 680742395574 ps
CPU time 945.45 seconds
Started Jul 24 04:25:31 PM PDT 24
Finished Jul 24 04:41:16 PM PDT 24
Peak memory 191280 kb
Host smart-10a78857-280f-4e60-b121-d0ca2caa7219
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664680257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.2664680257
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.1820095483
Short name T165
Test name
Test status
Simulation time 1069296727898 ps
CPU time 2080.22 seconds
Started Jul 24 04:25:25 PM PDT 24
Finished Jul 24 05:00:06 PM PDT 24
Peak memory 190436 kb
Host smart-56b6afae-a6b0-4577-b62d-820f5422dc25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820095483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.1820095483
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_random.244883011
Short name T223
Test name
Test status
Simulation time 443877879632 ps
CPU time 940.48 seconds
Started Jul 24 04:25:49 PM PDT 24
Finished Jul 24 04:41:30 PM PDT 24
Peak memory 191256 kb
Host smart-2fbf5ff5-4c39-47ad-9b47-d1552a29f316
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244883011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.244883011
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.633113234
Short name T273
Test name
Test status
Simulation time 7900004489469 ps
CPU time 4175.66 seconds
Started Jul 24 04:22:46 PM PDT 24
Finished Jul 24 05:32:23 PM PDT 24
Peak memory 194932 kb
Host smart-44f73994-5163-49c0-a8ac-f7af427109ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633113234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.
633113234
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.1495713057
Short name T70
Test name
Test status
Simulation time 804145053757 ps
CPU time 1374.95 seconds
Started Jul 24 04:25:35 PM PDT 24
Finished Jul 24 04:48:30 PM PDT 24
Peak memory 191392 kb
Host smart-d919f0f5-8c06-441c-94b1-0979ff520672
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495713057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.1495713057
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_random.3882392399
Short name T251
Test name
Test status
Simulation time 302256129842 ps
CPU time 1078.36 seconds
Started Jul 24 04:25:09 PM PDT 24
Finished Jul 24 04:43:08 PM PDT 24
Peak memory 189364 kb
Host smart-160220ba-774a-46f6-bb8d-07cac9095d9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882392399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.3882392399
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random.450076429
Short name T130
Test name
Test status
Simulation time 492427374994 ps
CPU time 1083.97 seconds
Started Jul 24 04:23:44 PM PDT 24
Finished Jul 24 04:41:49 PM PDT 24
Peak memory 191556 kb
Host smart-7e9521ec-46e9-45a9-9ebd-527f11ead8cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450076429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.450076429
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.3232418887
Short name T79
Test name
Test status
Simulation time 268001448983 ps
CPU time 229.17 seconds
Started Jul 24 04:25:47 PM PDT 24
Finished Jul 24 04:29:37 PM PDT 24
Peak memory 191500 kb
Host smart-536df700-6769-466f-8a5d-185f6cd01d2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232418887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.3232418887
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.2119073038
Short name T309
Test name
Test status
Simulation time 350848847619 ps
CPU time 887.98 seconds
Started Jul 24 04:25:41 PM PDT 24
Finished Jul 24 04:40:29 PM PDT 24
Peak memory 191140 kb
Host smart-5d54656a-30ca-441a-b9f3-8e3ddb195696
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119073038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.2119073038
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.3986736433
Short name T229
Test name
Test status
Simulation time 461579749628 ps
CPU time 1012.15 seconds
Started Jul 24 04:25:43 PM PDT 24
Finished Jul 24 04:42:36 PM PDT 24
Peak memory 190708 kb
Host smart-fbf0caed-b9d2-4080-af17-645d06784a68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986736433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.3986736433
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.1872091253
Short name T71
Test name
Test status
Simulation time 716411681436 ps
CPU time 1248.43 seconds
Started Jul 24 04:24:57 PM PDT 24
Finished Jul 24 04:45:46 PM PDT 24
Peak memory 196276 kb
Host smart-7e520cfa-45b9-4821-a844-923b0ca16d23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872091253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.1872091253
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.3635054644
Short name T175
Test name
Test status
Simulation time 398485763127 ps
CPU time 1449.31 seconds
Started Jul 24 04:23:42 PM PDT 24
Finished Jul 24 04:47:51 PM PDT 24
Peak memory 191564 kb
Host smart-6000f9dc-5acc-402f-9449-067a6c63de51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635054644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
3635054644
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.3215370156
Short name T173
Test name
Test status
Simulation time 438504891846 ps
CPU time 2296.66 seconds
Started Jul 24 04:25:23 PM PDT 24
Finished Jul 24 05:03:40 PM PDT 24
Peak memory 196020 kb
Host smart-a06f54bf-f03b-48a6-95a6-dbfa8486dedd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215370156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.3215370156
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.64591329
Short name T248
Test name
Test status
Simulation time 1020370118580 ps
CPU time 1488.48 seconds
Started Jul 24 04:25:59 PM PDT 24
Finished Jul 24 04:50:49 PM PDT 24
Peak memory 191548 kb
Host smart-d0ff0ffb-7f6c-4ffc-ac9f-d544f3cc8efa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64591329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all.64591329
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.653134052
Short name T176
Test name
Test status
Simulation time 749601103843 ps
CPU time 951.19 seconds
Started Jul 24 04:25:44 PM PDT 24
Finished Jul 24 04:41:35 PM PDT 24
Peak memory 191272 kb
Host smart-b56c1571-daea-408e-ad9f-d8ad3f4f6d01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653134052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.653134052
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.1896557505
Short name T459
Test name
Test status
Simulation time 147665903 ps
CPU time 0.84 seconds
Started Jul 24 04:21:47 PM PDT 24
Finished Jul 24 04:21:48 PM PDT 24
Peak memory 195168 kb
Host smart-83246ed0-4ebd-4bbb-a8e7-adaeb48ac819
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896557505 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.1896557505
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/131.rv_timer_random.685240427
Short name T349
Test name
Test status
Simulation time 207818145016 ps
CPU time 550.3 seconds
Started Jul 24 04:26:11 PM PDT 24
Finished Jul 24 04:35:22 PM PDT 24
Peak memory 191548 kb
Host smart-c61c0c6a-8ccf-4fa0-8505-84bdfb541a76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685240427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.685240427
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.2372824575
Short name T151
Test name
Test status
Simulation time 470181426339 ps
CPU time 692.62 seconds
Started Jul 24 04:26:13 PM PDT 24
Finished Jul 24 04:37:46 PM PDT 24
Peak memory 191528 kb
Host smart-0235de64-30c4-486c-9445-262c2edcde10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372824575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.2372824575
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/180.rv_timer_random.1415556022
Short name T95
Test name
Test status
Simulation time 186076544736 ps
CPU time 2193.66 seconds
Started Jul 24 04:26:12 PM PDT 24
Finished Jul 24 05:02:46 PM PDT 24
Peak memory 183340 kb
Host smart-3a1b6c13-72a9-41b4-a213-fef63198df38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415556022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.1415556022
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.1540461439
Short name T264
Test name
Test status
Simulation time 812656708540 ps
CPU time 571.37 seconds
Started Jul 24 04:23:46 PM PDT 24
Finished Jul 24 04:33:18 PM PDT 24
Peak memory 195816 kb
Host smart-88953013-f928-4487-9fe3-4265f723389a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540461439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.1540461439
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_random.3409531746
Short name T180
Test name
Test status
Simulation time 251567317391 ps
CPU time 134.09 seconds
Started Jul 24 04:25:57 PM PDT 24
Finished Jul 24 04:28:12 PM PDT 24
Peak memory 194916 kb
Host smart-85201ada-8698-47f5-90aa-1d4647a9d30d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409531746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.3409531746
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.562239792
Short name T242
Test name
Test status
Simulation time 172774384983 ps
CPU time 417.3 seconds
Started Jul 24 04:25:09 PM PDT 24
Finished Jul 24 04:32:07 PM PDT 24
Peak memory 183400 kb
Host smart-9bbe5561-bb9c-45c0-9d68-20492935cdd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562239792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.562239792
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.3797687597
Short name T235
Test name
Test status
Simulation time 258636357689 ps
CPU time 126.5 seconds
Started Jul 24 04:22:02 PM PDT 24
Finished Jul 24 04:24:09 PM PDT 24
Peak memory 183532 kb
Host smart-6c742be0-a717-4c5b-8c93-45f3a85d216c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797687597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.3797687597
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/112.rv_timer_random.248230210
Short name T183
Test name
Test status
Simulation time 234800952910 ps
CPU time 490 seconds
Started Jul 24 04:25:59 PM PDT 24
Finished Jul 24 04:34:09 PM PDT 24
Peak memory 191508 kb
Host smart-b84b65cb-eeba-4799-aa1a-7c7ea19a1992
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248230210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.248230210
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random.3329489008
Short name T155
Test name
Test status
Simulation time 148953014587 ps
CPU time 273.82 seconds
Started Jul 24 04:25:52 PM PDT 24
Finished Jul 24 04:30:27 PM PDT 24
Peak memory 191380 kb
Host smart-c8d5f614-3fc2-4c7f-9b7f-499f3247d1ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329489008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.3329489008
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.3763383882
Short name T162
Test name
Test status
Simulation time 147564941879 ps
CPU time 344.06 seconds
Started Jul 24 04:26:02 PM PDT 24
Finished Jul 24 04:31:46 PM PDT 24
Peak memory 191596 kb
Host smart-1b922f42-eb96-4809-a1a0-a8fb44e15339
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763383882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.3763383882
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random.2732178385
Short name T59
Test name
Test status
Simulation time 124934416393 ps
CPU time 197.95 seconds
Started Jul 24 04:25:58 PM PDT 24
Finished Jul 24 04:29:16 PM PDT 24
Peak memory 195460 kb
Host smart-ecb0e60f-9d47-4dc1-ad9a-b0dcce5d0214
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732178385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.2732178385
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random.999415832
Short name T128
Test name
Test status
Simulation time 417853216840 ps
CPU time 297.75 seconds
Started Jul 24 04:25:28 PM PDT 24
Finished Jul 24 04:30:26 PM PDT 24
Peak memory 191180 kb
Host smart-72bc9e56-9e53-423e-927d-ae43a8df253a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999415832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.999415832
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.1373423979
Short name T316
Test name
Test status
Simulation time 141595008463 ps
CPU time 198.29 seconds
Started Jul 24 04:25:52 PM PDT 24
Finished Jul 24 04:29:11 PM PDT 24
Peak memory 191932 kb
Host smart-72d60723-febe-4ca8-b152-0b962e213656
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373423979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.1373423979
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.251930634
Short name T205
Test name
Test status
Simulation time 597299330193 ps
CPU time 1295.12 seconds
Started Jul 24 04:26:07 PM PDT 24
Finished Jul 24 04:47:42 PM PDT 24
Peak memory 191444 kb
Host smart-56b197c5-8c99-4962-8adb-4d86cc93a6c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251930634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.251930634
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/190.rv_timer_random.85605252
Short name T258
Test name
Test status
Simulation time 95440972968 ps
CPU time 638.16 seconds
Started Jul 24 04:26:14 PM PDT 24
Finished Jul 24 04:36:52 PM PDT 24
Peak memory 191532 kb
Host smart-b3ca60b1-7cf0-4868-8d10-afc93e1d3c56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85605252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.85605252
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.1793917235
Short name T178
Test name
Test status
Simulation time 428722579044 ps
CPU time 580.66 seconds
Started Jul 24 04:23:19 PM PDT 24
Finished Jul 24 04:33:00 PM PDT 24
Peak memory 191584 kb
Host smart-3ca87142-b270-4349-9b6d-b7e6a5c9b70b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793917235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.1793917235
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_random.663010169
Short name T20
Test name
Test status
Simulation time 140354292732 ps
CPU time 203.89 seconds
Started Jul 24 04:25:21 PM PDT 24
Finished Jul 24 04:28:45 PM PDT 24
Peak memory 190584 kb
Host smart-70b7e3d2-6545-4c61-9aaa-e845beba225c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663010169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.663010169
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.2692596679
Short name T357
Test name
Test status
Simulation time 496345997092 ps
CPU time 2839.79 seconds
Started Jul 24 04:25:09 PM PDT 24
Finished Jul 24 05:12:30 PM PDT 24
Peak memory 191204 kb
Host smart-6e02621a-d7c8-4594-ab4f-7debd3efc9ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692596679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.2692596679
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/8.rv_timer_random.1656591146
Short name T144
Test name
Test status
Simulation time 146824260795 ps
CPU time 256.34 seconds
Started Jul 24 04:25:50 PM PDT 24
Finished Jul 24 04:30:07 PM PDT 24
Peak memory 191512 kb
Host smart-e4af2b5b-61b9-4ee4-a905-3319b0645e1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656591146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.1656591146
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all_with_rand_reset.3746399658
Short name T33
Test name
Test status
Simulation time 252721087380 ps
CPU time 773.15 seconds
Started Jul 24 04:22:37 PM PDT 24
Finished Jul 24 04:35:31 PM PDT 24
Peak memory 206304 kb
Host smart-fde49baf-24df-49f5-8137-36a98871f356
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746399658 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all_with_rand_reset.3746399658
Directory /workspace/1.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/103.rv_timer_random.593011901
Short name T184
Test name
Test status
Simulation time 136246848996 ps
CPU time 389.65 seconds
Started Jul 24 04:25:58 PM PDT 24
Finished Jul 24 04:32:28 PM PDT 24
Peak memory 191508 kb
Host smart-3c606e9b-0c6b-4806-acb1-58a945bcd6de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593011901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.593011901
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.1169296693
Short name T256
Test name
Test status
Simulation time 973358207692 ps
CPU time 683.21 seconds
Started Jul 24 04:25:56 PM PDT 24
Finished Jul 24 04:37:19 PM PDT 24
Peak memory 191544 kb
Host smart-35a40ef9-4721-4eb6-8514-82f5e6e8dbe7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169296693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.1169296693
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.3686602229
Short name T325
Test name
Test status
Simulation time 132130107280 ps
CPU time 213.98 seconds
Started Jul 24 04:26:07 PM PDT 24
Finished Jul 24 04:29:41 PM PDT 24
Peak memory 191624 kb
Host smart-1a0fd6fb-bfb4-4c3d-af48-be7feb1ce370
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686602229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.3686602229
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.1612371103
Short name T40
Test name
Test status
Simulation time 39426690752 ps
CPU time 49.12 seconds
Started Jul 24 04:26:05 PM PDT 24
Finished Jul 24 04:26:54 PM PDT 24
Peak memory 183084 kb
Host smart-7b8d1b90-3521-4aeb-b7f6-de8d12cc6e8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612371103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.1612371103
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.2071402799
Short name T153
Test name
Test status
Simulation time 299130430088 ps
CPU time 462.55 seconds
Started Jul 24 04:26:10 PM PDT 24
Finished Jul 24 04:33:53 PM PDT 24
Peak memory 191624 kb
Host smart-33e2b5ee-a1fd-4859-a4b8-74a098c5c884
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071402799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.2071402799
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.3848317066
Short name T182
Test name
Test status
Simulation time 67040262406 ps
CPU time 99.47 seconds
Started Jul 24 04:26:14 PM PDT 24
Finished Jul 24 04:27:53 PM PDT 24
Peak memory 191536 kb
Host smart-650f79a8-b280-4cfe-b836-092a4d50cdaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848317066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.3848317066
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.4140883474
Short name T208
Test name
Test status
Simulation time 381371951743 ps
CPU time 177.44 seconds
Started Jul 24 04:26:13 PM PDT 24
Finished Jul 24 04:29:11 PM PDT 24
Peak memory 191452 kb
Host smart-62c746a2-68ea-46b9-8023-a9e9223a4497
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140883474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.4140883474
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.3774737074
Short name T210
Test name
Test status
Simulation time 261000301501 ps
CPU time 239.19 seconds
Started Jul 24 04:26:18 PM PDT 24
Finished Jul 24 04:30:17 PM PDT 24
Peak memory 191500 kb
Host smart-416a8ff5-9131-4c06-a8b3-5459b9d7516f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774737074 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.3774737074
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.2311215126
Short name T295
Test name
Test status
Simulation time 84507005449 ps
CPU time 135.17 seconds
Started Jul 24 04:26:40 PM PDT 24
Finished Jul 24 04:28:56 PM PDT 24
Peak memory 191280 kb
Host smart-614296a0-adf9-4e66-88fe-646c0601a237
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311215126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.2311215126
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.1788968715
Short name T21
Test name
Test status
Simulation time 6203653693881 ps
CPU time 832.94 seconds
Started Jul 24 04:25:21 PM PDT 24
Finished Jul 24 04:39:15 PM PDT 24
Peak memory 191612 kb
Host smart-60b0d504-fc76-44b2-9269-d5742339dfe5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788968715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.1788968715
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_random.191254674
Short name T133
Test name
Test status
Simulation time 214333625685 ps
CPU time 172.8 seconds
Started Jul 24 04:24:27 PM PDT 24
Finished Jul 24 04:27:20 PM PDT 24
Peak memory 191956 kb
Host smart-524847c9-26a3-4af7-aa8b-2634d8467b3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191254674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.191254674
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.3198529874
Short name T94
Test name
Test status
Simulation time 16247969740 ps
CPU time 23.57 seconds
Started Jul 24 04:25:59 PM PDT 24
Finished Jul 24 04:26:23 PM PDT 24
Peak memory 191428 kb
Host smart-d66dffdd-c06a-4ca3-85f0-42d88ade43a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198529874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.3198529874
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.3739264742
Short name T129
Test name
Test status
Simulation time 49558086709 ps
CPU time 40.35 seconds
Started Jul 24 04:24:44 PM PDT 24
Finished Jul 24 04:25:24 PM PDT 24
Peak memory 191588 kb
Host smart-b856d3c1-e774-42b9-94eb-94348b3b8f20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739264742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.3739264742
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.2902260961
Short name T196
Test name
Test status
Simulation time 143317813695 ps
CPU time 402.23 seconds
Started Jul 24 04:24:42 PM PDT 24
Finished Jul 24 04:31:24 PM PDT 24
Peak memory 191592 kb
Host smart-66b9c9b3-03dd-498e-8d11-6cd067af447e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902260961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.2902260961
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.681414259
Short name T147
Test name
Test status
Simulation time 397565932983 ps
CPU time 433.13 seconds
Started Jul 24 04:25:22 PM PDT 24
Finished Jul 24 04:32:35 PM PDT 24
Peak memory 191608 kb
Host smart-99ea5854-fdee-4405-bf44-e6b0d2769743
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681414259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.681414259
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.2924147862
Short name T266
Test name
Test status
Simulation time 1042431553550 ps
CPU time 516.08 seconds
Started Jul 24 04:25:40 PM PDT 24
Finished Jul 24 04:34:17 PM PDT 24
Peak memory 182592 kb
Host smart-cd504a5d-d26a-47dc-b75f-33ff9746641f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924147862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.2924147862
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/83.rv_timer_random.3452085033
Short name T312
Test name
Test status
Simulation time 134471291354 ps
CPU time 209.63 seconds
Started Jul 24 04:25:56 PM PDT 24
Finished Jul 24 04:29:26 PM PDT 24
Peak memory 191536 kb
Host smart-8d04e077-c217-4efa-a0de-25f29c82a517
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452085033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.3452085033
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/100.rv_timer_random.2868854491
Short name T302
Test name
Test status
Simulation time 180876213692 ps
CPU time 144.64 seconds
Started Jul 24 04:26:04 PM PDT 24
Finished Jul 24 04:28:28 PM PDT 24
Peak memory 191536 kb
Host smart-9e3ac3cd-968f-4b01-9c3e-50725a626510
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868854491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.2868854491
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.2917403241
Short name T8
Test name
Test status
Simulation time 31011338863 ps
CPU time 38.79 seconds
Started Jul 24 04:22:10 PM PDT 24
Finished Jul 24 04:22:48 PM PDT 24
Peak memory 183368 kb
Host smart-3d9e7290-083a-4cc6-a7d9-8021f3654356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917403241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.2917403241
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.4155059889
Short name T245
Test name
Test status
Simulation time 49425795617 ps
CPU time 75.29 seconds
Started Jul 24 04:26:04 PM PDT 24
Finished Jul 24 04:27:20 PM PDT 24
Peak memory 191536 kb
Host smart-a498ac27-ad58-4e65-acba-1f0562c305fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155059889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.4155059889
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.2627173110
Short name T265
Test name
Test status
Simulation time 701620569278 ps
CPU time 593.63 seconds
Started Jul 24 04:25:49 PM PDT 24
Finished Jul 24 04:35:43 PM PDT 24
Peak memory 183064 kb
Host smart-c8a9e5d8-c655-4b1a-9746-176943c38784
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627173110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.2627173110
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/155.rv_timer_random.2338965445
Short name T331
Test name
Test status
Simulation time 741193647392 ps
CPU time 700.45 seconds
Started Jul 24 04:26:05 PM PDT 24
Finished Jul 24 04:37:45 PM PDT 24
Peak memory 191544 kb
Host smart-4e702537-4276-49e4-b97e-c1eb9d327033
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338965445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.2338965445
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.3343908345
Short name T318
Test name
Test status
Simulation time 146397911375 ps
CPU time 728.46 seconds
Started Jul 24 04:26:11 PM PDT 24
Finished Jul 24 04:38:20 PM PDT 24
Peak memory 194636 kb
Host smart-565549b4-ad35-467d-9cf4-9a1b446cfe32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343908345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.3343908345
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.1371139622
Short name T121
Test name
Test status
Simulation time 213329549566 ps
CPU time 508.94 seconds
Started Jul 24 04:26:12 PM PDT 24
Finished Jul 24 04:34:41 PM PDT 24
Peak memory 191544 kb
Host smart-3a891e00-5625-4b47-a359-791b665f0637
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371139622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.1371139622
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.4262680815
Short name T101
Test name
Test status
Simulation time 79383102397 ps
CPU time 127.52 seconds
Started Jul 24 04:21:59 PM PDT 24
Finished Jul 24 04:24:07 PM PDT 24
Peak memory 191992 kb
Host smart-eb807f14-f475-4f92-b67f-76d5151f361b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262680815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.4262680815
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.1145636868
Short name T89
Test name
Test status
Simulation time 36587347754 ps
CPU time 57.63 seconds
Started Jul 24 04:23:09 PM PDT 24
Finished Jul 24 04:24:07 PM PDT 24
Peak memory 183392 kb
Host smart-0579af3a-a39b-4e20-876f-4d13000e258c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145636868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.1145636868
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.1949727161
Short name T179
Test name
Test status
Simulation time 93670417344 ps
CPU time 170.11 seconds
Started Jul 24 04:22:44 PM PDT 24
Finished Jul 24 04:25:35 PM PDT 24
Peak memory 183344 kb
Host smart-ee6c9919-1254-4271-a5a7-abd9667d3d32
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949727161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.1949727161
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.1515159437
Short name T338
Test name
Test status
Simulation time 212514437003 ps
CPU time 166.03 seconds
Started Jul 24 04:24:19 PM PDT 24
Finished Jul 24 04:27:05 PM PDT 24
Peak memory 194020 kb
Host smart-5b3321de-fa0e-4d78-a6c1-323c9eff3415
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515159437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.1515159437
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_random.1399491336
Short name T345
Test name
Test status
Simulation time 141261435703 ps
CPU time 172.78 seconds
Started Jul 24 04:25:42 PM PDT 24
Finished Jul 24 04:28:35 PM PDT 24
Peak memory 191492 kb
Host smart-a359fc28-7c67-4256-b176-c7d249023835
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399491336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.1399491336
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.1436952509
Short name T327
Test name
Test status
Simulation time 2519161898552 ps
CPU time 1149.6 seconds
Started Jul 24 04:25:02 PM PDT 24
Finished Jul 24 04:44:12 PM PDT 24
Peak memory 182320 kb
Host smart-f4616322-7cdf-49db-ad8a-0c4b44d76042
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436952509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.1436952509
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.2064547736
Short name T297
Test name
Test status
Simulation time 1494130811005 ps
CPU time 403.45 seconds
Started Jul 24 04:24:45 PM PDT 24
Finished Jul 24 04:31:28 PM PDT 24
Peak memory 191996 kb
Host smart-842063eb-880c-4aaa-bc58-0365ac1404a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064547736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.2064547736
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.397270980
Short name T107
Test name
Test status
Simulation time 36535595 ps
CPU time 0.83 seconds
Started Jul 24 04:23:20 PM PDT 24
Finished Jul 24 04:23:21 PM PDT 24
Peak memory 190952 kb
Host smart-f536a8aa-d7b8-4409-ad0c-0694b7040a0b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397270980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alias
ing.397270980
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.616211376
Short name T109
Test name
Test status
Simulation time 182071422 ps
CPU time 3.26 seconds
Started Jul 24 04:22:02 PM PDT 24
Finished Jul 24 04:22:06 PM PDT 24
Peak memory 191056 kb
Host smart-f60190c1-308b-45ec-86b0-d4894774f011
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616211376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_b
ash.616211376
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.660452742
Short name T492
Test name
Test status
Simulation time 15605363 ps
CPU time 0.58 seconds
Started Jul 24 04:20:52 PM PDT 24
Finished Jul 24 04:20:52 PM PDT 24
Peak memory 182716 kb
Host smart-cc709813-939c-44e2-bdcf-84f99a89a0b3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660452742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_re
set.660452742
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.1935129377
Short name T487
Test name
Test status
Simulation time 147364073 ps
CPU time 0.56 seconds
Started Jul 24 04:25:46 PM PDT 24
Finished Jul 24 04:25:48 PM PDT 24
Peak memory 181668 kb
Host smart-42baa488-1635-4859-8138-8d2290a117b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935129377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.1935129377
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.2884391801
Short name T580
Test name
Test status
Simulation time 28395437 ps
CPU time 0.58 seconds
Started Jul 24 04:24:09 PM PDT 24
Finished Jul 24 04:24:10 PM PDT 24
Peak memory 182104 kb
Host smart-b82fea73-e801-4657-a0d7-b0918687aadf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884391801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.2884391801
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.479558164
Short name T110
Test name
Test status
Simulation time 36352419 ps
CPU time 0.73 seconds
Started Jul 24 04:25:40 PM PDT 24
Finished Jul 24 04:25:41 PM PDT 24
Peak memory 193336 kb
Host smart-6169b76b-d7cc-4792-b7b6-f519dfe2c448
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479558164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_tim
er_same_csr_outstanding.479558164
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.960535017
Short name T576
Test name
Test status
Simulation time 582210706 ps
CPU time 2.19 seconds
Started Jul 24 04:25:46 PM PDT 24
Finished Jul 24 04:25:49 PM PDT 24
Peak memory 197248 kb
Host smart-f67f4e0e-229c-43ff-a326-d4e3e9f54642
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960535017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.960535017
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1749279937
Short name T564
Test name
Test status
Simulation time 359315318 ps
CPU time 1.31 seconds
Started Jul 24 04:25:41 PM PDT 24
Finished Jul 24 04:25:44 PM PDT 24
Peak memory 194464 kb
Host smart-17e6b5ee-4298-4052-ab32-ce3029960fe0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749279937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.1749279937
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.83956422
Short name T516
Test name
Test status
Simulation time 28237495 ps
CPU time 0.69 seconds
Started Jul 24 04:25:21 PM PDT 24
Finished Jul 24 04:25:22 PM PDT 24
Peak memory 182596 kb
Host smart-6f936ea5-c13e-4099-91a9-668de13074e8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83956422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_aliasi
ng.83956422
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.3731394824
Short name T483
Test name
Test status
Simulation time 321437772 ps
CPU time 3.3 seconds
Started Jul 24 04:22:04 PM PDT 24
Finished Jul 24 04:22:08 PM PDT 24
Peak memory 182872 kb
Host smart-aaab9086-5a61-46e6-91ed-219cd2f8ac1e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731394824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.3731394824
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1461541164
Short name T105
Test name
Test status
Simulation time 56235787 ps
CPU time 0.53 seconds
Started Jul 24 04:23:41 PM PDT 24
Finished Jul 24 04:23:42 PM PDT 24
Peak memory 182320 kb
Host smart-7fce3dd4-9f7e-4233-a897-1fe051ea528f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461541164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.1461541164
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.3724114109
Short name T464
Test name
Test status
Simulation time 72370780 ps
CPU time 1.68 seconds
Started Jul 24 04:25:10 PM PDT 24
Finished Jul 24 04:25:12 PM PDT 24
Peak memory 197248 kb
Host smart-fa14544e-58cd-475b-a90b-d1a9ad25ca6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724114109 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.3724114109
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.2066588854
Short name T499
Test name
Test status
Simulation time 21634627 ps
CPU time 0.58 seconds
Started Jul 24 04:25:25 PM PDT 24
Finished Jul 24 04:25:26 PM PDT 24
Peak memory 181984 kb
Host smart-69ccf21f-9e15-4d4f-85b0-28fa1908bcb1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066588854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.2066588854
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.2444563180
Short name T583
Test name
Test status
Simulation time 11953986 ps
CPU time 0.52 seconds
Started Jul 24 04:25:53 PM PDT 24
Finished Jul 24 04:25:54 PM PDT 24
Peak memory 182184 kb
Host smart-b4e60287-c542-4bd1-9b69-258a6bc3fac1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444563180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.2444563180
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.3106280437
Short name T566
Test name
Test status
Simulation time 120372508 ps
CPU time 0.76 seconds
Started Jul 24 04:25:21 PM PDT 24
Finished Jul 24 04:25:23 PM PDT 24
Peak memory 193312 kb
Host smart-481dff76-40b7-4233-9b9b-8e9dddc41e74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106280437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.3106280437
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.2258039521
Short name T455
Test name
Test status
Simulation time 82368380 ps
CPU time 1.14 seconds
Started Jul 24 04:25:26 PM PDT 24
Finished Jul 24 04:25:27 PM PDT 24
Peak memory 196476 kb
Host smart-61a10f90-29dd-4f5c-a6e8-bed8cbb0a8c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258039521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.2258039521
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.4188017852
Short name T503
Test name
Test status
Simulation time 111692501 ps
CPU time 1.24 seconds
Started Jul 24 04:25:53 PM PDT 24
Finished Jul 24 04:25:54 PM PDT 24
Peak memory 195148 kb
Host smart-57e34db3-cc43-48b1-9aa0-1ab317bb00ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188017852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.4188017852
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.3237514231
Short name T494
Test name
Test status
Simulation time 40959422 ps
CPU time 0.7 seconds
Started Jul 24 04:25:06 PM PDT 24
Finished Jul 24 04:25:07 PM PDT 24
Peak memory 194980 kb
Host smart-1a4c41d5-e09c-415d-af9b-b4577665c137
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237514231 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.3237514231
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.1589399264
Short name T460
Test name
Test status
Simulation time 33596539 ps
CPU time 0.57 seconds
Started Jul 24 04:23:05 PM PDT 24
Finished Jul 24 04:23:06 PM PDT 24
Peak memory 182736 kb
Host smart-2443a4dc-f2b9-4890-a86f-35a5d63eec01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589399264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.1589399264
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.2690459196
Short name T531
Test name
Test status
Simulation time 83785116 ps
CPU time 0.53 seconds
Started Jul 24 04:25:20 PM PDT 24
Finished Jul 24 04:25:21 PM PDT 24
Peak memory 182688 kb
Host smart-8d8cf142-1ea8-4131-b70d-f2544be87b8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690459196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.2690459196
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2376290326
Short name T570
Test name
Test status
Simulation time 103941859 ps
CPU time 0.71 seconds
Started Jul 24 04:25:42 PM PDT 24
Finished Jul 24 04:25:43 PM PDT 24
Peak memory 193208 kb
Host smart-199e2669-dc61-4266-a5cc-b6cceb2fdcb1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376290326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.2376290326
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.2971072035
Short name T502
Test name
Test status
Simulation time 145972106 ps
CPU time 2.83 seconds
Started Jul 24 04:21:52 PM PDT 24
Finished Jul 24 04:21:55 PM PDT 24
Peak memory 197512 kb
Host smart-4f13b959-8c3e-4b62-8d3a-579bb156c74b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971072035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.2971072035
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.4012445290
Short name T28
Test name
Test status
Simulation time 48381808 ps
CPU time 0.82 seconds
Started Jul 24 04:25:26 PM PDT 24
Finished Jul 24 04:25:27 PM PDT 24
Peak memory 181828 kb
Host smart-3feeea25-f7c8-4bd9-8e7f-20dd0e65f807
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012445290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.4012445290
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.157456091
Short name T31
Test name
Test status
Simulation time 72545135 ps
CPU time 1.02 seconds
Started Jul 24 04:23:52 PM PDT 24
Finished Jul 24 04:23:53 PM PDT 24
Peak memory 197372 kb
Host smart-a86c7974-036e-4897-a958-e2257e804a35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157456091 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.157456091
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.1007232396
Short name T542
Test name
Test status
Simulation time 30596143 ps
CPU time 0.54 seconds
Started Jul 24 04:25:31 PM PDT 24
Finished Jul 24 04:25:32 PM PDT 24
Peak memory 182488 kb
Host smart-38232fb3-2e27-44d4-a676-099c1265feff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007232396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.1007232396
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.4083958651
Short name T473
Test name
Test status
Simulation time 23984686 ps
CPU time 0.56 seconds
Started Jul 24 04:21:52 PM PDT 24
Finished Jul 24 04:21:53 PM PDT 24
Peak memory 181940 kb
Host smart-55d34251-eec8-4e0d-bc6a-e0088f1ed258
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083958651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.4083958651
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3142222563
Short name T528
Test name
Test status
Simulation time 65398689 ps
CPU time 0.74 seconds
Started Jul 24 04:25:40 PM PDT 24
Finished Jul 24 04:25:41 PM PDT 24
Peak memory 193504 kb
Host smart-1b883053-c8b0-4296-983a-b3581255d91a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142222563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.3142222563
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.1386893764
Short name T521
Test name
Test status
Simulation time 55401745 ps
CPU time 2.57 seconds
Started Jul 24 04:25:31 PM PDT 24
Finished Jul 24 04:25:34 PM PDT 24
Peak memory 197344 kb
Host smart-225db2f9-8af4-4003-84d2-751d80389014
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386893764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.1386893764
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.570930495
Short name T500
Test name
Test status
Simulation time 132595614 ps
CPU time 0.8 seconds
Started Jul 24 04:25:26 PM PDT 24
Finished Jul 24 04:25:27 PM PDT 24
Peak memory 192776 kb
Host smart-f0cb2513-0901-47ee-ac8a-a5ba6d85d28f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570930495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_in
tg_err.570930495
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.37282997
Short name T454
Test name
Test status
Simulation time 86549824 ps
CPU time 1.12 seconds
Started Jul 24 04:24:24 PM PDT 24
Finished Jul 24 04:24:25 PM PDT 24
Peak memory 197836 kb
Host smart-77d05ddf-d3d8-42a6-99de-20382db78098
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37282997 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.37282997
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1228412197
Short name T30
Test name
Test status
Simulation time 24390836 ps
CPU time 0.54 seconds
Started Jul 24 04:25:26 PM PDT 24
Finished Jul 24 04:25:27 PM PDT 24
Peak memory 181952 kb
Host smart-59a9fcd7-294e-4642-b00f-28174ee0ee6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228412197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.1228412197
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.480190792
Short name T529
Test name
Test status
Simulation time 14262971 ps
CPU time 0.55 seconds
Started Jul 24 04:25:42 PM PDT 24
Finished Jul 24 04:25:43 PM PDT 24
Peak memory 182592 kb
Host smart-0546afa0-2d6f-4a4b-80d1-8036bf6c9239
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480190792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.480190792
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.2792449486
Short name T525
Test name
Test status
Simulation time 16541310 ps
CPU time 0.71 seconds
Started Jul 24 04:25:41 PM PDT 24
Finished Jul 24 04:25:43 PM PDT 24
Peak memory 193344 kb
Host smart-915b2808-00ee-43d3-accc-5d75e7c16ce6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792449486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.2792449486
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.3185126800
Short name T495
Test name
Test status
Simulation time 129179631 ps
CPU time 2.3 seconds
Started Jul 24 04:25:45 PM PDT 24
Finished Jul 24 04:25:48 PM PDT 24
Peak memory 197440 kb
Host smart-58072b75-56fc-4581-8ad2-d992250b1344
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185126800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.3185126800
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.4220207603
Short name T550
Test name
Test status
Simulation time 391312073 ps
CPU time 1.3 seconds
Started Jul 24 04:24:02 PM PDT 24
Finished Jul 24 04:24:04 PM PDT 24
Peak memory 195120 kb
Host smart-5e608301-997e-4117-921c-43dcd9923d38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220207603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.4220207603
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.3016017820
Short name T581
Test name
Test status
Simulation time 44938478 ps
CPU time 0.87 seconds
Started Jul 24 04:25:45 PM PDT 24
Finished Jul 24 04:25:46 PM PDT 24
Peak memory 196948 kb
Host smart-e9a58065-63cd-49b5-b7c5-c2e593022536
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016017820 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.3016017820
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3271084484
Short name T552
Test name
Test status
Simulation time 13354150 ps
CPU time 0.56 seconds
Started Jul 24 04:25:41 PM PDT 24
Finished Jul 24 04:25:42 PM PDT 24
Peak memory 182484 kb
Host smart-79398460-a36d-494a-8277-2c269aa932d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271084484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.3271084484
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3036384432
Short name T538
Test name
Test status
Simulation time 12115329 ps
CPU time 0.56 seconds
Started Jul 24 04:25:26 PM PDT 24
Finished Jul 24 04:25:27 PM PDT 24
Peak memory 181216 kb
Host smart-cf9427b6-ca57-40f9-aa09-5ffbf004c74a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036384432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.3036384432
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.492666082
Short name T111
Test name
Test status
Simulation time 23698308 ps
CPU time 0.62 seconds
Started Jul 24 04:25:30 PM PDT 24
Finished Jul 24 04:25:31 PM PDT 24
Peak memory 190780 kb
Host smart-934c2269-1907-4117-afcd-daf7e6c4948c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492666082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_ti
mer_same_csr_outstanding.492666082
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.923515914
Short name T505
Test name
Test status
Simulation time 160391434 ps
CPU time 0.99 seconds
Started Jul 24 04:25:26 PM PDT 24
Finished Jul 24 04:25:28 PM PDT 24
Peak memory 196724 kb
Host smart-80c148f3-db83-4a72-b7bb-4cafa01324de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923515914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.923515914
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.2577352637
Short name T29
Test name
Test status
Simulation time 200688045 ps
CPU time 0.79 seconds
Started Jul 24 04:25:31 PM PDT 24
Finished Jul 24 04:25:32 PM PDT 24
Peak memory 193188 kb
Host smart-7df60c85-5daa-4291-901b-03a1c83328f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577352637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.2577352637
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.2433269595
Short name T573
Test name
Test status
Simulation time 25293078 ps
CPU time 1.11 seconds
Started Jul 24 04:22:32 PM PDT 24
Finished Jul 24 04:22:34 PM PDT 24
Peak memory 197420 kb
Host smart-fefe9ebc-4d33-489f-bdb0-3161577e945c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433269595 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.2433269595
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3282006034
Short name T514
Test name
Test status
Simulation time 21551316 ps
CPU time 0.61 seconds
Started Jul 24 04:25:30 PM PDT 24
Finished Jul 24 04:25:32 PM PDT 24
Peak memory 181192 kb
Host smart-d1376887-bf12-4be0-bcc2-8022998fa24e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282006034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.3282006034
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.775095717
Short name T569
Test name
Test status
Simulation time 30554554 ps
CPU time 0.54 seconds
Started Jul 24 04:23:09 PM PDT 24
Finished Jul 24 04:23:10 PM PDT 24
Peak memory 182616 kb
Host smart-a652379b-a593-4d16-98af-1157ec7d3915
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775095717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.775095717
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.604078601
Short name T524
Test name
Test status
Simulation time 65795483 ps
CPU time 0.7 seconds
Started Jul 24 04:25:47 PM PDT 24
Finished Jul 24 04:25:49 PM PDT 24
Peak memory 193284 kb
Host smart-acbf8373-c2d6-4dd0-b695-3ba74016ffe9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604078601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_ti
mer_same_csr_outstanding.604078601
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2244293148
Short name T561
Test name
Test status
Simulation time 109162350 ps
CPU time 1.54 seconds
Started Jul 24 04:25:30 PM PDT 24
Finished Jul 24 04:25:32 PM PDT 24
Peak memory 196296 kb
Host smart-010e850a-f273-42a2-8574-98a436d00363
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244293148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.2244293148
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.2398714664
Short name T497
Test name
Test status
Simulation time 41733329 ps
CPU time 0.82 seconds
Started Jul 24 04:24:26 PM PDT 24
Finished Jul 24 04:24:27 PM PDT 24
Peak memory 183336 kb
Host smart-1bdf4ce0-6069-4e8d-82d2-bf38e00b4c54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398714664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.2398714664
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.507724928
Short name T462
Test name
Test status
Simulation time 26983344 ps
CPU time 0.77 seconds
Started Jul 24 04:21:12 PM PDT 24
Finished Jul 24 04:21:13 PM PDT 24
Peak memory 195628 kb
Host smart-266c80e7-fa97-4575-8aba-3e48ae3b03dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507724928 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.507724928
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.4073575780
Short name T93
Test name
Test status
Simulation time 17069805 ps
CPU time 0.6 seconds
Started Jul 24 04:21:06 PM PDT 24
Finished Jul 24 04:21:07 PM PDT 24
Peak memory 182776 kb
Host smart-fd89fe09-c42e-4862-a80a-99024e79c5ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073575780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.4073575780
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.292358835
Short name T506
Test name
Test status
Simulation time 37628117 ps
CPU time 0.55 seconds
Started Jul 24 04:25:31 PM PDT 24
Finished Jul 24 04:25:32 PM PDT 24
Peak memory 181868 kb
Host smart-d9f73c7f-1205-4c2c-92e2-a0ef745ae8ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292358835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.292358835
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.1102692371
Short name T91
Test name
Test status
Simulation time 25682785 ps
CPU time 0.7 seconds
Started Jul 24 04:21:17 PM PDT 24
Finished Jul 24 04:21:18 PM PDT 24
Peak memory 192400 kb
Host smart-0ea20cb8-88e0-48c2-ac8d-5077c2e6f594
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102692371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.1102692371
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.3806939430
Short name T532
Test name
Test status
Simulation time 101896010 ps
CPU time 1.9 seconds
Started Jul 24 04:21:09 PM PDT 24
Finished Jul 24 04:21:11 PM PDT 24
Peak memory 197540 kb
Host smart-e4d2d3bf-004f-4e61-8914-29933120c826
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806939430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.3806939430
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3885656182
Short name T574
Test name
Test status
Simulation time 94803781 ps
CPU time 1.33 seconds
Started Jul 24 04:21:12 PM PDT 24
Finished Jul 24 04:21:13 PM PDT 24
Peak memory 195800 kb
Host smart-076da8f5-23fa-4217-bc4a-c376c14fba6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885656182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.3885656182
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.4091810398
Short name T553
Test name
Test status
Simulation time 35552698 ps
CPU time 1.5 seconds
Started Jul 24 04:24:18 PM PDT 24
Finished Jul 24 04:24:20 PM PDT 24
Peak memory 197484 kb
Host smart-db828f48-3dd3-4d2b-a094-2974c6bb4588
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091810398 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.4091810398
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.2017942069
Short name T537
Test name
Test status
Simulation time 13431515 ps
CPU time 0.58 seconds
Started Jul 24 04:21:58 PM PDT 24
Finished Jul 24 04:21:59 PM PDT 24
Peak memory 183184 kb
Host smart-60eeb1e9-bf14-4fcd-9da3-039c8859ac28
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017942069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.2017942069
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.573044718
Short name T471
Test name
Test status
Simulation time 13074428 ps
CPU time 0.57 seconds
Started Jul 24 04:25:23 PM PDT 24
Finished Jul 24 04:25:24 PM PDT 24
Peak memory 181380 kb
Host smart-1acde288-4ed9-4b5f-9dcf-a4586007c86a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573044718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.573044718
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.4127194597
Short name T479
Test name
Test status
Simulation time 290591921 ps
CPU time 0.72 seconds
Started Jul 24 04:21:29 PM PDT 24
Finished Jul 24 04:21:30 PM PDT 24
Peak memory 193328 kb
Host smart-30dcd306-2478-4747-a1c6-c4cdcf96439a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127194597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.4127194597
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3555403115
Short name T562
Test name
Test status
Simulation time 133385844 ps
CPU time 1.29 seconds
Started Jul 24 04:25:19 PM PDT 24
Finished Jul 24 04:25:21 PM PDT 24
Peak memory 191108 kb
Host smart-d9da90e7-6157-4192-9be5-3078ec9a14af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555403115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.3555403115
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.492145562
Short name T507
Test name
Test status
Simulation time 363665405 ps
CPU time 1.38 seconds
Started Jul 24 04:21:18 PM PDT 24
Finished Jul 24 04:21:20 PM PDT 24
Peak memory 195428 kb
Host smart-ab867692-5a24-431f-a321-d556fef79761
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492145562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_in
tg_err.492145562
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.2603368553
Short name T548
Test name
Test status
Simulation time 40144168 ps
CPU time 1.01 seconds
Started Jul 24 04:22:30 PM PDT 24
Finished Jul 24 04:22:31 PM PDT 24
Peak memory 197512 kb
Host smart-57b79f90-99a9-4570-9973-a304e4b72f80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603368553 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.2603368553
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.2948816630
Short name T534
Test name
Test status
Simulation time 33084060 ps
CPU time 0.56 seconds
Started Jul 24 04:21:48 PM PDT 24
Finished Jul 24 04:21:49 PM PDT 24
Peak memory 182924 kb
Host smart-1f02ea4f-cf29-4a46-bd4f-301650826aeb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948816630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.2948816630
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.2439320730
Short name T579
Test name
Test status
Simulation time 20582728 ps
CPU time 0.59 seconds
Started Jul 24 04:21:58 PM PDT 24
Finished Jul 24 04:21:59 PM PDT 24
Peak memory 183092 kb
Host smart-3ae64e35-ae71-48e2-81a0-72326f33e1e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439320730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.2439320730
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2606574402
Short name T536
Test name
Test status
Simulation time 191801125 ps
CPU time 0.74 seconds
Started Jul 24 04:25:46 PM PDT 24
Finished Jul 24 04:25:47 PM PDT 24
Peak memory 190992 kb
Host smart-3a61ff6c-536b-46e1-9fda-a0094cf61c33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606574402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.2606574402
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.4256489201
Short name T568
Test name
Test status
Simulation time 131379717 ps
CPU time 2.59 seconds
Started Jul 24 04:25:45 PM PDT 24
Finished Jul 24 04:25:49 PM PDT 24
Peak memory 196780 kb
Host smart-2995fc19-a758-4a6c-ae12-eb17cade2306
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256489201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.4256489201
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.885681607
Short name T556
Test name
Test status
Simulation time 145554945 ps
CPU time 0.81 seconds
Started Jul 24 04:23:41 PM PDT 24
Finished Jul 24 04:23:42 PM PDT 24
Peak memory 193852 kb
Host smart-5c726d94-4f94-402c-9289-f8a9f5fe57af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885681607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_in
tg_err.885681607
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.4242097894
Short name T540
Test name
Test status
Simulation time 141075068 ps
CPU time 1.01 seconds
Started Jul 24 04:21:43 PM PDT 24
Finished Jul 24 04:21:44 PM PDT 24
Peak memory 197408 kb
Host smart-60841f68-441b-4807-999c-2915712ca7f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242097894 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.4242097894
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.2098602639
Short name T106
Test name
Test status
Simulation time 11856573 ps
CPU time 0.56 seconds
Started Jul 24 04:25:55 PM PDT 24
Finished Jul 24 04:25:56 PM PDT 24
Peak memory 182736 kb
Host smart-244fde36-b86e-453b-a5d5-a36e86d4e4af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098602639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.2098602639
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.2584271383
Short name T476
Test name
Test status
Simulation time 20405041 ps
CPU time 0.53 seconds
Started Jul 24 04:25:46 PM PDT 24
Finished Jul 24 04:25:47 PM PDT 24
Peak memory 182336 kb
Host smart-dd2a6d85-3cd7-4af2-ac1f-d892195ab856
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584271383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.2584271383
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3553915042
Short name T49
Test name
Test status
Simulation time 43804036 ps
CPU time 0.75 seconds
Started Jul 24 04:25:55 PM PDT 24
Finished Jul 24 04:25:56 PM PDT 24
Peak memory 193188 kb
Host smart-fd79dcf7-2f59-4b7a-ae93-b8d1742424b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553915042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.3553915042
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3654031142
Short name T485
Test name
Test status
Simulation time 96278305 ps
CPU time 1.73 seconds
Started Jul 24 04:25:20 PM PDT 24
Finished Jul 24 04:25:22 PM PDT 24
Peak memory 195212 kb
Host smart-39e60b0c-2d84-49ca-b758-eeedd89aedf4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654031142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.3654031142
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1300540966
Short name T117
Test name
Test status
Simulation time 290961980 ps
CPU time 1.3 seconds
Started Jul 24 04:25:29 PM PDT 24
Finished Jul 24 04:25:31 PM PDT 24
Peak memory 194272 kb
Host smart-7d94cab9-f8c2-442f-9c3e-6da72ddb4e29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300540966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.1300540966
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.154557782
Short name T567
Test name
Test status
Simulation time 36203477 ps
CPU time 1.29 seconds
Started Jul 24 04:25:41 PM PDT 24
Finished Jul 24 04:25:44 PM PDT 24
Peak memory 197472 kb
Host smart-7e8ee96a-8be6-44ee-8de5-a6bbb5ab3a57
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154557782 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.154557782
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.551927350
Short name T64
Test name
Test status
Simulation time 15541157 ps
CPU time 0.6 seconds
Started Jul 24 04:25:20 PM PDT 24
Finished Jul 24 04:25:21 PM PDT 24
Peak memory 180676 kb
Host smart-1397bbab-adb0-4f04-bd75-74d892a407ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551927350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.551927350
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.2117401387
Short name T565
Test name
Test status
Simulation time 26704352 ps
CPU time 0.6 seconds
Started Jul 24 04:25:20 PM PDT 24
Finished Jul 24 04:25:21 PM PDT 24
Peak memory 179784 kb
Host smart-bc624d92-4356-4785-be7e-1afc15d2fd22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117401387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.2117401387
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2332962386
Short name T501
Test name
Test status
Simulation time 75526094 ps
CPU time 0.82 seconds
Started Jul 24 04:23:02 PM PDT 24
Finished Jul 24 04:23:03 PM PDT 24
Peak memory 193620 kb
Host smart-7a4a1577-ddc6-4f3e-93d2-feb3c724f124
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332962386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.2332962386
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.4168361732
Short name T478
Test name
Test status
Simulation time 641969386 ps
CPU time 2.29 seconds
Started Jul 24 04:25:20 PM PDT 24
Finished Jul 24 04:25:23 PM PDT 24
Peak memory 196628 kb
Host smart-3ba4faa1-5030-464b-ae86-583885eeeb0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168361732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.4168361732
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.636376966
Short name T115
Test name
Test status
Simulation time 219837802 ps
CPU time 1.06 seconds
Started Jul 24 04:25:46 PM PDT 24
Finished Jul 24 04:25:48 PM PDT 24
Peak memory 195072 kb
Host smart-8e0fff9b-d917-4302-8f48-2fbc300bd3e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636376966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_in
tg_err.636376966
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.4208709947
Short name T496
Test name
Test status
Simulation time 16630899 ps
CPU time 0.84 seconds
Started Jul 24 04:22:18 PM PDT 24
Finished Jul 24 04:22:19 PM PDT 24
Peak memory 182752 kb
Host smart-09deddbe-4909-4d26-b1e7-0d870aebf593
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208709947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.4208709947
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.2937547006
Short name T482
Test name
Test status
Simulation time 1041867652 ps
CPU time 2.65 seconds
Started Jul 24 04:25:11 PM PDT 24
Finished Jul 24 04:25:14 PM PDT 24
Peak memory 192104 kb
Host smart-35646096-cfe1-432f-85d3-ef190f852905
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937547006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.2937547006
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.4254139889
Short name T472
Test name
Test status
Simulation time 32535607 ps
CPU time 0.58 seconds
Started Jul 24 04:25:06 PM PDT 24
Finished Jul 24 04:25:07 PM PDT 24
Peak memory 180992 kb
Host smart-51b1e030-7d12-4783-beed-48629e9ad4a8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254139889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.4254139889
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.2927532624
Short name T541
Test name
Test status
Simulation time 72323528 ps
CPU time 0.86 seconds
Started Jul 24 04:25:44 PM PDT 24
Finished Jul 24 04:25:45 PM PDT 24
Peak memory 196660 kb
Host smart-d3ba23b8-9ca7-49fe-a7af-28c7aafccd98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927532624 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.2927532624
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.1871073283
Short name T50
Test name
Test status
Simulation time 56826236 ps
CPU time 0.56 seconds
Started Jul 24 04:23:51 PM PDT 24
Finished Jul 24 04:23:52 PM PDT 24
Peak memory 183144 kb
Host smart-aa4b535a-5c18-4346-9bff-ac35d25e62f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871073283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.1871073283
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.3616015551
Short name T527
Test name
Test status
Simulation time 41215663 ps
CPU time 0.56 seconds
Started Jul 24 04:23:52 PM PDT 24
Finished Jul 24 04:23:52 PM PDT 24
Peak memory 182668 kb
Host smart-02fffedf-4b64-4952-bd84-7a366af06eeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616015551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.3616015551
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.4281802180
Short name T551
Test name
Test status
Simulation time 90013584 ps
CPU time 0.65 seconds
Started Jul 24 04:25:21 PM PDT 24
Finished Jul 24 04:25:23 PM PDT 24
Peak memory 191976 kb
Host smart-12b27424-591a-4c80-98ab-cd396008cb80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281802180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.4281802180
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.3475398790
Short name T539
Test name
Test status
Simulation time 58609000 ps
CPU time 1.32 seconds
Started Jul 24 04:23:41 PM PDT 24
Finished Jul 24 04:23:43 PM PDT 24
Peak memory 197448 kb
Host smart-3265e315-d6b7-4246-87df-d4f7d0de0faa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475398790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.3475398790
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.3095371579
Short name T554
Test name
Test status
Simulation time 52003882 ps
CPU time 0.92 seconds
Started Jul 24 04:21:59 PM PDT 24
Finished Jul 24 04:22:00 PM PDT 24
Peak memory 194056 kb
Host smart-481a6f02-2d92-4776-b390-e0b41e931544
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095371579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.3095371579
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.363408409
Short name T519
Test name
Test status
Simulation time 23161383 ps
CPU time 0.51 seconds
Started Jul 24 04:25:25 PM PDT 24
Finished Jul 24 04:25:26 PM PDT 24
Peak memory 182084 kb
Host smart-e1731431-f062-4526-a9e5-a26acee59661
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363408409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.363408409
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.2327647527
Short name T549
Test name
Test status
Simulation time 17612443 ps
CPU time 0.57 seconds
Started Jul 24 04:22:32 PM PDT 24
Finished Jul 24 04:22:33 PM PDT 24
Peak memory 182592 kb
Host smart-edc799c8-04a8-457e-b930-d5fc3b6ec79c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327647527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.2327647527
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.469077591
Short name T530
Test name
Test status
Simulation time 21350209 ps
CPU time 0.54 seconds
Started Jul 24 04:21:52 PM PDT 24
Finished Jul 24 04:21:53 PM PDT 24
Peak memory 182360 kb
Host smart-5f71da82-556e-4a5a-b451-2495299850ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469077591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.469077591
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.3426876320
Short name T467
Test name
Test status
Simulation time 14467040 ps
CPU time 0.58 seconds
Started Jul 24 04:22:35 PM PDT 24
Finished Jul 24 04:22:35 PM PDT 24
Peak memory 182368 kb
Host smart-cffbea88-0811-4b82-8454-98a03c439f3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426876320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.3426876320
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2536650324
Short name T484
Test name
Test status
Simulation time 63780163 ps
CPU time 0.54 seconds
Started Jul 24 04:25:46 PM PDT 24
Finished Jul 24 04:25:48 PM PDT 24
Peak memory 182324 kb
Host smart-47e824f3-ac30-4003-9db0-201e5c93222a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536650324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.2536650324
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.1006356814
Short name T488
Test name
Test status
Simulation time 55214795 ps
CPU time 0.6 seconds
Started Jul 24 04:25:26 PM PDT 24
Finished Jul 24 04:25:27 PM PDT 24
Peak memory 181096 kb
Host smart-820aee88-9d84-4e4a-802a-1a1a67bbddf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006356814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.1006356814
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1753055624
Short name T518
Test name
Test status
Simulation time 51211858 ps
CPU time 0.55 seconds
Started Jul 24 04:25:25 PM PDT 24
Finished Jul 24 04:25:26 PM PDT 24
Peak memory 182604 kb
Host smart-d53958d1-ffca-4126-8701-b33fcf2e97b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753055624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.1753055624
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.1598668489
Short name T474
Test name
Test status
Simulation time 13622581 ps
CPU time 0.57 seconds
Started Jul 24 04:25:25 PM PDT 24
Finished Jul 24 04:25:26 PM PDT 24
Peak memory 182688 kb
Host smart-187d42c9-2f1b-402b-a099-7b00b630d585
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598668489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.1598668489
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1116522933
Short name T526
Test name
Test status
Simulation time 48864866 ps
CPU time 0.54 seconds
Started Jul 24 04:25:21 PM PDT 24
Finished Jul 24 04:25:22 PM PDT 24
Peak memory 182688 kb
Host smart-9f1f7228-831e-42ad-9051-2fa2be5ae268
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116522933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.1116522933
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.3656584034
Short name T477
Test name
Test status
Simulation time 25754272 ps
CPU time 0.54 seconds
Started Jul 24 04:25:48 PM PDT 24
Finished Jul 24 04:25:49 PM PDT 24
Peak memory 182100 kb
Host smart-ccfc71e7-c25b-4924-87c1-31702875541c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656584034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.3656584034
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3296107179
Short name T510
Test name
Test status
Simulation time 27543170 ps
CPU time 0.7 seconds
Started Jul 24 04:22:19 PM PDT 24
Finished Jul 24 04:22:20 PM PDT 24
Peak memory 182692 kb
Host smart-ecc50762-5b95-40e5-8a99-e6b45486747f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296107179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.3296107179
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.4139777591
Short name T491
Test name
Test status
Simulation time 2798366476 ps
CPU time 1.48 seconds
Started Jul 24 04:25:49 PM PDT 24
Finished Jul 24 04:25:51 PM PDT 24
Peak memory 193192 kb
Host smart-68c40919-5d7a-4d9f-907f-abe6b55cd823
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139777591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.4139777591
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.1214598150
Short name T466
Test name
Test status
Simulation time 51622647 ps
CPU time 0.56 seconds
Started Jul 24 04:21:50 PM PDT 24
Finished Jul 24 04:21:51 PM PDT 24
Peak memory 182928 kb
Host smart-ad31e7b3-d305-4758-a6f0-64db6d25858b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214598150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.1214598150
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.807676518
Short name T547
Test name
Test status
Simulation time 181813682 ps
CPU time 0.9 seconds
Started Jul 24 04:25:28 PM PDT 24
Finished Jul 24 04:25:30 PM PDT 24
Peak memory 196460 kb
Host smart-f6509cf9-0b9c-4f1f-96aa-0500e16c66c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807676518 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.807676518
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.852342687
Short name T108
Test name
Test status
Simulation time 13997543 ps
CPU time 0.63 seconds
Started Jul 24 04:22:19 PM PDT 24
Finished Jul 24 04:22:20 PM PDT 24
Peak memory 182724 kb
Host smart-c7a40c02-98bf-4a8b-b652-f6cf074c9a7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852342687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.852342687
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.2586318014
Short name T535
Test name
Test status
Simulation time 27203379 ps
CPU time 0.53 seconds
Started Jul 24 04:25:48 PM PDT 24
Finished Jul 24 04:25:49 PM PDT 24
Peak memory 182132 kb
Host smart-59fbf914-3acb-432e-a83a-b9230c9e7f65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586318014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.2586318014
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.3703966853
Short name T112
Test name
Test status
Simulation time 16625827 ps
CPU time 0.61 seconds
Started Jul 24 04:24:27 PM PDT 24
Finished Jul 24 04:24:28 PM PDT 24
Peak memory 192008 kb
Host smart-2eb9c1b1-3ad5-4b5f-bc54-265647fcea0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703966853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.3703966853
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3104567121
Short name T470
Test name
Test status
Simulation time 34216300 ps
CPU time 1.59 seconds
Started Jul 24 04:21:53 PM PDT 24
Finished Jul 24 04:21:55 PM PDT 24
Peak memory 197528 kb
Host smart-4aa23e5d-55a4-4ac7-ab24-b18d31ac98ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104567121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.3104567121
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.1465497731
Short name T582
Test name
Test status
Simulation time 110826338 ps
CPU time 1.34 seconds
Started Jul 24 04:22:17 PM PDT 24
Finished Jul 24 04:22:18 PM PDT 24
Peak memory 195228 kb
Host smart-22f8cbad-85ff-4ad5-afbb-c5443adeeb87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465497731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.1465497731
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.812855835
Short name T493
Test name
Test status
Simulation time 41531257 ps
CPU time 0.53 seconds
Started Jul 24 04:22:05 PM PDT 24
Finished Jul 24 04:22:05 PM PDT 24
Peak memory 182132 kb
Host smart-9b53e0e9-3a96-4ecb-ab8d-a7b77758fd07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812855835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.812855835
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.2659380821
Short name T571
Test name
Test status
Simulation time 12931751 ps
CPU time 0.58 seconds
Started Jul 24 04:22:35 PM PDT 24
Finished Jul 24 04:22:35 PM PDT 24
Peak memory 182656 kb
Host smart-3302f002-2fb9-4af8-b056-95bbef2612f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659380821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.2659380821
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.3631347569
Short name T578
Test name
Test status
Simulation time 37906532 ps
CPU time 0.56 seconds
Started Jul 24 04:25:09 PM PDT 24
Finished Jul 24 04:25:10 PM PDT 24
Peak memory 181600 kb
Host smart-b3d3cc7b-68b3-4dae-b1ee-45c8276d5cda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631347569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.3631347569
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1505996172
Short name T456
Test name
Test status
Simulation time 11313649 ps
CPU time 0.53 seconds
Started Jul 24 04:23:01 PM PDT 24
Finished Jul 24 04:23:01 PM PDT 24
Peak memory 182340 kb
Host smart-4160d858-a96a-4c4e-8e25-18ba94467a93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505996172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.1505996172
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.2168704539
Short name T558
Test name
Test status
Simulation time 35874693 ps
CPU time 0.51 seconds
Started Jul 24 04:25:10 PM PDT 24
Finished Jul 24 04:25:11 PM PDT 24
Peak memory 181812 kb
Host smart-722a4cb9-9ff7-4b28-b131-9c9b3ea5fbcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168704539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.2168704539
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2461832106
Short name T457
Test name
Test status
Simulation time 44231074 ps
CPU time 0.52 seconds
Started Jul 24 04:25:52 PM PDT 24
Finished Jul 24 04:25:53 PM PDT 24
Peak memory 182428 kb
Host smart-97fdb192-bd05-4008-8382-dcfbe66c7f42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461832106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.2461832106
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.4122881520
Short name T563
Test name
Test status
Simulation time 72910771 ps
CPU time 0.5 seconds
Started Jul 24 04:25:52 PM PDT 24
Finished Jul 24 04:25:53 PM PDT 24
Peak memory 181848 kb
Host smart-f6993338-4b70-409c-9c79-d9e0a8cb9b82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122881520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.4122881520
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.3374179842
Short name T498
Test name
Test status
Simulation time 21592938 ps
CPU time 0.54 seconds
Started Jul 24 04:22:04 PM PDT 24
Finished Jul 24 04:22:05 PM PDT 24
Peak memory 182168 kb
Host smart-7e74115e-fb37-4a74-84f4-53977757fd79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374179842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.3374179842
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.3350808716
Short name T481
Test name
Test status
Simulation time 48600870 ps
CPU time 0.51 seconds
Started Jul 24 04:25:10 PM PDT 24
Finished Jul 24 04:25:11 PM PDT 24
Peak memory 181860 kb
Host smart-cc354402-470f-4604-8993-7f68efa9d2a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350808716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.3350808716
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.3805153063
Short name T523
Test name
Test status
Simulation time 22502873 ps
CPU time 0.59 seconds
Started Jul 24 04:25:09 PM PDT 24
Finished Jul 24 04:25:10 PM PDT 24
Peak memory 181200 kb
Host smart-0b635cc5-45b0-418d-a6f0-9da746596f29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805153063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.3805153063
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.526775575
Short name T504
Test name
Test status
Simulation time 61782350 ps
CPU time 0.75 seconds
Started Jul 24 04:21:52 PM PDT 24
Finished Jul 24 04:21:53 PM PDT 24
Peak memory 182748 kb
Host smart-52543a97-a968-4ad5-976c-9d4873c5a720
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526775575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alias
ing.526775575
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.39727556
Short name T114
Test name
Test status
Simulation time 197022877 ps
CPU time 1.42 seconds
Started Jul 24 04:25:48 PM PDT 24
Finished Jul 24 04:25:50 PM PDT 24
Peak memory 190752 kb
Host smart-cac912c8-dc82-42e8-84d6-98bc915d7984
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39727556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_ba
sh.39727556
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.4083953474
Short name T52
Test name
Test status
Simulation time 52357831 ps
CPU time 0.55 seconds
Started Jul 24 04:22:35 PM PDT 24
Finished Jul 24 04:22:36 PM PDT 24
Peak memory 182784 kb
Host smart-72fbb917-0e24-4aa9-90dc-e2c565fe8eea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083953474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.4083953474
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.1159978295
Short name T560
Test name
Test status
Simulation time 147289330 ps
CPU time 1.01 seconds
Started Jul 24 04:22:48 PM PDT 24
Finished Jul 24 04:22:49 PM PDT 24
Peak memory 197424 kb
Host smart-a13474ea-1aac-46ce-a4ff-6cf1a6edce8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159978295 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.1159978295
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.1215976408
Short name T480
Test name
Test status
Simulation time 13497683 ps
CPU time 0.56 seconds
Started Jul 24 04:25:28 PM PDT 24
Finished Jul 24 04:25:29 PM PDT 24
Peak memory 182588 kb
Host smart-e5590882-ab10-49a6-820b-5c8d9aa41866
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215976408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.1215976408
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.3238263859
Short name T461
Test name
Test status
Simulation time 27967183 ps
CPU time 0.52 seconds
Started Jul 24 04:25:59 PM PDT 24
Finished Jul 24 04:26:00 PM PDT 24
Peak memory 182456 kb
Host smart-300382a5-b710-4141-b751-0d7562b752ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238263859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.3238263859
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.4059104975
Short name T113
Test name
Test status
Simulation time 72497710 ps
CPU time 0.66 seconds
Started Jul 24 04:25:45 PM PDT 24
Finished Jul 24 04:25:47 PM PDT 24
Peak memory 191680 kb
Host smart-bdc569c3-f334-4d95-8af4-d4e8c97e2f69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059104975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.4059104975
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2154612017
Short name T489
Test name
Test status
Simulation time 21553186 ps
CPU time 1.21 seconds
Started Jul 24 04:23:25 PM PDT 24
Finished Jul 24 04:23:26 PM PDT 24
Peak memory 197296 kb
Host smart-7739712f-3989-417c-8c77-c580f063eb35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154612017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.2154612017
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.3704584631
Short name T572
Test name
Test status
Simulation time 654707644 ps
CPU time 1.33 seconds
Started Jul 24 04:22:04 PM PDT 24
Finished Jul 24 04:22:06 PM PDT 24
Peak memory 195164 kb
Host smart-55951cd2-a975-4677-a89d-336f06126103
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704584631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.3704584631
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.1231328347
Short name T515
Test name
Test status
Simulation time 16397872 ps
CPU time 0.57 seconds
Started Jul 24 04:25:50 PM PDT 24
Finished Jul 24 04:25:51 PM PDT 24
Peak memory 182592 kb
Host smart-330f4573-78ef-4b8d-affe-1c13c41da506
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231328347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.1231328347
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.1566245329
Short name T546
Test name
Test status
Simulation time 39895121 ps
CPU time 0.5 seconds
Started Jul 24 04:25:49 PM PDT 24
Finished Jul 24 04:25:50 PM PDT 24
Peak memory 181944 kb
Host smart-fbef4bf2-bf7b-49d0-843d-023b2de5d463
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566245329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.1566245329
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.2858783092
Short name T559
Test name
Test status
Simulation time 15716549 ps
CPU time 0.56 seconds
Started Jul 24 04:25:36 PM PDT 24
Finished Jul 24 04:25:37 PM PDT 24
Peak memory 182588 kb
Host smart-9796f8c8-990b-4275-8ecb-26c853b890ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858783092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.2858783092
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.3250145946
Short name T508
Test name
Test status
Simulation time 12230307 ps
CPU time 0.55 seconds
Started Jul 24 04:24:28 PM PDT 24
Finished Jul 24 04:24:29 PM PDT 24
Peak memory 182152 kb
Host smart-cb7d3c9e-cf96-42f4-b0cb-e9b89f642bfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250145946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.3250145946
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.2173415247
Short name T555
Test name
Test status
Simulation time 16278379 ps
CPU time 0.54 seconds
Started Jul 24 04:25:48 PM PDT 24
Finished Jul 24 04:25:49 PM PDT 24
Peak memory 182316 kb
Host smart-7cd925dd-1396-4b4c-a884-7ca1e4c6cf32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173415247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.2173415247
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.4125601177
Short name T533
Test name
Test status
Simulation time 24295443 ps
CPU time 0.53 seconds
Started Jul 24 04:25:49 PM PDT 24
Finished Jul 24 04:25:50 PM PDT 24
Peak memory 182352 kb
Host smart-34e58c19-7a89-42e1-ab82-654287bc9fad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125601177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.4125601177
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3663586030
Short name T575
Test name
Test status
Simulation time 11544105 ps
CPU time 0.53 seconds
Started Jul 24 04:25:41 PM PDT 24
Finished Jul 24 04:25:42 PM PDT 24
Peak memory 182444 kb
Host smart-bbee9a06-d7f1-4cd5-b6e2-6855b7982048
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663586030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.3663586030
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2740293797
Short name T475
Test name
Test status
Simulation time 44510810 ps
CPU time 0.51 seconds
Started Jul 24 04:25:40 PM PDT 24
Finished Jul 24 04:25:41 PM PDT 24
Peak memory 182300 kb
Host smart-17705184-13e3-4fa0-a200-46f49748e8ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740293797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.2740293797
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.3947013076
Short name T517
Test name
Test status
Simulation time 13931577 ps
CPU time 0.56 seconds
Started Jul 24 04:25:55 PM PDT 24
Finished Jul 24 04:25:56 PM PDT 24
Peak memory 182056 kb
Host smart-9f29b395-3d88-4348-8a9e-12a4654f81c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947013076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.3947013076
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.1298807510
Short name T468
Test name
Test status
Simulation time 30171025 ps
CPU time 0.55 seconds
Started Jul 24 04:22:04 PM PDT 24
Finished Jul 24 04:22:05 PM PDT 24
Peak memory 182724 kb
Host smart-b777bf1d-3bcd-4194-a583-a7fa26e7c513
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298807510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.1298807510
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.1202976944
Short name T511
Test name
Test status
Simulation time 104961621 ps
CPU time 0.75 seconds
Started Jul 24 04:25:03 PM PDT 24
Finished Jul 24 04:25:05 PM PDT 24
Peak memory 194268 kb
Host smart-f2284a2b-52d3-46c4-98f6-de1c078c5567
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202976944 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.1202976944
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.2857381719
Short name T51
Test name
Test status
Simulation time 16773044 ps
CPU time 0.59 seconds
Started Jul 24 04:25:39 PM PDT 24
Finished Jul 24 04:25:40 PM PDT 24
Peak memory 182708 kb
Host smart-8b9aeaad-4499-43ce-a071-679bacd62634
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857381719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.2857381719
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1577211023
Short name T458
Test name
Test status
Simulation time 40073160 ps
CPU time 0.54 seconds
Started Jul 24 04:25:20 PM PDT 24
Finished Jul 24 04:25:21 PM PDT 24
Peak memory 181704 kb
Host smart-28302b81-7bd5-4c08-98b0-31d389098a05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577211023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.1577211023
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2595717099
Short name T90
Test name
Test status
Simulation time 73335031 ps
CPU time 0.64 seconds
Started Jul 24 04:25:09 PM PDT 24
Finished Jul 24 04:25:11 PM PDT 24
Peak memory 192884 kb
Host smart-5ccb84ae-414d-4e4d-9865-695cbb4c5572
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595717099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.2595717099
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.289608022
Short name T545
Test name
Test status
Simulation time 155409060 ps
CPU time 1.68 seconds
Started Jul 24 04:22:24 PM PDT 24
Finished Jul 24 04:22:26 PM PDT 24
Peak memory 197532 kb
Host smart-317a3a15-82a4-4cb7-92b6-0d8e2828937b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289608022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.289608022
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3123341807
Short name T116
Test name
Test status
Simulation time 72414479 ps
CPU time 1.07 seconds
Started Jul 24 04:22:58 PM PDT 24
Finished Jul 24 04:23:00 PM PDT 24
Peak memory 195112 kb
Host smart-ce0a2ee4-c457-47d1-a3f9-3a9e95852a25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123341807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.3123341807
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3956537464
Short name T543
Test name
Test status
Simulation time 16985609 ps
CPU time 0.85 seconds
Started Jul 24 04:21:12 PM PDT 24
Finished Jul 24 04:21:13 PM PDT 24
Peak memory 196552 kb
Host smart-d153da25-a101-44f3-8a4b-0a8e646860a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956537464 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.3956537464
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.183956697
Short name T465
Test name
Test status
Simulation time 16389980 ps
CPU time 0.55 seconds
Started Jul 24 04:25:21 PM PDT 24
Finished Jul 24 04:25:22 PM PDT 24
Peak memory 182572 kb
Host smart-6abdf81c-6127-4dc5-a932-1255a67932d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183956697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.183956697
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.2393680242
Short name T522
Test name
Test status
Simulation time 56034843 ps
CPU time 0.69 seconds
Started Jul 24 04:25:38 PM PDT 24
Finished Jul 24 04:25:40 PM PDT 24
Peak memory 192592 kb
Host smart-5001ddb8-4683-4623-8480-443ca299b1b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393680242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.2393680242
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.4011688824
Short name T63
Test name
Test status
Simulation time 575949824 ps
CPU time 2.4 seconds
Started Jul 24 04:25:20 PM PDT 24
Finished Jul 24 04:25:22 PM PDT 24
Peak memory 197480 kb
Host smart-b8cfe80a-00bd-468e-b71b-3a1a641e66fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011688824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.4011688824
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.905216542
Short name T27
Test name
Test status
Simulation time 453683386 ps
CPU time 1.4 seconds
Started Jul 24 04:23:22 PM PDT 24
Finished Jul 24 04:23:23 PM PDT 24
Peak memory 195132 kb
Host smart-ef0ea230-8b06-45d8-b580-aa0b95e2b1be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905216542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_int
g_err.905216542
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.1373941520
Short name T463
Test name
Test status
Simulation time 33998299 ps
CPU time 0.89 seconds
Started Jul 24 04:25:31 PM PDT 24
Finished Jul 24 04:25:32 PM PDT 24
Peak memory 196500 kb
Host smart-9d15987b-8e9d-4da9-8266-407f5ad7ee66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373941520 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.1373941520
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.3979675578
Short name T104
Test name
Test status
Simulation time 14242377 ps
CPU time 0.55 seconds
Started Jul 24 04:25:06 PM PDT 24
Finished Jul 24 04:25:07 PM PDT 24
Peak memory 182444 kb
Host smart-375a76fc-ccf7-4633-ab1c-d56bf986466f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979675578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.3979675578
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.2125060042
Short name T557
Test name
Test status
Simulation time 95246539 ps
CPU time 0.54 seconds
Started Jul 24 04:24:02 PM PDT 24
Finished Jul 24 04:24:03 PM PDT 24
Peak memory 182536 kb
Host smart-bd5e5cc4-37d2-4934-93ed-112dc4d4b023
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125060042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.2125060042
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.827385450
Short name T92
Test name
Test status
Simulation time 64105410 ps
CPU time 0.62 seconds
Started Jul 24 04:22:00 PM PDT 24
Finished Jul 24 04:22:01 PM PDT 24
Peak memory 192032 kb
Host smart-162ad31f-c9bd-4582-9b02-8cc07297ac0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827385450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_tim
er_same_csr_outstanding.827385450
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.4019755014
Short name T544
Test name
Test status
Simulation time 144528290 ps
CPU time 2.78 seconds
Started Jul 24 04:25:41 PM PDT 24
Finished Jul 24 04:25:44 PM PDT 24
Peak memory 197380 kb
Host smart-2bdd2593-27c4-42b4-93a8-57ec2795bd67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019755014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.4019755014
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.1170403252
Short name T118
Test name
Test status
Simulation time 111292576 ps
CPU time 1.33 seconds
Started Jul 24 04:25:27 PM PDT 24
Finished Jul 24 04:25:29 PM PDT 24
Peak memory 193296 kb
Host smart-1b7ace91-de64-46c4-ab43-e48b2a4243a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170403252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.1170403252
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.1146018086
Short name T48
Test name
Test status
Simulation time 140673663 ps
CPU time 0.87 seconds
Started Jul 24 04:25:42 PM PDT 24
Finished Jul 24 04:25:44 PM PDT 24
Peak memory 196816 kb
Host smart-d9e47a7f-86cd-4b47-8af0-32c4db3ad4b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146018086 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.1146018086
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.3886665056
Short name T32
Test name
Test status
Simulation time 12978777 ps
CPU time 0.54 seconds
Started Jul 24 04:23:45 PM PDT 24
Finished Jul 24 04:23:46 PM PDT 24
Peak memory 182756 kb
Host smart-11304404-8de1-4d9d-85eb-2b50865832ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886665056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.3886665056
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.3968217491
Short name T469
Test name
Test status
Simulation time 19812160 ps
CPU time 0.5 seconds
Started Jul 24 04:25:30 PM PDT 24
Finished Jul 24 04:25:31 PM PDT 24
Peak memory 181816 kb
Host smart-9468f2c9-d329-43f3-8669-bb868cc2faf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968217491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.3968217491
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.2500653030
Short name T486
Test name
Test status
Simulation time 69977034 ps
CPU time 0.67 seconds
Started Jul 24 04:21:54 PM PDT 24
Finished Jul 24 04:21:55 PM PDT 24
Peak memory 191988 kb
Host smart-dadb2c75-7fee-4897-a836-06b18f9f6ba5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500653030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.2500653030
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.817786095
Short name T520
Test name
Test status
Simulation time 480631120 ps
CPU time 2.32 seconds
Started Jul 24 04:21:35 PM PDT 24
Finished Jul 24 04:21:38 PM PDT 24
Peak memory 197512 kb
Host smart-96845ab5-ee10-4dba-a5eb-8e8798ed9a91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817786095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.817786095
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.897906301
Short name T509
Test name
Test status
Simulation time 26470922 ps
CPU time 0.74 seconds
Started Jul 24 04:25:05 PM PDT 24
Finished Jul 24 04:25:07 PM PDT 24
Peak memory 194028 kb
Host smart-ad226a86-cfeb-41b9-bb23-61244ce88151
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897906301 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.897906301
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.382457454
Short name T103
Test name
Test status
Simulation time 19789152 ps
CPU time 0.55 seconds
Started Jul 24 04:22:41 PM PDT 24
Finished Jul 24 04:22:41 PM PDT 24
Peak memory 182772 kb
Host smart-0bf0c349-2345-4894-91b7-85cfdf49a72d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382457454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.382457454
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.4097411564
Short name T577
Test name
Test status
Simulation time 39461144 ps
CPU time 0.55 seconds
Started Jul 24 04:21:52 PM PDT 24
Finished Jul 24 04:21:52 PM PDT 24
Peak memory 181876 kb
Host smart-7a2c666c-77d9-4480-b58d-8a30548c5a80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097411564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.4097411564
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1518784242
Short name T513
Test name
Test status
Simulation time 18046506 ps
CPU time 0.71 seconds
Started Jul 24 04:25:20 PM PDT 24
Finished Jul 24 04:25:21 PM PDT 24
Peak memory 193496 kb
Host smart-bb96e8f5-ffb7-4f0b-8650-955e8132ddf5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518784242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.1518784242
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.149911311
Short name T512
Test name
Test status
Simulation time 44143443 ps
CPU time 0.91 seconds
Started Jul 24 04:25:27 PM PDT 24
Finished Jul 24 04:25:29 PM PDT 24
Peak memory 189992 kb
Host smart-c4088fe1-8050-492b-8481-7f295e206b27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149911311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.149911311
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3521865715
Short name T490
Test name
Test status
Simulation time 50414431 ps
CPU time 0.83 seconds
Started Jul 24 04:22:20 PM PDT 24
Finished Jul 24 04:22:21 PM PDT 24
Peak memory 193408 kb
Host smart-48eca68e-febb-4963-bce4-c0b4a13cb5f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521865715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.3521865715
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.3069303038
Short name T206
Test name
Test status
Simulation time 1249203197089 ps
CPU time 449.87 seconds
Started Jul 24 04:23:59 PM PDT 24
Finished Jul 24 04:31:29 PM PDT 24
Peak memory 183400 kb
Host smart-5821233f-5d6e-42ad-b5d6-211fe62e0d87
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069303038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.3069303038
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.3418081572
Short name T367
Test name
Test status
Simulation time 23147949172 ps
CPU time 35.42 seconds
Started Jul 24 04:24:32 PM PDT 24
Finished Jul 24 04:25:07 PM PDT 24
Peak memory 183368 kb
Host smart-2bba8f20-bd10-422c-a81a-ea4ec56a591a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418081572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.3418081572
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.2528447301
Short name T330
Test name
Test status
Simulation time 32882823493 ps
CPU time 10.99 seconds
Started Jul 24 04:21:35 PM PDT 24
Finished Jul 24 04:21:46 PM PDT 24
Peak memory 183328 kb
Host smart-18ec0733-2f71-47ab-9cc7-2624541b8833
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528447301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.2528447301
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.818154177
Short name T339
Test name
Test status
Simulation time 128822475357 ps
CPU time 281.24 seconds
Started Jul 24 04:25:43 PM PDT 24
Finished Jul 24 04:30:26 PM PDT 24
Peak memory 190768 kb
Host smart-31865644-7f93-4000-bcc2-e064a95e06c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818154177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.818154177
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.3455555366
Short name T24
Test name
Test status
Simulation time 103750683668 ps
CPU time 37.43 seconds
Started Jul 24 04:25:48 PM PDT 24
Finished Jul 24 04:26:26 PM PDT 24
Peak memory 183160 kb
Host smart-b0b245ca-c977-4acf-a294-c7d64eefed7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455555366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
3455555366
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.643062674
Short name T420
Test name
Test status
Simulation time 6762429978 ps
CPU time 12.26 seconds
Started Jul 24 04:25:26 PM PDT 24
Finished Jul 24 04:25:39 PM PDT 24
Peak memory 183032 kb
Host smart-3cf84693-44b1-47a7-a831-e0c5757769a3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643062674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.rv_timer_cfg_update_on_fly.643062674
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.1944771368
Short name T411
Test name
Test status
Simulation time 45221140296 ps
CPU time 59.03 seconds
Started Jul 24 04:25:41 PM PDT 24
Finished Jul 24 04:26:41 PM PDT 24
Peak memory 183308 kb
Host smart-8f054817-e2bd-43a1-bdba-95fd658b7482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944771368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.1944771368
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.79962682
Short name T344
Test name
Test status
Simulation time 70933362973 ps
CPU time 116.84 seconds
Started Jul 24 04:25:47 PM PDT 24
Finished Jul 24 04:27:45 PM PDT 24
Peak memory 191252 kb
Host smart-ebb810d0-9f29-4214-9998-4bef6e6e96c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79962682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.79962682
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.3859679713
Short name T419
Test name
Test status
Simulation time 93518286065 ps
CPU time 74.87 seconds
Started Jul 24 04:24:41 PM PDT 24
Finished Jul 24 04:25:57 PM PDT 24
Peak memory 189924 kb
Host smart-3268d3cd-fb6d-4b0b-96c2-ebb988eac1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859679713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.3859679713
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.1190485084
Short name T15
Test name
Test status
Simulation time 208981782 ps
CPU time 0.82 seconds
Started Jul 24 04:21:11 PM PDT 24
Finished Jul 24 04:21:13 PM PDT 24
Peak memory 214120 kb
Host smart-a5996851-6566-4aa5-8cfc-2464be412311
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190485084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.1190485084
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.274066404
Short name T380
Test name
Test status
Simulation time 44160505991 ps
CPU time 62.91 seconds
Started Jul 24 04:25:26 PM PDT 24
Finished Jul 24 04:26:30 PM PDT 24
Peak memory 183128 kb
Host smart-119c6552-a147-410a-8eb7-8bd5ede719bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274066404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.274066404
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.1497658242
Short name T393
Test name
Test status
Simulation time 28034063274 ps
CPU time 17.26 seconds
Started Jul 24 04:25:54 PM PDT 24
Finished Jul 24 04:26:12 PM PDT 24
Peak memory 183316 kb
Host smart-918d21c3-bdb6-460b-8343-4955b04eb0a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497658242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.1497658242
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.4235714902
Short name T434
Test name
Test status
Simulation time 128811628959 ps
CPU time 53.92 seconds
Started Jul 24 04:22:01 PM PDT 24
Finished Jul 24 04:22:55 PM PDT 24
Peak memory 195224 kb
Host smart-d10233cb-a6d3-4ad0-906d-4174257e060a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235714902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.4235714902
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/101.rv_timer_random.3172983150
Short name T83
Test name
Test status
Simulation time 808768642713 ps
CPU time 364.3 seconds
Started Jul 24 04:25:54 PM PDT 24
Finished Jul 24 04:31:59 PM PDT 24
Peak memory 191464 kb
Host smart-98b65c14-6200-4833-84e5-9f684ce791cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172983150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.3172983150
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.908560028
Short name T138
Test name
Test status
Simulation time 53976264430 ps
CPU time 38.17 seconds
Started Jul 24 04:26:04 PM PDT 24
Finished Jul 24 04:26:42 PM PDT 24
Peak memory 183148 kb
Host smart-7adc5d37-424f-4969-b37b-6e9e1e054ac9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908560028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.908560028
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.224859376
Short name T157
Test name
Test status
Simulation time 176112953771 ps
CPU time 362.81 seconds
Started Jul 24 04:26:00 PM PDT 24
Finished Jul 24 04:32:03 PM PDT 24
Peak memory 191536 kb
Host smart-e98725f5-3c5e-4c6a-a843-26623bc5ae9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224859376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.224859376
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.2361902237
Short name T160
Test name
Test status
Simulation time 203563442560 ps
CPU time 254.05 seconds
Started Jul 24 04:25:58 PM PDT 24
Finished Jul 24 04:30:12 PM PDT 24
Peak memory 191600 kb
Host smart-8a1f95f6-def1-47c9-a8f1-3b44627ece06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361902237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.2361902237
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.2775670265
Short name T308
Test name
Test status
Simulation time 201964526906 ps
CPU time 161.22 seconds
Started Jul 24 04:26:06 PM PDT 24
Finished Jul 24 04:28:48 PM PDT 24
Peak memory 191536 kb
Host smart-28dbca41-6b0b-4e6f-a0da-fc17ec7c62af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775670265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.2775670265
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.1661419420
Short name T164
Test name
Test status
Simulation time 158425714255 ps
CPU time 656.95 seconds
Started Jul 24 04:26:04 PM PDT 24
Finished Jul 24 04:37:01 PM PDT 24
Peak memory 191388 kb
Host smart-abee374b-375b-41d1-a917-3592be03e4cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661419420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.1661419420
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.2144939568
Short name T174
Test name
Test status
Simulation time 500369465837 ps
CPU time 200.37 seconds
Started Jul 24 04:26:00 PM PDT 24
Finished Jul 24 04:29:21 PM PDT 24
Peak memory 191536 kb
Host smart-8bdfe424-ddff-4a42-8de3-36b19fd4f264
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144939568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.2144939568
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.92115916
Short name T329
Test name
Test status
Simulation time 139354210347 ps
CPU time 48.04 seconds
Started Jul 24 04:25:59 PM PDT 24
Finished Jul 24 04:26:47 PM PDT 24
Peak memory 183148 kb
Host smart-013b5304-fdca-4173-b07e-73a3e9a72e41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92115916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.92115916
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.931555833
Short name T306
Test name
Test status
Simulation time 4425724116 ps
CPU time 8.06 seconds
Started Jul 24 04:22:04 PM PDT 24
Finished Jul 24 04:22:12 PM PDT 24
Peak memory 183376 kb
Host smart-72df33bf-cd29-404a-b6f5-3de0ffb9032b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931555833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.rv_timer_cfg_update_on_fly.931555833
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.4186648263
Short name T58
Test name
Test status
Simulation time 726681643542 ps
CPU time 292.71 seconds
Started Jul 24 04:25:40 PM PDT 24
Finished Jul 24 04:30:33 PM PDT 24
Peak memory 183268 kb
Host smart-78f0ddcd-8cbb-480b-aec7-12a0159b3cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186648263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.4186648263
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.2347090473
Short name T124
Test name
Test status
Simulation time 205610851493 ps
CPU time 383.02 seconds
Started Jul 24 04:25:27 PM PDT 24
Finished Jul 24 04:31:50 PM PDT 24
Peak memory 190080 kb
Host smart-97b49e36-d411-46bf-b286-2e015aa7a693
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347090473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.2347090473
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.2941030513
Short name T73
Test name
Test status
Simulation time 15246288958 ps
CPU time 37.54 seconds
Started Jul 24 04:25:28 PM PDT 24
Finished Jul 24 04:26:06 PM PDT 24
Peak memory 182980 kb
Host smart-1d74827d-bceb-44cb-922a-ac7759edf9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941030513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.2941030513
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/110.rv_timer_random.1442327393
Short name T86
Test name
Test status
Simulation time 59106645027 ps
CPU time 523.97 seconds
Started Jul 24 04:26:10 PM PDT 24
Finished Jul 24 04:34:54 PM PDT 24
Peak memory 183296 kb
Host smart-32e45223-129b-4b9c-a3f1-1b4008929025
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442327393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.1442327393
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.3987182294
Short name T171
Test name
Test status
Simulation time 399094766323 ps
CPU time 534.34 seconds
Started Jul 24 04:25:58 PM PDT 24
Finished Jul 24 04:34:52 PM PDT 24
Peak memory 191596 kb
Host smart-162798b9-926d-4333-bdeb-2bd042c47028
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987182294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.3987182294
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.524803649
Short name T76
Test name
Test status
Simulation time 2018347240751 ps
CPU time 1660.72 seconds
Started Jul 24 04:26:04 PM PDT 24
Finished Jul 24 04:53:45 PM PDT 24
Peak memory 191520 kb
Host smart-06ef1325-15c1-442c-a628-b97702f9a55c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524803649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.524803649
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.3781661710
Short name T261
Test name
Test status
Simulation time 69742599151 ps
CPU time 71.67 seconds
Started Jul 24 04:25:56 PM PDT 24
Finished Jul 24 04:27:08 PM PDT 24
Peak memory 183404 kb
Host smart-c19925b0-3e74-4dc9-9282-e4874697f87a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781661710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.3781661710
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.2525704758
Short name T55
Test name
Test status
Simulation time 81404634220 ps
CPU time 1373.45 seconds
Started Jul 24 04:25:58 PM PDT 24
Finished Jul 24 04:48:52 PM PDT 24
Peak memory 191540 kb
Host smart-6a0e5c17-00c5-4622-b9ce-e42cde97e085
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525704758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.2525704758
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.2343435860
Short name T26
Test name
Test status
Simulation time 300204361186 ps
CPU time 416.53 seconds
Started Jul 24 04:26:04 PM PDT 24
Finished Jul 24 04:33:00 PM PDT 24
Peak memory 183188 kb
Host smart-294271d3-a250-4076-ab65-376672c685fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343435860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.2343435860
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.3301264193
Short name T125
Test name
Test status
Simulation time 253817957810 ps
CPU time 123.47 seconds
Started Jul 24 04:26:00 PM PDT 24
Finished Jul 24 04:28:04 PM PDT 24
Peak memory 191536 kb
Host smart-602ef337-6f16-420c-82b9-e5edd9ccaa1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301264193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.3301264193
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.852388231
Short name T148
Test name
Test status
Simulation time 804605338474 ps
CPU time 419.33 seconds
Started Jul 24 04:23:25 PM PDT 24
Finished Jul 24 04:30:25 PM PDT 24
Peak memory 183788 kb
Host smart-0f47465e-37ca-4e97-b4ad-cdb44406eedb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852388231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.rv_timer_cfg_update_on_fly.852388231
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.2022863669
Short name T390
Test name
Test status
Simulation time 788992004044 ps
CPU time 226.42 seconds
Started Jul 24 04:25:23 PM PDT 24
Finished Jul 24 04:29:10 PM PDT 24
Peak memory 182620 kb
Host smart-437c80c5-c338-433b-9ffb-870649686d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022863669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.2022863669
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.1294501586
Short name T221
Test name
Test status
Simulation time 2206232847264 ps
CPU time 790.93 seconds
Started Jul 24 04:25:27 PM PDT 24
Finished Jul 24 04:38:38 PM PDT 24
Peak memory 191152 kb
Host smart-c6e7f5c4-c014-441e-af7c-11c61e28d9fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294501586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.1294501586
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.3735232567
Short name T255
Test name
Test status
Simulation time 400397629 ps
CPU time 2.45 seconds
Started Jul 24 04:25:45 PM PDT 24
Finished Jul 24 04:25:48 PM PDT 24
Peak memory 181976 kb
Host smart-ac30d1aa-0ec7-4d71-8c9e-f0be777fc044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735232567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.3735232567
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all_with_rand_reset.612969844
Short name T38
Test name
Test status
Simulation time 8687412557 ps
CPU time 73.72 seconds
Started Jul 24 04:23:14 PM PDT 24
Finished Jul 24 04:24:28 PM PDT 24
Peak memory 195620 kb
Host smart-358c03f9-d570-426d-af46-d03d98565ca1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612969844 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all_with_rand_reset.612969844
Directory /workspace/12.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.rv_timer_random.1883691856
Short name T199
Test name
Test status
Simulation time 68393129490 ps
CPU time 41.11 seconds
Started Jul 24 04:26:06 PM PDT 24
Finished Jul 24 04:26:47 PM PDT 24
Peak memory 191440 kb
Host smart-43b30b7f-e77b-407d-876d-9393e2c3f1cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883691856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.1883691856
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.1285972168
Short name T289
Test name
Test status
Simulation time 71723778289 ps
CPU time 130.85 seconds
Started Jul 24 04:26:13 PM PDT 24
Finished Jul 24 04:28:24 PM PDT 24
Peak memory 191536 kb
Host smart-9c9086a2-5be4-4899-b380-c3c1eaca9846
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285972168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.1285972168
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.3084387145
Short name T294
Test name
Test status
Simulation time 50684602364 ps
CPU time 81.72 seconds
Started Jul 24 04:26:14 PM PDT 24
Finished Jul 24 04:27:36 PM PDT 24
Peak memory 191528 kb
Host smart-063a4d76-49d9-457d-add4-f040311419f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084387145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.3084387145
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.1989134442
Short name T150
Test name
Test status
Simulation time 93003193362 ps
CPU time 51.46 seconds
Started Jul 24 04:26:06 PM PDT 24
Finished Jul 24 04:26:57 PM PDT 24
Peak memory 191460 kb
Host smart-2818a09d-cf47-4b44-b2d8-8b1c12c9de27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989134442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.1989134442
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.2305240975
Short name T81
Test name
Test status
Simulation time 22194348015 ps
CPU time 32.42 seconds
Started Jul 24 04:26:06 PM PDT 24
Finished Jul 24 04:26:39 PM PDT 24
Peak memory 183336 kb
Host smart-f839f716-b8eb-479d-bae6-dfc4f121d91e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305240975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.2305240975
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.404760246
Short name T358
Test name
Test status
Simulation time 30953355149 ps
CPU time 211.76 seconds
Started Jul 24 04:26:05 PM PDT 24
Finished Jul 24 04:29:37 PM PDT 24
Peak memory 183252 kb
Host smart-5d4f1eec-56c2-47d9-9b1c-9676ed12d01e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404760246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.404760246
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.1005127668
Short name T188
Test name
Test status
Simulation time 424010091875 ps
CPU time 526.78 seconds
Started Jul 24 04:26:09 PM PDT 24
Finished Jul 24 04:34:57 PM PDT 24
Peak memory 191488 kb
Host smart-279513ea-91f2-4988-b9b9-ae774fac86eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005127668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.1005127668
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.2491871900
Short name T451
Test name
Test status
Simulation time 29424861182 ps
CPU time 42.86 seconds
Started Jul 24 04:26:14 PM PDT 24
Finished Jul 24 04:26:57 PM PDT 24
Peak memory 183340 kb
Host smart-d465d7a7-d82f-42be-8a89-9f328abd47f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491871900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.2491871900
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.1556202904
Short name T200
Test name
Test status
Simulation time 92383243447 ps
CPU time 425.47 seconds
Started Jul 24 04:26:02 PM PDT 24
Finished Jul 24 04:33:08 PM PDT 24
Peak memory 191464 kb
Host smart-20c92eaf-ec8d-434a-bc27-cec189cd244b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556202904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.1556202904
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.3850826682
Short name T190
Test name
Test status
Simulation time 205034640356 ps
CPU time 104.12 seconds
Started Jul 24 04:25:38 PM PDT 24
Finished Jul 24 04:27:22 PM PDT 24
Peak memory 183260 kb
Host smart-e695821f-c1e2-457b-940f-06774c614b81
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850826682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.3850826682
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.2343465779
Short name T375
Test name
Test status
Simulation time 86277151761 ps
CPU time 70.64 seconds
Started Jul 24 04:23:14 PM PDT 24
Finished Jul 24 04:24:25 PM PDT 24
Peak memory 183412 kb
Host smart-db087281-7e71-490a-86cc-c7f965dd0a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343465779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.2343465779
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.394496119
Short name T317
Test name
Test status
Simulation time 342249367017 ps
CPU time 391.32 seconds
Started Jul 24 04:25:39 PM PDT 24
Finished Jul 24 04:32:10 PM PDT 24
Peak memory 191452 kb
Host smart-4f03d21b-9399-4822-a77b-38f6c9128204
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394496119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.394496119
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.3502610246
Short name T414
Test name
Test status
Simulation time 296826464513 ps
CPU time 165.11 seconds
Started Jul 24 04:25:40 PM PDT 24
Finished Jul 24 04:28:26 PM PDT 24
Peak memory 193996 kb
Host smart-8f8a2622-6933-49db-b521-81ed7816f7f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502610246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.3502610246
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/132.rv_timer_random.1817850067
Short name T3
Test name
Test status
Simulation time 106884889673 ps
CPU time 91.2 seconds
Started Jul 24 04:26:13 PM PDT 24
Finished Jul 24 04:27:45 PM PDT 24
Peak memory 191536 kb
Host smart-16c9a49d-ca5d-42ef-94d0-8d6df1b0498e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817850067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.1817850067
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.3324589812
Short name T281
Test name
Test status
Simulation time 523833255185 ps
CPU time 695.62 seconds
Started Jul 24 04:26:10 PM PDT 24
Finished Jul 24 04:37:46 PM PDT 24
Peak memory 191624 kb
Host smart-79f3c97b-e822-4f9b-a6ec-c4592cdc0a32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324589812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.3324589812
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.2163651933
Short name T399
Test name
Test status
Simulation time 188260003349 ps
CPU time 92.89 seconds
Started Jul 24 04:26:14 PM PDT 24
Finished Jul 24 04:27:47 PM PDT 24
Peak memory 191540 kb
Host smart-855007d5-9631-4d5c-b373-38aeb53520d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163651933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.2163651933
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.1923736720
Short name T271
Test name
Test status
Simulation time 191934138898 ps
CPU time 620.93 seconds
Started Jul 24 04:26:13 PM PDT 24
Finished Jul 24 04:36:34 PM PDT 24
Peak memory 191544 kb
Host smart-c71449c8-84c0-49a2-967f-2a907da5c486
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923736720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.1923736720
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.3429164848
Short name T409
Test name
Test status
Simulation time 722169332461 ps
CPU time 482.65 seconds
Started Jul 24 04:26:05 PM PDT 24
Finished Jul 24 04:34:08 PM PDT 24
Peak memory 191528 kb
Host smart-9c457bc3-cb73-40f1-967a-6a608b06f683
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429164848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.3429164848
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.1558480209
Short name T275
Test name
Test status
Simulation time 85871877392 ps
CPU time 42.4 seconds
Started Jul 24 04:26:07 PM PDT 24
Finished Jul 24 04:26:49 PM PDT 24
Peak memory 191628 kb
Host smart-86a58ba4-5318-474b-b11d-0bb35b25eea8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558480209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.1558480209
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.3739822801
Short name T194
Test name
Test status
Simulation time 35891025388 ps
CPU time 71.4 seconds
Started Jul 24 04:26:01 PM PDT 24
Finished Jul 24 04:27:13 PM PDT 24
Peak memory 191440 kb
Host smart-409e1cea-04e4-4bc3-a873-af1cabbb1b96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739822801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.3739822801
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.2032856964
Short name T192
Test name
Test status
Simulation time 229685644431 ps
CPU time 402.88 seconds
Started Jul 24 04:25:41 PM PDT 24
Finished Jul 24 04:32:24 PM PDT 24
Peak memory 183008 kb
Host smart-f37e3a74-18f5-42ff-8154-419d5a812cc1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032856964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.2032856964
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.844477215
Short name T85
Test name
Test status
Simulation time 117029143009 ps
CPU time 155.82 seconds
Started Jul 24 04:23:53 PM PDT 24
Finished Jul 24 04:26:29 PM PDT 24
Peak memory 183372 kb
Host smart-37c6d0fe-ff7f-433c-969b-6ddfc524c732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844477215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.844477215
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.3694770777
Short name T1
Test name
Test status
Simulation time 63263800459 ps
CPU time 113.98 seconds
Started Jul 24 04:25:43 PM PDT 24
Finished Jul 24 04:27:37 PM PDT 24
Peak memory 190660 kb
Host smart-47d018d5-0d77-426c-8b6f-ef537d026cf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694770777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.3694770777
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.1571991619
Short name T25
Test name
Test status
Simulation time 4859797312 ps
CPU time 51.87 seconds
Started Jul 24 04:25:43 PM PDT 24
Finished Jul 24 04:26:36 PM PDT 24
Peak memory 193476 kb
Host smart-2a16fd23-5148-46e5-92cd-60f034963ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571991619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.1571991619
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.547339630
Short name T305
Test name
Test status
Simulation time 379673123984 ps
CPU time 522 seconds
Started Jul 24 04:22:22 PM PDT 24
Finished Jul 24 04:31:04 PM PDT 24
Peak memory 191548 kb
Host smart-59e03ae2-332b-488f-a987-5f3b886973f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547339630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all.
547339630
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all_with_rand_reset.1833361755
Short name T34
Test name
Test status
Simulation time 165080670248 ps
CPU time 532.3 seconds
Started Jul 24 04:22:24 PM PDT 24
Finished Jul 24 04:31:16 PM PDT 24
Peak memory 206260 kb
Host smart-9bb96ccf-ee35-41f7-982e-98e74298f6ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833361755 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all_with_rand_reset.1833361755
Directory /workspace/14.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.rv_timer_random.4236951987
Short name T361
Test name
Test status
Simulation time 33866273724 ps
CPU time 49.26 seconds
Started Jul 24 04:26:13 PM PDT 24
Finished Jul 24 04:27:02 PM PDT 24
Peak memory 191544 kb
Host smart-d53392b0-c878-4b4d-bf26-ad83becce1d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236951987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.4236951987
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.3496813430
Short name T322
Test name
Test status
Simulation time 542461570429 ps
CPU time 991.83 seconds
Started Jul 24 04:26:04 PM PDT 24
Finished Jul 24 04:42:36 PM PDT 24
Peak memory 191604 kb
Host smart-f00b223b-4174-4c5d-b5df-7e34703fa858
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496813430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.3496813430
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.3172609973
Short name T78
Test name
Test status
Simulation time 46318642956 ps
CPU time 68.59 seconds
Started Jul 24 04:26:16 PM PDT 24
Finished Jul 24 04:27:24 PM PDT 24
Peak memory 183472 kb
Host smart-029dbef3-8716-4b73-9f18-cb64af3d07c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172609973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.3172609973
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.3676803991
Short name T156
Test name
Test status
Simulation time 150160245878 ps
CPU time 76.02 seconds
Started Jul 24 04:26:10 PM PDT 24
Finished Jul 24 04:27:26 PM PDT 24
Peak memory 191624 kb
Host smart-5fb4f3b5-4224-49b6-a4b3-bcc46b347a53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676803991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.3676803991
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.3137054030
Short name T252
Test name
Test status
Simulation time 173501069061 ps
CPU time 934.4 seconds
Started Jul 24 04:26:14 PM PDT 24
Finished Jul 24 04:41:49 PM PDT 24
Peak memory 191536 kb
Host smart-0370515b-dff2-45fc-a097-943d51309166
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137054030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.3137054030
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.3953395157
Short name T286
Test name
Test status
Simulation time 46296567764 ps
CPU time 22.86 seconds
Started Jul 24 04:26:07 PM PDT 24
Finished Jul 24 04:26:30 PM PDT 24
Peak memory 183428 kb
Host smart-09763c49-78e5-4ace-ae7f-d9df31324a75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953395157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.3953395157
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.1697116110
Short name T403
Test name
Test status
Simulation time 306959495764 ps
CPU time 143.9 seconds
Started Jul 24 04:26:05 PM PDT 24
Finished Jul 24 04:28:30 PM PDT 24
Peak memory 191628 kb
Host smart-174a2378-8a42-4901-8f2f-7e0eb728c300
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697116110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.1697116110
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.465701069
Short name T137
Test name
Test status
Simulation time 577274409102 ps
CPU time 215.1 seconds
Started Jul 24 04:26:05 PM PDT 24
Finished Jul 24 04:29:41 PM PDT 24
Peak memory 191520 kb
Host smart-d9ac87bd-2445-41af-a56a-05fab770b348
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465701069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.465701069
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.3351509859
Short name T303
Test name
Test status
Simulation time 403622983818 ps
CPU time 225.59 seconds
Started Jul 24 04:26:10 PM PDT 24
Finished Jul 24 04:29:56 PM PDT 24
Peak memory 191616 kb
Host smart-f679ce0f-81fb-4f35-9d8b-35d867295255
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351509859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.3351509859
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.3300551052
Short name T369
Test name
Test status
Simulation time 509616533140 ps
CPU time 193.46 seconds
Started Jul 24 04:25:53 PM PDT 24
Finished Jul 24 04:29:07 PM PDT 24
Peak memory 183184 kb
Host smart-1ad05d0b-8bc1-4e6d-bdb7-f37ff1c09a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300551052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.3300551052
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.2827517240
Short name T263
Test name
Test status
Simulation time 1246695811128 ps
CPU time 484.51 seconds
Started Jul 24 04:25:45 PM PDT 24
Finished Jul 24 04:33:51 PM PDT 24
Peak memory 190276 kb
Host smart-422d1d11-f6b9-4e8f-9d36-71cee4838ae5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827517240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.2827517240
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.738309260
Short name T131
Test name
Test status
Simulation time 198348304942 ps
CPU time 153.98 seconds
Started Jul 24 04:25:54 PM PDT 24
Finished Jul 24 04:28:28 PM PDT 24
Peak memory 194832 kb
Host smart-57d3a853-3d1a-4030-b0f2-f6e9ee235add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738309260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.738309260
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/150.rv_timer_random.4171436941
Short name T360
Test name
Test status
Simulation time 147498690815 ps
CPU time 70.86 seconds
Started Jul 24 04:26:13 PM PDT 24
Finished Jul 24 04:27:24 PM PDT 24
Peak memory 183328 kb
Host smart-e307d5fc-8260-4b87-a357-82dcebccf0f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171436941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.4171436941
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.4161009114
Short name T396
Test name
Test status
Simulation time 10938251679 ps
CPU time 101.98 seconds
Started Jul 24 04:26:13 PM PDT 24
Finished Jul 24 04:27:55 PM PDT 24
Peak memory 183336 kb
Host smart-5be1132c-f8c5-4b1d-b9ce-aabc60757977
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161009114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.4161009114
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.2435721373
Short name T77
Test name
Test status
Simulation time 1096665305029 ps
CPU time 1740.11 seconds
Started Jul 24 04:26:03 PM PDT 24
Finished Jul 24 04:55:04 PM PDT 24
Peak memory 191464 kb
Host smart-09dda35c-0c99-48ec-9a85-25874e91004a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435721373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.2435721373
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.2816781404
Short name T228
Test name
Test status
Simulation time 129163584244 ps
CPU time 220.16 seconds
Started Jul 24 04:26:01 PM PDT 24
Finished Jul 24 04:29:41 PM PDT 24
Peak memory 191432 kb
Host smart-d646a75a-c3e4-4e2a-86f1-f7c852a78537
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816781404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.2816781404
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.3228764808
Short name T241
Test name
Test status
Simulation time 161345538332 ps
CPU time 133.52 seconds
Started Jul 24 04:26:09 PM PDT 24
Finished Jul 24 04:28:23 PM PDT 24
Peak memory 191624 kb
Host smart-d7772549-f45f-4177-b45f-6dd1cb459d23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228764808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.3228764808
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.2328037850
Short name T145
Test name
Test status
Simulation time 637429945974 ps
CPU time 331.14 seconds
Started Jul 24 04:26:13 PM PDT 24
Finished Jul 24 04:31:44 PM PDT 24
Peak memory 191544 kb
Host smart-c702b50f-e13b-49b3-b396-d66216604a3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328037850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.2328037850
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.357139877
Short name T291
Test name
Test status
Simulation time 588891262509 ps
CPU time 349.36 seconds
Started Jul 24 04:26:09 PM PDT 24
Finished Jul 24 04:31:59 PM PDT 24
Peak memory 191636 kb
Host smart-1ebba8ed-47b7-4e70-8142-42a30c28324e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357139877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.357139877
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.2382825894
Short name T347
Test name
Test status
Simulation time 127889133322 ps
CPU time 59.07 seconds
Started Jul 24 04:26:06 PM PDT 24
Finished Jul 24 04:27:05 PM PDT 24
Peak memory 183344 kb
Host smart-4ef84322-665a-40d2-98ed-8a330086ae33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382825894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.2382825894
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.2044475593
Short name T433
Test name
Test status
Simulation time 8511015542 ps
CPU time 8.62 seconds
Started Jul 24 04:23:33 PM PDT 24
Finished Jul 24 04:23:42 PM PDT 24
Peak memory 183532 kb
Host smart-38c45b42-5e85-4e70-8b69-08f797225de3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044475593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.2044475593
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.2206585890
Short name T407
Test name
Test status
Simulation time 141488375681 ps
CPU time 223.43 seconds
Started Jul 24 04:25:46 PM PDT 24
Finished Jul 24 04:29:30 PM PDT 24
Peak memory 183044 kb
Host smart-4c54f0b3-ff71-4929-b91b-57cd8611c697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206585890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.2206585890
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.3937202678
Short name T387
Test name
Test status
Simulation time 16906461 ps
CPU time 0.58 seconds
Started Jul 24 04:25:46 PM PDT 24
Finished Jul 24 04:25:47 PM PDT 24
Peak memory 182856 kb
Host smart-89694c1a-cb9d-4c1f-a8d8-dead75448223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937202678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.3937202678
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.1092474922
Short name T394
Test name
Test status
Simulation time 930742727278 ps
CPU time 389.05 seconds
Started Jul 24 04:22:17 PM PDT 24
Finished Jul 24 04:28:47 PM PDT 24
Peak memory 191548 kb
Host smart-5a4edda8-3d51-4d1d-ac5c-ae6df81ae630
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092474922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.1092474922
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/160.rv_timer_random.3083958147
Short name T343
Test name
Test status
Simulation time 350075572975 ps
CPU time 1660.25 seconds
Started Jul 24 04:26:11 PM PDT 24
Finished Jul 24 04:53:52 PM PDT 24
Peak memory 191400 kb
Host smart-24dd5803-2128-471e-8185-db919400bc3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083958147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.3083958147
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.601235538
Short name T146
Test name
Test status
Simulation time 163025148388 ps
CPU time 719.38 seconds
Started Jul 24 04:26:06 PM PDT 24
Finished Jul 24 04:38:06 PM PDT 24
Peak memory 193832 kb
Host smart-b35ab7d3-87d0-4bf4-9644-b501151b6e85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601235538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.601235538
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.2917264522
Short name T214
Test name
Test status
Simulation time 841168393647 ps
CPU time 420.28 seconds
Started Jul 24 04:26:06 PM PDT 24
Finished Jul 24 04:33:07 PM PDT 24
Peak memory 191432 kb
Host smart-d6af5bf0-71ec-4b19-b4c6-5fa731f29db4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917264522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.2917264522
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.2241960991
Short name T169
Test name
Test status
Simulation time 1057537355225 ps
CPU time 922.84 seconds
Started Jul 24 04:26:14 PM PDT 24
Finished Jul 24 04:41:37 PM PDT 24
Peak memory 191548 kb
Host smart-c7d5413a-6a24-450c-ae74-8eeb37c4aa1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241960991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.2241960991
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.2818846632
Short name T238
Test name
Test status
Simulation time 18093564624 ps
CPU time 35.53 seconds
Started Jul 24 04:26:11 PM PDT 24
Finished Jul 24 04:26:47 PM PDT 24
Peak memory 183288 kb
Host smart-288a4a45-32d2-4df4-9a2f-4be0b3847d87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818846632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.2818846632
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.1025974471
Short name T319
Test name
Test status
Simulation time 120049239856 ps
CPU time 198.27 seconds
Started Jul 24 04:26:07 PM PDT 24
Finished Jul 24 04:29:25 PM PDT 24
Peak memory 191544 kb
Host smart-e05c8f95-9bb5-4353-8736-02d3e55d58ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025974471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.1025974471
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.3067021819
Short name T74
Test name
Test status
Simulation time 76193662725 ps
CPU time 34.36 seconds
Started Jul 24 04:26:15 PM PDT 24
Finished Jul 24 04:26:49 PM PDT 24
Peak memory 191632 kb
Host smart-60ecd094-85ce-4bcb-9aa8-d2fe8ea7e1c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067021819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.3067021819
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.324326305
Short name T272
Test name
Test status
Simulation time 304395851886 ps
CPU time 478.68 seconds
Started Jul 24 04:26:12 PM PDT 24
Finished Jul 24 04:34:12 PM PDT 24
Peak memory 191556 kb
Host smart-f4d133e1-e140-47e2-9282-6e9bbcf9343c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324326305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.324326305
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.1626383999
Short name T257
Test name
Test status
Simulation time 450633929882 ps
CPU time 237.7 seconds
Started Jul 24 04:25:46 PM PDT 24
Finished Jul 24 04:29:44 PM PDT 24
Peak memory 182996 kb
Host smart-419fcccb-da00-4c53-89f4-f70145d5688d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626383999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.1626383999
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.774749742
Short name T395
Test name
Test status
Simulation time 412413868084 ps
CPU time 153.03 seconds
Started Jul 24 04:25:43 PM PDT 24
Finished Jul 24 04:28:17 PM PDT 24
Peak memory 183016 kb
Host smart-71b2eb5e-b2f9-46a6-ad61-f96572ac1102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774749742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.774749742
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.1521161769
Short name T290
Test name
Test status
Simulation time 766414166111 ps
CPU time 1864.47 seconds
Started Jul 24 04:22:21 PM PDT 24
Finished Jul 24 04:53:26 PM PDT 24
Peak memory 191572 kb
Host smart-41e000fe-a946-4438-96f7-12900d63ee01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521161769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.1521161769
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.3963261066
Short name T233
Test name
Test status
Simulation time 135395984829 ps
CPU time 152.6 seconds
Started Jul 24 04:25:58 PM PDT 24
Finished Jul 24 04:28:31 PM PDT 24
Peak memory 191492 kb
Host smart-7e9633d1-07d2-40e9-9897-c3bd5728a57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963261066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.3963261066
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.61622714
Short name T278
Test name
Test status
Simulation time 423297624136 ps
CPU time 732 seconds
Started Jul 24 04:23:11 PM PDT 24
Finished Jul 24 04:35:24 PM PDT 24
Peak memory 191552 kb
Host smart-4a4aa566-fb1a-4d93-a67a-8b79ed8aaa16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61622714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all.61622714
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/170.rv_timer_random.694040911
Short name T299
Test name
Test status
Simulation time 384688751267 ps
CPU time 648.03 seconds
Started Jul 24 04:26:06 PM PDT 24
Finished Jul 24 04:36:55 PM PDT 24
Peak memory 191556 kb
Host smart-fe1d750b-b044-42af-88d2-49f64fd0b1f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694040911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.694040911
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.1296088619
Short name T335
Test name
Test status
Simulation time 1043006923446 ps
CPU time 271.42 seconds
Started Jul 24 04:26:15 PM PDT 24
Finished Jul 24 04:30:47 PM PDT 24
Peak memory 191664 kb
Host smart-044edfee-0d73-4808-97f8-71b81b68980f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296088619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.1296088619
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.2366945922
Short name T442
Test name
Test status
Simulation time 33348019349 ps
CPU time 19.83 seconds
Started Jul 24 04:26:11 PM PDT 24
Finished Jul 24 04:26:31 PM PDT 24
Peak memory 191512 kb
Host smart-d4f3a4de-4ca0-4a8c-8fa3-e3d7fce9a03a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366945922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.2366945922
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.2630261924
Short name T234
Test name
Test status
Simulation time 64525337672 ps
CPU time 175.97 seconds
Started Jul 24 04:26:07 PM PDT 24
Finished Jul 24 04:29:03 PM PDT 24
Peak memory 191604 kb
Host smart-291ca32d-5c73-4250-9f44-aa0d21e2a788
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630261924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.2630261924
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.2887145824
Short name T62
Test name
Test status
Simulation time 480558302890 ps
CPU time 659.81 seconds
Started Jul 24 04:26:10 PM PDT 24
Finished Jul 24 04:37:11 PM PDT 24
Peak memory 191504 kb
Host smart-84c26300-d91a-42db-ad7b-85126f561083
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887145824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.2887145824
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.1449526055
Short name T452
Test name
Test status
Simulation time 240547784657 ps
CPU time 219.54 seconds
Started Jul 24 04:26:19 PM PDT 24
Finished Jul 24 04:29:59 PM PDT 24
Peak memory 191488 kb
Host smart-8ca2a60d-1997-47b4-a475-ca514864e0c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449526055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.1449526055
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.1283974305
Short name T315
Test name
Test status
Simulation time 89853026929 ps
CPU time 149.77 seconds
Started Jul 24 04:26:19 PM PDT 24
Finished Jul 24 04:28:48 PM PDT 24
Peak memory 191500 kb
Host smart-dd1c0bdc-cad1-4a6d-97bc-6e168a9faf6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283974305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.1283974305
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.4129906578
Short name T287
Test name
Test status
Simulation time 160876936059 ps
CPU time 1650.94 seconds
Started Jul 24 04:26:10 PM PDT 24
Finished Jul 24 04:53:42 PM PDT 24
Peak memory 191504 kb
Host smart-248363e6-6a81-4cb4-9a91-57f30e230aa2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129906578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.4129906578
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.1069826674
Short name T285
Test name
Test status
Simulation time 506003680153 ps
CPU time 242.29 seconds
Started Jul 24 04:25:06 PM PDT 24
Finished Jul 24 04:29:09 PM PDT 24
Peak memory 182016 kb
Host smart-d319384c-6b77-4391-be54-6b1c6d053cc7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069826674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.1069826674
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_random.1174069163
Short name T296
Test name
Test status
Simulation time 314774300107 ps
CPU time 164.83 seconds
Started Jul 24 04:25:09 PM PDT 24
Finished Jul 24 04:27:55 PM PDT 24
Peak memory 190296 kb
Host smart-368245e3-4c9f-4a69-bedc-45a0ca28075f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174069163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.1174069163
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.1308027699
Short name T363
Test name
Test status
Simulation time 183615116229 ps
CPU time 88.04 seconds
Started Jul 24 04:25:38 PM PDT 24
Finished Jul 24 04:27:07 PM PDT 24
Peak memory 190356 kb
Host smart-f0710f1f-26fb-4905-a9fc-f9470cf42138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308027699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.1308027699
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/181.rv_timer_random.3071487063
Short name T230
Test name
Test status
Simulation time 87067760920 ps
CPU time 72.44 seconds
Started Jul 24 04:26:10 PM PDT 24
Finished Jul 24 04:27:23 PM PDT 24
Peak memory 183344 kb
Host smart-32526e39-78ed-45df-87a4-b9c1b4d1bb76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071487063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.3071487063
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.983503613
Short name T359
Test name
Test status
Simulation time 414577813668 ps
CPU time 363.85 seconds
Started Jul 24 04:26:12 PM PDT 24
Finished Jul 24 04:32:16 PM PDT 24
Peak memory 191556 kb
Host smart-7bc37429-8394-4956-92b5-702d49c6cc55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983503613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.983503613
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.1141000665
Short name T227
Test name
Test status
Simulation time 47848990669 ps
CPU time 66.8 seconds
Started Jul 24 04:26:12 PM PDT 24
Finished Jul 24 04:27:19 PM PDT 24
Peak memory 191444 kb
Host smart-48ba4e57-4d00-4892-b6bb-b206a257be1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141000665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.1141000665
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.135877194
Short name T438
Test name
Test status
Simulation time 140290923293 ps
CPU time 629.1 seconds
Started Jul 24 04:26:12 PM PDT 24
Finished Jul 24 04:36:41 PM PDT 24
Peak memory 191452 kb
Host smart-93f4414d-6564-4bf3-9fcf-adefa9700371
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135877194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.135877194
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.2600152450
Short name T166
Test name
Test status
Simulation time 474571829025 ps
CPU time 228.35 seconds
Started Jul 24 04:26:10 PM PDT 24
Finished Jul 24 04:29:58 PM PDT 24
Peak memory 191576 kb
Host smart-5063de20-6c28-41cc-b175-01c8dffdc054
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600152450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.2600152450
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.1166578220
Short name T225
Test name
Test status
Simulation time 1355878202011 ps
CPU time 835.31 seconds
Started Jul 24 04:26:12 PM PDT 24
Finished Jul 24 04:40:07 PM PDT 24
Peak memory 191452 kb
Host smart-e76e779e-7c4e-462a-9c70-7dc8f1dea1c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166578220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.1166578220
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.2993383396
Short name T348
Test name
Test status
Simulation time 414413248082 ps
CPU time 597.48 seconds
Started Jul 24 04:26:07 PM PDT 24
Finished Jul 24 04:36:05 PM PDT 24
Peak memory 195056 kb
Host smart-344b0820-daff-492c-85c3-2d494a7c1765
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993383396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.2993383396
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.3160450033
Short name T23
Test name
Test status
Simulation time 163251060038 ps
CPU time 235.23 seconds
Started Jul 24 04:23:45 PM PDT 24
Finished Jul 24 04:27:40 PM PDT 24
Peak memory 183372 kb
Host smart-bd4ac765-ab53-4948-a6d9-ed87f3d8d44f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160450033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.3160450033
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.3365151700
Short name T379
Test name
Test status
Simulation time 143221649094 ps
CPU time 42.42 seconds
Started Jul 24 04:22:26 PM PDT 24
Finished Jul 24 04:23:09 PM PDT 24
Peak memory 183364 kb
Host smart-7694ec3e-17ab-4834-a4fc-07a5367aab91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365151700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.3365151700
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.240950163
Short name T193
Test name
Test status
Simulation time 320335449238 ps
CPU time 302.06 seconds
Started Jul 24 04:25:31 PM PDT 24
Finished Jul 24 04:30:34 PM PDT 24
Peak memory 191268 kb
Host smart-d4375b02-f3de-4332-912d-d74b8c0172c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240950163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.240950163
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.3780198887
Short name T19
Test name
Test status
Simulation time 33891089588 ps
CPU time 27.1 seconds
Started Jul 24 04:25:12 PM PDT 24
Finished Jul 24 04:25:39 PM PDT 24
Peak memory 183304 kb
Host smart-1cc103ee-bc15-41ff-8df5-fab0808dc46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780198887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.3780198887
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/192.rv_timer_random.252231907
Short name T237
Test name
Test status
Simulation time 112533754247 ps
CPU time 613.36 seconds
Started Jul 24 04:26:21 PM PDT 24
Finished Jul 24 04:36:34 PM PDT 24
Peak memory 191488 kb
Host smart-6c21bea1-cf08-46d4-aa94-ae66e0a050f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252231907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.252231907
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.2417239069
Short name T4
Test name
Test status
Simulation time 366695955903 ps
CPU time 181.06 seconds
Started Jul 24 04:26:21 PM PDT 24
Finished Jul 24 04:29:22 PM PDT 24
Peak memory 191488 kb
Host smart-7b6047bd-e93f-4dd0-87b2-9308e8a9045f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417239069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.2417239069
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.928384165
Short name T254
Test name
Test status
Simulation time 59150184317 ps
CPU time 51.68 seconds
Started Jul 24 04:26:05 PM PDT 24
Finished Jul 24 04:26:57 PM PDT 24
Peak memory 191464 kb
Host smart-9573b273-9ddd-442a-bc78-1f05a5ff340e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928384165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.928384165
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.1270508689
Short name T259
Test name
Test status
Simulation time 282168963673 ps
CPU time 467.94 seconds
Started Jul 24 04:26:08 PM PDT 24
Finished Jul 24 04:33:57 PM PDT 24
Peak memory 191576 kb
Host smart-ed40d4b4-ce9a-4ee7-a5a6-4169913201cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270508689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.1270508689
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.1556816335
Short name T152
Test name
Test status
Simulation time 579094588463 ps
CPU time 413.51 seconds
Started Jul 24 04:26:21 PM PDT 24
Finished Jul 24 04:33:14 PM PDT 24
Peak memory 191488 kb
Host smart-be8e59bf-fdf6-4418-b5e9-01113c5eb70e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556816335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.1556816335
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.3904112347
Short name T448
Test name
Test status
Simulation time 243742859098 ps
CPU time 107.22 seconds
Started Jul 24 04:26:10 PM PDT 24
Finished Jul 24 04:27:58 PM PDT 24
Peak memory 191628 kb
Host smart-249dad59-dfde-41f2-a04b-4cbca6212a13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904112347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.3904112347
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.1525640378
Short name T82
Test name
Test status
Simulation time 53111798325 ps
CPU time 27.73 seconds
Started Jul 24 04:25:06 PM PDT 24
Finished Jul 24 04:25:34 PM PDT 24
Peak memory 181728 kb
Host smart-4bfb10ed-fb42-4e66-ad7a-3846b225427e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525640378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.1525640378
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.1629713579
Short name T389
Test name
Test status
Simulation time 53575906143 ps
CPU time 70.24 seconds
Started Jul 24 04:25:21 PM PDT 24
Finished Jul 24 04:26:32 PM PDT 24
Peak memory 183416 kb
Host smart-888611fc-bb61-4b9f-815b-de34ec060bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629713579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.1629713579
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.3627927841
Short name T84
Test name
Test status
Simulation time 106148108724 ps
CPU time 1036.86 seconds
Started Jul 24 04:20:51 PM PDT 24
Finished Jul 24 04:38:08 PM PDT 24
Peak memory 191484 kb
Host smart-85573866-67b2-44d5-bb98-4dbf31e7e2f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627927841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.3627927841
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.4047812042
Short name T17
Test name
Test status
Simulation time 142390978 ps
CPU time 0.8 seconds
Started Jul 24 04:25:21 PM PDT 24
Finished Jul 24 04:25:22 PM PDT 24
Peak memory 212692 kb
Host smart-72564326-249d-4930-94d6-80a87ff93c3c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047812042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.4047812042
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.584007224
Short name T168
Test name
Test status
Simulation time 925403399581 ps
CPU time 1045.89 seconds
Started Jul 24 04:25:28 PM PDT 24
Finished Jul 24 04:42:54 PM PDT 24
Peak memory 190124 kb
Host smart-55be8d71-c9d4-4f95-8539-5bbc6d33e165
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584007224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.584007224
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.900718073
Short name T269
Test name
Test status
Simulation time 486071933742 ps
CPU time 637.13 seconds
Started Jul 24 04:22:28 PM PDT 24
Finished Jul 24 04:33:06 PM PDT 24
Peak memory 183532 kb
Host smart-4feb69bc-ab23-4809-bd16-3d12b3606e6a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900718073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.rv_timer_cfg_update_on_fly.900718073
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.1996296457
Short name T374
Test name
Test status
Simulation time 651117933619 ps
CPU time 230.7 seconds
Started Jul 24 04:24:41 PM PDT 24
Finished Jul 24 04:28:33 PM PDT 24
Peak memory 181848 kb
Host smart-b67ed4b9-c0a4-4d5a-b231-65d06c61e985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996296457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.1996296457
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.336393709
Short name T195
Test name
Test status
Simulation time 314089042031 ps
CPU time 161.71 seconds
Started Jul 24 04:22:33 PM PDT 24
Finished Jul 24 04:25:15 PM PDT 24
Peak memory 191576 kb
Host smart-2615809c-2944-4f0d-80d4-eb562a8e3b7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336393709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.336393709
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.4131352172
Short name T283
Test name
Test status
Simulation time 535478241972 ps
CPU time 273.67 seconds
Started Jul 24 04:22:30 PM PDT 24
Finished Jul 24 04:27:04 PM PDT 24
Peak memory 191724 kb
Host smart-ecda690f-b04e-4cc8-bdc6-ac0c0f279389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131352172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.4131352172
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.2867417706
Short name T320
Test name
Test status
Simulation time 87153726019 ps
CPU time 27.05 seconds
Started Jul 24 04:24:41 PM PDT 24
Finished Jul 24 04:25:09 PM PDT 24
Peak memory 181568 kb
Host smart-c41aef10-5812-4806-be11-72db4b771d6b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867417706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.2867417706
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.3127116425
Short name T366
Test name
Test status
Simulation time 141077058985 ps
CPU time 168.68 seconds
Started Jul 24 04:22:45 PM PDT 24
Finished Jul 24 04:25:34 PM PDT 24
Peak memory 183368 kb
Host smart-45d5442a-6570-407b-85a3-d96aafb9459a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127116425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.3127116425
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.1087540617
Short name T203
Test name
Test status
Simulation time 227090492899 ps
CPU time 1047.04 seconds
Started Jul 24 04:22:59 PM PDT 24
Finished Jul 24 04:40:27 PM PDT 24
Peak memory 191568 kb
Host smart-7f3c6235-85ae-4839-bc22-ab7287fe834e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087540617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.1087540617
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.803531249
Short name T243
Test name
Test status
Simulation time 83155917190 ps
CPU time 46.92 seconds
Started Jul 24 04:25:23 PM PDT 24
Finished Jul 24 04:26:10 PM PDT 24
Peak memory 183032 kb
Host smart-d37a93c3-f138-4a02-a843-59514cfd1b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803531249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.803531249
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.622180305
Short name T288
Test name
Test status
Simulation time 35668976532 ps
CPU time 29.4 seconds
Started Jul 24 04:25:28 PM PDT 24
Finished Jul 24 04:25:58 PM PDT 24
Peak memory 183172 kb
Host smart-9ff9d7db-2080-4eed-8db9-b89c291dbb9f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622180305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.rv_timer_cfg_update_on_fly.622180305
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.1859311247
Short name T392
Test name
Test status
Simulation time 322118627075 ps
CPU time 114.08 seconds
Started Jul 24 04:23:08 PM PDT 24
Finished Jul 24 04:25:02 PM PDT 24
Peak memory 183380 kb
Host smart-e78df94f-11fe-4969-880f-120e8f9b9597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859311247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.1859311247
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.2116174988
Short name T276
Test name
Test status
Simulation time 1159042899747 ps
CPU time 483.95 seconds
Started Jul 24 04:25:23 PM PDT 24
Finished Jul 24 04:33:27 PM PDT 24
Peak memory 191224 kb
Host smart-79ff9ef4-92d5-45f5-b073-7ba317ac67d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116174988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.2116174988
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.2520900295
Short name T351
Test name
Test status
Simulation time 77565651511 ps
CPU time 58.43 seconds
Started Jul 24 04:22:45 PM PDT 24
Finished Jul 24 04:23:43 PM PDT 24
Peak memory 183800 kb
Host smart-838cca21-eac1-4e1a-8519-8b90a21def9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520900295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.2520900295
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.515960141
Short name T356
Test name
Test status
Simulation time 64559833378 ps
CPU time 56.43 seconds
Started Jul 24 04:25:22 PM PDT 24
Finished Jul 24 04:26:19 PM PDT 24
Peak memory 182764 kb
Host smart-8a0030b4-dcb9-4439-a71e-366db4ae5c92
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515960141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.rv_timer_cfg_update_on_fly.515960141
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.3963196177
Short name T425
Test name
Test status
Simulation time 138872506902 ps
CPU time 205.64 seconds
Started Jul 24 04:23:13 PM PDT 24
Finished Jul 24 04:26:39 PM PDT 24
Peak memory 183728 kb
Host smart-1906671b-ed94-4027-acae-cb4502590c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963196177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.3963196177
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.3113180915
Short name T373
Test name
Test status
Simulation time 13436435960 ps
CPU time 11.76 seconds
Started Jul 24 04:22:38 PM PDT 24
Finished Jul 24 04:22:50 PM PDT 24
Peak memory 183396 kb
Host smart-6e331345-705d-4bc9-926c-f656fe9e98a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113180915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.3113180915
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.1196479991
Short name T127
Test name
Test status
Simulation time 266743069000 ps
CPU time 464.63 seconds
Started Jul 24 04:23:15 PM PDT 24
Finished Jul 24 04:31:00 PM PDT 24
Peak memory 183352 kb
Host smart-0fc47cbe-0840-4484-b08a-f2274b0ecc5d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196479991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.1196479991
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.4081424244
Short name T370
Test name
Test status
Simulation time 539431899779 ps
CPU time 181.91 seconds
Started Jul 24 04:25:23 PM PDT 24
Finished Jul 24 04:28:25 PM PDT 24
Peak memory 183020 kb
Host smart-c5ec8bb6-767c-4e6c-a824-22c63e636ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081424244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.4081424244
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.1070190185
Short name T365
Test name
Test status
Simulation time 402423112 ps
CPU time 2.15 seconds
Started Jul 24 04:25:50 PM PDT 24
Finished Jul 24 04:25:53 PM PDT 24
Peak memory 191172 kb
Host smart-58934e64-a783-4683-b4c2-5b2ccc4ba156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070190185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.1070190185
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all_with_rand_reset.1581774659
Short name T45
Test name
Test status
Simulation time 26361974304 ps
CPU time 100.96 seconds
Started Jul 24 04:25:39 PM PDT 24
Finished Jul 24 04:27:21 PM PDT 24
Peak memory 197084 kb
Host smart-636a46cf-2984-4e94-a92b-7f4da1484c91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581774659 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all_with_rand_reset.1581774659
Directory /workspace/24.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.3626998554
Short name T383
Test name
Test status
Simulation time 140952327947 ps
CPU time 68.18 seconds
Started Jul 24 04:22:46 PM PDT 24
Finished Jul 24 04:23:54 PM PDT 24
Peak memory 183368 kb
Host smart-85be9b84-e049-4888-83fe-6a1c798eea48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626998554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.3626998554
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.2422754470
Short name T277
Test name
Test status
Simulation time 398795752380 ps
CPU time 725.22 seconds
Started Jul 24 04:23:34 PM PDT 24
Finished Jul 24 04:35:40 PM PDT 24
Peak memory 191588 kb
Host smart-ff515a6c-456a-4f5a-aa1e-2530ee40016a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422754470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.2422754470
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.3239084346
Short name T435
Test name
Test status
Simulation time 25170196 ps
CPU time 0.56 seconds
Started Jul 24 04:23:35 PM PDT 24
Finished Jul 24 04:23:35 PM PDT 24
Peak memory 183152 kb
Host smart-60fd1dc8-a56c-4a03-a5c2-103dcc3d0b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239084346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.3239084346
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.3776243696
Short name T250
Test name
Test status
Simulation time 6335425512387 ps
CPU time 887.61 seconds
Started Jul 24 04:25:40 PM PDT 24
Finished Jul 24 04:40:29 PM PDT 24
Peak memory 190460 kb
Host smart-9a83ef8e-ee95-44e5-8e6d-f04fadca95a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776243696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.3776243696
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all_with_rand_reset.2497916037
Short name T11
Test name
Test status
Simulation time 76424352240 ps
CPU time 110.13 seconds
Started Jul 24 04:25:49 PM PDT 24
Finished Jul 24 04:27:39 PM PDT 24
Peak memory 197792 kb
Host smart-58f5b0d7-9a1d-4f8a-9219-1be046fe907a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497916037 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all_with_rand_reset.2497916037
Directory /workspace/25.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.2126676972
Short name T22
Test name
Test status
Simulation time 233720807939 ps
CPU time 337.54 seconds
Started Jul 24 04:25:41 PM PDT 24
Finished Jul 24 04:31:19 PM PDT 24
Peak memory 183012 kb
Host smart-c6d189ab-6346-40f8-bdb7-fe8dd9a7364e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126676972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.2126676972
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.671260638
Short name T376
Test name
Test status
Simulation time 171249206314 ps
CPU time 58.84 seconds
Started Jul 24 04:25:50 PM PDT 24
Finished Jul 24 04:26:49 PM PDT 24
Peak memory 183056 kb
Host smart-3826dce1-507e-42c3-8cec-07e923a54443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671260638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.671260638
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.1003000729
Short name T80
Test name
Test status
Simulation time 158999919623 ps
CPU time 267.56 seconds
Started Jul 24 04:25:57 PM PDT 24
Finished Jul 24 04:30:24 PM PDT 24
Peak memory 191508 kb
Host smart-1c13fb97-13f1-4a5f-aef1-fcbd077d4db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003000729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.1003000729
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.2698216746
Short name T246
Test name
Test status
Simulation time 634992241518 ps
CPU time 353.66 seconds
Started Jul 24 04:25:36 PM PDT 24
Finished Jul 24 04:31:29 PM PDT 24
Peak memory 183312 kb
Host smart-1576a848-759e-4403-9694-3d589bb9ad84
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698216746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.2698216746
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.200818226
Short name T429
Test name
Test status
Simulation time 319470748606 ps
CPU time 346.97 seconds
Started Jul 24 04:25:36 PM PDT 24
Finished Jul 24 04:31:23 PM PDT 24
Peak memory 183296 kb
Host smart-a63c2b20-8aa3-438b-8f09-79ab5af2b9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200818226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.200818226
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.3946886625
Short name T401
Test name
Test status
Simulation time 302413838142 ps
CPU time 119.62 seconds
Started Jul 24 04:25:40 PM PDT 24
Finished Jul 24 04:27:40 PM PDT 24
Peak memory 193648 kb
Host smart-23581360-652e-4e95-aef9-9a812f8dfbcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946886625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.3946886625
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.33089506
Short name T219
Test name
Test status
Simulation time 685047982540 ps
CPU time 1149.84 seconds
Started Jul 24 04:22:55 PM PDT 24
Finished Jul 24 04:42:05 PM PDT 24
Peak memory 183348 kb
Host smart-3a5525cb-42c4-4cb8-97e5-778486222c37
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33089506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.rv_timer_cfg_update_on_fly.33089506
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.1185011970
Short name T97
Test name
Test status
Simulation time 511283662695 ps
CPU time 185.12 seconds
Started Jul 24 04:25:36 PM PDT 24
Finished Jul 24 04:28:41 PM PDT 24
Peak memory 183300 kb
Host smart-7407c26c-09a3-48fc-a9c9-890d18272470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185011970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.1185011970
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.2434053790
Short name T159
Test name
Test status
Simulation time 799284641551 ps
CPU time 308.83 seconds
Started Jul 24 04:25:36 PM PDT 24
Finished Jul 24 04:30:45 PM PDT 24
Peak memory 191488 kb
Host smart-8e149219-6104-46f8-9d57-4822246f9e93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434053790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.2434053790
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.1457017125
Short name T431
Test name
Test status
Simulation time 45223894207 ps
CPU time 96.28 seconds
Started Jul 24 04:25:05 PM PDT 24
Finished Jul 24 04:26:42 PM PDT 24
Peak memory 182256 kb
Host smart-07376717-fd85-4f5b-bfd8-e52571d97678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457017125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.1457017125
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.2985488144
Short name T332
Test name
Test status
Simulation time 540819434573 ps
CPU time 299.6 seconds
Started Jul 24 04:25:23 PM PDT 24
Finished Jul 24 04:30:23 PM PDT 24
Peak memory 183020 kb
Host smart-b38e888b-e327-454b-994a-ada18a1cbe1f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985488144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.2985488144
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.1756975625
Short name T436
Test name
Test status
Simulation time 40092045007 ps
CPU time 52.5 seconds
Started Jul 24 04:25:57 PM PDT 24
Finished Jul 24 04:26:50 PM PDT 24
Peak memory 183348 kb
Host smart-0f6fa41e-5dd6-4eba-ba21-6bab1ec9a07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756975625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.1756975625
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.2364264503
Short name T280
Test name
Test status
Simulation time 345677297208 ps
CPU time 217.38 seconds
Started Jul 24 04:25:39 PM PDT 24
Finished Jul 24 04:29:17 PM PDT 24
Peak memory 191480 kb
Host smart-4d12d13b-9280-41dd-af22-77d74875ad3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364264503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.2364264503
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.4199774126
Short name T378
Test name
Test status
Simulation time 243472037992 ps
CPU time 165.87 seconds
Started Jul 24 04:25:22 PM PDT 24
Finished Jul 24 04:28:08 PM PDT 24
Peak memory 190620 kb
Host smart-4acf424d-0829-4803-8588-630d94991f0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199774126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.4199774126
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.3570982311
Short name T432
Test name
Test status
Simulation time 197685958752 ps
CPU time 183.22 seconds
Started Jul 24 04:21:34 PM PDT 24
Finished Jul 24 04:24:37 PM PDT 24
Peak memory 183376 kb
Host smart-8be4f0ab-7517-4d9b-9a50-22ceea679c37
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570982311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.3570982311
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.3164983227
Short name T416
Test name
Test status
Simulation time 351845047142 ps
CPU time 121.23 seconds
Started Jul 24 04:25:09 PM PDT 24
Finished Jul 24 04:27:10 PM PDT 24
Peak memory 182456 kb
Host smart-da1f7982-ba19-40cf-a535-a12e10034e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164983227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.3164983227
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.2465076793
Short name T239
Test name
Test status
Simulation time 209210543021 ps
CPU time 396.75 seconds
Started Jul 24 04:22:35 PM PDT 24
Finished Jul 24 04:29:12 PM PDT 24
Peak memory 183392 kb
Host smart-d7a9f47d-01ff-4f94-b5b4-5473e34d0df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465076793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.2465076793
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.3629372903
Short name T14
Test name
Test status
Simulation time 176746654 ps
CPU time 0.85 seconds
Started Jul 24 04:25:21 PM PDT 24
Finished Jul 24 04:25:22 PM PDT 24
Peak memory 215780 kb
Host smart-f8200357-80d2-47ba-beb0-1dde6d240e35
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629372903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.3629372903
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.3155648638
Short name T123
Test name
Test status
Simulation time 271710502133 ps
CPU time 423.13 seconds
Started Jul 24 04:25:57 PM PDT 24
Finished Jul 24 04:33:01 PM PDT 24
Peak memory 183340 kb
Host smart-f1ca2ffe-378f-477c-bbd4-712c2ab24d04
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155648638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.3155648638
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.1856582476
Short name T391
Test name
Test status
Simulation time 38636983876 ps
CPU time 59.46 seconds
Started Jul 24 04:23:37 PM PDT 24
Finished Jul 24 04:24:37 PM PDT 24
Peak memory 183380 kb
Host smart-79706174-7803-4034-9f8e-12f5c9841b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856582476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.1856582476
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.2984065993
Short name T120
Test name
Test status
Simulation time 251923013962 ps
CPU time 88.28 seconds
Started Jul 24 04:25:57 PM PDT 24
Finished Jul 24 04:27:26 PM PDT 24
Peak memory 191548 kb
Host smart-a0c11f82-e234-444f-b43f-3b1ebf45cc05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984065993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.2984065993
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.3273174970
Short name T41
Test name
Test status
Simulation time 44948898649 ps
CPU time 62.96 seconds
Started Jul 24 04:25:39 PM PDT 24
Finished Jul 24 04:26:42 PM PDT 24
Peak memory 191472 kb
Host smart-d9d40a51-db2f-4a0f-8067-7dc8b35d76c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273174970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.3273174970
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.1683971269
Short name T428
Test name
Test status
Simulation time 1792074004571 ps
CPU time 696.74 seconds
Started Jul 24 04:25:55 PM PDT 24
Finished Jul 24 04:37:32 PM PDT 24
Peak memory 183328 kb
Host smart-f86fbd3f-954e-4b3d-83d6-7919bed555c0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683971269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.1683971269
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.850963919
Short name T96
Test name
Test status
Simulation time 76022225068 ps
CPU time 105.15 seconds
Started Jul 24 04:25:27 PM PDT 24
Finished Jul 24 04:27:12 PM PDT 24
Peak memory 181600 kb
Host smart-1ef6bb1b-2a21-4ef5-b7af-1340605728e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850963919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.850963919
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.1911792152
Short name T310
Test name
Test status
Simulation time 186809515666 ps
CPU time 446.1 seconds
Started Jul 24 04:23:00 PM PDT 24
Finished Jul 24 04:30:26 PM PDT 24
Peak memory 191992 kb
Host smart-fe157417-8b67-4185-883d-a6ec9cb4c5a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911792152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.1911792152
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.3860735853
Short name T384
Test name
Test status
Simulation time 6518476207 ps
CPU time 12.02 seconds
Started Jul 24 04:23:07 PM PDT 24
Finished Jul 24 04:23:20 PM PDT 24
Peak memory 195120 kb
Host smart-2ff86530-b499-4f75-90d5-bf54813bfe3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860735853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.3860735853
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.3068121353
Short name T268
Test name
Test status
Simulation time 323404718155 ps
CPU time 480.86 seconds
Started Jul 24 04:25:32 PM PDT 24
Finished Jul 24 04:33:33 PM PDT 24
Peak memory 193516 kb
Host smart-4bd759b4-4d7a-4991-ac07-1695d0bbb31a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068121353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.3068121353
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.2698025411
Short name T54
Test name
Test status
Simulation time 1212583336888 ps
CPU time 666.84 seconds
Started Jul 24 04:23:07 PM PDT 24
Finished Jul 24 04:34:14 PM PDT 24
Peak memory 183532 kb
Host smart-59a289e9-599c-4a6d-a15d-23b01e47ebcf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698025411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.2698025411
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.604270474
Short name T100
Test name
Test status
Simulation time 151108903488 ps
CPU time 213.75 seconds
Started Jul 24 04:25:32 PM PDT 24
Finished Jul 24 04:29:06 PM PDT 24
Peak memory 181956 kb
Host smart-2f56f5fc-2dc7-4f62-ab9c-e42f1a4847dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604270474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.604270474
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.1665877514
Short name T42
Test name
Test status
Simulation time 837699901249 ps
CPU time 420.44 seconds
Started Jul 24 04:23:04 PM PDT 24
Finished Jul 24 04:30:05 PM PDT 24
Peak memory 191548 kb
Host smart-475c2360-721c-4f9e-bd2b-36b5a887d615
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665877514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.1665877514
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.3058778064
Short name T220
Test name
Test status
Simulation time 171136806926 ps
CPU time 212.16 seconds
Started Jul 24 04:25:55 PM PDT 24
Finished Jul 24 04:29:28 PM PDT 24
Peak memory 191516 kb
Host smart-eb1207a6-b20b-4118-9440-2cc8e04ea9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058778064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.3058778064
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.104803685
Short name T298
Test name
Test status
Simulation time 477202929846 ps
CPU time 294.59 seconds
Started Jul 24 04:25:46 PM PDT 24
Finished Jul 24 04:30:41 PM PDT 24
Peak memory 182948 kb
Host smart-ef8cb270-033a-4880-a7ac-68b21922340e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104803685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.rv_timer_cfg_update_on_fly.104803685
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.1905487638
Short name T440
Test name
Test status
Simulation time 65749187777 ps
CPU time 86.48 seconds
Started Jul 24 04:25:47 PM PDT 24
Finished Jul 24 04:27:14 PM PDT 24
Peak memory 183268 kb
Host smart-5348c54b-e9fa-4474-ba7a-bc4f51737759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905487638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.1905487638
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.2783090590
Short name T134
Test name
Test status
Simulation time 615290333426 ps
CPU time 453.91 seconds
Started Jul 24 04:25:47 PM PDT 24
Finished Jul 24 04:33:22 PM PDT 24
Peak memory 191296 kb
Host smart-364d2f08-d594-4ab4-a07e-093b3e614c9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783090590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.2783090590
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.2901842645
Short name T362
Test name
Test status
Simulation time 74206706918 ps
CPU time 52.26 seconds
Started Jul 24 04:25:41 PM PDT 24
Finished Jul 24 04:26:34 PM PDT 24
Peak memory 191460 kb
Host smart-b55b69bb-9282-4001-bc2e-03838e78b486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901842645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.2901842645
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.4152866034
Short name T226
Test name
Test status
Simulation time 1628522294677 ps
CPU time 1373.54 seconds
Started Jul 24 04:25:44 PM PDT 24
Finished Jul 24 04:48:38 PM PDT 24
Peak memory 191464 kb
Host smart-f1975c78-0d61-4c7b-b251-459890c817a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152866034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.4152866034
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.2319687406
Short name T198
Test name
Test status
Simulation time 564636460816 ps
CPU time 476.52 seconds
Started Jul 24 04:25:47 PM PDT 24
Finished Jul 24 04:33:44 PM PDT 24
Peak memory 183280 kb
Host smart-14bc8732-16a9-43d6-8e55-203f823ccc11
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319687406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.2319687406
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.3162911774
Short name T368
Test name
Test status
Simulation time 172480637610 ps
CPU time 259.84 seconds
Started Jul 24 04:23:16 PM PDT 24
Finished Jul 24 04:27:36 PM PDT 24
Peak memory 183368 kb
Host smart-5421c627-9e84-4b24-9ce5-59aa899304b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162911774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.3162911774
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.1618040642
Short name T337
Test name
Test status
Simulation time 179118083765 ps
CPU time 152.58 seconds
Started Jul 24 04:25:47 PM PDT 24
Finished Jul 24 04:28:20 PM PDT 24
Peak memory 191464 kb
Host smart-7b8fdfcf-3d1a-4a71-a625-c3afdb22b8d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618040642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.1618040642
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.3043276377
Short name T423
Test name
Test status
Simulation time 6944096158 ps
CPU time 39.88 seconds
Started Jul 24 04:25:47 PM PDT 24
Finished Jul 24 04:26:27 PM PDT 24
Peak memory 182876 kb
Host smart-14624175-d3d0-4814-a1ef-c213459573cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043276377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.3043276377
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all_with_rand_reset.3195517049
Short name T35
Test name
Test status
Simulation time 60603324178 ps
CPU time 621.31 seconds
Started Jul 24 04:23:18 PM PDT 24
Finished Jul 24 04:33:39 PM PDT 24
Peak memory 198236 kb
Host smart-e48262c4-884a-4ab2-af48-20adf7221703
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195517049 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all_with_rand_reset.3195517049
Directory /workspace/34.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.3071246892
Short name T216
Test name
Test status
Simulation time 545807726535 ps
CPU time 243.41 seconds
Started Jul 24 04:25:50 PM PDT 24
Finished Jul 24 04:29:54 PM PDT 24
Peak memory 183068 kb
Host smart-d9dcea42-7045-4277-9c3a-1e461d646005
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071246892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.3071246892
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.1484041562
Short name T400
Test name
Test status
Simulation time 124524868759 ps
CPU time 171.81 seconds
Started Jul 24 04:25:20 PM PDT 24
Finished Jul 24 04:28:13 PM PDT 24
Peak memory 182612 kb
Host smart-69dc8174-9c1c-4fff-951f-19dce8e639e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484041562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.1484041562
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.3994195641
Short name T56
Test name
Test status
Simulation time 50892931034 ps
CPU time 101.04 seconds
Started Jul 24 04:25:22 PM PDT 24
Finished Jul 24 04:27:04 PM PDT 24
Peak memory 182480 kb
Host smart-801fbd86-3b22-40cc-a16d-a6665fce9dfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994195641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.3994195641
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.3063503057
Short name T388
Test name
Test status
Simulation time 30812000609 ps
CPU time 49.74 seconds
Started Jul 24 04:25:31 PM PDT 24
Finished Jul 24 04:26:21 PM PDT 24
Peak memory 192608 kb
Host smart-245ae09d-04ce-4e10-a5e8-3ed46923a419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063503057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.3063503057
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.2737542420
Short name T65
Test name
Test status
Simulation time 635612535392 ps
CPU time 264.15 seconds
Started Jul 24 04:25:28 PM PDT 24
Finished Jul 24 04:29:53 PM PDT 24
Peak memory 195612 kb
Host smart-3d17088f-2984-422e-ba94-403344a93288
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737542420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.2737542420
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all_with_rand_reset.2773672723
Short name T39
Test name
Test status
Simulation time 86455902175 ps
CPU time 392.95 seconds
Started Jul 24 04:25:35 PM PDT 24
Finished Jul 24 04:32:08 PM PDT 24
Peak memory 197952 kb
Host smart-5fce8f2f-db26-4f41-97e2-2b4c5a21a013
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773672723 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all_with_rand_reset.2773672723
Directory /workspace/35.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.2060876753
Short name T149
Test name
Test status
Simulation time 76746079568 ps
CPU time 23.53 seconds
Started Jul 24 04:25:28 PM PDT 24
Finished Jul 24 04:25:52 PM PDT 24
Peak memory 183080 kb
Host smart-198be9da-26a1-47a5-880a-9552963bfef9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060876753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.2060876753
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.3124639276
Short name T426
Test name
Test status
Simulation time 283719271023 ps
CPU time 97.22 seconds
Started Jul 24 04:25:27 PM PDT 24
Finished Jul 24 04:27:05 PM PDT 24
Peak memory 182480 kb
Host smart-ecdd7f50-0f18-41ee-99a8-03205148d542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124639276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.3124639276
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.1802097473
Short name T135
Test name
Test status
Simulation time 172690282565 ps
CPU time 503.29 seconds
Started Jul 24 04:23:17 PM PDT 24
Finished Jul 24 04:31:40 PM PDT 24
Peak memory 191568 kb
Host smart-3dee26b1-b5e2-4667-aebb-39d1e77ef26c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802097473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.1802097473
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.2706103342
Short name T57
Test name
Test status
Simulation time 1446309248 ps
CPU time 0.8 seconds
Started Jul 24 04:23:19 PM PDT 24
Finished Jul 24 04:23:20 PM PDT 24
Peak memory 183160 kb
Host smart-0437af31-7811-42ec-a652-6449d0686eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706103342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.2706103342
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.1294674979
Short name T67
Test name
Test status
Simulation time 1126500133299 ps
CPU time 142.82 seconds
Started Jul 24 04:25:54 PM PDT 24
Finished Jul 24 04:28:17 PM PDT 24
Peak memory 183320 kb
Host smart-2bf0c8df-0090-4656-91c1-285317504080
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294674979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.1294674979
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all_with_rand_reset.1676968631
Short name T12
Test name
Test status
Simulation time 41838186543 ps
CPU time 272.57 seconds
Started Jul 24 04:25:53 PM PDT 24
Finished Jul 24 04:30:26 PM PDT 24
Peak memory 198068 kb
Host smart-af9b2d78-d9b3-47aa-a640-fc82924facbb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676968631 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all_with_rand_reset.1676968631
Directory /workspace/36.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.174632514
Short name T412
Test name
Test status
Simulation time 79337944706 ps
CPU time 96.2 seconds
Started Jul 24 04:25:27 PM PDT 24
Finished Jul 24 04:27:04 PM PDT 24
Peak memory 181720 kb
Host smart-f3496df3-9609-43ce-9a3c-35e3ee39c70c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174632514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.rv_timer_cfg_update_on_fly.174632514
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.2755696560
Short name T87
Test name
Test status
Simulation time 157979487731 ps
CPU time 61.54 seconds
Started Jul 24 04:23:21 PM PDT 24
Finished Jul 24 04:24:22 PM PDT 24
Peak memory 183368 kb
Host smart-177198f6-d1f0-4a3f-94e0-5de158d978ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755696560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.2755696560
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.107239855
Short name T336
Test name
Test status
Simulation time 1502353717479 ps
CPU time 132.09 seconds
Started Jul 24 04:25:28 PM PDT 24
Finished Jul 24 04:27:41 PM PDT 24
Peak memory 191232 kb
Host smart-be8f1252-81a3-4a12-9c2b-1f83f59f4653
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107239855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.107239855
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.2111768190
Short name T413
Test name
Test status
Simulation time 491651302 ps
CPU time 0.68 seconds
Started Jul 24 04:25:03 PM PDT 24
Finished Jul 24 04:25:05 PM PDT 24
Peak memory 181936 kb
Host smart-129a4581-ff60-4177-bf53-d2eff23b6790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111768190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.2111768190
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.2872845244
Short name T450
Test name
Test status
Simulation time 113157029085 ps
CPU time 231.52 seconds
Started Jul 24 04:23:24 PM PDT 24
Finished Jul 24 04:27:16 PM PDT 24
Peak memory 191552 kb
Host smart-455bf9ca-a531-46b2-8cb8-e27590818135
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872845244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.2872845244
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.1564671040
Short name T328
Test name
Test status
Simulation time 57269474417 ps
CPU time 28.98 seconds
Started Jul 24 04:23:33 PM PDT 24
Finished Jul 24 04:24:02 PM PDT 24
Peak memory 183392 kb
Host smart-829c4afc-b444-4c1f-94cf-8a6257520414
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564671040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.1564671040
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.4091865296
Short name T382
Test name
Test status
Simulation time 326586716247 ps
CPU time 217.5 seconds
Started Jul 24 04:25:54 PM PDT 24
Finished Jul 24 04:29:32 PM PDT 24
Peak memory 183320 kb
Host smart-af3a3540-62df-46f7-a7a4-f14251e75ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091865296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.4091865296
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.1732914701
Short name T249
Test name
Test status
Simulation time 71796582304 ps
CPU time 161.32 seconds
Started Jul 24 04:23:27 PM PDT 24
Finished Jul 24 04:26:09 PM PDT 24
Peak memory 191560 kb
Host smart-0aa75f4f-1606-4e8b-8149-abf9a371897c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732914701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.1732914701
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.2572399133
Short name T417
Test name
Test status
Simulation time 357664594 ps
CPU time 0.64 seconds
Started Jul 24 04:24:57 PM PDT 24
Finished Jul 24 04:24:58 PM PDT 24
Peak memory 183072 kb
Host smart-86571218-7160-4b79-bc0a-b100fa68c9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572399133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.2572399133
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.198158757
Short name T142
Test name
Test status
Simulation time 153245596994 ps
CPU time 253.57 seconds
Started Jul 24 04:23:42 PM PDT 24
Finished Jul 24 04:27:55 PM PDT 24
Peak memory 183396 kb
Host smart-65db0159-fbab-4df6-9199-0468cdaad654
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198158757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.rv_timer_cfg_update_on_fly.198158757
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.527431732
Short name T404
Test name
Test status
Simulation time 159742865839 ps
CPU time 129.96 seconds
Started Jul 24 04:25:46 PM PDT 24
Finished Jul 24 04:27:57 PM PDT 24
Peak memory 183020 kb
Host smart-ecc040b4-584c-4d61-8c1b-7a3438fb7c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527431732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.527431732
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.2307478005
Short name T240
Test name
Test status
Simulation time 88654133173 ps
CPU time 67.48 seconds
Started Jul 24 04:23:30 PM PDT 24
Finished Jul 24 04:24:38 PM PDT 24
Peak memory 183368 kb
Host smart-5f7f19f2-6184-428a-a692-d1990b210692
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307478005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.2307478005
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.105004736
Short name T43
Test name
Test status
Simulation time 603127487 ps
CPU time 0.8 seconds
Started Jul 24 04:25:42 PM PDT 24
Finished Jul 24 04:25:43 PM PDT 24
Peak memory 183064 kb
Host smart-f212cd91-bc2d-4d85-ad1d-f95db9ee48bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105004736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.105004736
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.1253596169
Short name T408
Test name
Test status
Simulation time 92609626275 ps
CPU time 147.38 seconds
Started Jul 24 04:25:43 PM PDT 24
Finished Jul 24 04:28:11 PM PDT 24
Peak memory 182200 kb
Host smart-acf621bb-828b-4d70-ac0b-91d2b3f40153
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253596169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.1253596169
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.3000098011
Short name T377
Test name
Test status
Simulation time 138297750612 ps
CPU time 200.99 seconds
Started Jul 24 04:22:20 PM PDT 24
Finished Jul 24 04:25:42 PM PDT 24
Peak memory 183360 kb
Host smart-b0407305-1b26-449a-a802-01fddff59154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000098011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.3000098011
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.2862046364
Short name T215
Test name
Test status
Simulation time 206672774184 ps
CPU time 402.13 seconds
Started Jul 24 04:22:17 PM PDT 24
Finished Jul 24 04:28:59 PM PDT 24
Peak memory 191556 kb
Host smart-64637a81-06b2-41cb-88e8-17e1669fc01f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862046364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.2862046364
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.3733014065
Short name T167
Test name
Test status
Simulation time 63125743021 ps
CPU time 119.38 seconds
Started Jul 24 04:25:44 PM PDT 24
Finished Jul 24 04:27:43 PM PDT 24
Peak memory 191196 kb
Host smart-f3fe7b0d-5828-41c6-bccf-0c1e7f342c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733014065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.3733014065
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.1803710005
Short name T16
Test name
Test status
Simulation time 121940892 ps
CPU time 0.84 seconds
Started Jul 24 04:21:06 PM PDT 24
Finished Jul 24 04:21:07 PM PDT 24
Peak memory 214568 kb
Host smart-7856fb5f-fa1d-4b81-a301-fb6270e5602d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803710005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.1803710005
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.1768092780
Short name T279
Test name
Test status
Simulation time 462533137639 ps
CPU time 371.94 seconds
Started Jul 24 04:25:35 PM PDT 24
Finished Jul 24 04:31:47 PM PDT 24
Peak memory 183256 kb
Host smart-1cab3423-ddd1-4499-b084-c16a8f144212
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768092780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.1768092780
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.4193696110
Short name T405
Test name
Test status
Simulation time 90364207014 ps
CPU time 124.11 seconds
Started Jul 24 04:25:30 PM PDT 24
Finished Jul 24 04:27:35 PM PDT 24
Peak memory 181312 kb
Host smart-45b37c8e-21af-4e17-8c54-61424c869590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193696110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.4193696110
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.2176270403
Short name T422
Test name
Test status
Simulation time 97358421140 ps
CPU time 160.87 seconds
Started Jul 24 04:25:39 PM PDT 24
Finished Jul 24 04:28:21 PM PDT 24
Peak memory 190072 kb
Host smart-4ccde7e0-a991-4943-b77f-5d6ea9d9d1eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176270403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.2176270403
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.3914379724
Short name T381
Test name
Test status
Simulation time 22707947 ps
CPU time 0.55 seconds
Started Jul 24 04:25:55 PM PDT 24
Finished Jul 24 04:25:57 PM PDT 24
Peak memory 183080 kb
Host smart-f0fb4064-6070-4813-8781-e13e166e092c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914379724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.3914379724
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all_with_rand_reset.153011629
Short name T36
Test name
Test status
Simulation time 108575654299 ps
CPU time 744.47 seconds
Started Jul 24 04:25:41 PM PDT 24
Finished Jul 24 04:38:06 PM PDT 24
Peak memory 214408 kb
Host smart-37293234-3cfa-4df4-b4f8-d83432a59427
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153011629 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all_with_rand_reset.153011629
Directory /workspace/40.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.2854515855
Short name T282
Test name
Test status
Simulation time 393423488786 ps
CPU time 561.16 seconds
Started Jul 24 04:25:07 PM PDT 24
Finished Jul 24 04:34:28 PM PDT 24
Peak memory 183116 kb
Host smart-e1846687-f0b5-47fb-bca7-c755c778424c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854515855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.2854515855
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.3613705631
Short name T410
Test name
Test status
Simulation time 290249207824 ps
CPU time 230.22 seconds
Started Jul 24 04:25:41 PM PDT 24
Finished Jul 24 04:29:32 PM PDT 24
Peak memory 183284 kb
Host smart-1c1a0ac4-4a9c-4265-a281-73bf977ea1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613705631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.3613705631
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.1090563607
Short name T141
Test name
Test status
Simulation time 86783281621 ps
CPU time 81.46 seconds
Started Jul 24 04:25:06 PM PDT 24
Finished Jul 24 04:26:28 PM PDT 24
Peak memory 181752 kb
Host smart-ed5bfc1a-da58-458c-adda-6a4c77525fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090563607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.1090563607
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.1282549428
Short name T170
Test name
Test status
Simulation time 508579432172 ps
CPU time 524.29 seconds
Started Jul 24 04:23:50 PM PDT 24
Finished Jul 24 04:32:35 PM PDT 24
Peak memory 183356 kb
Host smart-2f7a1181-fb4f-4292-b94b-da53dae28a25
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282549428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.1282549428
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.3521494002
Short name T99
Test name
Test status
Simulation time 179014227322 ps
CPU time 278.03 seconds
Started Jul 24 04:25:35 PM PDT 24
Finished Jul 24 04:30:13 PM PDT 24
Peak memory 183236 kb
Host smart-fb8fa94e-64ef-4744-bf1e-95173e7c1713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521494002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.3521494002
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.1755717370
Short name T253
Test name
Test status
Simulation time 126128582765 ps
CPU time 64.99 seconds
Started Jul 24 04:24:19 PM PDT 24
Finished Jul 24 04:25:24 PM PDT 24
Peak memory 191568 kb
Host smart-a475cc4a-29b1-4702-b768-ed01f08f0202
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755717370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.1755717370
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.2645005273
Short name T354
Test name
Test status
Simulation time 273838902917 ps
CPU time 138.3 seconds
Started Jul 24 04:25:39 PM PDT 24
Finished Jul 24 04:27:57 PM PDT 24
Peak memory 191440 kb
Host smart-a36501e7-55db-478d-b17e-12f0c06c85eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645005273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.2645005273
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.859575641
Short name T187
Test name
Test status
Simulation time 1286360075777 ps
CPU time 243.38 seconds
Started Jul 24 04:23:50 PM PDT 24
Finished Jul 24 04:27:53 PM PDT 24
Peak memory 191552 kb
Host smart-f39ae344-258c-40a8-8d3b-3fa3c623a095
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859575641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all.
859575641
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.3477093205
Short name T386
Test name
Test status
Simulation time 141261767124 ps
CPU time 186.05 seconds
Started Jul 24 04:25:34 PM PDT 24
Finished Jul 24 04:28:40 PM PDT 24
Peak memory 183240 kb
Host smart-d85320d3-108d-43a8-afee-1eeade658eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477093205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.3477093205
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.3957257826
Short name T202
Test name
Test status
Simulation time 83494642883 ps
CPU time 340.2 seconds
Started Jul 24 04:25:09 PM PDT 24
Finished Jul 24 04:30:50 PM PDT 24
Peak memory 189552 kb
Host smart-5627180b-3a46-4d1a-b2c0-44479477573e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957257826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.3957257826
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.2369078033
Short name T444
Test name
Test status
Simulation time 357115695987 ps
CPU time 482.56 seconds
Started Jul 24 04:25:10 PM PDT 24
Finished Jul 24 04:33:13 PM PDT 24
Peak memory 191260 kb
Host smart-3d13b7b0-c59c-4835-a59b-a9ea7b279ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369078033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.2369078033
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.3603093475
Short name T7
Test name
Test status
Simulation time 371370198040 ps
CPU time 650.37 seconds
Started Jul 24 04:23:48 PM PDT 24
Finished Jul 24 04:34:38 PM PDT 24
Peak memory 191596 kb
Host smart-ec22ff86-d1ad-45e1-aa88-57a830861aaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603093475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.3603093475
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.3409124391
Short name T37
Test name
Test status
Simulation time 32365987464 ps
CPU time 327.19 seconds
Started Jul 24 04:25:38 PM PDT 24
Finished Jul 24 04:31:05 PM PDT 24
Peak memory 197984 kb
Host smart-8175a01a-e8cf-4327-953e-0ddd87df0685
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409124391 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.3409124391
Directory /workspace/43.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.939157269
Short name T232
Test name
Test status
Simulation time 889163479677 ps
CPU time 869.43 seconds
Started Jul 24 04:25:23 PM PDT 24
Finished Jul 24 04:39:53 PM PDT 24
Peak memory 183264 kb
Host smart-46fd755c-8758-48ea-a34c-603abb041e2f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939157269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.rv_timer_cfg_update_on_fly.939157269
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.592714497
Short name T406
Test name
Test status
Simulation time 191643129236 ps
CPU time 236.55 seconds
Started Jul 24 04:23:59 PM PDT 24
Finished Jul 24 04:27:56 PM PDT 24
Peak memory 183360 kb
Host smart-1f964ce3-18f9-4cd1-84f7-8516b7e5591f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592714497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.592714497
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.2793475901
Short name T75
Test name
Test status
Simulation time 38057972134 ps
CPU time 58.04 seconds
Started Jul 24 04:25:23 PM PDT 24
Finished Jul 24 04:26:21 PM PDT 24
Peak memory 183256 kb
Host smart-1407dd66-eb8c-4e68-972d-532f850f9a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793475901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.2793475901
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.20388202
Short name T244
Test name
Test status
Simulation time 461440544930 ps
CPU time 381.19 seconds
Started Jul 24 04:25:09 PM PDT 24
Finished Jul 24 04:31:31 PM PDT 24
Peak memory 189296 kb
Host smart-4f56b250-6d8d-43d0-ad18-97bff04f70b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20388202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all.20388202
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.643786723
Short name T191
Test name
Test status
Simulation time 821784773892 ps
CPU time 408.06 seconds
Started Jul 24 04:24:08 PM PDT 24
Finished Jul 24 04:30:56 PM PDT 24
Peak memory 183400 kb
Host smart-a9af8c7b-d76e-462a-b71e-0a077c4dddb1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643786723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.rv_timer_cfg_update_on_fly.643786723
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.3754362646
Short name T441
Test name
Test status
Simulation time 170749146510 ps
CPU time 152.06 seconds
Started Jul 24 04:25:20 PM PDT 24
Finished Jul 24 04:27:53 PM PDT 24
Peak memory 182688 kb
Host smart-aca0405d-a30c-462c-903d-3ea1b0b106d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754362646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.3754362646
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.2982401494
Short name T355
Test name
Test status
Simulation time 91071018041 ps
CPU time 89.55 seconds
Started Jul 24 04:24:00 PM PDT 24
Finished Jul 24 04:25:30 PM PDT 24
Peak memory 195124 kb
Host smart-66d5ab59-18f6-4fbb-ab52-e2e29a5757cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982401494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.2982401494
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.800795579
Short name T140
Test name
Test status
Simulation time 14733816904 ps
CPU time 14.22 seconds
Started Jul 24 04:25:20 PM PDT 24
Finished Jul 24 04:25:35 PM PDT 24
Peak memory 182292 kb
Host smart-ec71944f-5575-4c70-9616-ea0a78f48531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800795579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.800795579
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.2441718385
Short name T270
Test name
Test status
Simulation time 35633075144 ps
CPU time 16.38 seconds
Started Jul 24 04:25:43 PM PDT 24
Finished Jul 24 04:26:00 PM PDT 24
Peak memory 183320 kb
Host smart-909adfda-f419-4c45-b6c5-394e90bb7a2f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441718385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.2441718385
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.4257902786
Short name T371
Test name
Test status
Simulation time 165111963950 ps
CPU time 256.33 seconds
Started Jul 24 04:25:40 PM PDT 24
Finished Jul 24 04:29:57 PM PDT 24
Peak memory 183340 kb
Host smart-fdddfecf-d90c-4dbe-8cc3-50bc133804d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257902786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.4257902786
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.1495244052
Short name T284
Test name
Test status
Simulation time 31444189819 ps
CPU time 52.38 seconds
Started Jul 24 04:24:10 PM PDT 24
Finished Jul 24 04:25:03 PM PDT 24
Peak memory 183748 kb
Host smart-7690f9ec-2a70-4d1f-a162-ea685de1acf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495244052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.1495244052
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.287513025
Short name T324
Test name
Test status
Simulation time 29207243834 ps
CPU time 60.85 seconds
Started Jul 24 04:25:43 PM PDT 24
Finished Jul 24 04:26:45 PM PDT 24
Peak memory 193908 kb
Host smart-e41448fe-4407-4e8b-86b6-ad1f9cc88385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287513025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.287513025
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.681461249
Short name T66
Test name
Test status
Simulation time 2154082596870 ps
CPU time 1139.75 seconds
Started Jul 24 04:24:17 PM PDT 24
Finished Jul 24 04:43:17 PM PDT 24
Peak memory 196392 kb
Host smart-be22fe55-bebc-4b6b-bfb8-afd21b6a0b00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681461249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all.
681461249
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.138039513
Short name T353
Test name
Test status
Simulation time 696288029695 ps
CPU time 384.77 seconds
Started Jul 24 04:25:55 PM PDT 24
Finished Jul 24 04:32:21 PM PDT 24
Peak memory 183324 kb
Host smart-31f0aafb-1cff-4683-b796-72b6e8b58240
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138039513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.rv_timer_cfg_update_on_fly.138039513
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.3381185513
Short name T449
Test name
Test status
Simulation time 2817269292 ps
CPU time 4.28 seconds
Started Jul 24 04:25:55 PM PDT 24
Finished Jul 24 04:26:00 PM PDT 24
Peak memory 183132 kb
Host smart-cd053dd1-f4c8-4402-8438-9861f4aae7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381185513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.3381185513
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.3815315937
Short name T321
Test name
Test status
Simulation time 221323876779 ps
CPU time 345.21 seconds
Started Jul 24 04:25:40 PM PDT 24
Finished Jul 24 04:31:26 PM PDT 24
Peak memory 190440 kb
Host smart-9f10f1d5-b6c9-46f4-8d90-3f7c7e7988d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815315937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.3815315937
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.3497120242
Short name T439
Test name
Test status
Simulation time 55780583151 ps
CPU time 34.28 seconds
Started Jul 24 04:25:40 PM PDT 24
Finished Jul 24 04:26:15 PM PDT 24
Peak memory 190428 kb
Host smart-a980678c-f710-4ef2-b175-158c2d02b520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497120242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.3497120242
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.2031241368
Short name T430
Test name
Test status
Simulation time 2328734824801 ps
CPU time 698.97 seconds
Started Jul 24 04:24:33 PM PDT 24
Finished Jul 24 04:36:13 PM PDT 24
Peak memory 183340 kb
Host smart-04a37cf3-7e08-4c92-8bbf-3c2fe10f6934
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031241368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.2031241368
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.1572140803
Short name T427
Test name
Test status
Simulation time 47711787399 ps
CPU time 63.91 seconds
Started Jul 24 04:25:59 PM PDT 24
Finished Jul 24 04:27:04 PM PDT 24
Peak memory 183360 kb
Host smart-10bdc9cc-2082-4821-b98a-28879fc25eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572140803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.1572140803
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.4095106395
Short name T207
Test name
Test status
Simulation time 119993318632 ps
CPU time 174.97 seconds
Started Jul 24 04:24:35 PM PDT 24
Finished Jul 24 04:27:30 PM PDT 24
Peak memory 183348 kb
Host smart-0a69a95e-723c-480f-bae7-f8bcd030f683
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095106395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.4095106395
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.715099411
Short name T418
Test name
Test status
Simulation time 57468592789 ps
CPU time 88.21 seconds
Started Jul 24 04:25:52 PM PDT 24
Finished Jul 24 04:27:20 PM PDT 24
Peak memory 183084 kb
Host smart-deb70a93-a3ad-4a60-be43-32b1449dfff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715099411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.715099411
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.4165588535
Short name T189
Test name
Test status
Simulation time 93892283853 ps
CPU time 179.26 seconds
Started Jul 24 04:26:23 PM PDT 24
Finished Jul 24 04:29:22 PM PDT 24
Peak memory 191272 kb
Host smart-0389049f-8f24-4de6-b10b-41e5f9e0a407
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165588535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.4165588535
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.3010227587
Short name T372
Test name
Test status
Simulation time 42536010 ps
CPU time 0.52 seconds
Started Jul 24 04:25:52 PM PDT 24
Finished Jul 24 04:25:53 PM PDT 24
Peak memory 182812 kb
Host smart-0200508b-6646-4af3-9745-914459e3e385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010227587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.3010227587
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.3530457129
Short name T346
Test name
Test status
Simulation time 517667607879 ps
CPU time 124.89 seconds
Started Jul 24 04:23:48 PM PDT 24
Finished Jul 24 04:25:53 PM PDT 24
Peak memory 183344 kb
Host smart-54a3a54a-9453-4bf3-84ac-c9c2f96a89b0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530457129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.3530457129
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.3589350410
Short name T445
Test name
Test status
Simulation time 61539708428 ps
CPU time 85.55 seconds
Started Jul 24 04:22:19 PM PDT 24
Finished Jul 24 04:23:45 PM PDT 24
Peak memory 183336 kb
Host smart-435996d5-711b-4c62-a0eb-4a2f99f8ac3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589350410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.3589350410
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.327211291
Short name T314
Test name
Test status
Simulation time 192040906748 ps
CPU time 478.67 seconds
Started Jul 24 04:25:58 PM PDT 24
Finished Jul 24 04:33:57 PM PDT 24
Peak memory 191500 kb
Host smart-0e9f5fa7-6df3-4cb2-95f0-1dc99ffd6bba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327211291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.327211291
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.3510895097
Short name T98
Test name
Test status
Simulation time 80761348943 ps
CPU time 67.41 seconds
Started Jul 24 04:25:16 PM PDT 24
Finished Jul 24 04:26:23 PM PDT 24
Peak memory 183268 kb
Host smart-d89773ca-b506-43cd-8fd8-119f7302bc2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510895097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.3510895097
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all_with_rand_reset.1746647841
Short name T47
Test name
Test status
Simulation time 18774119830 ps
CPU time 152.98 seconds
Started Jul 24 04:25:23 PM PDT 24
Finished Jul 24 04:27:56 PM PDT 24
Peak memory 197760 kb
Host smart-07bb7961-aee9-4e34-8364-eb424879b71b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746647841 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all_with_rand_reset.1746647841
Directory /workspace/5.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.rv_timer_random.3444893314
Short name T231
Test name
Test status
Simulation time 108992616297 ps
CPU time 445.32 seconds
Started Jul 24 04:24:44 PM PDT 24
Finished Jul 24 04:32:09 PM PDT 24
Peak memory 191588 kb
Host smart-92430a50-32d3-4a31-bb35-dafdbdefee03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444893314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.3444893314
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.1197635974
Short name T204
Test name
Test status
Simulation time 274074090532 ps
CPU time 161.91 seconds
Started Jul 24 04:24:51 PM PDT 24
Finished Jul 24 04:27:33 PM PDT 24
Peak memory 191676 kb
Host smart-ad7d83d0-6661-4a01-b302-70f598d1f88c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197635974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.1197635974
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.202633066
Short name T398
Test name
Test status
Simulation time 359402309911 ps
CPU time 227.77 seconds
Started Jul 24 04:25:38 PM PDT 24
Finished Jul 24 04:29:26 PM PDT 24
Peak memory 191564 kb
Host smart-2f51487a-a123-46ee-a3d2-4d4cf232c5f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202633066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.202633066
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.1424056232
Short name T201
Test name
Test status
Simulation time 1210770262068 ps
CPU time 798.19 seconds
Started Jul 24 04:25:00 PM PDT 24
Finished Jul 24 04:38:18 PM PDT 24
Peak memory 191544 kb
Host smart-eb822a79-468c-4ab2-b4f4-5c041d72d37d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424056232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.1424056232
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.1427613865
Short name T341
Test name
Test status
Simulation time 98121715410 ps
CPU time 898.81 seconds
Started Jul 24 04:24:55 PM PDT 24
Finished Jul 24 04:39:54 PM PDT 24
Peak memory 191544 kb
Host smart-80a4319e-0f24-4ada-a59d-2a59a9710b41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427613865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.1427613865
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.887631767
Short name T9
Test name
Test status
Simulation time 140127487655 ps
CPU time 588.44 seconds
Started Jul 24 04:24:58 PM PDT 24
Finished Jul 24 04:34:47 PM PDT 24
Peak memory 191568 kb
Host smart-02dbd92e-3c45-4b35-9efc-b75e997fec75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887631767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.887631767
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.4125256332
Short name T326
Test name
Test status
Simulation time 12204271419 ps
CPU time 24.2 seconds
Started Jul 24 04:25:00 PM PDT 24
Finished Jul 24 04:25:24 PM PDT 24
Peak memory 195120 kb
Host smart-710feaae-67d3-4794-b34b-220b646f77d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125256332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.4125256332
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.2667965113
Short name T323
Test name
Test status
Simulation time 119287454387 ps
CPU time 58.31 seconds
Started Jul 24 04:25:00 PM PDT 24
Finished Jul 24 04:25:58 PM PDT 24
Peak memory 183380 kb
Host smart-153d9bf3-4bbe-4140-8f65-3b8a7508637c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667965113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.2667965113
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.173752275
Short name T72
Test name
Test status
Simulation time 23070331541 ps
CPU time 38.3 seconds
Started Jul 24 04:25:47 PM PDT 24
Finished Jul 24 04:26:26 PM PDT 24
Peak memory 183352 kb
Host smart-f261a81e-0085-4d72-93a2-3d16f02bbdf0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173752275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.rv_timer_cfg_update_on_fly.173752275
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.3713208028
Short name T443
Test name
Test status
Simulation time 871877092916 ps
CPU time 322.21 seconds
Started Jul 24 04:25:28 PM PDT 24
Finished Jul 24 04:30:51 PM PDT 24
Peak memory 183040 kb
Host smart-dfcce6ba-aa5f-4a0d-803a-cb2ae49e2e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713208028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.3713208028
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.1673278931
Short name T61
Test name
Test status
Simulation time 9964925341 ps
CPU time 8.24 seconds
Started Jul 24 04:23:03 PM PDT 24
Finished Jul 24 04:23:12 PM PDT 24
Peak memory 195140 kb
Host smart-a28e4c00-10f8-4b52-a8f7-1f4d3ae1b223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673278931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.1673278931
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.3671874969
Short name T262
Test name
Test status
Simulation time 76840419320 ps
CPU time 236.44 seconds
Started Jul 24 04:21:23 PM PDT 24
Finished Jul 24 04:25:20 PM PDT 24
Peak memory 195352 kb
Host smart-8e32ca8e-276f-4ee0-af5c-4ab72e0dafb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671874969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
3671874969
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/60.rv_timer_random.2891509866
Short name T304
Test name
Test status
Simulation time 93070915863 ps
CPU time 69.81 seconds
Started Jul 24 04:25:03 PM PDT 24
Finished Jul 24 04:26:13 PM PDT 24
Peak memory 183792 kb
Host smart-47f1f310-c638-4b1e-a2f4-5794fd16b566
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891509866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.2891509866
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.3095355476
Short name T292
Test name
Test status
Simulation time 61743381069 ps
CPU time 82.85 seconds
Started Jul 24 04:25:09 PM PDT 24
Finished Jul 24 04:26:32 PM PDT 24
Peak memory 191544 kb
Host smart-74f74201-1465-4e98-aa7b-6f8d4bfbf654
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095355476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.3095355476
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.2808599225
Short name T352
Test name
Test status
Simulation time 109660897199 ps
CPU time 210.06 seconds
Started Jul 24 04:25:06 PM PDT 24
Finished Jul 24 04:28:37 PM PDT 24
Peak memory 191584 kb
Host smart-a34eadb9-f5f8-444c-aace-4df628132fe9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808599225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.2808599225
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.1726437411
Short name T217
Test name
Test status
Simulation time 43703829946 ps
CPU time 73.62 seconds
Started Jul 24 04:25:09 PM PDT 24
Finished Jul 24 04:26:23 PM PDT 24
Peak memory 183344 kb
Host smart-60dba63f-5131-4957-aa42-4c8d8db34edb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726437411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.1726437411
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.2578713547
Short name T132
Test name
Test status
Simulation time 79702222041 ps
CPU time 154.32 seconds
Started Jul 24 04:25:06 PM PDT 24
Finished Jul 24 04:27:41 PM PDT 24
Peak memory 191584 kb
Host smart-5bb8d859-1a9f-49eb-b6fc-1f430574000e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578713547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.2578713547
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.1773880430
Short name T342
Test name
Test status
Simulation time 616751242869 ps
CPU time 581.31 seconds
Started Jul 24 04:25:04 PM PDT 24
Finished Jul 24 04:34:45 PM PDT 24
Peak memory 191560 kb
Host smart-fd70f1da-4c80-449b-9e95-422fd4287c9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773880430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.1773880430
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.2794780464
Short name T453
Test name
Test status
Simulation time 140447737532 ps
CPU time 1836.2 seconds
Started Jul 24 04:26:10 PM PDT 24
Finished Jul 24 04:56:48 PM PDT 24
Peak memory 190772 kb
Host smart-ffa62fbb-5a4d-4d78-8000-fa24c8afcef3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794780464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.2794780464
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.1833587157
Short name T415
Test name
Test status
Simulation time 531037869949 ps
CPU time 150.66 seconds
Started Jul 24 04:25:14 PM PDT 24
Finished Jul 24 04:27:45 PM PDT 24
Peak memory 191600 kb
Host smart-1fe589ec-1d73-455a-86d2-7138d6ad69cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833587157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.1833587157
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.1943897259
Short name T437
Test name
Test status
Simulation time 47672585112 ps
CPU time 61.15 seconds
Started Jul 24 04:25:12 PM PDT 24
Finished Jul 24 04:26:13 PM PDT 24
Peak memory 191588 kb
Host smart-0a99ca33-b37b-4486-8ed8-0cca2dde83c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943897259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.1943897259
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.484246071
Short name T293
Test name
Test status
Simulation time 720183408245 ps
CPU time 370.21 seconds
Started Jul 24 04:25:32 PM PDT 24
Finished Jul 24 04:31:43 PM PDT 24
Peak memory 182532 kb
Host smart-492d4bbb-bcc3-451a-84b9-fa9817e28bfe
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484246071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.rv_timer_cfg_update_on_fly.484246071
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.4104965734
Short name T402
Test name
Test status
Simulation time 95716554771 ps
CPU time 132.19 seconds
Started Jul 24 04:22:49 PM PDT 24
Finished Jul 24 04:25:01 PM PDT 24
Peak memory 183380 kb
Host smart-fb066ee4-5eb1-4f9e-9054-f71602cf1730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104965734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.4104965734
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.831175472
Short name T122
Test name
Test status
Simulation time 110009578098 ps
CPU time 180.81 seconds
Started Jul 24 04:25:28 PM PDT 24
Finished Jul 24 04:28:29 PM PDT 24
Peak memory 191216 kb
Host smart-e3a9fa5a-1c2c-4029-9072-bfebf76927d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831175472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.831175472
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.159118952
Short name T161
Test name
Test status
Simulation time 38885099016 ps
CPU time 21.26 seconds
Started Jul 24 04:25:33 PM PDT 24
Finished Jul 24 04:25:54 PM PDT 24
Peak memory 193564 kb
Host smart-9e527cba-91b3-42bb-aeb1-a9f79a8f2d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159118952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.159118952
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.113137553
Short name T446
Test name
Test status
Simulation time 41189856726 ps
CPU time 58.33 seconds
Started Jul 24 04:25:40 PM PDT 24
Finished Jul 24 04:26:39 PM PDT 24
Peak memory 182248 kb
Host smart-5cca2f46-b411-45bf-b86d-be51c535b4a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113137553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.113137553
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.3359093917
Short name T447
Test name
Test status
Simulation time 26321326210 ps
CPU time 283.81 seconds
Started Jul 24 04:23:25 PM PDT 24
Finished Jul 24 04:28:09 PM PDT 24
Peak memory 198496 kb
Host smart-506b38c8-960e-4d85-8825-69e7caee7c29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359093917 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all_with_rand_reset.3359093917
Directory /workspace/7.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.1572254866
Short name T224
Test name
Test status
Simulation time 108842330280 ps
CPU time 163.35 seconds
Started Jul 24 04:25:31 PM PDT 24
Finished Jul 24 04:28:15 PM PDT 24
Peak memory 194140 kb
Host smart-40021e39-d1df-48f0-9ff8-3200d38e1043
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572254866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.1572254866
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.502734590
Short name T158
Test name
Test status
Simulation time 190256195593 ps
CPU time 80.69 seconds
Started Jul 24 04:25:18 PM PDT 24
Finished Jul 24 04:26:39 PM PDT 24
Peak memory 191560 kb
Host smart-8f1f98f3-0ebb-4cf0-a0e8-e4a869283503
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502734590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.502734590
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.3004148448
Short name T197
Test name
Test status
Simulation time 566680656385 ps
CPU time 2710.85 seconds
Started Jul 24 04:25:24 PM PDT 24
Finished Jul 24 05:10:35 PM PDT 24
Peak memory 193932 kb
Host smart-ff9deb78-6558-4621-9e6b-03d9a7623f6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004148448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.3004148448
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.1661710168
Short name T300
Test name
Test status
Simulation time 367785512017 ps
CPU time 475.35 seconds
Started Jul 24 04:25:19 PM PDT 24
Finished Jul 24 04:33:14 PM PDT 24
Peak memory 191572 kb
Host smart-9c92b749-44c4-4b92-b2b6-5a71870c7bbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661710168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.1661710168
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.4076470545
Short name T333
Test name
Test status
Simulation time 379645949542 ps
CPU time 234.9 seconds
Started Jul 24 04:25:25 PM PDT 24
Finished Jul 24 04:29:20 PM PDT 24
Peak memory 193812 kb
Host smart-5fe3d6db-c0a1-4321-9d28-7f74decacd8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076470545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.4076470545
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.3506310449
Short name T311
Test name
Test status
Simulation time 329307331153 ps
CPU time 246.69 seconds
Started Jul 24 04:25:49 PM PDT 24
Finished Jul 24 04:29:56 PM PDT 24
Peak memory 191492 kb
Host smart-6a3a8d38-5541-41d4-a480-5f321da573ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506310449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.3506310449
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.2668072891
Short name T364
Test name
Test status
Simulation time 54200418678 ps
CPU time 99.09 seconds
Started Jul 24 04:25:43 PM PDT 24
Finished Jul 24 04:27:23 PM PDT 24
Peak memory 191464 kb
Host smart-b2360740-89d6-43f8-9445-2036432dc3b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668072891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.2668072891
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.2546701650
Short name T397
Test name
Test status
Simulation time 112462185257 ps
CPU time 116.38 seconds
Started Jul 24 04:25:47 PM PDT 24
Finished Jul 24 04:27:44 PM PDT 24
Peak memory 191376 kb
Host smart-97411f5b-2c59-4b49-9da2-44d7802aa0e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546701650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.2546701650
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.4094707172
Short name T186
Test name
Test status
Simulation time 862601654173 ps
CPU time 1054.16 seconds
Started Jul 24 04:25:44 PM PDT 24
Finished Jul 24 04:43:18 PM PDT 24
Peak memory 191588 kb
Host smart-9e752e34-2f19-4878-8ede-89bdd009eab5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094707172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.4094707172
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.530934869
Short name T424
Test name
Test status
Simulation time 49913248493 ps
CPU time 67 seconds
Started Jul 24 04:25:09 PM PDT 24
Finished Jul 24 04:26:17 PM PDT 24
Peak memory 182956 kb
Host smart-fb55469a-1c35-4321-bbb4-cebc2f74b9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530934869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.530934869
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.508221427
Short name T385
Test name
Test status
Simulation time 1699236886 ps
CPU time 0.86 seconds
Started Jul 24 04:25:41 PM PDT 24
Finished Jul 24 04:25:42 PM PDT 24
Peak memory 191504 kb
Host smart-898afb9f-137d-4e40-bc67-732b47231933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508221427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.508221427
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.817611866
Short name T44
Test name
Test status
Simulation time 549273455204 ps
CPU time 1356.13 seconds
Started Jul 24 04:25:47 PM PDT 24
Finished Jul 24 04:48:24 PM PDT 24
Peak memory 191508 kb
Host smart-f388d25e-ae33-4abe-8ffe-2936088e9bcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817611866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.817611866
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.3766134967
Short name T236
Test name
Test status
Simulation time 307355691721 ps
CPU time 150.81 seconds
Started Jul 24 04:25:47 PM PDT 24
Finished Jul 24 04:28:19 PM PDT 24
Peak memory 193440 kb
Host smart-ad3de5f6-be18-40f6-ba88-4e989ca78013
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766134967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.3766134967
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.2647129484
Short name T301
Test name
Test status
Simulation time 126072897448 ps
CPU time 217.56 seconds
Started Jul 24 04:26:00 PM PDT 24
Finished Jul 24 04:29:37 PM PDT 24
Peak memory 191548 kb
Host smart-87fb47ca-a545-4a0d-89ce-5cd1b1200007
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647129484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.2647129484
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.545919250
Short name T2
Test name
Test status
Simulation time 291641898407 ps
CPU time 181.9 seconds
Started Jul 24 04:25:57 PM PDT 24
Finished Jul 24 04:28:59 PM PDT 24
Peak memory 191596 kb
Host smart-59a25f1e-4b5a-4130-86ac-9166172da96c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545919250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.545919250
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.4051213933
Short name T260
Test name
Test status
Simulation time 345157627663 ps
CPU time 724.98 seconds
Started Jul 24 04:26:14 PM PDT 24
Finished Jul 24 04:38:19 PM PDT 24
Peak memory 191536 kb
Host smart-c21825e8-0e3b-4c51-bd01-f1930fc9e9d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051213933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.4051213933
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.2573027177
Short name T212
Test name
Test status
Simulation time 397749379755 ps
CPU time 456.98 seconds
Started Jul 24 04:25:58 PM PDT 24
Finished Jul 24 04:33:35 PM PDT 24
Peak memory 191536 kb
Host smart-b93af1f5-00e8-4176-b98e-ce6e7e3c67a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573027177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.2573027177
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.3509112776
Short name T222
Test name
Test status
Simulation time 48775420210 ps
CPU time 73.14 seconds
Started Jul 24 04:25:54 PM PDT 24
Finished Jul 24 04:27:07 PM PDT 24
Peak memory 183264 kb
Host smart-5d8af3ef-4255-44df-828e-3bcd6193c80d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509112776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.3509112776
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.1725605443
Short name T163
Test name
Test status
Simulation time 1425611170355 ps
CPU time 482.55 seconds
Started Jul 24 04:26:01 PM PDT 24
Finished Jul 24 04:34:04 PM PDT 24
Peak memory 191556 kb
Host smart-d33f82bf-4a94-4a1f-90a5-04d59d908789
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725605443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.1725605443
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.4114172428
Short name T10
Test name
Test status
Simulation time 31986050914 ps
CPU time 32.45 seconds
Started Jul 24 04:21:53 PM PDT 24
Finished Jul 24 04:22:25 PM PDT 24
Peak memory 183400 kb
Host smart-0bc8b22b-3e7c-452e-8bd7-674cca13fc8e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114172428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.4114172428
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.3887354348
Short name T421
Test name
Test status
Simulation time 426841947238 ps
CPU time 151.54 seconds
Started Jul 24 04:25:54 PM PDT 24
Finished Jul 24 04:28:26 PM PDT 24
Peak memory 183324 kb
Host smart-b8defad8-f56d-4e9b-a4d2-70b186312e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887354348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.3887354348
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.255641224
Short name T267
Test name
Test status
Simulation time 272511910539 ps
CPU time 569.6 seconds
Started Jul 24 04:22:24 PM PDT 24
Finished Jul 24 04:31:54 PM PDT 24
Peak memory 191588 kb
Host smart-d7ad0744-505d-4ca4-a4a0-0c2640bc777b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255641224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.255641224
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.1763209563
Short name T136
Test name
Test status
Simulation time 174821587554 ps
CPU time 96.75 seconds
Started Jul 24 04:25:44 PM PDT 24
Finished Jul 24 04:27:21 PM PDT 24
Peak memory 195352 kb
Host smart-b5754fec-5157-48cf-8d7d-1d46ff12b4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763209563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.1763209563
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.2011201136
Short name T68
Test name
Test status
Simulation time 194674724716 ps
CPU time 283.96 seconds
Started Jul 24 04:23:42 PM PDT 24
Finished Jul 24 04:28:26 PM PDT 24
Peak memory 194988 kb
Host smart-446921e3-e243-4fa5-8571-bb909aa0912f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011201136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
2011201136
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/90.rv_timer_random.247933484
Short name T307
Test name
Test status
Simulation time 85889247465 ps
CPU time 341 seconds
Started Jul 24 04:26:04 PM PDT 24
Finished Jul 24 04:31:45 PM PDT 24
Peak memory 191420 kb
Host smart-57105db9-457d-4f42-aa0f-731bcc43bf8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247933484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.247933484
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.2232804940
Short name T211
Test name
Test status
Simulation time 330362047811 ps
CPU time 107.36 seconds
Started Jul 24 04:25:53 PM PDT 24
Finished Jul 24 04:27:41 PM PDT 24
Peak memory 191628 kb
Host smart-a930e050-dbf6-4baf-8f41-c8944b9a49df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232804940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.2232804940
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.2597965553
Short name T18
Test name
Test status
Simulation time 148717879670 ps
CPU time 121.81 seconds
Started Jul 24 04:25:58 PM PDT 24
Finished Jul 24 04:28:01 PM PDT 24
Peak memory 191536 kb
Host smart-7d5902b5-568b-4c5e-8619-51caebe3a799
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597965553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.2597965553
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.2564236214
Short name T340
Test name
Test status
Simulation time 272026032415 ps
CPU time 299.04 seconds
Started Jul 24 04:26:00 PM PDT 24
Finished Jul 24 04:30:59 PM PDT 24
Peak memory 191536 kb
Host smart-2dfbe27c-14d4-4708-b7c5-67f57bc0d05f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564236214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.2564236214
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.2484749087
Short name T185
Test name
Test status
Simulation time 188214257309 ps
CPU time 159.16 seconds
Started Jul 24 04:25:57 PM PDT 24
Finished Jul 24 04:28:36 PM PDT 24
Peak memory 191596 kb
Host smart-8eb231dd-eb42-4c2c-9a47-71c72122ccdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484749087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.2484749087
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.4081636230
Short name T274
Test name
Test status
Simulation time 78933629554 ps
CPU time 119.41 seconds
Started Jul 24 04:26:04 PM PDT 24
Finished Jul 24 04:28:04 PM PDT 24
Peak memory 191392 kb
Host smart-d6cc7c2e-eb9b-46ea-9fb6-3fa56f053750
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081636230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.4081636230
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.1734860915
Short name T126
Test name
Test status
Simulation time 350420505712 ps
CPU time 1331.19 seconds
Started Jul 24 04:26:05 PM PDT 24
Finished Jul 24 04:48:17 PM PDT 24
Peak memory 191556 kb
Host smart-b56cd5fd-0902-43d1-9828-fb5a31617a3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734860915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.1734860915
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.3992833731
Short name T350
Test name
Test status
Simulation time 77310185326 ps
CPU time 50 seconds
Started Jul 24 04:26:05 PM PDT 24
Finished Jul 24 04:26:55 PM PDT 24
Peak memory 183356 kb
Host smart-2639576f-61b1-4c28-9a18-ee453d73ff68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992833731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.3992833731
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.549643307
Short name T334
Test name
Test status
Simulation time 649128760675 ps
CPU time 575.46 seconds
Started Jul 24 04:25:59 PM PDT 24
Finished Jul 24 04:35:34 PM PDT 24
Peak memory 191516 kb
Host smart-a56e289e-01e6-4374-99ff-02500dd4f86a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549643307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.549643307
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.2654113425
Short name T181
Test name
Test status
Simulation time 161263392573 ps
CPU time 233.74 seconds
Started Jul 24 04:26:00 PM PDT 24
Finished Jul 24 04:29:54 PM PDT 24
Peak memory 192536 kb
Host smart-2d0f6d88-971b-43ba-b930-e1922aa3d4ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654113425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.2654113425
Directory /workspace/99.rv_timer_random/latest
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