Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.61 99.36 98.73 100.00 100.00 100.00 99.55


Total test records in report: 577
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T506 /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.1490979280 Jul 25 04:52:54 PM PDT 24 Jul 25 04:52:56 PM PDT 24 325956161 ps
T507 /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.3489732582 Jul 25 04:52:51 PM PDT 24 Jul 25 04:52:53 PM PDT 24 1741391181 ps
T508 /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.1903592122 Jul 25 04:52:50 PM PDT 24 Jul 25 04:52:52 PM PDT 24 38680138 ps
T509 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.491035211 Jul 25 04:52:52 PM PDT 24 Jul 25 04:52:57 PM PDT 24 31620168 ps
T510 /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1891182533 Jul 25 04:52:56 PM PDT 24 Jul 25 04:52:57 PM PDT 24 18283754 ps
T511 /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.331154253 Jul 25 04:52:52 PM PDT 24 Jul 25 04:52:55 PM PDT 24 204766772 ps
T512 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.3871749663 Jul 25 04:52:54 PM PDT 24 Jul 25 04:52:55 PM PDT 24 42926944 ps
T513 /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.1232657116 Jul 25 04:52:34 PM PDT 24 Jul 25 04:52:35 PM PDT 24 79685649 ps
T514 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2674188100 Jul 25 04:53:00 PM PDT 24 Jul 25 04:53:01 PM PDT 24 27972766 ps
T515 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3543821618 Jul 25 04:52:49 PM PDT 24 Jul 25 04:52:50 PM PDT 24 27196623 ps
T516 /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.610391844 Jul 25 04:52:38 PM PDT 24 Jul 25 04:52:39 PM PDT 24 103630014 ps
T517 /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.3461187599 Jul 25 04:52:53 PM PDT 24 Jul 25 04:52:55 PM PDT 24 1007254692 ps
T518 /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.2221184468 Jul 25 04:52:54 PM PDT 24 Jul 25 04:52:55 PM PDT 24 11816828 ps
T519 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.555652341 Jul 25 04:52:55 PM PDT 24 Jul 25 04:53:01 PM PDT 24 30846314 ps
T520 /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.1612690478 Jul 25 04:52:46 PM PDT 24 Jul 25 04:52:46 PM PDT 24 41248379 ps
T521 /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.1389269283 Jul 25 04:52:47 PM PDT 24 Jul 25 04:52:48 PM PDT 24 18666975 ps
T522 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.734145716 Jul 25 04:53:01 PM PDT 24 Jul 25 04:53:02 PM PDT 24 62487506 ps
T523 /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.2395787219 Jul 25 04:52:53 PM PDT 24 Jul 25 04:52:54 PM PDT 24 51649712 ps
T524 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.3635660573 Jul 25 04:52:53 PM PDT 24 Jul 25 04:52:54 PM PDT 24 16744091 ps
T525 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.2791812586 Jul 25 04:52:22 PM PDT 24 Jul 25 04:52:23 PM PDT 24 122527339 ps
T84 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.3022067067 Jul 25 04:52:50 PM PDT 24 Jul 25 04:52:50 PM PDT 24 21029845 ps
T526 /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.708832312 Jul 25 04:52:52 PM PDT 24 Jul 25 04:52:55 PM PDT 24 1131828320 ps
T527 /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.2344122604 Jul 25 04:53:02 PM PDT 24 Jul 25 04:53:03 PM PDT 24 25767885 ps
T85 /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.1884695419 Jul 25 04:53:03 PM PDT 24 Jul 25 04:53:04 PM PDT 24 63449265 ps
T528 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.976370442 Jul 25 04:52:53 PM PDT 24 Jul 25 04:52:54 PM PDT 24 94940137 ps
T529 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.1186643974 Jul 25 04:53:00 PM PDT 24 Jul 25 04:53:01 PM PDT 24 624674957 ps
T530 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.157983227 Jul 25 04:52:50 PM PDT 24 Jul 25 04:52:51 PM PDT 24 20620679 ps
T531 /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3651042979 Jul 25 04:52:58 PM PDT 24 Jul 25 04:52:59 PM PDT 24 55419955 ps
T532 /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.2573367715 Jul 25 04:52:49 PM PDT 24 Jul 25 04:52:50 PM PDT 24 60340886 ps
T533 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.3622133807 Jul 25 04:52:53 PM PDT 24 Jul 25 04:52:55 PM PDT 24 456529644 ps
T534 /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.1717256450 Jul 25 04:52:49 PM PDT 24 Jul 25 04:52:50 PM PDT 24 47468617 ps
T535 /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.4164564803 Jul 25 04:52:47 PM PDT 24 Jul 25 04:52:48 PM PDT 24 15889274 ps
T536 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.4261513192 Jul 25 04:52:46 PM PDT 24 Jul 25 04:52:46 PM PDT 24 12390892 ps
T86 /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.2473330975 Jul 25 04:52:36 PM PDT 24 Jul 25 04:52:37 PM PDT 24 17464091 ps
T537 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.2505731898 Jul 25 04:53:04 PM PDT 24 Jul 25 04:53:05 PM PDT 24 42610456 ps
T538 /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.1422882483 Jul 25 04:52:51 PM PDT 24 Jul 25 04:52:53 PM PDT 24 35755349 ps
T539 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.1754795559 Jul 25 04:52:53 PM PDT 24 Jul 25 04:52:54 PM PDT 24 74637290 ps
T540 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.1161952654 Jul 25 04:52:28 PM PDT 24 Jul 25 04:52:29 PM PDT 24 265112426 ps
T541 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.1022317597 Jul 25 04:52:47 PM PDT 24 Jul 25 04:52:48 PM PDT 24 11805539 ps
T542 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.3820731558 Jul 25 04:53:01 PM PDT 24 Jul 25 04:53:03 PM PDT 24 109783985 ps
T543 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.3612628723 Jul 25 04:52:46 PM PDT 24 Jul 25 04:52:47 PM PDT 24 51722795 ps
T544 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1530214076 Jul 25 04:53:04 PM PDT 24 Jul 25 04:53:07 PM PDT 24 292635009 ps
T545 /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.2882657251 Jul 25 04:52:49 PM PDT 24 Jul 25 04:52:49 PM PDT 24 17240764 ps
T546 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.139366746 Jul 25 04:52:49 PM PDT 24 Jul 25 04:52:52 PM PDT 24 130109203 ps
T104 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.2264291721 Jul 25 04:52:52 PM PDT 24 Jul 25 04:52:54 PM PDT 24 114087896 ps
T547 /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.4143825500 Jul 25 04:52:53 PM PDT 24 Jul 25 04:52:54 PM PDT 24 192740889 ps
T548 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.2038330308 Jul 25 04:52:51 PM PDT 24 Jul 25 04:52:53 PM PDT 24 27098134 ps
T549 /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.2889338224 Jul 25 04:52:59 PM PDT 24 Jul 25 04:53:00 PM PDT 24 61274912 ps
T550 /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.4196659745 Jul 25 04:53:02 PM PDT 24 Jul 25 04:53:03 PM PDT 24 16116404 ps
T551 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.1945141060 Jul 25 04:53:02 PM PDT 24 Jul 25 04:53:03 PM PDT 24 13660726 ps
T552 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.1348261423 Jul 25 04:52:41 PM PDT 24 Jul 25 04:52:42 PM PDT 24 12654910 ps
T553 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.1161409523 Jul 25 04:53:00 PM PDT 24 Jul 25 04:53:01 PM PDT 24 66491952 ps
T554 /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.3154124634 Jul 25 04:53:01 PM PDT 24 Jul 25 04:53:02 PM PDT 24 97154376 ps
T555 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.4212641558 Jul 25 04:52:50 PM PDT 24 Jul 25 04:52:51 PM PDT 24 74239813 ps
T556 /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.2651685176 Jul 25 04:52:59 PM PDT 24 Jul 25 04:53:00 PM PDT 24 42963133 ps
T557 /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.3095574460 Jul 25 04:52:53 PM PDT 24 Jul 25 04:52:54 PM PDT 24 88430725 ps
T558 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1423053827 Jul 25 04:52:55 PM PDT 24 Jul 25 04:52:57 PM PDT 24 193873194 ps
T559 /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.4143206138 Jul 25 04:52:51 PM PDT 24 Jul 25 04:52:51 PM PDT 24 30380455 ps
T560 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.2102677767 Jul 25 04:52:53 PM PDT 24 Jul 25 04:52:54 PM PDT 24 121947946 ps
T561 /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.3952195274 Jul 25 04:53:02 PM PDT 24 Jul 25 04:53:03 PM PDT 24 18910910 ps
T562 /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.2292785594 Jul 25 04:53:05 PM PDT 24 Jul 25 04:53:05 PM PDT 24 35596053 ps
T563 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1364140068 Jul 25 04:52:53 PM PDT 24 Jul 25 04:52:54 PM PDT 24 318069332 ps
T564 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.208643673 Jul 25 04:53:06 PM PDT 24 Jul 25 04:53:07 PM PDT 24 26923405 ps
T565 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3777375506 Jul 25 04:52:59 PM PDT 24 Jul 25 04:53:00 PM PDT 24 19218254 ps
T566 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1136128407 Jul 25 04:52:59 PM PDT 24 Jul 25 04:53:01 PM PDT 24 85350483 ps
T567 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.3096431287 Jul 25 04:52:53 PM PDT 24 Jul 25 04:52:53 PM PDT 24 16713198 ps
T568 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.3712661807 Jul 25 04:52:46 PM PDT 24 Jul 25 04:52:47 PM PDT 24 14586107 ps
T569 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.4008496641 Jul 25 04:52:52 PM PDT 24 Jul 25 04:52:52 PM PDT 24 14679316 ps
T570 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.1414282091 Jul 25 04:52:49 PM PDT 24 Jul 25 04:52:51 PM PDT 24 153894966 ps
T571 /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.4171548224 Jul 25 04:52:53 PM PDT 24 Jul 25 04:52:58 PM PDT 24 16764055 ps
T572 /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.480668291 Jul 25 04:52:51 PM PDT 24 Jul 25 04:52:52 PM PDT 24 22956668 ps
T87 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.820323630 Jul 25 04:52:39 PM PDT 24 Jul 25 04:52:40 PM PDT 24 89923296 ps
T573 /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.2439342855 Jul 25 04:52:50 PM PDT 24 Jul 25 04:52:51 PM PDT 24 25345017 ps
T574 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2839351924 Jul 25 04:53:19 PM PDT 24 Jul 25 04:53:20 PM PDT 24 69300699 ps
T575 /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.2395503150 Jul 25 04:52:52 PM PDT 24 Jul 25 04:52:53 PM PDT 24 131553346 ps
T576 /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.2649708929 Jul 25 04:52:56 PM PDT 24 Jul 25 04:52:57 PM PDT 24 21258700 ps
T577 /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.1534434788 Jul 25 04:52:39 PM PDT 24 Jul 25 04:52:40 PM PDT 24 61182394 ps

Test location /workspace/coverage/default/21.rv_timer_stress_all_with_rand_reset.1521478486
Short name T1
Test name
Test status
Simulation time 18812788353 ps
CPU time 110.96 seconds
Started Jul 25 04:53:30 PM PDT 24
Finished Jul 25 04:55:21 PM PDT 24
Peak memory 196916 kb
Host smart-48186060-5b8d-4fcb-9eed-5a84ce22703d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521478486 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all_with_rand_reset.1521478486
Directory /workspace/21.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.2665067702
Short name T26
Test name
Test status
Simulation time 1408451502369 ps
CPU time 3197.33 seconds
Started Jul 25 04:53:24 PM PDT 24
Finished Jul 25 05:46:42 PM PDT 24
Peak memory 196544 kb
Host smart-4bcbfe2b-997b-4b61-93f9-8568e6a78617
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665067702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.2665067702
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.2712621481
Short name T24
Test name
Test status
Simulation time 115974460 ps
CPU time 1.42 seconds
Started Jul 25 04:52:58 PM PDT 24
Finished Jul 25 04:53:00 PM PDT 24
Peak memory 194640 kb
Host smart-cfdf0748-20e5-42bc-8b33-4b047d99b7d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712621481 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.2712621481
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.3961202440
Short name T8
Test name
Test status
Simulation time 400955024375 ps
CPU time 1289.7 seconds
Started Jul 25 04:53:06 PM PDT 24
Finished Jul 25 05:14:36 PM PDT 24
Peak memory 191684 kb
Host smart-64ffe74f-0e35-46cf-ab72-52a935acce58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961202440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
3961202440
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.2571445248
Short name T157
Test name
Test status
Simulation time 1069771700282 ps
CPU time 2342.57 seconds
Started Jul 25 04:53:38 PM PDT 24
Finished Jul 25 05:32:40 PM PDT 24
Peak memory 191764 kb
Host smart-12b47f31-8393-432b-876d-6ec1da6b566a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571445248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.2571445248
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.4110645342
Short name T155
Test name
Test status
Simulation time 2950118617956 ps
CPU time 2229.48 seconds
Started Jul 25 04:53:10 PM PDT 24
Finished Jul 25 05:30:20 PM PDT 24
Peak memory 191720 kb
Host smart-3bfd089c-25ad-427b-b777-eeb609cc8b24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110645342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.4110645342
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.2624891452
Short name T166
Test name
Test status
Simulation time 3709292703552 ps
CPU time 1484.89 seconds
Started Jul 25 04:53:31 PM PDT 24
Finished Jul 25 05:18:16 PM PDT 24
Peak memory 191748 kb
Host smart-33ae193f-b917-4baa-a8cb-6dfb8d6d41b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624891452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.2624891452
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.475904555
Short name T239
Test name
Test status
Simulation time 3334908642162 ps
CPU time 2544.32 seconds
Started Jul 25 04:53:46 PM PDT 24
Finished Jul 25 05:36:11 PM PDT 24
Peak memory 191780 kb
Host smart-10814e92-7faa-4661-b636-c0eaa130b41f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475904555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all.
475904555
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.522160416
Short name T56
Test name
Test status
Simulation time 2464960554191 ps
CPU time 1262.56 seconds
Started Jul 25 04:53:35 PM PDT 24
Finished Jul 25 05:14:38 PM PDT 24
Peak memory 191768 kb
Host smart-af3f3d7f-190c-4a03-8951-00eebecdfdd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522160416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all.
522160416
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.3062597780
Short name T195
Test name
Test status
Simulation time 903189556755 ps
CPU time 938.78 seconds
Started Jul 25 04:53:42 PM PDT 24
Finished Jul 25 05:09:21 PM PDT 24
Peak memory 191768 kb
Host smart-e18db638-e828-4b0a-820c-aabc6d3a0ad3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062597780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.3062597780
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.2515373726
Short name T119
Test name
Test status
Simulation time 1849828411880 ps
CPU time 862.33 seconds
Started Jul 25 04:53:10 PM PDT 24
Finished Jul 25 05:07:32 PM PDT 24
Peak memory 191684 kb
Host smart-267bda7d-4ad3-40d2-bba2-a5051bff01eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515373726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.2515373726
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_random.108576354
Short name T5
Test name
Test status
Simulation time 110524488999 ps
CPU time 308.93 seconds
Started Jul 25 04:53:02 PM PDT 24
Finished Jul 25 04:58:12 PM PDT 24
Peak memory 191664 kb
Host smart-13f836a6-0d42-4b3e-b90a-c2b003d165e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108576354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.108576354
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.2978213117
Short name T83
Test name
Test status
Simulation time 42234461 ps
CPU time 0.69 seconds
Started Jul 25 04:52:31 PM PDT 24
Finished Jul 25 04:52:32 PM PDT 24
Peak memory 192144 kb
Host smart-512de863-f72e-4284-8380-6aceaf734473
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978213117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.2978213117
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.223191045
Short name T179
Test name
Test status
Simulation time 1394396254402 ps
CPU time 2115.07 seconds
Started Jul 25 04:53:44 PM PDT 24
Finished Jul 25 05:28:59 PM PDT 24
Peak memory 191776 kb
Host smart-995f14b8-6dee-422b-8064-6571109ff82b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223191045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all.
223191045
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.2255530888
Short name T14
Test name
Test status
Simulation time 211526063 ps
CPU time 0.81 seconds
Started Jul 25 04:53:02 PM PDT 24
Finished Jul 25 04:53:04 PM PDT 24
Peak memory 214396 kb
Host smart-226be360-4f5f-4de1-84da-c4435aa8d9da
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255530888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.2255530888
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/16.rv_timer_random.2056093130
Short name T175
Test name
Test status
Simulation time 1742509966300 ps
CPU time 540.82 seconds
Started Jul 25 04:53:06 PM PDT 24
Finished Jul 25 05:02:07 PM PDT 24
Peak memory 191764 kb
Host smart-428d7a41-307d-44cf-a9e0-442d0d4fc367
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056093130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.2056093130
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.1966935276
Short name T218
Test name
Test status
Simulation time 760099814854 ps
CPU time 965.61 seconds
Started Jul 25 04:53:29 PM PDT 24
Finished Jul 25 05:09:34 PM PDT 24
Peak memory 196120 kb
Host smart-72372e3b-a562-447a-9030-26edda848fdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966935276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.1966935276
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.2640330473
Short name T153
Test name
Test status
Simulation time 1996220837286 ps
CPU time 1171.47 seconds
Started Jul 25 04:53:06 PM PDT 24
Finished Jul 25 05:12:38 PM PDT 24
Peak memory 191668 kb
Host smart-2843aeae-e306-4c1d-a20a-bd0459b04694
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640330473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
2640330473
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/153.rv_timer_random.1915109404
Short name T98
Test name
Test status
Simulation time 1365434818521 ps
CPU time 693.44 seconds
Started Jul 25 04:53:46 PM PDT 24
Finished Jul 25 05:05:20 PM PDT 24
Peak memory 191776 kb
Host smart-41557f8c-8e44-4e37-865e-224568678015
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915109404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.1915109404
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.4149424013
Short name T149
Test name
Test status
Simulation time 524611000587 ps
CPU time 1257.96 seconds
Started Jul 25 04:53:46 PM PDT 24
Finished Jul 25 05:14:44 PM PDT 24
Peak memory 191680 kb
Host smart-02ec8587-ac8d-4b04-b320-c7a9aafd851c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149424013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.4149424013
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.1407673473
Short name T151
Test name
Test status
Simulation time 335787157583 ps
CPU time 514.95 seconds
Started Jul 25 04:53:27 PM PDT 24
Finished Jul 25 05:02:03 PM PDT 24
Peak memory 191776 kb
Host smart-a74ae310-4969-4098-8e2f-92ca50bd3886
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407673473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.1407673473
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.4229980834
Short name T75
Test name
Test status
Simulation time 20818773 ps
CPU time 0.64 seconds
Started Jul 25 04:52:52 PM PDT 24
Finished Jul 25 04:52:53 PM PDT 24
Peak memory 192280 kb
Host smart-109a42ac-b008-4bb3-aa38-add0077662fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229980834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.4229980834
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.2022744609
Short name T196
Test name
Test status
Simulation time 409389747981 ps
CPU time 613.42 seconds
Started Jul 25 04:53:19 PM PDT 24
Finished Jul 25 05:03:33 PM PDT 24
Peak memory 196000 kb
Host smart-e408a9b6-8939-406e-9948-ab2622a10a7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022744609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.2022744609
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.3197527166
Short name T57
Test name
Test status
Simulation time 250281136934 ps
CPU time 901.97 seconds
Started Jul 25 04:52:52 PM PDT 24
Finished Jul 25 05:07:54 PM PDT 24
Peak memory 191696 kb
Host smart-e9862afe-c6c5-446c-a5d9-42c9e4a0dfb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197527166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
3197527166
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/127.rv_timer_random.995419745
Short name T145
Test name
Test status
Simulation time 162266784026 ps
CPU time 696.42 seconds
Started Jul 25 04:53:53 PM PDT 24
Finished Jul 25 05:05:30 PM PDT 24
Peak memory 191660 kb
Host smart-2bd60af8-41d7-4ac3-b2ae-01b48c17b22f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995419745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.995419745
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.2343638086
Short name T124
Test name
Test status
Simulation time 86289223957 ps
CPU time 114.28 seconds
Started Jul 25 04:53:56 PM PDT 24
Finished Jul 25 04:55:50 PM PDT 24
Peak memory 191688 kb
Host smart-f4ec33ff-8670-481b-8481-df08126f168d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343638086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.2343638086
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.3285279874
Short name T156
Test name
Test status
Simulation time 517370520964 ps
CPU time 306.23 seconds
Started Jul 25 04:53:43 PM PDT 24
Finished Jul 25 04:58:49 PM PDT 24
Peak memory 191852 kb
Host smart-f326e10c-04d5-4bf9-804b-2c172929cdea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285279874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.3285279874
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.204441748
Short name T432
Test name
Test status
Simulation time 348569330671 ps
CPU time 235.84 seconds
Started Jul 25 04:53:48 PM PDT 24
Finished Jul 25 04:57:44 PM PDT 24
Peak memory 191800 kb
Host smart-9516a634-d162-4f22-b348-e6b2a8ceb4d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204441748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.204441748
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.3438285677
Short name T297
Test name
Test status
Simulation time 970965420242 ps
CPU time 2429.33 seconds
Started Jul 25 04:53:08 PM PDT 24
Finished Jul 25 05:33:37 PM PDT 24
Peak memory 191748 kb
Host smart-ab52e2d4-d32b-402b-818e-ba2ad3377d38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438285677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.3438285677
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.2976293154
Short name T229
Test name
Test status
Simulation time 2991454754556 ps
CPU time 1533.71 seconds
Started Jul 25 04:53:38 PM PDT 24
Finished Jul 25 05:19:12 PM PDT 24
Peak memory 196220 kb
Host smart-8f26555e-c241-4304-b7c3-bb3fbeafe68e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976293154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.2976293154
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/78.rv_timer_random.2222264612
Short name T295
Test name
Test status
Simulation time 638589946818 ps
CPU time 377.37 seconds
Started Jul 25 04:53:51 PM PDT 24
Finished Jul 25 05:00:08 PM PDT 24
Peak memory 191812 kb
Host smart-51de803e-809f-4128-b4b3-00999ff2e115
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222264612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.2222264612
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.1125625875
Short name T223
Test name
Test status
Simulation time 639743881123 ps
CPU time 305.82 seconds
Started Jul 25 04:53:54 PM PDT 24
Finished Jul 25 04:59:00 PM PDT 24
Peak memory 191684 kb
Host smart-07578b4c-5d69-4220-b921-e8869ed72657
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125625875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.1125625875
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.3026876456
Short name T245
Test name
Test status
Simulation time 176757651207 ps
CPU time 523.23 seconds
Started Jul 25 04:53:53 PM PDT 24
Finished Jul 25 05:02:37 PM PDT 24
Peak memory 191764 kb
Host smart-d89d1ae2-d017-4e99-9e75-b22b69fcb20e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026876456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.3026876456
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.226332039
Short name T273
Test name
Test status
Simulation time 116771378210 ps
CPU time 84.62 seconds
Started Jul 25 04:53:59 PM PDT 24
Finished Jul 25 04:55:24 PM PDT 24
Peak memory 191776 kb
Host smart-96c5b9ef-5633-405e-bab7-49fb65f9822c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226332039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.226332039
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.2305627863
Short name T214
Test name
Test status
Simulation time 351600882720 ps
CPU time 290.53 seconds
Started Jul 25 04:53:28 PM PDT 24
Finished Jul 25 04:58:19 PM PDT 24
Peak memory 191632 kb
Host smart-36982fe1-bbd8-4182-afaf-36af8dc7e357
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305627863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.2305627863
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_random.835259872
Short name T174
Test name
Test status
Simulation time 158811225480 ps
CPU time 599.75 seconds
Started Jul 25 04:53:02 PM PDT 24
Finished Jul 25 05:03:01 PM PDT 24
Peak memory 191772 kb
Host smart-460ebae8-3478-4cfb-a6e9-495d3e737006
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835259872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.835259872
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.1899173151
Short name T221
Test name
Test status
Simulation time 485758744649 ps
CPU time 222.59 seconds
Started Jul 25 04:53:57 PM PDT 24
Finished Jul 25 04:57:40 PM PDT 24
Peak memory 191764 kb
Host smart-52fdb919-27ad-41b9-bd6e-902dd9bd6a64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899173151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.1899173151
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.3283106786
Short name T241
Test name
Test status
Simulation time 1224072864307 ps
CPU time 490.46 seconds
Started Jul 25 04:53:51 PM PDT 24
Finished Jul 25 05:02:02 PM PDT 24
Peak memory 195648 kb
Host smart-81d35f5b-ce51-479c-80d9-800f87d8fb88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283106786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.3283106786
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.2960529625
Short name T113
Test name
Test status
Simulation time 721888780637 ps
CPU time 1355.84 seconds
Started Jul 25 04:53:55 PM PDT 24
Finished Jul 25 05:16:31 PM PDT 24
Peak memory 191680 kb
Host smart-18069310-ef43-4e59-aa47-90ffe80d42b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960529625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.2960529625
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.1846301241
Short name T215
Test name
Test status
Simulation time 1820607906535 ps
CPU time 289.44 seconds
Started Jul 25 04:53:46 PM PDT 24
Finished Jul 25 04:58:36 PM PDT 24
Peak memory 191696 kb
Host smart-3e3278a2-88ed-43fe-9c01-a5463dc6fda3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846301241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.1846301241
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.3226435033
Short name T60
Test name
Test status
Simulation time 375444965047 ps
CPU time 1148.41 seconds
Started Jul 25 04:53:52 PM PDT 24
Finished Jul 25 05:13:01 PM PDT 24
Peak memory 194500 kb
Host smart-6a96c759-605a-4e87-b201-4d5cec94d526
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226435033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.3226435033
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.2447855958
Short name T316
Test name
Test status
Simulation time 789125374037 ps
CPU time 639.06 seconds
Started Jul 25 04:53:04 PM PDT 24
Finished Jul 25 05:03:43 PM PDT 24
Peak memory 183468 kb
Host smart-ba9332b0-691b-48bf-a17f-41325b78151e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447855958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.2447855958
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/154.rv_timer_random.2664034787
Short name T197
Test name
Test status
Simulation time 151536607415 ps
CPU time 246.87 seconds
Started Jul 25 04:53:47 PM PDT 24
Finished Jul 25 04:57:54 PM PDT 24
Peak memory 191776 kb
Host smart-885cc9b8-9fb5-41ca-86b4-c036bed6a256
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664034787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.2664034787
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.707592693
Short name T199
Test name
Test status
Simulation time 672846304095 ps
CPU time 456.85 seconds
Started Jul 25 04:53:54 PM PDT 24
Finished Jul 25 05:01:31 PM PDT 24
Peak memory 191788 kb
Host smart-02348c69-ad0c-4ab5-855d-6748183ca712
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707592693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.707592693
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.4225236367
Short name T236
Test name
Test status
Simulation time 362332758236 ps
CPU time 547.77 seconds
Started Jul 25 04:53:37 PM PDT 24
Finished Jul 25 05:02:45 PM PDT 24
Peak memory 183580 kb
Host smart-ac249a20-e0bf-47f6-938b-d566dada172f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225236367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.4225236367
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/57.rv_timer_random.3253683408
Short name T144
Test name
Test status
Simulation time 1538899194004 ps
CPU time 1443.27 seconds
Started Jul 25 04:53:44 PM PDT 24
Finished Jul 25 05:17:47 PM PDT 24
Peak memory 191788 kb
Host smart-14e91a37-200b-4884-b38a-2a2d2580a243
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253683408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.3253683408
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.4232371659
Short name T267
Test name
Test status
Simulation time 540002417393 ps
CPU time 594.01 seconds
Started Jul 25 04:53:47 PM PDT 24
Finished Jul 25 05:03:41 PM PDT 24
Peak memory 191716 kb
Host smart-c02d0041-7654-42b5-a327-bb79be565560
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232371659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.4232371659
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random.4143702080
Short name T286
Test name
Test status
Simulation time 1814777176543 ps
CPU time 622.01 seconds
Started Jul 25 04:53:05 PM PDT 24
Finished Jul 25 05:03:27 PM PDT 24
Peak memory 191680 kb
Host smart-5f16de29-c85d-4df4-a9ec-473f868c9d91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143702080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.4143702080
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.4294603579
Short name T202
Test name
Test status
Simulation time 46909215636 ps
CPU time 63.07 seconds
Started Jul 25 04:53:48 PM PDT 24
Finished Jul 25 04:54:52 PM PDT 24
Peak memory 191664 kb
Host smart-f157f4da-f2f3-4120-88a5-94127170e4b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294603579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.4294603579
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random.1992208325
Short name T189
Test name
Test status
Simulation time 359673131033 ps
CPU time 2513.84 seconds
Started Jul 25 04:53:05 PM PDT 24
Finished Jul 25 05:34:59 PM PDT 24
Peak memory 195668 kb
Host smart-b74add8c-4e21-40cd-9804-0de93b13181b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992208325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.1992208325
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random.2201695562
Short name T129
Test name
Test status
Simulation time 280943989806 ps
CPU time 260.49 seconds
Started Jul 25 04:53:04 PM PDT 24
Finished Jul 25 04:57:25 PM PDT 24
Peak memory 191660 kb
Host smart-a5bb567a-e1e5-461b-9bbe-d210e0ecff12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201695562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.2201695562
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.1669363751
Short name T139
Test name
Test status
Simulation time 147978966911 ps
CPU time 302.38 seconds
Started Jul 25 04:54:00 PM PDT 24
Finished Jul 25 04:59:03 PM PDT 24
Peak memory 191760 kb
Host smart-eb157a81-bb41-4d9e-b140-709152f0a29a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669363751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.1669363751
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.2613548413
Short name T173
Test name
Test status
Simulation time 199401750772 ps
CPU time 226.9 seconds
Started Jul 25 04:54:04 PM PDT 24
Finished Jul 25 04:57:51 PM PDT 24
Peak memory 191772 kb
Host smart-4120b413-f427-4aff-b860-71bafb9e0959
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613548413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.2613548413
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.2157186911
Short name T291
Test name
Test status
Simulation time 578210961029 ps
CPU time 556.62 seconds
Started Jul 25 04:53:21 PM PDT 24
Finished Jul 25 05:02:38 PM PDT 24
Peak memory 183568 kb
Host smart-bd0acd5d-cd3e-4099-84e2-c4c32ae71c67
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157186911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.2157186911
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.1339671271
Short name T147
Test name
Test status
Simulation time 352170648832 ps
CPU time 1477.16 seconds
Started Jul 25 04:53:04 PM PDT 24
Finished Jul 25 05:17:41 PM PDT 24
Peak memory 191712 kb
Host smart-29371a17-3f08-4f21-bfb1-7dedb2c2ea78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339671271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
1339671271
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.1774456564
Short name T240
Test name
Test status
Simulation time 1447895613273 ps
CPU time 1249.92 seconds
Started Jul 25 04:53:39 PM PDT 24
Finished Jul 25 05:14:29 PM PDT 24
Peak memory 191632 kb
Host smart-7a36ee49-1592-46f9-a052-1e15ae00c675
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774456564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.1774456564
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/106.rv_timer_random.1407690095
Short name T94
Test name
Test status
Simulation time 611344127516 ps
CPU time 1825.95 seconds
Started Jul 25 04:53:52 PM PDT 24
Finished Jul 25 05:24:18 PM PDT 24
Peak memory 191764 kb
Host smart-645ce517-a45d-4739-b8c6-a08ec146e832
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407690095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.1407690095
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.2807752207
Short name T282
Test name
Test status
Simulation time 510259760541 ps
CPU time 294.72 seconds
Started Jul 25 04:53:47 PM PDT 24
Finished Jul 25 04:58:42 PM PDT 24
Peak memory 191756 kb
Host smart-a7784157-4306-47b7-a350-5fa08dbc4966
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807752207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.2807752207
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.2694210146
Short name T135
Test name
Test status
Simulation time 125520703821 ps
CPU time 294.71 seconds
Started Jul 25 04:53:55 PM PDT 24
Finished Jul 25 04:58:50 PM PDT 24
Peak memory 183564 kb
Host smart-4e5d7845-1091-435a-a150-c445b7662176
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694210146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.2694210146
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.2989680827
Short name T254
Test name
Test status
Simulation time 297619817884 ps
CPU time 255.56 seconds
Started Jul 25 04:53:52 PM PDT 24
Finished Jul 25 04:58:08 PM PDT 24
Peak memory 194568 kb
Host smart-3660ac91-c9ad-4480-8f12-b559b8e48ebc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989680827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.2989680827
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.2689818396
Short name T294
Test name
Test status
Simulation time 337148745214 ps
CPU time 323.16 seconds
Started Jul 25 04:53:52 PM PDT 24
Finished Jul 25 04:59:15 PM PDT 24
Peak memory 191764 kb
Host smart-b856fad7-0f27-44e3-aa66-68d574ac4360
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689818396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.2689818396
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.1665094995
Short name T198
Test name
Test status
Simulation time 377838771859 ps
CPU time 1160.28 seconds
Started Jul 25 04:53:55 PM PDT 24
Finished Jul 25 05:13:15 PM PDT 24
Peak memory 191740 kb
Host smart-73ec751e-30c7-419d-954d-4319259af0aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665094995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.1665094995
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.855727024
Short name T132
Test name
Test status
Simulation time 1432466469036 ps
CPU time 777.17 seconds
Started Jul 25 04:53:03 PM PDT 24
Finished Jul 25 05:06:01 PM PDT 24
Peak memory 191760 kb
Host smart-f3bfc6b9-c0df-4a7c-8d82-150c9fc75278
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855727024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all.
855727024
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/155.rv_timer_random.75694889
Short name T186
Test name
Test status
Simulation time 432676549814 ps
CPU time 1749.76 seconds
Started Jul 25 04:53:43 PM PDT 24
Finished Jul 25 05:22:53 PM PDT 24
Peak memory 194140 kb
Host smart-373a9cf5-d3f5-4a5d-a8c2-bf9667ce378d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75694889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.75694889
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/160.rv_timer_random.1617935331
Short name T176
Test name
Test status
Simulation time 271116291432 ps
CPU time 1688.88 seconds
Started Jul 25 04:53:55 PM PDT 24
Finished Jul 25 05:22:04 PM PDT 24
Peak memory 191712 kb
Host smart-3d8a3759-6ec2-4e1a-93a6-b1ceb249b4cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617935331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.1617935331
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.629263212
Short name T251
Test name
Test status
Simulation time 944138380965 ps
CPU time 1999.22 seconds
Started Jul 25 04:53:13 PM PDT 24
Finished Jul 25 05:26:32 PM PDT 24
Peak memory 191776 kb
Host smart-be27f336-cf05-40a3-a1af-458c134dc7b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629263212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all.
629263212
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/190.rv_timer_random.2467012925
Short name T159
Test name
Test status
Simulation time 96887796590 ps
CPU time 167.66 seconds
Started Jul 25 04:53:58 PM PDT 24
Finished Jul 25 04:56:46 PM PDT 24
Peak memory 191764 kb
Host smart-1956a6f8-6efd-4718-bfff-af7e9315f276
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467012925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.2467012925
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.3192512904
Short name T169
Test name
Test status
Simulation time 397968758097 ps
CPU time 992.17 seconds
Started Jul 25 04:53:32 PM PDT 24
Finished Jul 25 05:10:04 PM PDT 24
Peak memory 191784 kb
Host smart-551b19bb-27d5-4bba-89fe-7817962c2d71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192512904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.3192512904
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_random.2222403401
Short name T141
Test name
Test status
Simulation time 2180240540173 ps
CPU time 1021.66 seconds
Started Jul 25 04:53:12 PM PDT 24
Finished Jul 25 05:10:14 PM PDT 24
Peak memory 191764 kb
Host smart-fbe3c137-8ef9-436e-96e3-d16ab440c331
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222403401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.2222403401
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.3919705273
Short name T440
Test name
Test status
Simulation time 75855115221 ps
CPU time 160.97 seconds
Started Jul 25 04:53:54 PM PDT 24
Finished Jul 25 04:56:35 PM PDT 24
Peak memory 191788 kb
Host smart-bf99944a-b7bc-4fdc-abbc-63379710d9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919705273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.3919705273
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/82.rv_timer_random.2785055775
Short name T182
Test name
Test status
Simulation time 373174923832 ps
CPU time 205.29 seconds
Started Jul 25 04:53:47 PM PDT 24
Finished Jul 25 04:57:13 PM PDT 24
Peak memory 191764 kb
Host smart-3341e364-1902-4dab-a23d-f000a995fd29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785055775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.2785055775
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.2264291721
Short name T104
Test name
Test status
Simulation time 114087896 ps
CPU time 1.32 seconds
Started Jul 25 04:52:52 PM PDT 24
Finished Jul 25 04:52:54 PM PDT 24
Peak memory 195520 kb
Host smart-415ad8b8-5216-4856-8679-e599528e661c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264291721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.2264291721
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.3608401949
Short name T238
Test name
Test status
Simulation time 1088364928384 ps
CPU time 545.85 seconds
Started Jul 25 04:52:54 PM PDT 24
Finished Jul 25 05:02:00 PM PDT 24
Peak memory 183480 kb
Host smart-c6f9e3c0-5104-48fb-ab5e-ef44cc997286
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608401949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.3608401949
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_random.22613189
Short name T167
Test name
Test status
Simulation time 365723074494 ps
CPU time 430.43 seconds
Started Jul 25 04:53:16 PM PDT 24
Finished Jul 25 05:00:27 PM PDT 24
Peak memory 191788 kb
Host smart-98812fb0-fed7-47bf-bd94-86d49526fa3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22613189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.22613189
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.1886696915
Short name T292
Test name
Test status
Simulation time 178091544574 ps
CPU time 1006.71 seconds
Started Jul 25 04:53:45 PM PDT 24
Finished Jul 25 05:10:33 PM PDT 24
Peak memory 191788 kb
Host smart-1983d6b8-cede-46e6-81d5-9ef5091c6ee8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886696915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.1886696915
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.1076807634
Short name T350
Test name
Test status
Simulation time 15443964645 ps
CPU time 106.12 seconds
Started Jul 25 04:53:47 PM PDT 24
Finished Jul 25 04:55:34 PM PDT 24
Peak memory 183568 kb
Host smart-5a32a0a4-ea74-480a-baa3-8196c090b9e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076807634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.1076807634
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.4059666757
Short name T40
Test name
Test status
Simulation time 328272278827 ps
CPU time 258.94 seconds
Started Jul 25 04:53:03 PM PDT 24
Finished Jul 25 04:57:22 PM PDT 24
Peak memory 183572 kb
Host smart-9b34247e-bfd3-462b-8aa0-9f76deb7798e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059666757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.4059666757
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.1261645745
Short name T191
Test name
Test status
Simulation time 177369572022 ps
CPU time 85.42 seconds
Started Jul 25 04:53:06 PM PDT 24
Finished Jul 25 04:54:37 PM PDT 24
Peak memory 183544 kb
Host smart-f0241241-57bf-47ee-89ab-7f0a4a99ea69
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261645745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.1261645745
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/130.rv_timer_random.2472473645
Short name T100
Test name
Test status
Simulation time 25868243178 ps
CPU time 76.81 seconds
Started Jul 25 04:53:45 PM PDT 24
Finished Jul 25 04:55:02 PM PDT 24
Peak memory 183540 kb
Host smart-daf4fdc3-0ad5-4fc7-9d91-b206fbd2b88a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472473645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.2472473645
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.739036574
Short name T148
Test name
Test status
Simulation time 137039528905 ps
CPU time 349.38 seconds
Started Jul 25 04:53:50 PM PDT 24
Finished Jul 25 04:59:40 PM PDT 24
Peak memory 194992 kb
Host smart-1128abc0-0251-4426-9422-9d52f692daf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739036574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.739036574
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.1722078820
Short name T172
Test name
Test status
Simulation time 1146159156725 ps
CPU time 819.71 seconds
Started Jul 25 04:53:45 PM PDT 24
Finished Jul 25 05:07:25 PM PDT 24
Peak memory 191660 kb
Host smart-48c4265b-dba7-4597-b37a-40725caf4cdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722078820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.1722078820
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.980012437
Short name T121
Test name
Test status
Simulation time 252476808279 ps
CPU time 261.65 seconds
Started Jul 25 04:53:48 PM PDT 24
Finished Jul 25 04:58:10 PM PDT 24
Peak memory 191776 kb
Host smart-aa98de4d-f2b7-4590-8ac9-76ff22aeb2cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980012437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.980012437
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.3116674416
Short name T107
Test name
Test status
Simulation time 293170956874 ps
CPU time 416.69 seconds
Started Jul 25 04:52:56 PM PDT 24
Finished Jul 25 04:59:53 PM PDT 24
Peak memory 183468 kb
Host smart-dc801d5f-87bc-4dac-9177-efd7d0c717fa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116674416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.3116674416
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.3539263441
Short name T308
Test name
Test status
Simulation time 245619619927 ps
CPU time 400.87 seconds
Started Jul 25 04:52:56 PM PDT 24
Finished Jul 25 04:59:37 PM PDT 24
Peak memory 183492 kb
Host smart-1ea72c03-8129-4d62-92d6-79da238c1ba5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539263441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.3539263441
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.852629731
Short name T253
Test name
Test status
Simulation time 464803341621 ps
CPU time 437.76 seconds
Started Jul 25 04:53:08 PM PDT 24
Finished Jul 25 05:00:26 PM PDT 24
Peak memory 183576 kb
Host smart-1c7936e5-c723-4f4f-a52a-0593c0025852
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852629731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.rv_timer_cfg_update_on_fly.852629731
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/187.rv_timer_random.1024430437
Short name T321
Test name
Test status
Simulation time 372653178034 ps
CPU time 267.37 seconds
Started Jul 25 04:53:49 PM PDT 24
Finished Jul 25 04:58:17 PM PDT 24
Peak memory 191764 kb
Host smart-6417d95c-e478-4d2d-8207-5ffd96da0b76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024430437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.1024430437
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.3972470013
Short name T225
Test name
Test status
Simulation time 18870701283 ps
CPU time 26.35 seconds
Started Jul 25 04:53:58 PM PDT 24
Finished Jul 25 04:54:24 PM PDT 24
Peak memory 191680 kb
Host smart-15835e7a-b719-4ba1-b935-20f9fccf72b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972470013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.3972470013
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random.1396409523
Short name T171
Test name
Test status
Simulation time 245535561268 ps
CPU time 193.91 seconds
Started Jul 25 04:53:14 PM PDT 24
Finished Jul 25 04:56:28 PM PDT 24
Peak memory 191732 kb
Host smart-574ce3ff-44a7-4ba6-8122-b3a9ad19822a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396409523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.1396409523
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.1537942069
Short name T299
Test name
Test status
Simulation time 14008981117 ps
CPU time 25.16 seconds
Started Jul 25 04:53:35 PM PDT 24
Finished Jul 25 04:54:01 PM PDT 24
Peak memory 183420 kb
Host smart-3aae4d6b-b292-4abd-abac-4f2176a02c62
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537942069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.1537942069
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_random.2283208522
Short name T96
Test name
Test status
Simulation time 119631918937 ps
CPU time 64.36 seconds
Started Jul 25 04:53:26 PM PDT 24
Finished Jul 25 04:54:30 PM PDT 24
Peak memory 191716 kb
Host smart-fc4b2b39-a19e-40ca-8172-26da1d407b3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283208522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.2283208522
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.1493257838
Short name T269
Test name
Test status
Simulation time 74129375675 ps
CPU time 32.3 seconds
Started Jul 25 04:53:15 PM PDT 24
Finished Jul 25 04:53:47 PM PDT 24
Peak memory 191804 kb
Host smart-60593422-9d5e-4803-8ad7-ac28f5d12b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493257838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.1493257838
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.1217036891
Short name T339
Test name
Test status
Simulation time 74734893917 ps
CPU time 18.92 seconds
Started Jul 25 04:53:41 PM PDT 24
Finished Jul 25 04:54:00 PM PDT 24
Peak memory 183576 kb
Host smart-cd9938bc-ba14-4de5-94e1-a4af5be96778
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217036891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.1217036891
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_random.2276013494
Short name T275
Test name
Test status
Simulation time 356361372150 ps
CPU time 410.9 seconds
Started Jul 25 04:53:31 PM PDT 24
Finished Jul 25 05:00:22 PM PDT 24
Peak memory 194992 kb
Host smart-a1144248-23c0-4ecb-b1d8-b7f775161761
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276013494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.2276013494
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.1600492575
Short name T247
Test name
Test status
Simulation time 314862481653 ps
CPU time 469.61 seconds
Started Jul 25 04:53:47 PM PDT 24
Finished Jul 25 05:01:37 PM PDT 24
Peak memory 183564 kb
Host smart-81179939-bc02-4e3e-8df0-fb6895d92947
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600492575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.1600492575
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_random.3116008671
Short name T317
Test name
Test status
Simulation time 23865350926 ps
CPU time 599.02 seconds
Started Jul 25 04:53:49 PM PDT 24
Finished Jul 25 05:03:48 PM PDT 24
Peak memory 191700 kb
Host smart-99b866c8-0b1c-4db1-8302-afa4e0dad6f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116008671 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.3116008671
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.3044055282
Short name T285
Test name
Test status
Simulation time 83317779074 ps
CPU time 127.4 seconds
Started Jul 25 04:53:45 PM PDT 24
Finished Jul 25 04:55:53 PM PDT 24
Peak memory 191792 kb
Host smart-c2845691-952e-4e56-a845-a2c9f4651d9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044055282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.3044055282
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.855994587
Short name T108
Test name
Test status
Simulation time 76623534102 ps
CPU time 117.73 seconds
Started Jul 25 04:53:53 PM PDT 24
Finished Jul 25 04:55:51 PM PDT 24
Peak memory 183580 kb
Host smart-15b55542-241e-466b-97cc-ef1dee80b5a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855994587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.855994587
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.2895605140
Short name T257
Test name
Test status
Simulation time 262067722355 ps
CPU time 133.3 seconds
Started Jul 25 04:54:01 PM PDT 24
Finished Jul 25 04:56:15 PM PDT 24
Peak memory 191668 kb
Host smart-8b8c9ebf-62a4-411f-a68c-6cf57808ff40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895605140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.2895605140
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.170623602
Short name T496
Test name
Test status
Simulation time 815759550 ps
CPU time 2.51 seconds
Started Jul 25 04:52:50 PM PDT 24
Finished Jul 25 04:52:53 PM PDT 24
Peak memory 191276 kb
Host smart-d2a3e826-72a9-41c3-b91a-defd616889b4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170623602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_b
ash.170623602
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.807859134
Short name T38
Test name
Test status
Simulation time 54280590 ps
CPU time 0.58 seconds
Started Jul 25 04:52:41 PM PDT 24
Finished Jul 25 04:52:41 PM PDT 24
Peak memory 182924 kb
Host smart-359334ae-f757-48ae-887b-0e10ef672891
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807859134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_re
set.807859134
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.2447821276
Short name T469
Test name
Test status
Simulation time 54342192 ps
CPU time 0.8 seconds
Started Jul 25 04:52:52 PM PDT 24
Finished Jul 25 04:52:53 PM PDT 24
Peak memory 195912 kb
Host smart-5f128d5d-b05d-4eae-9315-1b46d677d54f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447821276 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.2447821276
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.2473330975
Short name T86
Test name
Test status
Simulation time 17464091 ps
CPU time 0.56 seconds
Started Jul 25 04:52:36 PM PDT 24
Finished Jul 25 04:52:37 PM PDT 24
Peak memory 182904 kb
Host smart-ebf7cffc-ced6-47a9-97d7-f70ae2c78c3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473330975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.2473330975
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.3282625188
Short name T461
Test name
Test status
Simulation time 41514354 ps
CPU time 0.52 seconds
Started Jul 25 04:52:50 PM PDT 24
Finished Jul 25 04:52:51 PM PDT 24
Peak memory 182256 kb
Host smart-145c2f41-b8b6-4822-b94d-aae64aaaa39d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282625188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.3282625188
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.1232657116
Short name T513
Test name
Test status
Simulation time 79685649 ps
CPU time 0.69 seconds
Started Jul 25 04:52:34 PM PDT 24
Finished Jul 25 04:52:35 PM PDT 24
Peak memory 193456 kb
Host smart-ce09f1d0-6dca-4a19-9b2e-d23b6e288c55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232657116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.1232657116
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.3752089941
Short name T465
Test name
Test status
Simulation time 89148344 ps
CPU time 1.74 seconds
Started Jul 25 04:52:30 PM PDT 24
Finished Jul 25 04:52:32 PM PDT 24
Peak memory 197632 kb
Host smart-4d6cc909-7216-43b6-81a2-52c028973a59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752089941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.3752089941
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1760545542
Short name T491
Test name
Test status
Simulation time 630153219 ps
CPU time 1.09 seconds
Started Jul 25 04:52:41 PM PDT 24
Finished Jul 25 04:52:42 PM PDT 24
Peak memory 195440 kb
Host smart-779d02f4-3201-40c6-90d3-60532aa4d8aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760545542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.1760545542
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.2791812586
Short name T525
Test name
Test status
Simulation time 122527339 ps
CPU time 0.8 seconds
Started Jul 25 04:52:22 PM PDT 24
Finished Jul 25 04:52:23 PM PDT 24
Peak memory 192524 kb
Host smart-4fd53875-3aa4-4d5b-a651-c6296f6e4916
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791812586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.2791812586
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.70583838
Short name T78
Test name
Test status
Simulation time 1087791151 ps
CPU time 2.67 seconds
Started Jul 25 04:52:31 PM PDT 24
Finished Jul 25 04:52:34 PM PDT 24
Peak memory 191124 kb
Host smart-e7cbbae5-288a-44b1-a8a9-1e8094f16477
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70583838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_ba
sh.70583838
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.3712661807
Short name T568
Test name
Test status
Simulation time 14586107 ps
CPU time 0.56 seconds
Started Jul 25 04:52:46 PM PDT 24
Finished Jul 25 04:52:47 PM PDT 24
Peak memory 182888 kb
Host smart-b8ee9c4e-741c-460f-ad19-0155b3880103
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712661807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.3712661807
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.4034102792
Short name T25
Test name
Test status
Simulation time 73260490 ps
CPU time 0.7 seconds
Started Jul 25 04:52:48 PM PDT 24
Finished Jul 25 04:52:49 PM PDT 24
Peak memory 195456 kb
Host smart-283716f1-e3f2-41e0-9839-197c711e7a18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034102792 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.4034102792
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.4164564803
Short name T535
Test name
Test status
Simulation time 15889274 ps
CPU time 0.58 seconds
Started Jul 25 04:52:47 PM PDT 24
Finished Jul 25 04:52:48 PM PDT 24
Peak memory 192196 kb
Host smart-0c763903-de02-4fd3-a114-914aa4d2c37c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164564803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.4164564803
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.677622708
Short name T476
Test name
Test status
Simulation time 25957704 ps
CPU time 0.54 seconds
Started Jul 25 04:52:46 PM PDT 24
Finished Jul 25 04:52:47 PM PDT 24
Peak memory 182376 kb
Host smart-e7def081-3cd8-4bee-a217-20c279e42f10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677622708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.677622708
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.2357875508
Short name T79
Test name
Test status
Simulation time 56386434 ps
CPU time 0.76 seconds
Started Jul 25 04:52:31 PM PDT 24
Finished Jul 25 04:52:32 PM PDT 24
Peak memory 193664 kb
Host smart-a5a28b7d-66c0-41a8-976e-04349df8de40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357875508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.2357875508
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.2476635687
Short name T494
Test name
Test status
Simulation time 277120082 ps
CPU time 0.98 seconds
Started Jul 25 04:52:45 PM PDT 24
Finished Jul 25 04:52:47 PM PDT 24
Peak memory 197452 kb
Host smart-43559a6b-3c51-47c8-9f8e-119aac44c11a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476635687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.2476635687
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.1161952654
Short name T540
Test name
Test status
Simulation time 265112426 ps
CPU time 1.1 seconds
Started Jul 25 04:52:28 PM PDT 24
Finished Jul 25 04:52:29 PM PDT 24
Peak memory 193760 kb
Host smart-035ec7ad-a0a8-487f-846f-0fab8a54a999
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161952654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.1161952654
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.3820731558
Short name T542
Test name
Test status
Simulation time 109783985 ps
CPU time 1.3 seconds
Started Jul 25 04:53:01 PM PDT 24
Finished Jul 25 04:53:03 PM PDT 24
Peak memory 197712 kb
Host smart-bb16d281-1826-4374-8a55-9878e3951515
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820731558 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.3820731558
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.201935720
Short name T492
Test name
Test status
Simulation time 81599657 ps
CPU time 0.59 seconds
Started Jul 25 04:52:56 PM PDT 24
Finished Jul 25 04:52:57 PM PDT 24
Peak memory 182980 kb
Host smart-6449dd39-3bc8-4808-aa5d-528e31e761b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201935720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.201935720
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.3275261954
Short name T463
Test name
Test status
Simulation time 14108700 ps
CPU time 0.57 seconds
Started Jul 25 04:52:47 PM PDT 24
Finished Jul 25 04:52:48 PM PDT 24
Peak memory 182828 kb
Host smart-10f0936c-59b6-486a-9374-1db910401c2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275261954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.3275261954
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.4212641558
Short name T555
Test name
Test status
Simulation time 74239813 ps
CPU time 0.61 seconds
Started Jul 25 04:52:50 PM PDT 24
Finished Jul 25 04:52:51 PM PDT 24
Peak memory 192324 kb
Host smart-6e3ff730-dfe7-48c7-9549-f906d1e0d8a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212641558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.4212641558
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.139366746
Short name T546
Test name
Test status
Simulation time 130109203 ps
CPU time 2.7 seconds
Started Jul 25 04:52:49 PM PDT 24
Finished Jul 25 04:52:52 PM PDT 24
Peak memory 197700 kb
Host smart-7ea0a77c-91d1-436a-887c-c6b6f52fac3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139366746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.139366746
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.3120820174
Short name T23
Test name
Test status
Simulation time 72992740 ps
CPU time 1.02 seconds
Started Jul 25 04:52:50 PM PDT 24
Finished Jul 25 04:52:55 PM PDT 24
Peak memory 183576 kb
Host smart-f311273f-275f-4df7-ae7e-50dccce0ebf3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120820174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.3120820174
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.2649708929
Short name T576
Test name
Test status
Simulation time 21258700 ps
CPU time 1.02 seconds
Started Jul 25 04:52:56 PM PDT 24
Finished Jul 25 04:52:57 PM PDT 24
Peak memory 197536 kb
Host smart-f9aa9fc9-0d7d-4ce7-a528-a29339b2a33a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649708929 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.2649708929
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.2090629144
Short name T76
Test name
Test status
Simulation time 45970440 ps
CPU time 0.62 seconds
Started Jul 25 04:52:49 PM PDT 24
Finished Jul 25 04:52:50 PM PDT 24
Peak memory 182956 kb
Host smart-284b0935-ff47-433c-8f12-eb47cced7ae6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090629144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.2090629144
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.2882657251
Short name T545
Test name
Test status
Simulation time 17240764 ps
CPU time 0.61 seconds
Started Jul 25 04:52:49 PM PDT 24
Finished Jul 25 04:52:49 PM PDT 24
Peak memory 182916 kb
Host smart-c10f817c-592b-413b-84fb-94d8f026c517
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882657251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.2882657251
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3295043506
Short name T80
Test name
Test status
Simulation time 37660268 ps
CPU time 0.83 seconds
Started Jul 25 04:52:57 PM PDT 24
Finished Jul 25 04:52:58 PM PDT 24
Peak memory 191924 kb
Host smart-4929fe57-4728-4ae0-9641-0bd41e2eb47a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295043506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.3295043506
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.1161409523
Short name T553
Test name
Test status
Simulation time 66491952 ps
CPU time 1.3 seconds
Started Jul 25 04:53:00 PM PDT 24
Finished Jul 25 04:53:01 PM PDT 24
Peak memory 197672 kb
Host smart-3388e84d-8d89-48b1-98c0-b2006ea11559
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161409523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.1161409523
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.1490979280
Short name T506
Test name
Test status
Simulation time 325956161 ps
CPU time 1.26 seconds
Started Jul 25 04:52:54 PM PDT 24
Finished Jul 25 04:52:56 PM PDT 24
Peak memory 195452 kb
Host smart-b86c0823-6f9e-422a-a03a-073a41303500
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490979280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.1490979280
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3777375506
Short name T565
Test name
Test status
Simulation time 19218254 ps
CPU time 0.87 seconds
Started Jul 25 04:52:59 PM PDT 24
Finished Jul 25 04:53:00 PM PDT 24
Peak memory 197044 kb
Host smart-2ef6c458-1cae-49d1-b7e5-5135fe4a263f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777375506 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.3777375506
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2495326120
Short name T479
Test name
Test status
Simulation time 12304992 ps
CPU time 0.57 seconds
Started Jul 25 04:52:43 PM PDT 24
Finished Jul 25 04:52:44 PM PDT 24
Peak memory 182988 kb
Host smart-4b644dae-a123-4cb8-9c49-38a44318b166
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495326120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.2495326120
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.2736570065
Short name T505
Test name
Test status
Simulation time 100744092 ps
CPU time 0.54 seconds
Started Jul 25 04:52:58 PM PDT 24
Finished Jul 25 04:52:59 PM PDT 24
Peak memory 182480 kb
Host smart-9bb55289-97e3-43c0-90b9-cfdfff3aa597
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736570065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.2736570065
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.157983227
Short name T530
Test name
Test status
Simulation time 20620679 ps
CPU time 0.65 seconds
Started Jul 25 04:52:50 PM PDT 24
Finished Jul 25 04:52:51 PM PDT 24
Peak memory 191884 kb
Host smart-3318fe26-714a-4723-81da-e1d90e505d32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157983227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_ti
mer_same_csr_outstanding.157983227
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.331154253
Short name T511
Test name
Test status
Simulation time 204766772 ps
CPU time 2.49 seconds
Started Jul 25 04:52:52 PM PDT 24
Finished Jul 25 04:52:55 PM PDT 24
Peak memory 197604 kb
Host smart-b79fcbdb-3d74-4b47-8f9d-a3e3023d9cff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331154253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.331154253
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.437169737
Short name T467
Test name
Test status
Simulation time 20447428 ps
CPU time 0.82 seconds
Started Jul 25 04:52:49 PM PDT 24
Finished Jul 25 04:52:50 PM PDT 24
Peak memory 196476 kb
Host smart-647db1db-b189-403a-9228-6f018dfb1e6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437169737 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.437169737
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.2474184681
Short name T495
Test name
Test status
Simulation time 15828246 ps
CPU time 0.54 seconds
Started Jul 25 04:52:50 PM PDT 24
Finished Jul 25 04:52:51 PM PDT 24
Peak memory 182960 kb
Host smart-a9c60eb3-cc9a-44a6-9ca7-60b7816a3542
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474184681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.2474184681
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.1022317597
Short name T541
Test name
Test status
Simulation time 11805539 ps
CPU time 0.53 seconds
Started Jul 25 04:52:47 PM PDT 24
Finished Jul 25 04:52:48 PM PDT 24
Peak memory 182744 kb
Host smart-987f0a8f-4c98-4118-9fb3-bc5e677f67fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022317597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.1022317597
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1364140068
Short name T563
Test name
Test status
Simulation time 318069332 ps
CPU time 0.75 seconds
Started Jul 25 04:52:53 PM PDT 24
Finished Jul 25 04:52:54 PM PDT 24
Peak memory 193588 kb
Host smart-c38b3868-17a4-4c1e-a56c-e23ebeefcec7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364140068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.1364140068
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.734145716
Short name T522
Test name
Test status
Simulation time 62487506 ps
CPU time 1.2 seconds
Started Jul 25 04:53:01 PM PDT 24
Finished Jul 25 04:53:02 PM PDT 24
Peak memory 197672 kb
Host smart-4a4b9aac-a4c9-4b91-9122-f3d2900d73bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734145716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.734145716
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.3154124634
Short name T554
Test name
Test status
Simulation time 97154376 ps
CPU time 1.12 seconds
Started Jul 25 04:53:01 PM PDT 24
Finished Jul 25 04:53:02 PM PDT 24
Peak memory 195040 kb
Host smart-4c1da0f4-9082-4f24-8729-e61540b3ffa2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154124634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.3154124634
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.1903592122
Short name T508
Test name
Test status
Simulation time 38680138 ps
CPU time 0.93 seconds
Started Jul 25 04:52:50 PM PDT 24
Finished Jul 25 04:52:52 PM PDT 24
Peak memory 197624 kb
Host smart-9ce24a15-9d30-4747-88b9-95a247b20997
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903592122 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.1903592122
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3651042979
Short name T531
Test name
Test status
Simulation time 55419955 ps
CPU time 0.61 seconds
Started Jul 25 04:52:58 PM PDT 24
Finished Jul 25 04:52:59 PM PDT 24
Peak memory 182960 kb
Host smart-7e1913f5-15b8-4b22-8d2f-c1b2f39615ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651042979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.3651042979
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.1976873588
Short name T462
Test name
Test status
Simulation time 15561327 ps
CPU time 0.54 seconds
Started Jul 25 04:52:50 PM PDT 24
Finished Jul 25 04:52:51 PM PDT 24
Peak memory 182780 kb
Host smart-03fcc94a-de3c-4280-8552-2b76f8dc1690
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976873588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.1976873588
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.793490963
Short name T37
Test name
Test status
Simulation time 69743570 ps
CPU time 0.7 seconds
Started Jul 25 04:52:49 PM PDT 24
Finished Jul 25 04:52:50 PM PDT 24
Peak memory 192336 kb
Host smart-fd4bf3c3-bfc1-4700-a1f1-25a2a99f1fb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793490963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_ti
mer_same_csr_outstanding.793490963
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.3461187599
Short name T517
Test name
Test status
Simulation time 1007254692 ps
CPU time 1.96 seconds
Started Jul 25 04:52:53 PM PDT 24
Finished Jul 25 04:52:55 PM PDT 24
Peak memory 197812 kb
Host smart-5577ea92-6797-4f94-8ad0-e2dde97e69d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461187599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.3461187599
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.1186643974
Short name T529
Test name
Test status
Simulation time 624674957 ps
CPU time 1.23 seconds
Started Jul 25 04:53:00 PM PDT 24
Finished Jul 25 04:53:01 PM PDT 24
Peak memory 195420 kb
Host smart-8d634b8d-ddaa-46d0-8d31-9391c87b7e72
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186643974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.1186643974
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.421255820
Short name T39
Test name
Test status
Simulation time 71963674 ps
CPU time 0.71 seconds
Started Jul 25 04:52:51 PM PDT 24
Finished Jul 25 04:52:54 PM PDT 24
Peak memory 194324 kb
Host smart-c13b9e34-9c76-4c61-9cd7-6df44d1d0837
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421255820 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.421255820
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.3095574460
Short name T557
Test name
Test status
Simulation time 88430725 ps
CPU time 0.57 seconds
Started Jul 25 04:52:53 PM PDT 24
Finished Jul 25 04:52:54 PM PDT 24
Peak memory 183048 kb
Host smart-12964150-c4e1-42d8-bb10-2cc08276acb4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095574460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.3095574460
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2674188100
Short name T514
Test name
Test status
Simulation time 27972766 ps
CPU time 0.56 seconds
Started Jul 25 04:53:00 PM PDT 24
Finished Jul 25 04:53:01 PM PDT 24
Peak memory 182764 kb
Host smart-8d83018e-2ec2-4149-a19e-cf77607368ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674188100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.2674188100
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.1945141060
Short name T551
Test name
Test status
Simulation time 13660726 ps
CPU time 0.65 seconds
Started Jul 25 04:53:02 PM PDT 24
Finished Jul 25 04:53:03 PM PDT 24
Peak memory 192332 kb
Host smart-19f8e1f2-5d27-41a8-9cf2-a95343b7d1be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945141060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.1945141060
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1136128407
Short name T566
Test name
Test status
Simulation time 85350483 ps
CPU time 1.59 seconds
Started Jul 25 04:52:59 PM PDT 24
Finished Jul 25 04:53:01 PM PDT 24
Peak memory 197640 kb
Host smart-3c4d7a5c-71d2-49b1-b25b-d27ec5b5fa72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136128407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.1136128407
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1423053827
Short name T558
Test name
Test status
Simulation time 193873194 ps
CPU time 1.37 seconds
Started Jul 25 04:52:55 PM PDT 24
Finished Jul 25 04:52:57 PM PDT 24
Peak memory 195140 kb
Host smart-0d883ff9-fced-446f-b8a2-da0307ac9ee9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423053827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.1423053827
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.473849831
Short name T466
Test name
Test status
Simulation time 32241604 ps
CPU time 1.22 seconds
Started Jul 25 04:52:54 PM PDT 24
Finished Jul 25 04:52:55 PM PDT 24
Peak memory 197632 kb
Host smart-ec1825f4-af4c-4775-b85e-3b09c7ec26b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473849831 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.473849831
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.1648746875
Short name T77
Test name
Test status
Simulation time 18498460 ps
CPU time 0.6 seconds
Started Jul 25 04:52:55 PM PDT 24
Finished Jul 25 04:52:56 PM PDT 24
Peak memory 182900 kb
Host smart-711631d7-c177-4705-a45b-ed8b475ef122
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648746875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.1648746875
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.1612690478
Short name T520
Test name
Test status
Simulation time 41248379 ps
CPU time 0.52 seconds
Started Jul 25 04:52:46 PM PDT 24
Finished Jul 25 04:52:46 PM PDT 24
Peak memory 182876 kb
Host smart-f224eb0c-af5f-4c47-9135-c24623ca9ae2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612690478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.1612690478
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.1422882483
Short name T538
Test name
Test status
Simulation time 35755349 ps
CPU time 1.5 seconds
Started Jul 25 04:52:51 PM PDT 24
Finished Jul 25 04:52:53 PM PDT 24
Peak memory 197704 kb
Host smart-6d466a72-f182-46e7-9dad-4b1e0651b5d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422882483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.1422882483
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.3489732582
Short name T507
Test name
Test status
Simulation time 1741391181 ps
CPU time 1.32 seconds
Started Jul 25 04:52:51 PM PDT 24
Finished Jul 25 04:52:53 PM PDT 24
Peak memory 194484 kb
Host smart-22794a1e-8927-44b2-a6f2-ff15e744875d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489732582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.3489732582
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.2425967991
Short name T482
Test name
Test status
Simulation time 78971907 ps
CPU time 0.69 seconds
Started Jul 25 04:52:58 PM PDT 24
Finished Jul 25 04:52:59 PM PDT 24
Peak memory 195620 kb
Host smart-6bed5dbf-fd9c-464a-930f-c61dee69c0ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425967991 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.2425967991
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.555652341
Short name T519
Test name
Test status
Simulation time 30846314 ps
CPU time 0.58 seconds
Started Jul 25 04:52:55 PM PDT 24
Finished Jul 25 04:53:01 PM PDT 24
Peak memory 182932 kb
Host smart-1d65afd9-375d-478a-bb32-8ff977efbe10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555652341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.555652341
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.2102677767
Short name T560
Test name
Test status
Simulation time 121947946 ps
CPU time 0.53 seconds
Started Jul 25 04:52:53 PM PDT 24
Finished Jul 25 04:52:54 PM PDT 24
Peak memory 182812 kb
Host smart-0f9246ec-33a2-49d6-bfe9-5b05492eb77f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102677767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.2102677767
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.535635908
Short name T91
Test name
Test status
Simulation time 45635010 ps
CPU time 0.58 seconds
Started Jul 25 04:52:57 PM PDT 24
Finished Jul 25 04:52:58 PM PDT 24
Peak memory 192200 kb
Host smart-6cb28576-38f4-4a6d-976f-368fda7fb405
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535635908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_ti
mer_same_csr_outstanding.535635908
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.2395503150
Short name T575
Test name
Test status
Simulation time 131553346 ps
CPU time 1.35 seconds
Started Jul 25 04:52:52 PM PDT 24
Finished Jul 25 04:52:53 PM PDT 24
Peak memory 197740 kb
Host smart-01b79ec4-eca3-488c-8351-546ed61a5633
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395503150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.2395503150
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.2395787219
Short name T523
Test name
Test status
Simulation time 51649712 ps
CPU time 0.79 seconds
Started Jul 25 04:52:53 PM PDT 24
Finished Jul 25 04:52:54 PM PDT 24
Peak memory 193960 kb
Host smart-5ec93bd7-5c9c-41cd-8dc5-92524fbb244b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395787219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.2395787219
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.976370442
Short name T528
Test name
Test status
Simulation time 94940137 ps
CPU time 0.62 seconds
Started Jul 25 04:52:53 PM PDT 24
Finished Jul 25 04:52:54 PM PDT 24
Peak memory 194672 kb
Host smart-ae9c552a-d909-4b2f-94c2-9fd79828b782
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976370442 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.976370442
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.1279471218
Short name T489
Test name
Test status
Simulation time 124329824 ps
CPU time 0.51 seconds
Started Jul 25 04:53:00 PM PDT 24
Finished Jul 25 04:53:01 PM PDT 24
Peak memory 182740 kb
Host smart-5241ecb7-e1c9-431d-b407-a3bc1a2a86ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279471218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.1279471218
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.3342479406
Short name T470
Test name
Test status
Simulation time 13075707 ps
CPU time 0.56 seconds
Started Jul 25 04:52:54 PM PDT 24
Finished Jul 25 04:52:55 PM PDT 24
Peak memory 182912 kb
Host smart-e2a2c3f8-697e-44f5-a9de-f9f93bebb9ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342479406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.3342479406
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.2889338224
Short name T549
Test name
Test status
Simulation time 61274912 ps
CPU time 0.75 seconds
Started Jul 25 04:52:59 PM PDT 24
Finished Jul 25 04:53:00 PM PDT 24
Peak memory 193544 kb
Host smart-5d82e703-b0aa-4b7f-a320-3b7130ad8054
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889338224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.2889338224
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.2038330308
Short name T548
Test name
Test status
Simulation time 27098134 ps
CPU time 1.23 seconds
Started Jul 25 04:52:51 PM PDT 24
Finished Jul 25 04:52:53 PM PDT 24
Peak memory 197700 kb
Host smart-03bdd8c9-84e9-4699-8984-53abc69bdc8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038330308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.2038330308
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.3762039902
Short name T102
Test name
Test status
Simulation time 455117426 ps
CPU time 1.27 seconds
Started Jul 25 04:52:51 PM PDT 24
Finished Jul 25 04:52:55 PM PDT 24
Peak memory 183456 kb
Host smart-a9bf8992-ed61-415a-bd05-6c4783ccba61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762039902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.3762039902
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.1120754580
Short name T455
Test name
Test status
Simulation time 49659490 ps
CPU time 1 seconds
Started Jul 25 04:52:51 PM PDT 24
Finished Jul 25 04:52:52 PM PDT 24
Peak memory 197624 kb
Host smart-aa0fb7ed-d257-4bd5-8643-c999af60f462
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120754580 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.1120754580
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.1884695419
Short name T85
Test name
Test status
Simulation time 63449265 ps
CPU time 0.57 seconds
Started Jul 25 04:53:03 PM PDT 24
Finished Jul 25 04:53:04 PM PDT 24
Peak memory 182940 kb
Host smart-dc1816a4-2d02-49c4-93ea-7d769c83a445
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884695419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.1884695419
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.3822192603
Short name T475
Test name
Test status
Simulation time 54790803 ps
CPU time 0.57 seconds
Started Jul 25 04:52:59 PM PDT 24
Finished Jul 25 04:53:00 PM PDT 24
Peak memory 182852 kb
Host smart-68c4a5d8-9549-405b-ad66-7728525a0a2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822192603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.3822192603
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.3636586301
Short name T89
Test name
Test status
Simulation time 27257512 ps
CPU time 0.7 seconds
Started Jul 25 04:52:54 PM PDT 24
Finished Jul 25 04:52:55 PM PDT 24
Peak memory 193404 kb
Host smart-995abc7a-bc7b-4985-89cb-988ce7bce18f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636586301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.3636586301
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3486206757
Short name T503
Test name
Test status
Simulation time 59590687 ps
CPU time 1.19 seconds
Started Jul 25 04:52:54 PM PDT 24
Finished Jul 25 04:52:55 PM PDT 24
Peak memory 197676 kb
Host smart-3c27d7f1-ec7f-4325-ab09-ccd1498a69b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486206757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.3486206757
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.285852946
Short name T103
Test name
Test status
Simulation time 142739154 ps
CPU time 0.83 seconds
Started Jul 25 04:52:56 PM PDT 24
Finished Jul 25 04:52:57 PM PDT 24
Peak memory 193692 kb
Host smart-7f2e46eb-d4b5-45b3-b145-7a7506224ee7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285852946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_in
tg_err.285852946
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.2677336384
Short name T81
Test name
Test status
Simulation time 12298123 ps
CPU time 0.61 seconds
Started Jul 25 04:52:50 PM PDT 24
Finished Jul 25 04:52:50 PM PDT 24
Peak memory 182960 kb
Host smart-e2a5a32f-f8a3-4807-855b-1a9d07114f7e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677336384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.2677336384
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.2040561252
Short name T499
Test name
Test status
Simulation time 350062509 ps
CPU time 3.28 seconds
Started Jul 25 04:52:50 PM PDT 24
Finished Jul 25 04:52:58 PM PDT 24
Peak memory 194228 kb
Host smart-a166605d-5e66-46e3-a522-6fe834c2e4e7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040561252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.2040561252
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.2909848622
Short name T478
Test name
Test status
Simulation time 34289913 ps
CPU time 0.57 seconds
Started Jul 25 04:52:52 PM PDT 24
Finished Jul 25 04:52:52 PM PDT 24
Peak memory 182984 kb
Host smart-c93bff0a-4380-4aef-b50b-9816fe827b37
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909848622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.2909848622
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3543821618
Short name T515
Test name
Test status
Simulation time 27196623 ps
CPU time 0.83 seconds
Started Jul 25 04:52:49 PM PDT 24
Finished Jul 25 04:52:50 PM PDT 24
Peak memory 197160 kb
Host smart-2f748ca3-bb79-4c7e-a7c2-c27ac46088a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543821618 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.3543821618
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.1348261423
Short name T552
Test name
Test status
Simulation time 12654910 ps
CPU time 0.54 seconds
Started Jul 25 04:52:41 PM PDT 24
Finished Jul 25 04:52:42 PM PDT 24
Peak memory 182688 kb
Host smart-8f45e341-47ad-458c-a081-1e2b5bed7040
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348261423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.1348261423
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.2425814296
Short name T451
Test name
Test status
Simulation time 103029839 ps
CPU time 0.55 seconds
Started Jul 25 04:52:49 PM PDT 24
Finished Jul 25 04:52:50 PM PDT 24
Peak memory 182864 kb
Host smart-83406c67-7a71-4e45-98fc-3dc31793ad7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425814296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.2425814296
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.480668291
Short name T572
Test name
Test status
Simulation time 22956668 ps
CPU time 0.57 seconds
Started Jul 25 04:52:51 PM PDT 24
Finished Jul 25 04:52:52 PM PDT 24
Peak memory 192132 kb
Host smart-935c5e2a-4cb4-4807-9f04-c913f9caf188
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480668291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_tim
er_same_csr_outstanding.480668291
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.4005025405
Short name T449
Test name
Test status
Simulation time 43629984 ps
CPU time 2.06 seconds
Started Jul 25 04:52:38 PM PDT 24
Finished Jul 25 04:52:40 PM PDT 24
Peak memory 197656 kb
Host smart-e9fe3fd5-ea15-4b7c-adf8-04055cd30b24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005025405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.4005025405
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.4143825500
Short name T547
Test name
Test status
Simulation time 192740889 ps
CPU time 0.8 seconds
Started Jul 25 04:52:53 PM PDT 24
Finished Jul 25 04:52:54 PM PDT 24
Peak memory 194000 kb
Host smart-7a8a8e59-0e07-457d-8ec5-6b98b9da81da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143825500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.4143825500
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.281571071
Short name T450
Test name
Test status
Simulation time 38626662 ps
CPU time 0.55 seconds
Started Jul 25 04:52:53 PM PDT 24
Finished Jul 25 04:52:55 PM PDT 24
Peak memory 182836 kb
Host smart-42ff0048-2781-4858-be4e-1f6d8ae6ead8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281571071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.281571071
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.4008496641
Short name T569
Test name
Test status
Simulation time 14679316 ps
CPU time 0.53 seconds
Started Jul 25 04:52:52 PM PDT 24
Finished Jul 25 04:52:52 PM PDT 24
Peak memory 182836 kb
Host smart-364e5ec0-31f6-4227-b4c5-520b1e918a17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008496641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.4008496641
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.1277221781
Short name T504
Test name
Test status
Simulation time 15446909 ps
CPU time 0.54 seconds
Started Jul 25 04:52:52 PM PDT 24
Finished Jul 25 04:52:53 PM PDT 24
Peak memory 182852 kb
Host smart-bd7c3e7d-056e-4760-af91-5c5ab2107db4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277221781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.1277221781
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.2292785594
Short name T562
Test name
Test status
Simulation time 35596053 ps
CPU time 0.6 seconds
Started Jul 25 04:53:05 PM PDT 24
Finished Jul 25 04:53:05 PM PDT 24
Peak memory 182848 kb
Host smart-5e66b778-6cdc-4a17-aa54-90e595fd179c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292785594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.2292785594
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.4207859302
Short name T502
Test name
Test status
Simulation time 34128379 ps
CPU time 0.53 seconds
Started Jul 25 04:52:56 PM PDT 24
Finished Jul 25 04:52:56 PM PDT 24
Peak memory 182856 kb
Host smart-7fac95ab-d2bd-4adc-b29b-e8a71ba71930
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207859302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.4207859302
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.2265158668
Short name T464
Test name
Test status
Simulation time 23752794 ps
CPU time 0.54 seconds
Started Jul 25 04:53:03 PM PDT 24
Finished Jul 25 04:53:04 PM PDT 24
Peak memory 182792 kb
Host smart-4162de18-7f50-4c9e-9b76-c45fd1b761dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265158668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.2265158668
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.530591374
Short name T488
Test name
Test status
Simulation time 15933034 ps
CPU time 0.56 seconds
Started Jul 25 04:52:47 PM PDT 24
Finished Jul 25 04:52:48 PM PDT 24
Peak memory 182820 kb
Host smart-d2ad17f8-8d72-4bcf-84bb-e23a4893f9bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530591374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.530591374
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.3635660573
Short name T524
Test name
Test status
Simulation time 16744091 ps
CPU time 0.59 seconds
Started Jul 25 04:52:53 PM PDT 24
Finished Jul 25 04:52:54 PM PDT 24
Peak memory 182896 kb
Host smart-3e58637e-01eb-481f-b979-ef93b92c2861
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635660573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.3635660573
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.3170817213
Short name T471
Test name
Test status
Simulation time 15187245 ps
CPU time 0.54 seconds
Started Jul 25 04:52:52 PM PDT 24
Finished Jul 25 04:52:54 PM PDT 24
Peak memory 182880 kb
Host smart-40390d2c-2204-49a3-abcd-bf0584e10dc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170817213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.3170817213
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.491035211
Short name T509
Test name
Test status
Simulation time 31620168 ps
CPU time 0.53 seconds
Started Jul 25 04:52:52 PM PDT 24
Finished Jul 25 04:52:57 PM PDT 24
Peak memory 182748 kb
Host smart-3021ac9f-b9a0-4934-9c94-15c171ec67f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491035211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.491035211
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.1625105361
Short name T82
Test name
Test status
Simulation time 48181189 ps
CPU time 0.73 seconds
Started Jul 25 04:52:51 PM PDT 24
Finished Jul 25 04:52:52 PM PDT 24
Peak memory 192768 kb
Host smart-e4db2a78-06f0-4b0e-86f4-0699818f7b62
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625105361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.1625105361
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.997392116
Short name T35
Test name
Test status
Simulation time 414316047 ps
CPU time 3.68 seconds
Started Jul 25 04:52:50 PM PDT 24
Finished Jul 25 04:52:54 PM PDT 24
Peak memory 191264 kb
Host smart-ae90334c-647e-48f4-9bf3-e56f1121f6e3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997392116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_b
ash.997392116
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.1389269283
Short name T521
Test name
Test status
Simulation time 18666975 ps
CPU time 0.55 seconds
Started Jul 25 04:52:47 PM PDT 24
Finished Jul 25 04:52:48 PM PDT 24
Peak memory 182872 kb
Host smart-bcdc3ed3-8fe6-47f4-a866-277c5d12746e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389269283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.1389269283
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.3140567167
Short name T36
Test name
Test status
Simulation time 90655854 ps
CPU time 0.74 seconds
Started Jul 25 04:52:45 PM PDT 24
Finished Jul 25 04:52:46 PM PDT 24
Peak memory 194992 kb
Host smart-8d6085bd-2823-4271-8f19-d0367b35d005
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140567167 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.3140567167
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.3612628723
Short name T543
Test name
Test status
Simulation time 51722795 ps
CPU time 0.57 seconds
Started Jul 25 04:52:46 PM PDT 24
Finished Jul 25 04:52:47 PM PDT 24
Peak memory 192188 kb
Host smart-6be5e02e-6b9a-4899-a152-af48b1e48279
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612628723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.3612628723
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.2344122604
Short name T527
Test name
Test status
Simulation time 25767885 ps
CPU time 0.55 seconds
Started Jul 25 04:53:02 PM PDT 24
Finished Jul 25 04:53:03 PM PDT 24
Peak memory 182776 kb
Host smart-1d7de8c1-9ff9-45f9-8f06-3287dd4a56f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344122604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.2344122604
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.1717256450
Short name T534
Test name
Test status
Simulation time 47468617 ps
CPU time 0.65 seconds
Started Jul 25 04:52:49 PM PDT 24
Finished Jul 25 04:52:50 PM PDT 24
Peak memory 191844 kb
Host smart-cfa64254-c126-4573-8afd-43346c19c0ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717256450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.1717256450
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.2552878783
Short name T477
Test name
Test status
Simulation time 75223547 ps
CPU time 2.55 seconds
Started Jul 25 04:52:45 PM PDT 24
Finished Jul 25 04:52:48 PM PDT 24
Peak memory 197664 kb
Host smart-4796a9a2-674c-4670-9b8f-6c3f0a45780e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552878783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.2552878783
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.610391844
Short name T516
Test name
Test status
Simulation time 103630014 ps
CPU time 1.38 seconds
Started Jul 25 04:52:38 PM PDT 24
Finished Jul 25 04:52:39 PM PDT 24
Peak memory 183440 kb
Host smart-27b392a8-0d9c-4167-bc62-e902512d49ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610391844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_int
g_err.610391844
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.2651685176
Short name T556
Test name
Test status
Simulation time 42963133 ps
CPU time 0.54 seconds
Started Jul 25 04:52:59 PM PDT 24
Finished Jul 25 04:53:00 PM PDT 24
Peak memory 182904 kb
Host smart-d343aa9e-f66a-483f-86a3-43242fcbf3f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651685176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.2651685176
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.1003596669
Short name T483
Test name
Test status
Simulation time 35521615 ps
CPU time 0.58 seconds
Started Jul 25 04:53:01 PM PDT 24
Finished Jul 25 04:53:02 PM PDT 24
Peak memory 182420 kb
Host smart-7eb58cee-a5a6-4475-8a61-1e11fae655ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003596669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.1003596669
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.2505731898
Short name T537
Test name
Test status
Simulation time 42610456 ps
CPU time 0.55 seconds
Started Jul 25 04:53:04 PM PDT 24
Finished Jul 25 04:53:05 PM PDT 24
Peak memory 182448 kb
Host smart-83eea51a-5299-4d99-82ff-565c6f67875d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505731898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.2505731898
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.208643673
Short name T564
Test name
Test status
Simulation time 26923405 ps
CPU time 0.56 seconds
Started Jul 25 04:53:06 PM PDT 24
Finished Jul 25 04:53:07 PM PDT 24
Peak memory 182252 kb
Host smart-3017b6f9-6543-4ead-991b-2eccaee6b7b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208643673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.208643673
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.176643640
Short name T493
Test name
Test status
Simulation time 142947818 ps
CPU time 0.61 seconds
Started Jul 25 04:53:01 PM PDT 24
Finished Jul 25 04:53:02 PM PDT 24
Peak memory 182812 kb
Host smart-b7f4fdb2-2cba-4607-a557-c01c708cacf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176643640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.176643640
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2386007963
Short name T453
Test name
Test status
Simulation time 30829451 ps
CPU time 0.55 seconds
Started Jul 25 04:53:01 PM PDT 24
Finished Jul 25 04:53:02 PM PDT 24
Peak memory 182756 kb
Host smart-4f9c009b-4ce2-44bc-8436-58675b922f86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386007963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.2386007963
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.4171548224
Short name T571
Test name
Test status
Simulation time 16764055 ps
CPU time 0.55 seconds
Started Jul 25 04:52:53 PM PDT 24
Finished Jul 25 04:52:58 PM PDT 24
Peak memory 182828 kb
Host smart-5e5098eb-e228-4765-8143-b092acd01d7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171548224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.4171548224
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.873441022
Short name T498
Test name
Test status
Simulation time 52087977 ps
CPU time 0.57 seconds
Started Jul 25 04:52:54 PM PDT 24
Finished Jul 25 04:52:55 PM PDT 24
Peak memory 182984 kb
Host smart-aa52f88a-4d55-4621-9094-08cbf63875fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873441022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.873441022
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.4143206138
Short name T559
Test name
Test status
Simulation time 30380455 ps
CPU time 0.57 seconds
Started Jul 25 04:52:51 PM PDT 24
Finished Jul 25 04:52:51 PM PDT 24
Peak memory 182760 kb
Host smart-831cb64b-606d-441a-b5fb-b9963299e9e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143206138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.4143206138
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.152709551
Short name T452
Test name
Test status
Simulation time 44552260 ps
CPU time 0.58 seconds
Started Jul 25 04:52:59 PM PDT 24
Finished Jul 25 04:53:00 PM PDT 24
Peak memory 182808 kb
Host smart-3ff5efb1-e554-448c-b0df-de534716d120
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152709551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.152709551
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.820323630
Short name T87
Test name
Test status
Simulation time 89923296 ps
CPU time 0.8 seconds
Started Jul 25 04:52:39 PM PDT 24
Finished Jul 25 04:52:40 PM PDT 24
Peak memory 192768 kb
Host smart-a224ec1c-d299-49f3-b13e-dec374ee9280
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820323630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alias
ing.820323630
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.708832312
Short name T526
Test name
Test status
Simulation time 1131828320 ps
CPU time 3.28 seconds
Started Jul 25 04:52:52 PM PDT 24
Finished Jul 25 04:52:55 PM PDT 24
Peak memory 183064 kb
Host smart-eec510bf-bc7a-4df4-acec-79461083f2aa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708832312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_b
ash.708832312
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.3022067067
Short name T84
Test name
Test status
Simulation time 21029845 ps
CPU time 0.58 seconds
Started Jul 25 04:52:50 PM PDT 24
Finished Jul 25 04:52:50 PM PDT 24
Peak memory 192204 kb
Host smart-d3a3f551-0fa2-4e4a-83bb-8def5e9a7861
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022067067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.3022067067
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.851955432
Short name T34
Test name
Test status
Simulation time 228645506 ps
CPU time 0.72 seconds
Started Jul 25 04:52:50 PM PDT 24
Finished Jul 25 04:52:51 PM PDT 24
Peak memory 196120 kb
Host smart-56270217-b10b-43db-95c9-8509d5bd5ee4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851955432 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.851955432
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.4261513192
Short name T536
Test name
Test status
Simulation time 12390892 ps
CPU time 0.56 seconds
Started Jul 25 04:52:46 PM PDT 24
Finished Jul 25 04:52:46 PM PDT 24
Peak memory 182820 kb
Host smart-8e1d4132-2826-4581-a4a6-f6e7bb1ed512
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261513192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.4261513192
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.1972566236
Short name T459
Test name
Test status
Simulation time 11545047 ps
CPU time 0.54 seconds
Started Jul 25 04:52:54 PM PDT 24
Finished Jul 25 04:52:55 PM PDT 24
Peak memory 182816 kb
Host smart-94e5008a-78e0-44ba-bed8-96297fb07aff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972566236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.1972566236
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.2573367715
Short name T532
Test name
Test status
Simulation time 60340886 ps
CPU time 0.61 seconds
Started Jul 25 04:52:49 PM PDT 24
Finished Jul 25 04:52:50 PM PDT 24
Peak memory 191792 kb
Host smart-e386c0a0-fd18-46c7-9d2b-4dd908830b11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573367715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.2573367715
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1530214076
Short name T544
Test name
Test status
Simulation time 292635009 ps
CPU time 2.52 seconds
Started Jul 25 04:53:04 PM PDT 24
Finished Jul 25 04:53:07 PM PDT 24
Peak memory 197592 kb
Host smart-ce0a601f-4acb-4c08-a68f-08cb749b2b57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530214076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.1530214076
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.3622133807
Short name T533
Test name
Test status
Simulation time 456529644 ps
CPU time 1.34 seconds
Started Jul 25 04:52:53 PM PDT 24
Finished Jul 25 04:52:55 PM PDT 24
Peak memory 195580 kb
Host smart-dd4b38f6-cd2e-4fe0-9d71-ec9956ceff16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622133807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.3622133807
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.4000746981
Short name T457
Test name
Test status
Simulation time 45497541 ps
CPU time 0.54 seconds
Started Jul 25 04:53:29 PM PDT 24
Finished Jul 25 04:53:30 PM PDT 24
Peak memory 182864 kb
Host smart-8a4c2d79-26fb-429e-be69-d44f917a9232
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000746981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.4000746981
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.4196659745
Short name T550
Test name
Test status
Simulation time 16116404 ps
CPU time 0.58 seconds
Started Jul 25 04:53:02 PM PDT 24
Finished Jul 25 04:53:03 PM PDT 24
Peak memory 182788 kb
Host smart-c0aae25a-a535-4218-b214-d6c2970440b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196659745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.4196659745
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.3952195274
Short name T561
Test name
Test status
Simulation time 18910910 ps
CPU time 0.6 seconds
Started Jul 25 04:53:02 PM PDT 24
Finished Jul 25 04:53:03 PM PDT 24
Peak memory 182988 kb
Host smart-b12f740c-e6bc-4106-9bb5-0f6ed15a11c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952195274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.3952195274
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.3996083265
Short name T456
Test name
Test status
Simulation time 31918647 ps
CPU time 0.54 seconds
Started Jul 25 04:53:14 PM PDT 24
Finished Jul 25 04:53:15 PM PDT 24
Peak memory 182840 kb
Host smart-dea95f5e-19e1-4caa-81c5-f7598a4f4f5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996083265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.3996083265
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.375238378
Short name T460
Test name
Test status
Simulation time 13867302 ps
CPU time 0.54 seconds
Started Jul 25 04:52:54 PM PDT 24
Finished Jul 25 04:52:55 PM PDT 24
Peak memory 182716 kb
Host smart-9f93a7c8-6ec6-466e-8c0a-532c37f4c24b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375238378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.375238378
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.3098406360
Short name T500
Test name
Test status
Simulation time 14377616 ps
CPU time 0.52 seconds
Started Jul 25 04:52:59 PM PDT 24
Finished Jul 25 04:52:59 PM PDT 24
Peak memory 182560 kb
Host smart-5f89ff48-f31f-4c7f-a2c3-1f59afff177b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098406360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.3098406360
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.2146402346
Short name T480
Test name
Test status
Simulation time 12762625 ps
CPU time 0.57 seconds
Started Jul 25 04:52:55 PM PDT 24
Finished Jul 25 04:52:56 PM PDT 24
Peak memory 182804 kb
Host smart-24d6e36d-ad7c-431e-a1a7-802559e309f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146402346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.2146402346
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2839351924
Short name T574
Test name
Test status
Simulation time 69300699 ps
CPU time 0.55 seconds
Started Jul 25 04:53:19 PM PDT 24
Finished Jul 25 04:53:20 PM PDT 24
Peak memory 182840 kb
Host smart-95072fc9-f504-427f-9b0e-8c458cad752f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839351924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.2839351924
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.3871749663
Short name T512
Test name
Test status
Simulation time 42926944 ps
CPU time 0.54 seconds
Started Jul 25 04:52:54 PM PDT 24
Finished Jul 25 04:52:55 PM PDT 24
Peak memory 182884 kb
Host smart-b5d63d5a-880f-4b3f-9d06-a2c12e3cd4f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871749663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.3871749663
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.3096431287
Short name T567
Test name
Test status
Simulation time 16713198 ps
CPU time 0.55 seconds
Started Jul 25 04:52:53 PM PDT 24
Finished Jul 25 04:52:53 PM PDT 24
Peak memory 182824 kb
Host smart-45112153-2475-43b5-95ad-f4fa9c70d884
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096431287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.3096431287
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.1414282091
Short name T570
Test name
Test status
Simulation time 153894966 ps
CPU time 1.04 seconds
Started Jul 25 04:52:49 PM PDT 24
Finished Jul 25 04:52:51 PM PDT 24
Peak memory 197544 kb
Host smart-26b96eb1-ea19-4c16-badf-3b5d752962b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414282091 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.1414282091
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.4035996280
Short name T486
Test name
Test status
Simulation time 13804390 ps
CPU time 0.53 seconds
Started Jul 25 04:52:50 PM PDT 24
Finished Jul 25 04:52:51 PM PDT 24
Peak memory 182680 kb
Host smart-3bb9ed19-7834-49c8-acf3-18ded3f57a61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035996280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.4035996280
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.2221184468
Short name T518
Test name
Test status
Simulation time 11816828 ps
CPU time 0.55 seconds
Started Jul 25 04:52:54 PM PDT 24
Finished Jul 25 04:52:55 PM PDT 24
Peak memory 182336 kb
Host smart-afab484d-f1c7-47ca-bfe3-3cecd1caf340
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221184468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.2221184468
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1891182533
Short name T510
Test name
Test status
Simulation time 18283754 ps
CPU time 0.72 seconds
Started Jul 25 04:52:56 PM PDT 24
Finished Jul 25 04:52:57 PM PDT 24
Peak memory 193224 kb
Host smart-00533ef5-b9bc-4dbc-b37a-094939b1d303
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891182533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.1891182533
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.1776633448
Short name T49
Test name
Test status
Simulation time 164743204 ps
CPU time 1.6 seconds
Started Jul 25 04:52:43 PM PDT 24
Finished Jul 25 04:52:45 PM PDT 24
Peak memory 197652 kb
Host smart-8b45f186-1528-48fa-af5f-d3326baed03d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776633448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.1776633448
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.4221790973
Short name T105
Test name
Test status
Simulation time 130613839 ps
CPU time 0.79 seconds
Started Jul 25 04:52:43 PM PDT 24
Finished Jul 25 04:52:44 PM PDT 24
Peak memory 193000 kb
Host smart-f4e57620-cadb-4b38-aab7-dc8ef0919e8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221790973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.4221790973
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.2439342855
Short name T573
Test name
Test status
Simulation time 25345017 ps
CPU time 0.76 seconds
Started Jul 25 04:52:50 PM PDT 24
Finished Jul 25 04:52:51 PM PDT 24
Peak memory 195508 kb
Host smart-8223d2b0-02cd-4fb0-88dc-a65f5ba7fbee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439342855 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.2439342855
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.369380772
Short name T487
Test name
Test status
Simulation time 32611640 ps
CPU time 0.52 seconds
Started Jul 25 04:52:48 PM PDT 24
Finished Jul 25 04:52:48 PM PDT 24
Peak memory 182988 kb
Host smart-67765cdf-78df-4613-a33a-09b5b609b4c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369380772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.369380772
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.2984195298
Short name T485
Test name
Test status
Simulation time 18404052 ps
CPU time 0.57 seconds
Started Jul 25 04:52:45 PM PDT 24
Finished Jul 25 04:52:46 PM PDT 24
Peak memory 182780 kb
Host smart-a7157427-70b2-4660-a474-694d1e667a0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984195298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.2984195298
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.1534434788
Short name T577
Test name
Test status
Simulation time 61182394 ps
CPU time 0.61 seconds
Started Jul 25 04:52:39 PM PDT 24
Finished Jul 25 04:52:40 PM PDT 24
Peak memory 191764 kb
Host smart-2d3e9a95-47b5-4feb-8b33-ee619f8c4ead
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534434788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.1534434788
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.2945338724
Short name T458
Test name
Test status
Simulation time 42874564 ps
CPU time 1 seconds
Started Jul 25 04:52:53 PM PDT 24
Finished Jul 25 04:52:55 PM PDT 24
Peak memory 196300 kb
Host smart-06f4ca1f-ca20-4be4-8924-d274ef2c0f0a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945338724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.2945338724
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.267283473
Short name T501
Test name
Test status
Simulation time 98994990 ps
CPU time 1.35 seconds
Started Jul 25 04:52:56 PM PDT 24
Finished Jul 25 04:52:57 PM PDT 24
Peak memory 183408 kb
Host smart-37d2fdd6-d4c4-4676-a0c2-64b6c16e117e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267283473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_int
g_err.267283473
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.1754795559
Short name T539
Test name
Test status
Simulation time 74637290 ps
CPU time 0.68 seconds
Started Jul 25 04:52:53 PM PDT 24
Finished Jul 25 04:52:54 PM PDT 24
Peak memory 195088 kb
Host smart-371a4c8a-710d-4fd1-b058-8fa53591b9c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754795559 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.1754795559
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.516934024
Short name T88
Test name
Test status
Simulation time 16835195 ps
CPU time 0.55 seconds
Started Jul 25 04:52:45 PM PDT 24
Finished Jul 25 04:52:45 PM PDT 24
Peak memory 183008 kb
Host smart-236182d5-2e28-466d-92ff-1b9908a11cb7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516934024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.516934024
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.642838583
Short name T497
Test name
Test status
Simulation time 16316721 ps
CPU time 0.55 seconds
Started Jul 25 04:52:47 PM PDT 24
Finished Jul 25 04:52:48 PM PDT 24
Peak memory 182768 kb
Host smart-e2603b72-4243-4431-85a3-c58cff547886
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642838583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.642838583
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.2631474347
Short name T92
Test name
Test status
Simulation time 115505465 ps
CPU time 0.79 seconds
Started Jul 25 04:52:51 PM PDT 24
Finished Jul 25 04:52:52 PM PDT 24
Peak memory 191844 kb
Host smart-75827df9-5d89-44bc-b5af-1d7b4185febe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631474347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.2631474347
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.351725235
Short name T484
Test name
Test status
Simulation time 188678685 ps
CPU time 1.79 seconds
Started Jul 25 04:52:46 PM PDT 24
Finished Jul 25 04:52:48 PM PDT 24
Peak memory 197700 kb
Host smart-e032f80e-ff13-4996-8936-e9c3efe32224
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351725235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.351725235
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.272458355
Short name T106
Test name
Test status
Simulation time 140825064 ps
CPU time 0.82 seconds
Started Jul 25 04:52:42 PM PDT 24
Finished Jul 25 04:52:43 PM PDT 24
Peak memory 193604 kb
Host smart-5b3cd38d-3257-4e57-b767-9a7bba246012
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272458355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_int
g_err.272458355
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.2220775655
Short name T468
Test name
Test status
Simulation time 41621393 ps
CPU time 0.93 seconds
Started Jul 25 04:53:02 PM PDT 24
Finished Jul 25 04:53:03 PM PDT 24
Peak memory 197484 kb
Host smart-6155b82c-b8dd-4e64-989b-8cf7e12dd9c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220775655 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.2220775655
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.658205488
Short name T101
Test name
Test status
Simulation time 141690193 ps
CPU time 0.62 seconds
Started Jul 25 04:52:49 PM PDT 24
Finished Jul 25 04:52:50 PM PDT 24
Peak memory 182996 kb
Host smart-73405ae0-5c94-48d5-bac7-f40085f42db3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658205488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.658205488
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.3789330959
Short name T481
Test name
Test status
Simulation time 14356002 ps
CPU time 0.56 seconds
Started Jul 25 04:52:52 PM PDT 24
Finished Jul 25 04:52:52 PM PDT 24
Peak memory 182864 kb
Host smart-f2c59e8e-db1c-4dcd-b34d-60dd29be8493
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789330959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.3789330959
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.437762839
Short name T93
Test name
Test status
Simulation time 24223834 ps
CPU time 0.62 seconds
Started Jul 25 04:52:52 PM PDT 24
Finished Jul 25 04:52:53 PM PDT 24
Peak memory 192416 kb
Host smart-95cd7f02-58c1-4bc3-a894-da148dfd4128
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437762839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_tim
er_same_csr_outstanding.437762839
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3667436115
Short name T472
Test name
Test status
Simulation time 43115268 ps
CPU time 1.16 seconds
Started Jul 25 04:52:41 PM PDT 24
Finished Jul 25 04:52:42 PM PDT 24
Peak memory 197664 kb
Host smart-a256f40c-5844-4753-96db-b8252748516e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667436115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.3667436115
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3894238115
Short name T454
Test name
Test status
Simulation time 110399662 ps
CPU time 1.08 seconds
Started Jul 25 04:52:52 PM PDT 24
Finished Jul 25 04:52:54 PM PDT 24
Peak memory 197732 kb
Host smart-0aeaf9bc-5e4c-4ba6-a37f-349baa08ceb1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894238115 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.3894238115
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.3834338907
Short name T490
Test name
Test status
Simulation time 21001648 ps
CPU time 0.63 seconds
Started Jul 25 04:52:48 PM PDT 24
Finished Jul 25 04:52:49 PM PDT 24
Peak memory 182980 kb
Host smart-63e4fb78-2934-4705-98bc-8789c508f1b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834338907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.3834338907
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.2848797789
Short name T474
Test name
Test status
Simulation time 28534807 ps
CPU time 0.51 seconds
Started Jul 25 04:52:49 PM PDT 24
Finished Jul 25 04:52:49 PM PDT 24
Peak memory 182332 kb
Host smart-1ba01c00-a5a9-4a6a-ae99-79113f87c764
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848797789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.2848797789
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.926284613
Short name T90
Test name
Test status
Simulation time 20912689 ps
CPU time 0.77 seconds
Started Jul 25 04:52:52 PM PDT 24
Finished Jul 25 04:52:53 PM PDT 24
Peak memory 191936 kb
Host smart-19fd51ac-3f66-4557-b571-98b5882ab63a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926284613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_tim
er_same_csr_outstanding.926284613
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.331688734
Short name T473
Test name
Test status
Simulation time 46182895 ps
CPU time 2.1 seconds
Started Jul 25 04:52:56 PM PDT 24
Finished Jul 25 04:52:59 PM PDT 24
Peak memory 197792 kb
Host smart-d6c0662e-48b5-4e05-a993-7e0dcf48b200
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331688734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.331688734
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.1511984943
Short name T22
Test name
Test status
Simulation time 231668634 ps
CPU time 1.29 seconds
Started Jul 25 04:52:51 PM PDT 24
Finished Jul 25 04:52:55 PM PDT 24
Peak memory 195404 kb
Host smart-02477a37-4d2e-43fe-8ddd-497e0628feba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511984943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.1511984943
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.3371017857
Short name T134
Test name
Test status
Simulation time 907734981232 ps
CPU time 448.81 seconds
Started Jul 25 04:53:06 PM PDT 24
Finished Jul 25 05:00:35 PM PDT 24
Peak memory 183468 kb
Host smart-16ac411c-bb69-460d-8fa6-875dddffe091
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371017857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.3371017857
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.514486037
Short name T63
Test name
Test status
Simulation time 113153134393 ps
CPU time 139.57 seconds
Started Jul 25 04:53:06 PM PDT 24
Finished Jul 25 04:55:26 PM PDT 24
Peak memory 183496 kb
Host smart-7ec5d35f-2c84-43d3-b0e5-ae2e036b2e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514486037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.514486037
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.4120169222
Short name T344
Test name
Test status
Simulation time 756174431467 ps
CPU time 358.15 seconds
Started Jul 25 04:52:59 PM PDT 24
Finished Jul 25 04:58:58 PM PDT 24
Peak memory 195236 kb
Host smart-d6a9288f-db53-40a3-8570-d0fbb30d3ad6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120169222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.4120169222
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.3819978057
Short name T448
Test name
Test status
Simulation time 68380552860 ps
CPU time 635.19 seconds
Started Jul 25 04:53:01 PM PDT 24
Finished Jul 25 05:03:36 PM PDT 24
Peak memory 191696 kb
Host smart-079d1372-15da-4c23-b033-47799423e54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819978057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.3819978057
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.494059396
Short name T367
Test name
Test status
Simulation time 158100391941 ps
CPU time 198.41 seconds
Started Jul 25 04:53:19 PM PDT 24
Finished Jul 25 04:56:37 PM PDT 24
Peak memory 183568 kb
Host smart-35031b65-066c-46ea-a10c-093bf0ca9f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494059396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.494059396
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.3534510525
Short name T164
Test name
Test status
Simulation time 116074577995 ps
CPU time 1773.85 seconds
Started Jul 25 04:52:52 PM PDT 24
Finished Jul 25 05:22:28 PM PDT 24
Peak memory 191776 kb
Host smart-9895a483-eaff-4255-9864-2aae7b092345
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534510525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.3534510525
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.2535451809
Short name T417
Test name
Test status
Simulation time 50855135584 ps
CPU time 78.15 seconds
Started Jul 25 04:53:04 PM PDT 24
Finished Jul 25 04:54:22 PM PDT 24
Peak memory 183496 kb
Host smart-1db5a32b-5497-4cab-8f29-9158cc2acf46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535451809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.2535451809
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.3606537730
Short name T13
Test name
Test status
Simulation time 384317661 ps
CPU time 0.81 seconds
Started Jul 25 04:53:05 PM PDT 24
Finished Jul 25 04:53:06 PM PDT 24
Peak memory 213884 kb
Host smart-d61bf6fb-ef2d-43df-9cd6-08e21957ea62
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606537730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.3606537730
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all_with_rand_reset.3901983464
Short name T30
Test name
Test status
Simulation time 23139505908 ps
CPU time 96.73 seconds
Started Jul 25 04:52:53 PM PDT 24
Finished Jul 25 04:54:31 PM PDT 24
Peak memory 198132 kb
Host smart-92b36b65-3267-4b0c-87ff-82bc87e1260c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901983464 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all_with_rand_reset.3901983464
Directory /workspace/1.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.2493544182
Short name T244
Test name
Test status
Simulation time 147234644148 ps
CPU time 75.89 seconds
Started Jul 25 04:53:03 PM PDT 24
Finished Jul 25 04:54:19 PM PDT 24
Peak memory 183552 kb
Host smart-6affdbe5-d5c5-49d5-bfc3-7cf5846fd70c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493544182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.2493544182
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.3586656855
Short name T401
Test name
Test status
Simulation time 91069058665 ps
CPU time 38.64 seconds
Started Jul 25 04:53:13 PM PDT 24
Finished Jul 25 04:53:52 PM PDT 24
Peak memory 183596 kb
Host smart-f744d0a3-e55e-4ec3-a321-8e1996f53f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586656855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.3586656855
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.868347155
Short name T445
Test name
Test status
Simulation time 66243778 ps
CPU time 0.55 seconds
Started Jul 25 04:52:52 PM PDT 24
Finished Jul 25 04:52:53 PM PDT 24
Peak memory 183224 kb
Host smart-57fff272-0fb6-4adb-bbc5-e82783798495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868347155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.868347155
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.3937546184
Short name T399
Test name
Test status
Simulation time 103475726874 ps
CPU time 354.57 seconds
Started Jul 25 04:53:17 PM PDT 24
Finished Jul 25 04:59:12 PM PDT 24
Peak memory 195072 kb
Host smart-01bebc53-4b02-4076-90fd-1e6d98b3a7ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937546184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.3937546184
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/100.rv_timer_random.3507658927
Short name T284
Test name
Test status
Simulation time 31392315410 ps
CPU time 51.19 seconds
Started Jul 25 04:53:57 PM PDT 24
Finished Jul 25 04:54:48 PM PDT 24
Peak memory 183564 kb
Host smart-df2a4f59-5b92-4f36-82b1-3441f16a859a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507658927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.3507658927
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.3287335752
Short name T306
Test name
Test status
Simulation time 356940311456 ps
CPU time 657.76 seconds
Started Jul 25 04:53:57 PM PDT 24
Finished Jul 25 05:04:55 PM PDT 24
Peak memory 191756 kb
Host smart-bdada735-8579-4080-999f-a89d8ee83da8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287335752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.3287335752
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.3354310993
Short name T185
Test name
Test status
Simulation time 99250281872 ps
CPU time 161.77 seconds
Started Jul 25 04:53:48 PM PDT 24
Finished Jul 25 04:56:30 PM PDT 24
Peak memory 191676 kb
Host smart-03f50f23-f54f-4f5f-99b4-6494b6f6fc39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354310993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.3354310993
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.3048889086
Short name T136
Test name
Test status
Simulation time 1157742685188 ps
CPU time 644.82 seconds
Started Jul 25 04:53:53 PM PDT 24
Finished Jul 25 05:04:38 PM PDT 24
Peak memory 194936 kb
Host smart-e7b39d6a-e7dd-4423-901d-ca20973143bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048889086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.3048889086
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.1638566097
Short name T222
Test name
Test status
Simulation time 131884437413 ps
CPU time 339.06 seconds
Started Jul 25 04:53:49 PM PDT 24
Finished Jul 25 04:59:28 PM PDT 24
Peak memory 191700 kb
Host smart-4c89d6a5-0034-45b7-aa41-274a216a59b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638566097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.1638566097
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.2175553011
Short name T237
Test name
Test status
Simulation time 89902369326 ps
CPU time 134.33 seconds
Started Jul 25 04:53:46 PM PDT 24
Finished Jul 25 04:56:00 PM PDT 24
Peak memory 194832 kb
Host smart-b6a10d03-eb5d-434a-a7e7-7b5f8c0b6fa7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175553011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.2175553011
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.2440626069
Short name T233
Test name
Test status
Simulation time 420359922351 ps
CPU time 206 seconds
Started Jul 25 04:53:05 PM PDT 24
Finished Jul 25 04:56:31 PM PDT 24
Peak memory 183568 kb
Host smart-b55933ca-b084-4424-9449-9ee87fd69764
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440626069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.2440626069
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.294832361
Short name T154
Test name
Test status
Simulation time 87616504580 ps
CPU time 199.85 seconds
Started Jul 25 04:53:01 PM PDT 24
Finished Jul 25 04:56:21 PM PDT 24
Peak memory 196084 kb
Host smart-6f5da764-d7e8-4b0d-96fa-082d625e6fc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294832361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all.
294832361
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/110.rv_timer_random.75736829
Short name T304
Test name
Test status
Simulation time 376487245309 ps
CPU time 178.76 seconds
Started Jul 25 04:53:45 PM PDT 24
Finished Jul 25 04:56:44 PM PDT 24
Peak memory 191688 kb
Host smart-810c0a03-41e1-4bc9-9535-ac332f28a3e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75736829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.75736829
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.3794323461
Short name T152
Test name
Test status
Simulation time 5623642786 ps
CPU time 7.67 seconds
Started Jul 25 04:53:48 PM PDT 24
Finished Jul 25 04:53:56 PM PDT 24
Peak memory 183380 kb
Host smart-d6db97e8-ac41-4a87-87e1-4b109d35d96e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794323461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.3794323461
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.2813818817
Short name T192
Test name
Test status
Simulation time 79564470661 ps
CPU time 153.56 seconds
Started Jul 25 04:53:49 PM PDT 24
Finished Jul 25 04:56:23 PM PDT 24
Peak memory 191680 kb
Host smart-9fcd43df-0ec2-4425-b188-7cacdcae3159
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813818817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.2813818817
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.337456205
Short name T324
Test name
Test status
Simulation time 218300679522 ps
CPU time 194.38 seconds
Started Jul 25 04:53:53 PM PDT 24
Finished Jul 25 04:57:08 PM PDT 24
Peak memory 191752 kb
Host smart-e1e68e41-0f3a-492b-aa0e-12d6dc249d5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337456205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.337456205
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.766991002
Short name T117
Test name
Test status
Simulation time 1096923876032 ps
CPU time 538.44 seconds
Started Jul 25 04:53:47 PM PDT 24
Finished Jul 25 05:02:46 PM PDT 24
Peak memory 191784 kb
Host smart-fd6f84d8-5413-4c33-8578-03c8cb2a855f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766991002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.766991002
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.1650823082
Short name T371
Test name
Test status
Simulation time 266855910815 ps
CPU time 95.61 seconds
Started Jul 25 04:53:01 PM PDT 24
Finished Jul 25 04:54:37 PM PDT 24
Peak memory 183496 kb
Host smart-4bcc1eb6-01fb-437d-ac1c-ccb9bd0ca361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650823082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.1650823082
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.330168868
Short name T19
Test name
Test status
Simulation time 435897232454 ps
CPU time 181.56 seconds
Started Jul 25 04:52:59 PM PDT 24
Finished Jul 25 04:56:01 PM PDT 24
Peak memory 191764 kb
Host smart-2dfc89d0-c8ef-4fbd-92b7-cb33f7768c99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330168868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.330168868
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.4210277659
Short name T4
Test name
Test status
Simulation time 944936979 ps
CPU time 1.53 seconds
Started Jul 25 04:53:02 PM PDT 24
Finished Jul 25 04:53:04 PM PDT 24
Peak memory 191676 kb
Host smart-1119a8f4-24ff-41b4-9457-82668f88ebdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210277659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.4210277659
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.1853676201
Short name T55
Test name
Test status
Simulation time 210847586713 ps
CPU time 298.92 seconds
Started Jul 25 04:53:37 PM PDT 24
Finished Jul 25 04:58:36 PM PDT 24
Peak memory 191784 kb
Host smart-c8e57f3d-a525-4c55-90aa-98bb938001d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853676201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.1853676201
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/120.rv_timer_random.1783785969
Short name T314
Test name
Test status
Simulation time 71539643595 ps
CPU time 101.81 seconds
Started Jul 25 04:54:12 PM PDT 24
Finished Jul 25 04:55:54 PM PDT 24
Peak memory 191764 kb
Host smart-5234d9ad-6e2c-4b6a-9d67-19c5fc223903
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783785969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.1783785969
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.4076232865
Short name T343
Test name
Test status
Simulation time 552780945728 ps
CPU time 549.7 seconds
Started Jul 25 04:53:49 PM PDT 24
Finished Jul 25 05:02:59 PM PDT 24
Peak memory 191784 kb
Host smart-62636d86-4d85-40b0-95af-928bd7f33ec9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076232865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.4076232865
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.3817586846
Short name T18
Test name
Test status
Simulation time 628921915287 ps
CPU time 312.56 seconds
Started Jul 25 04:53:47 PM PDT 24
Finished Jul 25 04:59:00 PM PDT 24
Peak memory 191772 kb
Host smart-9ca33d43-4f24-46a1-bb14-0be5c500d056
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817586846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.3817586846
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.4155615446
Short name T146
Test name
Test status
Simulation time 2144480644464 ps
CPU time 889.1 seconds
Started Jul 25 04:53:47 PM PDT 24
Finished Jul 25 05:08:36 PM PDT 24
Peak memory 191764 kb
Host smart-bb6e1dc0-d601-4059-8e3c-28fe4aaf57c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155615446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.4155615446
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.2169895747
Short name T168
Test name
Test status
Simulation time 274880334973 ps
CPU time 139.01 seconds
Started Jul 25 04:53:43 PM PDT 24
Finished Jul 25 04:56:02 PM PDT 24
Peak memory 191672 kb
Host smart-9d43321d-fa3e-4b59-a2aa-02b0b4d5b9b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169895747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.2169895747
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.2773409210
Short name T170
Test name
Test status
Simulation time 123054769935 ps
CPU time 567.94 seconds
Started Jul 25 04:53:45 PM PDT 24
Finished Jul 25 05:03:13 PM PDT 24
Peak memory 191780 kb
Host smart-615335db-31b3-473d-9c9f-f21b3289a03e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773409210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.2773409210
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.4034348749
Short name T266
Test name
Test status
Simulation time 39015246342 ps
CPU time 77.45 seconds
Started Jul 25 04:53:48 PM PDT 24
Finished Jul 25 04:55:06 PM PDT 24
Peak memory 183564 kb
Host smart-e85a305d-0b34-4e88-a518-a3510985db33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034348749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.4034348749
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.1934912591
Short name T44
Test name
Test status
Simulation time 228202001435 ps
CPU time 339.43 seconds
Started Jul 25 04:53:26 PM PDT 24
Finished Jul 25 04:59:06 PM PDT 24
Peak memory 183488 kb
Host smart-1c346458-0161-4f5d-b8e7-c668aa3a236b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934912591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.1934912591
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.2425498791
Short name T374
Test name
Test status
Simulation time 849932384863 ps
CPU time 97.4 seconds
Started Jul 25 04:53:04 PM PDT 24
Finished Jul 25 04:54:42 PM PDT 24
Peak memory 183564 kb
Host smart-cdf76dee-ac2d-4d90-9cc9-ad00819963c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425498791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.2425498791
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.3703469279
Short name T204
Test name
Test status
Simulation time 111640983271 ps
CPU time 191 seconds
Started Jul 25 04:53:06 PM PDT 24
Finished Jul 25 04:56:17 PM PDT 24
Peak memory 191688 kb
Host smart-af941b1f-79ac-4486-8460-2d4f867c6f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703469279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.3703469279
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.3277953101
Short name T54
Test name
Test status
Simulation time 186816803976 ps
CPU time 287.83 seconds
Started Jul 25 04:53:03 PM PDT 24
Finished Jul 25 04:57:51 PM PDT 24
Peak memory 191692 kb
Host smart-f10d5018-612f-46f4-8f90-fa83673b21de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277953101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.3277953101
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all_with_rand_reset.3112176125
Short name T29
Test name
Test status
Simulation time 75564536855 ps
CPU time 632.01 seconds
Started Jul 25 04:53:05 PM PDT 24
Finished Jul 25 05:03:37 PM PDT 24
Peak memory 206560 kb
Host smart-feb2c22e-e163-44de-b3e7-4d5aaf50d4c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112176125 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all_with_rand_reset.3112176125
Directory /workspace/13.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/131.rv_timer_random.3347618686
Short name T323
Test name
Test status
Simulation time 932538382850 ps
CPU time 267 seconds
Started Jul 25 04:53:44 PM PDT 24
Finished Jul 25 04:58:11 PM PDT 24
Peak memory 191848 kb
Host smart-d25d460a-363d-4f4b-9929-ecff05ec3930
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347618686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.3347618686
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.2412910035
Short name T17
Test name
Test status
Simulation time 34438496294 ps
CPU time 807.81 seconds
Started Jul 25 04:53:50 PM PDT 24
Finished Jul 25 05:07:18 PM PDT 24
Peak memory 191712 kb
Host smart-b129a0d1-784b-4924-8044-ec4f4fd8527d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412910035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.2412910035
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.3758820633
Short name T234
Test name
Test status
Simulation time 299952992393 ps
CPU time 276.22 seconds
Started Jul 25 04:53:46 PM PDT 24
Finished Jul 25 04:58:23 PM PDT 24
Peak memory 193888 kb
Host smart-30a1924e-a138-4830-8a67-aaee8b4dd18f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758820633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.3758820633
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.985369204
Short name T346
Test name
Test status
Simulation time 362598952747 ps
CPU time 313.14 seconds
Started Jul 25 04:53:51 PM PDT 24
Finished Jul 25 04:59:05 PM PDT 24
Peak memory 191756 kb
Host smart-3eeda6be-936a-4b57-8470-8e4df0f99d10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985369204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.985369204
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.2180491173
Short name T429
Test name
Test status
Simulation time 152650495044 ps
CPU time 55.58 seconds
Started Jul 25 04:53:05 PM PDT 24
Finished Jul 25 04:54:01 PM PDT 24
Peak memory 183568 kb
Host smart-ba4caab9-cdeb-4489-8801-1add143547f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180491173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.2180491173
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.2159861045
Short name T227
Test name
Test status
Simulation time 243526986955 ps
CPU time 233.27 seconds
Started Jul 25 04:53:06 PM PDT 24
Finished Jul 25 04:57:04 PM PDT 24
Peak memory 191764 kb
Host smart-df3d36ad-752b-4685-afa4-2cdf9752320a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159861045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.2159861045
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.4096804750
Short name T318
Test name
Test status
Simulation time 60612342089 ps
CPU time 90.18 seconds
Started Jul 25 04:52:55 PM PDT 24
Finished Jul 25 04:54:26 PM PDT 24
Peak memory 191772 kb
Host smart-07a62e1c-8b3d-4230-b590-76a3dc06767d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096804750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.4096804750
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/140.rv_timer_random.634106945
Short name T131
Test name
Test status
Simulation time 636849541309 ps
CPU time 986.39 seconds
Started Jul 25 04:53:52 PM PDT 24
Finished Jul 25 05:10:19 PM PDT 24
Peak memory 191680 kb
Host smart-d8b0aab5-3c62-4076-8f3b-4b2fb514914d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634106945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.634106945
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.981573841
Short name T160
Test name
Test status
Simulation time 133021486931 ps
CPU time 1754.06 seconds
Started Jul 25 04:53:53 PM PDT 24
Finished Jul 25 05:23:07 PM PDT 24
Peak memory 191680 kb
Host smart-cfba886b-194e-46a9-a5f6-39241183bb50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981573841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.981573841
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.591028311
Short name T161
Test name
Test status
Simulation time 1023761666267 ps
CPU time 3033.61 seconds
Started Jul 25 04:53:43 PM PDT 24
Finished Jul 25 05:44:17 PM PDT 24
Peak memory 191796 kb
Host smart-95cfc407-351b-45df-b2a6-4837f592f9e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591028311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.591028311
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.341498658
Short name T208
Test name
Test status
Simulation time 78003960241 ps
CPU time 223.25 seconds
Started Jul 25 04:53:56 PM PDT 24
Finished Jul 25 04:57:39 PM PDT 24
Peak memory 191756 kb
Host smart-8a2dfa7a-f041-49de-aeda-fe1eba7c33fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341498658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.341498658
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.1718447671
Short name T424
Test name
Test status
Simulation time 43983473740 ps
CPU time 68.74 seconds
Started Jul 25 04:53:52 PM PDT 24
Finished Jul 25 04:55:01 PM PDT 24
Peak memory 191744 kb
Host smart-e51b0253-6e52-43eb-abd7-80235bc1f756
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718447671 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.1718447671
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.1259095342
Short name T327
Test name
Test status
Simulation time 194230250343 ps
CPU time 358.93 seconds
Started Jul 25 04:53:52 PM PDT 24
Finished Jul 25 04:59:52 PM PDT 24
Peak memory 191756 kb
Host smart-2ad822b0-18e5-45d3-a32f-734426e40f11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259095342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.1259095342
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.703208551
Short name T180
Test name
Test status
Simulation time 44789727296 ps
CPU time 553.83 seconds
Started Jul 25 04:53:46 PM PDT 24
Finished Jul 25 05:03:00 PM PDT 24
Peak memory 183580 kb
Host smart-dcda3163-8ece-4cd8-bf65-6615abf17fa4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703208551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.703208551
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.1945707395
Short name T277
Test name
Test status
Simulation time 1702423475069 ps
CPU time 910.99 seconds
Started Jul 25 04:53:13 PM PDT 24
Finished Jul 25 05:08:24 PM PDT 24
Peak memory 183484 kb
Host smart-5b96a301-848a-453e-b404-390fd717c7c9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945707395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.1945707395
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.1454189421
Short name T412
Test name
Test status
Simulation time 164756692079 ps
CPU time 115.16 seconds
Started Jul 25 04:53:03 PM PDT 24
Finished Jul 25 04:54:59 PM PDT 24
Peak memory 183572 kb
Host smart-4d094393-3c83-467f-853f-042e51efcb63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454189421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.1454189421
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.2979781000
Short name T444
Test name
Test status
Simulation time 705687190300 ps
CPU time 641.98 seconds
Started Jul 25 04:52:56 PM PDT 24
Finished Jul 25 05:03:38 PM PDT 24
Peak memory 191792 kb
Host smart-1e013c2a-0e75-4bd6-b28b-27a837937ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979781000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.2979781000
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.608936849
Short name T255
Test name
Test status
Simulation time 279967221680 ps
CPU time 371.29 seconds
Started Jul 25 04:52:55 PM PDT 24
Finished Jul 25 04:59:07 PM PDT 24
Peak memory 191760 kb
Host smart-2cfbf6f3-bbc8-4807-8c2c-0642a9c11435
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608936849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all.
608936849
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/150.rv_timer_random.4018679224
Short name T69
Test name
Test status
Simulation time 107804398565 ps
CPU time 823.34 seconds
Started Jul 25 04:53:44 PM PDT 24
Finished Jul 25 05:07:28 PM PDT 24
Peak memory 191672 kb
Host smart-fbc6cb29-fe84-4f43-a815-7ff80348f5d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018679224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.4018679224
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.4018588912
Short name T315
Test name
Test status
Simulation time 410473327582 ps
CPU time 676.78 seconds
Started Jul 25 04:53:46 PM PDT 24
Finished Jul 25 05:05:03 PM PDT 24
Peak memory 193520 kb
Host smart-30515689-e1b4-4551-8d79-2a60010841e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018588912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.4018588912
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.1653160186
Short name T228
Test name
Test status
Simulation time 48121549542 ps
CPU time 77.45 seconds
Started Jul 25 04:53:47 PM PDT 24
Finished Jul 25 04:55:05 PM PDT 24
Peak memory 183472 kb
Host smart-4c377dfc-9a99-4d7c-97c7-e8f31900e688
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653160186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.1653160186
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.2298018911
Short name T409
Test name
Test status
Simulation time 122431555317 ps
CPU time 373.69 seconds
Started Jul 25 04:53:44 PM PDT 24
Finished Jul 25 04:59:58 PM PDT 24
Peak memory 191776 kb
Host smart-9c70c508-698d-4206-a24f-14f04e1d6a13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298018911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.2298018911
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.774289957
Short name T231
Test name
Test status
Simulation time 339024128268 ps
CPU time 93.21 seconds
Started Jul 25 04:53:53 PM PDT 24
Finished Jul 25 04:55:27 PM PDT 24
Peak memory 191704 kb
Host smart-7bf77fb1-1769-447e-9bc4-653df5e81e9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774289957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.774289957
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.641256651
Short name T307
Test name
Test status
Simulation time 115641784622 ps
CPU time 42.31 seconds
Started Jul 25 04:53:55 PM PDT 24
Finished Jul 25 04:54:37 PM PDT 24
Peak memory 191744 kb
Host smart-96434a5e-7800-47c6-aa5a-80cc87f526c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641256651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.641256651
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.2604485128
Short name T406
Test name
Test status
Simulation time 435094569309 ps
CPU time 117.7 seconds
Started Jul 25 04:53:09 PM PDT 24
Finished Jul 25 04:55:06 PM PDT 24
Peak memory 183572 kb
Host smart-ba55f29f-f6f4-4fe4-87aa-7cea5e56611f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604485128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.2604485128
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.897859621
Short name T425
Test name
Test status
Simulation time 133601989106 ps
CPU time 68.73 seconds
Started Jul 25 04:52:58 PM PDT 24
Finished Jul 25 04:54:07 PM PDT 24
Peak memory 195016 kb
Host smart-b0adfd7f-ae50-47a6-9195-a7047b8e89c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897859621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.897859621
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.2753387041
Short name T58
Test name
Test status
Simulation time 112972518964 ps
CPU time 250.15 seconds
Started Jul 25 04:53:08 PM PDT 24
Finished Jul 25 04:57:18 PM PDT 24
Peak memory 195344 kb
Host smart-8d3b4f21-c0e2-4bc9-8f28-ed999f852d54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753387041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.2753387041
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/161.rv_timer_random.3616730573
Short name T330
Test name
Test status
Simulation time 440118438083 ps
CPU time 303.27 seconds
Started Jul 25 04:53:55 PM PDT 24
Finished Jul 25 04:58:59 PM PDT 24
Peak memory 191764 kb
Host smart-ed012caf-7977-450f-9d66-0eba77a62dae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616730573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.3616730573
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.2684045243
Short name T127
Test name
Test status
Simulation time 86155366906 ps
CPU time 83.22 seconds
Started Jul 25 04:53:46 PM PDT 24
Finished Jul 25 04:55:10 PM PDT 24
Peak memory 191696 kb
Host smart-8c7e6901-3bc9-4a25-bace-5ab7154a5ede
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684045243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.2684045243
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.3632523124
Short name T420
Test name
Test status
Simulation time 29311368647 ps
CPU time 5.19 seconds
Started Jul 25 04:53:58 PM PDT 24
Finished Jul 25 04:54:03 PM PDT 24
Peak memory 183564 kb
Host smart-a013d934-51eb-4f29-abe6-943c9bf97e91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632523124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.3632523124
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.798349227
Short name T348
Test name
Test status
Simulation time 29417625829 ps
CPU time 48.55 seconds
Started Jul 25 04:53:54 PM PDT 24
Finished Jul 25 04:54:43 PM PDT 24
Peak memory 183564 kb
Host smart-5ca9bc77-a06e-42e0-9bbd-42b41b84861b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798349227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.798349227
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.832985549
Short name T109
Test name
Test status
Simulation time 106201042017 ps
CPU time 423.86 seconds
Started Jul 25 04:53:49 PM PDT 24
Finished Jul 25 05:00:53 PM PDT 24
Peak memory 191692 kb
Host smart-b8417301-2c90-4454-acb1-83ea3c187582
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832985549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.832985549
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.3486142180
Short name T333
Test name
Test status
Simulation time 43746832078 ps
CPU time 61.72 seconds
Started Jul 25 04:53:50 PM PDT 24
Finished Jul 25 04:54:51 PM PDT 24
Peak memory 191716 kb
Host smart-0a89d575-7e99-461e-9c33-61ac417f6df7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486142180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.3486142180
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.3577567678
Short name T397
Test name
Test status
Simulation time 812949579557 ps
CPU time 316.96 seconds
Started Jul 25 04:53:03 PM PDT 24
Finished Jul 25 04:58:25 PM PDT 24
Peak memory 183580 kb
Host smart-d678f30b-9ad7-4064-9bdd-38b5dbed088b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577567678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.3577567678
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.2939764951
Short name T416
Test name
Test status
Simulation time 661721176700 ps
CPU time 124.28 seconds
Started Jul 25 04:53:14 PM PDT 24
Finished Jul 25 04:55:18 PM PDT 24
Peak memory 195188 kb
Host smart-03778db4-f274-40bd-9787-7a4918e5f747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939764951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.2939764951
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.3723197206
Short name T250
Test name
Test status
Simulation time 117450122393 ps
CPU time 173.98 seconds
Started Jul 25 04:53:53 PM PDT 24
Finished Jul 25 04:56:47 PM PDT 24
Peak memory 191700 kb
Host smart-64757f76-0dbc-4adf-b9a1-76dd683808f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723197206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.3723197206
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.869946955
Short name T162
Test name
Test status
Simulation time 170218475875 ps
CPU time 285.21 seconds
Started Jul 25 04:53:56 PM PDT 24
Finished Jul 25 04:58:42 PM PDT 24
Peak memory 191740 kb
Host smart-51dc1edd-8bd9-4726-9da6-2484f250e861
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869946955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.869946955
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.4205024849
Short name T335
Test name
Test status
Simulation time 66990639058 ps
CPU time 18.2 seconds
Started Jul 25 04:53:52 PM PDT 24
Finished Jul 25 04:54:10 PM PDT 24
Peak memory 183396 kb
Host smart-e182f3f4-2be6-47df-a547-cc662d6f3e1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205024849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.4205024849
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.3614178103
Short name T260
Test name
Test status
Simulation time 192161193761 ps
CPU time 242.53 seconds
Started Jul 25 04:53:53 PM PDT 24
Finished Jul 25 04:57:55 PM PDT 24
Peak memory 195252 kb
Host smart-cdfec5d3-23e9-4782-a119-6445e6d74915
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614178103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.3614178103
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.132156920
Short name T264
Test name
Test status
Simulation time 347108955640 ps
CPU time 235.19 seconds
Started Jul 25 04:53:55 PM PDT 24
Finished Jul 25 04:57:51 PM PDT 24
Peak memory 191664 kb
Host smart-c0bca15c-fbb0-4b66-ab9a-f796374e1805
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132156920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.132156920
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.1213191699
Short name T201
Test name
Test status
Simulation time 144053515064 ps
CPU time 137.02 seconds
Started Jul 25 04:53:46 PM PDT 24
Finished Jul 25 04:56:03 PM PDT 24
Peak memory 191756 kb
Host smart-38495d72-5171-4557-912e-6336995297b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213191699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.1213191699
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.4234609159
Short name T42
Test name
Test status
Simulation time 46455276926 ps
CPU time 72.26 seconds
Started Jul 25 04:53:55 PM PDT 24
Finished Jul 25 04:55:08 PM PDT 24
Peak memory 191668 kb
Host smart-05f3d429-e87d-4432-a6f2-c71c96fd4154
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234609159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.4234609159
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.280900340
Short name T319
Test name
Test status
Simulation time 5279355161 ps
CPU time 9.31 seconds
Started Jul 25 04:53:47 PM PDT 24
Finished Jul 25 04:53:56 PM PDT 24
Peak memory 183508 kb
Host smart-51c7a383-bf0b-4f1c-b80f-ee74c0093821
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280900340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.280900340
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.3393767982
Short name T70
Test name
Test status
Simulation time 462127454783 ps
CPU time 609.72 seconds
Started Jul 25 04:53:53 PM PDT 24
Finished Jul 25 05:04:03 PM PDT 24
Peak memory 195104 kb
Host smart-16d273e5-2b6d-4002-8da2-2bfb9d075c3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393767982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.3393767982
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.1383364208
Short name T430
Test name
Test status
Simulation time 318281807612 ps
CPU time 325.8 seconds
Started Jul 25 04:53:47 PM PDT 24
Finished Jul 25 04:59:13 PM PDT 24
Peak memory 191776 kb
Host smart-3eff4230-2cca-4e14-93e5-1fd8859ad987
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383364208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.1383364208
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.2023246458
Short name T363
Test name
Test status
Simulation time 106623663260 ps
CPU time 138.75 seconds
Started Jul 25 04:53:06 PM PDT 24
Finished Jul 25 04:55:25 PM PDT 24
Peak memory 183576 kb
Host smart-cec911f2-d524-4109-86b5-2b111ba4704a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023246458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.2023246458
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.2710999307
Short name T138
Test name
Test status
Simulation time 156791674916 ps
CPU time 248.51 seconds
Started Jul 25 04:53:25 PM PDT 24
Finished Jul 25 04:57:34 PM PDT 24
Peak memory 191640 kb
Host smart-43ffb952-f15e-49c5-a44d-1354d007cb63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710999307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.2710999307
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.634814907
Short name T354
Test name
Test status
Simulation time 282230105677 ps
CPU time 205.21 seconds
Started Jul 25 04:53:29 PM PDT 24
Finished Jul 25 04:56:55 PM PDT 24
Peak memory 183576 kb
Host smart-9b3c489f-4909-47cf-9333-b63f46c704c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634814907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.634814907
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.4250072709
Short name T368
Test name
Test status
Simulation time 261571452550 ps
CPU time 154.81 seconds
Started Jul 25 04:53:05 PM PDT 24
Finished Jul 25 04:55:40 PM PDT 24
Peak memory 183564 kb
Host smart-4d89262f-1596-43d6-a853-e9b15a61a2aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250072709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.4250072709
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.838484121
Short name T31
Test name
Test status
Simulation time 44596199669 ps
CPU time 170.43 seconds
Started Jul 25 04:53:10 PM PDT 24
Finished Jul 25 04:56:01 PM PDT 24
Peak memory 206504 kb
Host smart-a61378b7-0439-48f3-bb16-9a4ed92fcc52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838484121 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all_with_rand_reset.838484121
Directory /workspace/18.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.rv_timer_random.2830096161
Short name T329
Test name
Test status
Simulation time 75904523263 ps
CPU time 130.1 seconds
Started Jul 25 04:53:52 PM PDT 24
Finished Jul 25 04:56:02 PM PDT 24
Peak memory 191692 kb
Host smart-79c83725-9733-41a6-a94a-f95a26986056
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830096161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.2830096161
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.1703503242
Short name T256
Test name
Test status
Simulation time 694099756482 ps
CPU time 217.84 seconds
Started Jul 25 04:53:52 PM PDT 24
Finished Jul 25 04:57:30 PM PDT 24
Peak memory 191732 kb
Host smart-4874ae09-b1c0-402c-a600-4d7baf7c9693
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703503242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.1703503242
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.3339215172
Short name T142
Test name
Test status
Simulation time 48095083619 ps
CPU time 372.47 seconds
Started Jul 25 04:53:55 PM PDT 24
Finished Jul 25 05:00:07 PM PDT 24
Peak memory 183524 kb
Host smart-2122061e-9793-42c8-a076-9495a43d6a7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339215172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.3339215172
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.2614737488
Short name T213
Test name
Test status
Simulation time 181230600020 ps
CPU time 145.64 seconds
Started Jul 25 04:53:49 PM PDT 24
Finished Jul 25 04:56:15 PM PDT 24
Peak memory 191712 kb
Host smart-a7db50a0-f0d6-494f-8294-29d7f9f8d5a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614737488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.2614737488
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.3720064851
Short name T211
Test name
Test status
Simulation time 85814062135 ps
CPU time 125.94 seconds
Started Jul 25 04:53:55 PM PDT 24
Finished Jul 25 04:56:02 PM PDT 24
Peak memory 191704 kb
Host smart-921b8508-7621-45ae-8c86-def7d22fe7f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720064851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.3720064851
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.1841257543
Short name T219
Test name
Test status
Simulation time 510758002993 ps
CPU time 170.42 seconds
Started Jul 25 04:53:52 PM PDT 24
Finished Jul 25 04:56:43 PM PDT 24
Peak memory 191652 kb
Host smart-bf0b81d3-50d3-4449-adb6-008a34964a88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841257543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.1841257543
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.3503027720
Short name T447
Test name
Test status
Simulation time 171240541100 ps
CPU time 93.84 seconds
Started Jul 25 04:53:49 PM PDT 24
Finished Jul 25 04:55:23 PM PDT 24
Peak memory 183484 kb
Host smart-d6316b47-f53f-4e44-80b8-42a1adf54d73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503027720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.3503027720
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.142454063
Short name T242
Test name
Test status
Simulation time 11917587252 ps
CPU time 32.84 seconds
Started Jul 25 04:53:54 PM PDT 24
Finished Jul 25 04:54:27 PM PDT 24
Peak memory 183560 kb
Host smart-7d507095-be41-44f0-b020-6642921597bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142454063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.142454063
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.820635836
Short name T312
Test name
Test status
Simulation time 717239403378 ps
CPU time 646.31 seconds
Started Jul 25 04:53:13 PM PDT 24
Finished Jul 25 05:04:00 PM PDT 24
Peak memory 183480 kb
Host smart-78a44180-3058-4d98-ae49-27df5ffcb151
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820635836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.rv_timer_cfg_update_on_fly.820635836
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.3466273624
Short name T385
Test name
Test status
Simulation time 71431915880 ps
CPU time 91.98 seconds
Started Jul 25 04:53:10 PM PDT 24
Finished Jul 25 04:54:42 PM PDT 24
Peak memory 183588 kb
Host smart-c6e48058-5c3f-499d-ba07-e030c7cd6a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466273624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.3466273624
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.1314970209
Short name T220
Test name
Test status
Simulation time 46718962943 ps
CPU time 66.49 seconds
Started Jul 25 04:53:24 PM PDT 24
Finished Jul 25 04:54:30 PM PDT 24
Peak memory 191640 kb
Host smart-481eccc9-34c0-4a56-9c47-1f64ad20a156
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314970209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.1314970209
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.2095961031
Short name T230
Test name
Test status
Simulation time 31881020261 ps
CPU time 44.69 seconds
Started Jul 25 04:53:07 PM PDT 24
Finished Jul 25 04:53:52 PM PDT 24
Peak memory 195028 kb
Host smart-12513e4c-f0a9-4641-9761-421760974da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095961031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.2095961031
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/192.rv_timer_random.3163056579
Short name T122
Test name
Test status
Simulation time 136144759681 ps
CPU time 412.11 seconds
Started Jul 25 04:53:55 PM PDT 24
Finished Jul 25 05:00:48 PM PDT 24
Peak memory 191688 kb
Host smart-bc039b27-fd5b-44e8-a76b-4032e3e4b55f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163056579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.3163056579
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.3053031676
Short name T115
Test name
Test status
Simulation time 1370707517992 ps
CPU time 728.15 seconds
Started Jul 25 04:53:54 PM PDT 24
Finished Jul 25 05:06:02 PM PDT 24
Peak memory 191772 kb
Host smart-fdf53dab-9234-4b0a-8c45-6106471c9ad7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053031676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.3053031676
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.1548658712
Short name T325
Test name
Test status
Simulation time 140477827776 ps
CPU time 70.72 seconds
Started Jul 25 04:53:58 PM PDT 24
Finished Jul 25 04:55:09 PM PDT 24
Peak memory 183492 kb
Host smart-bd09a7a8-3e32-4f5d-b630-48856f741ec0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548658712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.1548658712
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.2844907236
Short name T128
Test name
Test status
Simulation time 76678982818 ps
CPU time 136.6 seconds
Started Jul 25 04:53:59 PM PDT 24
Finished Jul 25 04:56:16 PM PDT 24
Peak memory 191756 kb
Host smart-c443c0b1-d7bf-476c-986d-8dbfc6187eb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844907236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.2844907236
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.1984097107
Short name T410
Test name
Test status
Simulation time 22245951838 ps
CPU time 207.42 seconds
Started Jul 25 04:53:59 PM PDT 24
Finished Jul 25 04:57:26 PM PDT 24
Peak memory 183536 kb
Host smart-19900dac-54b9-4f05-97e6-03ecff3f1009
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984097107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.1984097107
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.846817423
Short name T280
Test name
Test status
Simulation time 21772594102 ps
CPU time 30.33 seconds
Started Jul 25 04:53:57 PM PDT 24
Finished Jul 25 04:54:28 PM PDT 24
Peak memory 183568 kb
Host smart-b28f72dd-a95a-4220-bcfe-7aaf2340172f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846817423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.846817423
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.2702320347
Short name T224
Test name
Test status
Simulation time 226833872203 ps
CPU time 345.02 seconds
Started Jul 25 04:52:56 PM PDT 24
Finished Jul 25 04:58:41 PM PDT 24
Peak memory 183496 kb
Host smart-41caa7e5-8aaf-41cb-921e-4b84545f66d6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702320347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.2702320347
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.2756935605
Short name T376
Test name
Test status
Simulation time 13408292885 ps
CPU time 16.5 seconds
Started Jul 25 04:52:56 PM PDT 24
Finished Jul 25 04:53:12 PM PDT 24
Peak memory 183576 kb
Host smart-c2cea46c-fabf-40e3-b331-0148cc2a7c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756935605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.2756935605
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.2900379730
Short name T125
Test name
Test status
Simulation time 470251109744 ps
CPU time 224.32 seconds
Started Jul 25 04:52:50 PM PDT 24
Finished Jul 25 04:56:35 PM PDT 24
Peak memory 191788 kb
Host smart-d0fd2b43-2fe3-4fa9-95c4-18e28008659d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900379730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.2900379730
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.623607730
Short name T353
Test name
Test status
Simulation time 86318277106 ps
CPU time 142.84 seconds
Started Jul 25 04:53:16 PM PDT 24
Finished Jul 25 04:55:39 PM PDT 24
Peak memory 183432 kb
Host smart-dd87d341-5ccf-46c2-97f3-a67afc8c5bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623607730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.623607730
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.2124418441
Short name T6
Test name
Test status
Simulation time 166152985 ps
CPU time 0.9 seconds
Started Jul 25 04:52:54 PM PDT 24
Finished Jul 25 04:52:55 PM PDT 24
Peak memory 214880 kb
Host smart-1993312b-21a3-4653-b249-fbe82612e9ac
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124418441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.2124418441
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.4063833756
Short name T365
Test name
Test status
Simulation time 262162309852 ps
CPU time 78.06 seconds
Started Jul 25 04:53:01 PM PDT 24
Finished Jul 25 04:54:20 PM PDT 24
Peak memory 183476 kb
Host smart-38f69315-0fa3-43a6-bb2b-537839f94094
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063833756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
4063833756
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.3909855923
Short name T20
Test name
Test status
Simulation time 79434192229 ps
CPU time 126.3 seconds
Started Jul 25 04:53:05 PM PDT 24
Finished Jul 25 04:55:12 PM PDT 24
Peak memory 183536 kb
Host smart-c04a457d-1ec4-4f1f-a9cd-baa7deb53eab
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909855923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.3909855923
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.3879431213
Short name T375
Test name
Test status
Simulation time 145824338660 ps
CPU time 113.22 seconds
Started Jul 25 04:52:57 PM PDT 24
Finished Jul 25 04:54:50 PM PDT 24
Peak memory 183584 kb
Host smart-663e94c7-2358-4bfa-9d34-c58c8621c6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879431213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.3879431213
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.3150568909
Short name T111
Test name
Test status
Simulation time 345287320333 ps
CPU time 181.28 seconds
Started Jul 25 04:53:25 PM PDT 24
Finished Jul 25 04:56:26 PM PDT 24
Peak memory 191800 kb
Host smart-090a2cf4-a7d7-4853-bf37-c06ea4cb0642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150568909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.3150568909
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.3638925037
Short name T407
Test name
Test status
Simulation time 382510787390 ps
CPU time 153.58 seconds
Started Jul 25 04:53:09 PM PDT 24
Finished Jul 25 04:55:42 PM PDT 24
Peak memory 183568 kb
Host smart-2fbccc98-7349-490f-a834-c007444af662
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638925037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.3638925037
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all_with_rand_reset.8544473
Short name T33
Test name
Test status
Simulation time 62992761971 ps
CPU time 472.27 seconds
Started Jul 25 04:53:20 PM PDT 24
Finished Jul 25 05:01:12 PM PDT 24
Peak memory 206440 kb
Host smart-b3f11895-8bd7-4086-8b2f-09e315acb63b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8544473 -assert nopost
proc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all_with_rand_reset.8544473
Directory /workspace/20.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.1382233539
Short name T158
Test name
Test status
Simulation time 320018298120 ps
CPU time 176.26 seconds
Started Jul 25 04:53:24 PM PDT 24
Finished Jul 25 04:56:20 PM PDT 24
Peak memory 183484 kb
Host smart-cae58732-de47-4323-9e38-33b919af7e56
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382233539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.1382233539
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.764568235
Short name T61
Test name
Test status
Simulation time 161022798245 ps
CPU time 222.37 seconds
Started Jul 25 04:53:20 PM PDT 24
Finished Jul 25 04:57:08 PM PDT 24
Peak memory 183572 kb
Host smart-548f40dc-f3e4-492d-9c62-d21451114dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764568235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.764568235
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.3961227444
Short name T351
Test name
Test status
Simulation time 1977646698 ps
CPU time 3.47 seconds
Started Jul 25 04:53:10 PM PDT 24
Finished Jul 25 04:53:13 PM PDT 24
Peak memory 183232 kb
Host smart-8eb1ec87-da49-4810-a7ac-11eb8ee51691
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961227444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.3961227444
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.3060565909
Short name T369
Test name
Test status
Simulation time 126280823 ps
CPU time 0.73 seconds
Started Jul 25 04:53:12 PM PDT 24
Finished Jul 25 04:53:13 PM PDT 24
Peak memory 183272 kb
Host smart-81bfaeaf-e194-4258-8dfe-b240abe91d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060565909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.3060565909
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.3778353956
Short name T246
Test name
Test status
Simulation time 4369547808759 ps
CPU time 1510.51 seconds
Started Jul 25 04:53:12 PM PDT 24
Finished Jul 25 05:18:23 PM PDT 24
Peak memory 183560 kb
Host smart-ee74d4f6-433e-46dd-91cf-e6bed472e506
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778353956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.3778353956
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.1887936452
Short name T372
Test name
Test status
Simulation time 83042317780 ps
CPU time 62.81 seconds
Started Jul 25 04:53:42 PM PDT 24
Finished Jul 25 04:54:45 PM PDT 24
Peak memory 183472 kb
Host smart-fb9accce-7f83-4353-b436-90699ad69073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887936452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.1887936452
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.797145577
Short name T442
Test name
Test status
Simulation time 99361639864 ps
CPU time 173.83 seconds
Started Jul 25 04:53:03 PM PDT 24
Finished Jul 25 04:55:57 PM PDT 24
Peak memory 191772 kb
Host smart-0a6a4d4e-3b98-4f56-bd6c-68851a3057cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797145577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.797145577
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.4154044434
Short name T336
Test name
Test status
Simulation time 654503165077 ps
CPU time 354.17 seconds
Started Jul 25 04:53:26 PM PDT 24
Finished Jul 25 04:59:21 PM PDT 24
Peak memory 191788 kb
Host smart-1621b09c-6b2a-4951-b277-63f44db737b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154044434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.4154044434
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.2421668673
Short name T41
Test name
Test status
Simulation time 1126130760485 ps
CPU time 506.76 seconds
Started Jul 25 04:53:13 PM PDT 24
Finished Jul 25 05:01:40 PM PDT 24
Peak memory 183508 kb
Host smart-e70b2975-c01d-4fe0-ab28-97317ce446de
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421668673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.2421668673
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.4191132640
Short name T361
Test name
Test status
Simulation time 41868781935 ps
CPU time 55.89 seconds
Started Jul 25 04:53:23 PM PDT 24
Finished Jul 25 04:54:19 PM PDT 24
Peak memory 183504 kb
Host smart-b783f3cf-ed71-4221-963b-ff4d9df2bc85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191132640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.4191132640
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.1901385866
Short name T116
Test name
Test status
Simulation time 611244814113 ps
CPU time 75.77 seconds
Started Jul 25 04:53:21 PM PDT 24
Finished Jul 25 04:54:37 PM PDT 24
Peak memory 183580 kb
Host smart-d2cedbe1-94b7-49f5-ac83-68dbe5f3f062
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901385866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.1901385866
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.2885011054
Short name T358
Test name
Test status
Simulation time 12486902485 ps
CPU time 6.9 seconds
Started Jul 25 04:53:13 PM PDT 24
Finished Jul 25 04:53:20 PM PDT 24
Peak memory 193696 kb
Host smart-c1d36701-1462-44b0-a212-d8a6ba14742e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885011054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.2885011054
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.2554872838
Short name T32
Test name
Test status
Simulation time 70527261572 ps
CPU time 526.72 seconds
Started Jul 25 04:53:32 PM PDT 24
Finished Jul 25 05:02:19 PM PDT 24
Peak memory 198188 kb
Host smart-c4bf9208-b1f2-40c3-9fb0-f147811dfc41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554872838 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_reset.2554872838
Directory /workspace/23.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.4200617557
Short name T3
Test name
Test status
Simulation time 545739813111 ps
CPU time 210.54 seconds
Started Jul 25 04:53:37 PM PDT 24
Finished Jul 25 04:57:08 PM PDT 24
Peak memory 183544 kb
Host smart-b8c60aba-f167-490b-8bfc-86baf092c98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200617557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.4200617557
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.1554610665
Short name T305
Test name
Test status
Simulation time 278198013291 ps
CPU time 299.8 seconds
Started Jul 25 04:53:31 PM PDT 24
Finished Jul 25 04:58:31 PM PDT 24
Peak memory 191668 kb
Host smart-bae74480-80a6-4b0d-848d-ad5b5e05a76c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554610665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.1554610665
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.2096450368
Short name T248
Test name
Test status
Simulation time 104894224660 ps
CPU time 37.6 seconds
Started Jul 25 04:53:12 PM PDT 24
Finished Jul 25 04:53:50 PM PDT 24
Peak memory 191760 kb
Host smart-3aedbf1e-f969-4996-b286-dc297e23e309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096450368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.2096450368
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.2282494674
Short name T226
Test name
Test status
Simulation time 200089128348 ps
CPU time 287.81 seconds
Started Jul 25 04:53:26 PM PDT 24
Finished Jul 25 04:58:14 PM PDT 24
Peak memory 183540 kb
Host smart-31fccc99-1488-489f-9df5-545b2e2851e5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282494674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.2282494674
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.3209638677
Short name T396
Test name
Test status
Simulation time 65970843458 ps
CPU time 97.37 seconds
Started Jul 25 04:53:26 PM PDT 24
Finished Jul 25 04:55:03 PM PDT 24
Peak memory 183568 kb
Host smart-f7f7989b-0eb6-4a46-99ec-08cefcf7e48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209638677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.3209638677
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.862645200
Short name T261
Test name
Test status
Simulation time 76969966433 ps
CPU time 27.98 seconds
Started Jul 25 04:53:33 PM PDT 24
Finished Jul 25 04:54:01 PM PDT 24
Peak memory 183388 kb
Host smart-c74b975d-d0cc-4571-84f3-5a2587c92d5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862645200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.862645200
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.4255911516
Short name T66
Test name
Test status
Simulation time 30996684866 ps
CPU time 48.88 seconds
Started Jul 25 04:53:25 PM PDT 24
Finished Jul 25 04:54:14 PM PDT 24
Peak memory 183496 kb
Host smart-7877e199-d074-42f2-b5dd-1582f58c0e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255911516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.4255911516
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.2432287083
Short name T217
Test name
Test status
Simulation time 1692002665165 ps
CPU time 785.89 seconds
Started Jul 25 04:53:16 PM PDT 24
Finished Jul 25 05:06:27 PM PDT 24
Peak memory 183564 kb
Host smart-7f5cc704-6aee-4cd5-923f-c4c309b5ee81
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432287083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.2432287083
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.2996992794
Short name T379
Test name
Test status
Simulation time 30686544628 ps
CPU time 45.31 seconds
Started Jul 25 04:53:12 PM PDT 24
Finished Jul 25 04:53:57 PM PDT 24
Peak memory 183476 kb
Host smart-3702b200-afbf-4c1a-ba7a-03035383dc24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996992794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.2996992794
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.1942912865
Short name T279
Test name
Test status
Simulation time 30416244658 ps
CPU time 241.9 seconds
Started Jul 25 04:53:34 PM PDT 24
Finished Jul 25 04:57:36 PM PDT 24
Peak memory 183600 kb
Host smart-d7e90755-dea4-41b6-904f-ede9103740c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942912865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.1942912865
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.2034597538
Short name T402
Test name
Test status
Simulation time 315829364 ps
CPU time 0.67 seconds
Started Jul 25 04:53:36 PM PDT 24
Finished Jul 25 04:53:37 PM PDT 24
Peak memory 191968 kb
Host smart-3b4e7a69-f305-436a-88c8-4f4e7343d9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034597538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.2034597538
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.1584807997
Short name T400
Test name
Test status
Simulation time 643846307953 ps
CPU time 563.77 seconds
Started Jul 25 04:53:31 PM PDT 24
Finished Jul 25 05:02:55 PM PDT 24
Peak memory 191760 kb
Host smart-ac247dff-cc5d-474a-9ee5-a2175fe15a4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584807997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.1584807997
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.1884573392
Short name T274
Test name
Test status
Simulation time 1251784345522 ps
CPU time 528.97 seconds
Started Jul 25 04:53:31 PM PDT 24
Finished Jul 25 05:02:20 PM PDT 24
Peak memory 183564 kb
Host smart-0b244210-9b27-4c79-afd2-7a9662feb8ce
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884573392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.1884573392
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.1109955177
Short name T377
Test name
Test status
Simulation time 77856005941 ps
CPU time 101.15 seconds
Started Jul 25 04:53:30 PM PDT 24
Finished Jul 25 04:55:11 PM PDT 24
Peak memory 183584 kb
Host smart-1624418c-314a-4e04-aa64-5ed293fc13f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109955177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.1109955177
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.2846582923
Short name T65
Test name
Test status
Simulation time 117708129956 ps
CPU time 194.86 seconds
Started Jul 25 04:53:11 PM PDT 24
Finished Jul 25 04:56:26 PM PDT 24
Peak memory 193348 kb
Host smart-2e483097-8e5f-4dc4-b844-d52cbd1585b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846582923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.2846582923
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.443314335
Short name T434
Test name
Test status
Simulation time 217637297054 ps
CPU time 1190.94 seconds
Started Jul 25 04:53:36 PM PDT 24
Finished Jul 25 05:13:27 PM PDT 24
Peak memory 191720 kb
Host smart-225012c2-f377-4b8c-8535-fb2b2c22d17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443314335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.443314335
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.4197660107
Short name T178
Test name
Test status
Simulation time 145423065690 ps
CPU time 98.93 seconds
Started Jul 25 04:53:22 PM PDT 24
Finished Jul 25 04:55:01 PM PDT 24
Peak memory 183564 kb
Host smart-270eee4d-6602-4410-bd8c-74c5b5d3ab9f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197660107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.4197660107
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.2948696324
Short name T398
Test name
Test status
Simulation time 111864548070 ps
CPU time 160.41 seconds
Started Jul 25 04:53:21 PM PDT 24
Finished Jul 25 04:56:01 PM PDT 24
Peak memory 183648 kb
Host smart-e975b5fe-5110-4ec2-9219-163fcd78bc32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948696324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.2948696324
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.2668176297
Short name T210
Test name
Test status
Simulation time 573987563310 ps
CPU time 1099.04 seconds
Started Jul 25 04:53:21 PM PDT 24
Finished Jul 25 05:11:40 PM PDT 24
Peak memory 191704 kb
Host smart-69f1bc4f-57e4-4553-8bce-848dc020a010
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668176297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.2668176297
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.2653770374
Short name T309
Test name
Test status
Simulation time 16387495901 ps
CPU time 24 seconds
Started Jul 25 04:53:28 PM PDT 24
Finished Jul 25 04:53:52 PM PDT 24
Peak memory 191708 kb
Host smart-e4f20528-6e8b-46dd-a009-ce6d7c86a382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653770374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.2653770374
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.2846534098
Short name T332
Test name
Test status
Simulation time 476512582579 ps
CPU time 390.31 seconds
Started Jul 25 04:53:47 PM PDT 24
Finished Jul 25 05:00:18 PM PDT 24
Peak memory 183572 kb
Host smart-0e2c4d9e-f297-4924-9cf2-e68cc94613b9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846534098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.2846534098
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.4058023820
Short name T394
Test name
Test status
Simulation time 91383274900 ps
CPU time 130.94 seconds
Started Jul 25 04:53:29 PM PDT 24
Finished Jul 25 04:55:40 PM PDT 24
Peak memory 183572 kb
Host smart-5e7ce214-972d-473c-8041-338a3606c0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058023820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.4058023820
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.4125479319
Short name T64
Test name
Test status
Simulation time 80291875622 ps
CPU time 68.47 seconds
Started Jul 25 04:53:38 PM PDT 24
Finished Jul 25 04:54:47 PM PDT 24
Peak memory 191728 kb
Host smart-e95c0066-6b60-4e3a-9a7a-2306cd9cd4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125479319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.4125479319
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all_with_rand_reset.1938696145
Short name T27
Test name
Test status
Simulation time 153186062773 ps
CPU time 397.78 seconds
Started Jul 25 04:53:34 PM PDT 24
Finished Jul 25 05:00:12 PM PDT 24
Peak memory 198244 kb
Host smart-b910a725-f280-4a6a-a6a1-c55897b0047d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938696145 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all_with_rand_reset.1938696145
Directory /workspace/29.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.3018161684
Short name T268
Test name
Test status
Simulation time 617926680071 ps
CPU time 459.21 seconds
Started Jul 25 04:52:57 PM PDT 24
Finished Jul 25 05:00:36 PM PDT 24
Peak memory 183448 kb
Host smart-b16621e5-fcf9-40a2-bdfa-3778d4d086f8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018161684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.3018161684
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.3628824356
Short name T393
Test name
Test status
Simulation time 180630966058 ps
CPU time 209.07 seconds
Started Jul 25 04:52:54 PM PDT 24
Finished Jul 25 04:56:24 PM PDT 24
Peak memory 183440 kb
Host smart-09e55c86-f602-439d-8642-2d0687d3646d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628824356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.3628824356
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.1703003106
Short name T413
Test name
Test status
Simulation time 110605226941 ps
CPU time 52.14 seconds
Started Jul 25 04:53:04 PM PDT 24
Finished Jul 25 04:53:56 PM PDT 24
Peak memory 183564 kb
Host smart-81e41966-7fd1-4119-b210-d27acceb2949
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703003106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.1703003106
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.2287868056
Short name T380
Test name
Test status
Simulation time 1548647776 ps
CPU time 1.07 seconds
Started Jul 25 04:53:00 PM PDT 24
Finished Jul 25 04:53:01 PM PDT 24
Peak memory 183260 kb
Host smart-893282ac-6437-4878-b068-d676b708aaf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287868056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.2287868056
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.3275126834
Short name T15
Test name
Test status
Simulation time 204216742 ps
CPU time 0.88 seconds
Started Jul 25 04:53:00 PM PDT 24
Finished Jul 25 04:53:01 PM PDT 24
Peak memory 214468 kb
Host smart-6b5a0903-67f6-4b1f-8a09-6ab3b1be8a67
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275126834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.3275126834
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.2656274019
Short name T313
Test name
Test status
Simulation time 690498130897 ps
CPU time 346.18 seconds
Started Jul 25 04:53:36 PM PDT 24
Finished Jul 25 04:59:22 PM PDT 24
Peak memory 183556 kb
Host smart-925ff86c-bec3-459e-9792-80ba3e72f37c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656274019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.2656274019
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.4037700573
Short name T366
Test name
Test status
Simulation time 136369787834 ps
CPU time 175.84 seconds
Started Jul 25 04:53:36 PM PDT 24
Finished Jul 25 04:56:32 PM PDT 24
Peak memory 183572 kb
Host smart-77420dab-b216-477e-8199-91eeed71f6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037700573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.4037700573
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.2395491179
Short name T341
Test name
Test status
Simulation time 127516589563 ps
CPU time 566.68 seconds
Started Jul 25 04:53:33 PM PDT 24
Finished Jul 25 05:03:00 PM PDT 24
Peak memory 194832 kb
Host smart-3bf4d6cb-1a3b-4ba3-aaf5-049d2158bde2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395491179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.2395491179
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.1158118794
Short name T188
Test name
Test status
Simulation time 81775645753 ps
CPU time 159.38 seconds
Started Jul 25 04:53:36 PM PDT 24
Finished Jul 25 04:56:16 PM PDT 24
Peak memory 191740 kb
Host smart-254aaf0c-11a5-4e33-8230-8e39bfaa0768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158118794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.1158118794
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.912410018
Short name T52
Test name
Test status
Simulation time 37392777 ps
CPU time 0.59 seconds
Started Jul 25 04:53:32 PM PDT 24
Finished Jul 25 04:53:33 PM PDT 24
Peak memory 183328 kb
Host smart-43b9cde6-e362-4426-a549-2104e90d0bca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912410018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all.
912410018
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.2215292303
Short name T431
Test name
Test status
Simulation time 224293713021 ps
CPU time 77.22 seconds
Started Jul 25 04:53:18 PM PDT 24
Finished Jul 25 04:54:35 PM PDT 24
Peak memory 183560 kb
Host smart-c7b548c9-f99c-4ca4-abfa-577a667f2e46
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215292303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.2215292303
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.1765281618
Short name T383
Test name
Test status
Simulation time 113445076323 ps
CPU time 146.01 seconds
Started Jul 25 04:53:33 PM PDT 24
Finished Jul 25 04:55:59 PM PDT 24
Peak memory 183600 kb
Host smart-1ca053ab-8db5-4d31-933b-11eba5bd3765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765281618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.1765281618
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.3054818223
Short name T418
Test name
Test status
Simulation time 145589791658 ps
CPU time 67.39 seconds
Started Jul 25 04:53:43 PM PDT 24
Finished Jul 25 04:54:51 PM PDT 24
Peak memory 183504 kb
Host smart-4fdb4634-dc22-4670-8812-ea72af52d367
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054818223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.3054818223
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.3799743815
Short name T283
Test name
Test status
Simulation time 254982964005 ps
CPU time 141.38 seconds
Started Jul 25 04:53:33 PM PDT 24
Finished Jul 25 04:55:55 PM PDT 24
Peak memory 195460 kb
Host smart-59985e5a-5968-4959-b38d-e967ddcc7736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799743815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.3799743815
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.1419040528
Short name T296
Test name
Test status
Simulation time 21358525567 ps
CPU time 33.21 seconds
Started Jul 25 04:53:38 PM PDT 24
Finished Jul 25 04:54:11 PM PDT 24
Peak memory 183568 kb
Host smart-f26b2a34-e2f7-441b-bffa-517622f780f6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419040528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.1419040528
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.769470336
Short name T403
Test name
Test status
Simulation time 956258641261 ps
CPU time 154.91 seconds
Started Jul 25 04:53:32 PM PDT 24
Finished Jul 25 04:56:07 PM PDT 24
Peak memory 183568 kb
Host smart-2796064e-23ad-4084-bab6-8bd243c46eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769470336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.769470336
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.2841359939
Short name T388
Test name
Test status
Simulation time 21842031177 ps
CPU time 35.47 seconds
Started Jul 25 04:53:27 PM PDT 24
Finished Jul 25 04:54:03 PM PDT 24
Peak memory 183488 kb
Host smart-abb8e716-d574-4de8-8a5d-fdf6f5eca30d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841359939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.2841359939
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.4246357452
Short name T414
Test name
Test status
Simulation time 28205615 ps
CPU time 0.56 seconds
Started Jul 25 04:53:45 PM PDT 24
Finished Jul 25 04:53:46 PM PDT 24
Peak memory 183228 kb
Host smart-6b7e91e7-4387-4ba8-bdc4-a0827f936115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246357452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.4246357452
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.3303567019
Short name T21
Test name
Test status
Simulation time 453427969819 ps
CPU time 195.08 seconds
Started Jul 25 04:53:21 PM PDT 24
Finished Jul 25 04:56:36 PM PDT 24
Peak memory 183420 kb
Host smart-6304b798-e002-479d-bd7a-77a2a77d11dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303567019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.3303567019
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.3520322802
Short name T150
Test name
Test status
Simulation time 130817642638 ps
CPU time 129.2 seconds
Started Jul 25 04:53:36 PM PDT 24
Finished Jul 25 04:55:46 PM PDT 24
Peak memory 183568 kb
Host smart-dc134bda-881f-4c32-ba44-efa752e6e23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520322802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.3520322802
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.2709279754
Short name T288
Test name
Test status
Simulation time 17571060696 ps
CPU time 28.68 seconds
Started Jul 25 04:53:39 PM PDT 24
Finished Jul 25 04:54:08 PM PDT 24
Peak memory 183488 kb
Host smart-bd64aee9-a6b0-4d1d-8661-0746fb1af978
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709279754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.2709279754
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.3981602907
Short name T356
Test name
Test status
Simulation time 198090067112 ps
CPU time 73.7 seconds
Started Jul 25 04:53:40 PM PDT 24
Finished Jul 25 04:54:53 PM PDT 24
Peak memory 183548 kb
Host smart-9b0f7aec-c23a-40e6-aba5-6e25b59fb779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981602907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.3981602907
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.1427337947
Short name T326
Test name
Test status
Simulation time 66555541162 ps
CPU time 52.33 seconds
Started Jul 25 04:53:41 PM PDT 24
Finished Jul 25 04:54:33 PM PDT 24
Peak memory 183556 kb
Host smart-2711607f-5d3b-4d3e-bf29-37fbc90982c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427337947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.1427337947
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.81999921
Short name T381
Test name
Test status
Simulation time 8919146192 ps
CPU time 5.74 seconds
Started Jul 25 04:53:30 PM PDT 24
Finished Jul 25 04:53:35 PM PDT 24
Peak memory 191776 kb
Host smart-286f8cb5-f98c-4c32-bff2-539e16db2a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81999921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.81999921
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.2422852572
Short name T51
Test name
Test status
Simulation time 101428481023 ps
CPU time 86.44 seconds
Started Jul 25 04:53:39 PM PDT 24
Finished Jul 25 04:55:05 PM PDT 24
Peak memory 191784 kb
Host smart-5078379a-34ce-42f8-8b94-779926a91bfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422852572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.2422852572
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.611668013
Short name T7
Test name
Test status
Simulation time 758179279392 ps
CPU time 657.74 seconds
Started Jul 25 04:53:28 PM PDT 24
Finished Jul 25 05:04:26 PM PDT 24
Peak memory 183564 kb
Host smart-9559194a-86f8-4622-89a4-405b9a1fe1c6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611668013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.rv_timer_cfg_update_on_fly.611668013
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.3136207705
Short name T438
Test name
Test status
Simulation time 813761070853 ps
CPU time 180.28 seconds
Started Jul 25 04:53:29 PM PDT 24
Finished Jul 25 04:56:29 PM PDT 24
Peak memory 183556 kb
Host smart-9bc6dea7-5305-42d3-a27f-d3d5790c4480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136207705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.3136207705
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.3554391211
Short name T342
Test name
Test status
Simulation time 146932126138 ps
CPU time 250.78 seconds
Started Jul 25 04:53:38 PM PDT 24
Finished Jul 25 04:57:49 PM PDT 24
Peak memory 191796 kb
Host smart-46cd38ce-adfa-46e3-bb4d-76f8b4c12402
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554391211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.3554391211
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.1529762173
Short name T391
Test name
Test status
Simulation time 267262748191 ps
CPU time 182.78 seconds
Started Jul 25 04:53:24 PM PDT 24
Finished Jul 25 04:56:27 PM PDT 24
Peak memory 183556 kb
Host smart-8e106ca6-b4ce-4e5d-9176-899361f47e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529762173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.1529762173
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.2364887574
Short name T177
Test name
Test status
Simulation time 977506171464 ps
CPU time 773.73 seconds
Started Jul 25 04:53:40 PM PDT 24
Finished Jul 25 05:06:34 PM PDT 24
Peak memory 191756 kb
Host smart-e3ac58c7-156d-4421-8b9f-2c66e340ea0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364887574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.2364887574
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.3259930760
Short name T355
Test name
Test status
Simulation time 92129155624 ps
CPU time 185.06 seconds
Started Jul 25 04:53:39 PM PDT 24
Finished Jul 25 04:56:44 PM PDT 24
Peak memory 195024 kb
Host smart-140e4320-f417-44ca-b863-ba79419ff75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259930760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.3259930760
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.3977885199
Short name T271
Test name
Test status
Simulation time 7127467044853 ps
CPU time 1488.84 seconds
Started Jul 25 04:53:38 PM PDT 24
Finished Jul 25 05:18:27 PM PDT 24
Peak memory 183476 kb
Host smart-01f39df2-1dd1-4ace-9982-5c0bed6c0826
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977885199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.3977885199
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.45407312
Short name T359
Test name
Test status
Simulation time 421986280642 ps
CPU time 155.21 seconds
Started Jul 25 04:53:43 PM PDT 24
Finished Jul 25 04:56:18 PM PDT 24
Peak memory 183480 kb
Host smart-2493d987-5bc4-4957-a21b-c12b9cee9141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45407312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.45407312
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.1905535135
Short name T281
Test name
Test status
Simulation time 366663741530 ps
CPU time 644.93 seconds
Started Jul 25 04:53:43 PM PDT 24
Finished Jul 25 05:04:28 PM PDT 24
Peak memory 191756 kb
Host smart-eab609c3-625a-4a8a-9068-08dd1110746f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905535135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.1905535135
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.2152916187
Short name T337
Test name
Test status
Simulation time 125830793606 ps
CPU time 233.85 seconds
Started Jul 25 04:53:39 PM PDT 24
Finished Jul 25 04:57:33 PM PDT 24
Peak memory 191696 kb
Host smart-1ba10428-5b28-4931-b080-261b22c2ea26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152916187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.2152916187
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.1918091958
Short name T53
Test name
Test status
Simulation time 255542950015 ps
CPU time 109.46 seconds
Started Jul 25 04:53:36 PM PDT 24
Finished Jul 25 04:55:26 PM PDT 24
Peak memory 183536 kb
Host smart-f13785df-7f65-4331-8f63-da728904ce59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918091958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.1918091958
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.2211461620
Short name T352
Test name
Test status
Simulation time 3577023028607 ps
CPU time 976.14 seconds
Started Jul 25 04:53:34 PM PDT 24
Finished Jul 25 05:09:50 PM PDT 24
Peak memory 183532 kb
Host smart-b56ba59a-4b42-46d9-a48e-3fbdb55ebdac
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211461620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.2211461620
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.2226739657
Short name T10
Test name
Test status
Simulation time 84224677136 ps
CPU time 119.4 seconds
Started Jul 25 04:53:41 PM PDT 24
Finished Jul 25 04:55:40 PM PDT 24
Peak memory 183512 kb
Host smart-674dcde9-4bca-4295-b4f4-a3d24715e296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226739657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.2226739657
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.2321033111
Short name T71
Test name
Test status
Simulation time 263586430080 ps
CPU time 140.47 seconds
Started Jul 25 04:53:53 PM PDT 24
Finished Jul 25 04:56:14 PM PDT 24
Peak memory 191752 kb
Host smart-9c63fa5e-fc2c-423b-9993-7f5fd16ece9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321033111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.2321033111
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.3575696317
Short name T235
Test name
Test status
Simulation time 45718749780 ps
CPU time 103.82 seconds
Started Jul 25 04:53:39 PM PDT 24
Finished Jul 25 04:55:23 PM PDT 24
Peak memory 191800 kb
Host smart-592e0ee0-c29a-41d9-9da6-4a9f7a3febfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575696317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.3575696317
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.727723164
Short name T303
Test name
Test status
Simulation time 97641238941 ps
CPU time 258.62 seconds
Started Jul 25 04:53:43 PM PDT 24
Finished Jul 25 04:58:01 PM PDT 24
Peak memory 191776 kb
Host smart-15cc305c-624b-489c-8941-f5c6a86c4680
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727723164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all.
727723164
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.2665475098
Short name T73
Test name
Test status
Simulation time 161060641805 ps
CPU time 274.46 seconds
Started Jul 25 04:53:39 PM PDT 24
Finished Jul 25 04:58:14 PM PDT 24
Peak memory 183552 kb
Host smart-96e59f77-03dc-430b-abdc-06b47e5f1497
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665475098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.2665475098
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.968423612
Short name T387
Test name
Test status
Simulation time 221906263861 ps
CPU time 152.39 seconds
Started Jul 25 04:53:43 PM PDT 24
Finished Jul 25 04:56:15 PM PDT 24
Peak memory 183576 kb
Host smart-7ac83c90-cff4-40c4-96ce-ac953022b93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968423612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.968423612
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.791072552
Short name T272
Test name
Test status
Simulation time 179627668474 ps
CPU time 393.8 seconds
Started Jul 25 04:53:40 PM PDT 24
Finished Jul 25 05:00:14 PM PDT 24
Peak memory 191712 kb
Host smart-c08e6599-83d7-4ae0-a077-8947c44f7e74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791072552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.791072552
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.3214326904
Short name T389
Test name
Test status
Simulation time 251422875 ps
CPU time 0.76 seconds
Started Jul 25 04:53:42 PM PDT 24
Finished Jul 25 04:53:43 PM PDT 24
Peak memory 183364 kb
Host smart-5db7ca16-6503-4b25-945d-4843ddbfeae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214326904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.3214326904
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.82646841
Short name T259
Test name
Test status
Simulation time 500941544828 ps
CPU time 492.7 seconds
Started Jul 25 04:53:43 PM PDT 24
Finished Jul 25 05:01:56 PM PDT 24
Peak memory 194824 kb
Host smart-cd69ff60-4915-4813-a778-e0aecb81d86e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82646841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all.82646841
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.3586166524
Short name T203
Test name
Test status
Simulation time 858821428465 ps
CPU time 430.5 seconds
Started Jul 25 04:53:02 PM PDT 24
Finished Jul 25 05:00:12 PM PDT 24
Peak memory 183544 kb
Host smart-d3d9b514-b36c-4fc4-890b-1bc18e4c982d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586166524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.3586166524
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.2273928550
Short name T441
Test name
Test status
Simulation time 668938307077 ps
CPU time 185.67 seconds
Started Jul 25 04:53:05 PM PDT 24
Finished Jul 25 04:56:10 PM PDT 24
Peak memory 183488 kb
Host smart-7361c0fd-b450-4ecf-baf2-47c451af5dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273928550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.2273928550
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.3801102620
Short name T422
Test name
Test status
Simulation time 70772581833 ps
CPU time 59.38 seconds
Started Jul 25 04:52:55 PM PDT 24
Finished Jul 25 04:53:54 PM PDT 24
Peak memory 183572 kb
Host smart-ef49a288-2ec4-4021-b1a9-22da824035d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801102620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.3801102620
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.1770848231
Short name T183
Test name
Test status
Simulation time 259844347097 ps
CPU time 717.42 seconds
Started Jul 25 04:53:03 PM PDT 24
Finished Jul 25 05:05:00 PM PDT 24
Peak memory 191784 kb
Host smart-6edb2a03-dd70-4d02-a95d-c16ded542214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770848231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.1770848231
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.2528036337
Short name T16
Test name
Test status
Simulation time 61399745 ps
CPU time 0.84 seconds
Started Jul 25 04:53:02 PM PDT 24
Finished Jul 25 04:53:03 PM PDT 24
Peak memory 213780 kb
Host smart-490f4fdd-ed07-45b9-a872-dc1593f580f4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528036337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.2528036337
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.2722270345
Short name T120
Test name
Test status
Simulation time 1104495410072 ps
CPU time 487.02 seconds
Started Jul 25 04:53:02 PM PDT 24
Finished Jul 25 05:01:10 PM PDT 24
Peak memory 191676 kb
Host smart-4d3da880-4112-4a82-a105-27caf73a79fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722270345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
2722270345
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.3148260452
Short name T289
Test name
Test status
Simulation time 584817350034 ps
CPU time 556.3 seconds
Started Jul 25 04:53:45 PM PDT 24
Finished Jul 25 05:03:02 PM PDT 24
Peak memory 183580 kb
Host smart-299097cc-d134-446a-a282-fa235e10c568
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148260452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.3148260452
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.3503301978
Short name T2
Test name
Test status
Simulation time 129769548177 ps
CPU time 187.17 seconds
Started Jul 25 04:53:43 PM PDT 24
Finished Jul 25 04:56:50 PM PDT 24
Peak memory 183576 kb
Host smart-0f11054e-773a-4eaa-b492-01a3fa386eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503301978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.3503301978
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.99416495
Short name T390
Test name
Test status
Simulation time 90512023088 ps
CPU time 81.77 seconds
Started Jul 25 04:53:38 PM PDT 24
Finished Jul 25 04:55:00 PM PDT 24
Peak memory 191784 kb
Host smart-bf7e35aa-9f34-4ea6-94d2-cb8ba6e89edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99416495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.99416495
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.2228775836
Short name T95
Test name
Test status
Simulation time 45267367507 ps
CPU time 57.79 seconds
Started Jul 25 04:53:47 PM PDT 24
Finished Jul 25 04:54:46 PM PDT 24
Peak memory 183572 kb
Host smart-c1e4a12e-13ec-420d-a054-26d21fb7f6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228775836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.2228775836
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.1586985189
Short name T331
Test name
Test status
Simulation time 182695863422 ps
CPU time 217.93 seconds
Started Jul 25 04:53:42 PM PDT 24
Finished Jul 25 04:57:20 PM PDT 24
Peak memory 191788 kb
Host smart-66d4bc20-4063-4ac4-848b-b396a2852b0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586985189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.1586985189
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.3320677636
Short name T435
Test name
Test status
Simulation time 122697094215 ps
CPU time 45.79 seconds
Started Jul 25 04:53:41 PM PDT 24
Finished Jul 25 04:54:27 PM PDT 24
Peak memory 195640 kb
Host smart-bcb8cac5-9b8f-4c75-830b-42fac88f7159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320677636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.3320677636
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all_with_rand_reset.830364115
Short name T419
Test name
Test status
Simulation time 24635223167 ps
CPU time 256.9 seconds
Started Jul 25 04:53:36 PM PDT 24
Finished Jul 25 04:57:54 PM PDT 24
Peak memory 206468 kb
Host smart-b9249dc7-e994-4b60-a015-41e27c09d3b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830364115 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all_with_rand_reset.830364115
Directory /workspace/41.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.1394151087
Short name T293
Test name
Test status
Simulation time 597663391812 ps
CPU time 549 seconds
Started Jul 25 04:53:38 PM PDT 24
Finished Jul 25 05:02:48 PM PDT 24
Peak memory 183464 kb
Host smart-db7eda24-17f3-4b82-9b9e-4ae05bbdabc4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394151087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.1394151087
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.2672685783
Short name T415
Test name
Test status
Simulation time 32775003112 ps
CPU time 42.31 seconds
Started Jul 25 04:53:46 PM PDT 24
Finished Jul 25 04:54:28 PM PDT 24
Peak memory 183584 kb
Host smart-ef1b41e1-b7df-48a0-adb7-dcd29619da47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672685783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.2672685783
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.1779696006
Short name T436
Test name
Test status
Simulation time 22114989099 ps
CPU time 18.58 seconds
Started Jul 25 04:53:44 PM PDT 24
Finished Jul 25 04:54:03 PM PDT 24
Peak memory 183592 kb
Host smart-b492a880-3bed-4750-badb-06a409d9a4c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779696006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.1779696006
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.781677966
Short name T357
Test name
Test status
Simulation time 96931554 ps
CPU time 0.63 seconds
Started Jul 25 04:53:30 PM PDT 24
Finished Jul 25 04:53:31 PM PDT 24
Peak memory 183224 kb
Host smart-4d57c6bc-0e6f-4e2f-acba-7292764ccd6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781677966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.781677966
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.1106549319
Short name T278
Test name
Test status
Simulation time 439191984640 ps
CPU time 848.81 seconds
Started Jul 25 04:53:43 PM PDT 24
Finished Jul 25 05:07:52 PM PDT 24
Peak memory 196500 kb
Host smart-c6b0e13a-25cb-446a-a058-aebbca14d145
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106549319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.1106549319
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all_with_rand_reset.2726264073
Short name T11
Test name
Test status
Simulation time 14909030858 ps
CPU time 156.31 seconds
Started Jul 25 04:53:30 PM PDT 24
Finished Jul 25 04:56:07 PM PDT 24
Peak memory 198292 kb
Host smart-2cede91b-122c-4e51-867a-8d555529530d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726264073 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all_with_rand_reset.2726264073
Directory /workspace/42.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.227706757
Short name T187
Test name
Test status
Simulation time 1146648386565 ps
CPU time 797.27 seconds
Started Jul 25 04:53:53 PM PDT 24
Finished Jul 25 05:07:10 PM PDT 24
Peak memory 183568 kb
Host smart-a50f00ce-41fe-4084-9c4b-b502d5af4c29
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227706757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.rv_timer_cfg_update_on_fly.227706757
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_random.4154994815
Short name T232
Test name
Test status
Simulation time 431095131335 ps
CPU time 647.61 seconds
Started Jul 25 04:53:39 PM PDT 24
Finished Jul 25 05:04:27 PM PDT 24
Peak memory 191668 kb
Host smart-e36cb0e3-924c-43aa-9585-a83d19121848
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154994815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.4154994815
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.526266215
Short name T386
Test name
Test status
Simulation time 673991251 ps
CPU time 1.41 seconds
Started Jul 25 04:53:46 PM PDT 24
Finished Jul 25 04:53:48 PM PDT 24
Peak memory 183340 kb
Host smart-a124f074-46dd-47eb-820f-7dfc71962e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526266215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.526266215
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.1534135258
Short name T378
Test name
Test status
Simulation time 150179266 ps
CPU time 0.59 seconds
Started Jul 25 04:53:45 PM PDT 24
Finished Jul 25 04:53:46 PM PDT 24
Peak memory 183232 kb
Host smart-de56fb3a-c271-409c-a402-7b1c4453a89d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534135258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.1534135258
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.3089441233
Short name T114
Test name
Test status
Simulation time 734323806910 ps
CPU time 674.46 seconds
Started Jul 25 04:53:39 PM PDT 24
Finished Jul 25 05:04:54 PM PDT 24
Peak memory 183556 kb
Host smart-a04ba12d-1b4e-4ab5-8f74-d4ac140943a6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089441233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.3089441233
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.3852992922
Short name T373
Test name
Test status
Simulation time 248707089421 ps
CPU time 103.91 seconds
Started Jul 25 04:53:47 PM PDT 24
Finished Jul 25 04:55:31 PM PDT 24
Peak memory 183440 kb
Host smart-6b1bc7fa-0722-4ec0-a343-d0980aca3bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852992922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.3852992922
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.3516330347
Short name T137
Test name
Test status
Simulation time 67795695323 ps
CPU time 150.87 seconds
Started Jul 25 04:53:47 PM PDT 24
Finished Jul 25 04:56:18 PM PDT 24
Peak memory 195884 kb
Host smart-4dc80729-b0cf-4457-ab0d-77908a45a39d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516330347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.3516330347
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.4015486757
Short name T262
Test name
Test status
Simulation time 268731773797 ps
CPU time 141.27 seconds
Started Jul 25 04:53:42 PM PDT 24
Finished Jul 25 04:56:03 PM PDT 24
Peak memory 191668 kb
Host smart-6f24505d-5e04-499e-b52d-cda87851d36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015486757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.4015486757
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.904964893
Short name T382
Test name
Test status
Simulation time 341184837239 ps
CPU time 268.56 seconds
Started Jul 25 04:53:44 PM PDT 24
Finished Jul 25 04:58:12 PM PDT 24
Peak memory 191776 kb
Host smart-f18d9693-e3c4-4e7f-9702-4a22ee63070e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904964893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all.
904964893
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.1039594535
Short name T43
Test name
Test status
Simulation time 11863625163 ps
CPU time 19.33 seconds
Started Jul 25 04:53:41 PM PDT 24
Finished Jul 25 04:54:00 PM PDT 24
Peak memory 183576 kb
Host smart-6f6e4420-1758-4049-a336-234376ed6c59
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039594535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.1039594535
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.1860142375
Short name T392
Test name
Test status
Simulation time 111513457680 ps
CPU time 78.99 seconds
Started Jul 25 04:53:49 PM PDT 24
Finished Jul 25 04:55:08 PM PDT 24
Peak memory 183492 kb
Host smart-eceaa721-b9f9-47f5-9d7f-ec099042def2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860142375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.1860142375
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.79859464
Short name T345
Test name
Test status
Simulation time 37863161010 ps
CPU time 68.41 seconds
Started Jul 25 04:53:47 PM PDT 24
Finished Jul 25 04:54:56 PM PDT 24
Peak memory 183544 kb
Host smart-2a6e5081-42e0-4c1d-b5b8-363cb01ff206
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79859464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.79859464
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.3026305485
Short name T252
Test name
Test status
Simulation time 67607639154 ps
CPU time 40.42 seconds
Started Jul 25 04:53:41 PM PDT 24
Finished Jul 25 04:54:21 PM PDT 24
Peak memory 191688 kb
Host smart-1ab3a16a-3518-4297-afa0-6c3af4ad78a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026305485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.3026305485
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.713798818
Short name T46
Test name
Test status
Simulation time 91835898 ps
CPU time 0.81 seconds
Started Jul 25 04:53:44 PM PDT 24
Finished Jul 25 04:53:45 PM PDT 24
Peak memory 183332 kb
Host smart-b0a63820-edee-4fd7-a323-29b5e76c535d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713798818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all.
713798818
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.3362729689
Short name T362
Test name
Test status
Simulation time 69670540328 ps
CPU time 92.17 seconds
Started Jul 25 04:53:46 PM PDT 24
Finished Jul 25 04:55:19 PM PDT 24
Peak memory 183524 kb
Host smart-22db2dee-634f-40df-bf73-46046bfd08d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362729689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.3362729689
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.3124390505
Short name T360
Test name
Test status
Simulation time 787298325 ps
CPU time 1.7 seconds
Started Jul 25 04:53:44 PM PDT 24
Finished Jul 25 04:53:46 PM PDT 24
Peak memory 183264 kb
Host smart-b98917d9-b961-402e-a6a5-90446e582509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124390505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.3124390505
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.4001134187
Short name T439
Test name
Test status
Simulation time 39767209 ps
CPU time 0.62 seconds
Started Jul 25 04:53:53 PM PDT 24
Finished Jul 25 04:53:54 PM PDT 24
Peak memory 183328 kb
Host smart-fd84e6f8-6c94-4cf6-bd38-d11decfda8f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001134187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.4001134187
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.598914959
Short name T133
Test name
Test status
Simulation time 330327244682 ps
CPU time 372.05 seconds
Started Jul 25 04:53:43 PM PDT 24
Finished Jul 25 04:59:55 PM PDT 24
Peak memory 183480 kb
Host smart-a28bf275-aa95-4c1e-8e96-16afbbaf89b6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598914959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.rv_timer_cfg_update_on_fly.598914959
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.2229244232
Short name T45
Test name
Test status
Simulation time 62720709045 ps
CPU time 24.52 seconds
Started Jul 25 04:53:51 PM PDT 24
Finished Jul 25 04:54:16 PM PDT 24
Peak memory 183572 kb
Host smart-81f23d52-b038-4954-b427-66c2f8c930a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229244232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.2229244232
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.839862792
Short name T446
Test name
Test status
Simulation time 110715771437 ps
CPU time 196.9 seconds
Started Jul 25 04:53:53 PM PDT 24
Finished Jul 25 04:57:10 PM PDT 24
Peak memory 191748 kb
Host smart-0df6f0ec-0828-46dd-b8b5-7194c05bdac0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839862792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.839862792
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.2047877129
Short name T364
Test name
Test status
Simulation time 664219279 ps
CPU time 0.9 seconds
Started Jul 25 04:53:44 PM PDT 24
Finished Jul 25 04:53:46 PM PDT 24
Peak memory 183364 kb
Host smart-011c1305-1cd1-4d1a-b151-a87c26aee116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047877129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.2047877129
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.285791559
Short name T209
Test name
Test status
Simulation time 246651843244 ps
CPU time 760.61 seconds
Started Jul 25 04:53:54 PM PDT 24
Finished Jul 25 05:06:35 PM PDT 24
Peak memory 196188 kb
Host smart-9884642f-e518-48c4-aa27-a4800a013046
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285791559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all.
285791559
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all_with_rand_reset.43074129
Short name T12
Test name
Test status
Simulation time 35711094026 ps
CPU time 161.92 seconds
Started Jul 25 04:53:43 PM PDT 24
Finished Jul 25 04:56:25 PM PDT 24
Peak memory 198280 kb
Host smart-92167478-c948-4579-99fa-e78c8b2d118b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43074129 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all_with_rand_reset.43074129
Directory /workspace/47.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.3666460032
Short name T340
Test name
Test status
Simulation time 97021905755 ps
CPU time 45.67 seconds
Started Jul 25 04:53:46 PM PDT 24
Finished Jul 25 04:54:32 PM PDT 24
Peak memory 183560 kb
Host smart-e38d3b15-66ec-4a92-a6cf-d58ed330e9c4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666460032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.3666460032
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_random.3220404899
Short name T74
Test name
Test status
Simulation time 143718992674 ps
CPU time 414.71 seconds
Started Jul 25 04:53:47 PM PDT 24
Finished Jul 25 05:00:42 PM PDT 24
Peak memory 193916 kb
Host smart-ec7656e4-bb6a-4666-b05e-4058544261f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220404899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.3220404899
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.3591848152
Short name T404
Test name
Test status
Simulation time 2024370719 ps
CPU time 4.5 seconds
Started Jul 25 04:53:41 PM PDT 24
Finished Jul 25 04:53:45 PM PDT 24
Peak memory 183480 kb
Host smart-913222d2-018b-40b9-aadf-49be3060b1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591848152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.3591848152
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.2829216132
Short name T140
Test name
Test status
Simulation time 249759042136 ps
CPU time 287.16 seconds
Started Jul 25 04:53:47 PM PDT 24
Finished Jul 25 04:58:35 PM PDT 24
Peak memory 183528 kb
Host smart-06f42c9e-9fb3-402c-85f7-1b840c11ab46
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829216132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.2829216132
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_random.917796541
Short name T263
Test name
Test status
Simulation time 30642983016 ps
CPU time 46 seconds
Started Jul 25 04:53:39 PM PDT 24
Finished Jul 25 04:54:25 PM PDT 24
Peak memory 183496 kb
Host smart-a12cfec0-d85e-41cf-917e-4c9a98c54a41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917796541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.917796541
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.926454533
Short name T302
Test name
Test status
Simulation time 378728458461 ps
CPU time 590.64 seconds
Started Jul 25 04:53:39 PM PDT 24
Finished Jul 25 05:03:30 PM PDT 24
Peak memory 191848 kb
Host smart-46458e0f-9f9b-4467-b71b-4343aaf0c766
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926454533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all.
926454533
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.1071712449
Short name T349
Test name
Test status
Simulation time 15219570167 ps
CPU time 5.58 seconds
Started Jul 25 04:52:55 PM PDT 24
Finished Jul 25 04:53:01 PM PDT 24
Peak memory 183464 kb
Host smart-546d06b6-7a85-4b6a-a84e-0b3dfe6aa9ae
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071712449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.1071712449
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.850465064
Short name T408
Test name
Test status
Simulation time 252397449570 ps
CPU time 185.16 seconds
Started Jul 25 04:53:04 PM PDT 24
Finished Jul 25 04:56:10 PM PDT 24
Peak memory 183576 kb
Host smart-814fc552-f4c7-4e32-97f0-b0d83017f84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850465064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.850465064
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.3995490948
Short name T99
Test name
Test status
Simulation time 163508465186 ps
CPU time 312.54 seconds
Started Jul 25 04:53:06 PM PDT 24
Finished Jul 25 04:58:19 PM PDT 24
Peak memory 183496 kb
Host smart-6050d8f1-74ca-4ff3-9799-045b5c8cad57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995490948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.3995490948
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.2241372689
Short name T112
Test name
Test status
Simulation time 26326130254 ps
CPU time 11.39 seconds
Started Jul 25 04:53:13 PM PDT 24
Finished Jul 25 04:53:25 PM PDT 24
Peak memory 191752 kb
Host smart-3272979d-2630-4f1e-af9e-b518f6774634
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241372689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
2241372689
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/50.rv_timer_random.1926464333
Short name T190
Test name
Test status
Simulation time 125885934242 ps
CPU time 716.95 seconds
Started Jul 25 04:53:50 PM PDT 24
Finished Jul 25 05:05:47 PM PDT 24
Peak memory 194096 kb
Host smart-3a783309-454e-4005-8df2-f5e7dd1c8d14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926464333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.1926464333
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.4184913580
Short name T265
Test name
Test status
Simulation time 604384687824 ps
CPU time 1619.22 seconds
Started Jul 25 04:53:46 PM PDT 24
Finished Jul 25 05:20:46 PM PDT 24
Peak memory 191700 kb
Host smart-d95fcdaa-ad17-425e-82b5-7ec9f61db2ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184913580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.4184913580
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.2688310510
Short name T338
Test name
Test status
Simulation time 469932841757 ps
CPU time 143.83 seconds
Started Jul 25 04:53:48 PM PDT 24
Finished Jul 25 04:56:12 PM PDT 24
Peak memory 191676 kb
Host smart-5990a17d-2820-49f0-9c2c-6e763f8759c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688310510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.2688310510
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.2721917753
Short name T181
Test name
Test status
Simulation time 401970502385 ps
CPU time 207.47 seconds
Started Jul 25 04:53:48 PM PDT 24
Finished Jul 25 04:57:16 PM PDT 24
Peak memory 191780 kb
Host smart-6da9fe3c-5c0d-4bf7-b3b8-f02850d812a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721917753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.2721917753
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.2422052854
Short name T72
Test name
Test status
Simulation time 52051043856 ps
CPU time 89.04 seconds
Started Jul 25 04:53:46 PM PDT 24
Finished Jul 25 04:55:15 PM PDT 24
Peak memory 191772 kb
Host smart-3368f13e-3a3b-4071-932c-61b8b3271cd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422052854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.2422052854
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.2826930199
Short name T311
Test name
Test status
Simulation time 19781422818 ps
CPU time 33.53 seconds
Started Jul 25 04:53:44 PM PDT 24
Finished Jul 25 04:54:18 PM PDT 24
Peak memory 183504 kb
Host smart-b42cc724-b39f-436e-8690-52ab9e9bd9a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826930199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.2826930199
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.2963728052
Short name T165
Test name
Test status
Simulation time 357169704191 ps
CPU time 1048.94 seconds
Started Jul 25 04:53:37 PM PDT 24
Finished Jul 25 05:11:06 PM PDT 24
Peak memory 191732 kb
Host smart-c58e4a03-efe1-4f59-b2ad-806430ca8b04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963728052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.2963728052
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.1956354011
Short name T207
Test name
Test status
Simulation time 85411546190 ps
CPU time 83.42 seconds
Started Jul 25 04:53:41 PM PDT 24
Finished Jul 25 04:55:04 PM PDT 24
Peak memory 183516 kb
Host smart-7ecc2826-03f8-423b-a249-cb86c6499edd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956354011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.1956354011
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.3769547610
Short name T126
Test name
Test status
Simulation time 13783149491 ps
CPU time 20.52 seconds
Started Jul 25 04:53:05 PM PDT 24
Finished Jul 25 04:53:25 PM PDT 24
Peak memory 183456 kb
Host smart-c433f912-e00b-406d-be09-070af0b53687
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769547610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.3769547610
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.1104213641
Short name T405
Test name
Test status
Simulation time 225773636937 ps
CPU time 73.68 seconds
Started Jul 25 04:52:58 PM PDT 24
Finished Jul 25 04:54:12 PM PDT 24
Peak memory 183532 kb
Host smart-873469e8-7208-4946-8862-dda902261ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104213641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.1104213641
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.1149053772
Short name T427
Test name
Test status
Simulation time 265599676680 ps
CPU time 135.54 seconds
Started Jul 25 04:53:06 PM PDT 24
Finished Jul 25 04:55:22 PM PDT 24
Peak memory 191680 kb
Host smart-d1aaae4d-9fbe-4918-85e3-a019791574fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149053772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.1149053772
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.2312400208
Short name T328
Test name
Test status
Simulation time 33922318499 ps
CPU time 38.38 seconds
Started Jul 25 04:52:56 PM PDT 24
Finished Jul 25 04:53:34 PM PDT 24
Peak memory 191752 kb
Host smart-48431b93-d350-48e2-bae5-c98b2f02b87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312400208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.2312400208
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.121659788
Short name T395
Test name
Test status
Simulation time 303632981210 ps
CPU time 425.28 seconds
Started Jul 25 04:52:53 PM PDT 24
Finished Jul 25 04:59:58 PM PDT 24
Peak memory 196112 kb
Host smart-560c98e5-e2ff-4dc7-84aa-43b821852196
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121659788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.121659788
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/60.rv_timer_random.3834464438
Short name T334
Test name
Test status
Simulation time 583458781712 ps
CPU time 752.08 seconds
Started Jul 25 04:53:48 PM PDT 24
Finished Jul 25 05:06:21 PM PDT 24
Peak memory 191756 kb
Host smart-1eb24030-e0b4-4398-b0c0-b01d3a301571
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834464438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.3834464438
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.2644299110
Short name T110
Test name
Test status
Simulation time 154076913302 ps
CPU time 624.06 seconds
Started Jul 25 04:53:43 PM PDT 24
Finished Jul 25 05:04:08 PM PDT 24
Peak memory 191744 kb
Host smart-2ec9dd61-2222-475d-ab48-ee0defd3fe48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644299110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.2644299110
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.3142565492
Short name T443
Test name
Test status
Simulation time 1910335366 ps
CPU time 1.92 seconds
Started Jul 25 04:53:44 PM PDT 24
Finished Jul 25 04:53:46 PM PDT 24
Peak memory 183524 kb
Host smart-9e4039db-6cbb-4ce8-a1a8-71556c5271d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142565492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.3142565492
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.92381448
Short name T184
Test name
Test status
Simulation time 969004975526 ps
CPU time 571.97 seconds
Started Jul 25 04:53:43 PM PDT 24
Finished Jul 25 05:03:15 PM PDT 24
Peak memory 191684 kb
Host smart-baaeedcf-80cc-4344-a943-d884614b9f04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92381448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.92381448
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.4218059533
Short name T426
Test name
Test status
Simulation time 136486507179 ps
CPU time 145.3 seconds
Started Jul 25 04:53:44 PM PDT 24
Finished Jul 25 04:56:10 PM PDT 24
Peak memory 191804 kb
Host smart-bfbe59d7-2f01-4c6a-a058-8c15ade9db24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218059533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.4218059533
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.3239632437
Short name T47
Test name
Test status
Simulation time 4633133305 ps
CPU time 7.73 seconds
Started Jul 25 04:53:40 PM PDT 24
Finished Jul 25 04:53:48 PM PDT 24
Peak memory 183496 kb
Host smart-d29f97bb-7273-4f43-8c39-cd7e0336d366
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239632437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.3239632437
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.1053064936
Short name T9
Test name
Test status
Simulation time 117909812176 ps
CPU time 191.79 seconds
Started Jul 25 04:53:57 PM PDT 24
Finished Jul 25 04:57:09 PM PDT 24
Peak memory 191772 kb
Host smart-73953f7d-4c2c-4364-927b-145064941189
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053064936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.1053064936
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.670762121
Short name T428
Test name
Test status
Simulation time 156351524835 ps
CPU time 80.62 seconds
Started Jul 25 04:53:43 PM PDT 24
Finished Jul 25 04:55:04 PM PDT 24
Peak memory 191788 kb
Host smart-1ef625b9-29bf-44a7-808a-6bd529d9703c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670762121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.670762121
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.3575085713
Short name T300
Test name
Test status
Simulation time 431685941935 ps
CPU time 733 seconds
Started Jul 25 04:53:48 PM PDT 24
Finished Jul 25 05:06:01 PM PDT 24
Peak memory 191772 kb
Host smart-e6e6c16d-849d-485d-9a53-b1bebd4ccd68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575085713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.3575085713
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.3344094152
Short name T212
Test name
Test status
Simulation time 2903873635 ps
CPU time 4.59 seconds
Started Jul 25 04:52:52 PM PDT 24
Finished Jul 25 04:52:57 PM PDT 24
Peak memory 183576 kb
Host smart-36093088-80ff-49ac-be75-f204d3643153
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344094152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.3344094152
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.4147554203
Short name T433
Test name
Test status
Simulation time 47109684805 ps
CPU time 65.86 seconds
Started Jul 25 04:53:06 PM PDT 24
Finished Jul 25 04:54:12 PM PDT 24
Peak memory 183580 kb
Host smart-5bf187ad-3ea4-41f6-92ce-fbe58dba43d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147554203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.4147554203
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.2112057184
Short name T97
Test name
Test status
Simulation time 76101487797 ps
CPU time 72.16 seconds
Started Jul 25 04:52:53 PM PDT 24
Finished Jul 25 04:54:06 PM PDT 24
Peak memory 191672 kb
Host smart-cca09de3-4f5f-45c8-982c-1796e21d39f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112057184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.2112057184
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.3766617708
Short name T347
Test name
Test status
Simulation time 291653673805 ps
CPU time 2599.44 seconds
Started Jul 25 04:52:58 PM PDT 24
Finished Jul 25 05:36:18 PM PDT 24
Peak memory 195012 kb
Host smart-c6a72764-d2cd-4a07-ac34-edfd9b62645c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766617708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.3766617708
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.613270167
Short name T50
Test name
Test status
Simulation time 1266383427460 ps
CPU time 805.15 seconds
Started Jul 25 04:53:05 PM PDT 24
Finished Jul 25 05:06:31 PM PDT 24
Peak memory 196448 kb
Host smart-53ffa28f-cabe-4960-9423-a00557c6dd1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613270167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.613270167
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/70.rv_timer_random.792741551
Short name T163
Test name
Test status
Simulation time 97988180605 ps
CPU time 243.03 seconds
Started Jul 25 04:53:45 PM PDT 24
Finished Jul 25 04:57:48 PM PDT 24
Peak memory 191708 kb
Host smart-ec558ca1-9525-4ae8-bbb7-8bc7eb6bb4d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792741551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.792741551
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.1305310988
Short name T118
Test name
Test status
Simulation time 403908615235 ps
CPU time 363.66 seconds
Started Jul 25 04:53:45 PM PDT 24
Finished Jul 25 04:59:49 PM PDT 24
Peak memory 191764 kb
Host smart-8332aca8-798b-4d2e-88f1-78185c3b5088
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305310988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.1305310988
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.324972749
Short name T290
Test name
Test status
Simulation time 141398864060 ps
CPU time 85.96 seconds
Started Jul 25 04:53:53 PM PDT 24
Finished Jul 25 04:55:19 PM PDT 24
Peak memory 183560 kb
Host smart-87100994-bb39-4e88-9703-217346c94e46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324972749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.324972749
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.3369421433
Short name T200
Test name
Test status
Simulation time 29734616603 ps
CPU time 42.85 seconds
Started Jul 25 04:53:38 PM PDT 24
Finished Jul 25 04:54:21 PM PDT 24
Peak memory 183476 kb
Host smart-6090c4b4-aeeb-41d0-bce6-6be7a330eb8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369421433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.3369421433
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.3518583803
Short name T322
Test name
Test status
Simulation time 44067314667 ps
CPU time 45 seconds
Started Jul 25 04:53:56 PM PDT 24
Finished Jul 25 04:54:41 PM PDT 24
Peak memory 191804 kb
Host smart-8ef87c78-ff91-45ed-a0e8-f52af9b03763
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518583803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.3518583803
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.77157396
Short name T59
Test name
Test status
Simulation time 67659480237 ps
CPU time 970.77 seconds
Started Jul 25 04:53:47 PM PDT 24
Finished Jul 25 05:09:59 PM PDT 24
Peak memory 183572 kb
Host smart-0905b9f0-19c9-49d5-8b1e-1213d606eac3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77157396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.77157396
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.2847823000
Short name T249
Test name
Test status
Simulation time 16093303018 ps
CPU time 25.39 seconds
Started Jul 25 04:53:44 PM PDT 24
Finished Jul 25 04:54:09 PM PDT 24
Peak memory 183588 kb
Host smart-9d197dcc-86b1-44fc-b452-146c88a8fefb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847823000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.2847823000
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.3153612383
Short name T67
Test name
Test status
Simulation time 879620793437 ps
CPU time 449.34 seconds
Started Jul 25 04:53:31 PM PDT 24
Finished Jul 25 05:01:01 PM PDT 24
Peak memory 183572 kb
Host smart-698fe371-25dd-4b18-a8bf-9b75f524e290
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153612383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.3153612383
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.484289698
Short name T370
Test name
Test status
Simulation time 140652465689 ps
CPU time 187.64 seconds
Started Jul 25 04:53:11 PM PDT 24
Finished Jul 25 04:56:19 PM PDT 24
Peak memory 183576 kb
Host smart-bb038022-5352-4356-a9c2-b727ce996b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484289698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.484289698
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.915507060
Short name T123
Test name
Test status
Simulation time 592688678447 ps
CPU time 466.32 seconds
Started Jul 25 04:53:07 PM PDT 24
Finished Jul 25 05:00:53 PM PDT 24
Peak memory 191664 kb
Host smart-dbf2af97-bd72-4e5e-87ac-9414a16840e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915507060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.915507060
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.1068932185
Short name T384
Test name
Test status
Simulation time 210116215 ps
CPU time 0.71 seconds
Started Jul 25 04:52:55 PM PDT 24
Finished Jul 25 04:52:56 PM PDT 24
Peak memory 183228 kb
Host smart-d90e54c3-b8bc-45ad-b680-f2eca608e92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068932185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.1068932185
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.3361303915
Short name T437
Test name
Test status
Simulation time 643549590456 ps
CPU time 160.77 seconds
Started Jul 25 04:53:47 PM PDT 24
Finished Jul 25 04:56:28 PM PDT 24
Peak memory 191796 kb
Host smart-0883281e-8a8b-46ef-97aa-0c326b78c297
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361303915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.3361303915
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.3433982298
Short name T68
Test name
Test status
Simulation time 50835411955 ps
CPU time 38.4 seconds
Started Jul 25 04:53:44 PM PDT 24
Finished Jul 25 04:54:22 PM PDT 24
Peak memory 183504 kb
Host smart-c500ecbe-4fae-415b-8ce1-179c236d5ec4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433982298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.3433982298
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.1392829804
Short name T194
Test name
Test status
Simulation time 32403996713 ps
CPU time 177.45 seconds
Started Jul 25 04:53:48 PM PDT 24
Finished Jul 25 04:56:46 PM PDT 24
Peak memory 183564 kb
Host smart-fadf1c85-4f64-4ecd-9169-0dad1aeb4966
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392829804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.1392829804
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.1115535612
Short name T206
Test name
Test status
Simulation time 36372491255 ps
CPU time 54.61 seconds
Started Jul 25 04:53:46 PM PDT 24
Finished Jul 25 04:54:41 PM PDT 24
Peak memory 191764 kb
Host smart-4314a6ec-c1d7-4e9e-b359-019fb8c27259
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115535612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.1115535612
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.3420390619
Short name T48
Test name
Test status
Simulation time 388160781383 ps
CPU time 66.53 seconds
Started Jul 25 04:53:40 PM PDT 24
Finished Jul 25 04:54:46 PM PDT 24
Peak memory 183460 kb
Host smart-ceadffa2-15f2-4e5d-9e76-39dc6fa13864
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420390619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.3420390619
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.2302691830
Short name T310
Test name
Test status
Simulation time 199958763512 ps
CPU time 447.01 seconds
Started Jul 25 04:53:40 PM PDT 24
Finished Jul 25 05:01:07 PM PDT 24
Peak memory 191696 kb
Host smart-3ad4c895-52b7-4123-8ad8-a128a6c3885b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302691830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.2302691830
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.1683864122
Short name T143
Test name
Test status
Simulation time 721028842135 ps
CPU time 3295.8 seconds
Started Jul 25 04:53:46 PM PDT 24
Finished Jul 25 05:48:42 PM PDT 24
Peak memory 191696 kb
Host smart-6d22bab5-0fa0-409c-918b-6b0b2b152d0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683864122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.1683864122
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.4100562799
Short name T423
Test name
Test status
Simulation time 91850663599 ps
CPU time 696.21 seconds
Started Jul 25 04:53:46 PM PDT 24
Finished Jul 25 05:05:22 PM PDT 24
Peak memory 191696 kb
Host smart-ce41556d-0860-4096-92f8-0280a20a3293
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100562799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.4100562799
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.761717728
Short name T258
Test name
Test status
Simulation time 326440465259 ps
CPU time 168.14 seconds
Started Jul 25 04:53:04 PM PDT 24
Finished Jul 25 04:55:53 PM PDT 24
Peak memory 183560 kb
Host smart-d2160c0c-357f-46dc-a0f4-a9e83794fd83
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761717728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.rv_timer_cfg_update_on_fly.761717728
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.2329022616
Short name T411
Test name
Test status
Simulation time 206348517354 ps
CPU time 81.65 seconds
Started Jul 25 04:53:01 PM PDT 24
Finished Jul 25 04:54:22 PM PDT 24
Peak memory 183456 kb
Host smart-4e822240-ee4f-4f1c-9c1c-73e955652ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329022616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.2329022616
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.1941275205
Short name T320
Test name
Test status
Simulation time 68758936659 ps
CPU time 336.85 seconds
Started Jul 25 04:52:52 PM PDT 24
Finished Jul 25 04:58:29 PM PDT 24
Peak memory 191796 kb
Host smart-9bb95265-00ec-49bc-b767-6c66aa3eb315
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941275205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.1941275205
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.2184597851
Short name T193
Test name
Test status
Simulation time 88769509397 ps
CPU time 79.21 seconds
Started Jul 25 04:53:07 PM PDT 24
Finished Jul 25 04:54:26 PM PDT 24
Peak memory 191704 kb
Host smart-e83c0210-2b4b-4006-a06c-90b5b6063391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184597851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.2184597851
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.2319043847
Short name T276
Test name
Test status
Simulation time 327700816467 ps
CPU time 451.2 seconds
Started Jul 25 04:53:04 PM PDT 24
Finished Jul 25 05:00:36 PM PDT 24
Peak memory 196172 kb
Host smart-6d0cafcb-1961-43da-9285-da71e59cd2cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319043847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
2319043847
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all_with_rand_reset.4248477122
Short name T28
Test name
Test status
Simulation time 63231522974 ps
CPU time 118.57 seconds
Started Jul 25 04:53:03 PM PDT 24
Finished Jul 25 04:55:02 PM PDT 24
Peak memory 206444 kb
Host smart-43435137-a558-4677-9c04-b3f6b81f13f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248477122 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all_with_rand_reset.4248477122
Directory /workspace/9.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.630318213
Short name T287
Test name
Test status
Simulation time 45245840127 ps
CPU time 342.16 seconds
Started Jul 25 04:53:40 PM PDT 24
Finished Jul 25 04:59:22 PM PDT 24
Peak memory 191776 kb
Host smart-f8f771f0-7b6a-474b-8da6-0388a5259e58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630318213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.630318213
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.2796357934
Short name T270
Test name
Test status
Simulation time 166819003528 ps
CPU time 235.77 seconds
Started Jul 25 04:53:51 PM PDT 24
Finished Jul 25 04:57:47 PM PDT 24
Peak memory 191760 kb
Host smart-a29b1758-5c4d-4314-b859-c9e88f813b40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796357934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.2796357934
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.3679519969
Short name T62
Test name
Test status
Simulation time 60648169303 ps
CPU time 113.8 seconds
Started Jul 25 04:53:40 PM PDT 24
Finished Jul 25 04:55:34 PM PDT 24
Peak memory 191724 kb
Host smart-f149a0ac-b525-427e-8dc7-da821aec2838
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679519969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.3679519969
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.324268127
Short name T130
Test name
Test status
Simulation time 47367966536 ps
CPU time 333.7 seconds
Started Jul 25 04:53:46 PM PDT 24
Finished Jul 25 04:59:20 PM PDT 24
Peak memory 191776 kb
Host smart-f8934649-a406-44ae-9a5c-7c9acfa48c3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324268127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.324268127
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.2563528961
Short name T298
Test name
Test status
Simulation time 265279209040 ps
CPU time 653.28 seconds
Started Jul 25 04:53:47 PM PDT 24
Finished Jul 25 05:04:40 PM PDT 24
Peak memory 191728 kb
Host smart-680a43a5-5eaa-48a5-b064-a025f4302d50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563528961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.2563528961
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.697214523
Short name T301
Test name
Test status
Simulation time 450380222475 ps
CPU time 991.38 seconds
Started Jul 25 04:53:47 PM PDT 24
Finished Jul 25 05:10:19 PM PDT 24
Peak memory 191776 kb
Host smart-ff7cbcc0-f2c9-4eab-9a2a-e47bedd743f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697214523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.697214523
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.602703593
Short name T216
Test name
Test status
Simulation time 622036878161 ps
CPU time 464.57 seconds
Started Jul 25 04:53:45 PM PDT 24
Finished Jul 25 05:01:29 PM PDT 24
Peak memory 191700 kb
Host smart-1350e8e7-d041-4796-931a-75cd80607167
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602703593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.602703593
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.2653756427
Short name T421
Test name
Test status
Simulation time 113777187371 ps
CPU time 291.6 seconds
Started Jul 25 04:53:47 PM PDT 24
Finished Jul 25 04:58:39 PM PDT 24
Peak memory 191708 kb
Host smart-8f21e42d-db72-4f81-81f1-03df87bf656b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653756427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.2653756427
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.636594395
Short name T243
Test name
Test status
Simulation time 295517588458 ps
CPU time 238.44 seconds
Started Jul 25 04:53:47 PM PDT 24
Finished Jul 25 04:57:46 PM PDT 24
Peak memory 191776 kb
Host smart-a4e82df2-ad41-4794-94e4-de00457b7b28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636594395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.636594395
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.2435712539
Short name T205
Test name
Test status
Simulation time 350770015635 ps
CPU time 421.9 seconds
Started Jul 25 04:53:51 PM PDT 24
Finished Jul 25 05:00:53 PM PDT 24
Peak memory 191740 kb
Host smart-7424818f-3b4d-4e62-b37c-d4767f7dc81d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435712539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.2435712539
Directory /workspace/99.rv_timer_random/latest
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