Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.64 99.36 98.73 100.00 100.00 100.00 99.77


Total test records in report: 584
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T508 /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.3830452814 Jul 26 04:47:42 PM PDT 24 Jul 26 04:47:44 PM PDT 24 378881212 ps
T509 /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.665602258 Jul 26 04:47:38 PM PDT 24 Jul 26 04:47:39 PM PDT 24 23031768 ps
T510 /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.751846789 Jul 26 04:47:31 PM PDT 24 Jul 26 04:47:32 PM PDT 24 28309854 ps
T511 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2750432597 Jul 26 04:47:17 PM PDT 24 Jul 26 04:47:17 PM PDT 24 16636114 ps
T512 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.2577235209 Jul 26 04:47:27 PM PDT 24 Jul 26 04:47:28 PM PDT 24 178999639 ps
T513 /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.1818521488 Jul 26 04:47:27 PM PDT 24 Jul 26 04:47:28 PM PDT 24 44726382 ps
T514 /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.674198155 Jul 26 04:47:28 PM PDT 24 Jul 26 04:47:29 PM PDT 24 44734945 ps
T515 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.415705795 Jul 26 04:48:01 PM PDT 24 Jul 26 04:48:06 PM PDT 24 56832162 ps
T516 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.3690389728 Jul 26 04:47:46 PM PDT 24 Jul 26 04:47:47 PM PDT 24 16440801 ps
T517 /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1875926741 Jul 26 04:47:41 PM PDT 24 Jul 26 04:47:42 PM PDT 24 15510011 ps
T518 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.1541780315 Jul 26 04:47:11 PM PDT 24 Jul 26 04:47:14 PM PDT 24 50721121 ps
T519 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.4249924609 Jul 26 04:47:33 PM PDT 24 Jul 26 04:47:33 PM PDT 24 31710786 ps
T520 /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3632874926 Jul 26 04:47:23 PM PDT 24 Jul 26 04:47:30 PM PDT 24 338917169 ps
T107 /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1589298407 Jul 26 04:47:23 PM PDT 24 Jul 26 04:47:24 PM PDT 24 48659578 ps
T521 /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.1038569649 Jul 26 04:47:53 PM PDT 24 Jul 26 04:47:53 PM PDT 24 54626199 ps
T522 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.1728262924 Jul 26 04:47:19 PM PDT 24 Jul 26 04:47:21 PM PDT 24 47491247 ps
T523 /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.2282390867 Jul 26 04:47:25 PM PDT 24 Jul 26 04:47:26 PM PDT 24 130584852 ps
T524 /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.2160895758 Jul 26 04:47:16 PM PDT 24 Jul 26 04:47:17 PM PDT 24 22405972 ps
T525 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.2113304218 Jul 26 04:47:31 PM PDT 24 Jul 26 04:47:32 PM PDT 24 18387564 ps
T526 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.277266952 Jul 26 04:47:37 PM PDT 24 Jul 26 04:47:37 PM PDT 24 22372030 ps
T527 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.495175904 Jul 26 04:47:15 PM PDT 24 Jul 26 04:47:16 PM PDT 24 20236161 ps
T528 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2652194519 Jul 26 04:47:24 PM PDT 24 Jul 26 04:47:25 PM PDT 24 19812480 ps
T94 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.1079222345 Jul 26 04:47:22 PM PDT 24 Jul 26 04:47:22 PM PDT 24 21560651 ps
T95 /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.2392197297 Jul 26 04:47:31 PM PDT 24 Jul 26 04:47:31 PM PDT 24 14857856 ps
T529 /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.3202531976 Jul 26 04:47:30 PM PDT 24 Jul 26 04:47:30 PM PDT 24 11610316 ps
T530 /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.961155283 Jul 26 04:47:16 PM PDT 24 Jul 26 04:47:18 PM PDT 24 78036659 ps
T531 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.2197201967 Jul 26 04:47:25 PM PDT 24 Jul 26 04:47:26 PM PDT 24 58106878 ps
T532 /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.1790555877 Jul 26 04:47:18 PM PDT 24 Jul 26 04:47:19 PM PDT 24 63674661 ps
T533 /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1236185271 Jul 26 04:47:56 PM PDT 24 Jul 26 04:47:57 PM PDT 24 150347693 ps
T534 /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.259000171 Jul 26 04:47:36 PM PDT 24 Jul 26 04:47:42 PM PDT 24 41189934 ps
T535 /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.3529477951 Jul 26 04:47:28 PM PDT 24 Jul 26 04:47:29 PM PDT 24 14826567 ps
T536 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.2692585146 Jul 26 04:47:28 PM PDT 24 Jul 26 04:47:29 PM PDT 24 30871292 ps
T537 /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.113316938 Jul 26 04:47:28 PM PDT 24 Jul 26 04:47:29 PM PDT 24 86429380 ps
T538 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.1395450292 Jul 26 04:47:27 PM PDT 24 Jul 26 04:47:29 PM PDT 24 127656562 ps
T539 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.2596879538 Jul 26 04:47:50 PM PDT 24 Jul 26 04:47:55 PM PDT 24 296400055 ps
T540 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.3779757281 Jul 26 04:47:23 PM PDT 24 Jul 26 04:47:24 PM PDT 24 14692009 ps
T541 /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.112354988 Jul 26 04:47:17 PM PDT 24 Jul 26 04:47:18 PM PDT 24 37161433 ps
T542 /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.3781354265 Jul 26 04:47:33 PM PDT 24 Jul 26 04:47:34 PM PDT 24 82699986 ps
T96 /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.3200782114 Jul 26 04:47:37 PM PDT 24 Jul 26 04:47:37 PM PDT 24 12147970 ps
T543 /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.2100001417 Jul 26 04:47:33 PM PDT 24 Jul 26 04:47:34 PM PDT 24 22351049 ps
T544 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.2771755687 Jul 26 04:47:37 PM PDT 24 Jul 26 04:47:38 PM PDT 24 15289471 ps
T97 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.2856213683 Jul 26 04:47:32 PM PDT 24 Jul 26 04:47:33 PM PDT 24 45033141 ps
T545 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1605261363 Jul 26 04:47:44 PM PDT 24 Jul 26 04:47:50 PM PDT 24 58992143 ps
T546 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1184335812 Jul 26 04:47:35 PM PDT 24 Jul 26 04:47:36 PM PDT 24 66751328 ps
T547 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.1197623879 Jul 26 04:47:22 PM PDT 24 Jul 26 04:47:23 PM PDT 24 46445284 ps
T548 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.3190216960 Jul 26 04:47:26 PM PDT 24 Jul 26 04:47:28 PM PDT 24 253554304 ps
T549 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.730929777 Jul 26 04:47:34 PM PDT 24 Jul 26 04:47:34 PM PDT 24 23123051 ps
T550 /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.417593304 Jul 26 04:47:25 PM PDT 24 Jul 26 04:47:26 PM PDT 24 28133911 ps
T551 /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.1755487568 Jul 26 04:47:13 PM PDT 24 Jul 26 04:47:14 PM PDT 24 38751684 ps
T552 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.4197848352 Jul 26 04:47:34 PM PDT 24 Jul 26 04:47:34 PM PDT 24 11453548 ps
T553 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.1538076898 Jul 26 04:47:27 PM PDT 24 Jul 26 04:47:28 PM PDT 24 13877129 ps
T554 /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2792989461 Jul 26 04:47:23 PM PDT 24 Jul 26 04:47:25 PM PDT 24 263253150 ps
T555 /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.1510061864 Jul 26 04:47:06 PM PDT 24 Jul 26 04:47:08 PM PDT 24 590363614 ps
T556 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.486866961 Jul 26 04:47:22 PM PDT 24 Jul 26 04:47:28 PM PDT 24 20092987 ps
T557 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.579762363 Jul 26 04:47:32 PM PDT 24 Jul 26 04:47:33 PM PDT 24 55175370 ps
T558 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.1618571065 Jul 26 04:47:29 PM PDT 24 Jul 26 04:47:30 PM PDT 24 97493747 ps
T559 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3318403578 Jul 26 04:47:30 PM PDT 24 Jul 26 04:47:31 PM PDT 24 16461565 ps
T98 /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.1926687383 Jul 26 04:47:34 PM PDT 24 Jul 26 04:47:38 PM PDT 24 1693656843 ps
T560 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3756410541 Jul 26 04:47:31 PM PDT 24 Jul 26 04:47:34 PM PDT 24 104406906 ps
T561 /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.2969930096 Jul 26 04:47:37 PM PDT 24 Jul 26 04:47:38 PM PDT 24 59799768 ps
T562 /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.312979246 Jul 26 04:47:38 PM PDT 24 Jul 26 04:47:38 PM PDT 24 14455031 ps
T563 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.648433997 Jul 26 04:47:22 PM PDT 24 Jul 26 04:47:23 PM PDT 24 157943944 ps
T564 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.1434636201 Jul 26 04:47:41 PM PDT 24 Jul 26 04:47:42 PM PDT 24 86033309 ps
T565 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.3031958033 Jul 26 04:47:37 PM PDT 24 Jul 26 04:47:38 PM PDT 24 55114358 ps
T566 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.1156735038 Jul 26 04:47:28 PM PDT 24 Jul 26 04:47:30 PM PDT 24 126059404 ps
T567 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.569436127 Jul 26 04:47:39 PM PDT 24 Jul 26 04:47:40 PM PDT 24 343141446 ps
T568 /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2198660658 Jul 26 04:47:41 PM PDT 24 Jul 26 04:47:42 PM PDT 24 43519195 ps
T569 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.3767660341 Jul 26 04:47:29 PM PDT 24 Jul 26 04:47:29 PM PDT 24 13135245 ps
T570 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.556869478 Jul 26 04:47:25 PM PDT 24 Jul 26 04:47:26 PM PDT 24 23558869 ps
T571 /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.3862472301 Jul 26 04:47:11 PM PDT 24 Jul 26 04:47:14 PM PDT 24 174088763 ps
T572 /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.595408640 Jul 26 04:47:49 PM PDT 24 Jul 26 04:47:49 PM PDT 24 12692289 ps
T113 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.4043285315 Jul 26 04:47:14 PM PDT 24 Jul 26 04:47:15 PM PDT 24 423038505 ps
T573 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.1680507534 Jul 26 04:47:31 PM PDT 24 Jul 26 04:47:32 PM PDT 24 37971833 ps
T574 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.4046702416 Jul 26 04:47:15 PM PDT 24 Jul 26 04:47:16 PM PDT 24 54960070 ps
T575 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.4024934525 Jul 26 04:47:27 PM PDT 24 Jul 26 04:47:28 PM PDT 24 25339233 ps
T576 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.4016794360 Jul 26 04:47:16 PM PDT 24 Jul 26 04:47:17 PM PDT 24 75319103 ps
T577 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2748158593 Jul 26 04:47:20 PM PDT 24 Jul 26 04:47:20 PM PDT 24 62389132 ps
T578 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3782157527 Jul 26 04:47:22 PM PDT 24 Jul 26 04:47:23 PM PDT 24 41340370 ps
T579 /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.3015438929 Jul 26 04:47:24 PM PDT 24 Jul 26 04:47:25 PM PDT 24 15975413 ps
T580 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1324835969 Jul 26 04:47:45 PM PDT 24 Jul 26 04:47:46 PM PDT 24 30976311 ps
T581 /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.4110159606 Jul 26 04:47:20 PM PDT 24 Jul 26 04:47:33 PM PDT 24 517550538 ps
T582 /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.3609999120 Jul 26 04:47:19 PM PDT 24 Jul 26 04:47:19 PM PDT 24 51139474 ps
T583 /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.2238190689 Jul 26 04:47:49 PM PDT 24 Jul 26 04:47:49 PM PDT 24 16755835 ps
T584 /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.484540048 Jul 26 04:47:43 PM PDT 24 Jul 26 04:47:45 PM PDT 24 118684836 ps

Test location /workspace/coverage/default/0.rv_timer_disabled.3399422792
Short name T5
Test name
Test status
Simulation time 257741318421 ps
CPU time 166.82 seconds
Started Jul 26 04:47:27 PM PDT 24
Finished Jul 26 04:50:14 PM PDT 24
Peak memory 183372 kb
Host smart-94f17cf7-7522-40e1-81e6-156cae1d4659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399422792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.3399422792
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all_with_rand_reset.270079876
Short name T12
Test name
Test status
Simulation time 59462037538 ps
CPU time 328.96 seconds
Started Jul 26 04:47:51 PM PDT 24
Finished Jul 26 04:53:20 PM PDT 24
Peak memory 206292 kb
Host smart-103f7b95-854d-43d2-93e8-c522fae25953
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270079876 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all_with_rand_reset.270079876
Directory /workspace/21.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.rv_timer_random.3003179840
Short name T2
Test name
Test status
Simulation time 185134012295 ps
CPU time 629.11 seconds
Started Jul 26 04:48:18 PM PDT 24
Finished Jul 26 04:58:47 PM PDT 24
Peak memory 191592 kb
Host smart-54c0034c-685c-4a14-a501-fd53e96f8050
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003179840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.3003179840
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.42130716
Short name T137
Test name
Test status
Simulation time 571290726861 ps
CPU time 1493.87 seconds
Started Jul 26 04:48:09 PM PDT 24
Finished Jul 26 05:13:03 PM PDT 24
Peak memory 191572 kb
Host smart-d6418b91-2e04-4352-b01f-1c98506385d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42130716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all.42130716
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.3455344184
Short name T30
Test name
Test status
Simulation time 173030989 ps
CPU time 0.83 seconds
Started Jul 26 04:47:24 PM PDT 24
Finished Jul 26 04:47:25 PM PDT 24
Peak memory 193948 kb
Host smart-ed74487d-637f-4fdc-a51c-7e23aaeacaff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455344184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.3455344184
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.1812931417
Short name T11
Test name
Test status
Simulation time 3803093157175 ps
CPU time 1821.54 seconds
Started Jul 26 04:48:00 PM PDT 24
Finished Jul 26 05:18:27 PM PDT 24
Peak memory 191564 kb
Host smart-2a6f76b3-ce2a-499f-9709-3ffaf129646b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812931417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.1812931417
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.3660679265
Short name T28
Test name
Test status
Simulation time 436187362588 ps
CPU time 2270.47 seconds
Started Jul 26 04:47:59 PM PDT 24
Finished Jul 26 05:25:49 PM PDT 24
Peak memory 191596 kb
Host smart-011cb62d-ffc4-4ac1-8f05-d63bd56cffce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660679265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.3660679265
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.3433449628
Short name T65
Test name
Test status
Simulation time 1131538722800 ps
CPU time 1776.39 seconds
Started Jul 26 04:47:55 PM PDT 24
Finished Jul 26 05:17:31 PM PDT 24
Peak memory 196416 kb
Host smart-ae987842-f3db-499e-8778-d984aebb4a00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433449628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
3433449628
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.394690184
Short name T235
Test name
Test status
Simulation time 572672277316 ps
CPU time 2728.77 seconds
Started Jul 26 04:48:05 PM PDT 24
Finished Jul 26 05:33:34 PM PDT 24
Peak memory 191568 kb
Host smart-7b62e65b-1841-4348-a8cc-1972195d4899
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394690184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all.
394690184
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.3266744949
Short name T178
Test name
Test status
Simulation time 972048802454 ps
CPU time 2457.22 seconds
Started Jul 26 04:48:01 PM PDT 24
Finished Jul 26 05:28:59 PM PDT 24
Peak memory 196232 kb
Host smart-64be1fab-735b-42ba-9fd3-3bfd56269afc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266744949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
3266744949
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.2614148083
Short name T211
Test name
Test status
Simulation time 1877961804160 ps
CPU time 1519.45 seconds
Started Jul 26 04:47:40 PM PDT 24
Finished Jul 26 05:13:00 PM PDT 24
Peak memory 191532 kb
Host smart-3c95b319-3d49-432e-8a91-8dd85d9bc9aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614148083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
2614148083
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.2878725305
Short name T48
Test name
Test status
Simulation time 477167592766 ps
CPU time 1545.32 seconds
Started Jul 26 04:48:04 PM PDT 24
Finished Jul 26 05:13:49 PM PDT 24
Peak memory 183428 kb
Host smart-3f85ba08-18ff-47db-9edd-21bff57f90a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878725305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.2878725305
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.2957746180
Short name T87
Test name
Test status
Simulation time 18043855 ps
CPU time 0.57 seconds
Started Jul 26 04:47:20 PM PDT 24
Finished Jul 26 04:47:21 PM PDT 24
Peak memory 182736 kb
Host smart-39de2912-70fa-4740-9c7a-2bcafc2753c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957746180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.2957746180
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.3640380067
Short name T207
Test name
Test status
Simulation time 675987295057 ps
CPU time 1597.98 seconds
Started Jul 26 04:47:48 PM PDT 24
Finished Jul 26 05:14:26 PM PDT 24
Peak memory 191592 kb
Host smart-e11661b9-26ae-41a4-b1e5-7087117c5948
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640380067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
3640380067
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.4011164656
Short name T204
Test name
Test status
Simulation time 2962961849541 ps
CPU time 2494.66 seconds
Started Jul 26 04:47:37 PM PDT 24
Finished Jul 26 05:29:12 PM PDT 24
Peak memory 191560 kb
Host smart-3212c5f3-7c78-4fbe-8d57-f3a244c8e014
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011164656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
4011164656
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.4155988077
Short name T209
Test name
Test status
Simulation time 2219571808937 ps
CPU time 3786.24 seconds
Started Jul 26 04:47:57 PM PDT 24
Finished Jul 26 05:51:04 PM PDT 24
Peak memory 191612 kb
Host smart-03dcd55d-65e5-4dff-9562-637fb3405cfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155988077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.4155988077
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.1178890160
Short name T16
Test name
Test status
Simulation time 141427180 ps
CPU time 1 seconds
Started Jul 26 04:47:40 PM PDT 24
Finished Jul 26 04:47:41 PM PDT 24
Peak memory 214828 kb
Host smart-1afd201e-fa4b-48c3-a957-3557151188f4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178890160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.1178890160
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.2479499797
Short name T78
Test name
Test status
Simulation time 533394409331 ps
CPU time 809.3 seconds
Started Jul 26 04:47:59 PM PDT 24
Finished Jul 26 05:01:29 PM PDT 24
Peak memory 195676 kb
Host smart-d33e221c-5f05-4e82-8b23-cc5fb887be96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479499797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.2479499797
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/189.rv_timer_random.4273493581
Short name T187
Test name
Test status
Simulation time 142539775655 ps
CPU time 324.03 seconds
Started Jul 26 04:48:34 PM PDT 24
Finished Jul 26 04:53:58 PM PDT 24
Peak memory 192536 kb
Host smart-ceb33202-a401-413f-a08a-b2352a8484cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273493581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.4273493581
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.1187985363
Short name T227
Test name
Test status
Simulation time 735665213293 ps
CPU time 1188.87 seconds
Started Jul 26 04:47:46 PM PDT 24
Finished Jul 26 05:07:35 PM PDT 24
Peak memory 191592 kb
Host smart-ab2a9e33-88c0-4525-9e36-a2d4fb271a9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187985363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.1187985363
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/95.rv_timer_random.2717551303
Short name T27
Test name
Test status
Simulation time 181292690082 ps
CPU time 318.91 seconds
Started Jul 26 04:48:18 PM PDT 24
Finished Jul 26 04:53:37 PM PDT 24
Peak memory 191540 kb
Host smart-bddd3fd9-1b13-4321-85ef-860af1b75459
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717551303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.2717551303
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.2096762100
Short name T166
Test name
Test status
Simulation time 740289022850 ps
CPU time 232.52 seconds
Started Jul 26 04:48:25 PM PDT 24
Finished Jul 26 04:52:18 PM PDT 24
Peak memory 191572 kb
Host smart-75b687f1-01c5-4974-be93-17736ec6799d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096762100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.2096762100
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random.2400389297
Short name T231
Test name
Test status
Simulation time 316750919706 ps
CPU time 659.24 seconds
Started Jul 26 04:47:40 PM PDT 24
Finished Jul 26 04:58:40 PM PDT 24
Peak memory 191608 kb
Host smart-63d1eaee-0577-4f96-b7b6-b2f6fcba3df9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400389297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.2400389297
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.2069810312
Short name T179
Test name
Test status
Simulation time 2351550985038 ps
CPU time 2480.14 seconds
Started Jul 26 04:47:28 PM PDT 24
Finished Jul 26 05:28:49 PM PDT 24
Peak memory 191564 kb
Host smart-77d74396-a546-4363-870a-acea5b60865d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069810312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
2069810312
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/146.rv_timer_random.3944715336
Short name T176
Test name
Test status
Simulation time 602401701111 ps
CPU time 497.22 seconds
Started Jul 26 04:48:05 PM PDT 24
Finished Jul 26 04:56:22 PM PDT 24
Peak memory 191552 kb
Host smart-7dfcd319-e279-4312-a3c9-8d74d6d37085
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944715336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.3944715336
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.2790049812
Short name T215
Test name
Test status
Simulation time 206050016875 ps
CPU time 368.54 seconds
Started Jul 26 04:48:28 PM PDT 24
Finished Jul 26 04:54:37 PM PDT 24
Peak memory 191564 kb
Host smart-743f9f4a-dacc-4d6a-851a-279d81f0af42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790049812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.2790049812
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.2775153162
Short name T10
Test name
Test status
Simulation time 510897645730 ps
CPU time 799.04 seconds
Started Jul 26 04:47:48 PM PDT 24
Finished Jul 26 05:01:07 PM PDT 24
Peak memory 183412 kb
Host smart-d3694200-330e-4d61-ba46-04f91d670b30
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775153162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.2775153162
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.4022654553
Short name T258
Test name
Test status
Simulation time 789481977599 ps
CPU time 1326.76 seconds
Started Jul 26 04:48:09 PM PDT 24
Finished Jul 26 05:10:16 PM PDT 24
Peak memory 191596 kb
Host smart-1f098464-f76e-4647-8cdb-a576675f2ddc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022654553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.4022654553
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/150.rv_timer_random.1832796382
Short name T456
Test name
Test status
Simulation time 267205035551 ps
CPU time 902.4 seconds
Started Jul 26 04:48:17 PM PDT 24
Finished Jul 26 05:03:20 PM PDT 24
Peak memory 191584 kb
Host smart-f1ad85e0-6fb3-40a9-809c-8f99528086d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832796382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.1832796382
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.1589950886
Short name T22
Test name
Test status
Simulation time 64056639792 ps
CPU time 277.5 seconds
Started Jul 26 04:48:19 PM PDT 24
Finished Jul 26 04:52:57 PM PDT 24
Peak memory 191536 kb
Host smart-df9d1fc0-e56d-4193-b128-1053bf8cf181
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589950886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.1589950886
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random.717835755
Short name T181
Test name
Test status
Simulation time 538427980791 ps
CPU time 737.85 seconds
Started Jul 26 04:47:44 PM PDT 24
Finished Jul 26 05:00:02 PM PDT 24
Peak memory 191604 kb
Host smart-9b193981-8f5d-46c2-b338-98f6a936a557
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717835755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.717835755
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.3464876474
Short name T67
Test name
Test status
Simulation time 2119996591534 ps
CPU time 898.34 seconds
Started Jul 26 04:47:45 PM PDT 24
Finished Jul 26 05:02:43 PM PDT 24
Peak memory 196092 kb
Host smart-6aad0a1a-d57c-4874-bf19-7fec5648c4d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464876474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
3464876474
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.1333344945
Short name T80
Test name
Test status
Simulation time 91632651334 ps
CPU time 524.82 seconds
Started Jul 26 04:47:51 PM PDT 24
Finished Jul 26 04:56:36 PM PDT 24
Peak memory 191552 kb
Host smart-53410a01-7675-4e3e-92e5-1c1f70a73d55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333344945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.1333344945
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/87.rv_timer_random.4116842366
Short name T149
Test name
Test status
Simulation time 671226369537 ps
CPU time 1300.39 seconds
Started Jul 26 04:48:07 PM PDT 24
Finished Jul 26 05:09:48 PM PDT 24
Peak memory 191576 kb
Host smart-8ed14a67-d949-4324-a6dd-c1b366c6a7fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116842366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.4116842366
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/100.rv_timer_random.94779970
Short name T329
Test name
Test status
Simulation time 268776071097 ps
CPU time 295 seconds
Started Jul 26 04:48:25 PM PDT 24
Finished Jul 26 04:53:20 PM PDT 24
Peak memory 191560 kb
Host smart-3f71cf51-eefc-4223-9636-79d6c45557fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94779970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.94779970
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.3945043963
Short name T268
Test name
Test status
Simulation time 259599824487 ps
CPU time 472.29 seconds
Started Jul 26 04:48:32 PM PDT 24
Finished Jul 26 04:56:24 PM PDT 24
Peak memory 194928 kb
Host smart-dd5dd5ec-2b18-4d8b-ad27-f24b7b945a7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945043963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.3945043963
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.2143864113
Short name T130
Test name
Test status
Simulation time 409587823498 ps
CPU time 213.91 seconds
Started Jul 26 04:47:58 PM PDT 24
Finished Jul 26 04:51:32 PM PDT 24
Peak memory 183380 kb
Host smart-6b916f24-dbec-4492-9247-cc145adab7d2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143864113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.2143864113
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.4241482143
Short name T279
Test name
Test status
Simulation time 47857488389 ps
CPU time 78.38 seconds
Started Jul 26 04:47:47 PM PDT 24
Finished Jul 26 04:49:06 PM PDT 24
Peak memory 183296 kb
Host smart-363647a4-6765-4135-b6b9-4aa42f4ad821
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241482143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.4241482143
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/184.rv_timer_random.3914404038
Short name T188
Test name
Test status
Simulation time 404308268146 ps
CPU time 680.47 seconds
Started Jul 26 04:48:12 PM PDT 24
Finished Jul 26 04:59:37 PM PDT 24
Peak memory 191576 kb
Host smart-b883bc61-e3f3-43a4-b026-d86e5fb86e5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914404038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.3914404038
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.3961632054
Short name T69
Test name
Test status
Simulation time 2359218850735 ps
CPU time 914.71 seconds
Started Jul 26 04:47:54 PM PDT 24
Finished Jul 26 05:03:09 PM PDT 24
Peak memory 191516 kb
Host smart-ddba7b49-032c-4fa3-8a43-82fd4999f210
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961632054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.3961632054
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.3964376921
Short name T213
Test name
Test status
Simulation time 198009214462 ps
CPU time 183.28 seconds
Started Jul 26 04:48:01 PM PDT 24
Finished Jul 26 04:51:04 PM PDT 24
Peak memory 183384 kb
Host smart-7b83c56d-c6dd-43cb-a6b8-ccc44e57e24a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964376921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.3964376921
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/103.rv_timer_random.3607601786
Short name T172
Test name
Test status
Simulation time 106824687171 ps
CPU time 339.88 seconds
Started Jul 26 04:48:03 PM PDT 24
Finished Jul 26 04:53:43 PM PDT 24
Peak memory 193328 kb
Host smart-d043ae83-3fb0-4f23-801e-b33a06d39f23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607601786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.3607601786
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.2230212584
Short name T220
Test name
Test status
Simulation time 275135665072 ps
CPU time 167.75 seconds
Started Jul 26 04:47:55 PM PDT 24
Finished Jul 26 04:50:43 PM PDT 24
Peak memory 183412 kb
Host smart-c41e2903-89fa-46a2-95d7-e17b809e1664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230212584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.2230212584
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/122.rv_timer_random.3605352440
Short name T117
Test name
Test status
Simulation time 121512503037 ps
CPU time 585.67 seconds
Started Jul 26 04:48:26 PM PDT 24
Finished Jul 26 04:58:11 PM PDT 24
Peak memory 191512 kb
Host smart-a6f0f20b-82e8-4d1b-aebb-0776e2856f14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605352440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.3605352440
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.3168213939
Short name T185
Test name
Test status
Simulation time 34669083272 ps
CPU time 60.89 seconds
Started Jul 26 04:48:13 PM PDT 24
Finished Jul 26 04:49:14 PM PDT 24
Peak memory 191560 kb
Host smart-ad0ce00d-add1-473b-89fb-b7eba6f4ab1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168213939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.3168213939
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.1517086637
Short name T9
Test name
Test status
Simulation time 75832915619 ps
CPU time 253.47 seconds
Started Jul 26 04:48:12 PM PDT 24
Finished Jul 26 04:52:25 PM PDT 24
Peak memory 191616 kb
Host smart-a9571937-e6ae-4163-8777-984a75cbe2fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517086637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.1517086637
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.3681988879
Short name T164
Test name
Test status
Simulation time 145905962362 ps
CPU time 507.17 seconds
Started Jul 26 04:48:08 PM PDT 24
Finished Jul 26 04:56:35 PM PDT 24
Peak memory 191548 kb
Host smart-3a59a676-7f12-4906-ac55-78b96ef63dc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681988879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.3681988879
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.2180397997
Short name T348
Test name
Test status
Simulation time 307018769622 ps
CPU time 1467.22 seconds
Started Jul 26 04:48:22 PM PDT 24
Finished Jul 26 05:12:49 PM PDT 24
Peak memory 191576 kb
Host smart-f1b73d06-8340-4c9f-9fe2-9e0546d26b11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180397997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.2180397997
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.647326325
Short name T167
Test name
Test status
Simulation time 464192441735 ps
CPU time 2245.26 seconds
Started Jul 26 04:48:00 PM PDT 24
Finished Jul 26 05:25:25 PM PDT 24
Peak memory 191620 kb
Host smart-d2dd53f9-1a71-46ee-8ce5-3335327a9599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647326325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.647326325
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.4101273973
Short name T248
Test name
Test status
Simulation time 718078715171 ps
CPU time 558.11 seconds
Started Jul 26 04:48:00 PM PDT 24
Finished Jul 26 04:57:18 PM PDT 24
Peak memory 196076 kb
Host smart-f0a65174-2cc1-4740-9773-5c1c21fd5cb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101273973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.4101273973
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.4168037242
Short name T169
Test name
Test status
Simulation time 248495842480 ps
CPU time 605.08 seconds
Started Jul 26 04:48:14 PM PDT 24
Finished Jul 26 04:58:19 PM PDT 24
Peak memory 191572 kb
Host smart-63475f99-8270-4b66-954f-9f3c898e04c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168037242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.4168037242
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/56.rv_timer_random.2766699277
Short name T232
Test name
Test status
Simulation time 103000200086 ps
CPU time 231.09 seconds
Started Jul 26 04:48:01 PM PDT 24
Finished Jul 26 04:51:52 PM PDT 24
Peak memory 194712 kb
Host smart-25ed611e-b7eb-47fd-8475-cff2ca37ec23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766699277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.2766699277
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.2903726013
Short name T100
Test name
Test status
Simulation time 21359702 ps
CPU time 0.66 seconds
Started Jul 26 04:47:13 PM PDT 24
Finished Jul 26 04:47:13 PM PDT 24
Peak memory 192228 kb
Host smart-de3975f3-1521-4489-9eb4-41cffddc907f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903726013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.2903726013
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1510156944
Short name T110
Test name
Test status
Simulation time 163597994 ps
CPU time 1.27 seconds
Started Jul 26 04:47:28 PM PDT 24
Finished Jul 26 04:47:29 PM PDT 24
Peak memory 195220 kb
Host smart-7c0aad54-3d77-40c6-b3ad-de391af3eb21
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510156944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.1510156944
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.4078753194
Short name T49
Test name
Test status
Simulation time 341159405986 ps
CPU time 161.3 seconds
Started Jul 26 04:47:37 PM PDT 24
Finished Jul 26 04:50:18 PM PDT 24
Peak memory 191528 kb
Host smart-b231bf62-6885-4218-a4b2-9001fdcdf518
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078753194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
4078753194
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/108.rv_timer_random.1171077634
Short name T173
Test name
Test status
Simulation time 1222120678989 ps
CPU time 556.64 seconds
Started Jul 26 04:48:42 PM PDT 24
Finished Jul 26 04:57:59 PM PDT 24
Peak memory 194216 kb
Host smart-40be903a-b12a-4332-9a9d-33776d2e0ebc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171077634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.1171077634
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.21711422
Short name T226
Test name
Test status
Simulation time 278527508451 ps
CPU time 1230.84 seconds
Started Jul 26 04:48:09 PM PDT 24
Finished Jul 26 05:08:40 PM PDT 24
Peak memory 191528 kb
Host smart-5e1b1932-bc3a-413d-a1e7-0a9fb5b0861c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21711422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.21711422
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.1065154115
Short name T324
Test name
Test status
Simulation time 536410076053 ps
CPU time 236.3 seconds
Started Jul 26 04:48:32 PM PDT 24
Finished Jul 26 04:52:28 PM PDT 24
Peak memory 193772 kb
Host smart-0f7853ab-d2c6-4e81-8e85-d13d0ac47405
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065154115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.1065154115
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/140.rv_timer_random.1141788162
Short name T194
Test name
Test status
Simulation time 179295503155 ps
CPU time 873.32 seconds
Started Jul 26 04:48:08 PM PDT 24
Finished Jul 26 05:02:42 PM PDT 24
Peak memory 191636 kb
Host smart-6b845303-f286-46be-823a-cb3714ff1213
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141788162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.1141788162
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random.765014934
Short name T152
Test name
Test status
Simulation time 884106765533 ps
CPU time 401.58 seconds
Started Jul 26 04:47:41 PM PDT 24
Finished Jul 26 04:54:23 PM PDT 24
Peak memory 191600 kb
Host smart-742d624b-8462-4dcb-bf25-997cf308a768
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765014934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.765014934
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.2809640298
Short name T190
Test name
Test status
Simulation time 403543744651 ps
CPU time 192.72 seconds
Started Jul 26 04:48:31 PM PDT 24
Finished Jul 26 04:51:44 PM PDT 24
Peak memory 191580 kb
Host smart-c780f5a1-3b23-4228-b160-1ffe9e477ee0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809640298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.2809640298
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.4163728602
Short name T283
Test name
Test status
Simulation time 53620937087 ps
CPU time 190.83 seconds
Started Jul 26 04:48:30 PM PDT 24
Finished Jul 26 04:51:41 PM PDT 24
Peak memory 191536 kb
Host smart-8dd08f31-83cd-40d6-b1ec-5ef4b56fbe31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163728602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.4163728602
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.3498031159
Short name T138
Test name
Test status
Simulation time 312299632196 ps
CPU time 740.54 seconds
Started Jul 26 04:48:11 PM PDT 24
Finished Jul 26 05:00:32 PM PDT 24
Peak memory 191576 kb
Host smart-a2df6d8c-6efe-4ad9-9eda-04bcdbb4650c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498031159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.3498031159
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_random.3167916649
Short name T151
Test name
Test status
Simulation time 161323913603 ps
CPU time 296.88 seconds
Started Jul 26 04:48:03 PM PDT 24
Finished Jul 26 04:53:00 PM PDT 24
Peak memory 191544 kb
Host smart-b0ce8d4b-3e8c-4dc9-829d-c7941ca9dc34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167916649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.3167916649
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.731901650
Short name T115
Test name
Test status
Simulation time 253296905153 ps
CPU time 405.74 seconds
Started Jul 26 04:48:04 PM PDT 24
Finished Jul 26 04:54:50 PM PDT 24
Peak memory 183368 kb
Host smart-92d3d8d9-129f-464f-a0e0-047a905fa911
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731901650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.rv_timer_cfg_update_on_fly.731901650
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.4252872563
Short name T250
Test name
Test status
Simulation time 47418712602 ps
CPU time 78.83 seconds
Started Jul 26 04:47:41 PM PDT 24
Finished Jul 26 04:49:00 PM PDT 24
Peak memory 183356 kb
Host smart-5295ab93-876b-491c-a35f-910e303e72a6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252872563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.4252872563
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.1308279036
Short name T447
Test name
Test status
Simulation time 836294541674 ps
CPU time 272.32 seconds
Started Jul 26 04:48:00 PM PDT 24
Finished Jul 26 04:52:32 PM PDT 24
Peak memory 191696 kb
Host smart-d1c87499-67f2-4fa6-a41b-38022255d8ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308279036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.1308279036
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/50.rv_timer_random.1055905068
Short name T323
Test name
Test status
Simulation time 221013755201 ps
CPU time 96.66 seconds
Started Jul 26 04:48:15 PM PDT 24
Finished Jul 26 04:49:52 PM PDT 24
Peak memory 191520 kb
Host smart-7927b627-5745-4ccb-b26f-c8663fa73cdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055905068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.1055905068
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.126847782
Short name T124
Test name
Test status
Simulation time 729099863915 ps
CPU time 1615.1 seconds
Started Jul 26 04:48:09 PM PDT 24
Finished Jul 26 05:15:05 PM PDT 24
Peak memory 191548 kb
Host smart-13518faf-0994-4458-8dec-194450ea4938
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126847782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.126847782
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.445045594
Short name T216
Test name
Test status
Simulation time 521697336174 ps
CPU time 266.37 seconds
Started Jul 26 04:48:01 PM PDT 24
Finished Jul 26 04:52:28 PM PDT 24
Peak memory 183384 kb
Host smart-1788c333-318a-4635-a36b-d77e446e2af2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445045594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.rv_timer_cfg_update_on_fly.445045594
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/106.rv_timer_random.3111896695
Short name T267
Test name
Test status
Simulation time 7633966808 ps
CPU time 10.77 seconds
Started Jul 26 04:48:09 PM PDT 24
Finished Jul 26 04:48:20 PM PDT 24
Peak memory 183316 kb
Host smart-2f28f188-457a-479c-9c7a-c723619a6ac2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111896695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.3111896695
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.3479807689
Short name T193
Test name
Test status
Simulation time 417357917730 ps
CPU time 601.76 seconds
Started Jul 26 04:47:49 PM PDT 24
Finished Jul 26 04:57:51 PM PDT 24
Peak memory 183308 kb
Host smart-5c4f3eed-4d0c-47b6-83f7-7b03a21b0d59
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479807689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.3479807689
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/110.rv_timer_random.3989790674
Short name T245
Test name
Test status
Simulation time 91327477702 ps
CPU time 129.89 seconds
Started Jul 26 04:48:18 PM PDT 24
Finished Jul 26 04:50:28 PM PDT 24
Peak memory 191452 kb
Host smart-27cf5e52-a6d1-4c31-84ad-2ca118c933b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989790674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.3989790674
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.3051815887
Short name T327
Test name
Test status
Simulation time 216578751161 ps
CPU time 282.34 seconds
Started Jul 26 04:48:16 PM PDT 24
Finished Jul 26 04:52:59 PM PDT 24
Peak memory 191528 kb
Host smart-1ce6e31e-ffcb-4620-98d1-ca18da42cf66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051815887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.3051815887
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.703825999
Short name T125
Test name
Test status
Simulation time 67911573170 ps
CPU time 119.68 seconds
Started Jul 26 04:48:09 PM PDT 24
Finished Jul 26 04:50:09 PM PDT 24
Peak memory 191528 kb
Host smart-66d88e50-9e3e-40cc-a381-913af9c65db5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703825999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.703825999
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.186783017
Short name T57
Test name
Test status
Simulation time 152673880461 ps
CPU time 61.23 seconds
Started Jul 26 04:47:59 PM PDT 24
Finished Jul 26 04:49:00 PM PDT 24
Peak memory 183384 kb
Host smart-956870ed-a13d-4e97-8b54-19574186128a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186783017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.186783017
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.1004436349
Short name T192
Test name
Test status
Simulation time 211383616185 ps
CPU time 324.03 seconds
Started Jul 26 04:47:56 PM PDT 24
Finished Jul 26 04:53:21 PM PDT 24
Peak memory 183316 kb
Host smart-dfebdea4-4a1d-4d73-af6c-8b10a9c64834
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004436349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.1004436349
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/132.rv_timer_random.3037937888
Short name T307
Test name
Test status
Simulation time 96169295026 ps
CPU time 1627.49 seconds
Started Jul 26 04:48:19 PM PDT 24
Finished Jul 26 05:15:27 PM PDT 24
Peak memory 191584 kb
Host smart-9b3dea9f-d50e-4533-8ae8-9cac33434477
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037937888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.3037937888
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.2121089238
Short name T47
Test name
Test status
Simulation time 327917353557 ps
CPU time 141.9 seconds
Started Jul 26 04:48:12 PM PDT 24
Finished Jul 26 04:50:34 PM PDT 24
Peak memory 191624 kb
Host smart-2a12f6bf-23cf-437d-859d-b587904fe451
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121089238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.2121089238
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.1336106133
Short name T24
Test name
Test status
Simulation time 464614214404 ps
CPU time 346.13 seconds
Started Jul 26 04:48:06 PM PDT 24
Finished Jul 26 04:53:57 PM PDT 24
Peak memory 191544 kb
Host smart-4be10c33-a86b-45ce-a34b-821e0e21a55c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336106133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.1336106133
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.3054859896
Short name T254
Test name
Test status
Simulation time 40253045762 ps
CPU time 37.73 seconds
Started Jul 26 04:48:27 PM PDT 24
Finished Jul 26 04:49:05 PM PDT 24
Peak memory 183360 kb
Host smart-996a61e8-882d-44e1-aee5-e6b75ca7e039
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054859896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.3054859896
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.3144490361
Short name T174
Test name
Test status
Simulation time 29052458202 ps
CPU time 39.5 seconds
Started Jul 26 04:48:30 PM PDT 24
Finished Jul 26 04:49:10 PM PDT 24
Peak memory 183220 kb
Host smart-c5ae1635-b5f8-4450-b0ad-6701597ae63d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144490361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.3144490361
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.1223687217
Short name T333
Test name
Test status
Simulation time 35913660758 ps
CPU time 46.54 seconds
Started Jul 26 04:48:29 PM PDT 24
Finished Jul 26 04:49:16 PM PDT 24
Peak memory 183208 kb
Host smart-ff2390a4-9364-4ac2-95a4-6c341791e70e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223687217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.1223687217
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.827093984
Short name T259
Test name
Test status
Simulation time 317091280043 ps
CPU time 797.25 seconds
Started Jul 26 04:48:26 PM PDT 24
Finished Jul 26 05:01:44 PM PDT 24
Peak memory 191584 kb
Host smart-033c6d0b-823f-4da6-a826-1e044c8b8bed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827093984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.827093984
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.2943065756
Short name T222
Test name
Test status
Simulation time 1043389976061 ps
CPU time 418.58 seconds
Started Jul 26 04:48:26 PM PDT 24
Finished Jul 26 04:55:25 PM PDT 24
Peak memory 191544 kb
Host smart-80e7a61c-cb28-49bf-81d2-9e69724a11d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943065756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.2943065756
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.25736848
Short name T273
Test name
Test status
Simulation time 383780614423 ps
CPU time 373.34 seconds
Started Jul 26 04:48:27 PM PDT 24
Finished Jul 26 04:54:40 PM PDT 24
Peak memory 194184 kb
Host smart-b9cf9686-acc9-4bb3-8a97-36df8b0a74a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25736848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.25736848
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.138543467
Short name T70
Test name
Test status
Simulation time 101687770711 ps
CPU time 472.51 seconds
Started Jul 26 04:48:33 PM PDT 24
Finished Jul 26 04:56:26 PM PDT 24
Peak memory 191584 kb
Host smart-55e8a327-9ef6-4329-ac31-d8acddb7f754
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138543467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.138543467
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.1979924186
Short name T314
Test name
Test status
Simulation time 117142655716 ps
CPU time 845.83 seconds
Started Jul 26 04:48:26 PM PDT 24
Finished Jul 26 05:02:32 PM PDT 24
Peak memory 191600 kb
Host smart-f992a43f-6540-473c-b9bf-19596e7cfeea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979924186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.1979924186
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.2030074100
Short name T143
Test name
Test status
Simulation time 174813994406 ps
CPU time 160.85 seconds
Started Jul 26 04:48:02 PM PDT 24
Finished Jul 26 04:50:43 PM PDT 24
Peak memory 183376 kb
Host smart-ca92e07a-e4f9-42a9-b9c4-c62b0bb67f14
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030074100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.2030074100
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.3376808434
Short name T196
Test name
Test status
Simulation time 51100847852 ps
CPU time 75.16 seconds
Started Jul 26 04:48:04 PM PDT 24
Finished Jul 26 04:49:19 PM PDT 24
Peak memory 183388 kb
Host smart-19e510e2-7fa7-4656-925b-cb77b8eb5bd8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376808434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.3376808434
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.2215457029
Short name T304
Test name
Test status
Simulation time 55924558682 ps
CPU time 430.7 seconds
Started Jul 26 04:47:50 PM PDT 24
Finished Jul 26 04:55:00 PM PDT 24
Peak memory 183408 kb
Host smart-d0ce4eae-6ef1-45ca-a654-0be2fdbf24f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215457029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.2215457029
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.3520921641
Short name T358
Test name
Test status
Simulation time 169998999388 ps
CPU time 1011.75 seconds
Started Jul 26 04:48:27 PM PDT 24
Finished Jul 26 05:05:19 PM PDT 24
Peak memory 183404 kb
Host smart-5592bf25-8f13-43eb-b134-9ff95a6d1b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520921641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.3520921641
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/78.rv_timer_random.1491949999
Short name T214
Test name
Test status
Simulation time 319862439438 ps
CPU time 263.03 seconds
Started Jul 26 04:48:16 PM PDT 24
Finished Jul 26 04:52:39 PM PDT 24
Peak memory 191592 kb
Host smart-9dfedf20-9572-4776-8228-8e515bbbd706
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491949999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.1491949999
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/80.rv_timer_random.3825564464
Short name T337
Test name
Test status
Simulation time 827445318689 ps
CPU time 3101.85 seconds
Started Jul 26 04:48:18 PM PDT 24
Finished Jul 26 05:40:00 PM PDT 24
Peak memory 191576 kb
Host smart-392ea860-7e3c-4129-bf7b-15cc470f585d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825564464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.3825564464
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.1095336386
Short name T355
Test name
Test status
Simulation time 158108094448 ps
CPU time 126.91 seconds
Started Jul 26 04:48:06 PM PDT 24
Finished Jul 26 04:50:13 PM PDT 24
Peak memory 191564 kb
Host smart-0d0abedc-a624-4c5b-8e01-8b1b2da3fddd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095336386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.1095336386
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3940635525
Short name T54
Test name
Test status
Simulation time 62471903 ps
CPU time 0.6 seconds
Started Jul 26 04:47:22 PM PDT 24
Finished Jul 26 04:47:23 PM PDT 24
Peak memory 182784 kb
Host smart-1626a5b8-072f-4ba5-a9b3-757f14dfd02a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940635525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.3940635525
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.1395450292
Short name T538
Test name
Test status
Simulation time 127656562 ps
CPU time 1.4 seconds
Started Jul 26 04:47:27 PM PDT 24
Finished Jul 26 04:47:29 PM PDT 24
Peak memory 192740 kb
Host smart-b83354a2-1dd0-428d-a4c6-9d498f0fb459
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395450292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.1395450292
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.807532342
Short name T491
Test name
Test status
Simulation time 12733880 ps
CPU time 0.55 seconds
Started Jul 26 04:47:21 PM PDT 24
Finished Jul 26 04:47:22 PM PDT 24
Peak memory 182756 kb
Host smart-c122dec9-a9fb-49f5-bc15-bd3925025030
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807532342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_re
set.807532342
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.259765508
Short name T476
Test name
Test status
Simulation time 442433479 ps
CPU time 1.51 seconds
Started Jul 26 04:47:22 PM PDT 24
Finished Jul 26 04:47:24 PM PDT 24
Peak memory 197588 kb
Host smart-cfab895f-9af0-475e-8ed4-5106e03743a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259765508 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.259765508
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.63880248
Short name T88
Test name
Test status
Simulation time 19256648 ps
CPU time 0.56 seconds
Started Jul 26 04:47:24 PM PDT 24
Finished Jul 26 04:47:25 PM PDT 24
Peak memory 182712 kb
Host smart-13a4ceb7-344a-4f81-9724-a9a0071d3d21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63880248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.63880248
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.1197623879
Short name T547
Test name
Test status
Simulation time 46445284 ps
CPU time 0.55 seconds
Started Jul 26 04:47:22 PM PDT 24
Finished Jul 26 04:47:23 PM PDT 24
Peak memory 182708 kb
Host smart-ca8db0d0-fde4-4c7f-a9ef-e2c6db6f3b11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197623879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.1197623879
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.1541780315
Short name T518
Test name
Test status
Simulation time 50721121 ps
CPU time 2.09 seconds
Started Jul 26 04:47:11 PM PDT 24
Finished Jul 26 04:47:14 PM PDT 24
Peak memory 197492 kb
Host smart-653cae5b-f4ff-4f74-ae2d-1009c0056687
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541780315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.1541780315
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.4043285315
Short name T113
Test name
Test status
Simulation time 423038505 ps
CPU time 1.31 seconds
Started Jul 26 04:47:14 PM PDT 24
Finished Jul 26 04:47:15 PM PDT 24
Peak memory 183144 kb
Host smart-440bec7e-1f55-49a9-a7eb-c2dcbdb8951a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043285315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.4043285315
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.3238474800
Short name T85
Test name
Test status
Simulation time 34511324 ps
CPU time 0.79 seconds
Started Jul 26 04:47:17 PM PDT 24
Finished Jul 26 04:47:18 PM PDT 24
Peak memory 191976 kb
Host smart-f13dfac2-0497-43a4-8544-1f88d122f942
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238474800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.3238474800
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.3862472301
Short name T571
Test name
Test status
Simulation time 174088763 ps
CPU time 3.15 seconds
Started Jul 26 04:47:11 PM PDT 24
Finished Jul 26 04:47:14 PM PDT 24
Peak memory 191068 kb
Host smart-e58f06f9-2918-4fe0-83bc-204cf6912b33
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862472301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.3862472301
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.290971823
Short name T92
Test name
Test status
Simulation time 43198569 ps
CPU time 0.6 seconds
Started Jul 26 04:47:17 PM PDT 24
Finished Jul 26 04:47:18 PM PDT 24
Peak memory 182788 kb
Host smart-d020c5ba-9b4f-4d9e-b56d-d0bc413fb82e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290971823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_re
set.290971823
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.4046702416
Short name T574
Test name
Test status
Simulation time 54960070 ps
CPU time 0.79 seconds
Started Jul 26 04:47:15 PM PDT 24
Finished Jul 26 04:47:16 PM PDT 24
Peak memory 195860 kb
Host smart-92ff7e2c-71b1-4288-a168-92a59b623859
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046702416 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.4046702416
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.1959953835
Short name T90
Test name
Test status
Simulation time 14643363 ps
CPU time 0.59 seconds
Started Jul 26 04:47:16 PM PDT 24
Finished Jul 26 04:47:17 PM PDT 24
Peak memory 182764 kb
Host smart-e9e5ec52-cdee-4fbf-a867-92c57cda85f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959953835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.1959953835
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.2451553655
Short name T469
Test name
Test status
Simulation time 14572174 ps
CPU time 0.54 seconds
Started Jul 26 04:47:14 PM PDT 24
Finished Jul 26 04:47:15 PM PDT 24
Peak memory 182684 kb
Host smart-d00a3ef2-024b-4f89-a167-635ca62b3070
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451553655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.2451553655
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.112354988
Short name T541
Test name
Test status
Simulation time 37161433 ps
CPU time 0.81 seconds
Started Jul 26 04:47:17 PM PDT 24
Finished Jul 26 04:47:18 PM PDT 24
Peak memory 194060 kb
Host smart-33885ff8-911c-4b07-aea7-3229a3cff74b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112354988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_tim
er_same_csr_outstanding.112354988
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.961155283
Short name T530
Test name
Test status
Simulation time 78036659 ps
CPU time 1.62 seconds
Started Jul 26 04:47:16 PM PDT 24
Finished Jul 26 04:47:18 PM PDT 24
Peak memory 197528 kb
Host smart-41ba849b-8c8f-4b1a-9862-7a2eeb393873
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961155283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.961155283
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.626174595
Short name T497
Test name
Test status
Simulation time 171199077 ps
CPU time 0.96 seconds
Started Jul 26 04:47:18 PM PDT 24
Finished Jul 26 04:47:19 PM PDT 24
Peak memory 183188 kb
Host smart-1b44cb96-0bbb-490e-bd95-c59d02dc1b77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626174595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_int
g_err.626174595
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.590832189
Short name T53
Test name
Test status
Simulation time 44723000 ps
CPU time 0.61 seconds
Started Jul 26 04:47:23 PM PDT 24
Finished Jul 26 04:47:23 PM PDT 24
Peak memory 193832 kb
Host smart-b572ec99-ef99-4863-a73f-7545f89dd26a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590832189 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.590832189
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.3031958033
Short name T565
Test name
Test status
Simulation time 55114358 ps
CPU time 0.6 seconds
Started Jul 26 04:47:37 PM PDT 24
Finished Jul 26 04:47:38 PM PDT 24
Peak memory 182764 kb
Host smart-6a8d7615-83c0-4b32-ba63-a724c1ba4fb8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031958033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.3031958033
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.972685352
Short name T464
Test name
Test status
Simulation time 62012917 ps
CPU time 0.55 seconds
Started Jul 26 04:47:44 PM PDT 24
Finished Jul 26 04:47:45 PM PDT 24
Peak memory 182592 kb
Host smart-91d7ac11-945f-4061-83ee-34cdcb4f671a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972685352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.972685352
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.3643460929
Short name T101
Test name
Test status
Simulation time 19518093 ps
CPU time 0.77 seconds
Started Jul 26 04:47:32 PM PDT 24
Finished Jul 26 04:47:33 PM PDT 24
Peak memory 193368 kb
Host smart-329b118d-2b36-4f53-8034-3c22651571b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643460929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.3643460929
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.3190216960
Short name T548
Test name
Test status
Simulation time 253554304 ps
CPU time 2.08 seconds
Started Jul 26 04:47:26 PM PDT 24
Finished Jul 26 04:47:28 PM PDT 24
Peak memory 197360 kb
Host smart-5597cbcd-81b8-46e2-a0f3-f0eb6985fe0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190216960 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.3190216960
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1236185271
Short name T533
Test name
Test status
Simulation time 150347693 ps
CPU time 0.81 seconds
Started Jul 26 04:47:56 PM PDT 24
Finished Jul 26 04:47:57 PM PDT 24
Peak memory 193508 kb
Host smart-8baca652-04b8-4633-b3c8-415f50bfab7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236185271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.1236185271
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.2558533762
Short name T467
Test name
Test status
Simulation time 18268588 ps
CPU time 0.72 seconds
Started Jul 26 04:47:17 PM PDT 24
Finished Jul 26 04:47:18 PM PDT 24
Peak memory 195428 kb
Host smart-102bc1d3-efd3-4969-aa9c-b96c85f2487d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558533762 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.2558533762
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.3202531976
Short name T529
Test name
Test status
Simulation time 11610316 ps
CPU time 0.59 seconds
Started Jul 26 04:47:30 PM PDT 24
Finished Jul 26 04:47:30 PM PDT 24
Peak memory 182756 kb
Host smart-8a2c8cff-7697-40d4-b043-555bbe778520
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202531976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.3202531976
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.83772739
Short name T473
Test name
Test status
Simulation time 17768758 ps
CPU time 0.57 seconds
Started Jul 26 04:47:43 PM PDT 24
Finished Jul 26 04:47:49 PM PDT 24
Peak memory 183076 kb
Host smart-8efc0008-97c0-48a8-95fa-9f66541e59bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83772739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.83772739
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.259000171
Short name T534
Test name
Test status
Simulation time 41189934 ps
CPU time 0.81 seconds
Started Jul 26 04:47:36 PM PDT 24
Finished Jul 26 04:47:42 PM PDT 24
Peak memory 191748 kb
Host smart-1a4cf2df-9df3-425c-8768-82cfd17a9d18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259000171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_ti
mer_same_csr_outstanding.259000171
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.1156735038
Short name T566
Test name
Test status
Simulation time 126059404 ps
CPU time 2.28 seconds
Started Jul 26 04:47:28 PM PDT 24
Finished Jul 26 04:47:30 PM PDT 24
Peak memory 197504 kb
Host smart-694e1dd7-7704-4023-b7bc-e1b6cca4c477
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156735038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.1156735038
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3632874926
Short name T520
Test name
Test status
Simulation time 338917169 ps
CPU time 1.08 seconds
Started Jul 26 04:47:23 PM PDT 24
Finished Jul 26 04:47:30 PM PDT 24
Peak memory 194992 kb
Host smart-4ac38115-a962-42e8-9936-21e5d1d55253
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632874926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.3632874926
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.569436127
Short name T567
Test name
Test status
Simulation time 343141446 ps
CPU time 1.14 seconds
Started Jul 26 04:47:39 PM PDT 24
Finished Jul 26 04:47:40 PM PDT 24
Peak memory 197344 kb
Host smart-276b8f5f-8179-40d4-991a-636de82a500d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569436127 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.569436127
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.495175904
Short name T527
Test name
Test status
Simulation time 20236161 ps
CPU time 0.55 seconds
Started Jul 26 04:47:15 PM PDT 24
Finished Jul 26 04:47:16 PM PDT 24
Peak memory 182760 kb
Host smart-6ea55d00-ff5d-4e86-b5c4-fdf89fa33d6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495175904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.495175904
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.4229474466
Short name T480
Test name
Test status
Simulation time 17374180 ps
CPU time 0.53 seconds
Started Jul 26 04:47:32 PM PDT 24
Finished Jul 26 04:47:32 PM PDT 24
Peak memory 182084 kb
Host smart-b8d34ef1-281a-4af1-9295-404bb3ed37c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229474466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.4229474466
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1184335812
Short name T546
Test name
Test status
Simulation time 66751328 ps
CPU time 0.63 seconds
Started Jul 26 04:47:35 PM PDT 24
Finished Jul 26 04:47:36 PM PDT 24
Peak memory 192012 kb
Host smart-b3812372-92cb-4d72-87f8-73841c2c144a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184335812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.1184335812
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.3781354265
Short name T542
Test name
Test status
Simulation time 82699986 ps
CPU time 0.93 seconds
Started Jul 26 04:47:33 PM PDT 24
Finished Jul 26 04:47:34 PM PDT 24
Peak memory 196224 kb
Host smart-515dfaba-7ad2-4886-ad9d-3e2245a10b88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781354265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.3781354265
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.3974312839
Short name T503
Test name
Test status
Simulation time 48918160 ps
CPU time 0.81 seconds
Started Jul 26 04:47:32 PM PDT 24
Finished Jul 26 04:47:33 PM PDT 24
Peak memory 183136 kb
Host smart-f4e592e7-dde7-4c9f-a655-5e0e5d702a88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974312839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.3974312839
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.665602258
Short name T509
Test name
Test status
Simulation time 23031768 ps
CPU time 1.04 seconds
Started Jul 26 04:47:38 PM PDT 24
Finished Jul 26 04:47:39 PM PDT 24
Peak memory 197420 kb
Host smart-5634a753-664f-46e8-8c83-d88c9d8178ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665602258 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.665602258
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.4249924609
Short name T519
Test name
Test status
Simulation time 31710786 ps
CPU time 0.58 seconds
Started Jul 26 04:47:33 PM PDT 24
Finished Jul 26 04:47:33 PM PDT 24
Peak memory 182764 kb
Host smart-7d206617-f8d8-4bf5-9d1a-35146bc064b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249924609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.4249924609
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.1680507534
Short name T573
Test name
Test status
Simulation time 37971833 ps
CPU time 0.53 seconds
Started Jul 26 04:47:31 PM PDT 24
Finished Jul 26 04:47:32 PM PDT 24
Peak memory 182676 kb
Host smart-7a7b1f13-9f13-4df6-8c25-e9e42ab5bc61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680507534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.1680507534
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1316713720
Short name T102
Test name
Test status
Simulation time 116771130 ps
CPU time 0.71 seconds
Started Jul 26 04:47:31 PM PDT 24
Finished Jul 26 04:47:32 PM PDT 24
Peak memory 191736 kb
Host smart-a4886aec-0a5a-4b43-a4df-97ab88599254
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316713720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.1316713720
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.3948214917
Short name T486
Test name
Test status
Simulation time 235543404 ps
CPU time 2.17 seconds
Started Jul 26 04:47:45 PM PDT 24
Finished Jul 26 04:47:47 PM PDT 24
Peak memory 197500 kb
Host smart-ec91f6f5-28d2-4e79-bafa-af05deeb6955
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948214917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.3948214917
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.417593304
Short name T550
Test name
Test status
Simulation time 28133911 ps
CPU time 0.61 seconds
Started Jul 26 04:47:25 PM PDT 24
Finished Jul 26 04:47:26 PM PDT 24
Peak memory 193320 kb
Host smart-f83bd89c-ec28-4f3e-a23b-66e395da5a1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417593304 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.417593304
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.2392197297
Short name T95
Test name
Test status
Simulation time 14857856 ps
CPU time 0.55 seconds
Started Jul 26 04:47:31 PM PDT 24
Finished Jul 26 04:47:31 PM PDT 24
Peak memory 182788 kb
Host smart-11911dd5-667c-4f11-b6d9-5cfc6ae52faa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392197297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.2392197297
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.3877118293
Short name T498
Test name
Test status
Simulation time 186717694 ps
CPU time 0.52 seconds
Started Jul 26 04:47:10 PM PDT 24
Finished Jul 26 04:47:11 PM PDT 24
Peak memory 182084 kb
Host smart-07d15533-e744-498f-9636-237f43fd2f1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877118293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.3877118293
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.1038569649
Short name T521
Test name
Test status
Simulation time 54626199 ps
CPU time 0.71 seconds
Started Jul 26 04:47:53 PM PDT 24
Finished Jul 26 04:47:53 PM PDT 24
Peak memory 191632 kb
Host smart-8252b354-b659-4a3b-b713-610f760b8cd6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038569649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.1038569649
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.4049467633
Short name T460
Test name
Test status
Simulation time 194965923 ps
CPU time 1.3 seconds
Started Jul 26 04:47:24 PM PDT 24
Finished Jul 26 04:47:25 PM PDT 24
Peak memory 197440 kb
Host smart-0ef4b0da-b844-48eb-9398-2d7fe43d8d39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049467633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.4049467633
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.2341862040
Short name T111
Test name
Test status
Simulation time 114280341 ps
CPU time 0.81 seconds
Started Jul 26 04:47:26 PM PDT 24
Finished Jul 26 04:47:27 PM PDT 24
Peak memory 193884 kb
Host smart-edda5de2-de54-402f-814f-7c3033ffed40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341862040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.2341862040
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.544394893
Short name T478
Test name
Test status
Simulation time 27180131 ps
CPU time 0.78 seconds
Started Jul 26 04:47:30 PM PDT 24
Finished Jul 26 04:47:31 PM PDT 24
Peak memory 195780 kb
Host smart-953e8658-72ce-41dd-a270-7b873b499f42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544394893 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.544394893
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.1105787613
Short name T475
Test name
Test status
Simulation time 14724563 ps
CPU time 0.55 seconds
Started Jul 26 04:47:47 PM PDT 24
Finished Jul 26 04:47:48 PM PDT 24
Peak memory 182812 kb
Host smart-8a41714f-dbda-4b18-b028-d0f59a6ac9d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105787613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.1105787613
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2748158593
Short name T577
Test name
Test status
Simulation time 62389132 ps
CPU time 0.55 seconds
Started Jul 26 04:47:20 PM PDT 24
Finished Jul 26 04:47:20 PM PDT 24
Peak memory 182612 kb
Host smart-169166e9-8cbc-4e7c-8308-bf9fdc72ef75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748158593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.2748158593
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.2113304218
Short name T525
Test name
Test status
Simulation time 18387564 ps
CPU time 0.61 seconds
Started Jul 26 04:47:31 PM PDT 24
Finished Jul 26 04:47:32 PM PDT 24
Peak memory 191676 kb
Host smart-89f10968-f3c4-401f-bb3d-e88d39f28476
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113304218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.2113304218
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.2596879538
Short name T539
Test name
Test status
Simulation time 296400055 ps
CPU time 2.71 seconds
Started Jul 26 04:47:50 PM PDT 24
Finished Jul 26 04:47:55 PM PDT 24
Peak memory 196800 kb
Host smart-866b3123-5bad-41f9-aa36-10a55e3b77c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596879538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.2596879538
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.2655105804
Short name T472
Test name
Test status
Simulation time 140824402 ps
CPU time 0.83 seconds
Started Jul 26 04:47:24 PM PDT 24
Finished Jul 26 04:47:25 PM PDT 24
Peak memory 194012 kb
Host smart-fc355393-052b-4220-811b-63a4db10d5a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655105804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.2655105804
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.3830452814
Short name T508
Test name
Test status
Simulation time 378881212 ps
CPU time 1.12 seconds
Started Jul 26 04:47:42 PM PDT 24
Finished Jul 26 04:47:44 PM PDT 24
Peak memory 197512 kb
Host smart-5ee15cc3-3d35-4611-82cf-04ab05b36cf4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830452814 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.3830452814
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.3767660341
Short name T569
Test name
Test status
Simulation time 13135245 ps
CPU time 0.53 seconds
Started Jul 26 04:47:29 PM PDT 24
Finished Jul 26 04:47:29 PM PDT 24
Peak memory 182524 kb
Host smart-b84e5189-7d35-4644-8ed9-9c3829e63a48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767660341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.3767660341
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2907875136
Short name T496
Test name
Test status
Simulation time 22399321 ps
CPU time 0.56 seconds
Started Jul 26 04:47:23 PM PDT 24
Finished Jul 26 04:47:24 PM PDT 24
Peak memory 182680 kb
Host smart-f561aaf9-c6ec-4804-bb16-30fc924b6a02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907875136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.2907875136
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.730929777
Short name T549
Test name
Test status
Simulation time 23123051 ps
CPU time 0.63 seconds
Started Jul 26 04:47:34 PM PDT 24
Finished Jul 26 04:47:34 PM PDT 24
Peak memory 192016 kb
Host smart-76729f9b-7501-4441-8e96-12def04bee44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730929777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_ti
mer_same_csr_outstanding.730929777
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.421266007
Short name T481
Test name
Test status
Simulation time 37760332 ps
CPU time 2 seconds
Started Jul 26 04:47:33 PM PDT 24
Finished Jul 26 04:47:35 PM PDT 24
Peak memory 197540 kb
Host smart-3515e052-ac7e-43c3-92f8-62dc51c9a40e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421266007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.421266007
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2792989461
Short name T554
Test name
Test status
Simulation time 263253150 ps
CPU time 1.08 seconds
Started Jul 26 04:47:23 PM PDT 24
Finished Jul 26 04:47:25 PM PDT 24
Peak memory 183132 kb
Host smart-d4e7b3a1-15e4-43ec-aeb3-66d1ad51a0f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792989461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.2792989461
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.2989700723
Short name T483
Test name
Test status
Simulation time 78105769 ps
CPU time 0.83 seconds
Started Jul 26 04:47:49 PM PDT 24
Finished Jul 26 04:47:50 PM PDT 24
Peak memory 196288 kb
Host smart-5b3f0df6-4f4e-4b17-b239-36db147f95d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989700723 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.2989700723
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.2275703392
Short name T495
Test name
Test status
Simulation time 23347315 ps
CPU time 0.56 seconds
Started Jul 26 04:47:23 PM PDT 24
Finished Jul 26 04:47:24 PM PDT 24
Peak memory 182756 kb
Host smart-7ca7dd65-c193-477e-a619-c1b9af49cb39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275703392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.2275703392
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.2895894399
Short name T487
Test name
Test status
Simulation time 41844304 ps
CPU time 0.53 seconds
Started Jul 26 04:47:25 PM PDT 24
Finished Jul 26 04:47:26 PM PDT 24
Peak memory 182160 kb
Host smart-4d661081-f6a1-41a4-ae4a-e9554b969ec9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895894399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.2895894399
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2782880203
Short name T64
Test name
Test status
Simulation time 145160219 ps
CPU time 0.74 seconds
Started Jul 26 04:47:31 PM PDT 24
Finished Jul 26 04:47:32 PM PDT 24
Peak memory 191700 kb
Host smart-c3a34078-76bf-4b45-abc3-8bb93dbec724
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782880203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.2782880203
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.484540048
Short name T584
Test name
Test status
Simulation time 118684836 ps
CPU time 1.53 seconds
Started Jul 26 04:47:43 PM PDT 24
Finished Jul 26 04:47:45 PM PDT 24
Peak memory 197396 kb
Host smart-39e85f3c-66ba-4961-8b3a-42beb9fbad56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484540048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.484540048
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.2107930707
Short name T502
Test name
Test status
Simulation time 358550658 ps
CPU time 1.3 seconds
Started Jul 26 04:47:38 PM PDT 24
Finished Jul 26 04:47:50 PM PDT 24
Peak memory 195256 kb
Host smart-f0d751b8-48bd-4d08-bac6-6757c3a532ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107930707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.2107930707
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.1434636201
Short name T564
Test name
Test status
Simulation time 86033309 ps
CPU time 1.42 seconds
Started Jul 26 04:47:41 PM PDT 24
Finished Jul 26 04:47:42 PM PDT 24
Peak memory 197488 kb
Host smart-82a26f1c-f287-4e64-bfd4-b2cd06b9b60a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434636201 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.1434636201
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.1292920709
Short name T86
Test name
Test status
Simulation time 16433332 ps
CPU time 0.56 seconds
Started Jul 26 04:47:25 PM PDT 24
Finished Jul 26 04:47:26 PM PDT 24
Peak memory 182788 kb
Host smart-0b062969-0457-4ece-875c-bf3454e4d29d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292920709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.1292920709
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.751846789
Short name T510
Test name
Test status
Simulation time 28309854 ps
CPU time 0.55 seconds
Started Jul 26 04:47:31 PM PDT 24
Finished Jul 26 04:47:32 PM PDT 24
Peak memory 182688 kb
Host smart-7482cbd8-b3a0-4119-a935-75ac5476b128
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751846789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.751846789
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1589298407
Short name T107
Test name
Test status
Simulation time 48659578 ps
CPU time 0.68 seconds
Started Jul 26 04:47:23 PM PDT 24
Finished Jul 26 04:47:24 PM PDT 24
Peak memory 193180 kb
Host smart-bfbcc1c4-db60-478a-8e76-acdf118233a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589298407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.1589298407
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3756410541
Short name T560
Test name
Test status
Simulation time 104406906 ps
CPU time 2.63 seconds
Started Jul 26 04:47:31 PM PDT 24
Finished Jul 26 04:47:34 PM PDT 24
Peak memory 197660 kb
Host smart-3ef19d4c-d842-450e-a341-d9c685971081
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756410541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.3756410541
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.2577235209
Short name T512
Test name
Test status
Simulation time 178999639 ps
CPU time 0.82 seconds
Started Jul 26 04:47:27 PM PDT 24
Finished Jul 26 04:47:28 PM PDT 24
Peak memory 193816 kb
Host smart-ac39aa71-3281-431c-be02-f122c962c79f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577235209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.2577235209
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.1203824010
Short name T32
Test name
Test status
Simulation time 26796870 ps
CPU time 1.11 seconds
Started Jul 26 04:47:38 PM PDT 24
Finished Jul 26 04:47:39 PM PDT 24
Peak memory 197504 kb
Host smart-05eac037-d31c-4607-9a69-c0a9305e7e26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203824010 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.1203824010
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.3200782114
Short name T96
Test name
Test status
Simulation time 12147970 ps
CPU time 0.54 seconds
Started Jul 26 04:47:37 PM PDT 24
Finished Jul 26 04:47:37 PM PDT 24
Peak memory 182780 kb
Host smart-1291e97c-f23c-414e-a9ab-5151fd6cee56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200782114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.3200782114
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.2409593525
Short name T505
Test name
Test status
Simulation time 30330974 ps
CPU time 0.54 seconds
Started Jul 26 04:47:26 PM PDT 24
Finished Jul 26 04:47:26 PM PDT 24
Peak memory 182652 kb
Host smart-0c0a09a1-ed95-4e33-ba31-a050317c5ac8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409593525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.2409593525
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2198660658
Short name T568
Test name
Test status
Simulation time 43519195 ps
CPU time 0.65 seconds
Started Jul 26 04:47:41 PM PDT 24
Finished Jul 26 04:47:42 PM PDT 24
Peak memory 192084 kb
Host smart-18422379-b333-40c7-9c56-8ecd589e7d52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198660658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.2198660658
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.4110159606
Short name T581
Test name
Test status
Simulation time 517550538 ps
CPU time 2.28 seconds
Started Jul 26 04:47:20 PM PDT 24
Finished Jul 26 04:47:33 PM PDT 24
Peak memory 197280 kb
Host smart-be6e40e0-a948-4e50-9545-e77e3f42df4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110159606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.4110159606
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.4022546025
Short name T112
Test name
Test status
Simulation time 212220933 ps
CPU time 1.32 seconds
Started Jul 26 04:47:27 PM PDT 24
Finished Jul 26 04:47:29 PM PDT 24
Peak memory 183384 kb
Host smart-d2425ff1-ef2e-47bc-a26f-28e9808b2812
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022546025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.4022546025
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.1545379178
Short name T93
Test name
Test status
Simulation time 57666605 ps
CPU time 0.69 seconds
Started Jul 26 04:47:21 PM PDT 24
Finished Jul 26 04:47:22 PM PDT 24
Peak memory 191988 kb
Host smart-68d8cb2f-f29f-446e-8076-42f939e3ff69
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545379178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.1545379178
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1842328788
Short name T493
Test name
Test status
Simulation time 192308905 ps
CPU time 2.54 seconds
Started Jul 26 04:47:21 PM PDT 24
Finished Jul 26 04:47:24 PM PDT 24
Peak memory 191044 kb
Host smart-1b20c297-5f61-4b9f-b157-bb6313ccf41e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842328788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.1842328788
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.1346780763
Short name T91
Test name
Test status
Simulation time 17323153 ps
CPU time 0.55 seconds
Started Jul 26 04:47:27 PM PDT 24
Finished Jul 26 04:47:28 PM PDT 24
Peak memory 182800 kb
Host smart-8c546090-5bf4-4a22-a283-7c47072de214
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346780763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.1346780763
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.1350800728
Short name T462
Test name
Test status
Simulation time 60293463 ps
CPU time 1.4 seconds
Started Jul 26 04:47:27 PM PDT 24
Finished Jul 26 04:47:29 PM PDT 24
Peak memory 197496 kb
Host smart-65e1c017-d1f3-4e0c-bbe2-db3ea8732d14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350800728 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.1350800728
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.112227877
Short name T474
Test name
Test status
Simulation time 76384120 ps
CPU time 0.54 seconds
Started Jul 26 04:47:27 PM PDT 24
Finished Jul 26 04:47:27 PM PDT 24
Peak memory 182760 kb
Host smart-3de6c117-8405-4ed1-9d0d-d15a02285367
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112227877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.112227877
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.523443378
Short name T468
Test name
Test status
Simulation time 83489911 ps
CPU time 0.59 seconds
Started Jul 26 04:47:26 PM PDT 24
Finished Jul 26 04:47:27 PM PDT 24
Peak memory 182592 kb
Host smart-73f014b2-44dd-4f0c-bae9-6b9e1c2a4ded
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523443378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.523443378
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.1083707551
Short name T104
Test name
Test status
Simulation time 37118472 ps
CPU time 0.79 seconds
Started Jul 26 04:47:31 PM PDT 24
Finished Jul 26 04:47:32 PM PDT 24
Peak memory 191664 kb
Host smart-e57cc2be-1b9a-4b0e-b4df-7188edbbd511
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083707551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.1083707551
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.1545828791
Short name T461
Test name
Test status
Simulation time 560448521 ps
CPU time 1.9 seconds
Started Jul 26 04:47:18 PM PDT 24
Finished Jul 26 04:47:20 PM PDT 24
Peak memory 197496 kb
Host smart-07427cb1-c443-4e85-8b8a-96ad6af47b11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545828791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.1545828791
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2586395875
Short name T31
Test name
Test status
Simulation time 390053181 ps
CPU time 1.28 seconds
Started Jul 26 04:47:21 PM PDT 24
Finished Jul 26 04:47:23 PM PDT 24
Peak memory 183444 kb
Host smart-4925c103-84f2-4ce4-b6a7-04b79849d167
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586395875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.2586395875
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.277266952
Short name T526
Test name
Test status
Simulation time 22372030 ps
CPU time 0.56 seconds
Started Jul 26 04:47:37 PM PDT 24
Finished Jul 26 04:47:37 PM PDT 24
Peak memory 182680 kb
Host smart-fd0c5d68-8c47-40c7-a83b-7489dc63e1d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277266952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.277266952
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1600711876
Short name T458
Test name
Test status
Simulation time 17920397 ps
CPU time 0.55 seconds
Started Jul 26 04:47:49 PM PDT 24
Finished Jul 26 04:47:49 PM PDT 24
Peak memory 182692 kb
Host smart-3bfb0705-a52f-454b-82f4-fafd1c36d820
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600711876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.1600711876
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.2100001417
Short name T543
Test name
Test status
Simulation time 22351049 ps
CPU time 0.56 seconds
Started Jul 26 04:47:33 PM PDT 24
Finished Jul 26 04:47:34 PM PDT 24
Peak memory 182616 kb
Host smart-e174cfdb-0d91-4056-a0f4-d905562bef75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100001417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.2100001417
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.3529477951
Short name T535
Test name
Test status
Simulation time 14826567 ps
CPU time 0.56 seconds
Started Jul 26 04:47:28 PM PDT 24
Finished Jul 26 04:47:29 PM PDT 24
Peak memory 182704 kb
Host smart-f406e471-b9c4-4442-82d2-8f3df01a73ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529477951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.3529477951
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.4293879531
Short name T488
Test name
Test status
Simulation time 34511646 ps
CPU time 0.51 seconds
Started Jul 26 04:47:20 PM PDT 24
Finished Jul 26 04:47:21 PM PDT 24
Peak memory 182368 kb
Host smart-ed02402f-e418-418e-87dc-75ee575e7603
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293879531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.4293879531
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.1182952711
Short name T459
Test name
Test status
Simulation time 100556539 ps
CPU time 0.57 seconds
Started Jul 26 04:47:25 PM PDT 24
Finished Jul 26 04:47:26 PM PDT 24
Peak memory 182092 kb
Host smart-b617479a-84f7-42a5-b5d4-d186ce9e70c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182952711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.1182952711
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.227172510
Short name T482
Test name
Test status
Simulation time 12740938 ps
CPU time 0.52 seconds
Started Jul 26 04:47:20 PM PDT 24
Finished Jul 26 04:47:20 PM PDT 24
Peak memory 182156 kb
Host smart-effcb431-244f-4a48-b3d9-adb0063a27cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227172510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.227172510
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.2771755687
Short name T544
Test name
Test status
Simulation time 15289471 ps
CPU time 0.56 seconds
Started Jul 26 04:47:37 PM PDT 24
Finished Jul 26 04:47:38 PM PDT 24
Peak memory 182712 kb
Host smart-4ec7955e-9923-44a0-848f-7d8ad81b254f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771755687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.2771755687
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1324835969
Short name T580
Test name
Test status
Simulation time 30976311 ps
CPU time 0.53 seconds
Started Jul 26 04:47:45 PM PDT 24
Finished Jul 26 04:47:46 PM PDT 24
Peak memory 182144 kb
Host smart-b1ca9470-e3c1-41e4-bd02-0dd58dc5f282
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324835969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.1324835969
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.1538076898
Short name T553
Test name
Test status
Simulation time 13877129 ps
CPU time 0.53 seconds
Started Jul 26 04:47:27 PM PDT 24
Finished Jul 26 04:47:28 PM PDT 24
Peak memory 182152 kb
Host smart-450a64f1-c6be-44d1-a0b1-10c4bab5ccfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538076898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.1538076898
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3318403578
Short name T559
Test name
Test status
Simulation time 16461565 ps
CPU time 0.62 seconds
Started Jul 26 04:47:30 PM PDT 24
Finished Jul 26 04:47:31 PM PDT 24
Peak memory 182772 kb
Host smart-ffd867d3-ad1d-48e3-ae04-be732d9c8a26
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318403578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.3318403578
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.1926687383
Short name T98
Test name
Test status
Simulation time 1693656843 ps
CPU time 3.75 seconds
Started Jul 26 04:47:34 PM PDT 24
Finished Jul 26 04:47:38 PM PDT 24
Peak memory 191088 kb
Host smart-5c108903-f825-40dc-a08d-9410adb40f9c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926687383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.1926687383
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3339843898
Short name T507
Test name
Test status
Simulation time 15265289 ps
CPU time 0.55 seconds
Started Jul 26 04:47:43 PM PDT 24
Finished Jul 26 04:47:44 PM PDT 24
Peak memory 182416 kb
Host smart-e044df89-5ea5-436c-ac92-271a049ed709
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339843898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.3339843898
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.4016794360
Short name T576
Test name
Test status
Simulation time 75319103 ps
CPU time 0.79 seconds
Started Jul 26 04:47:16 PM PDT 24
Finished Jul 26 04:47:17 PM PDT 24
Peak memory 196100 kb
Host smart-1db03e96-890a-4352-8a8e-c6cc27e1abf5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016794360 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.4016794360
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.3609999120
Short name T582
Test name
Test status
Simulation time 51139474 ps
CPU time 0.55 seconds
Started Jul 26 04:47:19 PM PDT 24
Finished Jul 26 04:47:19 PM PDT 24
Peak memory 182640 kb
Host smart-a0cf7d80-922f-4f34-9471-8e433b47a762
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609999120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.3609999120
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.639352797
Short name T99
Test name
Test status
Simulation time 20661750 ps
CPU time 0.72 seconds
Started Jul 26 04:47:24 PM PDT 24
Finished Jul 26 04:47:24 PM PDT 24
Peak memory 193440 kb
Host smart-b27e3159-bd85-40a7-9769-583a21fb4285
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639352797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_tim
er_same_csr_outstanding.639352797
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.621609187
Short name T484
Test name
Test status
Simulation time 182459348 ps
CPU time 1.21 seconds
Started Jul 26 04:47:18 PM PDT 24
Finished Jul 26 04:47:19 PM PDT 24
Peak memory 197256 kb
Host smart-be5929ce-f854-4676-b97d-036cc5333f05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621609187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.621609187
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.1510061864
Short name T555
Test name
Test status
Simulation time 590363614 ps
CPU time 1.03 seconds
Started Jul 26 04:47:06 PM PDT 24
Finished Jul 26 04:47:08 PM PDT 24
Peak memory 183076 kb
Host smart-23c71c68-a950-4724-b060-cf6618c219e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510061864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.1510061864
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.3533285673
Short name T506
Test name
Test status
Simulation time 15686567 ps
CPU time 0.54 seconds
Started Jul 26 04:47:25 PM PDT 24
Finished Jul 26 04:47:25 PM PDT 24
Peak memory 182700 kb
Host smart-03ca41df-172d-4e77-bd1c-1bb46b6060d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533285673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.3533285673
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.2969930096
Short name T561
Test name
Test status
Simulation time 59799768 ps
CPU time 0.58 seconds
Started Jul 26 04:47:37 PM PDT 24
Finished Jul 26 04:47:38 PM PDT 24
Peak memory 182612 kb
Host smart-434c31fc-56d7-48a3-902a-cec31aa545b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969930096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.2969930096
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.776484900
Short name T470
Test name
Test status
Simulation time 19276362 ps
CPU time 0.57 seconds
Started Jul 26 04:47:25 PM PDT 24
Finished Jul 26 04:47:26 PM PDT 24
Peak memory 182656 kb
Host smart-61da44e3-9444-4487-ad24-f5685b57c99f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776484900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.776484900
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.4197848352
Short name T552
Test name
Test status
Simulation time 11453548 ps
CPU time 0.52 seconds
Started Jul 26 04:47:34 PM PDT 24
Finished Jul 26 04:47:34 PM PDT 24
Peak memory 182632 kb
Host smart-841ca49a-9a59-47a6-abc0-888659214bd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197848352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.4197848352
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.284867739
Short name T504
Test name
Test status
Simulation time 17371703 ps
CPU time 0.62 seconds
Started Jul 26 04:47:51 PM PDT 24
Finished Jul 26 04:47:51 PM PDT 24
Peak memory 182572 kb
Host smart-ed1a78b6-d92a-42f0-8f42-cfc3cc0cba0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284867739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.284867739
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.3690389728
Short name T516
Test name
Test status
Simulation time 16440801 ps
CPU time 0.55 seconds
Started Jul 26 04:47:46 PM PDT 24
Finished Jul 26 04:47:47 PM PDT 24
Peak memory 182552 kb
Host smart-4afb83f4-5bb7-4a24-a521-026d00ddaab7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690389728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.3690389728
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.368943274
Short name T471
Test name
Test status
Simulation time 75620699 ps
CPU time 0.53 seconds
Started Jul 26 04:47:30 PM PDT 24
Finished Jul 26 04:47:31 PM PDT 24
Peak memory 182608 kb
Host smart-b0ce1883-d122-4923-8e4a-c8816b2898c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368943274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.368943274
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.4257838828
Short name T457
Test name
Test status
Simulation time 14609908 ps
CPU time 0.54 seconds
Started Jul 26 04:47:23 PM PDT 24
Finished Jul 26 04:47:24 PM PDT 24
Peak memory 182176 kb
Host smart-2c544b7a-8dfe-491a-a9b0-0329cb30997d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257838828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.4257838828
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.312979246
Short name T562
Test name
Test status
Simulation time 14455031 ps
CPU time 0.54 seconds
Started Jul 26 04:47:38 PM PDT 24
Finished Jul 26 04:47:38 PM PDT 24
Peak memory 182112 kb
Host smart-f93dd15d-c17f-4159-ba5d-57491ebb8004
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312979246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.312979246
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.3876515750
Short name T477
Test name
Test status
Simulation time 12461244 ps
CPU time 0.54 seconds
Started Jul 26 04:47:36 PM PDT 24
Finished Jul 26 04:47:37 PM PDT 24
Peak memory 182692 kb
Host smart-d201a88e-50fd-447b-99ef-35cffe376588
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876515750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.3876515750
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.486866961
Short name T556
Test name
Test status
Simulation time 20092987 ps
CPU time 0.62 seconds
Started Jul 26 04:47:22 PM PDT 24
Finished Jul 26 04:47:28 PM PDT 24
Peak memory 182788 kb
Host smart-6a031306-1616-45ce-b7a9-bab1636491ab
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486866961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alias
ing.486866961
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.1336219699
Short name T89
Test name
Test status
Simulation time 355329168 ps
CPU time 3.27 seconds
Started Jul 26 04:47:41 PM PDT 24
Finished Jul 26 04:47:44 PM PDT 24
Peak memory 191212 kb
Host smart-d1968ea7-660e-4f57-84d9-d2c5932eed52
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336219699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.1336219699
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.1079222345
Short name T94
Test name
Test status
Simulation time 21560651 ps
CPU time 0.6 seconds
Started Jul 26 04:47:22 PM PDT 24
Finished Jul 26 04:47:22 PM PDT 24
Peak memory 182792 kb
Host smart-ec33d605-f24f-4d69-b89e-eec4b4a2db80
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079222345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.1079222345
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.2106823274
Short name T33
Test name
Test status
Simulation time 134833212 ps
CPU time 0.91 seconds
Started Jul 26 04:47:53 PM PDT 24
Finished Jul 26 04:47:54 PM PDT 24
Peak memory 197168 kb
Host smart-0af62a91-a826-4784-990c-010bc3916159
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106823274 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.2106823274
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2750432597
Short name T511
Test name
Test status
Simulation time 16636114 ps
CPU time 0.58 seconds
Started Jul 26 04:47:17 PM PDT 24
Finished Jul 26 04:47:17 PM PDT 24
Peak memory 182772 kb
Host smart-4b37f53a-95ad-45e4-91e5-0ca0fa3a8222
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750432597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.2750432597
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.595408640
Short name T572
Test name
Test status
Simulation time 12692289 ps
CPU time 0.56 seconds
Started Jul 26 04:47:49 PM PDT 24
Finished Jul 26 04:47:49 PM PDT 24
Peak memory 182692 kb
Host smart-8bec43d5-5767-4365-a0ec-976fc982b3b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595408640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.595408640
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.2160895758
Short name T524
Test name
Test status
Simulation time 22405972 ps
CPU time 0.63 seconds
Started Jul 26 04:47:16 PM PDT 24
Finished Jul 26 04:47:17 PM PDT 24
Peak memory 192000 kb
Host smart-7ab991e6-0b06-457e-a2ab-3360f5742b21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160895758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.2160895758
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2652194519
Short name T528
Test name
Test status
Simulation time 19812480 ps
CPU time 1.11 seconds
Started Jul 26 04:47:24 PM PDT 24
Finished Jul 26 04:47:25 PM PDT 24
Peak memory 197432 kb
Host smart-f1f2f83e-b635-4d05-93e8-9c4d0c33b2aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652194519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.2652194519
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.4024934525
Short name T575
Test name
Test status
Simulation time 25339233 ps
CPU time 0.56 seconds
Started Jul 26 04:47:27 PM PDT 24
Finished Jul 26 04:47:28 PM PDT 24
Peak memory 182700 kb
Host smart-c611250e-12fe-465f-bb10-326b0b9f6ab6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024934525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.4024934525
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.3015438929
Short name T579
Test name
Test status
Simulation time 15975413 ps
CPU time 0.57 seconds
Started Jul 26 04:47:24 PM PDT 24
Finished Jul 26 04:47:25 PM PDT 24
Peak memory 182668 kb
Host smart-aa9743cb-4838-4413-8f15-34c6a64fbfd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015438929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.3015438929
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1875926741
Short name T517
Test name
Test status
Simulation time 15510011 ps
CPU time 0.56 seconds
Started Jul 26 04:47:41 PM PDT 24
Finished Jul 26 04:47:42 PM PDT 24
Peak memory 182832 kb
Host smart-43957a15-7ec4-47d6-afb6-4362bbc90db6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875926741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.1875926741
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.2197201967
Short name T531
Test name
Test status
Simulation time 58106878 ps
CPU time 0.57 seconds
Started Jul 26 04:47:25 PM PDT 24
Finished Jul 26 04:47:26 PM PDT 24
Peak memory 182632 kb
Host smart-cdef5e11-250c-43bb-a75d-71bbc864c77d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197201967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.2197201967
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.1145001636
Short name T501
Test name
Test status
Simulation time 11938017 ps
CPU time 0.55 seconds
Started Jul 26 04:47:32 PM PDT 24
Finished Jul 26 04:47:33 PM PDT 24
Peak memory 182692 kb
Host smart-74c30768-e71a-41f1-9d40-7fda24154cd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145001636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.1145001636
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1605261363
Short name T545
Test name
Test status
Simulation time 58992143 ps
CPU time 0.59 seconds
Started Jul 26 04:47:44 PM PDT 24
Finished Jul 26 04:47:50 PM PDT 24
Peak memory 182676 kb
Host smart-01af521e-13bb-4087-892a-efbcd1232d37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605261363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.1605261363
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.4274095862
Short name T485
Test name
Test status
Simulation time 66370896 ps
CPU time 0.56 seconds
Started Jul 26 04:47:25 PM PDT 24
Finished Jul 26 04:47:26 PM PDT 24
Peak memory 182696 kb
Host smart-4b56cb2c-e9f9-4908-a684-57dafa956f36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274095862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.4274095862
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2371063184
Short name T499
Test name
Test status
Simulation time 20542185 ps
CPU time 0.55 seconds
Started Jul 26 04:47:31 PM PDT 24
Finished Jul 26 04:47:32 PM PDT 24
Peak memory 182636 kb
Host smart-ac3286aa-3520-4521-8778-dc4015b4b36c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371063184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.2371063184
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.2692585146
Short name T536
Test name
Test status
Simulation time 30871292 ps
CPU time 0.54 seconds
Started Jul 26 04:47:28 PM PDT 24
Finished Jul 26 04:47:29 PM PDT 24
Peak memory 182708 kb
Host smart-4299ff2a-ccf8-43ed-94d1-804c130581f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692585146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.2692585146
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.579762363
Short name T557
Test name
Test status
Simulation time 55175370 ps
CPU time 0.57 seconds
Started Jul 26 04:47:32 PM PDT 24
Finished Jul 26 04:47:33 PM PDT 24
Peak memory 182632 kb
Host smart-fe29fa95-a1a6-43a4-80f9-542192911ba3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579762363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.579762363
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.556869478
Short name T570
Test name
Test status
Simulation time 23558869 ps
CPU time 0.76 seconds
Started Jul 26 04:47:25 PM PDT 24
Finished Jul 26 04:47:26 PM PDT 24
Peak memory 195004 kb
Host smart-7ceee9ca-98b4-475c-8f89-4af7cd48af43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556869478 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.556869478
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.3979418115
Short name T109
Test name
Test status
Simulation time 16303414 ps
CPU time 0.57 seconds
Started Jul 26 04:47:44 PM PDT 24
Finished Jul 26 04:47:44 PM PDT 24
Peak memory 182752 kb
Host smart-a53db0af-6ca1-48c8-9c64-0654d2c70dae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979418115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.3979418115
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1014546512
Short name T463
Test name
Test status
Simulation time 17194671 ps
CPU time 0.52 seconds
Started Jul 26 04:47:24 PM PDT 24
Finished Jul 26 04:47:24 PM PDT 24
Peak memory 182712 kb
Host smart-f04d97d1-ee8f-4923-9641-22fa8b56beed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014546512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.1014546512
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.3239113293
Short name T105
Test name
Test status
Simulation time 57776797 ps
CPU time 0.69 seconds
Started Jul 26 04:47:27 PM PDT 24
Finished Jul 26 04:47:33 PM PDT 24
Peak memory 191732 kb
Host smart-3f3e15ff-5081-478f-aed2-d6166c2cdfcb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239113293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.3239113293
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.3715202604
Short name T494
Test name
Test status
Simulation time 129232709 ps
CPU time 2.43 seconds
Started Jul 26 04:47:27 PM PDT 24
Finished Jul 26 04:47:30 PM PDT 24
Peak memory 197508 kb
Host smart-9c47a0dc-21c0-43c3-b7e6-87fddb89c08f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715202604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.3715202604
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3782157527
Short name T578
Test name
Test status
Simulation time 41340370 ps
CPU time 0.77 seconds
Started Jul 26 04:47:22 PM PDT 24
Finished Jul 26 04:47:23 PM PDT 24
Peak memory 183224 kb
Host smart-600ceceb-f2cd-4d18-b931-79998ec94be9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782157527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.3782157527
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.1755487568
Short name T551
Test name
Test status
Simulation time 38751684 ps
CPU time 0.91 seconds
Started Jul 26 04:47:13 PM PDT 24
Finished Jul 26 04:47:14 PM PDT 24
Peak memory 197432 kb
Host smart-1cd94484-e8bd-4fe1-a2a0-5787272d8f79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755487568 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.1755487568
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.351244393
Short name T103
Test name
Test status
Simulation time 21821569 ps
CPU time 0.54 seconds
Started Jul 26 04:47:12 PM PDT 24
Finished Jul 26 04:47:13 PM PDT 24
Peak memory 182564 kb
Host smart-26fd0bce-ef63-46e0-90a1-4f813343c8c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351244393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.351244393
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.415705795
Short name T515
Test name
Test status
Simulation time 56832162 ps
CPU time 0.53 seconds
Started Jul 26 04:48:01 PM PDT 24
Finished Jul 26 04:48:06 PM PDT 24
Peak memory 182124 kb
Host smart-fe827295-f4ce-4b22-986b-8d853a4da6e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415705795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.415705795
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.2238190689
Short name T583
Test name
Test status
Simulation time 16755835 ps
CPU time 0.71 seconds
Started Jul 26 04:47:49 PM PDT 24
Finished Jul 26 04:47:49 PM PDT 24
Peak memory 193332 kb
Host smart-1487150f-8250-40b0-9dec-b02c03300c47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238190689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.2238190689
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.1754981436
Short name T492
Test name
Test status
Simulation time 487952239 ps
CPU time 2.68 seconds
Started Jul 26 04:47:16 PM PDT 24
Finished Jul 26 04:47:19 PM PDT 24
Peak memory 197528 kb
Host smart-8c63b76e-685b-4684-8bd5-e4fb1d6b1a4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754981436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.1754981436
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.674198155
Short name T514
Test name
Test status
Simulation time 44734945 ps
CPU time 0.85 seconds
Started Jul 26 04:47:28 PM PDT 24
Finished Jul 26 04:47:29 PM PDT 24
Peak memory 193988 kb
Host smart-c91f557c-3187-446a-86c6-5aa8a06ba420
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674198155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_int
g_err.674198155
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.3064762538
Short name T466
Test name
Test status
Simulation time 36776882 ps
CPU time 0.99 seconds
Started Jul 26 04:47:01 PM PDT 24
Finished Jul 26 04:47:02 PM PDT 24
Peak memory 197436 kb
Host smart-c1a55384-5e6d-427e-8df8-62971b775002
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064762538 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.3064762538
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.1621585048
Short name T55
Test name
Test status
Simulation time 24628227 ps
CPU time 0.57 seconds
Started Jul 26 04:47:17 PM PDT 24
Finished Jul 26 04:47:18 PM PDT 24
Peak memory 182788 kb
Host smart-6b2624f2-8619-4403-9555-4a53faaade65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621585048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.1621585048
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.765100903
Short name T489
Test name
Test status
Simulation time 48396041 ps
CPU time 0.55 seconds
Started Jul 26 04:47:08 PM PDT 24
Finished Jul 26 04:47:09 PM PDT 24
Peak memory 182028 kb
Host smart-2bc8103f-bb4e-4a78-b3da-e357a2468d9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765100903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.765100903
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.1790555877
Short name T532
Test name
Test status
Simulation time 63674661 ps
CPU time 0.73 seconds
Started Jul 26 04:47:18 PM PDT 24
Finished Jul 26 04:47:19 PM PDT 24
Peak memory 193324 kb
Host smart-7161079f-db3d-47e4-97bc-0c334b112499
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790555877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.1790555877
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.2542427067
Short name T465
Test name
Test status
Simulation time 280116571 ps
CPU time 1.25 seconds
Started Jul 26 04:47:18 PM PDT 24
Finished Jul 26 04:47:19 PM PDT 24
Peak memory 197924 kb
Host smart-ce44731d-5480-461e-8645-698eba48eecb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542427067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.2542427067
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.113316938
Short name T537
Test name
Test status
Simulation time 86429380 ps
CPU time 1.15 seconds
Started Jul 26 04:47:28 PM PDT 24
Finished Jul 26 04:47:29 PM PDT 24
Peak memory 183308 kb
Host smart-417e4934-3709-4f28-a22a-2e66342e6a23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113316938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_int
g_err.113316938
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3890876475
Short name T479
Test name
Test status
Simulation time 15273675 ps
CPU time 0.71 seconds
Started Jul 26 04:47:23 PM PDT 24
Finished Jul 26 04:47:24 PM PDT 24
Peak memory 195188 kb
Host smart-c372c3d7-0955-4fd9-bdf8-9b53070bc1c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890876475 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.3890876475
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.2856213683
Short name T97
Test name
Test status
Simulation time 45033141 ps
CPU time 0.57 seconds
Started Jul 26 04:47:32 PM PDT 24
Finished Jul 26 04:47:33 PM PDT 24
Peak memory 182804 kb
Host smart-566b3454-cfbd-4472-8a55-53bdb1b551be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856213683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.2856213683
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.3167819254
Short name T490
Test name
Test status
Simulation time 22590362 ps
CPU time 0.57 seconds
Started Jul 26 04:47:25 PM PDT 24
Finished Jul 26 04:47:25 PM PDT 24
Peak memory 182688 kb
Host smart-38376564-6705-4571-be73-670f32d093ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167819254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.3167819254
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.1618571065
Short name T558
Test name
Test status
Simulation time 97493747 ps
CPU time 0.83 seconds
Started Jul 26 04:47:29 PM PDT 24
Finished Jul 26 04:47:30 PM PDT 24
Peak memory 193484 kb
Host smart-2bdf3e2c-3e9f-412b-9ff4-b0f8f50e7986
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618571065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.1618571065
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.1728262924
Short name T522
Test name
Test status
Simulation time 47491247 ps
CPU time 1.17 seconds
Started Jul 26 04:47:19 PM PDT 24
Finished Jul 26 04:47:21 PM PDT 24
Peak memory 197160 kb
Host smart-38af8298-1643-4cd4-9210-8a6c05ebef2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728262924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.1728262924
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.1200457581
Short name T29
Test name
Test status
Simulation time 361976931 ps
CPU time 1.01 seconds
Started Jul 26 04:47:35 PM PDT 24
Finished Jul 26 04:47:36 PM PDT 24
Peak memory 194632 kb
Host smart-9a21b80e-e979-40a2-8291-e316452013ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200457581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.1200457581
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3836869566
Short name T500
Test name
Test status
Simulation time 62172723 ps
CPU time 0.8 seconds
Started Jul 26 04:47:21 PM PDT 24
Finished Jul 26 04:47:22 PM PDT 24
Peak memory 196708 kb
Host smart-8b041f3d-d8de-4c21-b346-466188c69a90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836869566 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.3836869566
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.3779757281
Short name T540
Test name
Test status
Simulation time 14692009 ps
CPU time 0.56 seconds
Started Jul 26 04:47:23 PM PDT 24
Finished Jul 26 04:47:24 PM PDT 24
Peak memory 182740 kb
Host smart-ea0f0d1e-3eba-40ea-9412-a7f35c890ed3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779757281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.3779757281
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.1818521488
Short name T513
Test name
Test status
Simulation time 44726382 ps
CPU time 0.55 seconds
Started Jul 26 04:47:27 PM PDT 24
Finished Jul 26 04:47:28 PM PDT 24
Peak memory 182564 kb
Host smart-07b6ffd1-9e62-4180-af1e-ed25193384a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818521488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.1818521488
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.4110983660
Short name T106
Test name
Test status
Simulation time 50946796 ps
CPU time 0.62 seconds
Started Jul 26 04:47:27 PM PDT 24
Finished Jul 26 04:47:27 PM PDT 24
Peak memory 191596 kb
Host smart-d241c6bf-5ee9-4cae-98ce-7856190b6b58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110983660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.4110983660
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.2282390867
Short name T523
Test name
Test status
Simulation time 130584852 ps
CPU time 0.97 seconds
Started Jul 26 04:47:25 PM PDT 24
Finished Jul 26 04:47:26 PM PDT 24
Peak memory 195992 kb
Host smart-ea108eca-dc8e-4901-b324-9a96b73fcd6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282390867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.2282390867
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.648433997
Short name T563
Test name
Test status
Simulation time 157943944 ps
CPU time 0.83 seconds
Started Jul 26 04:47:22 PM PDT 24
Finished Jul 26 04:47:23 PM PDT 24
Peak memory 193764 kb
Host smart-f9aef52e-2298-4b9f-b53d-44d82751ed4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648433997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_int
g_err.648433997
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.2895142764
Short name T121
Test name
Test status
Simulation time 386101431002 ps
CPU time 623.51 seconds
Started Jul 26 04:47:48 PM PDT 24
Finished Jul 26 04:58:11 PM PDT 24
Peak memory 183352 kb
Host smart-0f8f93f1-50f3-4301-b094-44b199a92914
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895142764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.2895142764
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_random.3174759568
Short name T72
Test name
Test status
Simulation time 107160520061 ps
CPU time 315.12 seconds
Started Jul 26 04:47:39 PM PDT 24
Finished Jul 26 04:52:54 PM PDT 24
Peak memory 191612 kb
Host smart-ed080de0-56aa-46ba-bf75-61b65a307224
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174759568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.3174759568
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.4197652030
Short name T312
Test name
Test status
Simulation time 9467272076 ps
CPU time 7.75 seconds
Started Jul 26 04:47:29 PM PDT 24
Finished Jul 26 04:47:37 PM PDT 24
Peak memory 191556 kb
Host smart-c5f43c3d-c770-43b2-95d5-0b2ae77b1acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197652030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.4197652030
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.4063071179
Short name T344
Test name
Test status
Simulation time 230425665096 ps
CPU time 315.39 seconds
Started Jul 26 04:47:31 PM PDT 24
Finished Jul 26 04:52:47 PM PDT 24
Peak memory 191560 kb
Host smart-c5e24899-f217-405c-9318-d4ccde57cb4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063071179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
4063071179
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all_with_rand_reset.2040110567
Short name T51
Test name
Test status
Simulation time 22034177520 ps
CPU time 153.68 seconds
Started Jul 26 04:47:38 PM PDT 24
Finished Jul 26 04:50:12 PM PDT 24
Peak memory 198056 kb
Host smart-1edcd40e-ce5f-4ca3-84e5-85202d6a8e89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040110567 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all_with_rand_reset.2040110567
Directory /workspace/0.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.3428346971
Short name T377
Test name
Test status
Simulation time 95082405859 ps
CPU time 132.06 seconds
Started Jul 26 04:47:25 PM PDT 24
Finished Jul 26 04:49:37 PM PDT 24
Peak memory 183416 kb
Host smart-39bc6a91-1e63-4ee2-8acf-3d8dc3143320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428346971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.3428346971
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.1841556955
Short name T309
Test name
Test status
Simulation time 556362222863 ps
CPU time 290.63 seconds
Started Jul 26 04:47:42 PM PDT 24
Finished Jul 26 04:52:32 PM PDT 24
Peak memory 191596 kb
Host smart-5858576a-88c8-4e68-89c2-635b112103ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841556955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.1841556955
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.172353682
Short name T315
Test name
Test status
Simulation time 55586268233 ps
CPU time 82.87 seconds
Started Jul 26 04:47:48 PM PDT 24
Finished Jul 26 04:49:11 PM PDT 24
Peak memory 183308 kb
Host smart-0eed16da-808b-4131-a070-862d00b9cad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172353682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.172353682
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.2396181495
Short name T19
Test name
Test status
Simulation time 347966679 ps
CPU time 0.9 seconds
Started Jul 26 04:47:37 PM PDT 24
Finished Jul 26 04:47:38 PM PDT 24
Peak memory 214804 kb
Host smart-c60c3875-2fd5-4bd7-9ee4-a2e5724a9db9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396181495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.2396181495
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.2248959268
Short name T241
Test name
Test status
Simulation time 513312065838 ps
CPU time 274.54 seconds
Started Jul 26 04:47:41 PM PDT 24
Finished Jul 26 04:52:15 PM PDT 24
Peak memory 183348 kb
Host smart-4d518821-b710-40e0-b0ff-42ce4b594415
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248959268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.2248959268
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.3082984737
Short name T410
Test name
Test status
Simulation time 90462999328 ps
CPU time 136.08 seconds
Started Jul 26 04:47:49 PM PDT 24
Finished Jul 26 04:50:05 PM PDT 24
Peak memory 183300 kb
Host smart-f2afbec3-4f22-4fb7-a9d5-14dd77c5f9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082984737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.3082984737
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.1373290314
Short name T238
Test name
Test status
Simulation time 259867866354 ps
CPU time 447.11 seconds
Started Jul 26 04:47:43 PM PDT 24
Finished Jul 26 04:55:11 PM PDT 24
Peak memory 191620 kb
Host smart-cfff71a6-c844-458a-894e-5e28050e937f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373290314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.1373290314
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.2092186802
Short name T83
Test name
Test status
Simulation time 9575378015 ps
CPU time 53.83 seconds
Started Jul 26 04:47:55 PM PDT 24
Finished Jul 26 04:48:48 PM PDT 24
Peak memory 183380 kb
Host smart-758e966d-2608-4644-a300-7e4c29f713cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092186802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.2092186802
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.375547632
Short name T382
Test name
Test status
Simulation time 231651567082 ps
CPU time 202.41 seconds
Started Jul 26 04:47:43 PM PDT 24
Finished Jul 26 04:51:06 PM PDT 24
Peak memory 183420 kb
Host smart-80a21ddb-7938-4336-8f45-70f71d9d9847
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375547632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all.
375547632
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/101.rv_timer_random.1327994866
Short name T347
Test name
Test status
Simulation time 92508773150 ps
CPU time 288.35 seconds
Started Jul 26 04:48:06 PM PDT 24
Finished Jul 26 04:52:55 PM PDT 24
Peak memory 191564 kb
Host smart-5a765a53-2fc6-4a08-be4c-fbf430abea57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327994866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.1327994866
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.2167760238
Short name T223
Test name
Test status
Simulation time 52270477626 ps
CPU time 314.67 seconds
Started Jul 26 04:48:29 PM PDT 24
Finished Jul 26 04:53:44 PM PDT 24
Peak memory 194204 kb
Host smart-30d87a74-58cc-4545-b34f-7f20d9a85197
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167760238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.2167760238
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.2750411733
Short name T318
Test name
Test status
Simulation time 196605201609 ps
CPU time 119.46 seconds
Started Jul 26 04:48:20 PM PDT 24
Finished Jul 26 04:50:19 PM PDT 24
Peak memory 191692 kb
Host smart-b84313cb-97bf-4b26-a1c3-3992b492eb6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750411733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.2750411733
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.2527953942
Short name T198
Test name
Test status
Simulation time 787403282500 ps
CPU time 379.12 seconds
Started Jul 26 04:48:09 PM PDT 24
Finished Jul 26 04:54:29 PM PDT 24
Peak memory 191588 kb
Host smart-782a5217-f9cf-4564-a181-c17a16093b83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527953942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.2527953942
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.2223799739
Short name T212
Test name
Test status
Simulation time 171449590208 ps
CPU time 322.72 seconds
Started Jul 26 04:48:33 PM PDT 24
Finished Jul 26 04:53:56 PM PDT 24
Peak memory 191584 kb
Host smart-ae004b2a-83d6-47f7-aaa4-a3ed8e98015e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223799739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.2223799739
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random.3527865653
Short name T159
Test name
Test status
Simulation time 149121937324 ps
CPU time 235.81 seconds
Started Jul 26 04:47:45 PM PDT 24
Finished Jul 26 04:51:41 PM PDT 24
Peak memory 191608 kb
Host smart-3288d192-20da-4aa2-9a2e-783ecd04b021
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527865653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.3527865653
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.2568265184
Short name T225
Test name
Test status
Simulation time 46319566301 ps
CPU time 964.33 seconds
Started Jul 26 04:47:51 PM PDT 24
Finished Jul 26 05:03:55 PM PDT 24
Peak memory 194880 kb
Host smart-0608d74a-4697-48d0-bb6e-5b3c5fc3bc34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568265184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.2568265184
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/111.rv_timer_random.3978240091
Short name T424
Test name
Test status
Simulation time 273719363787 ps
CPU time 253.09 seconds
Started Jul 26 04:48:12 PM PDT 24
Finished Jul 26 04:52:25 PM PDT 24
Peak memory 183396 kb
Host smart-9cea4398-8084-47db-9966-70e3b1c1d960
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978240091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.3978240091
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.2864315675
Short name T397
Test name
Test status
Simulation time 344714829417 ps
CPU time 364.73 seconds
Started Jul 26 04:48:31 PM PDT 24
Finished Jul 26 04:54:36 PM PDT 24
Peak memory 191584 kb
Host smart-e45efeb8-ab85-4328-a407-518bb75035ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864315675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.2864315675
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.1498699464
Short name T296
Test name
Test status
Simulation time 176804813369 ps
CPU time 93.56 seconds
Started Jul 26 04:48:14 PM PDT 24
Finished Jul 26 04:49:48 PM PDT 24
Peak memory 183344 kb
Host smart-0b7eb18f-7a97-4552-a2f6-857dbe86e305
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498699464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.1498699464
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.1869916436
Short name T177
Test name
Test status
Simulation time 245479535048 ps
CPU time 156.66 seconds
Started Jul 26 04:48:25 PM PDT 24
Finished Jul 26 04:51:02 PM PDT 24
Peak memory 191460 kb
Host smart-a5f20e33-6f13-467f-a32c-caea64a005ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869916436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.1869916436
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.2829562030
Short name T183
Test name
Test status
Simulation time 228968191759 ps
CPU time 88.75 seconds
Started Jul 26 04:48:09 PM PDT 24
Finished Jul 26 04:49:38 PM PDT 24
Peak memory 191596 kb
Host smart-d7e31618-905a-4952-81db-f8006a7768ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829562030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.2829562030
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.492886826
Short name T170
Test name
Test status
Simulation time 128033751208 ps
CPU time 1655.49 seconds
Started Jul 26 04:48:13 PM PDT 24
Finished Jul 26 05:15:49 PM PDT 24
Peak memory 191528 kb
Host smart-3f13fb94-3c5d-4788-999d-2339779774cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492886826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.492886826
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.4019370681
Short name T455
Test name
Test status
Simulation time 58720885055 ps
CPU time 83.93 seconds
Started Jul 26 04:48:20 PM PDT 24
Finished Jul 26 04:49:44 PM PDT 24
Peak memory 183336 kb
Host smart-6319ac0f-0cbc-40af-92bf-82817bccb049
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019370681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.4019370681
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.4274113153
Short name T128
Test name
Test status
Simulation time 102950493417 ps
CPU time 171.84 seconds
Started Jul 26 04:48:22 PM PDT 24
Finished Jul 26 04:51:14 PM PDT 24
Peak memory 191592 kb
Host smart-b55660e2-dd1a-45d2-b8bd-634d17ddcbf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274113153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.4274113153
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.2189441776
Short name T434
Test name
Test status
Simulation time 1126495314176 ps
CPU time 584.23 seconds
Started Jul 26 04:47:59 PM PDT 24
Finished Jul 26 04:57:44 PM PDT 24
Peak memory 183352 kb
Host smart-604f7ed9-86aa-4c4b-b98c-84c2dcaef4f0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189441776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.2189441776
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.1123654211
Short name T383
Test name
Test status
Simulation time 259647336170 ps
CPU time 108.44 seconds
Started Jul 26 04:47:40 PM PDT 24
Finished Jul 26 04:49:28 PM PDT 24
Peak memory 183400 kb
Host smart-5811c06c-0d3a-42a5-be2f-15d899e0e961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123654211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.1123654211
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.3124090985
Short name T280
Test name
Test status
Simulation time 33544812110 ps
CPU time 53.09 seconds
Started Jul 26 04:47:45 PM PDT 24
Finished Jul 26 04:48:38 PM PDT 24
Peak memory 183388 kb
Host smart-aa2459a8-82ea-4ba4-90fa-e5869d3575f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124090985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.3124090985
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.4094819346
Short name T119
Test name
Test status
Simulation time 72384753103 ps
CPU time 17.4 seconds
Started Jul 26 04:47:37 PM PDT 24
Finished Jul 26 04:47:55 PM PDT 24
Peak memory 191560 kb
Host smart-2869c9cb-5b6d-408c-9114-6792a4907ff3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094819346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.4094819346
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all_with_rand_reset.735175860
Short name T13
Test name
Test status
Simulation time 224825242064 ps
CPU time 639.73 seconds
Started Jul 26 04:47:53 PM PDT 24
Finished Jul 26 04:58:33 PM PDT 24
Peak memory 208228 kb
Host smart-1f90a3a7-799a-4360-8dce-7b240a64f7ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735175860 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all_with_rand_reset.735175860
Directory /workspace/12.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.rv_timer_random.3147804242
Short name T154
Test name
Test status
Simulation time 40291671286 ps
CPU time 504.54 seconds
Started Jul 26 04:48:19 PM PDT 24
Finished Jul 26 04:56:44 PM PDT 24
Peak memory 191452 kb
Host smart-facb3826-9fa3-467f-8a23-e8c43ad9ded6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147804242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.3147804242
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.1567562459
Short name T136
Test name
Test status
Simulation time 79744509884 ps
CPU time 51.07 seconds
Started Jul 26 04:48:08 PM PDT 24
Finished Jul 26 04:49:00 PM PDT 24
Peak memory 194548 kb
Host smart-5fd6d7e9-0a90-4138-8d12-98cbabb48e82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567562459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.1567562459
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.870091666
Short name T287
Test name
Test status
Simulation time 20615812467 ps
CPU time 131.24 seconds
Started Jul 26 04:48:05 PM PDT 24
Finished Jul 26 04:50:17 PM PDT 24
Peak memory 183348 kb
Host smart-73a4e44a-5fb0-4cfb-8862-1792f90c057e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870091666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.870091666
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.2499554454
Short name T274
Test name
Test status
Simulation time 343559385547 ps
CPU time 340.19 seconds
Started Jul 26 04:48:38 PM PDT 24
Finished Jul 26 04:54:19 PM PDT 24
Peak memory 191912 kb
Host smart-0bad7018-9b05-44e2-84dc-1e46c6f01787
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499554454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.2499554454
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.3347575583
Short name T160
Test name
Test status
Simulation time 569105688459 ps
CPU time 469.01 seconds
Started Jul 26 04:48:25 PM PDT 24
Finished Jul 26 04:56:14 PM PDT 24
Peak memory 194828 kb
Host smart-95650958-4927-49d4-ba21-25272d185a53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347575583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.3347575583
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.722275826
Short name T349
Test name
Test status
Simulation time 47679930443 ps
CPU time 78.17 seconds
Started Jul 26 04:48:25 PM PDT 24
Finished Jul 26 04:49:43 PM PDT 24
Peak memory 191584 kb
Host smart-40b89206-ff4f-4965-bac7-f53a9d724bcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722275826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.722275826
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.2765227997
Short name T442
Test name
Test status
Simulation time 96791376509 ps
CPU time 140.47 seconds
Started Jul 26 04:47:50 PM PDT 24
Finished Jul 26 04:50:10 PM PDT 24
Peak memory 183392 kb
Host smart-9cca5720-68e6-472b-a278-16e0e1dad794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765227997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.2765227997
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.2357183063
Short name T165
Test name
Test status
Simulation time 93026683161 ps
CPU time 671.61 seconds
Started Jul 26 04:47:59 PM PDT 24
Finished Jul 26 04:59:11 PM PDT 24
Peak memory 191544 kb
Host smart-e07c30ad-ab54-4059-8912-3383893f62a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357183063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.2357183063
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/130.rv_timer_random.2033377755
Short name T428
Test name
Test status
Simulation time 177917213089 ps
CPU time 77.91 seconds
Started Jul 26 04:48:24 PM PDT 24
Finished Jul 26 04:49:42 PM PDT 24
Peak memory 191552 kb
Host smart-d508f432-f166-4e02-aac2-1a71645d60d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033377755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.2033377755
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.3669361491
Short name T42
Test name
Test status
Simulation time 308404773024 ps
CPU time 203.44 seconds
Started Jul 26 04:48:35 PM PDT 24
Finished Jul 26 04:51:59 PM PDT 24
Peak memory 194916 kb
Host smart-2fed547b-2d74-439f-ab4f-3dfc05d9d342
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669361491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.3669361491
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.680296240
Short name T415
Test name
Test status
Simulation time 312243581410 ps
CPU time 68.83 seconds
Started Jul 26 04:48:09 PM PDT 24
Finished Jul 26 04:49:18 PM PDT 24
Peak memory 183436 kb
Host smart-ffcb64c1-7a43-4301-886c-c8b9ec119df2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680296240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.680296240
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.3968305392
Short name T354
Test name
Test status
Simulation time 23513190168 ps
CPU time 30.57 seconds
Started Jul 26 04:48:19 PM PDT 24
Finished Jul 26 04:48:50 PM PDT 24
Peak memory 183196 kb
Host smart-c88e0f01-78eb-402d-887f-7b845ffaa5fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968305392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.3968305392
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.2599557930
Short name T180
Test name
Test status
Simulation time 316045297794 ps
CPU time 138.32 seconds
Started Jul 26 04:48:29 PM PDT 24
Finished Jul 26 04:50:47 PM PDT 24
Peak memory 191592 kb
Host smart-c326422c-679f-42fa-9c07-683f8eb2621e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599557930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.2599557930
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.4127909298
Short name T392
Test name
Test status
Simulation time 80772980712 ps
CPU time 137.81 seconds
Started Jul 26 04:48:46 PM PDT 24
Finished Jul 26 04:51:04 PM PDT 24
Peak memory 191532 kb
Host smart-cbabc81b-0439-4464-b9c3-6596ab30092d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127909298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.4127909298
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.1720446400
Short name T134
Test name
Test status
Simulation time 1172993753913 ps
CPU time 343.88 seconds
Started Jul 26 04:48:22 PM PDT 24
Finished Jul 26 04:54:06 PM PDT 24
Peak memory 191512 kb
Host smart-6dea5e31-7cb9-4f1a-bc80-067e31354697
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720446400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.1720446400
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.3222137049
Short name T162
Test name
Test status
Simulation time 365508822765 ps
CPU time 208.98 seconds
Started Jul 26 04:48:35 PM PDT 24
Finished Jul 26 04:52:04 PM PDT 24
Peak memory 191592 kb
Host smart-a3068285-fc8f-416b-8159-9a66726b3352
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222137049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.3222137049
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.162234612
Short name T252
Test name
Test status
Simulation time 153678367439 ps
CPU time 140.13 seconds
Started Jul 26 04:48:16 PM PDT 24
Finished Jul 26 04:50:36 PM PDT 24
Peak memory 191636 kb
Host smart-2dc67351-75db-4721-b937-fee918148865
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162234612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.162234612
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.3177226957
Short name T243
Test name
Test status
Simulation time 127986324280 ps
CPU time 206.68 seconds
Started Jul 26 04:47:47 PM PDT 24
Finished Jul 26 04:51:14 PM PDT 24
Peak memory 183356 kb
Host smart-056f172c-b775-417a-b2c7-6d8cd25c678a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177226957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.3177226957
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.3869026573
Short name T438
Test name
Test status
Simulation time 14323841017 ps
CPU time 22.11 seconds
Started Jul 26 04:47:44 PM PDT 24
Finished Jul 26 04:48:06 PM PDT 24
Peak memory 183356 kb
Host smart-3a5063bb-b6bb-404e-ad1a-2129cddb3fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869026573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.3869026573
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.2454604847
Short name T7
Test name
Test status
Simulation time 58231031416 ps
CPU time 442.9 seconds
Started Jul 26 04:47:53 PM PDT 24
Finished Jul 26 04:55:16 PM PDT 24
Peak memory 183356 kb
Host smart-5f7f4476-01bd-41cf-a34c-1b0d07d3e235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454604847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.2454604847
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.325029883
Short name T146
Test name
Test status
Simulation time 644045722321 ps
CPU time 2299.48 seconds
Started Jul 26 04:48:09 PM PDT 24
Finished Jul 26 05:26:29 PM PDT 24
Peak memory 191556 kb
Host smart-759c8c7e-a248-49de-b5db-78299b402eab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325029883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all.
325029883
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/141.rv_timer_random.2859995790
Short name T306
Test name
Test status
Simulation time 64714443895 ps
CPU time 105.64 seconds
Started Jul 26 04:48:19 PM PDT 24
Finished Jul 26 04:50:10 PM PDT 24
Peak memory 191532 kb
Host smart-5069c217-af8c-462e-bd69-7d0eebffa064
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859995790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.2859995790
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.1100680762
Short name T319
Test name
Test status
Simulation time 241269843976 ps
CPU time 224 seconds
Started Jul 26 04:48:08 PM PDT 24
Finished Jul 26 04:51:52 PM PDT 24
Peak memory 191576 kb
Host smart-37d92535-348b-46af-8372-54c770858ec1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100680762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.1100680762
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.2137459707
Short name T402
Test name
Test status
Simulation time 192176728601 ps
CPU time 1720.14 seconds
Started Jul 26 04:48:21 PM PDT 24
Finished Jul 26 05:17:01 PM PDT 24
Peak memory 183392 kb
Host smart-343de827-8c6b-4036-bd22-0b5c9f40fc57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137459707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.2137459707
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.2396489009
Short name T71
Test name
Test status
Simulation time 684092661182 ps
CPU time 739.62 seconds
Started Jul 26 04:48:16 PM PDT 24
Finished Jul 26 05:00:36 PM PDT 24
Peak memory 193256 kb
Host smart-5855ea0b-89b2-4b88-9409-e66438b47ffc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396489009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.2396489009
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.2383905067
Short name T240
Test name
Test status
Simulation time 87778896554 ps
CPU time 151.56 seconds
Started Jul 26 04:47:48 PM PDT 24
Finished Jul 26 04:50:19 PM PDT 24
Peak memory 183352 kb
Host smart-1c0542a4-9af4-46e8-96fb-83912ff1602d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383905067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.2383905067
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.3267562181
Short name T50
Test name
Test status
Simulation time 220687225589 ps
CPU time 163.46 seconds
Started Jul 26 04:47:58 PM PDT 24
Finished Jul 26 04:50:42 PM PDT 24
Peak memory 183412 kb
Host smart-b6c28669-9324-477d-929f-96941150778a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267562181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.3267562181
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.1435979774
Short name T281
Test name
Test status
Simulation time 423136804674 ps
CPU time 181.98 seconds
Started Jul 26 04:47:42 PM PDT 24
Finished Jul 26 04:50:44 PM PDT 24
Peak memory 191708 kb
Host smart-01dbae87-2438-4cec-b1f6-68c57b0fa6ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435979774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.1435979774
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.1567693727
Short name T432
Test name
Test status
Simulation time 189380486 ps
CPU time 0.65 seconds
Started Jul 26 04:48:02 PM PDT 24
Finished Jul 26 04:48:03 PM PDT 24
Peak memory 183184 kb
Host smart-5894fc22-c5d2-44be-b631-c191bfd94efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567693727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.1567693727
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.984380558
Short name T68
Test name
Test status
Simulation time 265546178759 ps
CPU time 139.24 seconds
Started Jul 26 04:47:49 PM PDT 24
Finished Jul 26 04:50:09 PM PDT 24
Peak memory 183364 kb
Host smart-d1ea735c-3a5e-4a29-9fa4-a767427b80ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984380558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all.
984380558
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.767796471
Short name T380
Test name
Test status
Simulation time 26192304171 ps
CPU time 279.35 seconds
Started Jul 26 04:47:48 PM PDT 24
Finished Jul 26 04:52:27 PM PDT 24
Peak memory 198044 kb
Host smart-15e0ca4d-3314-486f-92c9-76fd2efbcb71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767796471 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all_with_rand_reset.767796471
Directory /workspace/15.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/151.rv_timer_random.459094487
Short name T158
Test name
Test status
Simulation time 199841533879 ps
CPU time 228.54 seconds
Started Jul 26 04:48:31 PM PDT 24
Finished Jul 26 04:52:20 PM PDT 24
Peak memory 191584 kb
Host smart-f7fba465-b55d-49b2-878b-baf8df839467
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459094487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.459094487
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.4142139757
Short name T431
Test name
Test status
Simulation time 31444407886 ps
CPU time 37.09 seconds
Started Jul 26 04:48:06 PM PDT 24
Finished Jul 26 04:48:43 PM PDT 24
Peak memory 191612 kb
Host smart-c454f041-532d-41fa-a126-0a86ef8573a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142139757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.4142139757
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.4124514812
Short name T59
Test name
Test status
Simulation time 160742139553 ps
CPU time 49.16 seconds
Started Jul 26 04:48:18 PM PDT 24
Finished Jul 26 04:49:07 PM PDT 24
Peak memory 191576 kb
Host smart-39f7ce78-1573-4e06-ad21-0f16f50b61f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124514812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.4124514812
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.469164620
Short name T449
Test name
Test status
Simulation time 186371267271 ps
CPU time 98.64 seconds
Started Jul 26 04:48:09 PM PDT 24
Finished Jul 26 04:49:48 PM PDT 24
Peak memory 191972 kb
Host smart-d7674604-bb64-4e16-9641-9374e619582a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469164620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.469164620
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.3469441976
Short name T278
Test name
Test status
Simulation time 13067003867 ps
CPU time 10.18 seconds
Started Jul 26 04:48:26 PM PDT 24
Finished Jul 26 04:48:37 PM PDT 24
Peak memory 183404 kb
Host smart-9fc1a334-a3b1-4d32-8222-f11ed14c2955
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469441976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.3469441976
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.1876379832
Short name T330
Test name
Test status
Simulation time 274659372577 ps
CPU time 124.72 seconds
Started Jul 26 04:48:27 PM PDT 24
Finished Jul 26 04:50:32 PM PDT 24
Peak memory 191560 kb
Host smart-14d9f452-7086-45f2-a00b-3831b251ed1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876379832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.1876379832
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.1107794091
Short name T230
Test name
Test status
Simulation time 89133567007 ps
CPU time 153.79 seconds
Started Jul 26 04:48:17 PM PDT 24
Finished Jul 26 04:50:51 PM PDT 24
Peak memory 191540 kb
Host smart-99bb0af1-4c37-43ee-91ef-de9ccebcfb74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107794091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.1107794091
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.2242825410
Short name T322
Test name
Test status
Simulation time 33094539475 ps
CPU time 45.93 seconds
Started Jul 26 04:48:01 PM PDT 24
Finished Jul 26 04:48:47 PM PDT 24
Peak memory 183352 kb
Host smart-ebb82465-2986-4742-ad3b-43163868589f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242825410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.2242825410
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.1934597421
Short name T367
Test name
Test status
Simulation time 103057181134 ps
CPU time 137.02 seconds
Started Jul 26 04:47:54 PM PDT 24
Finished Jul 26 04:50:11 PM PDT 24
Peak memory 183312 kb
Host smart-461099a3-8cfd-44c5-812d-25c5579b58e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934597421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.1934597421
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.2087827490
Short name T6
Test name
Test status
Simulation time 36608464679 ps
CPU time 16.18 seconds
Started Jul 26 04:48:14 PM PDT 24
Finished Jul 26 04:48:30 PM PDT 24
Peak memory 183360 kb
Host smart-fa56f1ab-067c-47cd-93ce-42934d5afb96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087827490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.2087827490
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.1116975447
Short name T168
Test name
Test status
Simulation time 156993260493 ps
CPU time 596.7 seconds
Started Jul 26 04:48:14 PM PDT 24
Finished Jul 26 04:58:11 PM PDT 24
Peak memory 191516 kb
Host smart-6d1a3b56-761a-49bb-9a72-ebc008fe8940
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116975447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.1116975447
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.1170135997
Short name T334
Test name
Test status
Simulation time 203823553539 ps
CPU time 284.4 seconds
Started Jul 26 04:48:25 PM PDT 24
Finished Jul 26 04:53:09 PM PDT 24
Peak memory 191520 kb
Host smart-33f272ec-afac-42c6-8d99-f5ebc920f073
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170135997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.1170135997
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.155592196
Short name T362
Test name
Test status
Simulation time 337731986307 ps
CPU time 1571.91 seconds
Started Jul 26 04:48:18 PM PDT 24
Finished Jul 26 05:14:30 PM PDT 24
Peak memory 191592 kb
Host smart-cceb06cb-0fc5-479f-a54c-db6276c1eac1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155592196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.155592196
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.548986612
Short name T224
Test name
Test status
Simulation time 322993465301 ps
CPU time 74.03 seconds
Started Jul 26 04:48:03 PM PDT 24
Finished Jul 26 04:49:17 PM PDT 24
Peak memory 194076 kb
Host smart-635f798d-af67-44be-a4fe-c482ab166a7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548986612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.548986612
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.1715172583
Short name T186
Test name
Test status
Simulation time 408107024515 ps
CPU time 155.05 seconds
Started Jul 26 04:48:28 PM PDT 24
Finished Jul 26 04:51:03 PM PDT 24
Peak memory 191592 kb
Host smart-47ee7a9e-080c-47a8-8ed1-c8cba907f752
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715172583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.1715172583
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.1221094291
Short name T4
Test name
Test status
Simulation time 143014014044 ps
CPU time 610.13 seconds
Started Jul 26 04:48:19 PM PDT 24
Finished Jul 26 04:58:30 PM PDT 24
Peak memory 191536 kb
Host smart-a0afd0f6-51e1-46d1-8dbe-6d7fa15bd626
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221094291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.1221094291
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.169236597
Short name T8
Test name
Test status
Simulation time 40281494256 ps
CPU time 35.17 seconds
Started Jul 26 04:48:22 PM PDT 24
Finished Jul 26 04:48:57 PM PDT 24
Peak memory 183348 kb
Host smart-815c6823-b560-4dfc-912c-5f363fba61ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169236597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.169236597
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.3527339191
Short name T132
Test name
Test status
Simulation time 79384790084 ps
CPU time 40.97 seconds
Started Jul 26 04:47:49 PM PDT 24
Finished Jul 26 04:48:30 PM PDT 24
Peak memory 183280 kb
Host smart-07436d3d-0252-4fe1-bbf1-5354750549cc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527339191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.3527339191
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.978151889
Short name T430
Test name
Test status
Simulation time 166425947018 ps
CPU time 242.04 seconds
Started Jul 26 04:48:03 PM PDT 24
Finished Jul 26 04:52:05 PM PDT 24
Peak memory 183320 kb
Host smart-5aeb398a-2cf1-4a3f-8006-21eb2aa2893e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978151889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.978151889
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.1614489627
Short name T201
Test name
Test status
Simulation time 68877613496 ps
CPU time 95.6 seconds
Started Jul 26 04:47:37 PM PDT 24
Finished Jul 26 04:49:13 PM PDT 24
Peak memory 191572 kb
Host smart-d339ef2d-f893-40e2-a56c-303f9dc20dfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614489627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.1614489627
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.1320049994
Short name T155
Test name
Test status
Simulation time 321089706917 ps
CPU time 188.22 seconds
Started Jul 26 04:48:04 PM PDT 24
Finished Jul 26 04:51:13 PM PDT 24
Peak memory 191612 kb
Host smart-23339138-3190-4f0b-9aef-c2745570c13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320049994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.1320049994
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.885198315
Short name T148
Test name
Test status
Simulation time 3868414397346 ps
CPU time 1093.58 seconds
Started Jul 26 04:47:49 PM PDT 24
Finished Jul 26 05:06:03 PM PDT 24
Peak memory 191564 kb
Host smart-795ac76d-72ce-4d89-b388-f11ae97d9ea4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885198315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all.
885198315
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/170.rv_timer_random.210060394
Short name T272
Test name
Test status
Simulation time 365706451456 ps
CPU time 1045.71 seconds
Started Jul 26 04:48:46 PM PDT 24
Finished Jul 26 05:06:12 PM PDT 24
Peak memory 191584 kb
Host smart-6939211f-8400-41f6-af49-0a03cec3e6ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210060394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.210060394
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.3616942485
Short name T131
Test name
Test status
Simulation time 1442264113198 ps
CPU time 1222.29 seconds
Started Jul 26 04:48:14 PM PDT 24
Finished Jul 26 05:08:36 PM PDT 24
Peak memory 191584 kb
Host smart-35f38cf1-4583-4bc9-91fc-b881a7f6d69d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616942485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.3616942485
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.2421100813
Short name T446
Test name
Test status
Simulation time 50611134692 ps
CPU time 49.09 seconds
Started Jul 26 04:48:19 PM PDT 24
Finished Jul 26 04:49:08 PM PDT 24
Peak memory 183352 kb
Host smart-c9291824-46e6-4ab4-845b-88cb5c8ef4e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421100813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.2421100813
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.1373712262
Short name T191
Test name
Test status
Simulation time 14719806605 ps
CPU time 20.11 seconds
Started Jul 26 04:48:26 PM PDT 24
Finished Jul 26 04:48:46 PM PDT 24
Peak memory 183364 kb
Host smart-7603d1cb-3da5-4f0e-b374-46945551089a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373712262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.1373712262
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.2520681272
Short name T427
Test name
Test status
Simulation time 47871487731 ps
CPU time 76.08 seconds
Started Jul 26 04:48:17 PM PDT 24
Finished Jul 26 04:49:33 PM PDT 24
Peak memory 183380 kb
Host smart-fbec467c-e738-44fe-b609-8ee3b7566c86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520681272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.2520681272
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.3671555104
Short name T247
Test name
Test status
Simulation time 327966997085 ps
CPU time 146.31 seconds
Started Jul 26 04:48:31 PM PDT 24
Finished Jul 26 04:50:57 PM PDT 24
Peak memory 191516 kb
Host smart-c623de77-1af3-4444-be43-26c0c3d795d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671555104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.3671555104
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.3518587482
Short name T23
Test name
Test status
Simulation time 331168302371 ps
CPU time 72.81 seconds
Started Jul 26 04:47:54 PM PDT 24
Finished Jul 26 04:49:07 PM PDT 24
Peak memory 183328 kb
Host smart-82c2ecd4-33e2-4e92-a1cf-d5b334a907e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518587482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.3518587482
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.1871113767
Short name T237
Test name
Test status
Simulation time 114878752843 ps
CPU time 751.78 seconds
Started Jul 26 04:47:43 PM PDT 24
Finished Jul 26 05:00:16 PM PDT 24
Peak memory 191564 kb
Host smart-59504689-fd5e-4c6f-8858-256e510697ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871113767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.1871113767
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.2559443426
Short name T157
Test name
Test status
Simulation time 258294715398 ps
CPU time 315.14 seconds
Started Jul 26 04:47:46 PM PDT 24
Finished Jul 26 04:53:02 PM PDT 24
Peak memory 191576 kb
Host smart-99959388-e541-4113-8958-70f5774dfc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559443426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.2559443426
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.3463793831
Short name T388
Test name
Test status
Simulation time 3731463184781 ps
CPU time 780.03 seconds
Started Jul 26 04:47:48 PM PDT 24
Finished Jul 26 05:00:48 PM PDT 24
Peak memory 191548 kb
Host smart-564d1888-5c9f-473a-94fa-06bb85a4c97e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463793831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.3463793831
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.181628716
Short name T161
Test name
Test status
Simulation time 180033866545 ps
CPU time 370.14 seconds
Started Jul 26 04:47:45 PM PDT 24
Finished Jul 26 04:53:55 PM PDT 24
Peak memory 206628 kb
Host smart-20a2d2fb-878f-49eb-a36d-180a7707745c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181628716 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all_with_rand_reset.181628716
Directory /workspace/18.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.rv_timer_random.1671726345
Short name T249
Test name
Test status
Simulation time 289542842021 ps
CPU time 309.77 seconds
Started Jul 26 04:48:49 PM PDT 24
Finished Jul 26 04:53:59 PM PDT 24
Peak memory 191508 kb
Host smart-fbaeb5ee-2c2d-486a-9a99-ddeddb0be3ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671726345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.1671726345
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.837188915
Short name T321
Test name
Test status
Simulation time 977966059949 ps
CPU time 1803.85 seconds
Started Jul 26 04:48:23 PM PDT 24
Finished Jul 26 05:18:28 PM PDT 24
Peak memory 191696 kb
Host smart-2001dcef-7b0a-4129-afcd-128decca1889
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837188915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.837188915
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.3985830557
Short name T3
Test name
Test status
Simulation time 156975006878 ps
CPU time 267.65 seconds
Started Jul 26 04:48:11 PM PDT 24
Finished Jul 26 04:52:38 PM PDT 24
Peak memory 193352 kb
Host smart-13dec82e-e5b4-41d5-b808-df2153cdbcfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985830557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.3985830557
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.1197438505
Short name T301
Test name
Test status
Simulation time 29887416525 ps
CPU time 44.36 seconds
Started Jul 26 04:48:25 PM PDT 24
Finished Jul 26 04:49:10 PM PDT 24
Peak memory 183500 kb
Host smart-d1e4d470-2f27-486f-b582-1d154c0f0616
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197438505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.1197438505
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.1139351978
Short name T73
Test name
Test status
Simulation time 51273385403 ps
CPU time 155.25 seconds
Started Jul 26 04:48:25 PM PDT 24
Finished Jul 26 04:51:00 PM PDT 24
Peak memory 191624 kb
Host smart-ee80d71d-45ff-4924-b70c-35bcc2bfe1ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139351978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.1139351978
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.3955625314
Short name T297
Test name
Test status
Simulation time 93649893720 ps
CPU time 58.68 seconds
Started Jul 26 04:48:37 PM PDT 24
Finished Jul 26 04:49:36 PM PDT 24
Peak memory 183376 kb
Host smart-a1a6f469-859e-4e03-a492-0c6f3be19abc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955625314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.3955625314
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.708038027
Short name T313
Test name
Test status
Simulation time 167778025163 ps
CPU time 144.71 seconds
Started Jul 26 04:47:51 PM PDT 24
Finished Jul 26 04:50:16 PM PDT 24
Peak memory 183384 kb
Host smart-2375ed05-fe14-4060-bf3b-43d7686a82e1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708038027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.rv_timer_cfg_update_on_fly.708038027
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.761733631
Short name T387
Test name
Test status
Simulation time 220381130352 ps
CPU time 45.51 seconds
Started Jul 26 04:47:44 PM PDT 24
Finished Jul 26 04:48:30 PM PDT 24
Peak memory 183364 kb
Host smart-ebb6fdd1-a774-4339-a16d-1523321f04b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761733631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.761733631
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.2236971854
Short name T210
Test name
Test status
Simulation time 127768661883 ps
CPU time 244.19 seconds
Started Jul 26 04:47:53 PM PDT 24
Finished Jul 26 04:51:58 PM PDT 24
Peak memory 191612 kb
Host smart-1249aab5-3b44-4e1d-b584-013c1f6b90a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236971854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.2236971854
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.1839426575
Short name T199
Test name
Test status
Simulation time 41035100615 ps
CPU time 54.12 seconds
Started Jul 26 04:48:02 PM PDT 24
Finished Jul 26 04:48:56 PM PDT 24
Peak memory 183196 kb
Host smart-bbf4b1e5-62ae-4f7b-8dab-04aacd3f0468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839426575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.1839426575
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.3166697832
Short name T425
Test name
Test status
Simulation time 154873699923 ps
CPU time 107.76 seconds
Started Jul 26 04:47:40 PM PDT 24
Finished Jul 26 04:49:28 PM PDT 24
Peak memory 183364 kb
Host smart-1b2b12d5-3238-4b3c-9c8e-52ae32df90d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166697832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.3166697832
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all_with_rand_reset.432491691
Short name T39
Test name
Test status
Simulation time 13422631289 ps
CPU time 132.11 seconds
Started Jul 26 04:48:05 PM PDT 24
Finished Jul 26 04:50:17 PM PDT 24
Peak memory 198104 kb
Host smart-e8ac8b15-e7f6-4aba-9042-2fcaf2308308
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432491691 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all_with_rand_reset.432491691
Directory /workspace/19.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.428163960
Short name T264
Test name
Test status
Simulation time 154686629079 ps
CPU time 309.18 seconds
Started Jul 26 04:48:32 PM PDT 24
Finished Jul 26 04:53:42 PM PDT 24
Peak memory 191704 kb
Host smart-4569d44b-b4e1-4b48-aa23-b19e08d3758a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428163960 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.428163960
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.1149200418
Short name T20
Test name
Test status
Simulation time 159756717948 ps
CPU time 71.59 seconds
Started Jul 26 04:48:20 PM PDT 24
Finished Jul 26 04:49:32 PM PDT 24
Peak memory 191564 kb
Host smart-8a254bef-e96e-4e79-9e7a-48c47e157a1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149200418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.1149200418
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.1531908522
Short name T140
Test name
Test status
Simulation time 258535834825 ps
CPU time 893.43 seconds
Started Jul 26 04:48:32 PM PDT 24
Finished Jul 26 05:03:26 PM PDT 24
Peak memory 191616 kb
Host smart-a83bc57f-a892-479f-b8b5-11c86157432c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531908522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.1531908522
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.1028124542
Short name T285
Test name
Test status
Simulation time 173103350595 ps
CPU time 261.55 seconds
Started Jul 26 04:48:27 PM PDT 24
Finished Jul 26 04:52:49 PM PDT 24
Peak memory 191548 kb
Host smart-4bada73f-70f8-46c7-840d-dc206833b29e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028124542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.1028124542
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.2034658863
Short name T58
Test name
Test status
Simulation time 65127308558 ps
CPU time 37.84 seconds
Started Jul 26 04:48:20 PM PDT 24
Finished Jul 26 04:48:58 PM PDT 24
Peak memory 191576 kb
Host smart-8be2e8cb-25a6-4866-be11-ad720b0a8c41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034658863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.2034658863
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.2037756054
Short name T303
Test name
Test status
Simulation time 503754520748 ps
CPU time 555.28 seconds
Started Jul 26 04:48:34 PM PDT 24
Finished Jul 26 04:57:49 PM PDT 24
Peak memory 191612 kb
Host smart-d1af28d9-c452-46e1-8565-49485e11c153
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037756054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.2037756054
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.1877795548
Short name T454
Test name
Test status
Simulation time 1231236621041 ps
CPU time 400.41 seconds
Started Jul 26 04:47:42 PM PDT 24
Finished Jul 26 04:54:23 PM PDT 24
Peak memory 183496 kb
Host smart-9aea40af-13fc-46ec-ae9f-2e2ef6f2db39
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877795548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.1877795548
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.148215658
Short name T381
Test name
Test status
Simulation time 181383829679 ps
CPU time 263.44 seconds
Started Jul 26 04:47:44 PM PDT 24
Finished Jul 26 04:52:07 PM PDT 24
Peak memory 183348 kb
Host smart-1f15e6c2-bf1b-40e3-bdcf-1adb71244278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148215658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.148215658
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.3362387206
Short name T150
Test name
Test status
Simulation time 158098371997 ps
CPU time 2095.96 seconds
Started Jul 26 04:47:40 PM PDT 24
Finished Jul 26 05:22:36 PM PDT 24
Peak memory 191560 kb
Host smart-0fe57ec6-1ad8-46da-97e3-9fd77deff72e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362387206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.3362387206
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.631620796
Short name T271
Test name
Test status
Simulation time 174397023265 ps
CPU time 104.11 seconds
Started Jul 26 04:47:41 PM PDT 24
Finished Jul 26 04:49:25 PM PDT 24
Peak memory 195156 kb
Host smart-f0895e88-5131-47bb-9c84-97613f2a4149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631620796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.631620796
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.1709103222
Short name T15
Test name
Test status
Simulation time 79611484 ps
CPU time 0.86 seconds
Started Jul 26 04:47:37 PM PDT 24
Finished Jul 26 04:47:38 PM PDT 24
Peak memory 214728 kb
Host smart-5ae26f96-8508-4e6d-836a-52c1b66d2063
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709103222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.1709103222
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.1685139677
Short name T366
Test name
Test status
Simulation time 499289441347 ps
CPU time 181.54 seconds
Started Jul 26 04:47:45 PM PDT 24
Finished Jul 26 04:50:46 PM PDT 24
Peak memory 183512 kb
Host smart-c1778f39-d14e-4f2a-b0d1-ff613926923d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685139677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.1685139677
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.1086129502
Short name T311
Test name
Test status
Simulation time 175947106649 ps
CPU time 173.43 seconds
Started Jul 26 04:47:43 PM PDT 24
Finished Jul 26 04:50:37 PM PDT 24
Peak memory 191576 kb
Host smart-66617da0-8de3-47f0-813d-53e85a619473
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086129502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.1086129502
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.149773726
Short name T45
Test name
Test status
Simulation time 182399010246 ps
CPU time 373.55 seconds
Started Jul 26 04:47:50 PM PDT 24
Finished Jul 26 04:54:04 PM PDT 24
Peak memory 183356 kb
Host smart-07a2492a-6547-4d06-89e9-894af7c804aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149773726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.149773726
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.2561305284
Short name T294
Test name
Test status
Simulation time 430203946321 ps
CPU time 837.33 seconds
Started Jul 26 04:48:01 PM PDT 24
Finished Jul 26 05:01:59 PM PDT 24
Peak memory 196004 kb
Host smart-506119db-92fc-4db2-a37a-949bd868acc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561305284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.2561305284
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.615263013
Short name T452
Test name
Test status
Simulation time 10754234820 ps
CPU time 17.6 seconds
Started Jul 26 04:47:45 PM PDT 24
Finished Jul 26 04:48:03 PM PDT 24
Peak memory 183376 kb
Host smart-f03a7d13-964d-40f3-8c0c-89111f39b868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615263013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.615263013
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.3014458866
Short name T234
Test name
Test status
Simulation time 6881790118 ps
CPU time 13.22 seconds
Started Jul 26 04:47:59 PM PDT 24
Finished Jul 26 04:48:12 PM PDT 24
Peak memory 183376 kb
Host smart-87370b5d-2bd3-4838-8c12-d4ec74ea790b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014458866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.3014458866
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.2054715072
Short name T391
Test name
Test status
Simulation time 124202776 ps
CPU time 0.54 seconds
Started Jul 26 04:47:38 PM PDT 24
Finished Jul 26 04:47:38 PM PDT 24
Peak memory 183104 kb
Host smart-deaa8e04-c4e5-4a05-8a17-f5b1bafdf2d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054715072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.2054715072
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.182824170
Short name T153
Test name
Test status
Simulation time 261332337237 ps
CPU time 382.63 seconds
Started Jul 26 04:47:51 PM PDT 24
Finished Jul 26 04:54:15 PM PDT 24
Peak memory 183260 kb
Host smart-2ccb0dca-b569-4c4e-a4ab-7f558011c7d2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182824170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.rv_timer_cfg_update_on_fly.182824170
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.2816207170
Short name T440
Test name
Test status
Simulation time 204286694847 ps
CPU time 146.18 seconds
Started Jul 26 04:47:47 PM PDT 24
Finished Jul 26 04:50:13 PM PDT 24
Peak memory 183420 kb
Host smart-a1db2b33-8159-4dab-8f80-45ea19b04117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816207170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.2816207170
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.54307930
Short name T221
Test name
Test status
Simulation time 530713074878 ps
CPU time 194.98 seconds
Started Jul 26 04:47:52 PM PDT 24
Finished Jul 26 04:51:07 PM PDT 24
Peak memory 191588 kb
Host smart-f98fe583-5a60-4dff-b6af-c58a99598632
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54307930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.54307930
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.3276562304
Short name T284
Test name
Test status
Simulation time 358172823308 ps
CPU time 201.22 seconds
Started Jul 26 04:47:44 PM PDT 24
Finished Jul 26 04:51:05 PM PDT 24
Peak memory 183508 kb
Host smart-4f6ba7e8-c098-45bf-8994-f5252ac1544d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276562304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.3276562304
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.733673902
Short name T414
Test name
Test status
Simulation time 1141821168836 ps
CPU time 141.22 seconds
Started Jul 26 04:47:50 PM PDT 24
Finished Jul 26 04:50:11 PM PDT 24
Peak memory 183400 kb
Host smart-f49e9fd5-9fde-4119-aa08-0e5aa78ed987
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733673902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all.
733673902
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all_with_rand_reset.1195232459
Short name T416
Test name
Test status
Simulation time 5734530347 ps
CPU time 60.35 seconds
Started Jul 26 04:48:13 PM PDT 24
Finished Jul 26 04:49:14 PM PDT 24
Peak memory 198092 kb
Host smart-b8803aec-aa8c-4818-b713-8a5937de4040
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195232459 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all_with_rand_reset.1195232459
Directory /workspace/22.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.988933095
Short name T147
Test name
Test status
Simulation time 263816787072 ps
CPU time 144.63 seconds
Started Jul 26 04:47:52 PM PDT 24
Finished Jul 26 04:50:17 PM PDT 24
Peak memory 183384 kb
Host smart-b3a143ef-5362-4187-b581-2883b61a53ee
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988933095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.rv_timer_cfg_update_on_fly.988933095
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.868018403
Short name T43
Test name
Test status
Simulation time 331138308387 ps
CPU time 135.31 seconds
Started Jul 26 04:47:47 PM PDT 24
Finished Jul 26 04:50:03 PM PDT 24
Peak memory 183408 kb
Host smart-69501e42-6e97-43b3-a26a-f49194ec5dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868018403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.868018403
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.3150537082
Short name T429
Test name
Test status
Simulation time 447009068738 ps
CPU time 240.7 seconds
Started Jul 26 04:47:44 PM PDT 24
Finished Jul 26 04:51:45 PM PDT 24
Peak memory 191548 kb
Host smart-f3b5add5-8684-48b1-a509-b8bb222031b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150537082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.3150537082
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.1026505118
Short name T332
Test name
Test status
Simulation time 407044329504 ps
CPU time 469.38 seconds
Started Jul 26 04:47:53 PM PDT 24
Finished Jul 26 04:55:43 PM PDT 24
Peak memory 191616 kb
Host smart-4e973f1e-bd51-41b9-83eb-86e0944e07f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026505118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.1026505118
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.2762939282
Short name T34
Test name
Test status
Simulation time 23093059 ps
CPU time 0.55 seconds
Started Jul 26 04:47:54 PM PDT 24
Finished Jul 26 04:47:55 PM PDT 24
Peak memory 182756 kb
Host smart-5018da83-45f0-41f5-93ad-bcf97d011559
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762939282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.2762939282
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.2157639899
Short name T37
Test name
Test status
Simulation time 91845859624 ps
CPU time 955.37 seconds
Started Jul 26 04:48:16 PM PDT 24
Finished Jul 26 05:04:12 PM PDT 24
Peak memory 209976 kb
Host smart-18ce04e6-7af8-4795-820c-41862642a810
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157639899 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_reset.2157639899
Directory /workspace/23.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.3974284796
Short name T444
Test name
Test status
Simulation time 113736779245 ps
CPU time 169.08 seconds
Started Jul 26 04:47:48 PM PDT 24
Finished Jul 26 04:50:37 PM PDT 24
Peak memory 183380 kb
Host smart-8e906d34-4b6d-4486-b498-10ae0a47bafe
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974284796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.3974284796
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.3634544027
Short name T379
Test name
Test status
Simulation time 120295172015 ps
CPU time 184.62 seconds
Started Jul 26 04:48:01 PM PDT 24
Finished Jul 26 04:51:06 PM PDT 24
Peak memory 183388 kb
Host smart-ae44bb5c-ae9b-45e5-b7fa-d6a82460567e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634544027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.3634544027
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.2810180642
Short name T189
Test name
Test status
Simulation time 195260903930 ps
CPU time 135.28 seconds
Started Jul 26 04:47:50 PM PDT 24
Finished Jul 26 04:50:05 PM PDT 24
Peak memory 191584 kb
Host smart-3fab6b87-500e-473c-85d7-5b66d551d517
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810180642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.2810180642
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.3301226559
Short name T372
Test name
Test status
Simulation time 26023362468 ps
CPU time 15.48 seconds
Started Jul 26 04:47:44 PM PDT 24
Finished Jul 26 04:47:59 PM PDT 24
Peak memory 183416 kb
Host smart-80adc96b-4c77-4590-837c-558223db27c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301226559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.3301226559
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.2998606546
Short name T1
Test name
Test status
Simulation time 168219478768 ps
CPU time 250.07 seconds
Started Jul 26 04:47:42 PM PDT 24
Finished Jul 26 04:51:52 PM PDT 24
Peak memory 191596 kb
Host smart-0ed4d99c-3804-42b7-a62e-164cc2bc2e9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998606546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.2998606546
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all_with_rand_reset.2010679558
Short name T36
Test name
Test status
Simulation time 171830130934 ps
CPU time 624.89 seconds
Started Jul 26 04:47:58 PM PDT 24
Finished Jul 26 04:58:23 PM PDT 24
Peak memory 207380 kb
Host smart-ebc2cbee-992a-43f6-a752-14e1a7d6583c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010679558 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all_with_rand_reset.2010679558
Directory /workspace/24.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.2823842379
Short name T263
Test name
Test status
Simulation time 209838295771 ps
CPU time 181.36 seconds
Started Jul 26 04:47:50 PM PDT 24
Finished Jul 26 04:50:52 PM PDT 24
Peak memory 183328 kb
Host smart-b51d0ce9-84bf-455d-a43a-6faf6c60a91b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823842379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.2823842379
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.1168427219
Short name T426
Test name
Test status
Simulation time 546912147467 ps
CPU time 220.54 seconds
Started Jul 26 04:47:49 PM PDT 24
Finished Jul 26 04:51:30 PM PDT 24
Peak memory 183312 kb
Host smart-1b266852-f665-4428-a0b1-a2e7898fcc06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168427219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.1168427219
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.982284253
Short name T338
Test name
Test status
Simulation time 399540183166 ps
CPU time 890.59 seconds
Started Jul 26 04:48:07 PM PDT 24
Finished Jul 26 05:02:58 PM PDT 24
Peak memory 183360 kb
Host smart-45109a65-0fbc-4fa8-a15d-99e2b41edb5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982284253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.982284253
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.488741324
Short name T423
Test name
Test status
Simulation time 150427560382 ps
CPU time 42.67 seconds
Started Jul 26 04:47:58 PM PDT 24
Finished Jul 26 04:48:40 PM PDT 24
Peak memory 183320 kb
Host smart-4997f16a-730a-4e9b-bb95-f70f76f170d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488741324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.488741324
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all_with_rand_reset.3022047367
Short name T40
Test name
Test status
Simulation time 177695174168 ps
CPU time 336.36 seconds
Started Jul 26 04:47:51 PM PDT 24
Finished Jul 26 04:53:27 PM PDT 24
Peak memory 206232 kb
Host smart-b80d9a1c-3022-499d-9591-12018036e93d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022047367 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all_with_rand_reset.3022047367
Directory /workspace/25.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.4147679735
Short name T305
Test name
Test status
Simulation time 55140546467 ps
CPU time 24.33 seconds
Started Jul 26 04:48:08 PM PDT 24
Finished Jul 26 04:48:33 PM PDT 24
Peak memory 183428 kb
Host smart-22b95c2a-4718-4ef3-bb25-f290be8c9383
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147679735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.4147679735
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.3173767986
Short name T390
Test name
Test status
Simulation time 255767820432 ps
CPU time 87.72 seconds
Started Jul 26 04:47:56 PM PDT 24
Finished Jul 26 04:49:23 PM PDT 24
Peak memory 183416 kb
Host smart-66f3aab7-7677-499a-9628-4bd31cacaf39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173767986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.3173767986
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.4240741686
Short name T393
Test name
Test status
Simulation time 624043319363 ps
CPU time 254.56 seconds
Started Jul 26 04:48:01 PM PDT 24
Finished Jul 26 04:52:16 PM PDT 24
Peak memory 191548 kb
Host smart-6a32cb84-84cd-44ea-8a87-9e7fba5bfc86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240741686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.4240741686
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.3557595394
Short name T376
Test name
Test status
Simulation time 34820900361 ps
CPU time 16.86 seconds
Started Jul 26 04:47:57 PM PDT 24
Finished Jul 26 04:48:14 PM PDT 24
Peak memory 194896 kb
Host smart-e8265621-0e54-44de-9ef1-1ed5fdd735ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557595394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.3557595394
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.2902137162
Short name T66
Test name
Test status
Simulation time 1827183058642 ps
CPU time 955.75 seconds
Started Jul 26 04:47:50 PM PDT 24
Finished Jul 26 05:03:47 PM PDT 24
Peak memory 195952 kb
Host smart-f4b52ff4-7ae9-4491-9cb7-488ff3243a4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902137162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.2902137162
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.3119891263
Short name T77
Test name
Test status
Simulation time 109768135855 ps
CPU time 167.36 seconds
Started Jul 26 04:47:49 PM PDT 24
Finished Jul 26 04:50:37 PM PDT 24
Peak memory 183352 kb
Host smart-4af55d6c-53b9-4828-ba34-41800c62be45
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119891263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.3119891263
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.2397493491
Short name T365
Test name
Test status
Simulation time 307870155615 ps
CPU time 114.62 seconds
Started Jul 26 04:48:05 PM PDT 24
Finished Jul 26 04:50:00 PM PDT 24
Peak memory 183384 kb
Host smart-e5eefd6f-569a-473d-a3cf-1a638f26cf4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397493491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.2397493491
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.4164084333
Short name T345
Test name
Test status
Simulation time 81860042857 ps
CPU time 38.97 seconds
Started Jul 26 04:48:10 PM PDT 24
Finished Jul 26 04:48:49 PM PDT 24
Peak memory 191612 kb
Host smart-fc262ac8-713c-4130-9fee-d77f6ede0fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164084333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.4164084333
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all_with_rand_reset.3299633604
Short name T450
Test name
Test status
Simulation time 13257614170 ps
CPU time 137.54 seconds
Started Jul 26 04:47:59 PM PDT 24
Finished Jul 26 04:50:17 PM PDT 24
Peak memory 198064 kb
Host smart-f294de9c-1ac6-4c38-8e91-d70ea1cbf38b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299633604 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all_with_rand_reset.3299633604
Directory /workspace/27.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.128161761
Short name T350
Test name
Test status
Simulation time 796797231074 ps
CPU time 408.13 seconds
Started Jul 26 04:48:08 PM PDT 24
Finished Jul 26 04:54:56 PM PDT 24
Peak memory 183296 kb
Host smart-28331ca7-f09c-4252-9592-459c729bc2b7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128161761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.rv_timer_cfg_update_on_fly.128161761
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.501151812
Short name T436
Test name
Test status
Simulation time 261357303012 ps
CPU time 259.15 seconds
Started Jul 26 04:48:03 PM PDT 24
Finished Jul 26 04:52:22 PM PDT 24
Peak memory 183376 kb
Host smart-cbbc016b-01d2-493c-9d53-005a3f5a6d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501151812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.501151812
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.1602221758
Short name T236
Test name
Test status
Simulation time 351376685352 ps
CPU time 200.38 seconds
Started Jul 26 04:48:07 PM PDT 24
Finished Jul 26 04:51:28 PM PDT 24
Peak memory 192596 kb
Host smart-0f8428c7-4738-42eb-856f-cbdb624bc307
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602221758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.1602221758
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.1894321706
Short name T203
Test name
Test status
Simulation time 115357197292 ps
CPU time 257.1 seconds
Started Jul 26 04:48:03 PM PDT 24
Finished Jul 26 04:52:20 PM PDT 24
Peak memory 191712 kb
Host smart-e3f28761-2623-4dab-ba63-acff4212cce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894321706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.1894321706
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.2768358525
Short name T443
Test name
Test status
Simulation time 508327368903 ps
CPU time 808.95 seconds
Started Jul 26 04:48:06 PM PDT 24
Finished Jul 26 05:01:35 PM PDT 24
Peak memory 183296 kb
Host smart-f95e851c-060e-472d-81ea-cbfd1cac01ce
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768358525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.2768358525
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.899186116
Short name T62
Test name
Test status
Simulation time 62747787610 ps
CPU time 93.33 seconds
Started Jul 26 04:47:53 PM PDT 24
Finished Jul 26 04:49:27 PM PDT 24
Peak memory 183420 kb
Host smart-1e7a4d84-5ff2-4626-a2bd-ab16d93bb8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899186116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.899186116
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.1314037137
Short name T135
Test name
Test status
Simulation time 193381046547 ps
CPU time 79.96 seconds
Started Jul 26 04:47:51 PM PDT 24
Finished Jul 26 04:49:12 PM PDT 24
Peak memory 191584 kb
Host smart-4f7eec74-9413-4980-887b-b8e1ce8d9e0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314037137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.1314037137
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.3691562271
Short name T275
Test name
Test status
Simulation time 175649196602 ps
CPU time 117.03 seconds
Started Jul 26 04:47:51 PM PDT 24
Finished Jul 26 04:49:48 PM PDT 24
Peak memory 183388 kb
Host smart-ef195194-0279-44c6-a758-0804c723a853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691562271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.3691562271
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.3118933398
Short name T219
Test name
Test status
Simulation time 510017834018 ps
CPU time 683.82 seconds
Started Jul 26 04:48:16 PM PDT 24
Finished Jul 26 04:59:40 PM PDT 24
Peak memory 194664 kb
Host smart-5a18e4f3-8066-4a38-92cc-a19ba6be09cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118933398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.3118933398
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.604345284
Short name T375
Test name
Test status
Simulation time 137765502562 ps
CPU time 52.3 seconds
Started Jul 26 04:47:42 PM PDT 24
Finished Jul 26 04:48:35 PM PDT 24
Peak memory 183404 kb
Host smart-59458819-542f-48b7-9939-a540e50c5365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604345284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.604345284
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.4045917699
Short name T195
Test name
Test status
Simulation time 129851034292 ps
CPU time 203.8 seconds
Started Jul 26 04:47:42 PM PDT 24
Finished Jul 26 04:51:06 PM PDT 24
Peak memory 191576 kb
Host smart-14c5b7c5-7545-4aee-a3d2-b45b36cb166d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045917699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.4045917699
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.255647911
Short name T141
Test name
Test status
Simulation time 69001124144 ps
CPU time 174.02 seconds
Started Jul 26 04:47:45 PM PDT 24
Finished Jul 26 04:50:39 PM PDT 24
Peak memory 194940 kb
Host smart-a231d3c5-7b46-452f-beff-1e81b480aa02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255647911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.255647911
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.2263265631
Short name T17
Test name
Test status
Simulation time 37914385 ps
CPU time 0.75 seconds
Started Jul 26 04:47:52 PM PDT 24
Finished Jul 26 04:47:53 PM PDT 24
Peak memory 214056 kb
Host smart-c5ef381b-68f8-43c2-b742-4bf9d78e0387
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263265631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.2263265631
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.2156252709
Short name T336
Test name
Test status
Simulation time 2151005446252 ps
CPU time 1252.58 seconds
Started Jul 26 04:47:33 PM PDT 24
Finished Jul 26 05:08:26 PM PDT 24
Peak memory 196244 kb
Host smart-4d8fc296-ddb1-44b0-b578-411c06290f3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156252709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
2156252709
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.2862623436
Short name T418
Test name
Test status
Simulation time 734662316129 ps
CPU time 161.95 seconds
Started Jul 26 04:48:09 PM PDT 24
Finished Jul 26 04:50:51 PM PDT 24
Peak memory 183304 kb
Host smart-65649d25-b065-4298-bb45-6c9fa14f61e6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862623436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.2862623436
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.3088253933
Short name T399
Test name
Test status
Simulation time 73095510448 ps
CPU time 100.52 seconds
Started Jul 26 04:48:10 PM PDT 24
Finished Jul 26 04:49:50 PM PDT 24
Peak memory 183408 kb
Host smart-d3171192-83c7-4a43-bc89-80c5025c395f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088253933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.3088253933
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.1881631626
Short name T257
Test name
Test status
Simulation time 105088077829 ps
CPU time 457.07 seconds
Started Jul 26 04:47:49 PM PDT 24
Finished Jul 26 04:55:26 PM PDT 24
Peak memory 191604 kb
Host smart-065f13d4-1cc8-45b7-9abd-5e342aa5b133
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881631626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.1881631626
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.943826180
Short name T206
Test name
Test status
Simulation time 1785573693070 ps
CPU time 1407.87 seconds
Started Jul 26 04:48:09 PM PDT 24
Finished Jul 26 05:11:37 PM PDT 24
Peak memory 195748 kb
Host smart-03cc67bf-dcac-4ac9-a1be-5be3a1be03e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943826180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all.
943826180
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.122850738
Short name T26
Test name
Test status
Simulation time 170979450166 ps
CPU time 162.68 seconds
Started Jul 26 04:48:11 PM PDT 24
Finished Jul 26 04:50:54 PM PDT 24
Peak memory 183312 kb
Host smart-ebbf7cf1-76f7-4850-8eee-80e110423a10
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122850738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.rv_timer_cfg_update_on_fly.122850738
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.3654591704
Short name T369
Test name
Test status
Simulation time 79007178008 ps
CPU time 105.86 seconds
Started Jul 26 04:47:59 PM PDT 24
Finished Jul 26 04:49:45 PM PDT 24
Peak memory 183392 kb
Host smart-47c7914b-1ad5-45af-ba6b-a8b9c6dd7a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654591704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.3654591704
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.2944736591
Short name T202
Test name
Test status
Simulation time 94140680607 ps
CPU time 144.52 seconds
Started Jul 26 04:48:05 PM PDT 24
Finished Jul 26 04:50:30 PM PDT 24
Peak memory 191572 kb
Host smart-f37625c9-43c8-4fd3-82fe-7f2b9db952ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944736591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.2944736591
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.2110942365
Short name T385
Test name
Test status
Simulation time 42906623212 ps
CPU time 32.14 seconds
Started Jul 26 04:48:05 PM PDT 24
Finished Jul 26 04:48:37 PM PDT 24
Peak memory 183408 kb
Host smart-bbd5d406-550f-413c-9592-3b68d28ad2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110942365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.2110942365
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.70185711
Short name T60
Test name
Test status
Simulation time 49648070733 ps
CPU time 17.89 seconds
Started Jul 26 04:48:16 PM PDT 24
Finished Jul 26 04:48:34 PM PDT 24
Peak memory 183296 kb
Host smart-0c4b6acb-341e-4906-a4f0-dbad9e984358
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70185711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.rv_timer_cfg_update_on_fly.70185711
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.1857749511
Short name T445
Test name
Test status
Simulation time 78848514653 ps
CPU time 32.55 seconds
Started Jul 26 04:48:05 PM PDT 24
Finished Jul 26 04:48:38 PM PDT 24
Peak memory 183400 kb
Host smart-4542db00-2204-47a9-b4bf-58d4d7b15e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857749511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.1857749511
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.325560492
Short name T208
Test name
Test status
Simulation time 717093142081 ps
CPU time 489.23 seconds
Started Jul 26 04:48:05 PM PDT 24
Finished Jul 26 04:56:14 PM PDT 24
Peak memory 191592 kb
Host smart-8a7aca05-7e55-4196-a382-743c8c621704
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325560492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.325560492
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.455988459
Short name T437
Test name
Test status
Simulation time 875000392 ps
CPU time 1.24 seconds
Started Jul 26 04:48:07 PM PDT 24
Finished Jul 26 04:48:08 PM PDT 24
Peak memory 191544 kb
Host smart-3e98617b-b3b6-4c46-9f7b-99e1d5ecec08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455988459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.455988459
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.4193937638
Short name T384
Test name
Test status
Simulation time 79672704647 ps
CPU time 112.64 seconds
Started Jul 26 04:47:58 PM PDT 24
Finished Jul 26 04:49:51 PM PDT 24
Peak memory 183520 kb
Host smart-d6d26579-8f67-4008-b646-0adc70a2c8ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193937638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.4193937638
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.2283272663
Short name T44
Test name
Test status
Simulation time 198657550423 ps
CPU time 158.73 seconds
Started Jul 26 04:48:06 PM PDT 24
Finished Jul 26 04:50:50 PM PDT 24
Peak memory 183368 kb
Host smart-dbf64597-9e24-47da-8e20-346b5703a491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283272663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.2283272663
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.3801589719
Short name T441
Test name
Test status
Simulation time 3263889419 ps
CPU time 2.37 seconds
Started Jul 26 04:47:58 PM PDT 24
Finished Jul 26 04:48:00 PM PDT 24
Peak memory 183312 kb
Host smart-91273f6b-7e85-450c-8d97-5b54a28b33c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801589719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.3801589719
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.2123096719
Short name T310
Test name
Test status
Simulation time 61750621206 ps
CPU time 144.61 seconds
Started Jul 26 04:48:02 PM PDT 24
Finished Jul 26 04:50:27 PM PDT 24
Peak memory 191572 kb
Host smart-3d63edf1-ce4c-4754-8654-8d8f4cf0cc3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123096719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.2123096719
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.2385142060
Short name T412
Test name
Test status
Simulation time 828140237975 ps
CPU time 717.48 seconds
Started Jul 26 04:48:03 PM PDT 24
Finished Jul 26 05:00:01 PM PDT 24
Peak memory 183348 kb
Host smart-50d58ca4-821e-405b-a928-97729e082081
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385142060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.2385142060
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_random.1792369196
Short name T253
Test name
Test status
Simulation time 300831467572 ps
CPU time 963.01 seconds
Started Jul 26 04:48:12 PM PDT 24
Finished Jul 26 05:04:16 PM PDT 24
Peak memory 191564 kb
Host smart-d14c0795-2f30-443b-8f80-565e74890fd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792369196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.1792369196
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.1401331877
Short name T300
Test name
Test status
Simulation time 171049796955 ps
CPU time 660.94 seconds
Started Jul 26 04:48:12 PM PDT 24
Finished Jul 26 04:59:13 PM PDT 24
Peak memory 193956 kb
Host smart-ec5bef5f-42a9-4a8e-b20d-0a1596a1a092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401331877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.1401331877
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.3882674246
Short name T282
Test name
Test status
Simulation time 1569655145702 ps
CPU time 517.22 seconds
Started Jul 26 04:48:00 PM PDT 24
Finished Jul 26 04:56:37 PM PDT 24
Peak memory 183508 kb
Host smart-3da35f45-1169-41fb-b406-5acb5a32babb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882674246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.3882674246
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.1713874222
Short name T406
Test name
Test status
Simulation time 11401621819 ps
CPU time 16.97 seconds
Started Jul 26 04:48:03 PM PDT 24
Finished Jul 26 04:48:25 PM PDT 24
Peak memory 183400 kb
Host smart-7b410908-bf28-4649-a106-d34363389536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713874222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.1713874222
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.754941488
Short name T256
Test name
Test status
Simulation time 214356635734 ps
CPU time 1414.15 seconds
Started Jul 26 04:48:05 PM PDT 24
Finished Jul 26 05:11:39 PM PDT 24
Peak memory 191620 kb
Host smart-7ca0522d-0d91-48ff-bd38-9da68369b28b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754941488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.754941488
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.4040963994
Short name T299
Test name
Test status
Simulation time 747705529810 ps
CPU time 2390.67 seconds
Started Jul 26 04:48:08 PM PDT 24
Finished Jul 26 05:27:59 PM PDT 24
Peak memory 191620 kb
Host smart-eab8ac24-28ca-4aa5-b98a-4f548e776b18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040963994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.4040963994
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all_with_rand_reset.1925508378
Short name T41
Test name
Test status
Simulation time 100407958776 ps
CPU time 278.48 seconds
Started Jul 26 04:48:00 PM PDT 24
Finished Jul 26 04:52:38 PM PDT 24
Peak memory 206424 kb
Host smart-b3b93650-7423-4ed0-883d-b9642c78efe9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925508378 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all_with_rand_reset.1925508378
Directory /workspace/35.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.2285988744
Short name T439
Test name
Test status
Simulation time 1545495043701 ps
CPU time 531.15 seconds
Started Jul 26 04:48:06 PM PDT 24
Finished Jul 26 04:56:57 PM PDT 24
Peak memory 183348 kb
Host smart-c2ad5fe5-1744-41f2-9c03-5cfb5a34907c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285988744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.2285988744
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.3264430211
Short name T396
Test name
Test status
Simulation time 289825412218 ps
CPU time 102.29 seconds
Started Jul 26 04:47:53 PM PDT 24
Finished Jul 26 04:49:36 PM PDT 24
Peak memory 183328 kb
Host smart-5b705935-22e5-4a82-a774-b57cd7c6f0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264430211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.3264430211
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.1255129774
Short name T276
Test name
Test status
Simulation time 214825206005 ps
CPU time 158.13 seconds
Started Jul 26 04:47:57 PM PDT 24
Finished Jul 26 04:50:35 PM PDT 24
Peak memory 195496 kb
Host smart-dfa955aa-54dd-4448-bb34-221f109e4469
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255129774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.1255129774
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.258045455
Short name T356
Test name
Test status
Simulation time 51778073911 ps
CPU time 112.54 seconds
Started Jul 26 04:48:05 PM PDT 24
Finished Jul 26 04:49:58 PM PDT 24
Peak memory 191576 kb
Host smart-14860792-51b0-4a41-b3b9-eebbb48edeb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258045455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.258045455
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.2878508233
Short name T229
Test name
Test status
Simulation time 309973045297 ps
CPU time 155 seconds
Started Jul 26 04:47:56 PM PDT 24
Finished Jul 26 04:50:31 PM PDT 24
Peak memory 183344 kb
Host smart-fef4560b-ffcb-49f5-bdeb-1e6b8b59ef9f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878508233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.2878508233
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_random.1809955725
Short name T361
Test name
Test status
Simulation time 198270936352 ps
CPU time 273.52 seconds
Started Jul 26 04:48:05 PM PDT 24
Finished Jul 26 04:52:39 PM PDT 24
Peak memory 191528 kb
Host smart-c0b62ed9-5fbb-4ebf-bc59-ec1508b3b297
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809955725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.1809955725
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.510011197
Short name T451
Test name
Test status
Simulation time 119017099515 ps
CPU time 194.26 seconds
Started Jul 26 04:48:11 PM PDT 24
Finished Jul 26 04:51:26 PM PDT 24
Peak memory 193908 kb
Host smart-585b4bec-2e44-4602-b8fa-8d4c63654538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510011197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.510011197
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.539199271
Short name T421
Test name
Test status
Simulation time 168070862 ps
CPU time 0.52 seconds
Started Jul 26 04:47:52 PM PDT 24
Finished Jul 26 04:47:52 PM PDT 24
Peak memory 182756 kb
Host smart-2f09c8d7-d274-40e9-8d42-d3f12f349ece
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539199271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all.
539199271
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.2581862702
Short name T261
Test name
Test status
Simulation time 2298390892339 ps
CPU time 1006.05 seconds
Started Jul 26 04:47:55 PM PDT 24
Finished Jul 26 05:04:41 PM PDT 24
Peak memory 183384 kb
Host smart-5ade9d12-cef8-406f-ab3e-748b36372cca
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581862702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.2581862702
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.455067307
Short name T401
Test name
Test status
Simulation time 46188657285 ps
CPU time 36.64 seconds
Started Jul 26 04:48:16 PM PDT 24
Finished Jul 26 04:48:53 PM PDT 24
Peak memory 183416 kb
Host smart-d5a3c4d8-b749-48f8-a1f2-70ee72e5e139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455067307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.455067307
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.330401147
Short name T205
Test name
Test status
Simulation time 169853141903 ps
CPU time 66.14 seconds
Started Jul 26 04:47:54 PM PDT 24
Finished Jul 26 04:49:01 PM PDT 24
Peak memory 191620 kb
Host smart-52eff383-1428-41b1-bcc7-1f799ec177fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330401147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.330401147
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.1030918390
Short name T378
Test name
Test status
Simulation time 15910505055 ps
CPU time 122.11 seconds
Started Jul 26 04:48:00 PM PDT 24
Finished Jul 26 04:50:02 PM PDT 24
Peak memory 183416 kb
Host smart-85addd8f-c597-4361-bba3-e4d6b27bf535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030918390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.1030918390
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.1633991296
Short name T244
Test name
Test status
Simulation time 82193427626 ps
CPU time 118.91 seconds
Started Jul 26 04:48:06 PM PDT 24
Finished Jul 26 04:50:05 PM PDT 24
Peak memory 183392 kb
Host smart-db83bbab-7653-4995-868e-a640dbb316a4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633991296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.1633991296
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.3459555169
Short name T364
Test name
Test status
Simulation time 27264664397 ps
CPU time 23.35 seconds
Started Jul 26 04:47:54 PM PDT 24
Finished Jul 26 04:48:17 PM PDT 24
Peak memory 183404 kb
Host smart-89c1ff6d-5a02-4107-b2e0-60508506a879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459555169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.3459555169
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.2959696428
Short name T335
Test name
Test status
Simulation time 46157884978 ps
CPU time 512.73 seconds
Started Jul 26 04:48:11 PM PDT 24
Finished Jul 26 04:56:44 PM PDT 24
Peak memory 183332 kb
Host smart-8c88ea83-d710-4b88-bf75-06f29972b4e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959696428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.2959696428
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.1379915107
Short name T368
Test name
Test status
Simulation time 734703823 ps
CPU time 1.83 seconds
Started Jul 26 04:48:15 PM PDT 24
Finished Jul 26 04:48:17 PM PDT 24
Peak memory 183336 kb
Host smart-c0101702-1e58-482f-8d42-8fd4eac95885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379915107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.1379915107
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.3742881349
Short name T409
Test name
Test status
Simulation time 1759149116793 ps
CPU time 296.13 seconds
Started Jul 26 04:48:26 PM PDT 24
Finished Jul 26 04:53:23 PM PDT 24
Peak memory 191596 kb
Host smart-777bd718-927e-4aba-b13c-31b05798a4e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742881349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.3742881349
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all_with_rand_reset.1659800224
Short name T35
Test name
Test status
Simulation time 31400539888 ps
CPU time 322.94 seconds
Started Jul 26 04:48:09 PM PDT 24
Finished Jul 26 04:53:32 PM PDT 24
Peak memory 206264 kb
Host smart-cc8a1abc-beac-4e82-8f0d-e7e0ea91bd3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659800224 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all_with_rand_reset.1659800224
Directory /workspace/39.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.4029156891
Short name T46
Test name
Test status
Simulation time 119653351553 ps
CPU time 145.49 seconds
Started Jul 26 04:47:37 PM PDT 24
Finished Jul 26 04:50:02 PM PDT 24
Peak memory 183320 kb
Host smart-0091532c-da40-4173-b808-7b2f07e340f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029156891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.4029156891
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.497575947
Short name T126
Test name
Test status
Simulation time 151514421845 ps
CPU time 325.28 seconds
Started Jul 26 04:47:20 PM PDT 24
Finished Jul 26 04:52:45 PM PDT 24
Peak memory 191592 kb
Host smart-50dff931-81db-448c-a8c3-e66cfec87079
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497575947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.497575947
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.1570756778
Short name T79
Test name
Test status
Simulation time 268406278 ps
CPU time 0.73 seconds
Started Jul 26 04:47:44 PM PDT 24
Finished Jul 26 04:47:45 PM PDT 24
Peak memory 183124 kb
Host smart-f85f28d5-0b90-4c3f-b6e6-7f89d1982478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570756778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.1570756778
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.1778757423
Short name T18
Test name
Test status
Simulation time 122016612 ps
CPU time 0.77 seconds
Started Jul 26 04:47:48 PM PDT 24
Finished Jul 26 04:47:49 PM PDT 24
Peak memory 213660 kb
Host smart-ee57ecaf-1f9e-4fd4-b9f3-6c8b4811ff90
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778757423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.1778757423
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.1614973732
Short name T400
Test name
Test status
Simulation time 133624287356 ps
CPU time 53.59 seconds
Started Jul 26 04:48:08 PM PDT 24
Finished Jul 26 04:49:02 PM PDT 24
Peak memory 183400 kb
Host smart-b8ec2c3f-91d8-4efb-b0a2-7a1c7e2e498e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614973732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.1614973732
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.3674571579
Short name T251
Test name
Test status
Simulation time 48817019750 ps
CPU time 101.6 seconds
Started Jul 26 04:48:10 PM PDT 24
Finished Jul 26 04:49:52 PM PDT 24
Peak memory 191608 kb
Host smart-8023a40e-5dfc-44a5-a904-1c8fd937ee92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674571579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.3674571579
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.873430500
Short name T239
Test name
Test status
Simulation time 448245624762 ps
CPU time 299.2 seconds
Started Jul 26 04:48:00 PM PDT 24
Finished Jul 26 04:53:00 PM PDT 24
Peak memory 194784 kb
Host smart-0d58f34b-1251-414e-a2c6-83ce29e5e58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873430500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.873430500
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all_with_rand_reset.3522098605
Short name T52
Test name
Test status
Simulation time 111623789533 ps
CPU time 833.24 seconds
Started Jul 26 04:48:09 PM PDT 24
Finished Jul 26 05:02:02 PM PDT 24
Peak memory 209440 kb
Host smart-7ea374e0-5976-4006-a9ec-dd3ff1051e8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522098605 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all_with_rand_reset.3522098605
Directory /workspace/40.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.2620124086
Short name T277
Test name
Test status
Simulation time 672117153800 ps
CPU time 351.95 seconds
Started Jul 26 04:48:04 PM PDT 24
Finished Jul 26 04:53:56 PM PDT 24
Peak memory 183352 kb
Host smart-07b3075b-a44e-4c06-b25d-f4d10f103b66
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620124086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.2620124086
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.1626532646
Short name T404
Test name
Test status
Simulation time 88791685946 ps
CPU time 58.36 seconds
Started Jul 26 04:47:49 PM PDT 24
Finished Jul 26 04:48:48 PM PDT 24
Peak memory 183364 kb
Host smart-6484ac52-b9cd-4606-8599-bbfda96e7452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626532646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.1626532646
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.3475724781
Short name T339
Test name
Test status
Simulation time 567032677052 ps
CPU time 427.82 seconds
Started Jul 26 04:48:07 PM PDT 24
Finished Jul 26 04:55:15 PM PDT 24
Peak memory 191604 kb
Host smart-f28210b8-9ca9-4c1d-9d2b-e75fbc5a6560
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475724781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.3475724781
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.2343350903
Short name T346
Test name
Test status
Simulation time 45837896313 ps
CPU time 81.85 seconds
Started Jul 26 04:48:09 PM PDT 24
Finished Jul 26 04:49:31 PM PDT 24
Peak memory 183360 kb
Host smart-172560a4-1473-47b0-94f1-7b19feb56a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343350903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.2343350903
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.1755743604
Short name T182
Test name
Test status
Simulation time 671961730083 ps
CPU time 621.29 seconds
Started Jul 26 04:48:07 PM PDT 24
Finished Jul 26 04:58:28 PM PDT 24
Peak memory 183388 kb
Host smart-3b4b7fe5-7833-47c8-8dd5-bc07abb1ab27
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755743604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.1755743604
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.2577110122
Short name T448
Test name
Test status
Simulation time 814079427671 ps
CPU time 244.58 seconds
Started Jul 26 04:48:18 PM PDT 24
Finished Jul 26 04:52:23 PM PDT 24
Peak memory 183328 kb
Host smart-fee52f77-358d-4833-854e-f7e59ed893af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577110122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.2577110122
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.2230725997
Short name T25
Test name
Test status
Simulation time 100566112070 ps
CPU time 223.4 seconds
Started Jul 26 04:48:13 PM PDT 24
Finished Jul 26 04:51:57 PM PDT 24
Peak memory 191548 kb
Host smart-edcf7a7d-c1af-47ec-87f3-f98c11d8e416
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230725997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.2230725997
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.1883833713
Short name T357
Test name
Test status
Simulation time 55783547285 ps
CPU time 225.89 seconds
Started Jul 26 04:48:14 PM PDT 24
Finished Jul 26 04:52:00 PM PDT 24
Peak memory 183420 kb
Host smart-6a7d5d65-0757-4d6f-9a1d-c679a21cdcb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883833713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.1883833713
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.753773297
Short name T56
Test name
Test status
Simulation time 1775166133563 ps
CPU time 899.64 seconds
Started Jul 26 04:48:16 PM PDT 24
Finished Jul 26 05:03:16 PM PDT 24
Peak memory 191516 kb
Host smart-3e4b9487-9959-4bde-997f-206f3044931e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753773297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all.
753773297
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all_with_rand_reset.4089176338
Short name T14
Test name
Test status
Simulation time 105499548192 ps
CPU time 367.72 seconds
Started Jul 26 04:48:25 PM PDT 24
Finished Jul 26 04:54:33 PM PDT 24
Peak memory 206296 kb
Host smart-dd16dd6a-d4e7-4b99-852b-720a1a5abf28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089176338 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all_with_rand_reset.4089176338
Directory /workspace/42.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.3218125210
Short name T341
Test name
Test status
Simulation time 42459916496 ps
CPU time 67.62 seconds
Started Jul 26 04:48:07 PM PDT 24
Finished Jul 26 04:49:15 PM PDT 24
Peak memory 183376 kb
Host smart-84ef9ec9-5a29-4f25-8c29-6a797c717c83
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218125210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.3218125210
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.3450138837
Short name T453
Test name
Test status
Simulation time 26797287611 ps
CPU time 36.95 seconds
Started Jul 26 04:48:04 PM PDT 24
Finished Jul 26 04:48:41 PM PDT 24
Peak memory 183372 kb
Host smart-101c8229-d446-455e-b373-8c217f8a1c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450138837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.3450138837
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.786471092
Short name T420
Test name
Test status
Simulation time 111467742428 ps
CPU time 101.18 seconds
Started Jul 26 04:48:38 PM PDT 24
Finished Jul 26 04:50:19 PM PDT 24
Peak memory 183376 kb
Host smart-d2a5f756-fe78-418c-80d6-d3fa34c2ac76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786471092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.786471092
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.291494664
Short name T351
Test name
Test status
Simulation time 125986703367 ps
CPU time 206.61 seconds
Started Jul 26 04:48:27 PM PDT 24
Finished Jul 26 04:51:53 PM PDT 24
Peak memory 191544 kb
Host smart-00ae5b7c-62da-4697-a4a7-08c2863aaa0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291494664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.291494664
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.1328161799
Short name T395
Test name
Test status
Simulation time 4873758988179 ps
CPU time 578.62 seconds
Started Jul 26 04:48:08 PM PDT 24
Finished Jul 26 04:57:47 PM PDT 24
Peak memory 191608 kb
Host smart-dbd7d159-1b3e-40aa-b7ed-e0c2ac7c9b1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328161799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.1328161799
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.3095140784
Short name T108
Test name
Test status
Simulation time 101139987092 ps
CPU time 212.36 seconds
Started Jul 26 04:48:14 PM PDT 24
Finished Jul 26 04:51:47 PM PDT 24
Peak memory 197388 kb
Host smart-5c81e0b1-3490-4c0e-8b5d-ec26e8b0e38d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095140784 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.3095140784
Directory /workspace/43.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.3293304256
Short name T144
Test name
Test status
Simulation time 219909838464 ps
CPU time 389.03 seconds
Started Jul 26 04:48:11 PM PDT 24
Finished Jul 26 04:54:40 PM PDT 24
Peak memory 183376 kb
Host smart-2e00450f-9597-4346-ac22-5c360b270f3e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293304256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.3293304256
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.2955598196
Short name T398
Test name
Test status
Simulation time 36521914604 ps
CPU time 51.58 seconds
Started Jul 26 04:48:28 PM PDT 24
Finished Jul 26 04:49:20 PM PDT 24
Peak memory 183320 kb
Host smart-ef51a4b5-37ac-48ce-8e07-f8c7856eaa99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955598196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.2955598196
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.1988161878
Short name T265
Test name
Test status
Simulation time 563694209459 ps
CPU time 868.59 seconds
Started Jul 26 04:48:11 PM PDT 24
Finished Jul 26 05:02:40 PM PDT 24
Peak memory 192868 kb
Host smart-22a87a6d-c934-4faa-9d9c-92f11d2a0fc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988161878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.1988161878
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.3062974697
Short name T359
Test name
Test status
Simulation time 13506143406 ps
CPU time 19.05 seconds
Started Jul 26 04:48:16 PM PDT 24
Finished Jul 26 04:48:35 PM PDT 24
Peak memory 183380 kb
Host smart-5b82c514-87d3-4dc8-b6f8-ecc072f29ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062974697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.3062974697
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.1812236118
Short name T422
Test name
Test status
Simulation time 19056231365 ps
CPU time 15.01 seconds
Started Jul 26 04:48:16 PM PDT 24
Finished Jul 26 04:48:31 PM PDT 24
Peak memory 183368 kb
Host smart-7ea33747-a1c1-4598-93f6-56e4e967eef9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812236118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.1812236118
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.1541919033
Short name T371
Test name
Test status
Simulation time 204133918483 ps
CPU time 123.61 seconds
Started Jul 26 04:48:15 PM PDT 24
Finished Jul 26 04:50:19 PM PDT 24
Peak memory 183788 kb
Host smart-a63eb2ed-8111-4fb4-9130-b0bd0c827bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541919033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.1541919033
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.3741385910
Short name T163
Test name
Test status
Simulation time 65518801133 ps
CPU time 94.52 seconds
Started Jul 26 04:48:33 PM PDT 24
Finished Jul 26 04:50:08 PM PDT 24
Peak memory 194884 kb
Host smart-1f2520cb-bd3f-45a5-8fd7-228e11c3fa85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741385910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.3741385910
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.3014932815
Short name T408
Test name
Test status
Simulation time 117428549 ps
CPU time 0.74 seconds
Started Jul 26 04:48:14 PM PDT 24
Finished Jul 26 04:48:15 PM PDT 24
Peak memory 183172 kb
Host smart-82c4caaa-4e69-46b6-84be-449dcfc4bf23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014932815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.3014932815
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.3708128145
Short name T435
Test name
Test status
Simulation time 177623045069 ps
CPU time 249.14 seconds
Started Jul 26 04:48:08 PM PDT 24
Finished Jul 26 04:52:18 PM PDT 24
Peak memory 191560 kb
Host smart-2952d3cd-e0ce-46cc-a7cf-37d610d7afff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708128145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.3708128145
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.2994143721
Short name T114
Test name
Test status
Simulation time 185227693422 ps
CPU time 299.55 seconds
Started Jul 26 04:48:16 PM PDT 24
Finished Jul 26 04:53:15 PM PDT 24
Peak memory 183340 kb
Host smart-cb287c4b-a0e3-49da-8770-190179ab2aa2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994143721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.2994143721
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.3981354827
Short name T374
Test name
Test status
Simulation time 147974593177 ps
CPU time 113.87 seconds
Started Jul 26 04:48:06 PM PDT 24
Finished Jul 26 04:50:00 PM PDT 24
Peak memory 183312 kb
Host smart-caa1c5f6-35b6-4a7c-85d7-574aeb4a94e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981354827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.3981354827
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.847288248
Short name T320
Test name
Test status
Simulation time 50506180000 ps
CPU time 77.2 seconds
Started Jul 26 04:48:12 PM PDT 24
Finished Jul 26 04:49:29 PM PDT 24
Peak memory 191604 kb
Host smart-5397f034-8c03-4779-b7d5-fee71ee2a48e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847288248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.847288248
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.1258149194
Short name T120
Test name
Test status
Simulation time 134748744381 ps
CPU time 94.15 seconds
Started Jul 26 04:48:07 PM PDT 24
Finished Jul 26 04:49:41 PM PDT 24
Peak memory 183384 kb
Host smart-954d336d-1877-4271-900c-ba80ad4f7b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258149194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.1258149194
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.124317173
Short name T260
Test name
Test status
Simulation time 230218327889 ps
CPU time 392.65 seconds
Started Jul 26 04:48:02 PM PDT 24
Finished Jul 26 04:54:35 PM PDT 24
Peak memory 183352 kb
Host smart-91f180d7-74a5-4222-a6dc-6c1f0a5a8930
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124317173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.rv_timer_cfg_update_on_fly.124317173
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.3374125832
Short name T373
Test name
Test status
Simulation time 747176632835 ps
CPU time 292.22 seconds
Started Jul 26 04:48:15 PM PDT 24
Finished Jul 26 04:53:08 PM PDT 24
Peak memory 183408 kb
Host smart-d36f2f9e-424b-4b86-8269-2b20eec7aeaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374125832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.3374125832
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.534918636
Short name T343
Test name
Test status
Simulation time 38758598349 ps
CPU time 61.09 seconds
Started Jul 26 04:48:18 PM PDT 24
Finished Jul 26 04:49:20 PM PDT 24
Peak memory 191576 kb
Host smart-92ffdc1d-f095-4015-82dc-c0f3e2ba3635
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534918636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.534918636
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.2967103354
Short name T133
Test name
Test status
Simulation time 281003363260 ps
CPU time 206.53 seconds
Started Jul 26 04:48:07 PM PDT 24
Finished Jul 26 04:51:34 PM PDT 24
Peak memory 191528 kb
Host smart-5321183f-22dd-40c1-acbf-9f7e72c67d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967103354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.2967103354
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.1159113164
Short name T389
Test name
Test status
Simulation time 17075035 ps
CPU time 0.53 seconds
Started Jul 26 04:48:34 PM PDT 24
Finished Jul 26 04:48:34 PM PDT 24
Peak memory 183156 kb
Host smart-4e301ba4-92cc-4577-ba30-3342f18dcbb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159113164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.1159113164
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.1376102904
Short name T340
Test name
Test status
Simulation time 8348815738 ps
CPU time 4.82 seconds
Started Jul 26 04:48:11 PM PDT 24
Finished Jul 26 04:48:16 PM PDT 24
Peak memory 183336 kb
Host smart-824ec01e-28cb-4af1-849e-c37da52edfa0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376102904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.1376102904
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.3889081530
Short name T405
Test name
Test status
Simulation time 71052850096 ps
CPU time 50.23 seconds
Started Jul 26 04:48:20 PM PDT 24
Finished Jul 26 04:49:11 PM PDT 24
Peak memory 183392 kb
Host smart-6bc7b746-66c6-4760-a564-9dfeda10ddfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889081530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.3889081530
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.3866188194
Short name T75
Test name
Test status
Simulation time 164076421074 ps
CPU time 1480.47 seconds
Started Jul 26 04:48:07 PM PDT 24
Finished Jul 26 05:12:48 PM PDT 24
Peak memory 191620 kb
Host smart-4aab86aa-5197-47d7-b8ab-f16021499108
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866188194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.3866188194
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.2507847954
Short name T175
Test name
Test status
Simulation time 51648130349 ps
CPU time 48.99 seconds
Started Jul 26 04:48:19 PM PDT 24
Finished Jul 26 04:49:08 PM PDT 24
Peak memory 191528 kb
Host smart-544960fe-585b-465a-835f-6f9e35e9a8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507847954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.2507847954
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.1031746552
Short name T413
Test name
Test status
Simulation time 819451177625 ps
CPU time 384.81 seconds
Started Jul 26 04:48:28 PM PDT 24
Finished Jul 26 04:54:53 PM PDT 24
Peak memory 183384 kb
Host smart-107a8d2f-1c45-4737-a46f-ba0e25a555ed
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031746552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.1031746552
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.3061959678
Short name T21
Test name
Test status
Simulation time 253741938171 ps
CPU time 70.59 seconds
Started Jul 26 04:48:00 PM PDT 24
Finished Jul 26 04:49:11 PM PDT 24
Peak memory 183320 kb
Host smart-a6501bc4-f5de-4ec4-8a0f-a8b92f5b2f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061959678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.3061959678
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.1010703206
Short name T242
Test name
Test status
Simulation time 163902210354 ps
CPU time 504.89 seconds
Started Jul 26 04:48:05 PM PDT 24
Finished Jul 26 04:56:30 PM PDT 24
Peak memory 191596 kb
Host smart-c06db8a7-742b-4e92-a45d-18e5d258a6d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010703206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.1010703206
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.2219718794
Short name T118
Test name
Test status
Simulation time 384165044818 ps
CPU time 3445.65 seconds
Started Jul 26 04:48:22 PM PDT 24
Finished Jul 26 05:45:48 PM PDT 24
Peak memory 196288 kb
Host smart-015a97a3-7ac8-4464-a67f-9351affe2fbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219718794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.2219718794
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.170540943
Short name T171
Test name
Test status
Simulation time 202087121832 ps
CPU time 90.67 seconds
Started Jul 26 04:47:44 PM PDT 24
Finished Jul 26 04:49:15 PM PDT 24
Peak memory 183508 kb
Host smart-5e443ca2-d0c8-42d7-95c3-2c9a3ce2f026
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170540943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.rv_timer_cfg_update_on_fly.170540943
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.2979699069
Short name T370
Test name
Test status
Simulation time 140578038342 ps
CPU time 55.62 seconds
Started Jul 26 04:47:27 PM PDT 24
Finished Jul 26 04:48:23 PM PDT 24
Peak memory 183396 kb
Host smart-a8368569-5248-4cf6-be6f-b7a7c1ca7150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979699069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.2979699069
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.354251200
Short name T293
Test name
Test status
Simulation time 44170308553 ps
CPU time 153.37 seconds
Started Jul 26 04:47:35 PM PDT 24
Finished Jul 26 04:50:08 PM PDT 24
Peak memory 183396 kb
Host smart-711bf477-cdeb-4579-9b2c-934018c0a328
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354251200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.354251200
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.4289596195
Short name T255
Test name
Test status
Simulation time 212796002986 ps
CPU time 99.74 seconds
Started Jul 26 04:47:55 PM PDT 24
Finished Jul 26 04:49:35 PM PDT 24
Peak memory 191572 kb
Host smart-11be9d81-b1f1-4860-820f-42a267b1298d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289596195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.4289596195
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/51.rv_timer_random.1552623688
Short name T76
Test name
Test status
Simulation time 564174050561 ps
CPU time 221.55 seconds
Started Jul 26 04:48:04 PM PDT 24
Finished Jul 26 04:51:46 PM PDT 24
Peak memory 191704 kb
Host smart-a308e1fe-1b83-4f11-a458-ed260e219354
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552623688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.1552623688
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.4125290291
Short name T295
Test name
Test status
Simulation time 521132891218 ps
CPU time 290.4 seconds
Started Jul 26 04:48:28 PM PDT 24
Finished Jul 26 04:53:19 PM PDT 24
Peak memory 191584 kb
Host smart-c5522918-ae1f-435c-9685-941f6162c7c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125290291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.4125290291
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.2225002080
Short name T197
Test name
Test status
Simulation time 79408627353 ps
CPU time 416.28 seconds
Started Jul 26 04:48:12 PM PDT 24
Finished Jul 26 04:55:08 PM PDT 24
Peak memory 191528 kb
Host smart-e8693161-1697-4de1-aa41-8dd4d522276b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225002080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.2225002080
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.1850123209
Short name T360
Test name
Test status
Simulation time 11634222031 ps
CPU time 18.54 seconds
Started Jul 26 04:48:11 PM PDT 24
Finished Jul 26 04:48:29 PM PDT 24
Peak memory 183336 kb
Host smart-edce2fd8-699d-4ee2-acf3-7edd38ca7a97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850123209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.1850123209
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.1782092284
Short name T352
Test name
Test status
Simulation time 154294623774 ps
CPU time 771.53 seconds
Started Jul 26 04:47:55 PM PDT 24
Finished Jul 26 05:00:47 PM PDT 24
Peak memory 191600 kb
Host smart-d82c891a-653b-4d73-b0eb-a21d1df28a09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782092284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.1782092284
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.3366131201
Short name T139
Test name
Test status
Simulation time 148914393657 ps
CPU time 231.2 seconds
Started Jul 26 04:48:16 PM PDT 24
Finished Jul 26 04:52:07 PM PDT 24
Peak memory 191592 kb
Host smart-7073347c-d9be-417c-98f0-485b0405e429
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366131201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.3366131201
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.1941504842
Short name T269
Test name
Test status
Simulation time 414499936934 ps
CPU time 254.34 seconds
Started Jul 26 04:48:19 PM PDT 24
Finished Jul 26 04:52:34 PM PDT 24
Peak memory 191592 kb
Host smart-1dad8064-3dcc-40dc-80a6-ee3b05cbbadd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941504842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.1941504842
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.1633128539
Short name T82
Test name
Test status
Simulation time 223778617619 ps
CPU time 151.28 seconds
Started Jul 26 04:48:21 PM PDT 24
Finished Jul 26 04:50:52 PM PDT 24
Peak memory 191720 kb
Host smart-c4418a7e-5ca8-40f2-9338-5677c030a3aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633128539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.1633128539
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.1525022720
Short name T326
Test name
Test status
Simulation time 798967934241 ps
CPU time 358.17 seconds
Started Jul 26 04:47:45 PM PDT 24
Finished Jul 26 04:53:44 PM PDT 24
Peak memory 183352 kb
Host smart-be358184-a8bf-4ba4-b964-447c6853b3fc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525022720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.1525022720
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.3217938482
Short name T411
Test name
Test status
Simulation time 7075155510 ps
CPU time 5.75 seconds
Started Jul 26 04:47:31 PM PDT 24
Finished Jul 26 04:47:37 PM PDT 24
Peak memory 183364 kb
Host smart-2067a728-ffe1-4063-91f2-95c5e1783931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217938482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.3217938482
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.1112653804
Short name T116
Test name
Test status
Simulation time 178127872741 ps
CPU time 648.94 seconds
Started Jul 26 04:47:54 PM PDT 24
Finished Jul 26 04:58:43 PM PDT 24
Peak memory 192924 kb
Host smart-5e5063dd-697b-4805-8b14-b94572b83e63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112653804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.1112653804
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.1667997998
Short name T289
Test name
Test status
Simulation time 52470670281 ps
CPU time 91.92 seconds
Started Jul 26 04:48:05 PM PDT 24
Finished Jul 26 04:49:38 PM PDT 24
Peak memory 183376 kb
Host smart-2f941a34-fc31-4d2f-b612-8176382363d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667997998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.1667997998
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.3140099550
Short name T217
Test name
Test status
Simulation time 203401326585 ps
CPU time 282.77 seconds
Started Jul 26 04:48:24 PM PDT 24
Finished Jul 26 04:53:07 PM PDT 24
Peak memory 191520 kb
Host smart-d84c2ba7-f1fa-46a4-9282-1620533f5801
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140099550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.3140099550
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.2113969188
Short name T266
Test name
Test status
Simulation time 31347995513 ps
CPU time 66.37 seconds
Started Jul 26 04:48:02 PM PDT 24
Finished Jul 26 04:49:09 PM PDT 24
Peak memory 183368 kb
Host smart-d2ef5741-01c1-4902-8c41-3c76917a903d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113969188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.2113969188
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.1334013819
Short name T316
Test name
Test status
Simulation time 193627138537 ps
CPU time 84.8 seconds
Started Jul 26 04:48:12 PM PDT 24
Finished Jul 26 04:49:37 PM PDT 24
Peak memory 183368 kb
Host smart-b73d398b-ef17-44f6-a621-a1803d8d7a5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334013819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.1334013819
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.2568511456
Short name T302
Test name
Test status
Simulation time 85165749834 ps
CPU time 70.82 seconds
Started Jul 26 04:48:13 PM PDT 24
Finished Jul 26 04:49:24 PM PDT 24
Peak memory 183392 kb
Host smart-09527b3c-b92e-4053-866a-7ba1256a0b21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568511456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.2568511456
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.1802982770
Short name T246
Test name
Test status
Simulation time 1242565568425 ps
CPU time 437.86 seconds
Started Jul 26 04:48:03 PM PDT 24
Finished Jul 26 04:55:22 PM PDT 24
Peak memory 191512 kb
Host smart-0844560f-631a-4aae-b94e-623490758e89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802982770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.1802982770
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.710942012
Short name T184
Test name
Test status
Simulation time 44229734687 ps
CPU time 70.17 seconds
Started Jul 26 04:48:22 PM PDT 24
Finished Jul 26 04:49:33 PM PDT 24
Peak memory 191520 kb
Host smart-b513f14f-2878-49ae-81d6-43426b65bd22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710942012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.710942012
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.1369548800
Short name T298
Test name
Test status
Simulation time 405617806902 ps
CPU time 1197.54 seconds
Started Jul 26 04:48:15 PM PDT 24
Finished Jul 26 05:08:13 PM PDT 24
Peak memory 191580 kb
Host smart-1e2ce34a-b258-439f-a855-c63fe9fdb6b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369548800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.1369548800
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.2857272387
Short name T233
Test name
Test status
Simulation time 481531764128 ps
CPU time 178.6 seconds
Started Jul 26 04:48:17 PM PDT 24
Finished Jul 26 04:51:16 PM PDT 24
Peak memory 191584 kb
Host smart-daf08e43-af2c-4ec1-bcc1-9230c07490c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857272387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.2857272387
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.4218215196
Short name T325
Test name
Test status
Simulation time 353235964855 ps
CPU time 341.49 seconds
Started Jul 26 04:48:25 PM PDT 24
Finished Jul 26 04:54:07 PM PDT 24
Peak memory 191588 kb
Host smart-abd0a4a2-fee7-402a-a04b-7de81ad0da2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218215196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.4218215196
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.1683275905
Short name T81
Test name
Test status
Simulation time 10222833767 ps
CPU time 15.46 seconds
Started Jul 26 04:47:48 PM PDT 24
Finished Jul 26 04:48:04 PM PDT 24
Peak memory 183384 kb
Host smart-0cae3d39-00ad-4533-827c-6a3c5eb9e58d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683275905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.1683275905
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.3637761086
Short name T63
Test name
Test status
Simulation time 218832027566 ps
CPU time 155.68 seconds
Started Jul 26 04:47:48 PM PDT 24
Finished Jul 26 04:50:24 PM PDT 24
Peak memory 183376 kb
Host smart-15d1f797-c566-4813-9c21-a8379b87e2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637761086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.3637761086
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.3944135980
Short name T290
Test name
Test status
Simulation time 555015408790 ps
CPU time 555.16 seconds
Started Jul 26 04:47:49 PM PDT 24
Finished Jul 26 04:57:05 PM PDT 24
Peak memory 191552 kb
Host smart-2ee9961f-3b94-457e-a156-28c4e663f0bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944135980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.3944135980
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.2492919614
Short name T407
Test name
Test status
Simulation time 602550933 ps
CPU time 0.73 seconds
Started Jul 26 04:47:46 PM PDT 24
Finished Jul 26 04:47:47 PM PDT 24
Peak memory 183136 kb
Host smart-887a1c0b-5646-4740-948b-d85ccc16aafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492919614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.2492919614
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.510138630
Short name T38
Test name
Test status
Simulation time 54908778174 ps
CPU time 176.77 seconds
Started Jul 26 04:48:00 PM PDT 24
Finished Jul 26 04:50:57 PM PDT 24
Peak memory 198100 kb
Host smart-b259dd7f-8ab6-4011-9b48-3fe9141e94fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510138630 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all_with_rand_reset.510138630
Directory /workspace/7.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.4002730652
Short name T270
Test name
Test status
Simulation time 44314197230 ps
CPU time 73.05 seconds
Started Jul 26 04:48:05 PM PDT 24
Finished Jul 26 04:49:19 PM PDT 24
Peak memory 191620 kb
Host smart-e73a2c4a-1191-4437-adab-f0c3fecbaf05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002730652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.4002730652
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.1038932159
Short name T317
Test name
Test status
Simulation time 556908119816 ps
CPU time 675.63 seconds
Started Jul 26 04:48:13 PM PDT 24
Finished Jul 26 04:59:28 PM PDT 24
Peak memory 194852 kb
Host smart-b606ab64-4099-45d3-9955-d81a34a80c20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038932159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.1038932159
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.1080190852
Short name T403
Test name
Test status
Simulation time 22023277931 ps
CPU time 31.19 seconds
Started Jul 26 04:48:15 PM PDT 24
Finished Jul 26 04:48:46 PM PDT 24
Peak memory 183372 kb
Host smart-c42adc34-afa3-4e67-9531-7a1cfa772ae8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080190852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.1080190852
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.2653440288
Short name T61
Test name
Test status
Simulation time 78343744685 ps
CPU time 235.62 seconds
Started Jul 26 04:48:17 PM PDT 24
Finished Jul 26 04:52:13 PM PDT 24
Peak memory 191580 kb
Host smart-74f96260-cc0b-486b-9529-aef935d8f63a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653440288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.2653440288
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.1826287706
Short name T228
Test name
Test status
Simulation time 215328886097 ps
CPU time 2266.84 seconds
Started Jul 26 04:48:18 PM PDT 24
Finished Jul 26 05:26:05 PM PDT 24
Peak memory 191504 kb
Host smart-aa9bbecf-6984-4d42-bbfe-bb5e736f4f8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826287706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.1826287706
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.1613858071
Short name T218
Test name
Test status
Simulation time 977556395818 ps
CPU time 197.76 seconds
Started Jul 26 04:48:16 PM PDT 24
Finished Jul 26 04:51:34 PM PDT 24
Peak memory 191552 kb
Host smart-5939306f-094b-4622-94e4-120041aa8404
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613858071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.1613858071
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.606551764
Short name T127
Test name
Test status
Simulation time 671851010782 ps
CPU time 548.81 seconds
Started Jul 26 04:48:14 PM PDT 24
Finished Jul 26 04:57:28 PM PDT 24
Peak memory 191608 kb
Host smart-50f4b555-fde3-45f1-837f-37f935bf2e17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606551764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.606551764
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.630201340
Short name T74
Test name
Test status
Simulation time 41784466195 ps
CPU time 335.88 seconds
Started Jul 26 04:48:17 PM PDT 24
Finished Jul 26 04:53:53 PM PDT 24
Peak memory 183408 kb
Host smart-eff755b9-6510-4f3a-af96-6b284e2047e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630201340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.630201340
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.212263156
Short name T363
Test name
Test status
Simulation time 85797927859 ps
CPU time 93.98 seconds
Started Jul 26 04:48:10 PM PDT 24
Finished Jul 26 04:49:44 PM PDT 24
Peak memory 192676 kb
Host smart-4afe26d1-52e8-4ecb-9b83-ddc8659c644c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212263156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.212263156
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.467564657
Short name T419
Test name
Test status
Simulation time 1277188110661 ps
CPU time 707.18 seconds
Started Jul 26 04:48:03 PM PDT 24
Finished Jul 26 04:59:51 PM PDT 24
Peak memory 183344 kb
Host smart-71ed737e-c146-497d-9139-04008e907587
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467564657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.rv_timer_cfg_update_on_fly.467564657
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.3686673499
Short name T394
Test name
Test status
Simulation time 79734809602 ps
CPU time 120.81 seconds
Started Jul 26 04:47:44 PM PDT 24
Finished Jul 26 04:49:45 PM PDT 24
Peak memory 183408 kb
Host smart-6e3911ef-d144-4a37-8412-bd9730bd135a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686673499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.3686673499
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.1651863485
Short name T292
Test name
Test status
Simulation time 77248546305 ps
CPU time 79.9 seconds
Started Jul 26 04:47:56 PM PDT 24
Finished Jul 26 04:49:16 PM PDT 24
Peak memory 191560 kb
Host smart-8ff67973-f112-4987-9b6a-fa1485c2b505
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651863485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.1651863485
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.362993715
Short name T145
Test name
Test status
Simulation time 85041517616 ps
CPU time 131.94 seconds
Started Jul 26 04:47:47 PM PDT 24
Finished Jul 26 04:49:59 PM PDT 24
Peak memory 191708 kb
Host smart-c9c9049e-4816-4e92-a169-322be4c21ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362993715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.362993715
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/81.rv_timer_random.2336084684
Short name T200
Test name
Test status
Simulation time 173976915777 ps
CPU time 135.69 seconds
Started Jul 26 04:48:16 PM PDT 24
Finished Jul 26 04:50:31 PM PDT 24
Peak memory 191552 kb
Host smart-35baacfb-24e4-4031-9755-ea40eb66ad82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336084684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.2336084684
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.1493924242
Short name T262
Test name
Test status
Simulation time 100244688538 ps
CPU time 153.72 seconds
Started Jul 26 04:48:09 PM PDT 24
Finished Jul 26 04:50:43 PM PDT 24
Peak memory 191564 kb
Host smart-a5a1c26b-e5db-4eb5-9a7a-09a692c7d6d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493924242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.1493924242
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.3821220141
Short name T331
Test name
Test status
Simulation time 502801899953 ps
CPU time 168.94 seconds
Started Jul 26 04:48:21 PM PDT 24
Finished Jul 26 04:51:10 PM PDT 24
Peak memory 191552 kb
Host smart-d8313712-66d7-4545-b786-42d3d6118afa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821220141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.3821220141
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.1064749865
Short name T433
Test name
Test status
Simulation time 8346643497 ps
CPU time 305.86 seconds
Started Jul 26 04:48:01 PM PDT 24
Finished Jul 26 04:53:07 PM PDT 24
Peak memory 183368 kb
Host smart-ddb72c38-2536-4ebc-94df-c36a0cdc9321
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064749865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.1064749865
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.2815257598
Short name T308
Test name
Test status
Simulation time 113259512831 ps
CPU time 570.4 seconds
Started Jul 26 04:48:09 PM PDT 24
Finished Jul 26 04:57:39 PM PDT 24
Peak memory 191564 kb
Host smart-eb17989e-7e2f-485f-b220-c97e918a660b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815257598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.2815257598
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.1435005909
Short name T142
Test name
Test status
Simulation time 217777464088 ps
CPU time 98.54 seconds
Started Jul 26 04:48:12 PM PDT 24
Finished Jul 26 04:49:51 PM PDT 24
Peak memory 191564 kb
Host smart-207e9c85-94f5-4074-8233-5e6155b9837e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435005909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.1435005909
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.35212472
Short name T156
Test name
Test status
Simulation time 489888415963 ps
CPU time 241.69 seconds
Started Jul 26 04:48:22 PM PDT 24
Finished Jul 26 04:52:24 PM PDT 24
Peak memory 191560 kb
Host smart-611850b8-dc94-4cff-a0b3-cc203ac65e63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35212472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.35212472
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.2771722383
Short name T129
Test name
Test status
Simulation time 81391733846 ps
CPU time 66.89 seconds
Started Jul 26 04:47:54 PM PDT 24
Finished Jul 26 04:49:01 PM PDT 24
Peak memory 183348 kb
Host smart-4defd844-45a6-4db4-a5c7-8cb627c902dc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771722383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.2771722383
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.1560061812
Short name T417
Test name
Test status
Simulation time 225657194037 ps
CPU time 123.13 seconds
Started Jul 26 04:47:32 PM PDT 24
Finished Jul 26 04:49:35 PM PDT 24
Peak memory 183416 kb
Host smart-66a2e7de-a182-43ae-b396-486678b7d8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560061812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.1560061812
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.3266000347
Short name T328
Test name
Test status
Simulation time 165018105278 ps
CPU time 183.38 seconds
Started Jul 26 04:47:43 PM PDT 24
Finished Jul 26 04:50:46 PM PDT 24
Peak memory 191712 kb
Host smart-5d946897-ac76-409a-b5bb-36f72b6f2671
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266000347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.3266000347
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.3470610163
Short name T386
Test name
Test status
Simulation time 212571413 ps
CPU time 0.6 seconds
Started Jul 26 04:47:31 PM PDT 24
Finished Jul 26 04:47:32 PM PDT 24
Peak memory 183148 kb
Host smart-09252d2a-6b11-4017-8504-84e11066ef40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470610163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.3470610163
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.1073339179
Short name T123
Test name
Test status
Simulation time 115490293345 ps
CPU time 186.97 seconds
Started Jul 26 04:48:09 PM PDT 24
Finished Jul 26 04:51:16 PM PDT 24
Peak memory 191520 kb
Host smart-aec73fc6-0609-4a23-aa08-26da9c5fef9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073339179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.1073339179
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.3273549180
Short name T353
Test name
Test status
Simulation time 439235719305 ps
CPU time 197.44 seconds
Started Jul 26 04:48:07 PM PDT 24
Finished Jul 26 04:51:25 PM PDT 24
Peak memory 191568 kb
Host smart-230abd6f-3102-4679-b08c-e4c8f7c3626d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273549180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.3273549180
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.979108171
Short name T342
Test name
Test status
Simulation time 71997226884 ps
CPU time 110.15 seconds
Started Jul 26 04:48:29 PM PDT 24
Finished Jul 26 04:50:24 PM PDT 24
Peak memory 191528 kb
Host smart-8d70e62a-14f7-4792-9abe-cd9a96909655
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979108171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.979108171
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.3323079762
Short name T84
Test name
Test status
Simulation time 362963998342 ps
CPU time 1202.8 seconds
Started Jul 26 04:48:12 PM PDT 24
Finished Jul 26 05:08:15 PM PDT 24
Peak memory 191460 kb
Host smart-2f278f3d-518b-4524-b53f-78ac042b8c30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323079762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.3323079762
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.3684219582
Short name T291
Test name
Test status
Simulation time 64061267799 ps
CPU time 408.55 seconds
Started Jul 26 04:48:07 PM PDT 24
Finished Jul 26 04:55:06 PM PDT 24
Peak memory 191572 kb
Host smart-f71d44b3-2d3a-4096-8376-563e4008c303
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684219582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.3684219582
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.2894450992
Short name T286
Test name
Test status
Simulation time 115872367778 ps
CPU time 257.25 seconds
Started Jul 26 04:48:24 PM PDT 24
Finished Jul 26 04:52:47 PM PDT 24
Peak memory 191512 kb
Host smart-b6c8fd60-8008-4d18-aa5c-9ef8969c24c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894450992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.2894450992
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.1557456201
Short name T288
Test name
Test status
Simulation time 170242229764 ps
CPU time 106.11 seconds
Started Jul 26 04:48:18 PM PDT 24
Finished Jul 26 04:50:04 PM PDT 24
Peak memory 191460 kb
Host smart-511eaf07-92be-4c04-be2d-bec77f387965
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557456201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.1557456201
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.4218122980
Short name T122
Test name
Test status
Simulation time 26800241906 ps
CPU time 44.2 seconds
Started Jul 26 04:48:07 PM PDT 24
Finished Jul 26 04:48:51 PM PDT 24
Peak memory 191600 kb
Host smart-088cf46d-1e9e-41fd-b2bc-7e5d5b44cc38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218122980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.4218122980
Directory /workspace/99.rv_timer_random/latest
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