Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.49 99.36 98.73 100.00 100.00 100.00 98.87


Total test records in report: 579
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T510 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.1050146888 Jul 27 05:08:53 PM PDT 24 Jul 27 05:08:54 PM PDT 24 551753323 ps
T511 /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.4100448052 Jul 27 05:08:55 PM PDT 24 Jul 27 05:08:57 PM PDT 24 70837382 ps
T512 /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2202051553 Jul 27 05:09:21 PM PDT 24 Jul 27 05:09:21 PM PDT 24 22162455 ps
T513 /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.128464028 Jul 27 05:09:18 PM PDT 24 Jul 27 05:09:21 PM PDT 24 178116516 ps
T514 /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.4184022897 Jul 27 05:09:11 PM PDT 24 Jul 27 05:09:12 PM PDT 24 43022322 ps
T515 /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.2381315710 Jul 27 05:09:22 PM PDT 24 Jul 27 05:09:23 PM PDT 24 31041979 ps
T516 /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.116372794 Jul 27 05:08:55 PM PDT 24 Jul 27 05:08:55 PM PDT 24 30443947 ps
T517 /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.2823909207 Jul 27 05:09:08 PM PDT 24 Jul 27 05:09:10 PM PDT 24 146693010 ps
T518 /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.3111677093 Jul 27 05:09:18 PM PDT 24 Jul 27 05:09:19 PM PDT 24 15470883 ps
T519 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.1223834046 Jul 27 05:08:55 PM PDT 24 Jul 27 05:08:56 PM PDT 24 39115899 ps
T520 /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.124621595 Jul 27 05:09:10 PM PDT 24 Jul 27 05:09:10 PM PDT 24 28752665 ps
T73 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3171809054 Jul 27 05:08:55 PM PDT 24 Jul 27 05:08:56 PM PDT 24 20178427 ps
T521 /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3432781523 Jul 27 05:09:08 PM PDT 24 Jul 27 05:09:09 PM PDT 24 62066332 ps
T522 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.2154120450 Jul 27 05:09:06 PM PDT 24 Jul 27 05:09:07 PM PDT 24 20267612 ps
T523 /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1223438014 Jul 27 05:09:06 PM PDT 24 Jul 27 05:09:07 PM PDT 24 30699442 ps
T79 /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.212014873 Jul 27 05:08:55 PM PDT 24 Jul 27 05:08:56 PM PDT 24 23829419 ps
T90 /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.2765715922 Jul 27 05:09:08 PM PDT 24 Jul 27 05:09:09 PM PDT 24 118666830 ps
T524 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1616809081 Jul 27 05:08:54 PM PDT 24 Jul 27 05:08:55 PM PDT 24 53401599 ps
T525 /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.720724041 Jul 27 05:09:13 PM PDT 24 Jul 27 05:09:14 PM PDT 24 78273077 ps
T526 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1708172997 Jul 27 05:09:18 PM PDT 24 Jul 27 05:09:19 PM PDT 24 176823895 ps
T527 /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.268060531 Jul 27 05:08:57 PM PDT 24 Jul 27 05:08:58 PM PDT 24 44000821 ps
T528 /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.619143519 Jul 27 05:09:08 PM PDT 24 Jul 27 05:09:08 PM PDT 24 15031128 ps
T529 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.2347272652 Jul 27 05:09:17 PM PDT 24 Jul 27 05:09:18 PM PDT 24 120567169 ps
T530 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.198539593 Jul 27 05:08:56 PM PDT 24 Jul 27 05:08:58 PM PDT 24 37352943 ps
T91 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1170216642 Jul 27 05:09:16 PM PDT 24 Jul 27 05:09:18 PM PDT 24 220718303 ps
T531 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.778965622 Jul 27 05:08:56 PM PDT 24 Jul 27 05:08:57 PM PDT 24 42357933 ps
T74 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1075764670 Jul 27 05:08:58 PM PDT 24 Jul 27 05:09:02 PM PDT 24 570909450 ps
T532 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.2809352900 Jul 27 05:09:17 PM PDT 24 Jul 27 05:09:18 PM PDT 24 37033841 ps
T75 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.720092601 Jul 27 05:08:55 PM PDT 24 Jul 27 05:08:56 PM PDT 24 18718330 ps
T533 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.3812239224 Jul 27 05:09:18 PM PDT 24 Jul 27 05:09:19 PM PDT 24 13305338 ps
T534 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.402817198 Jul 27 05:09:28 PM PDT 24 Jul 27 05:09:29 PM PDT 24 12710583 ps
T535 /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.411493711 Jul 27 05:09:09 PM PDT 24 Jul 27 05:09:10 PM PDT 24 43195198 ps
T76 /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3404599373 Jul 27 05:09:17 PM PDT 24 Jul 27 05:09:18 PM PDT 24 29665245 ps
T536 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.4174753307 Jul 27 05:08:55 PM PDT 24 Jul 27 05:08:57 PM PDT 24 28542556 ps
T537 /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.2324786999 Jul 27 05:09:10 PM PDT 24 Jul 27 05:09:10 PM PDT 24 161853488 ps
T538 /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.811097723 Jul 27 05:09:08 PM PDT 24 Jul 27 05:09:09 PM PDT 24 49900587 ps
T539 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3463876321 Jul 27 05:09:07 PM PDT 24 Jul 27 05:09:09 PM PDT 24 87482727 ps
T540 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2936347163 Jul 27 05:09:19 PM PDT 24 Jul 27 05:09:20 PM PDT 24 63443256 ps
T541 /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.649887248 Jul 27 05:09:08 PM PDT 24 Jul 27 05:09:09 PM PDT 24 79035624 ps
T77 /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3479678487 Jul 27 05:08:59 PM PDT 24 Jul 27 05:08:59 PM PDT 24 136810800 ps
T542 /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.4058565753 Jul 27 05:09:17 PM PDT 24 Jul 27 05:09:19 PM PDT 24 33294404 ps
T543 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.2999869288 Jul 27 05:09:28 PM PDT 24 Jul 27 05:09:29 PM PDT 24 80796558 ps
T544 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.579430118 Jul 27 05:09:08 PM PDT 24 Jul 27 05:09:09 PM PDT 24 299300304 ps
T545 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.2528819115 Jul 27 05:09:09 PM PDT 24 Jul 27 05:09:10 PM PDT 24 124113432 ps
T546 /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.1514885345 Jul 27 05:09:07 PM PDT 24 Jul 27 05:09:08 PM PDT 24 122877190 ps
T547 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.894013438 Jul 27 05:09:08 PM PDT 24 Jul 27 05:09:09 PM PDT 24 115922246 ps
T548 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.2234732005 Jul 27 05:09:22 PM PDT 24 Jul 27 05:09:23 PM PDT 24 17100898 ps
T549 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1746102631 Jul 27 05:09:21 PM PDT 24 Jul 27 05:09:22 PM PDT 24 33805598 ps
T550 /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.586577066 Jul 27 05:09:20 PM PDT 24 Jul 27 05:09:21 PM PDT 24 595290053 ps
T551 /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.978017195 Jul 27 05:09:21 PM PDT 24 Jul 27 05:09:22 PM PDT 24 83005958 ps
T552 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.413237716 Jul 27 05:09:09 PM PDT 24 Jul 27 05:09:10 PM PDT 24 177476731 ps
T553 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.203641359 Jul 27 05:09:00 PM PDT 24 Jul 27 05:09:04 PM PDT 24 181777222 ps
T554 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.2080550658 Jul 27 05:09:21 PM PDT 24 Jul 27 05:09:21 PM PDT 24 14070194 ps
T555 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.4132476786 Jul 27 05:09:20 PM PDT 24 Jul 27 05:09:21 PM PDT 24 307570242 ps
T556 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.4193475204 Jul 27 05:09:19 PM PDT 24 Jul 27 05:09:20 PM PDT 24 19083169 ps
T557 /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.124789197 Jul 27 05:09:17 PM PDT 24 Jul 27 05:09:18 PM PDT 24 14790685 ps
T558 /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.4050868163 Jul 27 05:08:57 PM PDT 24 Jul 27 05:08:58 PM PDT 24 24243111 ps
T559 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1880886384 Jul 27 05:09:20 PM PDT 24 Jul 27 05:09:20 PM PDT 24 15886305 ps
T78 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1297071002 Jul 27 05:09:08 PM PDT 24 Jul 27 05:09:09 PM PDT 24 17296970 ps
T560 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.1641592882 Jul 27 05:09:17 PM PDT 24 Jul 27 05:09:18 PM PDT 24 16745764 ps
T561 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.391614952 Jul 27 05:09:18 PM PDT 24 Jul 27 05:09:19 PM PDT 24 65790635 ps
T562 /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.1735059536 Jul 27 05:08:54 PM PDT 24 Jul 27 05:08:54 PM PDT 24 29161133 ps
T563 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.1560030547 Jul 27 05:09:09 PM PDT 24 Jul 27 05:09:10 PM PDT 24 86692119 ps
T564 /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.2040426062 Jul 27 05:09:26 PM PDT 24 Jul 27 05:09:27 PM PDT 24 100128241 ps
T565 /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1311030446 Jul 27 05:09:10 PM PDT 24 Jul 27 05:09:11 PM PDT 24 248843458 ps
T566 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.2563224762 Jul 27 05:09:07 PM PDT 24 Jul 27 05:09:07 PM PDT 24 22219829 ps
T567 /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.513448244 Jul 27 05:09:15 PM PDT 24 Jul 27 05:09:16 PM PDT 24 30616208 ps
T568 /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2161057354 Jul 27 05:08:56 PM PDT 24 Jul 27 05:08:57 PM PDT 24 531721811 ps
T569 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.4200204501 Jul 27 05:08:53 PM PDT 24 Jul 27 05:08:54 PM PDT 24 66087419 ps
T570 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3090857055 Jul 27 05:09:15 PM PDT 24 Jul 27 05:09:16 PM PDT 24 46533392 ps
T571 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.4216842880 Jul 27 05:08:53 PM PDT 24 Jul 27 05:08:55 PM PDT 24 117286448 ps
T572 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.582089271 Jul 27 05:09:22 PM PDT 24 Jul 27 05:09:24 PM PDT 24 123467192 ps
T573 /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.4003578838 Jul 27 05:08:55 PM PDT 24 Jul 27 05:08:56 PM PDT 24 53177073 ps
T574 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.575307351 Jul 27 05:09:19 PM PDT 24 Jul 27 05:09:20 PM PDT 24 363949995 ps
T575 /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.2961355680 Jul 27 05:09:27 PM PDT 24 Jul 27 05:09:27 PM PDT 24 31729898 ps
T576 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.1567351640 Jul 27 05:09:10 PM PDT 24 Jul 27 05:09:11 PM PDT 24 49456998 ps
T577 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.3379117425 Jul 27 05:09:27 PM PDT 24 Jul 27 05:09:28 PM PDT 24 32419499 ps
T578 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.2086723951 Jul 27 05:09:23 PM PDT 24 Jul 27 05:09:24 PM PDT 24 18451986 ps
T579 /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.1406513953 Jul 27 05:08:55 PM PDT 24 Jul 27 05:08:57 PM PDT 24 302054411 ps

Test location /workspace/coverage/default/137.rv_timer_random.1599981871
Short name T6
Test name
Test status
Simulation time 45568737433 ps
CPU time 67.13 seconds
Started Jul 27 05:11:06 PM PDT 24
Finished Jul 27 05:12:13 PM PDT 24
Peak memory 194428 kb
Host smart-6b4872e5-cb9c-4108-97a8-b21042c38b3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599981871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.1599981871
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all_with_rand_reset.1801947743
Short name T13
Test name
Test status
Simulation time 100529777888 ps
CPU time 204.93 seconds
Started Jul 27 05:09:34 PM PDT 24
Finished Jul 27 05:12:59 PM PDT 24
Peak memory 206460 kb
Host smart-42b63e1b-a8c1-4e57-b52c-6bf798c80853
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801947743 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all_with_rand_reset.1801947743
Directory /workspace/0.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.555936958
Short name T31
Test name
Test status
Simulation time 51209135 ps
CPU time 0.85 seconds
Started Jul 27 05:09:18 PM PDT 24
Finished Jul 27 05:09:19 PM PDT 24
Peak memory 193816 kb
Host smart-aef8b54f-523f-42b4-8eef-76f14b8a61dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555936958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_in
tg_err.555936958
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.3818864889
Short name T52
Test name
Test status
Simulation time 323949049249 ps
CPU time 1397.25 seconds
Started Jul 27 05:09:56 PM PDT 24
Finished Jul 27 05:33:13 PM PDT 24
Peak memory 191636 kb
Host smart-036836ec-4086-4bfc-92d4-125f5462f960
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818864889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.3818864889
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.1971169085
Short name T177
Test name
Test status
Simulation time 2231470921358 ps
CPU time 2991.51 seconds
Started Jul 27 05:09:53 PM PDT 24
Finished Jul 27 05:59:45 PM PDT 24
Peak memory 191696 kb
Host smart-41f53199-2a0f-41de-9bb9-28c2e56e7d5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971169085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.1971169085
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.2572466552
Short name T131
Test name
Test status
Simulation time 7594692983939 ps
CPU time 2999.9 seconds
Started Jul 27 05:09:36 PM PDT 24
Finished Jul 27 05:59:36 PM PDT 24
Peak memory 191732 kb
Host smart-7547e5e5-8c6d-4ea7-8e9c-c126996fa7ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572466552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.2572466552
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.420876043
Short name T148
Test name
Test status
Simulation time 4361445262160 ps
CPU time 2748.36 seconds
Started Jul 27 05:10:22 PM PDT 24
Finished Jul 27 05:56:11 PM PDT 24
Peak memory 191740 kb
Host smart-84e6ff28-e8b3-4520-abcf-b2e28a0e813a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420876043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all.
420876043
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.3133986043
Short name T10
Test name
Test status
Simulation time 1346143886576 ps
CPU time 2310.1 seconds
Started Jul 27 05:10:03 PM PDT 24
Finished Jul 27 05:48:33 PM PDT 24
Peak memory 191740 kb
Host smart-d2435648-bec7-45d0-898c-0e52ac335bd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133986043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.3133986043
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.2977318170
Short name T123
Test name
Test status
Simulation time 691690979047 ps
CPU time 3717.16 seconds
Started Jul 27 05:10:04 PM PDT 24
Finished Jul 27 06:12:02 PM PDT 24
Peak memory 191736 kb
Host smart-d68140df-b2a8-4527-8d58-d5076c12f292
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977318170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.2977318170
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.4212895934
Short name T43
Test name
Test status
Simulation time 56238080 ps
CPU time 0.57 seconds
Started Jul 27 05:08:57 PM PDT 24
Finished Jul 27 05:08:58 PM PDT 24
Peak memory 182972 kb
Host smart-66f60fa8-a96a-423b-aab4-551dc70addfc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212895934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.4212895934
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.3364222784
Short name T194
Test name
Test status
Simulation time 517978958492 ps
CPU time 887.61 seconds
Started Jul 27 05:10:09 PM PDT 24
Finished Jul 27 05:24:57 PM PDT 24
Peak memory 191736 kb
Host smart-dff907cc-c081-4d9e-b1c0-7fc1b1ddfaee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364222784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.3364222784
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/57.rv_timer_random.3092853734
Short name T50
Test name
Test status
Simulation time 733891526692 ps
CPU time 480.39 seconds
Started Jul 27 05:10:19 PM PDT 24
Finished Jul 27 05:18:19 PM PDT 24
Peak memory 191720 kb
Host smart-ee22486b-c0f9-4bf0-8757-77d07484dc19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092853734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.3092853734
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/180.rv_timer_random.3837458259
Short name T96
Test name
Test status
Simulation time 1284494486068 ps
CPU time 523.53 seconds
Started Jul 27 05:11:35 PM PDT 24
Finished Jul 27 05:20:19 PM PDT 24
Peak memory 191740 kb
Host smart-f7850c5f-c889-4351-9dd7-28c92fd145bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837458259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.3837458259
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.2811279403
Short name T20
Test name
Test status
Simulation time 347503002 ps
CPU time 0.92 seconds
Started Jul 27 05:09:28 PM PDT 24
Finished Jul 27 05:09:29 PM PDT 24
Peak memory 214880 kb
Host smart-f9fd2e33-2f31-4ba6-8ea8-bbdd386fa207
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811279403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.2811279403
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.1511985125
Short name T1
Test name
Test status
Simulation time 695979614645 ps
CPU time 972.5 seconds
Started Jul 27 05:09:47 PM PDT 24
Finished Jul 27 05:26:00 PM PDT 24
Peak memory 191740 kb
Host smart-d5804496-77cb-41b9-8679-2253da4f0ced
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511985125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.1511985125
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/113.rv_timer_random.851655833
Short name T197
Test name
Test status
Simulation time 146423618399 ps
CPU time 732.23 seconds
Started Jul 27 05:10:53 PM PDT 24
Finished Jul 27 05:23:05 PM PDT 24
Peak memory 191680 kb
Host smart-a62229a9-d462-48b5-ad5d-d78a69083bfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851655833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.851655833
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.2438398138
Short name T188
Test name
Test status
Simulation time 212260881200 ps
CPU time 476.65 seconds
Started Jul 27 05:11:07 PM PDT 24
Finished Jul 27 05:19:04 PM PDT 24
Peak memory 191764 kb
Host smart-976c5974-4545-48b1-8d87-b2d30afa79ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438398138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.2438398138
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.3461725462
Short name T192
Test name
Test status
Simulation time 1244802696854 ps
CPU time 1495.73 seconds
Started Jul 27 05:09:47 PM PDT 24
Finished Jul 27 05:34:43 PM PDT 24
Peak memory 191652 kb
Host smart-7eede9e4-f020-49af-a13b-67f394058f5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461725462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.3461725462
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.898004779
Short name T146
Test name
Test status
Simulation time 2231268133775 ps
CPU time 3517.85 seconds
Started Jul 27 05:10:04 PM PDT 24
Finished Jul 27 06:08:42 PM PDT 24
Peak memory 191968 kb
Host smart-c3024b33-8ebe-49af-a1f9-bca226929c40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898004779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all.
898004779
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.78759768
Short name T139
Test name
Test status
Simulation time 473943775634 ps
CPU time 740.48 seconds
Started Jul 27 05:09:34 PM PDT 24
Finished Jul 27 05:21:55 PM PDT 24
Peak memory 191756 kb
Host smart-f31b6304-372d-4b8d-a283-9ee9b750e094
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78759768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.78759768
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/153.rv_timer_random.1312522842
Short name T259
Test name
Test status
Simulation time 685094536678 ps
CPU time 485.88 seconds
Started Jul 27 05:11:20 PM PDT 24
Finished Jul 27 05:19:26 PM PDT 24
Peak memory 191664 kb
Host smart-11a0d560-db97-4af6-aabe-dd37b167ab0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312522842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.1312522842
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.3312792189
Short name T243
Test name
Test status
Simulation time 993329388682 ps
CPU time 781.46 seconds
Started Jul 27 05:10:16 PM PDT 24
Finished Jul 27 05:23:18 PM PDT 24
Peak memory 191632 kb
Host smart-0d94da80-c55d-499a-aad8-bdc94574053f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312792189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.3312792189
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.543348428
Short name T269
Test name
Test status
Simulation time 779474404661 ps
CPU time 276.42 seconds
Started Jul 27 05:09:35 PM PDT 24
Finished Jul 27 05:14:12 PM PDT 24
Peak memory 196420 kb
Host smart-65199582-86f3-4aac-bd45-ffee6375ae33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543348428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all.
543348428
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/130.rv_timer_random.3530629979
Short name T94
Test name
Test status
Simulation time 271224545548 ps
CPU time 2499.57 seconds
Started Jul 27 05:11:06 PM PDT 24
Finished Jul 27 05:52:46 PM PDT 24
Peak memory 191632 kb
Host smart-0f2f8688-9638-428e-9296-c682f7ab4bbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530629979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.3530629979
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.3098617803
Short name T182
Test name
Test status
Simulation time 675395248950 ps
CPU time 1904.08 seconds
Started Jul 27 05:11:42 PM PDT 24
Finished Jul 27 05:43:27 PM PDT 24
Peak memory 191672 kb
Host smart-325ea983-8cdb-4e8a-b9a9-717f9fd19787
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098617803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.3098617803
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.2010039942
Short name T305
Test name
Test status
Simulation time 2311167128474 ps
CPU time 1776.96 seconds
Started Jul 27 05:10:11 PM PDT 24
Finished Jul 27 05:39:48 PM PDT 24
Peak memory 196196 kb
Host smart-60b15852-9561-4684-a74c-6ede9a0343df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010039942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.2010039942
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/150.rv_timer_random.1749881521
Short name T157
Test name
Test status
Simulation time 1070411039703 ps
CPU time 846.14 seconds
Started Jul 27 05:11:21 PM PDT 24
Finished Jul 27 05:25:28 PM PDT 24
Peak memory 191740 kb
Host smart-02ab31ba-471b-401d-a785-e605b495dd32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749881521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.1749881521
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random.932741558
Short name T142
Test name
Test status
Simulation time 200611464531 ps
CPU time 1639.27 seconds
Started Jul 27 05:09:39 PM PDT 24
Finished Jul 27 05:36:59 PM PDT 24
Peak memory 191724 kb
Host smart-b1282985-3db6-41c6-a9b6-12e174f52ffb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932741558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.932741558
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.2707937359
Short name T112
Test name
Test status
Simulation time 938210028807 ps
CPU time 484.11 seconds
Started Jul 27 05:10:53 PM PDT 24
Finished Jul 27 05:18:58 PM PDT 24
Peak memory 194032 kb
Host smart-45c6d231-d006-41d6-a3ff-26daea855eff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707937359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.2707937359
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.3105491876
Short name T116
Test name
Test status
Simulation time 394031789820 ps
CPU time 558.08 seconds
Started Jul 27 05:11:06 PM PDT 24
Finished Jul 27 05:20:24 PM PDT 24
Peak memory 191756 kb
Host smart-03966139-01f7-4818-a283-8904faf87926
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105491876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.3105491876
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/140.rv_timer_random.2277843547
Short name T136
Test name
Test status
Simulation time 281247844333 ps
CPU time 1755.14 seconds
Started Jul 27 05:11:06 PM PDT 24
Finished Jul 27 05:40:21 PM PDT 24
Peak memory 191716 kb
Host smart-7c85b956-ffde-4155-b76b-c01c36e7df30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277843547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.2277843547
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.3902736044
Short name T273
Test name
Test status
Simulation time 197569948200 ps
CPU time 186.61 seconds
Started Jul 27 05:09:36 PM PDT 24
Finished Jul 27 05:12:43 PM PDT 24
Peak memory 196716 kb
Host smart-5660f47a-ff45-4b98-a691-152d82e86ab1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902736044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
3902736044
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.922276700
Short name T47
Test name
Test status
Simulation time 611320316909 ps
CPU time 1188.73 seconds
Started Jul 27 05:09:37 PM PDT 24
Finished Jul 27 05:29:26 PM PDT 24
Peak memory 191696 kb
Host smart-59fce059-2e60-4db4-ad30-0de7e3ce84ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922276700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all.
922276700
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/131.rv_timer_random.544002244
Short name T263
Test name
Test status
Simulation time 51015688660 ps
CPU time 162.73 seconds
Started Jul 27 05:11:08 PM PDT 24
Finished Jul 27 05:13:50 PM PDT 24
Peak memory 191724 kb
Host smart-70fab9f8-ab82-447d-a74f-801cccc145a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544002244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.544002244
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.3435596423
Short name T25
Test name
Test status
Simulation time 416089546961 ps
CPU time 206.65 seconds
Started Jul 27 05:10:33 PM PDT 24
Finished Jul 27 05:13:59 PM PDT 24
Peak memory 191712 kb
Host smart-9b245541-82cb-4063-ad5b-e277cab70116
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435596423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.3435596423
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.1260368360
Short name T357
Test name
Test status
Simulation time 156930208322 ps
CPU time 320 seconds
Started Jul 27 05:10:58 PM PDT 24
Finished Jul 27 05:16:18 PM PDT 24
Peak memory 195384 kb
Host smart-08200190-5a34-4d8a-8589-d595131bff33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260368360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.1260368360
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.4210005799
Short name T240
Test name
Test status
Simulation time 355304177553 ps
CPU time 1277.42 seconds
Started Jul 27 05:11:42 PM PDT 24
Finished Jul 27 05:33:00 PM PDT 24
Peak memory 191656 kb
Host smart-4896222d-f6a1-4466-9b89-5cf9a0931c83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210005799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.4210005799
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.59625389
Short name T105
Test name
Test status
Simulation time 173619003411 ps
CPU time 253.68 seconds
Started Jul 27 05:09:47 PM PDT 24
Finished Jul 27 05:14:01 PM PDT 24
Peak memory 183496 kb
Host smart-9737a058-7006-4592-bec3-00ad227e940c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59625389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.rv_timer_cfg_update_on_fly.59625389
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.3124009603
Short name T335
Test name
Test status
Simulation time 101698358039 ps
CPU time 160.48 seconds
Started Jul 27 05:09:49 PM PDT 24
Finished Jul 27 05:12:29 PM PDT 24
Peak memory 183524 kb
Host smart-06c3f063-74f7-44d6-81c1-92200c256c0f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124009603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.3124009603
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.235301883
Short name T260
Test name
Test status
Simulation time 1633319985984 ps
CPU time 2422.63 seconds
Started Jul 27 05:10:08 PM PDT 24
Finished Jul 27 05:50:31 PM PDT 24
Peak memory 197428 kb
Host smart-fbca6760-9c3b-4cbb-8dc2-49fec1d5137e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235301883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all.
235301883
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/107.rv_timer_random.1131153185
Short name T99
Test name
Test status
Simulation time 542463190613 ps
CPU time 172.85 seconds
Started Jul 27 05:10:43 PM PDT 24
Finished Jul 27 05:13:36 PM PDT 24
Peak memory 191964 kb
Host smart-bcd2b67e-5e1f-4f27-988b-292f1f056850
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131153185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.1131153185
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.3285220872
Short name T251
Test name
Test status
Simulation time 102093293042 ps
CPU time 1093.92 seconds
Started Jul 27 05:11:22 PM PDT 24
Finished Jul 27 05:29:36 PM PDT 24
Peak memory 191672 kb
Host smart-cd52ab11-e4c6-40d9-bc7f-27c7be56dec1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285220872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.3285220872
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.1547313067
Short name T107
Test name
Test status
Simulation time 1498749678680 ps
CPU time 638.57 seconds
Started Jul 27 05:11:23 PM PDT 24
Finished Jul 27 05:22:01 PM PDT 24
Peak memory 191732 kb
Host smart-f48f7af8-b529-49e1-befd-e2d44bf0ba0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547313067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.1547313067
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.1723899255
Short name T102
Test name
Test status
Simulation time 165794670588 ps
CPU time 161.39 seconds
Started Jul 27 05:11:36 PM PDT 24
Finished Jul 27 05:14:18 PM PDT 24
Peak memory 191732 kb
Host smart-5e02089f-3943-4a2a-a2a7-11ad06268185
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723899255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.1723899255
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/170.rv_timer_random.3267794938
Short name T121
Test name
Test status
Simulation time 188674976687 ps
CPU time 209 seconds
Started Jul 27 05:11:36 PM PDT 24
Finished Jul 27 05:15:05 PM PDT 24
Peak memory 191720 kb
Host smart-6a1bbe33-27ed-40b4-85ee-2b4b29a60893
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267794938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.3267794938
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.4025921639
Short name T169
Test name
Test status
Simulation time 93755245310 ps
CPU time 1038.89 seconds
Started Jul 27 05:11:44 PM PDT 24
Finished Jul 27 05:29:03 PM PDT 24
Peak memory 191680 kb
Host smart-3fc5cf3b-d39d-4575-961b-a43cf9b0aff5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025921639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.4025921639
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.2989649973
Short name T130
Test name
Test status
Simulation time 726923387582 ps
CPU time 1948.78 seconds
Started Jul 27 05:09:29 PM PDT 24
Finished Jul 27 05:41:58 PM PDT 24
Peak memory 191740 kb
Host smart-69e39d2f-fd92-4a50-b515-b3113476351a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989649973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
2989649973
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.3103307734
Short name T301
Test name
Test status
Simulation time 79952311305 ps
CPU time 242.7 seconds
Started Jul 27 05:09:31 PM PDT 24
Finished Jul 27 05:13:34 PM PDT 24
Peak memory 183452 kb
Host smart-bfb41756-d73a-4b69-962d-5d606663e811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103307734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.3103307734
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/126.rv_timer_random.3412050258
Short name T95
Test name
Test status
Simulation time 224533932516 ps
CPU time 1854.87 seconds
Started Jul 27 05:11:05 PM PDT 24
Finished Jul 27 05:42:00 PM PDT 24
Peak memory 183460 kb
Host smart-e7e71fb6-e9c9-4e86-a2b5-9bfeadca3ec9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412050258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.3412050258
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.2085957228
Short name T262
Test name
Test status
Simulation time 400920495443 ps
CPU time 991.59 seconds
Started Jul 27 05:11:07 PM PDT 24
Finished Jul 27 05:27:39 PM PDT 24
Peak memory 191660 kb
Host smart-6dde093e-156b-4378-baf9-8fdfb0bf01c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085957228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.2085957228
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.523188148
Short name T219
Test name
Test status
Simulation time 111487135823 ps
CPU time 1455.25 seconds
Started Jul 27 05:11:42 PM PDT 24
Finished Jul 27 05:35:58 PM PDT 24
Peak memory 191652 kb
Host smart-f30614d4-cb1b-4cb1-9a8d-77a65e2f91eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523188148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.523188148
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random.3581895215
Short name T149
Test name
Test status
Simulation time 198603204200 ps
CPU time 173.02 seconds
Started Jul 27 05:10:05 PM PDT 24
Finished Jul 27 05:12:58 PM PDT 24
Peak memory 195420 kb
Host smart-5682ddd9-3a98-4779-9208-8d2a9838a38f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581895215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.3581895215
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random.640440090
Short name T152
Test name
Test status
Simulation time 458338158223 ps
CPU time 140.47 seconds
Started Jul 27 05:10:05 PM PDT 24
Finished Jul 27 05:12:26 PM PDT 24
Peak memory 191736 kb
Host smart-dfdf2d3c-1576-40ce-836a-6424713ffddc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640440090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.640440090
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.1587778637
Short name T129
Test name
Test status
Simulation time 79596357458 ps
CPU time 125 seconds
Started Jul 27 05:09:35 PM PDT 24
Finished Jul 27 05:11:40 PM PDT 24
Peak memory 183520 kb
Host smart-cfcdd96e-7723-4cc9-865f-45f59247eca5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587778637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.1587778637
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/87.rv_timer_random.529711396
Short name T268
Test name
Test status
Simulation time 651565235522 ps
CPU time 333.44 seconds
Started Jul 27 05:10:31 PM PDT 24
Finished Jul 27 05:16:05 PM PDT 24
Peak memory 191740 kb
Host smart-3f0d55bb-180e-4550-a3a8-4c45a0f596e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529711396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.529711396
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.407094560
Short name T83
Test name
Test status
Simulation time 37644800 ps
CPU time 0.63 seconds
Started Jul 27 05:08:52 PM PDT 24
Finished Jul 27 05:08:53 PM PDT 24
Peak memory 192232 kb
Host smart-333b9bdd-c890-4b43-a1b1-d591e8ffa2d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407094560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_tim
er_same_csr_outstanding.407094560
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rv_timer_random.1180866497
Short name T334
Test name
Test status
Simulation time 112831692997 ps
CPU time 83.84 seconds
Started Jul 27 05:09:25 PM PDT 24
Finished Jul 27 05:10:49 PM PDT 24
Peak memory 191760 kb
Host smart-9a33d5ac-623b-4d68-9bb1-2d81de8138a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180866497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.1180866497
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.1076177734
Short name T238
Test name
Test status
Simulation time 180773832070 ps
CPU time 293.94 seconds
Started Jul 27 05:09:26 PM PDT 24
Finished Jul 27 05:14:20 PM PDT 24
Peak memory 183536 kb
Host smart-26f4f9ac-592f-487a-9b42-2f08ad05d634
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076177734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.1076177734
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/100.rv_timer_random.2078799485
Short name T281
Test name
Test status
Simulation time 170258166136 ps
CPU time 702.78 seconds
Started Jul 27 05:10:43 PM PDT 24
Finished Jul 27 05:22:26 PM PDT 24
Peak memory 191736 kb
Host smart-21be9060-c994-4ff6-9f73-19ead2b7e24f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078799485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.2078799485
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.79776293
Short name T210
Test name
Test status
Simulation time 270111007962 ps
CPU time 147.05 seconds
Started Jul 27 05:11:07 PM PDT 24
Finished Jul 27 05:13:34 PM PDT 24
Peak memory 191680 kb
Host smart-9c484177-24b6-4a76-bc71-cf4a0f1534b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79776293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.79776293
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.1823197886
Short name T159
Test name
Test status
Simulation time 113950238573 ps
CPU time 130.5 seconds
Started Jul 27 05:11:07 PM PDT 24
Finished Jul 27 05:13:17 PM PDT 24
Peak memory 191656 kb
Host smart-f25c3f78-d37d-4b55-b148-86c8e180c24a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823197886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.1823197886
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.717568944
Short name T173
Test name
Test status
Simulation time 108193214186 ps
CPU time 199.28 seconds
Started Jul 27 05:11:35 PM PDT 24
Finished Jul 27 05:14:54 PM PDT 24
Peak memory 191660 kb
Host smart-3d742d08-d35d-42f0-b11f-5569124fea46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717568944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.717568944
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.3565464657
Short name T234
Test name
Test status
Simulation time 585416893764 ps
CPU time 528.26 seconds
Started Jul 27 05:11:35 PM PDT 24
Finished Jul 27 05:20:24 PM PDT 24
Peak memory 191700 kb
Host smart-fabf956e-f19c-422b-84db-54a5ef198ccc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565464657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.3565464657
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.954152351
Short name T213
Test name
Test status
Simulation time 655465290873 ps
CPU time 959.88 seconds
Started Jul 27 05:11:35 PM PDT 24
Finished Jul 27 05:27:35 PM PDT 24
Peak memory 191704 kb
Host smart-e3aa803b-61ca-4b58-8907-75615307c26b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954152351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.954152351
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.3211030780
Short name T256
Test name
Test status
Simulation time 311302317575 ps
CPU time 332.14 seconds
Started Jul 27 05:09:52 PM PDT 24
Finished Jul 27 05:15:24 PM PDT 24
Peak memory 191736 kb
Host smart-e9ea0881-35ad-403f-86a9-749b50cdb912
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211030780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.3211030780
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_random.705484487
Short name T246
Test name
Test status
Simulation time 83741322943 ps
CPU time 1219.02 seconds
Started Jul 27 05:09:57 PM PDT 24
Finished Jul 27 05:30:16 PM PDT 24
Peak memory 191648 kb
Host smart-2ef3a4e7-b127-4dde-bddb-b2247c625de6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705484487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.705484487
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.2993066233
Short name T221
Test name
Test status
Simulation time 414298476414 ps
CPU time 219.87 seconds
Started Jul 27 05:09:56 PM PDT 24
Finished Jul 27 05:13:36 PM PDT 24
Peak memory 196160 kb
Host smart-876b772e-eafd-4ed9-b87f-bdab8041e73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993066233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.2993066233
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.3967913758
Short name T426
Test name
Test status
Simulation time 254281874467 ps
CPU time 455.72 seconds
Started Jul 27 05:10:07 PM PDT 24
Finished Jul 27 05:17:43 PM PDT 24
Peak memory 183284 kb
Host smart-e8aa0a6e-72c3-4c07-83b5-9d41757d037a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967913758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.3967913758
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.799799371
Short name T119
Test name
Test status
Simulation time 820769177019 ps
CPU time 859.25 seconds
Started Jul 27 05:10:15 PM PDT 24
Finished Jul 27 05:24:34 PM PDT 24
Peak memory 191748 kb
Host smart-4942b36d-6f03-4921-bfca-4050cfb9b64e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799799371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all.
799799371
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/92.rv_timer_random.1907724867
Short name T199
Test name
Test status
Simulation time 77407695407 ps
CPU time 37.63 seconds
Started Jul 27 05:10:33 PM PDT 24
Finished Jul 27 05:11:11 PM PDT 24
Peak memory 191732 kb
Host smart-5975dd47-6712-4cf4-bb6c-5589bbdff8d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907724867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.1907724867
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.977236174
Short name T88
Test name
Test status
Simulation time 452878763 ps
CPU time 1.09 seconds
Started Jul 27 05:08:54 PM PDT 24
Finished Jul 27 05:08:55 PM PDT 24
Peak memory 183504 kb
Host smart-a59553fb-972e-4d96-976a-52228b0bfa65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977236174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_int
g_err.977236174
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.2765715922
Short name T90
Test name
Test status
Simulation time 118666830 ps
CPU time 1.32 seconds
Started Jul 27 05:09:08 PM PDT 24
Finished Jul 27 05:09:09 PM PDT 24
Peak memory 195296 kb
Host smart-562fbed4-fff2-4e5e-af07-34186ba3337c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765715922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.2765715922
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.2751074896
Short name T5
Test name
Test status
Simulation time 36315596007 ps
CPU time 18.9 seconds
Started Jul 27 05:09:27 PM PDT 24
Finished Jul 27 05:09:46 PM PDT 24
Peak memory 183528 kb
Host smart-aef0c07d-b573-48cd-bb56-59fae73199dd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751074896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.2751074896
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/108.rv_timer_random.2943349167
Short name T114
Test name
Test status
Simulation time 298551581925 ps
CPU time 1097.9 seconds
Started Jul 27 05:10:44 PM PDT 24
Finished Jul 27 05:29:02 PM PDT 24
Peak memory 194880 kb
Host smart-b5e45871-64a4-4d7d-83ec-4d2e07d024f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943349167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.2943349167
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.1090576619
Short name T225
Test name
Test status
Simulation time 89939882891 ps
CPU time 122.71 seconds
Started Jul 27 05:10:44 PM PDT 24
Finished Jul 27 05:12:47 PM PDT 24
Peak memory 194496 kb
Host smart-6e442262-2144-4db2-b895-8e7c4985a060
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090576619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.1090576619
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.3150345385
Short name T208
Test name
Test status
Simulation time 3606803054670 ps
CPU time 1314.72 seconds
Started Jul 27 05:10:57 PM PDT 24
Finished Jul 27 05:32:53 PM PDT 24
Peak memory 191728 kb
Host smart-680e9041-eeb5-4d35-9783-fc2f6827f850
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150345385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.3150345385
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.3581763387
Short name T254
Test name
Test status
Simulation time 103204251726 ps
CPU time 82.34 seconds
Started Jul 27 05:11:11 PM PDT 24
Finished Jul 27 05:12:34 PM PDT 24
Peak memory 191728 kb
Host smart-4c2a1871-fe23-43c1-af04-989b34442f59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581763387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.3581763387
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random.407810833
Short name T285
Test name
Test status
Simulation time 113682510997 ps
CPU time 522.7 seconds
Started Jul 27 05:09:38 PM PDT 24
Finished Jul 27 05:18:21 PM PDT 24
Peak memory 191736 kb
Host smart-7d649642-a738-4ebc-a2bd-680632114162
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407810833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.407810833
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.2550647290
Short name T138
Test name
Test status
Simulation time 301608484455 ps
CPU time 441.83 seconds
Started Jul 27 05:09:37 PM PDT 24
Finished Jul 27 05:16:59 PM PDT 24
Peak memory 191696 kb
Host smart-93fc1041-23c2-4b85-88a7-5dc0add7fb51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550647290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.2550647290
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/144.rv_timer_random.1309434296
Short name T22
Test name
Test status
Simulation time 714612929317 ps
CPU time 345.21 seconds
Started Jul 27 05:11:21 PM PDT 24
Finished Jul 27 05:17:06 PM PDT 24
Peak memory 191628 kb
Host smart-97fde583-1d72-4027-99a5-89ed5bfff0db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309434296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.1309434296
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.771907427
Short name T215
Test name
Test status
Simulation time 35049859505 ps
CPU time 98.06 seconds
Started Jul 27 05:11:58 PM PDT 24
Finished Jul 27 05:13:36 PM PDT 24
Peak memory 194564 kb
Host smart-1444dbf4-e0f5-4f48-a076-3a3c66502272
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771907427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.771907427
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.1701871031
Short name T280
Test name
Test status
Simulation time 24283375543 ps
CPU time 33.28 seconds
Started Jul 27 05:11:21 PM PDT 24
Finished Jul 27 05:11:55 PM PDT 24
Peak memory 183268 kb
Host smart-b537dde6-ad7f-40c4-8ffa-014a21eddc4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701871031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.1701871031
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.2234098205
Short name T122
Test name
Test status
Simulation time 111424083141 ps
CPU time 228.12 seconds
Started Jul 27 05:11:22 PM PDT 24
Finished Jul 27 05:15:10 PM PDT 24
Peak memory 191732 kb
Host smart-08f47af9-9f7c-4eb0-9a52-a5cf24469730
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234098205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.2234098205
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.4075473109
Short name T309
Test name
Test status
Simulation time 49163299814 ps
CPU time 289.58 seconds
Started Jul 27 05:11:37 PM PDT 24
Finished Jul 27 05:16:27 PM PDT 24
Peak memory 191664 kb
Host smart-7371459d-4278-47a2-a06b-cf81736a8e9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075473109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.4075473109
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.2098324198
Short name T261
Test name
Test status
Simulation time 64672099111 ps
CPU time 99.88 seconds
Started Jul 27 05:11:35 PM PDT 24
Finished Jul 27 05:13:15 PM PDT 24
Peak memory 191660 kb
Host smart-c004dc76-3c2c-4fa3-a2d0-c9344f0fd889
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098324198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.2098324198
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.1164948927
Short name T7
Test name
Test status
Simulation time 168259849899 ps
CPU time 315.04 seconds
Started Jul 27 05:11:37 PM PDT 24
Finished Jul 27 05:16:52 PM PDT 24
Peak memory 191712 kb
Host smart-989898af-42f3-4082-a275-c4db3636647b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164948927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.1164948927
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.2339301832
Short name T164
Test name
Test status
Simulation time 102596496992 ps
CPU time 1686.88 seconds
Started Jul 27 05:11:37 PM PDT 24
Finished Jul 27 05:39:44 PM PDT 24
Peak memory 191740 kb
Host smart-d884c1ca-c782-4c93-8374-55f4efc31d6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339301832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.2339301832
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random.3463298177
Short name T320
Test name
Test status
Simulation time 658820941069 ps
CPU time 1576.06 seconds
Started Jul 27 05:09:50 PM PDT 24
Finished Jul 27 05:36:07 PM PDT 24
Peak memory 191640 kb
Host smart-aa51507a-23c5-43dd-b0b9-f0d7dd0ceff9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463298177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.3463298177
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/190.rv_timer_random.1892010582
Short name T229
Test name
Test status
Simulation time 292433529005 ps
CPU time 169.65 seconds
Started Jul 27 05:11:42 PM PDT 24
Finished Jul 27 05:14:32 PM PDT 24
Peak memory 191756 kb
Host smart-4fcbd458-cee4-44ac-a1f7-5974e08bfaa2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892010582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.1892010582
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.3823998464
Short name T26
Test name
Test status
Simulation time 69840191974 ps
CPU time 232.2 seconds
Started Jul 27 05:11:43 PM PDT 24
Finished Jul 27 05:15:35 PM PDT 24
Peak memory 191712 kb
Host smart-dd7f1e7f-718b-4b80-ba35-7a492b1828f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823998464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.3823998464
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.1165561184
Short name T347
Test name
Test status
Simulation time 63250734193 ps
CPU time 90.2 seconds
Started Jul 27 05:11:43 PM PDT 24
Finished Jul 27 05:13:13 PM PDT 24
Peak memory 183512 kb
Host smart-b9d9b8f0-5f6f-4fb2-918e-7ff04a616640
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165561184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.1165561184
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random.974596776
Short name T190
Test name
Test status
Simulation time 123205730774 ps
CPU time 116.54 seconds
Started Jul 27 05:09:45 PM PDT 24
Finished Jul 27 05:11:42 PM PDT 24
Peak memory 191712 kb
Host smart-8a7865e4-660a-479e-bf19-5b3af1f3436a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974596776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.974596776
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.1509811125
Short name T293
Test name
Test status
Simulation time 450142458185 ps
CPU time 719.17 seconds
Started Jul 27 05:09:46 PM PDT 24
Finished Jul 27 05:21:45 PM PDT 24
Peak memory 183508 kb
Host smart-0940f19e-0d11-4ea7-88a1-08b0ec60473b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509811125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.1509811125
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.4070325283
Short name T162
Test name
Test status
Simulation time 153208398875 ps
CPU time 518.35 seconds
Started Jul 27 05:09:55 PM PDT 24
Finished Jul 27 05:18:34 PM PDT 24
Peak memory 191648 kb
Host smart-894a508b-44c6-479a-a067-3c791788691b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070325283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.4070325283
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_random.1203429181
Short name T312
Test name
Test status
Simulation time 67443879932 ps
CPU time 108.06 seconds
Started Jul 27 05:09:55 PM PDT 24
Finished Jul 27 05:11:43 PM PDT 24
Peak memory 191732 kb
Host smart-a96c9d43-3eae-4fb0-891b-9e4d3c1769a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203429181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.1203429181
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.4225946543
Short name T290
Test name
Test status
Simulation time 101711579285 ps
CPU time 35.51 seconds
Started Jul 27 05:10:06 PM PDT 24
Finished Jul 27 05:10:42 PM PDT 24
Peak memory 183524 kb
Host smart-6edd2531-e603-4ae2-98ec-d335ddd09222
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225946543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.4225946543
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.173406929
Short name T343
Test name
Test status
Simulation time 56807268065 ps
CPU time 44.81 seconds
Started Jul 27 05:10:14 PM PDT 24
Finished Jul 27 05:10:59 PM PDT 24
Peak memory 194940 kb
Host smart-59757924-837e-41f1-837a-1d3e72ad8e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173406929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.173406929
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.81516149
Short name T344
Test name
Test status
Simulation time 394248563191 ps
CPU time 153.75 seconds
Started Jul 27 05:10:15 PM PDT 24
Finished Jul 27 05:12:48 PM PDT 24
Peak memory 191748 kb
Host smart-d03a9e54-0bdc-4185-92f2-d2c0b3dd767b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81516149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.81516149
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/56.rv_timer_random.2400594781
Short name T174
Test name
Test status
Simulation time 248611339685 ps
CPU time 1448.91 seconds
Started Jul 27 05:10:16 PM PDT 24
Finished Jul 27 05:34:25 PM PDT 24
Peak memory 191692 kb
Host smart-3cda9722-40aa-46b0-a821-14df66060e43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400594781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.2400594781
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3479678487
Short name T77
Test name
Test status
Simulation time 136810800 ps
CPU time 0.8 seconds
Started Jul 27 05:08:59 PM PDT 24
Finished Jul 27 05:08:59 PM PDT 24
Peak memory 182888 kb
Host smart-54d8fb20-cad6-4b9e-b056-a0fbfe304c22
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479678487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.3479678487
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.203641359
Short name T553
Test name
Test status
Simulation time 181777222 ps
CPU time 3.13 seconds
Started Jul 27 05:09:00 PM PDT 24
Finished Jul 27 05:09:04 PM PDT 24
Peak memory 191228 kb
Host smart-0e5f9840-ba6e-48c6-8374-1c43c2db59a1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203641359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_b
ash.203641359
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.268060531
Short name T527
Test name
Test status
Simulation time 44000821 ps
CPU time 1.06 seconds
Started Jul 27 05:08:57 PM PDT 24
Finished Jul 27 05:08:58 PM PDT 24
Peak memory 197512 kb
Host smart-70265fd0-50b5-4d8d-9fa0-4082051c5070
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268060531 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.268060531
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.116372794
Short name T516
Test name
Test status
Simulation time 30443947 ps
CPU time 0.55 seconds
Started Jul 27 05:08:55 PM PDT 24
Finished Jul 27 05:08:55 PM PDT 24
Peak memory 182756 kb
Host smart-6967c785-a20f-4ca8-b337-9e41129edb6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116372794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.116372794
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.1223834046
Short name T519
Test name
Test status
Simulation time 39115899 ps
CPU time 0.55 seconds
Started Jul 27 05:08:55 PM PDT 24
Finished Jul 27 05:08:56 PM PDT 24
Peak memory 182856 kb
Host smart-90fc2406-23aa-484b-abb4-f5353a38c45d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223834046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.1223834046
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.4216842880
Short name T571
Test name
Test status
Simulation time 117286448 ps
CPU time 1.4 seconds
Started Jul 27 05:08:53 PM PDT 24
Finished Jul 27 05:08:55 PM PDT 24
Peak memory 197684 kb
Host smart-0dafa7b6-719b-46e1-a37f-9fa4d6190c7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216842880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.4216842880
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1616809081
Short name T524
Test name
Test status
Simulation time 53401599 ps
CPU time 0.83 seconds
Started Jul 27 05:08:54 PM PDT 24
Finished Jul 27 05:08:55 PM PDT 24
Peak memory 193376 kb
Host smart-9667c539-2ff6-4c53-b920-4bfe5a938740
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616809081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.1616809081
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.1344803437
Short name T509
Test name
Test status
Simulation time 58590999 ps
CPU time 0.81 seconds
Started Jul 27 05:08:57 PM PDT 24
Finished Jul 27 05:08:58 PM PDT 24
Peak memory 192584 kb
Host smart-cc154a04-2079-45e6-b612-c57dc218566c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344803437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.1344803437
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.1204964486
Short name T64
Test name
Test status
Simulation time 347157277 ps
CPU time 3.17 seconds
Started Jul 27 05:08:57 PM PDT 24
Finished Jul 27 05:09:01 PM PDT 24
Peak memory 191260 kb
Host smart-2d5a2f59-27ae-4442-9f08-9888efaf012e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204964486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.1204964486
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.3587427197
Short name T504
Test name
Test status
Simulation time 15919277 ps
CPU time 0.57 seconds
Started Jul 27 05:08:58 PM PDT 24
Finished Jul 27 05:08:59 PM PDT 24
Peak memory 182852 kb
Host smart-d2552911-e648-4704-ab1d-d1e3cde959da
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587427197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.3587427197
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.2947451483
Short name T34
Test name
Test status
Simulation time 46228124 ps
CPU time 0.67 seconds
Started Jul 27 05:08:54 PM PDT 24
Finished Jul 27 05:08:55 PM PDT 24
Peak memory 194384 kb
Host smart-cb09b0a0-3619-42db-922c-09bddc2cda95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947451483 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.2947451483
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.212014873
Short name T79
Test name
Test status
Simulation time 23829419 ps
CPU time 0.56 seconds
Started Jul 27 05:08:55 PM PDT 24
Finished Jul 27 05:08:56 PM PDT 24
Peak memory 182952 kb
Host smart-cc50e1ac-6b18-4ce1-8378-68805cdd9614
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212014873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.212014873
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.1735059536
Short name T562
Test name
Test status
Simulation time 29161133 ps
CPU time 0.54 seconds
Started Jul 27 05:08:54 PM PDT 24
Finished Jul 27 05:08:54 PM PDT 24
Peak memory 182784 kb
Host smart-427add07-47b3-4bae-a2d3-9bb4bf5d6e83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735059536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.1735059536
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.2561945215
Short name T85
Test name
Test status
Simulation time 36208814 ps
CPU time 0.82 seconds
Started Jul 27 05:08:55 PM PDT 24
Finished Jul 27 05:08:56 PM PDT 24
Peak memory 193572 kb
Host smart-b77f0335-9133-4905-9add-eb32f599c0a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561945215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.2561945215
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.4100448052
Short name T511
Test name
Test status
Simulation time 70837382 ps
CPU time 1.37 seconds
Started Jul 27 05:08:55 PM PDT 24
Finished Jul 27 05:08:57 PM PDT 24
Peak memory 197652 kb
Host smart-c83dde23-523c-465a-8d1f-2bc51f09bbb9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100448052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.4100448052
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.1560030547
Short name T563
Test name
Test status
Simulation time 86692119 ps
CPU time 0.84 seconds
Started Jul 27 05:09:09 PM PDT 24
Finished Jul 27 05:09:10 PM PDT 24
Peak memory 196492 kb
Host smart-1481fa52-c9b3-4528-bfd4-6a601693ef7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560030547 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.1560030547
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.2563224762
Short name T566
Test name
Test status
Simulation time 22219829 ps
CPU time 0.57 seconds
Started Jul 27 05:09:07 PM PDT 24
Finished Jul 27 05:09:07 PM PDT 24
Peak memory 182832 kb
Host smart-6187fd29-87e1-4a77-aa4a-b5a01d36bdb2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563224762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.2563224762
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.2058112959
Short name T492
Test name
Test status
Simulation time 16076500 ps
CPU time 0.52 seconds
Started Jul 27 05:09:07 PM PDT 24
Finished Jul 27 05:09:08 PM PDT 24
Peak memory 182464 kb
Host smart-45b8c69d-392b-47ce-ad0c-06db908fe672
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058112959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.2058112959
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.3580096279
Short name T63
Test name
Test status
Simulation time 125928688 ps
CPU time 0.86 seconds
Started Jul 27 05:09:07 PM PDT 24
Finished Jul 27 05:09:08 PM PDT 24
Peak memory 194700 kb
Host smart-107ebca0-1814-47d7-aff1-a8d7115e412b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580096279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.3580096279
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1829615898
Short name T472
Test name
Test status
Simulation time 747870590 ps
CPU time 1.31 seconds
Started Jul 27 05:09:05 PM PDT 24
Finished Jul 27 05:09:06 PM PDT 24
Peak memory 197644 kb
Host smart-2672340c-42e4-4d57-8c81-b7366ad2fa98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829615898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.1829615898
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1311030446
Short name T565
Test name
Test status
Simulation time 248843458 ps
CPU time 0.83 seconds
Started Jul 27 05:09:10 PM PDT 24
Finished Jul 27 05:09:11 PM PDT 24
Peak memory 183308 kb
Host smart-1f717170-468b-4f0a-98d2-e8800b0406e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311030446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.1311030446
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.649887248
Short name T541
Test name
Test status
Simulation time 79035624 ps
CPU time 0.71 seconds
Started Jul 27 05:09:08 PM PDT 24
Finished Jul 27 05:09:09 PM PDT 24
Peak memory 194544 kb
Host smart-4cfa40a3-2937-4602-8102-a23d6cfa08ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649887248 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.649887248
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.124621595
Short name T520
Test name
Test status
Simulation time 28752665 ps
CPU time 0.56 seconds
Started Jul 27 05:09:10 PM PDT 24
Finished Jul 27 05:09:10 PM PDT 24
Peak memory 182840 kb
Host smart-50129530-c897-48d6-8d5d-4eb0af103e75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124621595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.124621595
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.811097723
Short name T538
Test name
Test status
Simulation time 49900587 ps
CPU time 0.55 seconds
Started Jul 27 05:09:08 PM PDT 24
Finished Jul 27 05:09:09 PM PDT 24
Peak memory 182836 kb
Host smart-eb09184f-1cb2-4d0f-8254-c21b3aab8fd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811097723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.811097723
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.291305143
Short name T86
Test name
Test status
Simulation time 51588379 ps
CPU time 0.74 seconds
Started Jul 27 05:09:10 PM PDT 24
Finished Jul 27 05:09:11 PM PDT 24
Peak memory 193356 kb
Host smart-0cb23bfa-a035-403b-b87d-b27475e69297
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291305143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_ti
mer_same_csr_outstanding.291305143
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.1270337409
Short name T464
Test name
Test status
Simulation time 771412294 ps
CPU time 0.97 seconds
Started Jul 27 05:09:06 PM PDT 24
Finished Jul 27 05:09:07 PM PDT 24
Peak memory 196096 kb
Host smart-e6ec0020-f16d-448c-b2db-fde9054009f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270337409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.1270337409
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.391614952
Short name T561
Test name
Test status
Simulation time 65790635 ps
CPU time 0.64 seconds
Started Jul 27 05:09:18 PM PDT 24
Finished Jul 27 05:09:19 PM PDT 24
Peak memory 194236 kb
Host smart-4e1c74b9-e26b-46e0-8758-50791dcc1fda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391614952 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.391614952
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1297071002
Short name T78
Test name
Test status
Simulation time 17296970 ps
CPU time 0.58 seconds
Started Jul 27 05:09:08 PM PDT 24
Finished Jul 27 05:09:09 PM PDT 24
Peak memory 182944 kb
Host smart-a0115984-7599-4e79-b905-42973b2ff650
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297071002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.1297071002
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.413237716
Short name T552
Test name
Test status
Simulation time 177476731 ps
CPU time 0.54 seconds
Started Jul 27 05:09:09 PM PDT 24
Finished Jul 27 05:09:10 PM PDT 24
Peak memory 182268 kb
Host smart-58a1a5c9-2882-4276-98ef-8908560922f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413237716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.413237716
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1364897404
Short name T501
Test name
Test status
Simulation time 51950384 ps
CPU time 0.65 seconds
Started Jul 27 05:09:06 PM PDT 24
Finished Jul 27 05:09:07 PM PDT 24
Peak memory 192480 kb
Host smart-c06b2268-90b1-44c4-ae3a-6f3eb63eb355
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364897404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.1364897404
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.873981624
Short name T482
Test name
Test status
Simulation time 137525750 ps
CPU time 1.32 seconds
Started Jul 27 05:09:11 PM PDT 24
Finished Jul 27 05:09:12 PM PDT 24
Peak memory 197616 kb
Host smart-25cd0623-0bda-4c71-a414-099727427cf1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873981624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.873981624
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.1567351640
Short name T576
Test name
Test status
Simulation time 49456998 ps
CPU time 0.85 seconds
Started Jul 27 05:09:10 PM PDT 24
Finished Jul 27 05:09:11 PM PDT 24
Peak memory 193604 kb
Host smart-e948f9e4-67d1-42cc-8881-d17dc4e5039c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567351640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.1567351640
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.3898217237
Short name T468
Test name
Test status
Simulation time 511804190 ps
CPU time 0.76 seconds
Started Jul 27 05:09:19 PM PDT 24
Finished Jul 27 05:09:20 PM PDT 24
Peak memory 194664 kb
Host smart-be8b7103-07fa-4892-9f98-7a6c9c83e820
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898217237 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.3898217237
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3090857055
Short name T570
Test name
Test status
Simulation time 46533392 ps
CPU time 0.57 seconds
Started Jul 27 05:09:15 PM PDT 24
Finished Jul 27 05:09:16 PM PDT 24
Peak memory 182844 kb
Host smart-6c36f9bf-c575-4177-a3cf-d1b3bfa36ca9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090857055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.3090857055
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.1116709544
Short name T461
Test name
Test status
Simulation time 52924054 ps
CPU time 0.55 seconds
Started Jul 27 05:09:15 PM PDT 24
Finished Jul 27 05:09:16 PM PDT 24
Peak memory 182688 kb
Host smart-11a88e3c-6222-4bdd-80d8-afd43bdc3496
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116709544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.1116709544
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1708172997
Short name T526
Test name
Test status
Simulation time 176823895 ps
CPU time 0.75 seconds
Started Jul 27 05:09:18 PM PDT 24
Finished Jul 27 05:09:19 PM PDT 24
Peak memory 193648 kb
Host smart-797f26b0-f3d1-46ae-833a-74d68398d165
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708172997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.1708172997
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.582089271
Short name T572
Test name
Test status
Simulation time 123467192 ps
CPU time 1.42 seconds
Started Jul 27 05:09:22 PM PDT 24
Finished Jul 27 05:09:24 PM PDT 24
Peak memory 197668 kb
Host smart-6725b6c8-bae5-408c-b6a6-31b42334c26d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582089271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.582089271
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1464349058
Short name T30
Test name
Test status
Simulation time 46205357 ps
CPU time 0.76 seconds
Started Jul 27 05:09:16 PM PDT 24
Finished Jul 27 05:09:17 PM PDT 24
Peak memory 193520 kb
Host smart-c813b218-a77a-4b12-9d87-ac33b729272d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464349058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.1464349058
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.3771729185
Short name T496
Test name
Test status
Simulation time 41310843 ps
CPU time 0.6 seconds
Started Jul 27 05:09:19 PM PDT 24
Finished Jul 27 05:09:20 PM PDT 24
Peak memory 193960 kb
Host smart-4be258d6-369d-4b74-92a2-7942a324ba11
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771729185 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.3771729185
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3404599373
Short name T76
Test name
Test status
Simulation time 29665245 ps
CPU time 0.56 seconds
Started Jul 27 05:09:17 PM PDT 24
Finished Jul 27 05:09:18 PM PDT 24
Peak memory 182916 kb
Host smart-2b5f020d-23ee-4a41-a6f3-5df8f290a073
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404599373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.3404599373
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.2381315710
Short name T515
Test name
Test status
Simulation time 31041979 ps
CPU time 0.56 seconds
Started Jul 27 05:09:22 PM PDT 24
Finished Jul 27 05:09:23 PM PDT 24
Peak memory 182784 kb
Host smart-fdc0297e-ae36-47a3-85fa-e47212100559
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381315710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.2381315710
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.3297687183
Short name T66
Test name
Test status
Simulation time 78070100 ps
CPU time 0.66 seconds
Started Jul 27 05:09:15 PM PDT 24
Finished Jul 27 05:09:16 PM PDT 24
Peak memory 192152 kb
Host smart-22def555-5774-476f-a52f-6945f8aaa3d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297687183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.3297687183
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.123530879
Short name T502
Test name
Test status
Simulation time 66228839 ps
CPU time 2.79 seconds
Started Jul 27 05:09:20 PM PDT 24
Finished Jul 27 05:09:23 PM PDT 24
Peak memory 197644 kb
Host smart-e43a91bc-99b9-4cdf-845c-57f1a0a49893
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123530879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.123530879
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.575307351
Short name T574
Test name
Test status
Simulation time 363949995 ps
CPU time 1.1 seconds
Started Jul 27 05:09:19 PM PDT 24
Finished Jul 27 05:09:20 PM PDT 24
Peak memory 183300 kb
Host smart-0f5640ca-580e-4aac-b0e2-93472a0f3d1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575307351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_in
tg_err.575307351
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1800318098
Short name T467
Test name
Test status
Simulation time 29116381 ps
CPU time 0.8 seconds
Started Jul 27 05:09:19 PM PDT 24
Finished Jul 27 05:09:20 PM PDT 24
Peak memory 197072 kb
Host smart-7bd8bd65-805f-468a-b472-ca673e192436
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800318098 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.1800318098
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.124789197
Short name T557
Test name
Test status
Simulation time 14790685 ps
CPU time 0.58 seconds
Started Jul 27 05:09:17 PM PDT 24
Finished Jul 27 05:09:18 PM PDT 24
Peak memory 182916 kb
Host smart-8ac930f7-c179-491a-a0d9-85d592c12914
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124789197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.124789197
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.3812239224
Short name T533
Test name
Test status
Simulation time 13305338 ps
CPU time 0.52 seconds
Started Jul 27 05:09:18 PM PDT 24
Finished Jul 27 05:09:19 PM PDT 24
Peak memory 182304 kb
Host smart-61897a90-1a4e-4d9c-a63d-9f23435577bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812239224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.3812239224
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.2234732005
Short name T548
Test name
Test status
Simulation time 17100898 ps
CPU time 0.61 seconds
Started Jul 27 05:09:22 PM PDT 24
Finished Jul 27 05:09:23 PM PDT 24
Peak memory 191644 kb
Host smart-359fb625-6601-46ea-9157-c827cabb45b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234732005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.2234732005
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.3465630919
Short name T508
Test name
Test status
Simulation time 170746435 ps
CPU time 3.03 seconds
Started Jul 27 05:09:18 PM PDT 24
Finished Jul 27 05:09:21 PM PDT 24
Peak memory 197564 kb
Host smart-baef7f1f-ebcb-46db-87b1-eba1b37549bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465630919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.3465630919
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.4132476786
Short name T555
Test name
Test status
Simulation time 307570242 ps
CPU time 1.11 seconds
Started Jul 27 05:09:20 PM PDT 24
Finished Jul 27 05:09:21 PM PDT 24
Peak memory 195152 kb
Host smart-87c0f960-819a-48d3-9c30-5962d62787df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132476786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.4132476786
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.978017195
Short name T551
Test name
Test status
Simulation time 83005958 ps
CPU time 0.7 seconds
Started Jul 27 05:09:21 PM PDT 24
Finished Jul 27 05:09:22 PM PDT 24
Peak memory 194960 kb
Host smart-2c927458-04fe-4020-bf9e-cb49a81a6e29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978017195 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.978017195
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.3593063606
Short name T480
Test name
Test status
Simulation time 10844379 ps
CPU time 0.54 seconds
Started Jul 27 05:09:17 PM PDT 24
Finished Jul 27 05:09:18 PM PDT 24
Peak memory 182640 kb
Host smart-91b1666c-8450-4fc7-9e8e-1a488f4f7508
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593063606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.3593063606
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2202051553
Short name T512
Test name
Test status
Simulation time 22162455 ps
CPU time 0.51 seconds
Started Jul 27 05:09:21 PM PDT 24
Finished Jul 27 05:09:21 PM PDT 24
Peak memory 182292 kb
Host smart-910dbe99-48ea-411a-8b53-5e1ab8d74d1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202051553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.2202051553
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1746102631
Short name T549
Test name
Test status
Simulation time 33805598 ps
CPU time 0.75 seconds
Started Jul 27 05:09:21 PM PDT 24
Finished Jul 27 05:09:22 PM PDT 24
Peak memory 193516 kb
Host smart-40e9e51c-55b9-41e8-b068-165ba2842c2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746102631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.1746102631
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.4058565753
Short name T542
Test name
Test status
Simulation time 33294404 ps
CPU time 1.54 seconds
Started Jul 27 05:09:17 PM PDT 24
Finished Jul 27 05:09:19 PM PDT 24
Peak memory 197612 kb
Host smart-0922a40d-cc7e-4f87-91fa-a0c31129a105
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058565753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.4058565753
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.586577066
Short name T550
Test name
Test status
Simulation time 595290053 ps
CPU time 0.95 seconds
Started Jul 27 05:09:20 PM PDT 24
Finished Jul 27 05:09:21 PM PDT 24
Peak memory 193728 kb
Host smart-b9bd9c9a-2ff2-4564-ae18-4652bfcf542f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586577066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_in
tg_err.586577066
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.2951124453
Short name T506
Test name
Test status
Simulation time 65578604 ps
CPU time 0.7 seconds
Started Jul 27 05:09:19 PM PDT 24
Finished Jul 27 05:09:19 PM PDT 24
Peak memory 195496 kb
Host smart-7c6e9a29-6070-400d-bb1b-b7ed2ed91ffc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951124453 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.2951124453
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.1641592882
Short name T560
Test name
Test status
Simulation time 16745764 ps
CPU time 0.63 seconds
Started Jul 27 05:09:17 PM PDT 24
Finished Jul 27 05:09:18 PM PDT 24
Peak memory 182944 kb
Host smart-03b62a21-1eb5-4997-80ec-054b5b69d127
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641592882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.1641592882
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1638005008
Short name T457
Test name
Test status
Simulation time 24809803 ps
CPU time 0.53 seconds
Started Jul 27 05:09:17 PM PDT 24
Finished Jul 27 05:09:17 PM PDT 24
Peak memory 182796 kb
Host smart-b09d7e99-c7de-4450-8ec2-7a4b2f71b23c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638005008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.1638005008
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.454779125
Short name T80
Test name
Test status
Simulation time 41188936 ps
CPU time 0.65 seconds
Started Jul 27 05:09:18 PM PDT 24
Finished Jul 27 05:09:19 PM PDT 24
Peak memory 191832 kb
Host smart-9e8f408d-6b3f-444d-a2ba-f81c7494fd21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454779125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_ti
mer_same_csr_outstanding.454779125
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.760422788
Short name T476
Test name
Test status
Simulation time 69959796 ps
CPU time 1.05 seconds
Started Jul 27 05:09:21 PM PDT 24
Finished Jul 27 05:09:22 PM PDT 24
Peak memory 197668 kb
Host smart-034d21d5-935f-4097-94e5-2b57e2e03cfe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760422788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.760422788
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.1768683554
Short name T87
Test name
Test status
Simulation time 369920262 ps
CPU time 1.07 seconds
Started Jul 27 05:09:19 PM PDT 24
Finished Jul 27 05:09:21 PM PDT 24
Peak memory 183200 kb
Host smart-7bb6029d-271f-4cee-9377-5492c9300ec8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768683554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.1768683554
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.2086723951
Short name T578
Test name
Test status
Simulation time 18451986 ps
CPU time 0.9 seconds
Started Jul 27 05:09:23 PM PDT 24
Finished Jul 27 05:09:24 PM PDT 24
Peak memory 197648 kb
Host smart-e102d6c5-1de2-43c0-8794-89612d0f9a91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086723951 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.2086723951
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.2942879605
Short name T82
Test name
Test status
Simulation time 15061863 ps
CPU time 0.62 seconds
Started Jul 27 05:09:22 PM PDT 24
Finished Jul 27 05:09:23 PM PDT 24
Peak memory 182912 kb
Host smart-94a68d0f-6b4a-4b21-bfe6-7e82a72d88f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942879605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.2942879605
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.3111677093
Short name T518
Test name
Test status
Simulation time 15470883 ps
CPU time 0.56 seconds
Started Jul 27 05:09:18 PM PDT 24
Finished Jul 27 05:09:19 PM PDT 24
Peak memory 182684 kb
Host smart-b5dff1de-9f82-443e-95ba-09ea2e60af3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111677093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.3111677093
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.513448244
Short name T567
Test name
Test status
Simulation time 30616208 ps
CPU time 0.68 seconds
Started Jul 27 05:09:15 PM PDT 24
Finished Jul 27 05:09:16 PM PDT 24
Peak memory 194132 kb
Host smart-083cb6e0-51c8-4ba8-bd01-75b8712e7fab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513448244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_ti
mer_same_csr_outstanding.513448244
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3657843302
Short name T495
Test name
Test status
Simulation time 154543045 ps
CPU time 3.17 seconds
Started Jul 27 05:09:16 PM PDT 24
Finished Jul 27 05:09:19 PM PDT 24
Peak memory 197692 kb
Host smart-4f31385a-eeaa-4ef4-8231-10f973575264
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657843302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.3657843302
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.2347272652
Short name T529
Test name
Test status
Simulation time 120567169 ps
CPU time 0.88 seconds
Started Jul 27 05:09:17 PM PDT 24
Finished Jul 27 05:09:18 PM PDT 24
Peak memory 196752 kb
Host smart-c4ed2a4c-ad84-45ce-9c65-73df6adbac52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347272652 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.2347272652
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.923243704
Short name T67
Test name
Test status
Simulation time 43280460 ps
CPU time 0.58 seconds
Started Jul 27 05:09:23 PM PDT 24
Finished Jul 27 05:09:24 PM PDT 24
Peak memory 182948 kb
Host smart-fccd843a-6cab-444e-8fa6-375cd69ea328
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923243704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.923243704
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.4047467641
Short name T471
Test name
Test status
Simulation time 15312200 ps
CPU time 0.55 seconds
Started Jul 27 05:09:16 PM PDT 24
Finished Jul 27 05:09:17 PM PDT 24
Peak memory 182824 kb
Host smart-59c05b70-5254-47b4-ac11-cf5671fabea3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047467641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.4047467641
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2481800112
Short name T507
Test name
Test status
Simulation time 91788817 ps
CPU time 0.64 seconds
Started Jul 27 05:09:16 PM PDT 24
Finished Jul 27 05:09:17 PM PDT 24
Peak memory 191684 kb
Host smart-ab06f3c4-c8d5-41f1-a55c-a9575b8df2e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481800112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.2481800112
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.128464028
Short name T513
Test name
Test status
Simulation time 178116516 ps
CPU time 2.82 seconds
Started Jul 27 05:09:18 PM PDT 24
Finished Jul 27 05:09:21 PM PDT 24
Peak memory 197644 kb
Host smart-f00d2630-fb15-4119-ba45-bf8993804646
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128464028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.128464028
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1170216642
Short name T91
Test name
Test status
Simulation time 220718303 ps
CPU time 1.33 seconds
Started Jul 27 05:09:16 PM PDT 24
Finished Jul 27 05:09:18 PM PDT 24
Peak memory 195604 kb
Host smart-87b4e107-8d49-4d26-819f-817bb56b29b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170216642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.1170216642
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.3580438879
Short name T65
Test name
Test status
Simulation time 24823542 ps
CPU time 0.72 seconds
Started Jul 27 05:08:57 PM PDT 24
Finished Jul 27 05:08:58 PM PDT 24
Peak memory 192704 kb
Host smart-75a5a7fd-5fe9-4005-bd3e-6bd8597bd2e8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580438879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.3580438879
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1075764670
Short name T74
Test name
Test status
Simulation time 570909450 ps
CPU time 3.66 seconds
Started Jul 27 05:08:58 PM PDT 24
Finished Jul 27 05:09:02 PM PDT 24
Peak memory 191212 kb
Host smart-2ea978ea-5588-4c8d-b314-fdf8397c5696
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075764670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.1075764670
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.4003578838
Short name T573
Test name
Test status
Simulation time 53177073 ps
CPU time 0.61 seconds
Started Jul 27 05:08:55 PM PDT 24
Finished Jul 27 05:08:56 PM PDT 24
Peak memory 182892 kb
Host smart-3ca28083-655d-43a9-93df-c6f2c031a32d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003578838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.4003578838
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.1050146888
Short name T510
Test name
Test status
Simulation time 551753323 ps
CPU time 0.94 seconds
Started Jul 27 05:08:53 PM PDT 24
Finished Jul 27 05:08:54 PM PDT 24
Peak memory 196972 kb
Host smart-7af9b2d7-fb2c-4c65-82c3-779d2fb8d805
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050146888 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.1050146888
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.3818694189
Short name T70
Test name
Test status
Simulation time 71624806 ps
CPU time 0.56 seconds
Started Jul 27 05:08:55 PM PDT 24
Finished Jul 27 05:08:56 PM PDT 24
Peak memory 182864 kb
Host smart-7cde8fbc-eb74-47b6-86b6-6c16914fd682
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818694189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.3818694189
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.4154829574
Short name T481
Test name
Test status
Simulation time 14860899 ps
CPU time 0.56 seconds
Started Jul 27 05:08:58 PM PDT 24
Finished Jul 27 05:08:59 PM PDT 24
Peak memory 182736 kb
Host smart-f806183a-f611-4def-8184-1d25d6212207
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154829574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.4154829574
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.3242900467
Short name T505
Test name
Test status
Simulation time 112542021 ps
CPU time 0.69 seconds
Started Jul 27 05:08:58 PM PDT 24
Finished Jul 27 05:08:59 PM PDT 24
Peak memory 191824 kb
Host smart-eb01fd17-f90b-4661-a540-4c4471526644
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242900467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.3242900467
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.198539593
Short name T530
Test name
Test status
Simulation time 37352943 ps
CPU time 1.68 seconds
Started Jul 27 05:08:56 PM PDT 24
Finished Jul 27 05:08:58 PM PDT 24
Peak memory 197676 kb
Host smart-f3430982-368a-44db-8bc1-0796d40dc927
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198539593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.198539593
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2161057354
Short name T568
Test name
Test status
Simulation time 531721811 ps
CPU time 1.05 seconds
Started Jul 27 05:08:56 PM PDT 24
Finished Jul 27 05:08:57 PM PDT 24
Peak memory 195020 kb
Host smart-e5a5df7b-0756-4733-b216-416bf9ba1995
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161057354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.2161057354
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.2809352900
Short name T532
Test name
Test status
Simulation time 37033841 ps
CPU time 0.51 seconds
Started Jul 27 05:09:17 PM PDT 24
Finished Jul 27 05:09:18 PM PDT 24
Peak memory 182724 kb
Host smart-a3208783-0b35-4547-a628-28dc32d883c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809352900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.2809352900
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1519441010
Short name T462
Test name
Test status
Simulation time 18488663 ps
CPU time 0.57 seconds
Started Jul 27 05:09:19 PM PDT 24
Finished Jul 27 05:09:20 PM PDT 24
Peak memory 182836 kb
Host smart-ba8bbfbc-f829-4b25-8496-b95124e6b996
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519441010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.1519441010
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.2818003906
Short name T494
Test name
Test status
Simulation time 17868085 ps
CPU time 0.55 seconds
Started Jul 27 05:09:18 PM PDT 24
Finished Jul 27 05:09:18 PM PDT 24
Peak memory 182724 kb
Host smart-0709adff-9cb9-4b52-bc9c-fd1453fb9b8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818003906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.2818003906
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.3320685669
Short name T456
Test name
Test status
Simulation time 14527058 ps
CPU time 0.55 seconds
Started Jul 27 05:09:19 PM PDT 24
Finished Jul 27 05:09:20 PM PDT 24
Peak memory 182748 kb
Host smart-f624d4dd-1984-4062-9830-13d3b773470a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320685669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.3320685669
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.3556338083
Short name T455
Test name
Test status
Simulation time 17721935 ps
CPU time 0.58 seconds
Started Jul 27 05:09:20 PM PDT 24
Finished Jul 27 05:09:21 PM PDT 24
Peak memory 182764 kb
Host smart-4b4fbae2-1935-4f7e-be55-624a730c0b32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556338083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.3556338083
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.1941565973
Short name T473
Test name
Test status
Simulation time 17574564 ps
CPU time 0.53 seconds
Started Jul 27 05:09:19 PM PDT 24
Finished Jul 27 05:09:19 PM PDT 24
Peak memory 182836 kb
Host smart-2fd121bc-4ab0-4c65-bbfa-1b2a6355cb34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941565973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.1941565973
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.200244764
Short name T485
Test name
Test status
Simulation time 14529875 ps
CPU time 0.57 seconds
Started Jul 27 05:09:22 PM PDT 24
Finished Jul 27 05:09:22 PM PDT 24
Peak memory 182784 kb
Host smart-6ea1a1d1-355d-4b68-b57e-03b7b9963f1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200244764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.200244764
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.2465376404
Short name T477
Test name
Test status
Simulation time 37787191 ps
CPU time 0.53 seconds
Started Jul 27 05:09:19 PM PDT 24
Finished Jul 27 05:09:20 PM PDT 24
Peak memory 182264 kb
Host smart-9f4b81e0-9302-4f14-ab31-fe16c4783795
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465376404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.2465376404
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1880886384
Short name T559
Test name
Test status
Simulation time 15886305 ps
CPU time 0.54 seconds
Started Jul 27 05:09:20 PM PDT 24
Finished Jul 27 05:09:20 PM PDT 24
Peak memory 182680 kb
Host smart-b9f1d396-3d59-41c7-8813-1dd36a77ca0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880886384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.1880886384
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.2080550658
Short name T554
Test name
Test status
Simulation time 14070194 ps
CPU time 0.55 seconds
Started Jul 27 05:09:21 PM PDT 24
Finished Jul 27 05:09:21 PM PDT 24
Peak memory 182728 kb
Host smart-1cb1d552-85c5-45fd-a3fa-13bc202ef2f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080550658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.2080550658
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3171809054
Short name T73
Test name
Test status
Simulation time 20178427 ps
CPU time 0.8 seconds
Started Jul 27 05:08:55 PM PDT 24
Finished Jul 27 05:08:56 PM PDT 24
Peak memory 182888 kb
Host smart-198d1eab-1c2f-4d02-ae19-6232986dacb4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171809054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.3171809054
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.1118726974
Short name T71
Test name
Test status
Simulation time 1505299661 ps
CPU time 3.63 seconds
Started Jul 27 05:08:59 PM PDT 24
Finished Jul 27 05:09:03 PM PDT 24
Peak memory 191236 kb
Host smart-92b9949c-9995-4ebb-8e06-d93d117d2815
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118726974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.1118726974
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.2826046565
Short name T69
Test name
Test status
Simulation time 15381932 ps
CPU time 0.55 seconds
Started Jul 27 05:08:54 PM PDT 24
Finished Jul 27 05:08:55 PM PDT 24
Peak memory 182924 kb
Host smart-65cfa11b-f908-4053-a6ce-5e5ac1d35c60
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826046565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.2826046565
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.4174753307
Short name T536
Test name
Test status
Simulation time 28542556 ps
CPU time 1.28 seconds
Started Jul 27 05:08:55 PM PDT 24
Finished Jul 27 05:08:57 PM PDT 24
Peak memory 197652 kb
Host smart-54f5944c-0c61-4e9d-9b9f-fb5cd9e280d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174753307 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.4174753307
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.4044108901
Short name T72
Test name
Test status
Simulation time 53712262 ps
CPU time 0.55 seconds
Started Jul 27 05:09:01 PM PDT 24
Finished Jul 27 05:09:01 PM PDT 24
Peak memory 182948 kb
Host smart-139d8382-5764-4cd4-a308-c8ab7466c9d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044108901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.4044108901
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.4050868163
Short name T558
Test name
Test status
Simulation time 24243111 ps
CPU time 0.56 seconds
Started Jul 27 05:08:57 PM PDT 24
Finished Jul 27 05:08:58 PM PDT 24
Peak memory 182784 kb
Host smart-c7771436-4ecb-489c-84df-6e0bace2602d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050868163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.4050868163
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.3742479771
Short name T81
Test name
Test status
Simulation time 19507794 ps
CPU time 0.68 seconds
Started Jul 27 05:08:56 PM PDT 24
Finished Jul 27 05:08:57 PM PDT 24
Peak memory 193408 kb
Host smart-d7e51855-7bc0-4b3a-97ef-4c3cabb058a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742479771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.3742479771
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.1398955954
Short name T469
Test name
Test status
Simulation time 992148723 ps
CPU time 2.24 seconds
Started Jul 27 05:08:54 PM PDT 24
Finished Jul 27 05:08:57 PM PDT 24
Peak memory 197648 kb
Host smart-df9352cc-ab71-48ff-81cf-0fc863af9c7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398955954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.1398955954
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.3352458965
Short name T32
Test name
Test status
Simulation time 124276136 ps
CPU time 1.34 seconds
Started Jul 27 05:08:54 PM PDT 24
Finished Jul 27 05:08:55 PM PDT 24
Peak memory 195640 kb
Host smart-f0ff8b99-3eb4-480e-b4ce-1989d346e544
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352458965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.3352458965
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.359563862
Short name T499
Test name
Test status
Simulation time 34964010 ps
CPU time 0.55 seconds
Started Jul 27 05:09:23 PM PDT 24
Finished Jul 27 05:09:24 PM PDT 24
Peak memory 182828 kb
Host smart-b834428e-6a7e-4406-bccf-ac87914a5570
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359563862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.359563862
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.1273875758
Short name T454
Test name
Test status
Simulation time 83565933 ps
CPU time 0.58 seconds
Started Jul 27 05:09:17 PM PDT 24
Finished Jul 27 05:09:18 PM PDT 24
Peak memory 182832 kb
Host smart-5b54c943-b11c-4993-a723-fa6204b9e4cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273875758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.1273875758
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.4193475204
Short name T556
Test name
Test status
Simulation time 19083169 ps
CPU time 0.53 seconds
Started Jul 27 05:09:19 PM PDT 24
Finished Jul 27 05:09:20 PM PDT 24
Peak memory 182788 kb
Host smart-67f777f5-83b6-4246-b14d-199e68e94c1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193475204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.4193475204
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.939733622
Short name T500
Test name
Test status
Simulation time 41463550 ps
CPU time 0.54 seconds
Started Jul 27 05:09:18 PM PDT 24
Finished Jul 27 05:09:19 PM PDT 24
Peak memory 182776 kb
Host smart-a5e8fa4e-194b-4db9-8de4-5759b93e44ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939733622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.939733622
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.2663516732
Short name T463
Test name
Test status
Simulation time 73915538 ps
CPU time 0.52 seconds
Started Jul 27 05:09:20 PM PDT 24
Finished Jul 27 05:09:21 PM PDT 24
Peak memory 182360 kb
Host smart-398dd004-ec5e-46ac-865a-f50eb2ea82c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663516732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.2663516732
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2936347163
Short name T540
Test name
Test status
Simulation time 63443256 ps
CPU time 0.59 seconds
Started Jul 27 05:09:19 PM PDT 24
Finished Jul 27 05:09:20 PM PDT 24
Peak memory 182676 kb
Host smart-61eebceb-74d7-40c2-a757-e9619e0ce777
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936347163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.2936347163
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.1995046360
Short name T478
Test name
Test status
Simulation time 20551137 ps
CPU time 0.58 seconds
Started Jul 27 05:09:21 PM PDT 24
Finished Jul 27 05:09:22 PM PDT 24
Peak memory 182768 kb
Host smart-c8db7311-c7df-4b6e-804c-e8781088114c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995046360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.1995046360
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.3399706717
Short name T486
Test name
Test status
Simulation time 14229360 ps
CPU time 0.54 seconds
Started Jul 27 05:09:26 PM PDT 24
Finished Jul 27 05:09:26 PM PDT 24
Peak memory 183112 kb
Host smart-a23b3cdc-cdad-402d-afbe-c08d3fbff879
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399706717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.3399706717
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.3136271046
Short name T479
Test name
Test status
Simulation time 33620999 ps
CPU time 0.53 seconds
Started Jul 27 05:09:26 PM PDT 24
Finished Jul 27 05:09:27 PM PDT 24
Peak memory 182832 kb
Host smart-a6604a53-77d5-4804-a934-55b87703168e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136271046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.3136271046
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.2904611131
Short name T490
Test name
Test status
Simulation time 50875389 ps
CPU time 0.54 seconds
Started Jul 27 05:09:27 PM PDT 24
Finished Jul 27 05:09:27 PM PDT 24
Peak memory 182212 kb
Host smart-09009734-40f9-462f-80cd-093645f055d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904611131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.2904611131
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.720092601
Short name T75
Test name
Test status
Simulation time 18718330 ps
CPU time 0.68 seconds
Started Jul 27 05:08:55 PM PDT 24
Finished Jul 27 05:08:56 PM PDT 24
Peak memory 182972 kb
Host smart-20dd4b92-6187-44d4-a155-825a84c45a32
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720092601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alias
ing.720092601
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.360115479
Short name T491
Test name
Test status
Simulation time 578194569 ps
CPU time 3.36 seconds
Started Jul 27 05:08:55 PM PDT 24
Finished Jul 27 05:08:59 PM PDT 24
Peak memory 192636 kb
Host smart-fb2d0498-3a35-4f94-bef0-19ebca6c3fe0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360115479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_b
ash.360115479
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.1174231851
Short name T62
Test name
Test status
Simulation time 28723443 ps
CPU time 0.61 seconds
Started Jul 27 05:08:55 PM PDT 24
Finished Jul 27 05:08:56 PM PDT 24
Peak memory 192148 kb
Host smart-8b4b9b1e-0839-4b51-9868-797845cf9314
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174231851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.1174231851
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.2895486515
Short name T489
Test name
Test status
Simulation time 28801376 ps
CPU time 1.29 seconds
Started Jul 27 05:08:56 PM PDT 24
Finished Jul 27 05:08:57 PM PDT 24
Peak memory 197588 kb
Host smart-c40a24a7-35a5-406b-8015-319f7b176597
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895486515 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.2895486515
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.4200204501
Short name T569
Test name
Test status
Simulation time 66087419 ps
CPU time 0.57 seconds
Started Jul 27 05:08:53 PM PDT 24
Finished Jul 27 05:08:54 PM PDT 24
Peak memory 182952 kb
Host smart-f9cb884e-e8d6-4f5d-8e82-9ff0450590b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200204501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.4200204501
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.173871582
Short name T474
Test name
Test status
Simulation time 17749630 ps
CPU time 0.51 seconds
Started Jul 27 05:08:53 PM PDT 24
Finished Jul 27 05:08:54 PM PDT 24
Peak memory 182792 kb
Host smart-2136b435-55c8-4891-95e3-3c5916a78c18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173871582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.173871582
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.2697844258
Short name T84
Test name
Test status
Simulation time 20814577 ps
CPU time 0.8 seconds
Started Jul 27 05:08:57 PM PDT 24
Finished Jul 27 05:08:58 PM PDT 24
Peak memory 193692 kb
Host smart-af10780d-f7b7-430b-812c-7bbb378cee06
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697844258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.2697844258
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.3913613286
Short name T45
Test name
Test status
Simulation time 146224184 ps
CPU time 2.47 seconds
Started Jul 27 05:08:56 PM PDT 24
Finished Jul 27 05:08:59 PM PDT 24
Peak memory 197660 kb
Host smart-12c3127d-157a-4425-9035-325402e0ae8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913613286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.3913613286
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.4193147513
Short name T487
Test name
Test status
Simulation time 371313369 ps
CPU time 1.31 seconds
Started Jul 27 05:08:59 PM PDT 24
Finished Jul 27 05:09:01 PM PDT 24
Peak memory 195584 kb
Host smart-674df93b-ffd7-4571-bb59-f48481352481
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193147513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.4193147513
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.1821681377
Short name T488
Test name
Test status
Simulation time 18847457 ps
CPU time 0.59 seconds
Started Jul 27 05:09:26 PM PDT 24
Finished Jul 27 05:09:27 PM PDT 24
Peak memory 182864 kb
Host smart-1f022414-21cb-4aee-ae6b-a8d15ebb5d38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821681377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.1821681377
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.2961355680
Short name T575
Test name
Test status
Simulation time 31729898 ps
CPU time 0.59 seconds
Started Jul 27 05:09:27 PM PDT 24
Finished Jul 27 05:09:27 PM PDT 24
Peak memory 182840 kb
Host smart-8f2857b3-3bae-420d-8659-94ccb9ea91a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961355680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.2961355680
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.2040426062
Short name T564
Test name
Test status
Simulation time 100128241 ps
CPU time 0.56 seconds
Started Jul 27 05:09:26 PM PDT 24
Finished Jul 27 05:09:27 PM PDT 24
Peak memory 182788 kb
Host smart-ea71a6a0-279e-48bf-9da1-f7ec545ef1a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040426062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.2040426062
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.2974036354
Short name T470
Test name
Test status
Simulation time 15313235 ps
CPU time 0.52 seconds
Started Jul 27 05:09:25 PM PDT 24
Finished Jul 27 05:09:26 PM PDT 24
Peak memory 182860 kb
Host smart-2ee37edc-4d30-415c-8faa-7faa1060769d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974036354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.2974036354
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.402817198
Short name T534
Test name
Test status
Simulation time 12710583 ps
CPU time 0.52 seconds
Started Jul 27 05:09:28 PM PDT 24
Finished Jul 27 05:09:29 PM PDT 24
Peak memory 182264 kb
Host smart-49634e8f-69f7-4c1f-be5b-2c69634271ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402817198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.402817198
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.3402155496
Short name T460
Test name
Test status
Simulation time 82629500 ps
CPU time 0.53 seconds
Started Jul 27 05:09:26 PM PDT 24
Finished Jul 27 05:09:26 PM PDT 24
Peak memory 182284 kb
Host smart-0f9d577a-5b1f-4a87-9ea3-f57462801014
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402155496 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.3402155496
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.2999869288
Short name T543
Test name
Test status
Simulation time 80796558 ps
CPU time 0.52 seconds
Started Jul 27 05:09:28 PM PDT 24
Finished Jul 27 05:09:29 PM PDT 24
Peak memory 182272 kb
Host smart-aa24710b-6141-405c-9617-e7685bcfa472
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999869288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.2999869288
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.1793485931
Short name T497
Test name
Test status
Simulation time 67249082 ps
CPU time 0.54 seconds
Started Jul 27 05:09:24 PM PDT 24
Finished Jul 27 05:09:25 PM PDT 24
Peak memory 182784 kb
Host smart-b7a3be2b-3b95-41ef-a606-1f6a4ecb3283
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793485931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.1793485931
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.3121733972
Short name T458
Test name
Test status
Simulation time 13471534 ps
CPU time 0.55 seconds
Started Jul 27 05:09:28 PM PDT 24
Finished Jul 27 05:09:29 PM PDT 24
Peak memory 182432 kb
Host smart-1f264ffe-92e3-433b-a3d6-5966fd4bb1ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121733972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.3121733972
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.3379117425
Short name T577
Test name
Test status
Simulation time 32419499 ps
CPU time 0.54 seconds
Started Jul 27 05:09:27 PM PDT 24
Finished Jul 27 05:09:28 PM PDT 24
Peak memory 182296 kb
Host smart-b3d1d3fc-4b5d-47ff-ab21-a14b73952b84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379117425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.3379117425
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2903753069
Short name T503
Test name
Test status
Simulation time 35081434 ps
CPU time 1.28 seconds
Started Jul 27 05:09:08 PM PDT 24
Finished Jul 27 05:09:09 PM PDT 24
Peak memory 197596 kb
Host smart-94531a70-bc76-4ded-baf7-e8adf199f7d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903753069 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.2903753069
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.2690148089
Short name T484
Test name
Test status
Simulation time 13959967 ps
CPU time 0.55 seconds
Started Jul 27 05:09:09 PM PDT 24
Finished Jul 27 05:09:10 PM PDT 24
Peak memory 182632 kb
Host smart-9aa6cb4f-d68b-43be-a7cd-2e6baf53b805
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690148089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.2690148089
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.583153129
Short name T498
Test name
Test status
Simulation time 26370146 ps
CPU time 0.53 seconds
Started Jul 27 05:09:09 PM PDT 24
Finished Jul 27 05:09:10 PM PDT 24
Peak memory 182708 kb
Host smart-64acea10-d86b-499e-88d5-67ae1a35ab50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583153129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.583153129
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1223438014
Short name T523
Test name
Test status
Simulation time 30699442 ps
CPU time 0.6 seconds
Started Jul 27 05:09:06 PM PDT 24
Finished Jul 27 05:09:07 PM PDT 24
Peak memory 192132 kb
Host smart-213fa172-01bc-468f-a553-1f551ae2071c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223438014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.1223438014
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.1406513953
Short name T579
Test name
Test status
Simulation time 302054411 ps
CPU time 2.11 seconds
Started Jul 27 05:08:55 PM PDT 24
Finished Jul 27 05:08:57 PM PDT 24
Peak memory 197584 kb
Host smart-778657be-fc59-4f53-bc2e-9c966fa6da2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406513953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.1406513953
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.778965622
Short name T531
Test name
Test status
Simulation time 42357933 ps
CPU time 0.83 seconds
Started Jul 27 05:08:56 PM PDT 24
Finished Jul 27 05:08:57 PM PDT 24
Peak memory 194092 kb
Host smart-8cc714d9-dbac-44ea-8bc8-00397ebfa4bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778965622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_int
g_err.778965622
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3432781523
Short name T521
Test name
Test status
Simulation time 62066332 ps
CPU time 1.42 seconds
Started Jul 27 05:09:08 PM PDT 24
Finished Jul 27 05:09:09 PM PDT 24
Peak memory 197528 kb
Host smart-2cea1c03-6948-45cb-b99b-e8e41fc9ff42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432781523 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.3432781523
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.3189072490
Short name T68
Test name
Test status
Simulation time 18767262 ps
CPU time 0.63 seconds
Started Jul 27 05:09:07 PM PDT 24
Finished Jul 27 05:09:08 PM PDT 24
Peak memory 182868 kb
Host smart-1ce3da98-17a5-4856-bc83-6d3ba111d1c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189072490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.3189072490
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.2213372848
Short name T493
Test name
Test status
Simulation time 22119060 ps
CPU time 0.55 seconds
Started Jul 27 05:09:10 PM PDT 24
Finished Jul 27 05:09:11 PM PDT 24
Peak memory 182476 kb
Host smart-4a83c5ca-15a1-4347-b7fd-48c36ba9ab76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213372848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.2213372848
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.411493711
Short name T535
Test name
Test status
Simulation time 43195198 ps
CPU time 0.69 seconds
Started Jul 27 05:09:09 PM PDT 24
Finished Jul 27 05:09:10 PM PDT 24
Peak memory 192288 kb
Host smart-665d0de7-5235-48e2-bfa7-0bdc9c2bbf93
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411493711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_tim
er_same_csr_outstanding.411493711
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.615653377
Short name T44
Test name
Test status
Simulation time 387809538 ps
CPU time 1.75 seconds
Started Jul 27 05:09:09 PM PDT 24
Finished Jul 27 05:09:11 PM PDT 24
Peak memory 197652 kb
Host smart-7505119d-0f87-4282-beb8-14b16fa77b47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615653377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.615653377
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.2324786999
Short name T537
Test name
Test status
Simulation time 161853488 ps
CPU time 0.81 seconds
Started Jul 27 05:09:10 PM PDT 24
Finished Jul 27 05:09:10 PM PDT 24
Peak memory 183392 kb
Host smart-3d1a18be-425e-43f3-9c6e-6697ed849699
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324786999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.2324786999
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.1668051907
Short name T46
Test name
Test status
Simulation time 87902347 ps
CPU time 0.76 seconds
Started Jul 27 05:09:08 PM PDT 24
Finished Jul 27 05:09:09 PM PDT 24
Peak memory 195208 kb
Host smart-ad9ee636-b646-46cd-8ca9-a72c332be0ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668051907 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.1668051907
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.619143519
Short name T528
Test name
Test status
Simulation time 15031128 ps
CPU time 0.57 seconds
Started Jul 27 05:09:08 PM PDT 24
Finished Jul 27 05:09:08 PM PDT 24
Peak memory 182956 kb
Host smart-bbd66da7-5041-4b9c-a4c8-fa688f2a3f96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619143519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.619143519
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.70585736
Short name T475
Test name
Test status
Simulation time 15300517 ps
CPU time 0.57 seconds
Started Jul 27 05:09:07 PM PDT 24
Finished Jul 27 05:09:08 PM PDT 24
Peak memory 182840 kb
Host smart-12df5e4c-cb87-4113-beef-ad73a57651af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70585736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.70585736
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.1229726898
Short name T33
Test name
Test status
Simulation time 109599700 ps
CPU time 0.75 seconds
Started Jul 27 05:09:07 PM PDT 24
Finished Jul 27 05:09:08 PM PDT 24
Peak memory 193880 kb
Host smart-be296a7a-6632-4a7e-8f4f-2474a4814b30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229726898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.1229726898
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.4028341187
Short name T466
Test name
Test status
Simulation time 1092103451 ps
CPU time 1.21 seconds
Started Jul 27 05:09:06 PM PDT 24
Finished Jul 27 05:09:08 PM PDT 24
Peak memory 197480 kb
Host smart-17bc502c-f871-4928-bd94-fa7580ce4982
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028341187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.4028341187
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.1111187702
Short name T89
Test name
Test status
Simulation time 126057616 ps
CPU time 1.34 seconds
Started Jul 27 05:09:07 PM PDT 24
Finished Jul 27 05:09:09 PM PDT 24
Peak memory 195608 kb
Host smart-a881f4bb-f92c-44c6-88c5-511f3232f312
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111187702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.1111187702
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.2528819115
Short name T545
Test name
Test status
Simulation time 124113432 ps
CPU time 0.8 seconds
Started Jul 27 05:09:09 PM PDT 24
Finished Jul 27 05:09:10 PM PDT 24
Peak memory 196344 kb
Host smart-83309b89-f5a4-415c-b251-1b40f2866c4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528819115 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.2528819115
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.894013438
Short name T547
Test name
Test status
Simulation time 115922246 ps
CPU time 0.56 seconds
Started Jul 27 05:09:08 PM PDT 24
Finished Jul 27 05:09:09 PM PDT 24
Peak memory 182888 kb
Host smart-4aa4dc36-6da1-49c1-85c6-c70c72aa6558
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894013438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.894013438
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.3888064193
Short name T459
Test name
Test status
Simulation time 20025222 ps
CPU time 0.54 seconds
Started Jul 27 05:09:07 PM PDT 24
Finished Jul 27 05:09:08 PM PDT 24
Peak memory 182808 kb
Host smart-3da2c9fd-222e-4299-867d-a3b8def401f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888064193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.3888064193
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.2154120450
Short name T522
Test name
Test status
Simulation time 20267612 ps
CPU time 0.6 seconds
Started Jul 27 05:09:06 PM PDT 24
Finished Jul 27 05:09:07 PM PDT 24
Peak memory 191480 kb
Host smart-274ca256-d342-4c3d-98ca-235fb51b4958
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154120450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.2154120450
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3463876321
Short name T539
Test name
Test status
Simulation time 87482727 ps
CPU time 1.18 seconds
Started Jul 27 05:09:07 PM PDT 24
Finished Jul 27 05:09:09 PM PDT 24
Peak memory 197668 kb
Host smart-f96112f6-53d4-4029-ae72-7a73157dafd7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463876321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.3463876321
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.4184022897
Short name T514
Test name
Test status
Simulation time 43022322 ps
CPU time 0.9 seconds
Started Jul 27 05:09:11 PM PDT 24
Finished Jul 27 05:09:12 PM PDT 24
Peak memory 194192 kb
Host smart-24f40be8-28d3-4800-80fb-d294b1fd3b5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184022897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.4184022897
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.1514885345
Short name T546
Test name
Test status
Simulation time 122877190 ps
CPU time 0.87 seconds
Started Jul 27 05:09:07 PM PDT 24
Finished Jul 27 05:09:08 PM PDT 24
Peak memory 196976 kb
Host smart-94f94332-dd61-4b4d-913d-160a9098cd18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514885345 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.1514885345
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.3671000158
Short name T483
Test name
Test status
Simulation time 41831370 ps
CPU time 0.56 seconds
Started Jul 27 05:09:08 PM PDT 24
Finished Jul 27 05:09:08 PM PDT 24
Peak memory 182712 kb
Host smart-b9d1217d-74cd-42e6-a784-e28a29f76788
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671000158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.3671000158
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.172797970
Short name T465
Test name
Test status
Simulation time 17355119 ps
CPU time 0.57 seconds
Started Jul 27 05:09:05 PM PDT 24
Finished Jul 27 05:09:05 PM PDT 24
Peak memory 182864 kb
Host smart-5836a580-95bf-4243-89e4-2e46d3df41d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172797970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.172797970
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.720724041
Short name T525
Test name
Test status
Simulation time 78273077 ps
CPU time 0.68 seconds
Started Jul 27 05:09:13 PM PDT 24
Finished Jul 27 05:09:14 PM PDT 24
Peak memory 191904 kb
Host smart-e613347d-bf4a-4379-b036-66393833adda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720724041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_tim
er_same_csr_outstanding.720724041
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.2823909207
Short name T517
Test name
Test status
Simulation time 146693010 ps
CPU time 2.32 seconds
Started Jul 27 05:09:08 PM PDT 24
Finished Jul 27 05:09:10 PM PDT 24
Peak memory 197568 kb
Host smart-af24989b-d9bb-4310-80d3-0b788cdbe818
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823909207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.2823909207
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.579430118
Short name T544
Test name
Test status
Simulation time 299300304 ps
CPU time 1.04 seconds
Started Jul 27 05:09:08 PM PDT 24
Finished Jul 27 05:09:09 PM PDT 24
Peak memory 183424 kb
Host smart-32103ff9-c65a-40ab-aa69-f6739378c29e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579430118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_int
g_err.579430118
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.3523352908
Short name T434
Test name
Test status
Simulation time 37901010011 ps
CPU time 56.8 seconds
Started Jul 27 05:09:31 PM PDT 24
Finished Jul 27 05:10:28 PM PDT 24
Peak memory 183452 kb
Host smart-0f9beb20-fefb-4021-ad4e-513b4afc038d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523352908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.3523352908
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.2512690192
Short name T407
Test name
Test status
Simulation time 155844497 ps
CPU time 0.72 seconds
Started Jul 27 05:09:25 PM PDT 24
Finished Jul 27 05:09:26 PM PDT 24
Peak memory 183284 kb
Host smart-19c58aac-6204-4e0a-9d84-fc1be8d75143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512690192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.2512690192
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.1759977238
Short name T365
Test name
Test status
Simulation time 643876797725 ps
CPU time 254.28 seconds
Started Jul 27 05:09:34 PM PDT 24
Finished Jul 27 05:13:48 PM PDT 24
Peak memory 183544 kb
Host smart-66c1fd99-fed0-4db4-8442-0afcd4812d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759977238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.1759977238
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.1201057749
Short name T245
Test name
Test status
Simulation time 148353760310 ps
CPU time 73.84 seconds
Started Jul 27 05:09:31 PM PDT 24
Finished Jul 27 05:10:45 PM PDT 24
Peak memory 191664 kb
Host smart-66f9e890-8047-43ce-a7ae-7d79f4a4d3e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201057749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.1201057749
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.4109513445
Short name T133
Test name
Test status
Simulation time 75529245914 ps
CPU time 153.77 seconds
Started Jul 27 05:09:27 PM PDT 24
Finished Jul 27 05:12:01 PM PDT 24
Peak memory 195092 kb
Host smart-840c7566-ef6c-4c71-8d93-00db1a819ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109513445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.4109513445
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.1574617178
Short name T17
Test name
Test status
Simulation time 35478143 ps
CPU time 0.72 seconds
Started Jul 27 05:09:25 PM PDT 24
Finished Jul 27 05:09:25 PM PDT 24
Peak memory 213736 kb
Host smart-1c31ccd5-50a5-4b7c-b020-00eddf5900d2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574617178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.1574617178
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.4118932025
Short name T11
Test name
Test status
Simulation time 2442914205948 ps
CPU time 1134.36 seconds
Started Jul 27 05:09:28 PM PDT 24
Finished Jul 27 05:28:23 PM PDT 24
Peak memory 191720 kb
Host smart-6458b560-7fd4-47dd-9221-a04a8a7fbfd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118932025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
4118932025
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.2021569354
Short name T218
Test name
Test status
Simulation time 49831491960 ps
CPU time 82.64 seconds
Started Jul 27 05:09:35 PM PDT 24
Finished Jul 27 05:10:57 PM PDT 24
Peak memory 183532 kb
Host smart-2b49f63f-a73c-4a62-ab7d-5b6486e4c0de
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021569354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.2021569354
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.2856435432
Short name T427
Test name
Test status
Simulation time 12787824810 ps
CPU time 19.04 seconds
Started Jul 27 05:09:39 PM PDT 24
Finished Jul 27 05:09:58 PM PDT 24
Peak memory 183568 kb
Host smart-25dbc332-2ecb-4ba7-8cd1-4eb004de1e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856435432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.2856435432
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.2079913237
Short name T307
Test name
Test status
Simulation time 547130658112 ps
CPU time 658.29 seconds
Started Jul 27 05:09:38 PM PDT 24
Finished Jul 27 05:20:36 PM PDT 24
Peak memory 191728 kb
Host smart-72a3ee97-8f6f-418d-94d9-c3e89a5bbca6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079913237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.2079913237
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.1554848307
Short name T171
Test name
Test status
Simulation time 78064182329 ps
CPU time 254.41 seconds
Started Jul 27 05:09:40 PM PDT 24
Finished Jul 27 05:13:55 PM PDT 24
Peak memory 191756 kb
Host smart-4c47804f-7c38-4418-a4a1-3e788e8489ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554848307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.1554848307
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/101.rv_timer_random.2144255834
Short name T276
Test name
Test status
Simulation time 144090475495 ps
CPU time 72.3 seconds
Started Jul 27 05:10:48 PM PDT 24
Finished Jul 27 05:12:00 PM PDT 24
Peak memory 183428 kb
Host smart-ff22d31f-6df6-4148-b1e7-e0b0afe58a70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144255834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.2144255834
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.1033303142
Short name T339
Test name
Test status
Simulation time 52171959732 ps
CPU time 21.89 seconds
Started Jul 27 05:10:43 PM PDT 24
Finished Jul 27 05:11:05 PM PDT 24
Peak memory 183512 kb
Host smart-e11a75ef-c5a1-4724-a1f9-5b71a453cfbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033303142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.1033303142
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.81912524
Short name T241
Test name
Test status
Simulation time 13185239668 ps
CPU time 10.36 seconds
Started Jul 27 05:10:44 PM PDT 24
Finished Jul 27 05:10:54 PM PDT 24
Peak memory 183288 kb
Host smart-e8e20933-a8b5-494d-9b63-6812b67a97c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81912524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.81912524
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.1694309533
Short name T118
Test name
Test status
Simulation time 143579620659 ps
CPU time 70.32 seconds
Started Jul 27 05:10:42 PM PDT 24
Finished Jul 27 05:11:53 PM PDT 24
Peak memory 191744 kb
Host smart-2810355f-ba9b-40b4-bf10-bbf79cf14e0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694309533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.1694309533
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.1660863753
Short name T228
Test name
Test status
Simulation time 178768719577 ps
CPU time 92.61 seconds
Started Jul 27 05:10:43 PM PDT 24
Finished Jul 27 05:12:16 PM PDT 24
Peak memory 191744 kb
Host smart-26b267f3-8447-449d-ab34-e7eaca44dc2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660863753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.1660863753
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.2073351646
Short name T106
Test name
Test status
Simulation time 61262899182 ps
CPU time 49.85 seconds
Started Jul 27 05:10:43 PM PDT 24
Finished Jul 27 05:11:33 PM PDT 24
Peak memory 191636 kb
Host smart-2a848fb0-a7b4-4566-be2b-c686f2e27be9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073351646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.2073351646
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.2036422289
Short name T325
Test name
Test status
Simulation time 60213576249 ps
CPU time 85.94 seconds
Started Jul 27 05:09:38 PM PDT 24
Finished Jul 27 05:11:04 PM PDT 24
Peak memory 183424 kb
Host smart-3bb536dc-a846-48bc-9dd4-e44fd7bcc631
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036422289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.2036422289
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.2351989318
Short name T397
Test name
Test status
Simulation time 165882154742 ps
CPU time 55.38 seconds
Started Jul 27 05:09:38 PM PDT 24
Finished Jul 27 05:10:33 PM PDT 24
Peak memory 183556 kb
Host smart-57b5e21f-f0e3-4547-bb89-2e0c12e59141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351989318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.2351989318
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.2224190157
Short name T306
Test name
Test status
Simulation time 192679595593 ps
CPU time 441.52 seconds
Started Jul 27 05:09:39 PM PDT 24
Finished Jul 27 05:17:00 PM PDT 24
Peak memory 191724 kb
Host smart-24febe22-50c1-4abf-9c5f-98466551a8b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224190157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.2224190157
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.3497343953
Short name T324
Test name
Test status
Simulation time 194705477030 ps
CPU time 1737.08 seconds
Started Jul 27 05:09:35 PM PDT 24
Finished Jul 27 05:38:33 PM PDT 24
Peak memory 183540 kb
Host smart-b4c9a54e-7e4e-4738-988a-7c6569679e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497343953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.3497343953
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.2385339558
Short name T380
Test name
Test status
Simulation time 1771067002918 ps
CPU time 607.14 seconds
Started Jul 27 05:09:41 PM PDT 24
Finished Jul 27 05:19:48 PM PDT 24
Peak memory 191744 kb
Host smart-a7a02ecf-bb80-4bb4-b950-ae3b9adb52b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385339558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.2385339558
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/110.rv_timer_random.1681718186
Short name T61
Test name
Test status
Simulation time 189059232129 ps
CPU time 1207.53 seconds
Started Jul 27 05:10:43 PM PDT 24
Finished Jul 27 05:30:51 PM PDT 24
Peak memory 191680 kb
Host smart-3c78b44a-4244-4f47-b4de-6623c35c8273
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681718186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.1681718186
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.1130318677
Short name T154
Test name
Test status
Simulation time 18466942188 ps
CPU time 28.64 seconds
Started Jul 27 05:10:43 PM PDT 24
Finished Jul 27 05:11:12 PM PDT 24
Peak memory 183580 kb
Host smart-29b47e31-a263-486b-af2a-02be0981c8a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130318677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.1130318677
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.4157620216
Short name T349
Test name
Test status
Simulation time 200925937300 ps
CPU time 153.43 seconds
Started Jul 27 05:10:55 PM PDT 24
Finished Jul 27 05:13:29 PM PDT 24
Peak memory 183772 kb
Host smart-6cf4536e-edb3-4a7d-82a5-9712614f4348
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157620216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.4157620216
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.2697963365
Short name T250
Test name
Test status
Simulation time 311255594731 ps
CPU time 111.27 seconds
Started Jul 27 05:10:59 PM PDT 24
Finished Jul 27 05:12:50 PM PDT 24
Peak memory 183548 kb
Host smart-b95bd303-adcf-42de-ae8b-bf7341bbea31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697963365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.2697963365
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.1386165972
Short name T58
Test name
Test status
Simulation time 190201293937 ps
CPU time 189.53 seconds
Started Jul 27 05:11:00 PM PDT 24
Finished Jul 27 05:14:10 PM PDT 24
Peak memory 191748 kb
Host smart-3b673f57-0e81-44d7-8e8c-68ae0f3a8e8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386165972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.1386165972
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.1832825020
Short name T340
Test name
Test status
Simulation time 36428353597 ps
CPU time 66.54 seconds
Started Jul 27 05:10:54 PM PDT 24
Finished Jul 27 05:12:01 PM PDT 24
Peak memory 191656 kb
Host smart-2539b3e4-85ae-4896-83d9-22dd19ba9cf1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832825020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.1832825020
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.1788000096
Short name T336
Test name
Test status
Simulation time 83281711227 ps
CPU time 113.58 seconds
Started Jul 27 05:10:58 PM PDT 24
Finished Jul 27 05:12:52 PM PDT 24
Peak memory 191748 kb
Host smart-6fac8fa5-8250-447e-8112-0f55d10de5d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788000096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.1788000096
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.14455709
Short name T249
Test name
Test status
Simulation time 902109034449 ps
CPU time 504.5 seconds
Started Jul 27 05:09:36 PM PDT 24
Finished Jul 27 05:18:01 PM PDT 24
Peak memory 183492 kb
Host smart-b51a1595-0da0-4f4a-a767-5850f3f5f6ae
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14455709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.rv_timer_cfg_update_on_fly.14455709
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.2972654409
Short name T415
Test name
Test status
Simulation time 624757668934 ps
CPU time 295.92 seconds
Started Jul 27 05:09:39 PM PDT 24
Finished Jul 27 05:14:35 PM PDT 24
Peak memory 183564 kb
Host smart-91a4ccbf-5bec-4f12-8a74-c2718583145b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972654409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.2972654409
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.1424702098
Short name T12
Test name
Test status
Simulation time 102595452319 ps
CPU time 574.38 seconds
Started Jul 27 05:09:38 PM PDT 24
Finished Jul 27 05:19:12 PM PDT 24
Peak memory 191656 kb
Host smart-ecdefc06-5835-462c-b804-09de1220ba88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424702098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.1424702098
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.2333376235
Short name T223
Test name
Test status
Simulation time 11272925578 ps
CPU time 9.45 seconds
Started Jul 27 05:09:34 PM PDT 24
Finished Jul 27 05:09:44 PM PDT 24
Peak memory 183556 kb
Host smart-01f3952a-5688-4126-a5ab-ff685dcc6b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333376235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.2333376235
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/120.rv_timer_random.2841192335
Short name T247
Test name
Test status
Simulation time 259127421187 ps
CPU time 1646.98 seconds
Started Jul 27 05:11:00 PM PDT 24
Finished Jul 27 05:38:28 PM PDT 24
Peak memory 191748 kb
Host smart-8145a818-eed5-467b-b305-2eb8b1d0dcd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841192335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.2841192335
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.445720132
Short name T206
Test name
Test status
Simulation time 611322162971 ps
CPU time 152.22 seconds
Started Jul 27 05:10:53 PM PDT 24
Finished Jul 27 05:13:25 PM PDT 24
Peak memory 191664 kb
Host smart-41930e85-c480-433d-9312-6efb5bd4a214
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445720132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.445720132
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.1579677542
Short name T23
Test name
Test status
Simulation time 484278416248 ps
CPU time 342.31 seconds
Started Jul 27 05:10:55 PM PDT 24
Finished Jul 27 05:16:38 PM PDT 24
Peak memory 191628 kb
Host smart-f0ebd520-f740-4c82-9fe0-f53dad137d74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579677542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.1579677542
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.1351875039
Short name T248
Test name
Test status
Simulation time 214272104119 ps
CPU time 284.71 seconds
Started Jul 27 05:10:55 PM PDT 24
Finished Jul 27 05:15:41 PM PDT 24
Peak memory 191744 kb
Host smart-c8d1e32f-b322-4ea3-bc5e-bd4ad70e965d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351875039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.1351875039
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.3581608509
Short name T9
Test name
Test status
Simulation time 24566710564 ps
CPU time 661.43 seconds
Started Jul 27 05:11:11 PM PDT 24
Finished Jul 27 05:22:13 PM PDT 24
Peak memory 191720 kb
Host smart-9c314ea4-1a2c-4857-a6e2-9c5a9f6efef6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581608509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.3581608509
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.4156490939
Short name T147
Test name
Test status
Simulation time 403017240609 ps
CPU time 289.06 seconds
Started Jul 27 05:09:37 PM PDT 24
Finished Jul 27 05:14:26 PM PDT 24
Peak memory 183492 kb
Host smart-903b0224-0518-4e3e-881d-5de4ad871d05
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156490939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.4156490939
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.2583117466
Short name T444
Test name
Test status
Simulation time 125859307043 ps
CPU time 194.2 seconds
Started Jul 27 05:09:37 PM PDT 24
Finished Jul 27 05:12:51 PM PDT 24
Peak memory 183512 kb
Host smart-ab2474ad-9121-487c-bdd4-b4e1383ad7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583117466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.2583117466
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.466058117
Short name T135
Test name
Test status
Simulation time 202013749129 ps
CPU time 311.57 seconds
Started Jul 27 05:09:36 PM PDT 24
Finished Jul 27 05:14:48 PM PDT 24
Peak memory 191732 kb
Host smart-97087883-9dee-4de2-8f43-b46a8ba3c96a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466058117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.466058117
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.516904195
Short name T216
Test name
Test status
Simulation time 111565405007 ps
CPU time 108.23 seconds
Started Jul 27 05:09:38 PM PDT 24
Finished Jul 27 05:11:26 PM PDT 24
Peak memory 183452 kb
Host smart-58233f5d-bf45-4082-8cc2-62709c95c333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516904195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.516904195
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all_with_rand_reset.1417736546
Short name T40
Test name
Test status
Simulation time 8219105975 ps
CPU time 59.47 seconds
Started Jul 27 05:09:36 PM PDT 24
Finished Jul 27 05:10:36 PM PDT 24
Peak memory 198228 kb
Host smart-ee04d8af-fb2d-4ec1-8f95-c4f3bddc1bd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417736546 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all_with_rand_reset.1417736546
Directory /workspace/13.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/133.rv_timer_random.1066376067
Short name T295
Test name
Test status
Simulation time 642552977947 ps
CPU time 3187.17 seconds
Started Jul 27 05:11:08 PM PDT 24
Finished Jul 27 06:04:15 PM PDT 24
Peak memory 191628 kb
Host smart-e5a445e2-db3b-4735-908e-547f9ddeaa0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066376067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.1066376067
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.199924211
Short name T203
Test name
Test status
Simulation time 1372819209832 ps
CPU time 718.62 seconds
Started Jul 27 05:11:07 PM PDT 24
Finished Jul 27 05:23:06 PM PDT 24
Peak memory 191716 kb
Host smart-8fb215b7-f877-428f-be2a-33fb9b886cc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199924211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.199924211
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.3982695890
Short name T212
Test name
Test status
Simulation time 60728593543 ps
CPU time 943.07 seconds
Started Jul 27 05:11:06 PM PDT 24
Finished Jul 27 05:26:50 PM PDT 24
Peak memory 191972 kb
Host smart-1e013668-bf01-4821-b11a-96cadaf3a5f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982695890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.3982695890
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.3174329863
Short name T189
Test name
Test status
Simulation time 132425564295 ps
CPU time 105.38 seconds
Started Jul 27 05:11:11 PM PDT 24
Finished Jul 27 05:12:57 PM PDT 24
Peak memory 191728 kb
Host smart-c18750f4-450f-4818-b78e-1073982d2bf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174329863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.3174329863
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.382320616
Short name T435
Test name
Test status
Simulation time 243058483796 ps
CPU time 421.02 seconds
Started Jul 27 05:09:37 PM PDT 24
Finished Jul 27 05:16:38 PM PDT 24
Peak memory 183492 kb
Host smart-20171737-dfc7-4b0d-bce5-9d05224ef6a2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382320616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.rv_timer_cfg_update_on_fly.382320616
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.2010776434
Short name T387
Test name
Test status
Simulation time 118735369569 ps
CPU time 182.21 seconds
Started Jul 27 05:09:38 PM PDT 24
Finished Jul 27 05:12:41 PM PDT 24
Peak memory 183460 kb
Host smart-bfa772d4-e6a5-4d2a-b5c7-d72372b75efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010776434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.2010776434
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.1774528008
Short name T27
Test name
Test status
Simulation time 552455028870 ps
CPU time 112.21 seconds
Started Jul 27 05:09:37 PM PDT 24
Finished Jul 27 05:11:29 PM PDT 24
Peak memory 191724 kb
Host smart-c5e670b9-341c-4acf-891f-5c155334b5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774528008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.1774528008
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/141.rv_timer_random.2581395911
Short name T272
Test name
Test status
Simulation time 51514931572 ps
CPU time 43.38 seconds
Started Jul 27 05:11:09 PM PDT 24
Finished Jul 27 05:11:52 PM PDT 24
Peak memory 183456 kb
Host smart-6e419381-611a-4511-90be-08e2dcf21481
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581395911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.2581395911
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.3809116626
Short name T270
Test name
Test status
Simulation time 5209106465 ps
CPU time 5.2 seconds
Started Jul 27 05:11:20 PM PDT 24
Finished Jul 27 05:11:25 PM PDT 24
Peak memory 183536 kb
Host smart-a365eff6-5482-4b28-8250-a9b9bace553e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809116626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.3809116626
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.2853913243
Short name T98
Test name
Test status
Simulation time 65562124993 ps
CPU time 217.27 seconds
Started Jul 27 05:11:20 PM PDT 24
Finished Jul 27 05:14:58 PM PDT 24
Peak memory 191652 kb
Host smart-beac072c-9006-4ea8-99b3-3786865f59a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853913243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.2853913243
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.1003918748
Short name T453
Test name
Test status
Simulation time 107155139936 ps
CPU time 339.06 seconds
Started Jul 27 05:11:21 PM PDT 24
Finished Jul 27 05:17:00 PM PDT 24
Peak memory 191772 kb
Host smart-11cf91cd-4eaa-47d7-b197-2d15fa4d3865
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003918748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.1003918748
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.4014224489
Short name T279
Test name
Test status
Simulation time 46522192801 ps
CPU time 147.84 seconds
Started Jul 27 05:11:21 PM PDT 24
Finished Jul 27 05:13:49 PM PDT 24
Peak memory 183536 kb
Host smart-bb1ae3be-4d27-41e0-b5c8-133c75f21844
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014224489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.4014224489
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.2701506700
Short name T193
Test name
Test status
Simulation time 615354445220 ps
CPU time 305.68 seconds
Started Jul 27 05:11:21 PM PDT 24
Finished Jul 27 05:16:27 PM PDT 24
Peak memory 191680 kb
Host smart-337ce60b-098e-470d-9682-08a3a32d129f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701506700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.2701506700
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.1304794177
Short name T399
Test name
Test status
Simulation time 124665399458 ps
CPU time 208.76 seconds
Started Jul 27 05:09:38 PM PDT 24
Finished Jul 27 05:13:07 PM PDT 24
Peak memory 183428 kb
Host smart-280b858d-98fd-42b0-b1a3-5cae18f96f1c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304794177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.1304794177
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_random.779881410
Short name T354
Test name
Test status
Simulation time 171716452189 ps
CPU time 422.15 seconds
Started Jul 27 05:09:41 PM PDT 24
Finished Jul 27 05:16:43 PM PDT 24
Peak memory 191752 kb
Host smart-631d4d36-b93f-467f-bc05-47eedd8d8dea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779881410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.779881410
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.4279353962
Short name T201
Test name
Test status
Simulation time 118771651762 ps
CPU time 217.14 seconds
Started Jul 27 05:09:37 PM PDT 24
Finished Jul 27 05:13:14 PM PDT 24
Peak memory 183540 kb
Host smart-c4f309f6-b858-4d95-99be-0b19fb0f6f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279353962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.4279353962
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.2585739958
Short name T372
Test name
Test status
Simulation time 262468188423 ps
CPU time 185.33 seconds
Started Jul 27 05:09:41 PM PDT 24
Finished Jul 27 05:12:46 PM PDT 24
Peak memory 183444 kb
Host smart-e34b2d80-3774-4e3c-afd6-e96a20613a02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585739958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.2585739958
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/151.rv_timer_random.2989517787
Short name T59
Test name
Test status
Simulation time 204370104808 ps
CPU time 494.73 seconds
Started Jul 27 05:11:20 PM PDT 24
Finished Jul 27 05:19:35 PM PDT 24
Peak memory 191736 kb
Host smart-f5d0138b-c4f0-40d2-bcfe-9b473cdb809a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989517787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.2989517787
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.1087625591
Short name T172
Test name
Test status
Simulation time 78925623669 ps
CPU time 445.65 seconds
Started Jul 27 05:11:22 PM PDT 24
Finished Jul 27 05:18:48 PM PDT 24
Peak memory 191744 kb
Host smart-d6476e32-a637-4e0a-a710-5e6d8c568a95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087625591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.1087625591
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.1212439383
Short name T299
Test name
Test status
Simulation time 143504346489 ps
CPU time 78.32 seconds
Started Jul 27 05:11:21 PM PDT 24
Finished Jul 27 05:12:39 PM PDT 24
Peak memory 183444 kb
Host smart-8434e704-06cf-4a08-bea7-3c59403540b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212439383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.1212439383
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.3372155037
Short name T143
Test name
Test status
Simulation time 64063666532 ps
CPU time 38.21 seconds
Started Jul 27 05:11:20 PM PDT 24
Finished Jul 27 05:11:59 PM PDT 24
Peak memory 183532 kb
Host smart-4bf612e0-a947-46f1-8137-8ff35d3c67e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372155037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.3372155037
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.1740954570
Short name T300
Test name
Test status
Simulation time 203319002460 ps
CPU time 1531.86 seconds
Started Jul 27 05:11:37 PM PDT 24
Finished Jul 27 05:37:09 PM PDT 24
Peak memory 191736 kb
Host smart-1ad0028a-631b-4afe-8877-eadf6f323b12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740954570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.1740954570
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.494613477
Short name T120
Test name
Test status
Simulation time 1989492742069 ps
CPU time 964.24 seconds
Started Jul 27 05:09:40 PM PDT 24
Finished Jul 27 05:25:44 PM PDT 24
Peak memory 183452 kb
Host smart-f4957a9b-2b16-4554-afc8-245311b4b6ce
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494613477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.rv_timer_cfg_update_on_fly.494613477
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.718827389
Short name T395
Test name
Test status
Simulation time 785569259369 ps
CPU time 219.61 seconds
Started Jul 27 05:09:41 PM PDT 24
Finished Jul 27 05:13:20 PM PDT 24
Peak memory 183460 kb
Host smart-aef682ee-b415-4b7c-8c26-84d4832f9984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718827389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.718827389
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.14962197
Short name T187
Test name
Test status
Simulation time 46365741717 ps
CPU time 420.73 seconds
Started Jul 27 05:09:37 PM PDT 24
Finished Jul 27 05:16:38 PM PDT 24
Peak memory 191716 kb
Host smart-e07cb7d6-dc6d-4b70-9afb-55502a9f839a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14962197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.14962197
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.3220207473
Short name T363
Test name
Test status
Simulation time 952420393 ps
CPU time 1.3 seconds
Started Jul 27 05:09:37 PM PDT 24
Finished Jul 27 05:09:39 PM PDT 24
Peak memory 192748 kb
Host smart-5f78d9e5-60b0-47fc-bb7b-c89385ee3feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220207473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.3220207473
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.1764671741
Short name T403
Test name
Test status
Simulation time 356515699376 ps
CPU time 120.84 seconds
Started Jul 27 05:09:40 PM PDT 24
Finished Jul 27 05:11:41 PM PDT 24
Peak memory 191488 kb
Host smart-cc121eca-d71f-45ba-a7cb-44a2b405291f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764671741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.1764671741
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all_with_rand_reset.2134738460
Short name T37
Test name
Test status
Simulation time 14403530742 ps
CPU time 109.19 seconds
Started Jul 27 05:09:38 PM PDT 24
Finished Jul 27 05:11:28 PM PDT 24
Peak memory 198216 kb
Host smart-e15fa530-01d5-4b29-bc8f-fe1678c216f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134738460 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all_with_rand_reset.2134738460
Directory /workspace/16.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.920741762
Short name T8
Test name
Test status
Simulation time 106444108259 ps
CPU time 252.94 seconds
Started Jul 27 05:11:35 PM PDT 24
Finished Jul 27 05:15:48 PM PDT 24
Peak memory 183496 kb
Host smart-a5703902-32b1-4391-b4cb-25a26b0857d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920741762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.920741762
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.1771216232
Short name T167
Test name
Test status
Simulation time 313998552077 ps
CPU time 403.99 seconds
Started Jul 27 05:11:36 PM PDT 24
Finished Jul 27 05:18:20 PM PDT 24
Peak memory 191652 kb
Host smart-d429147d-884d-4c2f-b5ba-ab1b5f0e22c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771216232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.1771216232
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.1961411849
Short name T4
Test name
Test status
Simulation time 118990561022 ps
CPU time 128.11 seconds
Started Jul 27 05:11:36 PM PDT 24
Finished Jul 27 05:13:44 PM PDT 24
Peak memory 191740 kb
Host smart-dbb16379-4565-4f6f-b596-e60ad8bb9b48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961411849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.1961411849
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.2792959232
Short name T322
Test name
Test status
Simulation time 523985942631 ps
CPU time 265.2 seconds
Started Jul 27 05:11:36 PM PDT 24
Finished Jul 27 05:16:01 PM PDT 24
Peak memory 191744 kb
Host smart-32bfd595-3b16-4594-84cf-a37cba3baefa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792959232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.2792959232
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.648428429
Short name T166
Test name
Test status
Simulation time 99829877671 ps
CPU time 164.56 seconds
Started Jul 27 05:11:37 PM PDT 24
Finished Jul 27 05:14:21 PM PDT 24
Peak memory 191716 kb
Host smart-cafdece2-0664-48df-a36b-52c35e4aa51e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648428429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.648428429
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.1773814525
Short name T436
Test name
Test status
Simulation time 2550893758694 ps
CPU time 1007.92 seconds
Started Jul 27 05:11:35 PM PDT 24
Finished Jul 27 05:28:23 PM PDT 24
Peak memory 191656 kb
Host smart-9c2d4f98-d2b9-45f7-8d58-f721cc8a1d58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773814525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.1773814525
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.1318601279
Short name T267
Test name
Test status
Simulation time 18241841359 ps
CPU time 28.9 seconds
Started Jul 27 05:11:37 PM PDT 24
Finished Jul 27 05:12:06 PM PDT 24
Peak memory 183472 kb
Host smart-7fe2a63c-b227-4f23-96c7-8fc29fb113b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318601279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.1318601279
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.1973042184
Short name T57
Test name
Test status
Simulation time 21571200386 ps
CPU time 32.79 seconds
Started Jul 27 05:09:38 PM PDT 24
Finished Jul 27 05:10:11 PM PDT 24
Peak memory 183444 kb
Host smart-6c5b64d0-c1ee-44f6-ac7f-b7e4a5c1dfc1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973042184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.1973042184
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.3703435823
Short name T442
Test name
Test status
Simulation time 40865720177 ps
CPU time 53.2 seconds
Started Jul 27 05:09:38 PM PDT 24
Finished Jul 27 05:10:32 PM PDT 24
Peak memory 183456 kb
Host smart-c2876242-ee48-4c3d-a2bb-c0bbd4a2eead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703435823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.3703435823
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.1120247631
Short name T414
Test name
Test status
Simulation time 22246786506 ps
CPU time 157.44 seconds
Started Jul 27 05:09:40 PM PDT 24
Finished Jul 27 05:12:18 PM PDT 24
Peak memory 183348 kb
Host smart-4eebb681-cfdf-4b7e-9340-8bf21181f235
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120247631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.1120247631
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.880755558
Short name T317
Test name
Test status
Simulation time 47842276200 ps
CPU time 48.74 seconds
Started Jul 27 05:09:38 PM PDT 24
Finished Jul 27 05:10:27 PM PDT 24
Peak memory 183452 kb
Host smart-b3ec5568-cd6e-4007-a1fe-ca489b45066f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880755558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.880755558
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.3829289459
Short name T41
Test name
Test status
Simulation time 15195166652 ps
CPU time 138.29 seconds
Started Jul 27 05:09:37 PM PDT 24
Finished Jul 27 05:11:55 PM PDT 24
Peak memory 198268 kb
Host smart-490bb03f-bd65-4d03-a264-1cd6a942dee6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829289459 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all_with_rand_reset.3829289459
Directory /workspace/17.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/172.rv_timer_random.2265553869
Short name T153
Test name
Test status
Simulation time 171300162174 ps
CPU time 2905.62 seconds
Started Jul 27 05:11:35 PM PDT 24
Finished Jul 27 06:00:01 PM PDT 24
Peak memory 191772 kb
Host smart-d244d985-a42b-4cc9-92dc-4b0961f07aca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265553869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.2265553869
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.4086838711
Short name T257
Test name
Test status
Simulation time 28227348962 ps
CPU time 37.77 seconds
Started Jul 27 05:11:39 PM PDT 24
Finished Jul 27 05:12:16 PM PDT 24
Peak memory 183372 kb
Host smart-0a8c19c1-5a49-4502-b96a-804d3b73929d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086838711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.4086838711
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.1828256293
Short name T161
Test name
Test status
Simulation time 204684696799 ps
CPU time 310.11 seconds
Started Jul 27 05:11:37 PM PDT 24
Finished Jul 27 05:16:48 PM PDT 24
Peak memory 191640 kb
Host smart-52fffc52-243c-41eb-bf63-21c56bbf1642
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828256293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.1828256293
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.1623095416
Short name T179
Test name
Test status
Simulation time 38612963945 ps
CPU time 62.53 seconds
Started Jul 27 05:11:37 PM PDT 24
Finished Jul 27 05:12:40 PM PDT 24
Peak memory 183544 kb
Host smart-827dbd03-4d31-462e-aaaa-cc6ab1b0b98d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623095416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.1623095416
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.346002838
Short name T53
Test name
Test status
Simulation time 64366765194 ps
CPU time 41.73 seconds
Started Jul 27 05:11:35 PM PDT 24
Finished Jul 27 05:12:17 PM PDT 24
Peak memory 183360 kb
Host smart-4d5c8b37-795b-474a-b928-0c997e6cf446
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346002838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.346002838
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.4128179554
Short name T185
Test name
Test status
Simulation time 194754357602 ps
CPU time 166.01 seconds
Started Jul 27 05:09:48 PM PDT 24
Finished Jul 27 05:12:34 PM PDT 24
Peak memory 183460 kb
Host smart-e42ba2ce-e8b1-4ad7-8340-5e4aa531278e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128179554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.4128179554
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.110156294
Short name T375
Test name
Test status
Simulation time 74396843971 ps
CPU time 111.34 seconds
Started Jul 27 05:09:44 PM PDT 24
Finished Jul 27 05:11:36 PM PDT 24
Peak memory 183556 kb
Host smart-b2a8ae80-3cba-4059-963c-6cb0e2330951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110156294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.110156294
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.2103674460
Short name T274
Test name
Test status
Simulation time 389593101949 ps
CPU time 162.8 seconds
Started Jul 27 05:09:50 PM PDT 24
Finished Jul 27 05:12:33 PM PDT 24
Peak memory 191732 kb
Host smart-e83c1af7-cdf2-480e-97e5-7627cacc225b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103674460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.2103674460
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.2895139814
Short name T406
Test name
Test status
Simulation time 161822569610 ps
CPU time 312.61 seconds
Started Jul 27 05:09:49 PM PDT 24
Finished Jul 27 05:15:02 PM PDT 24
Peak memory 192936 kb
Host smart-db5014a6-17d9-4b9d-b150-d425b1ca72df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895139814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.2895139814
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.1385460684
Short name T42
Test name
Test status
Simulation time 3457995226143 ps
CPU time 501.3 seconds
Started Jul 27 05:09:47 PM PDT 24
Finished Jul 27 05:18:08 PM PDT 24
Peak memory 191628 kb
Host smart-fe74ed5b-22ac-4d48-9db0-d158e9609014
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385460684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.1385460684
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/181.rv_timer_random.226404851
Short name T350
Test name
Test status
Simulation time 12828745098 ps
CPU time 15.82 seconds
Started Jul 27 05:11:34 PM PDT 24
Finished Jul 27 05:11:50 PM PDT 24
Peak memory 191764 kb
Host smart-b94b7574-84cb-4323-8dc4-04aebb096d23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226404851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.226404851
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.1238105708
Short name T29
Test name
Test status
Simulation time 94640414486 ps
CPU time 1129.03 seconds
Started Jul 27 05:11:35 PM PDT 24
Finished Jul 27 05:30:24 PM PDT 24
Peak memory 191740 kb
Host smart-7d4e5ae0-e541-44eb-9116-f338a75806a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238105708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.1238105708
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.2727529866
Short name T108
Test name
Test status
Simulation time 95699730290 ps
CPU time 122.28 seconds
Started Jul 27 05:11:36 PM PDT 24
Finished Jul 27 05:13:39 PM PDT 24
Peak memory 191680 kb
Host smart-1c29d48e-be90-4fd0-af65-be1c6e8859c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727529866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.2727529866
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.1088878029
Short name T132
Test name
Test status
Simulation time 135924384793 ps
CPU time 415.43 seconds
Started Jul 27 05:11:39 PM PDT 24
Finished Jul 27 05:18:34 PM PDT 24
Peak memory 191732 kb
Host smart-d238d6e8-4952-4dcb-b28c-4ac45e956f8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088878029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.1088878029
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.2005935072
Short name T345
Test name
Test status
Simulation time 841051760762 ps
CPU time 181.78 seconds
Started Jul 27 05:11:42 PM PDT 24
Finished Jul 27 05:14:43 PM PDT 24
Peak memory 191728 kb
Host smart-f98dea33-03a5-46ff-982b-a527e6580a7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005935072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.2005935072
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.3557354071
Short name T239
Test name
Test status
Simulation time 26665678094 ps
CPU time 98.51 seconds
Started Jul 27 05:11:42 PM PDT 24
Finished Jul 27 05:13:21 PM PDT 24
Peak memory 191720 kb
Host smart-5c788f5a-4f10-4dcd-8064-5976b8458c2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557354071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.3557354071
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.1410341887
Short name T413
Test name
Test status
Simulation time 36381732456 ps
CPU time 23.03 seconds
Started Jul 27 05:09:47 PM PDT 24
Finished Jul 27 05:10:11 PM PDT 24
Peak memory 183448 kb
Host smart-3db6cf2b-e1bc-4cf7-bfaf-a123e5e73cbb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410341887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.1410341887
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.1123633703
Short name T393
Test name
Test status
Simulation time 84663132649 ps
CPU time 57.45 seconds
Started Jul 27 05:09:46 PM PDT 24
Finished Jul 27 05:10:44 PM PDT 24
Peak memory 183472 kb
Host smart-c665a63f-48bb-41b2-a2a5-1f6eb60dad3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123633703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.1123633703
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.3415528500
Short name T362
Test name
Test status
Simulation time 95168370 ps
CPU time 0.54 seconds
Started Jul 27 05:09:44 PM PDT 24
Finished Jul 27 05:09:44 PM PDT 24
Peak memory 183216 kb
Host smart-40d89b2b-3707-4387-a268-7180ea4638b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415528500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.3415528500
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all_with_rand_reset.3283023813
Short name T14
Test name
Test status
Simulation time 375238930144 ps
CPU time 1785.73 seconds
Started Jul 27 05:09:50 PM PDT 24
Finished Jul 27 05:39:36 PM PDT 24
Peak memory 222744 kb
Host smart-26222b23-3e3e-4258-81b4-e149370d2117
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283023813 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all_with_rand_reset.3283023813
Directory /workspace/19.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/192.rv_timer_random.568226239
Short name T117
Test name
Test status
Simulation time 54023559993 ps
CPU time 448.61 seconds
Started Jul 27 05:11:42 PM PDT 24
Finished Jul 27 05:19:11 PM PDT 24
Peak memory 191724 kb
Host smart-f8855129-6ee6-48e8-b6f5-0855b43bc151
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568226239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.568226239
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.3970883975
Short name T337
Test name
Test status
Simulation time 96283265656 ps
CPU time 92.35 seconds
Started Jul 27 05:11:43 PM PDT 24
Finished Jul 27 05:13:16 PM PDT 24
Peak memory 191636 kb
Host smart-13a16b49-e55b-43ec-81b9-a453b02dd236
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970883975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.3970883975
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.474191006
Short name T328
Test name
Test status
Simulation time 161406630381 ps
CPU time 276.38 seconds
Started Jul 27 05:11:44 PM PDT 24
Finished Jul 27 05:16:20 PM PDT 24
Peak memory 191740 kb
Host smart-7bd9253f-f1d2-4862-9a3d-5d4c835e8232
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474191006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.474191006
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.3953539521
Short name T311
Test name
Test status
Simulation time 69506974837 ps
CPU time 47.47 seconds
Started Jul 27 05:11:44 PM PDT 24
Finished Jul 27 05:12:31 PM PDT 24
Peak memory 183480 kb
Host smart-ce9370f8-cdcf-4f37-add5-75e30700d395
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953539521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.3953539521
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.3390887555
Short name T286
Test name
Test status
Simulation time 555050996 ps
CPU time 1.52 seconds
Started Jul 27 05:11:43 PM PDT 24
Finished Jul 27 05:11:44 PM PDT 24
Peak memory 183312 kb
Host smart-1237e1ce-67db-46ee-a5a1-96ffb9c12300
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390887555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.3390887555
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.1740860161
Short name T2
Test name
Test status
Simulation time 127366344603 ps
CPU time 213.69 seconds
Started Jul 27 05:09:32 PM PDT 24
Finished Jul 27 05:13:05 PM PDT 24
Peak memory 183436 kb
Host smart-3436a86a-af9d-45e0-a40a-5cf5c21f7ff8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740860161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.1740860161
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.1824213046
Short name T448
Test name
Test status
Simulation time 129757014004 ps
CPU time 190.98 seconds
Started Jul 27 05:09:28 PM PDT 24
Finished Jul 27 05:12:40 PM PDT 24
Peak memory 183472 kb
Host smart-93b7e5c5-a7fc-459b-aa40-1d75c7870fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824213046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.1824213046
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.1192614763
Short name T28
Test name
Test status
Simulation time 580412741 ps
CPU time 1.05 seconds
Started Jul 27 05:09:27 PM PDT 24
Finished Jul 27 05:09:28 PM PDT 24
Peak memory 183332 kb
Host smart-44250a22-9b57-4de6-9e4f-c1acf7470541
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192614763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.1192614763
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.2971467968
Short name T176
Test name
Test status
Simulation time 8529236285 ps
CPU time 14.96 seconds
Started Jul 27 05:09:34 PM PDT 24
Finished Jul 27 05:09:49 PM PDT 24
Peak memory 191744 kb
Host smart-23e5d5ee-b97f-4236-8420-b1d38db3f006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971467968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.2971467968
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.2966750228
Short name T19
Test name
Test status
Simulation time 86939728 ps
CPU time 0.73 seconds
Started Jul 27 05:09:29 PM PDT 24
Finished Jul 27 05:09:30 PM PDT 24
Peak memory 213832 kb
Host smart-67555e4a-4fa5-4e60-b4e4-adfab1bbe3a5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966750228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.2966750228
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.861028387
Short name T410
Test name
Test status
Simulation time 309124252628 ps
CPU time 126.53 seconds
Started Jul 27 05:09:49 PM PDT 24
Finished Jul 27 05:11:56 PM PDT 24
Peak memory 183536 kb
Host smart-71495316-c676-4dc3-a66f-1088e78e2ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861028387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.861028387
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.1416209909
Short name T200
Test name
Test status
Simulation time 82576522840 ps
CPU time 170.26 seconds
Started Jul 27 05:09:45 PM PDT 24
Finished Jul 27 05:12:36 PM PDT 24
Peak memory 191656 kb
Host smart-37475c0f-54fa-4bcb-baa9-835ad7474dd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416209909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.1416209909
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.3456225817
Short name T160
Test name
Test status
Simulation time 143107706046 ps
CPU time 421.15 seconds
Started Jul 27 05:09:47 PM PDT 24
Finished Jul 27 05:16:48 PM PDT 24
Peak memory 191752 kb
Host smart-29069ad6-a873-476b-99a6-13deff2ceeb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456225817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.3456225817
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.421149443
Short name T374
Test name
Test status
Simulation time 179661615257 ps
CPU time 271.33 seconds
Started Jul 27 05:09:49 PM PDT 24
Finished Jul 27 05:14:21 PM PDT 24
Peak memory 191748 kb
Host smart-62e6d3d1-fc91-4b88-a678-94563d501009
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421149443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all.
421149443
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.2465078443
Short name T288
Test name
Test status
Simulation time 1822689137 ps
CPU time 3.65 seconds
Started Jul 27 05:09:45 PM PDT 24
Finished Jul 27 05:09:48 PM PDT 24
Peak memory 183212 kb
Host smart-626b498b-e2b0-4a96-94f8-47eabb501d35
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465078443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.2465078443
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.3555302137
Short name T378
Test name
Test status
Simulation time 96581436270 ps
CPU time 123.6 seconds
Started Jul 27 05:09:46 PM PDT 24
Finished Jul 27 05:11:50 PM PDT 24
Peak memory 183516 kb
Host smart-6345bf06-0221-46dd-9cab-95c727a78b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555302137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.3555302137
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.1288023939
Short name T319
Test name
Test status
Simulation time 25828935611 ps
CPU time 35.19 seconds
Started Jul 27 05:09:45 PM PDT 24
Finished Jul 27 05:10:21 PM PDT 24
Peak memory 183440 kb
Host smart-24de8b67-0ec4-4ebb-8000-17b4dd01da9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288023939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.1288023939
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.1700914922
Short name T348
Test name
Test status
Simulation time 121098946039 ps
CPU time 283.91 seconds
Started Jul 27 05:09:45 PM PDT 24
Finished Jul 27 05:14:29 PM PDT 24
Peak memory 183464 kb
Host smart-f22c65f6-2e68-472b-8f37-daf233fe498f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700914922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.1700914922
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.366359714
Short name T284
Test name
Test status
Simulation time 624720835417 ps
CPU time 597.1 seconds
Started Jul 27 05:09:50 PM PDT 24
Finished Jul 27 05:19:47 PM PDT 24
Peak memory 195504 kb
Host smart-2bad609d-5981-4408-a1d9-f790edc59d0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366359714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all.
366359714
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.887993702
Short name T424
Test name
Test status
Simulation time 591768931491 ps
CPU time 207.17 seconds
Started Jul 27 05:09:46 PM PDT 24
Finished Jul 27 05:13:13 PM PDT 24
Peak memory 183508 kb
Host smart-f15cc697-98d7-4e24-bb4d-ede87b82ed68
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887993702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.rv_timer_cfg_update_on_fly.887993702
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.2719272479
Short name T367
Test name
Test status
Simulation time 290558137373 ps
CPU time 135.24 seconds
Started Jul 27 05:09:44 PM PDT 24
Finished Jul 27 05:12:00 PM PDT 24
Peak memory 183532 kb
Host smart-1d1441d6-3eb5-462f-8472-5211791f64e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719272479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.2719272479
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.2879323621
Short name T382
Test name
Test status
Simulation time 42521560 ps
CPU time 0.64 seconds
Started Jul 27 05:09:51 PM PDT 24
Finished Jul 27 05:09:52 PM PDT 24
Peak memory 183204 kb
Host smart-e04d47e8-0f16-49ec-be11-98f1c095750b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879323621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.2879323621
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.2995224615
Short name T92
Test name
Test status
Simulation time 5275828343621 ps
CPU time 1042.89 seconds
Started Jul 27 05:09:49 PM PDT 24
Finished Jul 27 05:27:13 PM PDT 24
Peak memory 191748 kb
Host smart-0abe8e6a-f971-421f-b462-02c7e5c56473
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995224615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.2995224615
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.3157579175
Short name T388
Test name
Test status
Simulation time 494197574452 ps
CPU time 168.25 seconds
Started Jul 27 05:09:46 PM PDT 24
Finished Jul 27 05:12:34 PM PDT 24
Peak memory 183772 kb
Host smart-bebfa4d2-86c0-421c-9b1a-4a45dc015a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157579175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.3157579175
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.690106586
Short name T310
Test name
Test status
Simulation time 142067458937 ps
CPU time 98.44 seconds
Started Jul 27 05:09:46 PM PDT 24
Finished Jul 27 05:11:24 PM PDT 24
Peak memory 183540 kb
Host smart-08bf2c4f-08a2-4574-a162-da0de16fd6da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690106586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.690106586
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.1397472665
Short name T332
Test name
Test status
Simulation time 36114463056 ps
CPU time 33.39 seconds
Started Jul 27 05:09:49 PM PDT 24
Finished Jul 27 05:10:23 PM PDT 24
Peak memory 191644 kb
Host smart-6032e239-9fa8-40f5-9058-e82e7c967560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397472665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.1397472665
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.365644852
Short name T48
Test name
Test status
Simulation time 959691856443 ps
CPU time 666.03 seconds
Started Jul 27 05:09:49 PM PDT 24
Finished Jul 27 05:20:55 PM PDT 24
Peak memory 195244 kb
Host smart-027a5ea8-c456-48d5-9345-621d1cf1e559
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365644852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all.
365644852
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.1706303035
Short name T419
Test name
Test status
Simulation time 129284038087 ps
CPU time 153.28 seconds
Started Jul 27 05:09:47 PM PDT 24
Finished Jul 27 05:12:20 PM PDT 24
Peak memory 183452 kb
Host smart-7989248c-ed69-4d3c-bbca-e0b1cd7cd741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706303035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.1706303035
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.703508704
Short name T353
Test name
Test status
Simulation time 89853094582 ps
CPU time 116.32 seconds
Started Jul 27 05:09:46 PM PDT 24
Finished Jul 27 05:11:42 PM PDT 24
Peak memory 183544 kb
Host smart-06b469f1-8f46-4967-be21-17a402f72846
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703508704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.703508704
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.1374829469
Short name T323
Test name
Test status
Simulation time 53373776900 ps
CPU time 109.99 seconds
Started Jul 27 05:09:51 PM PDT 24
Finished Jul 27 05:11:41 PM PDT 24
Peak memory 191644 kb
Host smart-2d285d99-a30e-4461-935a-c2e347377b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374829469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.1374829469
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.1141961070
Short name T364
Test name
Test status
Simulation time 60121506 ps
CPU time 0.53 seconds
Started Jul 27 05:09:50 PM PDT 24
Finished Jul 27 05:09:51 PM PDT 24
Peak memory 183300 kb
Host smart-aa902de0-38f6-4388-82c9-e62947f1fcdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141961070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.1141961070
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.3151928807
Short name T303
Test name
Test status
Simulation time 149260850903 ps
CPU time 150.41 seconds
Started Jul 27 05:09:44 PM PDT 24
Finished Jul 27 05:12:14 PM PDT 24
Peak memory 183532 kb
Host smart-06dde5ca-f0ad-427d-a14f-bba9eb7acf89
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151928807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.3151928807
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.2773373218
Short name T398
Test name
Test status
Simulation time 145462036640 ps
CPU time 62.58 seconds
Started Jul 27 05:09:50 PM PDT 24
Finished Jul 27 05:10:53 PM PDT 24
Peak memory 183532 kb
Host smart-b67d24d9-386d-4f9c-83c8-4a641ceb26a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773373218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.2773373218
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.3525630481
Short name T292
Test name
Test status
Simulation time 30048591307 ps
CPU time 33.96 seconds
Started Jul 27 05:09:45 PM PDT 24
Finished Jul 27 05:10:19 PM PDT 24
Peak memory 183772 kb
Host smart-52a48444-2cc9-4471-a07a-a5f5d0645694
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525630481 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.3525630481
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.1063996894
Short name T443
Test name
Test status
Simulation time 461382842170 ps
CPU time 103.08 seconds
Started Jul 27 05:09:49 PM PDT 24
Finished Jul 27 05:11:32 PM PDT 24
Peak memory 183540 kb
Host smart-5c32c293-7929-49e5-944c-add8afc158bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063996894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.1063996894
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.1918904144
Short name T222
Test name
Test status
Simulation time 180288661544 ps
CPU time 93.99 seconds
Started Jul 27 05:09:49 PM PDT 24
Finished Jul 27 05:11:24 PM PDT 24
Peak memory 183544 kb
Host smart-7af22158-8d81-46b6-8fec-d644317233ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918904144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.1918904144
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.941667431
Short name T304
Test name
Test status
Simulation time 96191869222 ps
CPU time 156.24 seconds
Started Jul 27 05:09:47 PM PDT 24
Finished Jul 27 05:12:23 PM PDT 24
Peak memory 183528 kb
Host smart-d3ae1a53-aa73-4503-8166-e37f177fb57b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941667431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.rv_timer_cfg_update_on_fly.941667431
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_random.764939849
Short name T326
Test name
Test status
Simulation time 131725485943 ps
CPU time 220.76 seconds
Started Jul 27 05:09:47 PM PDT 24
Finished Jul 27 05:13:28 PM PDT 24
Peak memory 183520 kb
Host smart-dca8c821-b771-49fa-9621-91e4245f399b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764939849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.764939849
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.3128308949
Short name T266
Test name
Test status
Simulation time 9961040943 ps
CPU time 13.71 seconds
Started Jul 27 05:09:49 PM PDT 24
Finished Jul 27 05:10:04 PM PDT 24
Peak memory 183400 kb
Host smart-61292225-aa74-4c5c-b6bc-c59a206691ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128308949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.3128308949
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.1286503681
Short name T198
Test name
Test status
Simulation time 134190243947 ps
CPU time 111.13 seconds
Started Jul 27 05:09:58 PM PDT 24
Finished Jul 27 05:11:49 PM PDT 24
Peak memory 183440 kb
Host smart-0e860d5a-be29-4188-b3ee-0ed5ad98d0f3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286503681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.1286503681
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.2603062389
Short name T440
Test name
Test status
Simulation time 12589886386 ps
CPU time 9.02 seconds
Started Jul 27 05:09:54 PM PDT 24
Finished Jul 27 05:10:03 PM PDT 24
Peak memory 183540 kb
Host smart-885dc346-769d-4f5e-a423-53f9e175ef93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603062389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.2603062389
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.95450779
Short name T60
Test name
Test status
Simulation time 104273428657 ps
CPU time 1480.48 seconds
Started Jul 27 05:09:55 PM PDT 24
Finished Jul 27 05:34:36 PM PDT 24
Peak memory 191656 kb
Host smart-5486fc23-83a0-45b2-9ffa-f69136e8eb26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95450779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.95450779
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.2601183175
Short name T439
Test name
Test status
Simulation time 100230080096 ps
CPU time 154.73 seconds
Started Jul 27 05:09:54 PM PDT 24
Finished Jul 27 05:12:29 PM PDT 24
Peak memory 191756 kb
Host smart-2d8d6fa8-bd36-4fae-bdf1-142b47bddf04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601183175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.2601183175
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.1338496709
Short name T211
Test name
Test status
Simulation time 1197183919113 ps
CPU time 1446.55 seconds
Started Jul 27 05:09:57 PM PDT 24
Finished Jul 27 05:34:04 PM PDT 24
Peak memory 196620 kb
Host smart-fecdf3f0-1682-4028-90fb-961c5e5357e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338496709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.1338496709
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.2481289749
Short name T202
Test name
Test status
Simulation time 19530658207 ps
CPU time 30.34 seconds
Started Jul 27 05:09:56 PM PDT 24
Finished Jul 27 05:10:26 PM PDT 24
Peak memory 183512 kb
Host smart-9d0eaecf-1135-4f13-a1f1-7e5e93010516
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481289749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.2481289749
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.757775214
Short name T371
Test name
Test status
Simulation time 107109560030 ps
CPU time 132.62 seconds
Started Jul 27 05:09:54 PM PDT 24
Finished Jul 27 05:12:07 PM PDT 24
Peak memory 183432 kb
Host smart-907da12d-b693-4153-b5ec-3d37c6dc2268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757775214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.757775214
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.231538523
Short name T258
Test name
Test status
Simulation time 120967031083 ps
CPU time 429.34 seconds
Started Jul 27 05:10:08 PM PDT 24
Finished Jul 27 05:17:18 PM PDT 24
Peak memory 193680 kb
Host smart-7c3e7fa6-e7f6-4f8a-95b9-ca88cd147d69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231538523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.231538523
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.612460931
Short name T416
Test name
Test status
Simulation time 439936762818 ps
CPU time 98.73 seconds
Started Jul 27 05:09:53 PM PDT 24
Finished Jul 27 05:11:32 PM PDT 24
Peak memory 191628 kb
Host smart-f881d03c-1573-455b-aeb3-9268af90bb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612460931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.612460931
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.3473719412
Short name T196
Test name
Test status
Simulation time 96232463946 ps
CPU time 114.32 seconds
Started Jul 27 05:09:59 PM PDT 24
Finished Jul 27 05:11:53 PM PDT 24
Peak memory 183524 kb
Host smart-2cf18ea3-ff80-423c-85fd-0b738ac10de6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473719412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.3473719412
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.3304192536
Short name T330
Test name
Test status
Simulation time 2764035619366 ps
CPU time 1372.84 seconds
Started Jul 27 05:09:57 PM PDT 24
Finished Jul 27 05:32:50 PM PDT 24
Peak memory 183444 kb
Host smart-29e6b094-bf11-4cf8-9739-e97a257ac709
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304192536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.3304192536
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.3979046415
Short name T431
Test name
Test status
Simulation time 56153199407 ps
CPU time 69.18 seconds
Started Jul 27 05:09:57 PM PDT 24
Finished Jul 27 05:11:06 PM PDT 24
Peak memory 183464 kb
Host smart-c6e98fbe-e32f-4b23-9774-f0a88f9836a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979046415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.3979046415
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all_with_rand_reset.1812328103
Short name T422
Test name
Test status
Simulation time 48831206009 ps
CPU time 504.65 seconds
Started Jul 27 05:10:08 PM PDT 24
Finished Jul 27 05:18:33 PM PDT 24
Peak memory 206348 kb
Host smart-7a86a4f9-1bc8-42e6-8c9b-125ab1898193
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812328103 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all_with_rand_reset.1812328103
Directory /workspace/29.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.2816869444
Short name T235
Test name
Test status
Simulation time 655599461307 ps
CPU time 380.14 seconds
Started Jul 27 05:09:34 PM PDT 24
Finished Jul 27 05:15:54 PM PDT 24
Peak memory 183528 kb
Host smart-af2ed449-9c95-4312-b2f8-d3caa3ba09fd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816869444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.2816869444
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.824421423
Short name T430
Test name
Test status
Simulation time 451199975939 ps
CPU time 189.7 seconds
Started Jul 27 05:09:26 PM PDT 24
Finished Jul 27 05:12:36 PM PDT 24
Peak memory 183552 kb
Host smart-5e190932-3fad-447a-a3e4-f833c998b7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824421423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.824421423
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.3253990943
Short name T277
Test name
Test status
Simulation time 562053266655 ps
CPU time 354.73 seconds
Started Jul 27 05:09:30 PM PDT 24
Finished Jul 27 05:15:25 PM PDT 24
Peak memory 191740 kb
Host smart-55ff9bb2-434e-4355-9d70-db434981b1ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253990943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.3253990943
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.3286875090
Short name T452
Test name
Test status
Simulation time 50117613807 ps
CPU time 1314.47 seconds
Started Jul 27 05:09:30 PM PDT 24
Finished Jul 27 05:31:25 PM PDT 24
Peak memory 191760 kb
Host smart-2c50ac0f-d1ed-4b86-8fab-98257150b632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286875090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.3286875090
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.1618705515
Short name T18
Test name
Test status
Simulation time 42022803 ps
CPU time 0.74 seconds
Started Jul 27 05:09:26 PM PDT 24
Finished Jul 27 05:09:27 PM PDT 24
Peak memory 214720 kb
Host smart-74a563d8-f695-4e56-b4c1-7441bb889f2f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618705515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.1618705515
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.1561234657
Short name T271
Test name
Test status
Simulation time 681644601746 ps
CPU time 624.41 seconds
Started Jul 27 05:09:27 PM PDT 24
Finished Jul 27 05:19:52 PM PDT 24
Peak memory 191744 kb
Host smart-0d4388a9-206d-4be2-a6fe-b184e7ef5c39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561234657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
1561234657
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all_with_rand_reset.726414175
Short name T38
Test name
Test status
Simulation time 27023816616 ps
CPU time 213.44 seconds
Started Jul 27 05:09:30 PM PDT 24
Finished Jul 27 05:13:04 PM PDT 24
Peak memory 198216 kb
Host smart-fafbda86-e915-44be-bad1-b3c723e7d31f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726414175 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all_with_rand_reset.726414175
Directory /workspace/3.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.2076713987
Short name T355
Test name
Test status
Simulation time 1437447701181 ps
CPU time 1274.39 seconds
Started Jul 27 05:09:55 PM PDT 24
Finished Jul 27 05:31:10 PM PDT 24
Peak memory 183524 kb
Host smart-caf852ce-cf43-4a59-840f-d7dc6848dbe2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076713987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.2076713987
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.778074407
Short name T409
Test name
Test status
Simulation time 46933812514 ps
CPU time 58.76 seconds
Started Jul 27 05:09:58 PM PDT 24
Finished Jul 27 05:10:57 PM PDT 24
Peak memory 183560 kb
Host smart-36443643-b64b-4b34-9fd7-df84e2e2b43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778074407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.778074407
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.4219003060
Short name T352
Test name
Test status
Simulation time 100958978007 ps
CPU time 307.53 seconds
Started Jul 27 05:09:58 PM PDT 24
Finished Jul 27 05:15:06 PM PDT 24
Peak memory 191732 kb
Host smart-25364c95-b8ac-41df-b0fd-27a08e640302
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219003060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.4219003060
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.2954908976
Short name T451
Test name
Test status
Simulation time 11776597476 ps
CPU time 21.27 seconds
Started Jul 27 05:09:58 PM PDT 24
Finished Jul 27 05:10:19 PM PDT 24
Peak memory 191760 kb
Host smart-0a0836df-36d8-4aed-aa26-183584434adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954908976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.2954908976
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.4088738704
Short name T361
Test name
Test status
Simulation time 63045271782 ps
CPU time 49.82 seconds
Started Jul 27 05:09:56 PM PDT 24
Finished Jul 27 05:10:45 PM PDT 24
Peak memory 193936 kb
Host smart-6deef2fc-e9bd-483d-b423-87a5059771e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088738704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.4088738704
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.607607678
Short name T21
Test name
Test status
Simulation time 632126370222 ps
CPU time 531.21 seconds
Started Jul 27 05:09:54 PM PDT 24
Finished Jul 27 05:18:45 PM PDT 24
Peak memory 183528 kb
Host smart-82f0daad-d507-426a-9fbc-ce6d15affc35
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607607678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.rv_timer_cfg_update_on_fly.607607678
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.122512233
Short name T396
Test name
Test status
Simulation time 803138674718 ps
CPU time 157.65 seconds
Started Jul 27 05:09:55 PM PDT 24
Finished Jul 27 05:12:33 PM PDT 24
Peak memory 183532 kb
Host smart-8f47fefb-229b-47eb-9880-4f4117bc7615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122512233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.122512233
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.1770292519
Short name T283
Test name
Test status
Simulation time 1018884657404 ps
CPU time 195.36 seconds
Started Jul 27 05:09:59 PM PDT 24
Finished Jul 27 05:13:14 PM PDT 24
Peak memory 191672 kb
Host smart-640337a6-18bb-4fb2-b70c-5146098cdcbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770292519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.1770292519
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.3115305041
Short name T358
Test name
Test status
Simulation time 35407510128 ps
CPU time 28.05 seconds
Started Jul 27 05:09:57 PM PDT 24
Finished Jul 27 05:10:25 PM PDT 24
Peak memory 191688 kb
Host smart-a4203a7e-97d5-494d-a6f2-a3f8ba33474c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115305041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.3115305041
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.3391918362
Short name T445
Test name
Test status
Simulation time 648354387900 ps
CPU time 307.33 seconds
Started Jul 27 05:10:09 PM PDT 24
Finished Jul 27 05:15:16 PM PDT 24
Peak memory 183416 kb
Host smart-51315c09-0d43-4e4a-aebb-8760d06c8bc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391918362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.3391918362
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all_with_rand_reset.2108960911
Short name T438
Test name
Test status
Simulation time 98223218447 ps
CPU time 410.26 seconds
Started Jul 27 05:09:56 PM PDT 24
Finished Jul 27 05:16:46 PM PDT 24
Peak memory 198236 kb
Host smart-d86fe6be-e018-403f-95e2-350dc54d7fe4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108960911 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all_with_rand_reset.2108960911
Directory /workspace/31.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.1129603627
Short name T429
Test name
Test status
Simulation time 38855298055 ps
CPU time 20.64 seconds
Started Jul 27 05:09:59 PM PDT 24
Finished Jul 27 05:10:19 PM PDT 24
Peak memory 183480 kb
Host smart-bf39935c-467a-452d-ab4d-891e8b6241e2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129603627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.1129603627
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.2564508602
Short name T390
Test name
Test status
Simulation time 549719262828 ps
CPU time 216.2 seconds
Started Jul 27 05:09:53 PM PDT 24
Finished Jul 27 05:13:30 PM PDT 24
Peak memory 183456 kb
Host smart-896ecc1f-78a5-4a6e-b0ac-fe3426f2c89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564508602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.2564508602
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.1012951867
Short name T233
Test name
Test status
Simulation time 105558621543 ps
CPU time 705.81 seconds
Started Jul 27 05:09:56 PM PDT 24
Finished Jul 27 05:21:42 PM PDT 24
Peak memory 191764 kb
Host smart-7b10af6c-7fed-4a5e-91d9-3097f2b3c19b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012951867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.1012951867
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.3056010064
Short name T178
Test name
Test status
Simulation time 27173937101 ps
CPU time 46.23 seconds
Started Jul 27 05:09:56 PM PDT 24
Finished Jul 27 05:10:42 PM PDT 24
Peak memory 191644 kb
Host smart-82ae3f33-3691-452e-9f9a-928dc5afdab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056010064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.3056010064
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.2927354850
Short name T49
Test name
Test status
Simulation time 148997652160 ps
CPU time 223.44 seconds
Started Jul 27 05:09:55 PM PDT 24
Finished Jul 27 05:13:38 PM PDT 24
Peak memory 191700 kb
Host smart-094892fe-48ce-46f0-92a2-3e044f6ad2c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927354850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.2927354850
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.2538182723
Short name T321
Test name
Test status
Simulation time 47624391613 ps
CPU time 72.6 seconds
Started Jul 27 05:09:55 PM PDT 24
Finished Jul 27 05:11:08 PM PDT 24
Peak memory 183452 kb
Host smart-9a3704bc-8918-4d9e-b33a-db4831a0bf3e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538182723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.2538182723
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.3370127380
Short name T437
Test name
Test status
Simulation time 519988447445 ps
CPU time 215.2 seconds
Started Jul 27 05:09:54 PM PDT 24
Finished Jul 27 05:13:29 PM PDT 24
Peak memory 183472 kb
Host smart-38bea42e-a0cc-4d4f-9d65-52aeee069c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370127380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.3370127380
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.2604279209
Short name T93
Test name
Test status
Simulation time 385871068174 ps
CPU time 177.17 seconds
Started Jul 27 05:10:09 PM PDT 24
Finished Jul 27 05:13:06 PM PDT 24
Peak memory 191628 kb
Host smart-2be3d47e-84cd-472e-a751-4a9046dc7c10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604279209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.2604279209
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.1237196653
Short name T356
Test name
Test status
Simulation time 1480652410 ps
CPU time 2.87 seconds
Started Jul 27 05:09:57 PM PDT 24
Finished Jul 27 05:10:00 PM PDT 24
Peak memory 183200 kb
Host smart-ace2b8f2-aacd-45dc-b63b-0c92f2ea6e43
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237196653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.1237196653
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.3822211733
Short name T381
Test name
Test status
Simulation time 874447132803 ps
CPU time 349.57 seconds
Started Jul 27 05:09:56 PM PDT 24
Finished Jul 27 05:15:46 PM PDT 24
Peak memory 183472 kb
Host smart-6610df77-5b86-4513-acf8-6b31033b27b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822211733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.3822211733
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.298725980
Short name T331
Test name
Test status
Simulation time 36532987605 ps
CPU time 70.52 seconds
Started Jul 27 05:09:55 PM PDT 24
Finished Jul 27 05:11:05 PM PDT 24
Peak memory 183556 kb
Host smart-f5e9c813-1ee0-427a-9dfd-8ae9cf6052ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298725980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.298725980
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.1166629231
Short name T278
Test name
Test status
Simulation time 119679761801 ps
CPU time 209.68 seconds
Started Jul 27 05:09:56 PM PDT 24
Finished Jul 27 05:13:26 PM PDT 24
Peak memory 191732 kb
Host smart-62ddd533-00cf-41ad-87fa-54a70db309d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166629231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.1166629231
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.2883097888
Short name T128
Test name
Test status
Simulation time 184618342265 ps
CPU time 299.96 seconds
Started Jul 27 05:10:04 PM PDT 24
Finished Jul 27 05:15:04 PM PDT 24
Peak memory 183484 kb
Host smart-d927c587-1ba5-4e4a-b869-e3cd0e917610
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883097888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.2883097888
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.2001997072
Short name T385
Test name
Test status
Simulation time 315369354294 ps
CPU time 234.05 seconds
Started Jul 27 05:10:09 PM PDT 24
Finished Jul 27 05:14:03 PM PDT 24
Peak memory 183436 kb
Host smart-cdf1b4b9-3b9d-44e2-bd30-884c0323b027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001997072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.2001997072
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.2445928262
Short name T420
Test name
Test status
Simulation time 9610859924 ps
CPU time 166.4 seconds
Started Jul 27 05:10:09 PM PDT 24
Finished Jul 27 05:12:55 PM PDT 24
Peak memory 183436 kb
Host smart-81b1a0bc-b4ae-4912-ae5c-ed4893e8198e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445928262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.2445928262
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.4130903412
Short name T428
Test name
Test status
Simulation time 44131047322 ps
CPU time 332.9 seconds
Started Jul 27 05:10:04 PM PDT 24
Finished Jul 27 05:15:37 PM PDT 24
Peak memory 194660 kb
Host smart-1bdbc08e-6a6a-49ed-9e93-c434e393efe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130903412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.4130903412
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.2606648333
Short name T366
Test name
Test status
Simulation time 851226503833 ps
CPU time 294.47 seconds
Started Jul 27 05:10:02 PM PDT 24
Finished Jul 27 05:14:56 PM PDT 24
Peak memory 191736 kb
Host smart-e1c5ccac-9d4e-4e50-bfea-91d5b5607150
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606648333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.2606648333
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.839407085
Short name T386
Test name
Test status
Simulation time 18595772616 ps
CPU time 11.2 seconds
Started Jul 27 05:10:04 PM PDT 24
Finished Jul 27 05:10:16 PM PDT 24
Peak memory 183764 kb
Host smart-4abab660-3ebe-4796-bd5d-c1ec723f4efb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839407085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.rv_timer_cfg_update_on_fly.839407085
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.112894179
Short name T370
Test name
Test status
Simulation time 99085053999 ps
CPU time 148.29 seconds
Started Jul 27 05:10:05 PM PDT 24
Finished Jul 27 05:12:33 PM PDT 24
Peak memory 183548 kb
Host smart-aea637b3-869c-4c24-b946-5912321f08cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112894179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.112894179
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.402131886
Short name T329
Test name
Test status
Simulation time 587618466442 ps
CPU time 357.48 seconds
Started Jul 27 05:10:09 PM PDT 24
Finished Jul 27 05:16:07 PM PDT 24
Peak memory 191740 kb
Host smart-7040a2cf-eae4-41c9-8591-07a5842a4025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402131886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.402131886
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.3157778556
Short name T402
Test name
Test status
Simulation time 1750051933603 ps
CPU time 731.57 seconds
Started Jul 27 05:10:04 PM PDT 24
Finished Jul 27 05:22:16 PM PDT 24
Peak memory 191740 kb
Host smart-5a940460-5e58-4846-a3a7-d6f90328ee81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157778556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.3157778556
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.2941759184
Short name T376
Test name
Test status
Simulation time 94528703443 ps
CPU time 38.51 seconds
Started Jul 27 05:10:06 PM PDT 24
Finished Jul 27 05:10:45 PM PDT 24
Peak memory 183448 kb
Host smart-05c1fc3c-c9ca-4bef-9cf7-a28a67a661a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941759184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.2941759184
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.3183653916
Short name T150
Test name
Test status
Simulation time 609108747782 ps
CPU time 187.65 seconds
Started Jul 27 05:10:06 PM PDT 24
Finished Jul 27 05:13:14 PM PDT 24
Peak memory 191736 kb
Host smart-6eb2bb05-221d-4287-86c4-eb147a251e24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183653916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.3183653916
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.2372959
Short name T411
Test name
Test status
Simulation time 4195044078 ps
CPU time 7.17 seconds
Started Jul 27 05:10:07 PM PDT 24
Finished Jul 27 05:10:14 PM PDT 24
Peak memory 183536 kb
Host smart-2a72a0b0-8d1f-4080-946d-a90b44197caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.2372959
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.3165235040
Short name T168
Test name
Test status
Simulation time 292519174903 ps
CPU time 2131.4 seconds
Started Jul 27 05:10:10 PM PDT 24
Finished Jul 27 05:45:41 PM PDT 24
Peak memory 191804 kb
Host smart-a6a1f6dd-c872-4850-ae57-7047c77f91cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165235040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.3165235040
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all_with_rand_reset.1202677070
Short name T15
Test name
Test status
Simulation time 131529092575 ps
CPU time 1061.87 seconds
Started Jul 27 05:10:06 PM PDT 24
Finished Jul 27 05:27:48 PM PDT 24
Peak memory 212956 kb
Host smart-0bd068f2-b99b-4e99-8774-47d57b776ca0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202677070 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all_with_rand_reset.1202677070
Directory /workspace/37.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.3194522654
Short name T220
Test name
Test status
Simulation time 1438572073010 ps
CPU time 791.87 seconds
Started Jul 27 05:10:06 PM PDT 24
Finished Jul 27 05:23:18 PM PDT 24
Peak memory 183528 kb
Host smart-f7939144-042d-4f65-bcae-33575fc9a2d7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194522654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.3194522654
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.3163561730
Short name T377
Test name
Test status
Simulation time 26464615696 ps
CPU time 39.15 seconds
Started Jul 27 05:10:07 PM PDT 24
Finished Jul 27 05:10:46 PM PDT 24
Peak memory 183540 kb
Host smart-22c50f1f-91ea-474d-b0c2-e00d4c5e3293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163561730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.3163561730
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.3619464608
Short name T421
Test name
Test status
Simulation time 53986482832 ps
CPU time 1858.36 seconds
Started Jul 27 05:10:07 PM PDT 24
Finished Jul 27 05:41:06 PM PDT 24
Peak memory 191712 kb
Host smart-4c162f7c-8548-4e84-b5e3-b87345606e4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619464608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.3619464608
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.2856098765
Short name T401
Test name
Test status
Simulation time 737678290 ps
CPU time 0.89 seconds
Started Jul 27 05:10:06 PM PDT 24
Finished Jul 27 05:10:07 PM PDT 24
Peak memory 192084 kb
Host smart-ab5a7094-8250-4902-9613-00607c57a563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856098765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.2856098765
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.1222335588
Short name T408
Test name
Test status
Simulation time 5706595961 ps
CPU time 9.07 seconds
Started Jul 27 05:10:10 PM PDT 24
Finished Jul 27 05:10:19 PM PDT 24
Peak memory 183568 kb
Host smart-ae35c479-87e5-4db0-831e-16a92673adf0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222335588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.1222335588
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.3646226634
Short name T417
Test name
Test status
Simulation time 117400733673 ps
CPU time 166.96 seconds
Started Jul 27 05:10:09 PM PDT 24
Finished Jul 27 05:12:56 PM PDT 24
Peak memory 183524 kb
Host smart-d0b8be91-da91-43ff-95e2-a504173df9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646226634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.3646226634
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.3802216691
Short name T140
Test name
Test status
Simulation time 255815739491 ps
CPU time 437.06 seconds
Started Jul 27 05:10:06 PM PDT 24
Finished Jul 27 05:17:23 PM PDT 24
Peak memory 191744 kb
Host smart-a2286654-d2ce-4a0a-a708-bef92a072997
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802216691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.3802216691
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.3243733633
Short name T244
Test name
Test status
Simulation time 4100741655 ps
CPU time 6.67 seconds
Started Jul 27 05:10:08 PM PDT 24
Finished Jul 27 05:10:15 PM PDT 24
Peak memory 191684 kb
Host smart-d06e034e-9de6-4122-a5f7-e60a284a0ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243733633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.3243733633
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.3496977005
Short name T253
Test name
Test status
Simulation time 1191655412464 ps
CPU time 630.71 seconds
Started Jul 27 05:09:27 PM PDT 24
Finished Jul 27 05:19:58 PM PDT 24
Peak memory 183536 kb
Host smart-a7de72b1-1487-4073-b027-5d8f1c007f4d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496977005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.3496977005
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.1981554625
Short name T423
Test name
Test status
Simulation time 331031584064 ps
CPU time 139.2 seconds
Started Jul 27 05:09:26 PM PDT 24
Finished Jul 27 05:11:46 PM PDT 24
Peak memory 183556 kb
Host smart-60c28773-fdd5-494f-afe4-78f16756eb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981554625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.1981554625
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.603250555
Short name T327
Test name
Test status
Simulation time 151373388790 ps
CPU time 506.05 seconds
Started Jul 27 05:09:26 PM PDT 24
Finished Jul 27 05:17:52 PM PDT 24
Peak memory 195192 kb
Host smart-01cb3c45-af3e-49fe-9075-f9c58522fe91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603250555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.603250555
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.487736001
Short name T389
Test name
Test status
Simulation time 1102873566 ps
CPU time 1.07 seconds
Started Jul 27 05:09:27 PM PDT 24
Finished Jul 27 05:09:29 PM PDT 24
Peak memory 193104 kb
Host smart-045f3e5e-cb4d-4e94-bf54-81e9bf938abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487736001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.487736001
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.3770214710
Short name T16
Test name
Test status
Simulation time 280523059 ps
CPU time 0.82 seconds
Started Jul 27 05:09:28 PM PDT 24
Finished Jul 27 05:09:29 PM PDT 24
Peak memory 213828 kb
Host smart-1e3d559f-8fb9-4524-8dd9-a5f15972b622
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770214710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.3770214710
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.2319747438
Short name T56
Test name
Test status
Simulation time 34108452659 ps
CPU time 22.49 seconds
Started Jul 27 05:09:30 PM PDT 24
Finished Jul 27 05:09:52 PM PDT 24
Peak memory 183492 kb
Host smart-394972d5-fa1a-4374-8e83-c3f7f9b90cf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319747438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
2319747438
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.2229873928
Short name T314
Test name
Test status
Simulation time 1547549186480 ps
CPU time 885.07 seconds
Started Jul 27 05:10:07 PM PDT 24
Finished Jul 27 05:24:53 PM PDT 24
Peak memory 183528 kb
Host smart-73dcbedc-724a-48a1-b80a-0474bd36e62a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229873928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.2229873928
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.74341851
Short name T369
Test name
Test status
Simulation time 111484512408 ps
CPU time 46.89 seconds
Started Jul 27 05:10:07 PM PDT 24
Finished Jul 27 05:10:54 PM PDT 24
Peak memory 183564 kb
Host smart-095eaa45-673d-4316-9058-69e3a46a94e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74341851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.74341851
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.766191461
Short name T360
Test name
Test status
Simulation time 145063372080 ps
CPU time 50.22 seconds
Started Jul 27 05:10:11 PM PDT 24
Finished Jul 27 05:11:01 PM PDT 24
Peak memory 193936 kb
Host smart-7de26f94-e589-4fd1-8ed3-ac0a5112e302
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766191461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.766191461
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.1867483843
Short name T224
Test name
Test status
Simulation time 27641547146 ps
CPU time 36.97 seconds
Started Jul 27 05:10:10 PM PDT 24
Finished Jul 27 05:10:47 PM PDT 24
Peak memory 191784 kb
Host smart-452151e9-0da6-436f-a019-dd53943fae76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867483843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.1867483843
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.98126961
Short name T165
Test name
Test status
Simulation time 392820241116 ps
CPU time 784.06 seconds
Started Jul 27 05:10:06 PM PDT 24
Finished Jul 27 05:23:10 PM PDT 24
Peak memory 191760 kb
Host smart-d569271c-4f7a-4e02-8e8a-d9a2232d67c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98126961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all.98126961
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.4163684893
Short name T275
Test name
Test status
Simulation time 835720816919 ps
CPU time 1452.84 seconds
Started Jul 27 05:10:05 PM PDT 24
Finished Jul 27 05:34:18 PM PDT 24
Peak memory 183468 kb
Host smart-49e43c00-7827-4cd7-850f-39339e13505e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163684893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.4163684893
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.3613474593
Short name T379
Test name
Test status
Simulation time 167569167589 ps
CPU time 234.02 seconds
Started Jul 27 05:10:05 PM PDT 24
Finished Jul 27 05:13:59 PM PDT 24
Peak memory 183456 kb
Host smart-38a3db6e-a688-4491-a2be-65e6a32ead3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613474593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.3613474593
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.1538477899
Short name T338
Test name
Test status
Simulation time 41119597336 ps
CPU time 40.1 seconds
Started Jul 27 05:10:04 PM PDT 24
Finished Jul 27 05:10:44 PM PDT 24
Peak memory 183516 kb
Host smart-92b54ff7-5baf-4c47-9e3b-78756a716d05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538477899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.1538477899
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.2673072773
Short name T205
Test name
Test status
Simulation time 43788758491 ps
CPU time 72.54 seconds
Started Jul 27 05:10:06 PM PDT 24
Finished Jul 27 05:11:19 PM PDT 24
Peak memory 183528 kb
Host smart-076b0ee1-e8a0-4272-93e4-96e792501b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673072773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.2673072773
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.826207975
Short name T351
Test name
Test status
Simulation time 1612065382163 ps
CPU time 904.04 seconds
Started Jul 27 05:10:08 PM PDT 24
Finished Jul 27 05:25:12 PM PDT 24
Peak memory 191736 kb
Host smart-e4a191b9-09c3-4743-8736-e4edc6bfc370
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826207975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all.
826207975
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.1876540348
Short name T109
Test name
Test status
Simulation time 115540885926 ps
CPU time 195.21 seconds
Started Jul 27 05:10:06 PM PDT 24
Finished Jul 27 05:13:21 PM PDT 24
Peak memory 183520 kb
Host smart-7fa8bf81-c529-4b19-9820-b6c43636bd3e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876540348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.1876540348
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.1946788464
Short name T404
Test name
Test status
Simulation time 826445552018 ps
CPU time 295.69 seconds
Started Jul 27 05:10:05 PM PDT 24
Finished Jul 27 05:15:01 PM PDT 24
Peak memory 183500 kb
Host smart-70efd048-382b-4d3a-beea-2041700ef971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946788464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.1946788464
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.1500126457
Short name T242
Test name
Test status
Simulation time 128208543857 ps
CPU time 158.76 seconds
Started Jul 27 05:10:08 PM PDT 24
Finished Jul 27 05:12:47 PM PDT 24
Peak memory 183476 kb
Host smart-80eb2195-1abb-4390-b8c4-65394cf1e980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500126457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.1500126457
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.3048351439
Short name T104
Test name
Test status
Simulation time 1682051923179 ps
CPU time 770.15 seconds
Started Jul 27 05:10:04 PM PDT 24
Finished Jul 27 05:22:55 PM PDT 24
Peak memory 183484 kb
Host smart-8563088f-8703-4050-bb1d-2d779a55289c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048351439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.3048351439
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.347094467
Short name T400
Test name
Test status
Simulation time 19941644131 ps
CPU time 32.07 seconds
Started Jul 27 05:10:07 PM PDT 24
Finished Jul 27 05:10:39 PM PDT 24
Peak memory 183448 kb
Host smart-b9c6fd3f-aebc-4edc-a27f-a2914acc9c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347094467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.347094467
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.2170332566
Short name T137
Test name
Test status
Simulation time 314929692784 ps
CPU time 121.01 seconds
Started Jul 27 05:10:07 PM PDT 24
Finished Jul 27 05:12:08 PM PDT 24
Peak memory 195024 kb
Host smart-154e51ff-f447-44fb-9337-a9913f390ea3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170332566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.2170332566
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.3402501352
Short name T384
Test name
Test status
Simulation time 136405403 ps
CPU time 0.6 seconds
Started Jul 27 05:10:05 PM PDT 24
Finished Jul 27 05:10:06 PM PDT 24
Peak memory 183276 kb
Host smart-f4192c60-24f2-40d9-9975-c37b27b8f60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402501352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.3402501352
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.3200463007
Short name T333
Test name
Test status
Simulation time 499229845508 ps
CPU time 801.45 seconds
Started Jul 27 05:10:06 PM PDT 24
Finished Jul 27 05:23:27 PM PDT 24
Peak memory 183420 kb
Host smart-9a7c22d3-3e10-4013-a28f-9cb37aa9729f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200463007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.3200463007
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.3685492584
Short name T405
Test name
Test status
Simulation time 169957153624 ps
CPU time 66.27 seconds
Started Jul 27 05:10:06 PM PDT 24
Finished Jul 27 05:11:12 PM PDT 24
Peak memory 183524 kb
Host smart-8d56e54a-c74d-4c80-b266-5e88860f0502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685492584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.3685492584
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.4257138628
Short name T191
Test name
Test status
Simulation time 28488098308 ps
CPU time 47.63 seconds
Started Jul 27 05:10:08 PM PDT 24
Finished Jul 27 05:10:56 PM PDT 24
Peak memory 191728 kb
Host smart-45ba207d-df64-4f64-92bc-51ccc1e31714
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257138628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.4257138628
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.1473097619
Short name T313
Test name
Test status
Simulation time 57936748588 ps
CPU time 93.81 seconds
Started Jul 27 05:10:06 PM PDT 24
Finished Jul 27 05:11:40 PM PDT 24
Peak memory 183528 kb
Host smart-a4675643-ccba-48ef-9756-076b2c3a9e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473097619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.1473097619
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.645849226
Short name T35
Test name
Test status
Simulation time 208121404099 ps
CPU time 200.85 seconds
Started Jul 27 05:10:10 PM PDT 24
Finished Jul 27 05:13:31 PM PDT 24
Peak memory 198236 kb
Host smart-f82d9d9b-af07-461d-8ae1-6ac355818f0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645849226 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.645849226
Directory /workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rv_timer_random.2230716443
Short name T125
Test name
Test status
Simulation time 762438222179 ps
CPU time 476.53 seconds
Started Jul 27 05:10:07 PM PDT 24
Finished Jul 27 05:18:04 PM PDT 24
Peak memory 191732 kb
Host smart-c97abede-5b58-4b5b-95e5-a9a09854014e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230716443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.2230716443
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.3777249885
Short name T181
Test name
Test status
Simulation time 599277513026 ps
CPU time 797.35 seconds
Started Jul 27 05:10:11 PM PDT 24
Finished Jul 27 05:23:28 PM PDT 24
Peak memory 191728 kb
Host smart-2befcb3d-91cc-4279-aa6c-498a23c4e78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777249885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.3777249885
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.690143331
Short name T341
Test name
Test status
Simulation time 160954264962 ps
CPU time 269.48 seconds
Started Jul 27 05:10:12 PM PDT 24
Finished Jul 27 05:14:42 PM PDT 24
Peak memory 183536 kb
Host smart-5a79c53e-6279-401a-b4a8-1f6114ae0679
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690143331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.rv_timer_cfg_update_on_fly.690143331
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.2187438502
Short name T368
Test name
Test status
Simulation time 172995913970 ps
CPU time 261.58 seconds
Started Jul 27 05:10:06 PM PDT 24
Finished Jul 27 05:14:27 PM PDT 24
Peak memory 183492 kb
Host smart-b965e241-b793-46ce-a544-593c7a7c57fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187438502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.2187438502
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.1295797505
Short name T24
Test name
Test status
Simulation time 206066744873 ps
CPU time 205.01 seconds
Started Jul 27 05:10:08 PM PDT 24
Finished Jul 27 05:13:33 PM PDT 24
Peak memory 191724 kb
Host smart-7c026dfd-13be-45f0-be8c-24398daf081e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295797505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.1295797505
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all_with_rand_reset.2093433367
Short name T36
Test name
Test status
Simulation time 57330247201 ps
CPU time 593.96 seconds
Started Jul 27 05:10:13 PM PDT 24
Finished Jul 27 05:20:07 PM PDT 24
Peak memory 206444 kb
Host smart-c9de9361-c5de-42f3-8fd1-a2309794b9d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093433367 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all_with_rand_reset.2093433367
Directory /workspace/46.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.4167769412
Short name T115
Test name
Test status
Simulation time 144748344629 ps
CPU time 218.24 seconds
Started Jul 27 05:10:18 PM PDT 24
Finished Jul 27 05:13:56 PM PDT 24
Peak memory 183528 kb
Host smart-6cae05c8-ee66-4180-b172-c9a2791b7291
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167769412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.4167769412
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.183003572
Short name T373
Test name
Test status
Simulation time 77379097124 ps
CPU time 110.98 seconds
Started Jul 27 05:10:17 PM PDT 24
Finished Jul 27 05:12:09 PM PDT 24
Peak memory 183540 kb
Host smart-9718a4a3-21ec-41e4-9d60-e5bf3b92e23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183003572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.183003572
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.453353905
Short name T232
Test name
Test status
Simulation time 916071745651 ps
CPU time 415 seconds
Started Jul 27 05:10:16 PM PDT 24
Finished Jul 27 05:17:11 PM PDT 24
Peak memory 191628 kb
Host smart-1eae4a03-9785-432a-873c-f0dc42b4e29c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453353905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.453353905
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.646513720
Short name T110
Test name
Test status
Simulation time 51838494284 ps
CPU time 443.1 seconds
Started Jul 27 05:10:17 PM PDT 24
Finished Jul 27 05:17:41 PM PDT 24
Peak memory 191748 kb
Host smart-6e1ce36e-1025-47c7-91bc-7359c2a13f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646513720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.646513720
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.976944254
Short name T237
Test name
Test status
Simulation time 441610929910 ps
CPU time 372.4 seconds
Started Jul 27 05:10:17 PM PDT 24
Finished Jul 27 05:16:30 PM PDT 24
Peak memory 183508 kb
Host smart-5fb32055-cc85-4d68-b165-da2ffcf2d959
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976944254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.rv_timer_cfg_update_on_fly.976944254
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.818193623
Short name T446
Test name
Test status
Simulation time 41721082455 ps
CPU time 49.86 seconds
Started Jul 27 05:10:22 PM PDT 24
Finished Jul 27 05:11:12 PM PDT 24
Peak memory 183556 kb
Host smart-6ed96c1c-187e-4e4d-bfd7-9a6dab56024d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818193623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.818193623
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.741755797
Short name T186
Test name
Test status
Simulation time 126555795428 ps
CPU time 66.55 seconds
Started Jul 27 05:10:15 PM PDT 24
Finished Jul 27 05:11:21 PM PDT 24
Peak memory 183552 kb
Host smart-868dd88a-be26-42e4-bf9d-7a03b81d0bdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741755797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.741755797
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.388002890
Short name T282
Test name
Test status
Simulation time 146197557409 ps
CPU time 942.04 seconds
Started Jul 27 05:10:17 PM PDT 24
Finished Jul 27 05:25:59 PM PDT 24
Peak memory 191732 kb
Host smart-9455dee2-3a45-4ac5-a9ad-e9601e68c125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388002890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.388002890
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all_with_rand_reset.1436540418
Short name T433
Test name
Test status
Simulation time 21547382011 ps
CPU time 185.41 seconds
Started Jul 27 05:10:19 PM PDT 24
Finished Jul 27 05:13:24 PM PDT 24
Peak memory 198244 kb
Host smart-14640eec-370f-4426-8244-01498cd144cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436540418 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all_with_rand_reset.1436540418
Directory /workspace/48.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.1696226263
Short name T51
Test name
Test status
Simulation time 520193090984 ps
CPU time 566.48 seconds
Started Jul 27 05:10:17 PM PDT 24
Finished Jul 27 05:19:43 PM PDT 24
Peak memory 183416 kb
Host smart-a9b05a2b-786b-480e-934e-3f256aa65f16
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696226263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.1696226263
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.3956857182
Short name T418
Test name
Test status
Simulation time 674024877896 ps
CPU time 277.65 seconds
Started Jul 27 05:10:16 PM PDT 24
Finished Jul 27 05:14:54 PM PDT 24
Peak memory 183428 kb
Host smart-3980e590-2a1c-493f-b4c4-2fc74120015c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956857182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.3956857182
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.4175021227
Short name T214
Test name
Test status
Simulation time 202491511360 ps
CPU time 354.9 seconds
Started Jul 27 05:10:14 PM PDT 24
Finished Jul 27 05:16:09 PM PDT 24
Peak memory 194268 kb
Host smart-38dbcc14-3835-4245-a42a-48efa303ae9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175021227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.4175021227
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.98189789
Short name T441
Test name
Test status
Simulation time 114620102657 ps
CPU time 87.98 seconds
Started Jul 27 05:10:15 PM PDT 24
Finished Jul 27 05:11:43 PM PDT 24
Peak memory 183472 kb
Host smart-318a9999-288e-49dd-a177-46d764279162
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98189789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all.98189789
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all_with_rand_reset.1887982044
Short name T39
Test name
Test status
Simulation time 81283274433 ps
CPU time 542.46 seconds
Started Jul 27 05:10:18 PM PDT 24
Finished Jul 27 05:19:21 PM PDT 24
Peak memory 206492 kb
Host smart-60f7a8a8-8b0e-4081-8e69-d8309bafcedf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887982044 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all_with_rand_reset.1887982044
Directory /workspace/49.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.3619803225
Short name T297
Test name
Test status
Simulation time 5317895975 ps
CPU time 9.42 seconds
Started Jul 27 05:09:28 PM PDT 24
Finished Jul 27 05:09:38 PM PDT 24
Peak memory 183496 kb
Host smart-d03d6668-a8c2-4f58-b845-c23b9034d9fb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619803225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.3619803225
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.2343917034
Short name T447
Test name
Test status
Simulation time 373897367405 ps
CPU time 144.78 seconds
Started Jul 27 05:09:26 PM PDT 24
Finished Jul 27 05:11:51 PM PDT 24
Peak memory 183572 kb
Host smart-1035a92f-e0ff-42b5-8ed7-19352cc83cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343917034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.2343917034
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.2245383687
Short name T126
Test name
Test status
Simulation time 263411212036 ps
CPU time 924.96 seconds
Started Jul 27 05:09:28 PM PDT 24
Finished Jul 27 05:24:54 PM PDT 24
Peak memory 191704 kb
Host smart-26bd7234-151c-4631-a135-33d745e72b9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245383687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.2245383687
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.3023071311
Short name T227
Test name
Test status
Simulation time 122224301505 ps
CPU time 183.09 seconds
Started Jul 27 05:09:34 PM PDT 24
Finished Jul 27 05:12:38 PM PDT 24
Peak memory 195468 kb
Host smart-749275ef-72a2-48f9-9d50-07b6083f8f7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023071311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
3023071311
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/50.rv_timer_random.1036264752
Short name T158
Test name
Test status
Simulation time 123264410838 ps
CPU time 199.64 seconds
Started Jul 27 05:10:17 PM PDT 24
Finished Jul 27 05:13:37 PM PDT 24
Peak memory 191712 kb
Host smart-3ea7a2a0-4e27-4a25-bd79-d90517cff56b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036264752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.1036264752
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.2749762579
Short name T156
Test name
Test status
Simulation time 230339157536 ps
CPU time 193.61 seconds
Started Jul 27 05:10:17 PM PDT 24
Finished Jul 27 05:13:30 PM PDT 24
Peak memory 191680 kb
Host smart-5f906b6f-e014-4563-969d-ada424502e73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749762579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.2749762579
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.3918762183
Short name T151
Test name
Test status
Simulation time 126782028947 ps
CPU time 279.31 seconds
Started Jul 27 05:10:18 PM PDT 24
Finished Jul 27 05:14:58 PM PDT 24
Peak memory 191640 kb
Host smart-2b8c281c-912a-4dc5-88e8-416df6e568ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918762183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.3918762183
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.3644843569
Short name T342
Test name
Test status
Simulation time 57731433790 ps
CPU time 95.52 seconds
Started Jul 27 05:10:17 PM PDT 24
Finished Jul 27 05:11:53 PM PDT 24
Peak memory 191712 kb
Host smart-52f6d27b-6339-4174-a9ff-a9117c722568
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644843569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.3644843569
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.2388635305
Short name T111
Test name
Test status
Simulation time 361390852967 ps
CPU time 232.77 seconds
Started Jul 27 05:10:18 PM PDT 24
Finished Jul 27 05:14:11 PM PDT 24
Peak memory 191632 kb
Host smart-256f1c1c-5212-4119-9c14-8f245be0dd3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388635305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.2388635305
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.302516202
Short name T184
Test name
Test status
Simulation time 35171258966 ps
CPU time 27.56 seconds
Started Jul 27 05:10:16 PM PDT 24
Finished Jul 27 05:10:44 PM PDT 24
Peak memory 191636 kb
Host smart-074ca943-0eae-40eb-a384-45d0e71fec59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302516202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.302516202
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.1330311882
Short name T3
Test name
Test status
Simulation time 145945804892 ps
CPU time 241.17 seconds
Started Jul 27 05:10:14 PM PDT 24
Finished Jul 27 05:14:15 PM PDT 24
Peak memory 191652 kb
Host smart-b681d6a1-d12d-4d7e-8c37-3089ade70b1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330311882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.1330311882
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.3711140218
Short name T287
Test name
Test status
Simulation time 394105936973 ps
CPU time 379.79 seconds
Started Jul 27 05:10:15 PM PDT 24
Finished Jul 27 05:16:35 PM PDT 24
Peak memory 194232 kb
Host smart-dde0c80a-c84f-4bf3-87d3-88c410945d5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711140218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.3711140218
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.2332501430
Short name T383
Test name
Test status
Simulation time 133003858181 ps
CPU time 97.61 seconds
Started Jul 27 05:09:27 PM PDT 24
Finished Jul 27 05:11:04 PM PDT 24
Peak memory 183440 kb
Host smart-a088ab2c-12fa-496a-b24b-83c349cf5f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332501430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.2332501430
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.847836020
Short name T226
Test name
Test status
Simulation time 107770160303 ps
CPU time 1546.28 seconds
Started Jul 27 05:09:29 PM PDT 24
Finished Jul 27 05:35:15 PM PDT 24
Peak memory 191716 kb
Host smart-dabb2c12-754c-4012-8c35-05713fdec214
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847836020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.847836020
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.1157730851
Short name T294
Test name
Test status
Simulation time 41502144191 ps
CPU time 75.21 seconds
Started Jul 27 05:09:36 PM PDT 24
Finished Jul 27 05:10:51 PM PDT 24
Peak memory 191708 kb
Host smart-e50b1b8f-1837-438b-8630-45118f058714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157730851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.1157730851
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.2349015457
Short name T425
Test name
Test status
Simulation time 46251083210 ps
CPU time 63.73 seconds
Started Jul 27 05:09:35 PM PDT 24
Finished Jul 27 05:10:39 PM PDT 24
Peak memory 183572 kb
Host smart-d3dacbb6-6ec0-4d95-9773-7fdd0fbb9e3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349015457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
2349015457
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/60.rv_timer_random.354575644
Short name T170
Test name
Test status
Simulation time 317989990832 ps
CPU time 104.48 seconds
Started Jul 27 05:10:17 PM PDT 24
Finished Jul 27 05:12:02 PM PDT 24
Peak memory 191620 kb
Host smart-f4736c00-a899-4252-8194-0af129358a1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354575644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.354575644
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.2231706609
Short name T412
Test name
Test status
Simulation time 7838768168 ps
CPU time 253.27 seconds
Started Jul 27 05:10:23 PM PDT 24
Finished Jul 27 05:14:36 PM PDT 24
Peak memory 183544 kb
Host smart-c9b7237b-5ab0-45e2-bbb6-0e16ae6a6cdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231706609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.2231706609
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.1805124503
Short name T209
Test name
Test status
Simulation time 324762166845 ps
CPU time 278.6 seconds
Started Jul 27 05:10:19 PM PDT 24
Finished Jul 27 05:14:57 PM PDT 24
Peak memory 191640 kb
Host smart-404f1852-94b8-45db-b439-72cdf5f83c42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805124503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.1805124503
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.43691924
Short name T346
Test name
Test status
Simulation time 142689317499 ps
CPU time 290.76 seconds
Started Jul 27 05:10:21 PM PDT 24
Finished Jul 27 05:15:12 PM PDT 24
Peak memory 191740 kb
Host smart-8aa2771d-84ca-4ca0-a10b-7852dcf38020
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43691924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.43691924
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.1090940931
Short name T183
Test name
Test status
Simulation time 518218744617 ps
CPU time 816.08 seconds
Started Jul 27 05:10:26 PM PDT 24
Finished Jul 27 05:24:02 PM PDT 24
Peak memory 191640 kb
Host smart-631cabea-f61c-4da5-ae5d-7ca211460034
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090940931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.1090940931
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.1895380410
Short name T432
Test name
Test status
Simulation time 992349591889 ps
CPU time 225.43 seconds
Started Jul 27 05:10:23 PM PDT 24
Finished Jul 27 05:14:08 PM PDT 24
Peak memory 193880 kb
Host smart-a18d6426-e3d4-48e7-934f-cb2a46e5f548
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895380410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.1895380410
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.526259727
Short name T144
Test name
Test status
Simulation time 178012411578 ps
CPU time 757.83 seconds
Started Jul 27 05:10:21 PM PDT 24
Finished Jul 27 05:22:59 PM PDT 24
Peak memory 191764 kb
Host smart-b6442161-894b-46ba-8429-b753013dd90f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526259727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.526259727
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.4206848358
Short name T449
Test name
Test status
Simulation time 214875794909 ps
CPU time 284.38 seconds
Started Jul 27 05:10:23 PM PDT 24
Finished Jul 27 05:15:07 PM PDT 24
Peak memory 192772 kb
Host smart-c004c911-13cb-4727-a368-61c78fd1ce07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206848358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.4206848358
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.353768896
Short name T230
Test name
Test status
Simulation time 142398282097 ps
CPU time 132.02 seconds
Started Jul 27 05:10:23 PM PDT 24
Finished Jul 27 05:12:35 PM PDT 24
Peak memory 191728 kb
Host smart-1fafba04-1862-4f0d-88e9-051607497b50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353768896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.353768896
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.837585865
Short name T54
Test name
Test status
Simulation time 196522025620 ps
CPU time 457.92 seconds
Started Jul 27 05:10:22 PM PDT 24
Finished Jul 27 05:18:01 PM PDT 24
Peak memory 191724 kb
Host smart-e3832d16-2bfe-4ea7-9115-b971127a4d04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837585865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.837585865
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.3090047901
Short name T55
Test name
Test status
Simulation time 366873182527 ps
CPU time 551.08 seconds
Started Jul 27 05:09:38 PM PDT 24
Finished Jul 27 05:18:49 PM PDT 24
Peak memory 183536 kb
Host smart-5d3d0532-c24f-4b64-9c6a-c103a7c51329
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090047901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.3090047901
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.722039920
Short name T394
Test name
Test status
Simulation time 83177547771 ps
CPU time 115.21 seconds
Started Jul 27 05:09:35 PM PDT 24
Finished Jul 27 05:11:31 PM PDT 24
Peak memory 183476 kb
Host smart-06f5e987-82e7-456c-8279-617191a13272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722039920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.722039920
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.2180094372
Short name T204
Test name
Test status
Simulation time 128586192437 ps
CPU time 60.09 seconds
Started Jul 27 05:09:41 PM PDT 24
Finished Jul 27 05:10:41 PM PDT 24
Peak memory 183456 kb
Host smart-83cee007-8855-42fa-bad1-321022de99e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180094372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.2180094372
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.2300835129
Short name T298
Test name
Test status
Simulation time 27149642453 ps
CPU time 23.86 seconds
Started Jul 27 05:09:36 PM PDT 24
Finished Jul 27 05:10:00 PM PDT 24
Peak memory 191720 kb
Host smart-b165b5e1-567a-4c91-b41a-1828f22245e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300835129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.2300835129
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.4290854746
Short name T155
Test name
Test status
Simulation time 81099385792 ps
CPU time 193.73 seconds
Started Jul 27 05:10:23 PM PDT 24
Finished Jul 27 05:13:37 PM PDT 24
Peak memory 191744 kb
Host smart-cf66bfbc-c0a6-4dd5-b1e3-cea1c2cfa8cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290854746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.4290854746
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.3263131034
Short name T101
Test name
Test status
Simulation time 133828443397 ps
CPU time 236.43 seconds
Started Jul 27 05:10:23 PM PDT 24
Finished Jul 27 05:14:19 PM PDT 24
Peak memory 191664 kb
Host smart-36a57547-a026-4ae3-9016-0457950c8f97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263131034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.3263131034
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.922098807
Short name T296
Test name
Test status
Simulation time 8638002502 ps
CPU time 14.77 seconds
Started Jul 27 05:10:21 PM PDT 24
Finished Jul 27 05:10:35 PM PDT 24
Peak memory 183544 kb
Host smart-95afde70-85dc-4bea-9e76-1aa899f9f3f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922098807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.922098807
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.2046154830
Short name T315
Test name
Test status
Simulation time 25745958741 ps
CPU time 28.9 seconds
Started Jul 27 05:10:24 PM PDT 24
Finished Jul 27 05:10:53 PM PDT 24
Peak memory 183532 kb
Host smart-4e6039bc-0ea8-4d6f-ac89-8ada340f4068
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046154830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.2046154830
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.1883448984
Short name T308
Test name
Test status
Simulation time 90568040221 ps
CPU time 83.89 seconds
Started Jul 27 05:10:24 PM PDT 24
Finished Jul 27 05:11:48 PM PDT 24
Peak memory 183436 kb
Host smart-52cb6387-1314-4fa3-9afd-b2b6bbe0f2b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883448984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.1883448984
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.3877104377
Short name T359
Test name
Test status
Simulation time 847869018326 ps
CPU time 195.08 seconds
Started Jul 27 05:10:24 PM PDT 24
Finished Jul 27 05:13:39 PM PDT 24
Peak memory 191680 kb
Host smart-0ed9d779-f302-4ad2-a87a-0b1b95166f77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877104377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.3877104377
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.2717849109
Short name T175
Test name
Test status
Simulation time 477745318367 ps
CPU time 898.62 seconds
Started Jul 27 05:10:22 PM PDT 24
Finished Jul 27 05:25:21 PM PDT 24
Peak memory 191764 kb
Host smart-d3f06069-a451-4f8b-b888-11963ea81b3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717849109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.2717849109
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.2242133512
Short name T100
Test name
Test status
Simulation time 145282762201 ps
CPU time 270.52 seconds
Started Jul 27 05:10:22 PM PDT 24
Finished Jul 27 05:14:52 PM PDT 24
Peak memory 191664 kb
Host smart-c851cccd-cc70-475e-88b5-99c2af009805
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242133512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.2242133512
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.3248919898
Short name T265
Test name
Test status
Simulation time 58850319769 ps
CPU time 101.48 seconds
Started Jul 27 05:10:23 PM PDT 24
Finished Jul 27 05:12:05 PM PDT 24
Peak memory 191732 kb
Host smart-308f9fae-6bac-4e2a-b1b3-55be1e8eb9ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248919898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.3248919898
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.1802688128
Short name T180
Test name
Test status
Simulation time 1697963778177 ps
CPU time 809.73 seconds
Started Jul 27 05:09:38 PM PDT 24
Finished Jul 27 05:23:08 PM PDT 24
Peak memory 183448 kb
Host smart-d8375df8-32b9-4381-817a-db64db8fbcaa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802688128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.1802688128
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_random.3578908721
Short name T252
Test name
Test status
Simulation time 96316706211 ps
CPU time 1352.17 seconds
Started Jul 27 05:09:39 PM PDT 24
Finished Jul 27 05:32:11 PM PDT 24
Peak memory 193880 kb
Host smart-4a5c748c-9539-4b22-89d2-fef8a28eb7d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578908721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.3578908721
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.2122828767
Short name T195
Test name
Test status
Simulation time 91338942089 ps
CPU time 68.7 seconds
Started Jul 27 05:09:36 PM PDT 24
Finished Jul 27 05:10:45 PM PDT 24
Peak memory 191748 kb
Host smart-e954a138-e18b-4d86-86c4-2977cfb92eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122828767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.2122828767
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.2458115451
Short name T391
Test name
Test status
Simulation time 1247698009062 ps
CPU time 216.84 seconds
Started Jul 27 05:09:37 PM PDT 24
Finished Jul 27 05:13:14 PM PDT 24
Peak memory 191716 kb
Host smart-0313b2e1-5b3a-4142-b7e0-a2b289419bfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458115451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
2458115451
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/80.rv_timer_random.2250984068
Short name T127
Test name
Test status
Simulation time 303287384281 ps
CPU time 285.99 seconds
Started Jul 27 05:10:24 PM PDT 24
Finished Jul 27 05:15:11 PM PDT 24
Peak memory 191632 kb
Host smart-c988eb86-40dd-4dda-8c39-08448634ffd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250984068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.2250984068
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.363226826
Short name T302
Test name
Test status
Simulation time 79022299963 ps
CPU time 48.49 seconds
Started Jul 27 05:10:26 PM PDT 24
Finished Jul 27 05:11:14 PM PDT 24
Peak memory 183432 kb
Host smart-465b5939-bae1-4c71-b3af-c9a0f19e4179
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363226826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.363226826
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.1608482012
Short name T97
Test name
Test status
Simulation time 118352672248 ps
CPU time 309.66 seconds
Started Jul 27 05:10:32 PM PDT 24
Finished Jul 27 05:15:42 PM PDT 24
Peak memory 191660 kb
Host smart-157551f5-f94a-4494-8f66-f6263420be32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608482012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.1608482012
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.4072140302
Short name T141
Test name
Test status
Simulation time 743760273593 ps
CPU time 376.21 seconds
Started Jul 27 05:10:33 PM PDT 24
Finished Jul 27 05:16:50 PM PDT 24
Peak memory 191648 kb
Host smart-6bad8af1-d5da-4266-80df-15d9032f1141
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072140302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.4072140302
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.2483052931
Short name T103
Test name
Test status
Simulation time 57282741436 ps
CPU time 80.03 seconds
Started Jul 27 05:10:33 PM PDT 24
Finished Jul 27 05:11:53 PM PDT 24
Peak memory 194172 kb
Host smart-e6a25b6b-c80b-4cf2-bb44-65814636f628
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483052931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.2483052931
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.3599916342
Short name T316
Test name
Test status
Simulation time 265712040732 ps
CPU time 140.34 seconds
Started Jul 27 05:10:33 PM PDT 24
Finished Jul 27 05:12:54 PM PDT 24
Peak memory 191724 kb
Host smart-35fdd0a3-5e2f-43b1-8837-c61bc1ecae8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599916342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.3599916342
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.1682204842
Short name T289
Test name
Test status
Simulation time 71281946933 ps
CPU time 113.72 seconds
Started Jul 27 05:10:32 PM PDT 24
Finished Jul 27 05:12:26 PM PDT 24
Peak memory 191736 kb
Host smart-1b47735a-ead9-41b7-ae4f-46715bdb8cc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682204842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.1682204842
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.2487775634
Short name T255
Test name
Test status
Simulation time 131661879331 ps
CPU time 56.41 seconds
Started Jul 27 05:10:33 PM PDT 24
Finished Jul 27 05:11:30 PM PDT 24
Peak memory 183464 kb
Host smart-e1d45ad2-9718-4f07-9333-fb0a480d5fe8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487775634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.2487775634
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.4243573142
Short name T134
Test name
Test status
Simulation time 625117945044 ps
CPU time 535.09 seconds
Started Jul 27 05:09:41 PM PDT 24
Finished Jul 27 05:18:36 PM PDT 24
Peak memory 183448 kb
Host smart-69d52d2c-68a8-4ba8-9212-74d35ff9c73a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243573142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.4243573142
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.1055396312
Short name T392
Test name
Test status
Simulation time 39639241220 ps
CPU time 58.04 seconds
Started Jul 27 05:09:40 PM PDT 24
Finished Jul 27 05:10:38 PM PDT 24
Peak memory 183560 kb
Host smart-a2c0ece3-cbab-44c5-9c4e-14ce1cf351b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055396312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.1055396312
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.973589159
Short name T264
Test name
Test status
Simulation time 178728157698 ps
CPU time 198.01 seconds
Started Jul 27 05:09:35 PM PDT 24
Finished Jul 27 05:12:53 PM PDT 24
Peak memory 194024 kb
Host smart-9b645f48-b58c-40b9-a240-926391683a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973589159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.973589159
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.4279056758
Short name T291
Test name
Test status
Simulation time 1161990126792 ps
CPU time 825.74 seconds
Started Jul 27 05:09:38 PM PDT 24
Finished Jul 27 05:23:24 PM PDT 24
Peak memory 196132 kb
Host smart-fb36a286-944a-4f73-92a3-4e2f82adbebf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279056758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
4279056758
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all_with_rand_reset.2121401469
Short name T450
Test name
Test status
Simulation time 1038043765091 ps
CPU time 1025.04 seconds
Started Jul 27 05:09:38 PM PDT 24
Finished Jul 27 05:26:43 PM PDT 24
Peak memory 213128 kb
Host smart-b8b97bdb-4c7e-4b88-b717-ba404056d26d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121401469 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all_with_rand_reset.2121401469
Directory /workspace/9.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.1556722568
Short name T231
Test name
Test status
Simulation time 271608379005 ps
CPU time 322.38 seconds
Started Jul 27 05:10:33 PM PDT 24
Finished Jul 27 05:15:55 PM PDT 24
Peak memory 191752 kb
Host smart-34da7c4d-6a03-4f05-811d-f3767a0bfce2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556722568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.1556722568
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.88556517
Short name T145
Test name
Test status
Simulation time 128804702472 ps
CPU time 232.53 seconds
Started Jul 27 05:10:33 PM PDT 24
Finished Jul 27 05:14:25 PM PDT 24
Peak memory 191656 kb
Host smart-82a8d3cc-c7a4-410a-a022-15dcda6b0ac2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88556517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.88556517
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.2297653575
Short name T113
Test name
Test status
Simulation time 399809359265 ps
CPU time 1052.16 seconds
Started Jul 27 05:10:32 PM PDT 24
Finished Jul 27 05:28:05 PM PDT 24
Peak memory 191736 kb
Host smart-7b5cd89e-8bd1-4243-a2ca-2ea8197711a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297653575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.2297653575
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.666933759
Short name T236
Test name
Test status
Simulation time 23938272186 ps
CPU time 38.46 seconds
Started Jul 27 05:10:34 PM PDT 24
Finished Jul 27 05:11:12 PM PDT 24
Peak memory 183512 kb
Host smart-c1a1ac4a-954f-493a-a39c-549709f9d816
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666933759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.666933759
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.3069069662
Short name T207
Test name
Test status
Simulation time 302420519145 ps
CPU time 351.47 seconds
Started Jul 27 05:10:35 PM PDT 24
Finished Jul 27 05:16:26 PM PDT 24
Peak memory 191712 kb
Host smart-6541a775-b801-479d-bc1e-8b685505cdb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069069662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.3069069662
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.1822014968
Short name T318
Test name
Test status
Simulation time 5247372511 ps
CPU time 3.86 seconds
Started Jul 27 05:10:43 PM PDT 24
Finished Jul 27 05:10:47 PM PDT 24
Peak memory 183360 kb
Host smart-10faf0fc-5fe8-4933-b68b-37559eea9092
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822014968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.1822014968
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.4019712266
Short name T163
Test name
Test status
Simulation time 111184404698 ps
CPU time 216.01 seconds
Started Jul 27 05:10:44 PM PDT 24
Finished Jul 27 05:14:20 PM PDT 24
Peak memory 191736 kb
Host smart-fddf80c7-ec58-4cb4-a804-428a34080723
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019712266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.4019712266
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.3987163432
Short name T217
Test name
Test status
Simulation time 208742857905 ps
CPU time 1014.72 seconds
Started Jul 27 05:10:44 PM PDT 24
Finished Jul 27 05:27:39 PM PDT 24
Peak memory 191712 kb
Host smart-f6e33427-c140-456a-be56-2c5787d0ee4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987163432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.3987163432
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.1832968586
Short name T124
Test name
Test status
Simulation time 596421740212 ps
CPU time 488.61 seconds
Started Jul 27 05:10:42 PM PDT 24
Finished Jul 27 05:18:50 PM PDT 24
Peak memory 191764 kb
Host smart-896d6dce-a56f-4ecb-be94-71d3e04ab703
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832968586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.1832968586
Directory /workspace/99.rv_timer_random/latest
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