Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.55 99.36 98.73 100.00 100.00 100.00 99.21


Total test records in report: 578
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T506 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2861135561 Jul 28 04:24:44 PM PDT 24 Jul 28 04:24:45 PM PDT 24 38608785 ps
T507 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.2438928956 Jul 28 04:21:49 PM PDT 24 Jul 28 04:21:50 PM PDT 24 23955650 ps
T88 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.3466453479 Jul 28 04:28:40 PM PDT 24 Jul 28 04:28:40 PM PDT 24 40730051 ps
T508 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.131866366 Jul 28 04:21:29 PM PDT 24 Jul 28 04:21:30 PM PDT 24 63950972 ps
T509 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.111770941 Jul 28 04:22:27 PM PDT 24 Jul 28 04:22:27 PM PDT 24 47938666 ps
T510 /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.3536104271 Jul 28 04:28:46 PM PDT 24 Jul 28 04:28:46 PM PDT 24 34264621 ps
T89 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.224954512 Jul 28 04:20:28 PM PDT 24 Jul 28 04:20:28 PM PDT 24 21870972 ps
T511 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1705675068 Jul 28 04:28:48 PM PDT 24 Jul 28 04:28:49 PM PDT 24 23499714 ps
T512 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.2668520964 Jul 28 04:28:53 PM PDT 24 Jul 28 04:28:54 PM PDT 24 52534838 ps
T513 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.1902614252 Jul 28 04:28:45 PM PDT 24 Jul 28 04:28:46 PM PDT 24 51806935 ps
T514 /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.1861598598 Jul 28 04:24:37 PM PDT 24 Jul 28 04:24:38 PM PDT 24 81266344 ps
T515 /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.1546844534 Jul 28 04:20:31 PM PDT 24 Jul 28 04:20:33 PM PDT 24 39817798 ps
T516 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.52888274 Jul 28 04:28:48 PM PDT 24 Jul 28 04:28:49 PM PDT 24 22394480 ps
T517 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.1066689790 Jul 28 04:24:54 PM PDT 24 Jul 28 04:24:55 PM PDT 24 104468156 ps
T518 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.909305365 Jul 28 04:21:47 PM PDT 24 Jul 28 04:21:48 PM PDT 24 215137927 ps
T519 /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.545971685 Jul 28 04:25:33 PM PDT 24 Jul 28 04:25:35 PM PDT 24 171609989 ps
T520 /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.2944986315 Jul 28 04:24:54 PM PDT 24 Jul 28 04:24:55 PM PDT 24 60321720 ps
T521 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.4267924976 Jul 28 04:28:39 PM PDT 24 Jul 28 04:28:40 PM PDT 24 34259008 ps
T522 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.2338590113 Jul 28 04:24:53 PM PDT 24 Jul 28 04:24:54 PM PDT 24 20015486 ps
T523 /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.3714828054 Jul 28 04:28:36 PM PDT 24 Jul 28 04:28:42 PM PDT 24 182023314 ps
T524 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.1618802402 Jul 28 04:28:38 PM PDT 24 Jul 28 04:28:41 PM PDT 24 353621374 ps
T525 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.3739833976 Jul 28 04:28:47 PM PDT 24 Jul 28 04:28:48 PM PDT 24 42936529 ps
T526 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.1741723448 Jul 28 04:21:06 PM PDT 24 Jul 28 04:21:06 PM PDT 24 23511199 ps
T527 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.3370168212 Jul 28 04:28:51 PM PDT 24 Jul 28 04:28:52 PM PDT 24 19301486 ps
T528 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2654203209 Jul 28 04:24:53 PM PDT 24 Jul 28 04:24:54 PM PDT 24 15588972 ps
T529 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.3941318245 Jul 28 04:28:40 PM PDT 24 Jul 28 04:28:42 PM PDT 24 82343822 ps
T530 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.1059695343 Jul 28 04:28:45 PM PDT 24 Jul 28 04:28:47 PM PDT 24 39374891 ps
T531 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.643597917 Jul 28 04:28:51 PM PDT 24 Jul 28 04:28:51 PM PDT 24 15821243 ps
T532 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.1070090325 Jul 28 04:24:48 PM PDT 24 Jul 28 04:24:49 PM PDT 24 27373067 ps
T533 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.3590616871 Jul 28 04:28:50 PM PDT 24 Jul 28 04:28:51 PM PDT 24 20087575 ps
T534 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.2179847246 Jul 28 04:28:36 PM PDT 24 Jul 28 04:28:37 PM PDT 24 25246854 ps
T535 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.76854919 Jul 28 04:22:00 PM PDT 24 Jul 28 04:22:01 PM PDT 24 22823644 ps
T536 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.1074858754 Jul 28 04:29:03 PM PDT 24 Jul 28 04:29:06 PM PDT 24 313911877 ps
T537 /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.266876279 Jul 28 04:21:04 PM PDT 24 Jul 28 04:21:05 PM PDT 24 34206317 ps
T538 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.621725575 Jul 28 04:28:37 PM PDT 24 Jul 28 04:28:39 PM PDT 24 217175824 ps
T539 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2005888923 Jul 28 04:28:40 PM PDT 24 Jul 28 04:28:41 PM PDT 24 188262679 ps
T540 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.541420457 Jul 28 04:28:43 PM PDT 24 Jul 28 04:28:45 PM PDT 24 896740972 ps
T541 /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.2900111612 Jul 28 04:23:26 PM PDT 24 Jul 28 04:23:27 PM PDT 24 59568743 ps
T542 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.3788942722 Jul 28 04:28:48 PM PDT 24 Jul 28 04:28:49 PM PDT 24 50414104 ps
T543 /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.919224022 Jul 28 04:28:37 PM PDT 24 Jul 28 04:28:39 PM PDT 24 144955010 ps
T544 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.4169624285 Jul 28 04:28:42 PM PDT 24 Jul 28 04:28:43 PM PDT 24 22090993 ps
T545 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.1357178683 Jul 28 04:21:14 PM PDT 24 Jul 28 04:21:15 PM PDT 24 36654355 ps
T92 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2165386443 Jul 28 04:28:41 PM PDT 24 Jul 28 04:28:42 PM PDT 24 43496269 ps
T546 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3127551848 Jul 28 04:28:41 PM PDT 24 Jul 28 04:28:42 PM PDT 24 18988556 ps
T547 /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.886279803 Jul 28 04:28:51 PM PDT 24 Jul 28 04:28:51 PM PDT 24 16560579 ps
T548 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1172225070 Jul 28 04:28:52 PM PDT 24 Jul 28 04:28:53 PM PDT 24 112742102 ps
T549 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.647017559 Jul 28 04:22:13 PM PDT 24 Jul 28 04:22:14 PM PDT 24 139722052 ps
T550 /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.2103076375 Jul 28 04:25:15 PM PDT 24 Jul 28 04:25:16 PM PDT 24 63497291 ps
T551 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.3967026460 Jul 28 04:25:32 PM PDT 24 Jul 28 04:25:33 PM PDT 24 609611470 ps
T552 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.3419045073 Jul 28 04:28:55 PM PDT 24 Jul 28 04:28:56 PM PDT 24 14610341 ps
T553 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.2619383374 Jul 28 04:28:41 PM PDT 24 Jul 28 04:28:43 PM PDT 24 236009090 ps
T90 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.3816793940 Jul 28 04:20:25 PM PDT 24 Jul 28 04:20:26 PM PDT 24 34345038 ps
T554 /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.2016027551 Jul 28 04:24:48 PM PDT 24 Jul 28 04:24:49 PM PDT 24 42099770 ps
T555 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.3621659546 Jul 28 04:23:11 PM PDT 24 Jul 28 04:23:12 PM PDT 24 22798732 ps
T556 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1477161350 Jul 28 04:24:44 PM PDT 24 Jul 28 04:24:45 PM PDT 24 13645070 ps
T557 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1795715417 Jul 28 04:20:27 PM PDT 24 Jul 28 04:20:31 PM PDT 24 1622317553 ps
T558 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.1452258801 Jul 28 04:20:17 PM PDT 24 Jul 28 04:20:18 PM PDT 24 84101454 ps
T559 /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.3652209747 Jul 28 04:28:41 PM PDT 24 Jul 28 04:28:41 PM PDT 24 87495138 ps
T560 /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.4112997902 Jul 28 04:28:42 PM PDT 24 Jul 28 04:28:42 PM PDT 24 18062072 ps
T561 /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3758152604 Jul 28 04:28:58 PM PDT 24 Jul 28 04:28:58 PM PDT 24 114847251 ps
T562 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.3755492344 Jul 28 04:20:30 PM PDT 24 Jul 28 04:20:31 PM PDT 24 32670466 ps
T563 /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.804972154 Jul 28 04:28:55 PM PDT 24 Jul 28 04:28:56 PM PDT 24 44159790 ps
T564 /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.542757172 Jul 28 04:21:38 PM PDT 24 Jul 28 04:21:39 PM PDT 24 28388182 ps
T91 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.523262258 Jul 28 04:21:50 PM PDT 24 Jul 28 04:21:51 PM PDT 24 26015946 ps
T565 /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.94747323 Jul 28 04:25:27 PM PDT 24 Jul 28 04:25:28 PM PDT 24 27901358 ps
T566 /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.615694617 Jul 28 04:28:38 PM PDT 24 Jul 28 04:28:40 PM PDT 24 113868266 ps
T567 /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.345902567 Jul 28 04:28:41 PM PDT 24 Jul 28 04:28:42 PM PDT 24 54430494 ps
T568 /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.1551975021 Jul 28 04:24:56 PM PDT 24 Jul 28 04:24:57 PM PDT 24 90073586 ps
T569 /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.2908928922 Jul 28 04:24:58 PM PDT 24 Jul 28 04:25:00 PM PDT 24 85329274 ps
T570 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1004128416 Jul 28 04:28:43 PM PDT 24 Jul 28 04:28:44 PM PDT 24 80934142 ps
T571 /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.107847501 Jul 28 04:28:43 PM PDT 24 Jul 28 04:28:44 PM PDT 24 84649877 ps
T572 /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3607182509 Jul 28 04:28:39 PM PDT 24 Jul 28 04:28:40 PM PDT 24 14337330 ps
T573 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1149281329 Jul 28 04:24:51 PM PDT 24 Jul 28 04:24:52 PM PDT 24 30804102 ps
T574 /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3675410969 Jul 28 04:28:38 PM PDT 24 Jul 28 04:28:40 PM PDT 24 34977863 ps
T575 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.36015991 Jul 28 04:25:15 PM PDT 24 Jul 28 04:25:17 PM PDT 24 69544059 ps
T576 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1280795476 Jul 28 04:28:41 PM PDT 24 Jul 28 04:28:42 PM PDT 24 14108979 ps
T577 /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.992704819 Jul 28 04:29:05 PM PDT 24 Jul 28 04:29:06 PM PDT 24 18433127 ps
T578 /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.2291066951 Jul 28 04:22:24 PM PDT 24 Jul 28 04:22:25 PM PDT 24 22600667 ps

Test location /workspace/coverage/default/73.rv_timer_random.3689446656
Short name T10
Test name
Test status
Simulation time 23011265542 ps
CPU time 29.19 seconds
Started Jul 28 04:29:32 PM PDT 24
Finished Jul 28 04:30:01 PM PDT 24
Peak memory 183336 kb
Host smart-c1eeeb78-96c3-408b-8f70-c83a417d316f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689446656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.3689446656
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all_with_rand_reset.1039911413
Short name T12
Test name
Test status
Simulation time 79135758712 ps
CPU time 824.07 seconds
Started Jul 28 04:23:18 PM PDT 24
Finished Jul 28 04:37:02 PM PDT 24
Peak memory 210876 kb
Host smart-4e25f56d-be07-4cdc-bf3c-48022ab90cd4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039911413 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all_with_rand_reset.1039911413
Directory /workspace/5.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.rv_timer_random.3818824704
Short name T4
Test name
Test status
Simulation time 1728088081848 ps
CPU time 488.72 seconds
Started Jul 28 04:29:32 PM PDT 24
Finished Jul 28 04:37:41 PM PDT 24
Peak memory 194020 kb
Host smart-5ca16513-93af-45ee-959a-d30c450c554d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818824704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.3818824704
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.235994379
Short name T29
Test name
Test status
Simulation time 95889324 ps
CPU time 1.04 seconds
Started Jul 28 04:25:05 PM PDT 24
Finished Jul 28 04:25:07 PM PDT 24
Peak memory 194808 kb
Host smart-83f52868-6cf7-4213-956f-05764eaeedba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235994379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_int
g_err.235994379
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.3977401501
Short name T178
Test name
Test status
Simulation time 992731013420 ps
CPU time 2870.4 seconds
Started Jul 28 04:30:40 PM PDT 24
Finished Jul 28 05:18:31 PM PDT 24
Peak memory 191284 kb
Host smart-bd7836da-a577-449e-a159-13d9d402c094
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977401501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.3977401501
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.2592730324
Short name T179
Test name
Test status
Simulation time 1459220346577 ps
CPU time 1630.2 seconds
Started Jul 28 04:29:23 PM PDT 24
Finished Jul 28 04:56:33 PM PDT 24
Peak memory 191552 kb
Host smart-5b4a3072-0f80-448d-99b1-ce851762bffb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592730324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.2592730324
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.1727995032
Short name T65
Test name
Test status
Simulation time 648892562398 ps
CPU time 1503.83 seconds
Started Jul 28 04:29:19 PM PDT 24
Finished Jul 28 04:54:23 PM PDT 24
Peak memory 196896 kb
Host smart-1df547b4-9dbb-4dee-9328-18d1b346c800
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727995032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.1727995032
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.4100759428
Short name T246
Test name
Test status
Simulation time 3136964925826 ps
CPU time 4998.64 seconds
Started Jul 28 04:22:12 PM PDT 24
Finished Jul 28 05:45:32 PM PDT 24
Peak memory 191556 kb
Host smart-edd9ae0e-1041-4063-8762-cdf3e18a7ef1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100759428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
4100759428
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.2235727277
Short name T61
Test name
Test status
Simulation time 988450098238 ps
CPU time 1358.6 seconds
Started Jul 28 04:29:18 PM PDT 24
Finished Jul 28 04:51:57 PM PDT 24
Peak memory 191512 kb
Host smart-8c0ab5b6-37a0-4968-90b7-f1393cb98cbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235727277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.2235727277
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.2511275568
Short name T221
Test name
Test status
Simulation time 709860625500 ps
CPU time 927.55 seconds
Started Jul 28 04:29:24 PM PDT 24
Finished Jul 28 04:44:52 PM PDT 24
Peak memory 197052 kb
Host smart-7b8b55b6-76c1-4151-8ebc-cf258e163332
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511275568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.2511275568
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.2689101300
Short name T169
Test name
Test status
Simulation time 3839887668225 ps
CPU time 7214.02 seconds
Started Jul 28 04:29:15 PM PDT 24
Finished Jul 28 06:29:30 PM PDT 24
Peak memory 191536 kb
Host smart-41dd5c30-1103-42f0-8762-57680a9e9593
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689101300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.2689101300
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.4005484165
Short name T305
Test name
Test status
Simulation time 1059021545622 ps
CPU time 2021.73 seconds
Started Jul 28 04:29:13 PM PDT 24
Finished Jul 28 05:02:55 PM PDT 24
Peak memory 191508 kb
Host smart-bd5130bb-f002-425f-ab14-c575d6637628
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005484165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.4005484165
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/125.rv_timer_random.298640935
Short name T114
Test name
Test status
Simulation time 129621141740 ps
CPU time 542.46 seconds
Started Jul 28 04:29:50 PM PDT 24
Finished Jul 28 04:38:53 PM PDT 24
Peak memory 191516 kb
Host smart-3066db32-83ee-41c3-9f07-b45f23d8050a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298640935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.298640935
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.3736696091
Short name T67
Test name
Test status
Simulation time 330302149747 ps
CPU time 1088.56 seconds
Started Jul 28 04:29:23 PM PDT 24
Finished Jul 28 04:47:32 PM PDT 24
Peak memory 196200 kb
Host smart-b1b49f17-befe-4e86-affd-7735df50ea1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736696091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.3736696091
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.1300211753
Short name T15
Test name
Test status
Simulation time 58705948 ps
CPU time 0.86 seconds
Started Jul 28 04:24:53 PM PDT 24
Finished Jul 28 04:24:54 PM PDT 24
Peak memory 212716 kb
Host smart-72beec0a-b2b0-48e6-a2d8-39688f98fb6d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300211753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.1300211753
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/147.rv_timer_random.1216747460
Short name T135
Test name
Test status
Simulation time 123454415341 ps
CPU time 1896.03 seconds
Started Jul 28 04:29:43 PM PDT 24
Finished Jul 28 05:01:19 PM PDT 24
Peak memory 191524 kb
Host smart-35257ce0-7548-4198-a9ab-39e922ec003d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216747460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.1216747460
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.2595786168
Short name T131
Test name
Test status
Simulation time 124569523853 ps
CPU time 738.17 seconds
Started Jul 28 04:29:42 PM PDT 24
Finished Jul 28 04:42:00 PM PDT 24
Peak memory 191516 kb
Host smart-e914e60f-a24b-4136-b80b-1a30d5dac66f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595786168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.2595786168
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.1632753167
Short name T63
Test name
Test status
Simulation time 1008719369912 ps
CPU time 1188.55 seconds
Started Jul 28 04:29:06 PM PDT 24
Finished Jul 28 04:48:55 PM PDT 24
Peak memory 191608 kb
Host smart-9e77c9eb-b65b-41b4-b80c-912f9703f63f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632753167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.1632753167
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.2148307294
Short name T185
Test name
Test status
Simulation time 1580974665426 ps
CPU time 3369.16 seconds
Started Jul 28 04:29:08 PM PDT 24
Finished Jul 28 05:25:17 PM PDT 24
Peak memory 191552 kb
Host smart-b16e9308-4b39-4e43-80fd-578d5712f834
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148307294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.2148307294
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.1150759046
Short name T157
Test name
Test status
Simulation time 265893421836 ps
CPU time 146.81 seconds
Started Jul 28 04:24:49 PM PDT 24
Finished Jul 28 04:27:16 PM PDT 24
Peak memory 181936 kb
Host smart-8431a9b2-fcff-4cce-ba5c-a27efe6ecd01
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150759046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.1150759046
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.3972874638
Short name T70
Test name
Test status
Simulation time 394240103670 ps
CPU time 675.85 seconds
Started Jul 28 04:23:04 PM PDT 24
Finished Jul 28 04:34:20 PM PDT 24
Peak memory 183312 kb
Host smart-862e20a4-d20e-4651-a65f-e200e887a462
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972874638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.3972874638
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.4154441258
Short name T68
Test name
Test status
Simulation time 4016785609512 ps
CPU time 998.58 seconds
Started Jul 28 04:29:02 PM PDT 24
Finished Jul 28 04:45:41 PM PDT 24
Peak memory 191572 kb
Host smart-35ebb07d-f2e0-4269-8ce8-7adf7d6b75cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154441258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.4154441258
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.2591263119
Short name T69
Test name
Test status
Simulation time 1539811043990 ps
CPU time 1791.19 seconds
Started Jul 28 04:29:24 PM PDT 24
Finished Jul 28 04:59:15 PM PDT 24
Peak memory 191648 kb
Host smart-c53813ce-ae9c-406d-b954-2fb0ffed0fdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591263119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.2591263119
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_random.2379795160
Short name T116
Test name
Test status
Simulation time 143156492697 ps
CPU time 239.77 seconds
Started Jul 28 04:23:00 PM PDT 24
Finished Jul 28 04:27:00 PM PDT 24
Peak memory 194604 kb
Host smart-e72c488f-e8db-42d3-a103-c9764c6d4d82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379795160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.2379795160
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.3198737996
Short name T283
Test name
Test status
Simulation time 372918696924 ps
CPU time 1169.68 seconds
Started Jul 28 04:29:55 PM PDT 24
Finished Jul 28 04:49:25 PM PDT 24
Peak memory 191560 kb
Host smart-f972f7f4-32b4-41ff-aeed-065451291b5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198737996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.3198737996
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.2484078611
Short name T208
Test name
Test status
Simulation time 323651046037 ps
CPU time 948.27 seconds
Started Jul 28 04:29:31 PM PDT 24
Finished Jul 28 04:45:20 PM PDT 24
Peak memory 191548 kb
Host smart-0b5c71d8-4bc6-4bb6-8991-fb231a5abf05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484078611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.2484078611
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/160.rv_timer_random.2858739277
Short name T9
Test name
Test status
Simulation time 147989885236 ps
CPU time 1782.19 seconds
Started Jul 28 04:29:46 PM PDT 24
Finished Jul 28 04:59:28 PM PDT 24
Peak memory 183316 kb
Host smart-2239dc93-e44e-49be-a21a-c8825b24f5a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858739277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.2858739277
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.3253583455
Short name T118
Test name
Test status
Simulation time 508702940844 ps
CPU time 655.03 seconds
Started Jul 28 04:29:48 PM PDT 24
Finished Jul 28 04:40:43 PM PDT 24
Peak memory 191584 kb
Host smart-cebed3c6-456d-4b5e-999a-530b9745f0e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253583455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.3253583455
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.3569403377
Short name T237
Test name
Test status
Simulation time 896434424029 ps
CPU time 435.71 seconds
Started Jul 28 04:23:45 PM PDT 24
Finished Jul 28 04:31:01 PM PDT 24
Peak memory 191672 kb
Host smart-f01ef315-db32-41ac-a600-9c28c656f1d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569403377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
3569403377
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.600802820
Short name T86
Test name
Test status
Simulation time 13147088 ps
CPU time 0.56 seconds
Started Jul 28 04:28:40 PM PDT 24
Finished Jul 28 04:28:41 PM PDT 24
Peak memory 182764 kb
Host smart-833aabb5-824f-49a6-bead-d16e002305c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600802820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.600802820
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/115.rv_timer_random.4227352081
Short name T106
Test name
Test status
Simulation time 551050677793 ps
CPU time 487.99 seconds
Started Jul 28 04:29:40 PM PDT 24
Finished Jul 28 04:37:48 PM PDT 24
Peak memory 191556 kb
Host smart-24c1de3e-840c-485b-b6a8-dd3bf977e55d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227352081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.4227352081
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.1685419722
Short name T300
Test name
Test status
Simulation time 1108046798154 ps
CPU time 389.74 seconds
Started Jul 28 04:29:32 PM PDT 24
Finished Jul 28 04:36:02 PM PDT 24
Peak memory 191540 kb
Host smart-35bc3f19-3e2a-4b7d-ba0d-484697adaa88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685419722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.1685419722
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.486436039
Short name T146
Test name
Test status
Simulation time 403600372891 ps
CPU time 585.96 seconds
Started Jul 28 04:29:33 PM PDT 24
Finished Jul 28 04:39:19 PM PDT 24
Peak memory 191568 kb
Host smart-4e53d0c0-c85a-4817-9cc2-81b146872b51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486436039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.486436039
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.1555852902
Short name T60
Test name
Test status
Simulation time 2493375238754 ps
CPU time 1502.42 seconds
Started Jul 28 04:29:20 PM PDT 24
Finished Jul 28 04:54:23 PM PDT 24
Peak memory 191540 kb
Host smart-1223219a-63d9-4265-a8d5-9a7d0c9606ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555852902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.1555852902
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.3369603596
Short name T230
Test name
Test status
Simulation time 978002433133 ps
CPU time 1079.99 seconds
Started Jul 28 04:29:14 PM PDT 24
Finished Jul 28 04:47:14 PM PDT 24
Peak memory 196012 kb
Host smart-95afbbee-04d5-4539-a543-0a2d1731ff9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369603596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.3369603596
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/84.rv_timer_random.2550208340
Short name T155
Test name
Test status
Simulation time 116519256880 ps
CPU time 329.06 seconds
Started Jul 28 04:29:32 PM PDT 24
Finished Jul 28 04:35:01 PM PDT 24
Peak memory 191592 kb
Host smart-03f70c9c-ad28-411e-85ca-cd181ff62f6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550208340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.2550208340
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.3422541187
Short name T71
Test name
Test status
Simulation time 446170240287 ps
CPU time 240.34 seconds
Started Jul 28 04:29:37 PM PDT 24
Finished Jul 28 04:33:38 PM PDT 24
Peak memory 191552 kb
Host smart-6f48d750-cd2b-47f3-932b-b7260d890983
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422541187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.3422541187
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.3112284297
Short name T314
Test name
Test status
Simulation time 465773131347 ps
CPU time 252.71 seconds
Started Jul 28 04:29:51 PM PDT 24
Finished Jul 28 04:34:04 PM PDT 24
Peak memory 191564 kb
Host smart-b00677ab-3d23-426a-99dc-cede7dd85b78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112284297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.3112284297
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.2052254210
Short name T164
Test name
Test status
Simulation time 153734160523 ps
CPU time 189.49 seconds
Started Jul 28 04:29:46 PM PDT 24
Finished Jul 28 04:32:55 PM PDT 24
Peak memory 191560 kb
Host smart-dc2d4376-5bca-484c-b358-c63871c56be9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052254210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.2052254210
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random.2279469489
Short name T269
Test name
Test status
Simulation time 66317209106 ps
CPU time 121.42 seconds
Started Jul 28 04:29:06 PM PDT 24
Finished Jul 28 04:31:07 PM PDT 24
Peak memory 191504 kb
Host smart-5299ebae-8737-49b1-8504-a5c47182a478
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279469489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.2279469489
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random.139053361
Short name T153
Test name
Test status
Simulation time 167156527254 ps
CPU time 881.9 seconds
Started Jul 28 04:29:20 PM PDT 24
Finished Jul 28 04:44:02 PM PDT 24
Peak memory 191604 kb
Host smart-10da8b23-0503-4e69-bb82-b7e19af1acb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139053361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.139053361
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.3430453520
Short name T272
Test name
Test status
Simulation time 1428366958188 ps
CPU time 632.77 seconds
Started Jul 28 04:29:28 PM PDT 24
Finished Jul 28 04:40:01 PM PDT 24
Peak memory 191560 kb
Host smart-7cb998c6-c1d9-4d78-b3db-06ee3d41692b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430453520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.3430453520
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.3881592804
Short name T310
Test name
Test status
Simulation time 678730352330 ps
CPU time 576.45 seconds
Started Jul 28 04:24:49 PM PDT 24
Finished Jul 28 04:34:27 PM PDT 24
Peak memory 181616 kb
Host smart-92795223-1823-4b3d-a998-2769b77a944e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881592804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.3881592804
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/57.rv_timer_random.1929750448
Short name T281
Test name
Test status
Simulation time 153293967865 ps
CPU time 708.54 seconds
Started Jul 28 04:29:29 PM PDT 24
Finished Jul 28 04:41:18 PM PDT 24
Peak memory 191568 kb
Host smart-587bb532-4301-4a20-858c-ccb982e405a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929750448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.1929750448
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.361008479
Short name T127
Test name
Test status
Simulation time 304020036196 ps
CPU time 318.88 seconds
Started Jul 28 04:29:19 PM PDT 24
Finished Jul 28 04:34:38 PM PDT 24
Peak memory 183364 kb
Host smart-1e31f86f-5f71-4402-b2fd-364540649978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361008479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.361008479
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.2791925497
Short name T215
Test name
Test status
Simulation time 350167299454 ps
CPU time 320.16 seconds
Started Jul 28 04:26:01 PM PDT 24
Finished Jul 28 04:31:21 PM PDT 24
Peak memory 183312 kb
Host smart-f03c0343-f713-45d9-aa64-099d505a13de
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791925497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.2791925497
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/112.rv_timer_random.1730226747
Short name T212
Test name
Test status
Simulation time 667320056572 ps
CPU time 1185.04 seconds
Started Jul 28 04:29:30 PM PDT 24
Finished Jul 28 04:49:16 PM PDT 24
Peak memory 191632 kb
Host smart-3918e0ae-f194-4ad6-9c8b-cf07a8ee8a0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730226747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.1730226747
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.1992724709
Short name T265
Test name
Test status
Simulation time 105521374912 ps
CPU time 214.22 seconds
Started Jul 28 04:29:28 PM PDT 24
Finished Jul 28 04:33:02 PM PDT 24
Peak memory 191512 kb
Host smart-7a31f0d9-48ca-4edb-a111-b7049e8526eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992724709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.1992724709
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.733622284
Short name T206
Test name
Test status
Simulation time 63357588192 ps
CPU time 146.63 seconds
Started Jul 28 04:29:52 PM PDT 24
Finished Jul 28 04:32:19 PM PDT 24
Peak memory 191592 kb
Host smart-bd2f4f4e-6cd0-4a8a-b2c9-dc60fe0d556b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733622284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.733622284
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.3439617411
Short name T259
Test name
Test status
Simulation time 862704080604 ps
CPU time 397.18 seconds
Started Jul 28 04:29:48 PM PDT 24
Finished Jul 28 04:36:25 PM PDT 24
Peak memory 191548 kb
Host smart-3878b6e4-e83b-489e-99b0-4c9118b6379e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439617411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.3439617411
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.1844137733
Short name T236
Test name
Test status
Simulation time 308052525020 ps
CPU time 161.3 seconds
Started Jul 28 04:29:18 PM PDT 24
Finished Jul 28 04:31:59 PM PDT 24
Peak memory 191568 kb
Host smart-423a4d53-80a2-4239-b8da-fa5778d08e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844137733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.1844137733
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.3137781974
Short name T336
Test name
Test status
Simulation time 165494391508 ps
CPU time 160.2 seconds
Started Jul 28 04:29:15 PM PDT 24
Finished Jul 28 04:31:55 PM PDT 24
Peak memory 183336 kb
Host smart-846c8ef0-a324-4061-b226-bfa42d8807d3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137781974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.3137781974
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_random.2410225157
Short name T51
Test name
Test status
Simulation time 457555278497 ps
CPU time 489.63 seconds
Started Jul 28 04:29:22 PM PDT 24
Finished Jul 28 04:37:32 PM PDT 24
Peak memory 191572 kb
Host smart-1c25eb0d-f6ea-4ad1-864b-8bcba2c35259
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410225157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.2410225157
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random.1499857463
Short name T49
Test name
Test status
Simulation time 81156681598 ps
CPU time 384.22 seconds
Started Jul 28 04:29:25 PM PDT 24
Finished Jul 28 04:35:49 PM PDT 24
Peak memory 191568 kb
Host smart-42602694-2488-4ece-8e7c-2046b0ace26e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499857463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.1499857463
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random.4233655355
Short name T197
Test name
Test status
Simulation time 130245714275 ps
CPU time 619.86 seconds
Started Jul 28 04:29:41 PM PDT 24
Finished Jul 28 04:40:01 PM PDT 24
Peak memory 191528 kb
Host smart-1a902d02-d4b9-4336-9cdf-78a1ea63a187
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233655355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.4233655355
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.2489436086
Short name T82
Test name
Test status
Simulation time 14774124 ps
CPU time 0.58 seconds
Started Jul 28 04:28:40 PM PDT 24
Finished Jul 28 04:28:41 PM PDT 24
Peak memory 182740 kb
Host smart-340ff475-5116-43e3-ad49-a2151f7a0546
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489436086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.2489436086
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.1323117939
Short name T30
Test name
Test status
Simulation time 147233298 ps
CPU time 1.36 seconds
Started Jul 28 04:21:18 PM PDT 24
Finished Jul 28 04:21:19 PM PDT 24
Peak memory 194772 kb
Host smart-2f58a629-3645-4a27-97ff-54120db52f64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323117939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.1323117939
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/107.rv_timer_random.398286687
Short name T112
Test name
Test status
Simulation time 580373304306 ps
CPU time 271.77 seconds
Started Jul 28 04:29:28 PM PDT 24
Finished Jul 28 04:34:00 PM PDT 24
Peak memory 191540 kb
Host smart-8beea599-47f8-40bc-83ff-42189c7abbf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398286687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.398286687
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.3709266209
Short name T303
Test name
Test status
Simulation time 2541964836727 ps
CPU time 822.39 seconds
Started Jul 28 04:30:39 PM PDT 24
Finished Jul 28 04:44:22 PM PDT 24
Peak memory 191280 kb
Host smart-a5fb1eff-320c-4fcd-a61f-ad745fa083c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709266209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.3709266209
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.500938166
Short name T5
Test name
Test status
Simulation time 731946586826 ps
CPU time 643.58 seconds
Started Jul 28 04:28:53 PM PDT 24
Finished Jul 28 04:39:37 PM PDT 24
Peak memory 183332 kb
Host smart-5952900a-408c-4ae2-b57f-b4fe4e8ac0bb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500938166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.rv_timer_cfg_update_on_fly.500938166
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/137.rv_timer_random.3775131197
Short name T240
Test name
Test status
Simulation time 235722831925 ps
CPU time 3100.19 seconds
Started Jul 28 04:29:47 PM PDT 24
Finished Jul 28 05:21:27 PM PDT 24
Peak memory 191552 kb
Host smart-11d6f321-a8dc-45d3-bb97-f35468a74e18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775131197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.3775131197
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.1725843986
Short name T279
Test name
Test status
Simulation time 573953760300 ps
CPU time 1037.76 seconds
Started Jul 28 04:29:51 PM PDT 24
Finished Jul 28 04:47:09 PM PDT 24
Peak memory 191512 kb
Host smart-20b8882e-b688-41c8-92cb-12788829aa30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725843986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.1725843986
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.2286466684
Short name T273
Test name
Test status
Simulation time 1456110085729 ps
CPU time 1049.36 seconds
Started Jul 28 04:29:47 PM PDT 24
Finished Jul 28 04:47:17 PM PDT 24
Peak memory 191532 kb
Host smart-807e1d97-fde2-4919-821d-9342b4d85bdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286466684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.2286466684
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.2016808986
Short name T126
Test name
Test status
Simulation time 286533662010 ps
CPU time 553.76 seconds
Started Jul 28 04:29:49 PM PDT 24
Finished Jul 28 04:39:03 PM PDT 24
Peak memory 191896 kb
Host smart-ee215dbe-29ec-41ba-a4db-197ab0a80bc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016808986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.2016808986
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.229334967
Short name T200
Test name
Test status
Simulation time 609924497667 ps
CPU time 686.52 seconds
Started Jul 28 04:29:56 PM PDT 24
Finished Jul 28 04:41:23 PM PDT 24
Peak memory 191484 kb
Host smart-0de84f97-65a4-4202-8a13-cf9e72c7d52d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229334967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.229334967
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.3856282239
Short name T25
Test name
Test status
Simulation time 1236471715932 ps
CPU time 804.83 seconds
Started Jul 28 04:29:14 PM PDT 24
Finished Jul 28 04:42:39 PM PDT 24
Peak memory 183328 kb
Host smart-a834a3e2-a89d-438f-a532-1cc5925c9d25
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856282239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.3856282239
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.1025221441
Short name T154
Test name
Test status
Simulation time 692916842877 ps
CPU time 647.52 seconds
Started Jul 28 04:29:19 PM PDT 24
Finished Jul 28 04:40:07 PM PDT 24
Peak memory 183348 kb
Host smart-fef4977f-b3b8-42eb-a188-6d6a9aa9278f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025221441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.1025221441
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.449818269
Short name T195
Test name
Test status
Simulation time 54837641244 ps
CPU time 47.57 seconds
Started Jul 28 04:29:21 PM PDT 24
Finished Jul 28 04:30:09 PM PDT 24
Peak memory 183328 kb
Host smart-c957dfce-1fed-4116-bec0-139a95fabbab
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449818269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.rv_timer_cfg_update_on_fly.449818269
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_random.3941759985
Short name T316
Test name
Test status
Simulation time 220262298433 ps
CPU time 103.93 seconds
Started Jul 28 04:29:22 PM PDT 24
Finished Jul 28 04:31:06 PM PDT 24
Peak memory 191548 kb
Host smart-8c16ef8b-a14d-48a0-ab93-bd2e373cdfd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941759985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.3941759985
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all_with_rand_reset.807607794
Short name T98
Test name
Test status
Simulation time 342483865836 ps
CPU time 698.68 seconds
Started Jul 28 04:29:27 PM PDT 24
Finished Jul 28 04:41:06 PM PDT 24
Peak memory 200748 kb
Host smart-f7cdbb90-347f-427c-a0d8-3a0fffb7901f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807607794 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all_with_rand_reset.807607794
Directory /workspace/46.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.rv_timer_random.3869673331
Short name T57
Test name
Test status
Simulation time 80939098866 ps
CPU time 1043 seconds
Started Jul 28 04:29:21 PM PDT 24
Finished Jul 28 04:46:45 PM PDT 24
Peak memory 192596 kb
Host smart-e5c3d6e0-dd0f-4f85-a5f4-24d97ca83196
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869673331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.3869673331
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.2416070175
Short name T113
Test name
Test status
Simulation time 758855982271 ps
CPU time 326.72 seconds
Started Jul 28 04:24:54 PM PDT 24
Finished Jul 28 04:30:21 PM PDT 24
Peak memory 183248 kb
Host smart-d2d7dccb-5388-4a18-8ded-4c7380086921
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416070175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.2416070175
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_random.556985582
Short name T326
Test name
Test status
Simulation time 78669142304 ps
CPU time 128.4 seconds
Started Jul 28 04:24:58 PM PDT 24
Finished Jul 28 04:27:07 PM PDT 24
Peak memory 190796 kb
Host smart-0b66e925-9b96-4535-ba2e-8fbed0c6bf97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556985582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.556985582
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random.1472456746
Short name T109
Test name
Test status
Simulation time 45058536450 ps
CPU time 75.3 seconds
Started Jul 28 04:24:54 PM PDT 24
Finished Jul 28 04:26:09 PM PDT 24
Peak memory 191376 kb
Host smart-dad2d018-b625-44e7-8ced-5be38d6ad7b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472456746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.1472456746
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.3165817786
Short name T77
Test name
Test status
Simulation time 458079159129 ps
CPU time 639.55 seconds
Started Jul 28 04:29:35 PM PDT 24
Finished Jul 28 04:40:15 PM PDT 24
Peak memory 191516 kb
Host smart-67bfa311-f578-4555-b01d-c4dc9636b8c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165817786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.3165817786
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.718686694
Short name T171
Test name
Test status
Simulation time 135204106167 ps
CPU time 107.83 seconds
Started Jul 28 04:29:29 PM PDT 24
Finished Jul 28 04:31:17 PM PDT 24
Peak memory 193716 kb
Host smart-b6f24953-fbee-421c-904c-de631522dee4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718686694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.718686694
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.2778713019
Short name T6
Test name
Test status
Simulation time 113444401474 ps
CPU time 124.66 seconds
Started Jul 28 04:29:20 PM PDT 24
Finished Jul 28 04:31:25 PM PDT 24
Peak memory 183520 kb
Host smart-41a60450-52a8-4e8c-a448-3d9851dccdb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778713019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.2778713019
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/133.rv_timer_random.4243030982
Short name T160
Test name
Test status
Simulation time 235876538338 ps
CPU time 852.65 seconds
Started Jul 28 04:29:51 PM PDT 24
Finished Jul 28 04:44:04 PM PDT 24
Peak memory 191560 kb
Host smart-cbf28bc4-6b32-4cab-82e9-a153365ddcbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243030982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.4243030982
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.3102293774
Short name T168
Test name
Test status
Simulation time 127464890867 ps
CPU time 546.17 seconds
Started Jul 28 04:29:39 PM PDT 24
Finished Jul 28 04:38:45 PM PDT 24
Peak memory 191560 kb
Host smart-a8c7e13e-616f-4bca-aee6-c247d42143f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102293774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.3102293774
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random.1987147989
Short name T258
Test name
Test status
Simulation time 613119109145 ps
CPU time 1690.4 seconds
Started Jul 28 04:29:11 PM PDT 24
Finished Jul 28 04:57:22 PM PDT 24
Peak memory 191532 kb
Host smart-e386609c-f26f-48f0-8aa5-c8dac3d99bdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987147989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.1987147989
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/150.rv_timer_random.2059147024
Short name T222
Test name
Test status
Simulation time 71039237099 ps
CPU time 164.96 seconds
Started Jul 28 04:29:39 PM PDT 24
Finished Jul 28 04:32:24 PM PDT 24
Peak memory 191724 kb
Host smart-85f6c194-5c40-4a35-9e01-05af630663f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059147024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.2059147024
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.1977369118
Short name T299
Test name
Test status
Simulation time 103497476297 ps
CPU time 293.1 seconds
Started Jul 28 04:29:55 PM PDT 24
Finished Jul 28 04:34:48 PM PDT 24
Peak memory 194420 kb
Host smart-004e20f1-23e9-4249-bd3a-7c95718f5c39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977369118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.1977369118
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random.1966415950
Short name T244
Test name
Test status
Simulation time 65900603132 ps
CPU time 234.94 seconds
Started Jul 28 04:29:04 PM PDT 24
Finished Jul 28 04:32:59 PM PDT 24
Peak memory 191544 kb
Host smart-8628b4a7-264c-4f7f-86ca-48a17e541ee3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966415950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.1966415950
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.1280659105
Short name T123
Test name
Test status
Simulation time 109937303911 ps
CPU time 954.6 seconds
Started Jul 28 04:29:50 PM PDT 24
Finished Jul 28 04:45:44 PM PDT 24
Peak memory 191532 kb
Host smart-f3ba4aa5-a10c-49bf-b721-f0e36e373308
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280659105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.1280659105
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.1780402732
Short name T260
Test name
Test status
Simulation time 81153187561 ps
CPU time 354.7 seconds
Started Jul 28 04:29:51 PM PDT 24
Finished Jul 28 04:35:46 PM PDT 24
Peak memory 191552 kb
Host smart-fc4c1253-cd68-47f8-8f6f-d768e29e7ee8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780402732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.1780402732
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random.2671550948
Short name T239
Test name
Test status
Simulation time 180649283485 ps
CPU time 355.73 seconds
Started Jul 28 04:29:17 PM PDT 24
Finished Jul 28 04:35:13 PM PDT 24
Peak memory 183688 kb
Host smart-6e8ff36c-2e59-4318-bf56-fc379ad63eba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671550948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.2671550948
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random.3460750431
Short name T238
Test name
Test status
Simulation time 704376397725 ps
CPU time 543.84 seconds
Started Jul 28 04:29:24 PM PDT 24
Finished Jul 28 04:38:28 PM PDT 24
Peak memory 191556 kb
Host smart-fa4f144d-42ff-42f3-9618-16730212f3f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460750431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.3460750431
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random.2329814191
Short name T319
Test name
Test status
Simulation time 4928801390 ps
CPU time 9.11 seconds
Started Jul 28 04:29:27 PM PDT 24
Finished Jul 28 04:29:36 PM PDT 24
Peak memory 183320 kb
Host smart-787450d4-64c4-46dd-8f56-3e400cd2b5fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329814191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.2329814191
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.347088626
Short name T286
Test name
Test status
Simulation time 1193307651331 ps
CPU time 222.5 seconds
Started Jul 28 04:29:34 PM PDT 24
Finished Jul 28 04:33:17 PM PDT 24
Peak memory 191056 kb
Host smart-9e061124-d22d-4e50-bf66-c68f2ee7c9ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347088626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.347088626
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.70377910
Short name T247
Test name
Test status
Simulation time 404440097696 ps
CPU time 191.82 seconds
Started Jul 28 04:29:30 PM PDT 24
Finished Jul 28 04:32:42 PM PDT 24
Peak memory 193696 kb
Host smart-7d6a91fe-4361-41f2-b763-2d0006661e70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70377910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.70377910
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.681353647
Short name T115
Test name
Test status
Simulation time 2138358342177 ps
CPU time 1095.03 seconds
Started Jul 28 04:21:06 PM PDT 24
Finished Jul 28 04:39:22 PM PDT 24
Peak memory 191564 kb
Host smart-5e66795e-b1dd-4dcf-a1d0-d90a42758ed3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681353647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.681353647
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/83.rv_timer_random.3758024282
Short name T182
Test name
Test status
Simulation time 122218330678 ps
CPU time 161.61 seconds
Started Jul 28 04:29:28 PM PDT 24
Finished Jul 28 04:32:10 PM PDT 24
Peak memory 191552 kb
Host smart-4c4af9c0-4ef9-466d-b347-1fde09a65ed0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758024282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.3758024282
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.99822505
Short name T85
Test name
Test status
Simulation time 21156559 ps
CPU time 0.6 seconds
Started Jul 28 04:21:11 PM PDT 24
Finished Jul 28 04:21:11 PM PDT 24
Peak memory 182780 kb
Host smart-b34e981a-06a5-42d8-92f7-8b1d2d8eaf04
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99822505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_aliasi
ng.99822505
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.1357178683
Short name T545
Test name
Test status
Simulation time 36654355 ps
CPU time 1.35 seconds
Started Jul 28 04:21:14 PM PDT 24
Finished Jul 28 04:21:15 PM PDT 24
Peak memory 192596 kb
Host smart-cf984f3e-fdd6-4fab-af66-6c149c5ca5b3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357178683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.1357178683
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.2900111612
Short name T541
Test name
Test status
Simulation time 59568743 ps
CPU time 0.55 seconds
Started Jul 28 04:23:26 PM PDT 24
Finished Jul 28 04:23:27 PM PDT 24
Peak memory 182852 kb
Host smart-9a9a9887-6b8e-4097-8183-eb89cf355824
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900111612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.2900111612
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.1145890203
Short name T450
Test name
Test status
Simulation time 109909135 ps
CPU time 1.38 seconds
Started Jul 28 04:21:29 PM PDT 24
Finished Jul 28 04:21:31 PM PDT 24
Peak memory 197456 kb
Host smart-375e35d8-2cc3-47f6-9d70-d9d1f06cbe79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145890203 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.1145890203
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.2097266323
Short name T79
Test name
Test status
Simulation time 17749549 ps
CPU time 0.6 seconds
Started Jul 28 04:21:14 PM PDT 24
Finished Jul 28 04:21:15 PM PDT 24
Peak memory 181440 kb
Host smart-38e341ae-6056-46da-b993-78b7d39de6cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097266323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.2097266323
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.131866366
Short name T508
Test name
Test status
Simulation time 63950972 ps
CPU time 0.58 seconds
Started Jul 28 04:21:29 PM PDT 24
Finished Jul 28 04:21:30 PM PDT 24
Peak memory 182500 kb
Host smart-5336b67a-6c42-4ead-8054-521745c8ad3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131866366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.131866366
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.792371259
Short name T496
Test name
Test status
Simulation time 50108619 ps
CPU time 0.68 seconds
Started Jul 28 04:23:26 PM PDT 24
Finished Jul 28 04:23:27 PM PDT 24
Peak memory 192356 kb
Host smart-ad62d73c-cb23-421a-af6a-54d0ee331bba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792371259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_tim
er_same_csr_outstanding.792371259
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2269521972
Short name T492
Test name
Test status
Simulation time 30233311 ps
CPU time 1.41 seconds
Started Jul 28 04:24:57 PM PDT 24
Finished Jul 28 04:24:59 PM PDT 24
Peak memory 197148 kb
Host smart-769bfd71-581e-40ce-b808-7f4054a83339
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269521972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.2269521972
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.3680438466
Short name T486
Test name
Test status
Simulation time 285193733 ps
CPU time 1.02 seconds
Started Jul 28 04:21:28 PM PDT 24
Finished Jul 28 04:21:29 PM PDT 24
Peak memory 195092 kb
Host smart-253a8169-9ced-44d4-9470-58f3978a022c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680438466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.3680438466
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.3816793940
Short name T90
Test name
Test status
Simulation time 34345038 ps
CPU time 0.83 seconds
Started Jul 28 04:20:25 PM PDT 24
Finished Jul 28 04:20:26 PM PDT 24
Peak memory 192656 kb
Host smart-f960232e-fdee-4a64-92c7-6433c6c8901a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816793940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.3816793940
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.301732110
Short name T31
Test name
Test status
Simulation time 2103878213 ps
CPU time 3.34 seconds
Started Jul 28 04:20:29 PM PDT 24
Finished Jul 28 04:20:32 PM PDT 24
Peak memory 193944 kb
Host smart-0c964e04-dc8c-4e28-9155-ac42483da150
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301732110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_b
ash.301732110
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.224954512
Short name T89
Test name
Test status
Simulation time 21870972 ps
CPU time 0.55 seconds
Started Jul 28 04:20:28 PM PDT 24
Finished Jul 28 04:20:28 PM PDT 24
Peak memory 182464 kb
Host smart-a9e6a149-751b-46f3-baf2-e25aa7e5ca28
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224954512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_re
set.224954512
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.1066689790
Short name T517
Test name
Test status
Simulation time 104468156 ps
CPU time 1.22 seconds
Started Jul 28 04:24:54 PM PDT 24
Finished Jul 28 04:24:55 PM PDT 24
Peak memory 197148 kb
Host smart-d357fe80-54a5-47a2-89a6-e5eacdfe12e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066689790 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.1066689790
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.617048137
Short name T465
Test name
Test status
Simulation time 39864745 ps
CPU time 0.55 seconds
Started Jul 28 04:20:29 PM PDT 24
Finished Jul 28 04:20:30 PM PDT 24
Peak memory 182464 kb
Host smart-95f9890e-15c8-4194-901e-4b9665eddf0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617048137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.617048137
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.2016027551
Short name T554
Test name
Test status
Simulation time 42099770 ps
CPU time 0.5 seconds
Started Jul 28 04:24:48 PM PDT 24
Finished Jul 28 04:24:49 PM PDT 24
Peak memory 181164 kb
Host smart-8b6e3e8f-c658-4d2b-af1a-b45c72aa5e21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016027551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.2016027551
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.2944986315
Short name T520
Test name
Test status
Simulation time 60321720 ps
CPU time 0.79 seconds
Started Jul 28 04:24:54 PM PDT 24
Finished Jul 28 04:24:55 PM PDT 24
Peak memory 192468 kb
Host smart-7e3d6b43-0390-4f5c-8579-a0c31ce38601
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944986315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.2944986315
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.2908928922
Short name T569
Test name
Test status
Simulation time 85329274 ps
CPU time 2 seconds
Started Jul 28 04:24:58 PM PDT 24
Finished Jul 28 04:25:00 PM PDT 24
Peak memory 197168 kb
Host smart-51e067c9-7ba2-47d1-9006-1dfb91b00696
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908928922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.2908928922
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.2179847246
Short name T534
Test name
Test status
Simulation time 25246854 ps
CPU time 0.74 seconds
Started Jul 28 04:28:36 PM PDT 24
Finished Jul 28 04:28:37 PM PDT 24
Peak memory 195448 kb
Host smart-41d3dcfc-f757-4969-909a-c6ff6271d9ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179847246 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.2179847246
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.3466453479
Short name T88
Test name
Test status
Simulation time 40730051 ps
CPU time 0.56 seconds
Started Jul 28 04:28:40 PM PDT 24
Finished Jul 28 04:28:40 PM PDT 24
Peak memory 182716 kb
Host smart-32b9e18e-1e14-4bb4-bf7e-f089205027be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466453479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.3466453479
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1280795476
Short name T576
Test name
Test status
Simulation time 14108979 ps
CPU time 0.54 seconds
Started Jul 28 04:28:41 PM PDT 24
Finished Jul 28 04:28:42 PM PDT 24
Peak memory 182564 kb
Host smart-cbcbfb49-44b4-487b-abe4-2869d9d23dc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280795476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.1280795476
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.4267924976
Short name T521
Test name
Test status
Simulation time 34259008 ps
CPU time 0.71 seconds
Started Jul 28 04:28:39 PM PDT 24
Finished Jul 28 04:28:40 PM PDT 24
Peak memory 191704 kb
Host smart-d49946cc-f720-421b-bd67-f48405ad2556
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267924976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.4267924976
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.621725575
Short name T538
Test name
Test status
Simulation time 217175824 ps
CPU time 1.92 seconds
Started Jul 28 04:28:37 PM PDT 24
Finished Jul 28 04:28:39 PM PDT 24
Peak memory 197444 kb
Host smart-ed4cab2e-a673-41be-8edf-4d38d7b01137
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621725575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.621725575
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.3714828054
Short name T523
Test name
Test status
Simulation time 182023314 ps
CPU time 0.81 seconds
Started Jul 28 04:28:36 PM PDT 24
Finished Jul 28 04:28:42 PM PDT 24
Peak memory 193856 kb
Host smart-c5f4f217-431c-4ae3-b310-fda253696bda
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714828054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.3714828054
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.2474591296
Short name T478
Test name
Test status
Simulation time 23299631 ps
CPU time 0.7 seconds
Started Jul 28 04:28:41 PM PDT 24
Finished Jul 28 04:28:45 PM PDT 24
Peak memory 194040 kb
Host smart-376ed857-13e2-4163-a041-57c25c46039c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474591296 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.2474591296
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.4112997902
Short name T560
Test name
Test status
Simulation time 18062072 ps
CPU time 0.54 seconds
Started Jul 28 04:28:42 PM PDT 24
Finished Jul 28 04:28:42 PM PDT 24
Peak memory 182676 kb
Host smart-050ac068-76d3-46a7-aa55-77f79a1bbe73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112997902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.4112997902
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.2764267107
Short name T93
Test name
Test status
Simulation time 79654988 ps
CPU time 0.68 seconds
Started Jul 28 04:28:39 PM PDT 24
Finished Jul 28 04:28:40 PM PDT 24
Peak memory 191664 kb
Host smart-fce3aab5-76c9-449b-aa45-cc490cba499a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764267107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.2764267107
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.1618802402
Short name T524
Test name
Test status
Simulation time 353621374 ps
CPU time 2.63 seconds
Started Jul 28 04:28:38 PM PDT 24
Finished Jul 28 04:28:41 PM PDT 24
Peak memory 197604 kb
Host smart-c1c8230a-657c-4f75-8159-5447e7959bef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618802402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.1618802402
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.919224022
Short name T543
Test name
Test status
Simulation time 144955010 ps
CPU time 1.17 seconds
Started Jul 28 04:28:37 PM PDT 24
Finished Jul 28 04:28:39 PM PDT 24
Peak memory 194756 kb
Host smart-03ed4766-1b5c-4a13-8ccd-0290f783cf23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919224022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_in
tg_err.919224022
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.806926732
Short name T498
Test name
Test status
Simulation time 28656712 ps
CPU time 1.19 seconds
Started Jul 28 04:28:44 PM PDT 24
Finished Jul 28 04:28:45 PM PDT 24
Peak memory 197432 kb
Host smart-3b8fe1a9-c2f1-4686-9bb6-f0a3fe5561e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806926732 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.806926732
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2165386443
Short name T92
Test name
Test status
Simulation time 43496269 ps
CPU time 0.55 seconds
Started Jul 28 04:28:41 PM PDT 24
Finished Jul 28 04:28:42 PM PDT 24
Peak memory 182692 kb
Host smart-d8e88f03-92b1-474f-a97c-fcdfd95b1a44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165386443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.2165386443
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.1358966154
Short name T471
Test name
Test status
Simulation time 12923911 ps
CPU time 0.56 seconds
Started Jul 28 04:28:41 PM PDT 24
Finished Jul 28 04:28:41 PM PDT 24
Peak memory 182720 kb
Host smart-87588454-e6db-493c-810a-183eafdf1b38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358966154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.1358966154
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3804147223
Short name T95
Test name
Test status
Simulation time 160006514 ps
CPU time 0.77 seconds
Started Jul 28 04:28:40 PM PDT 24
Finished Jul 28 04:28:41 PM PDT 24
Peak memory 192108 kb
Host smart-e8fa9c47-5da4-40f4-8e31-683d84989987
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804147223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.3804147223
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.2477825418
Short name T467
Test name
Test status
Simulation time 63381197 ps
CPU time 1.59 seconds
Started Jul 28 04:28:46 PM PDT 24
Finished Jul 28 04:28:48 PM PDT 24
Peak memory 197516 kb
Host smart-12c9953c-d142-4021-bea0-7df4282fe2c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477825418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.2477825418
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.3941318245
Short name T529
Test name
Test status
Simulation time 82343822 ps
CPU time 1.1 seconds
Started Jul 28 04:28:40 PM PDT 24
Finished Jul 28 04:28:42 PM PDT 24
Peak memory 195252 kb
Host smart-0a626c36-e5c7-46e7-8eba-8eff841d2e62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941318245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.3941318245
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2138349760
Short name T490
Test name
Test status
Simulation time 103794206 ps
CPU time 1.26 seconds
Started Jul 28 04:28:44 PM PDT 24
Finished Jul 28 04:28:46 PM PDT 24
Peak memory 197424 kb
Host smart-ae0ce717-debe-45d0-818e-9b0346e3cd9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138349760 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.2138349760
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.817611644
Short name T43
Test name
Test status
Simulation time 30480439 ps
CPU time 0.57 seconds
Started Jul 28 04:28:41 PM PDT 24
Finished Jul 28 04:28:42 PM PDT 24
Peak memory 182744 kb
Host smart-522c7d51-7170-48b0-8cc2-e10bebc6bddd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817611644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.817611644
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.1902614252
Short name T513
Test name
Test status
Simulation time 51806935 ps
CPU time 0.53 seconds
Started Jul 28 04:28:45 PM PDT 24
Finished Jul 28 04:28:46 PM PDT 24
Peak memory 182596 kb
Host smart-7036e188-175f-41a0-9957-9db0887f2a05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902614252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.1902614252
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.3262052849
Short name T94
Test name
Test status
Simulation time 55540485 ps
CPU time 0.7 seconds
Started Jul 28 04:28:41 PM PDT 24
Finished Jul 28 04:28:42 PM PDT 24
Peak memory 193356 kb
Host smart-cab6ac81-c7b3-42e7-9cfb-64f66962fb6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262052849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.3262052849
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.2619383374
Short name T553
Test name
Test status
Simulation time 236009090 ps
CPU time 2.09 seconds
Started Jul 28 04:28:41 PM PDT 24
Finished Jul 28 04:28:43 PM PDT 24
Peak memory 197496 kb
Host smart-9e703c88-1530-4e46-9032-70eafe090d55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619383374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.2619383374
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.3134954853
Short name T48
Test name
Test status
Simulation time 289977010 ps
CPU time 1.1 seconds
Started Jul 28 04:28:47 PM PDT 24
Finished Jul 28 04:28:48 PM PDT 24
Peak memory 183072 kb
Host smart-fa6b192b-eb98-461f-ab24-cf5d220a3620
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134954853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.3134954853
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.2830455341
Short name T46
Test name
Test status
Simulation time 83847173 ps
CPU time 0.67 seconds
Started Jul 28 04:28:45 PM PDT 24
Finished Jul 28 04:28:46 PM PDT 24
Peak memory 194608 kb
Host smart-26bba5f8-6f21-4d1f-b386-5cbd036bfe1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830455341 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.2830455341
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3607182509
Short name T572
Test name
Test status
Simulation time 14337330 ps
CPU time 0.53 seconds
Started Jul 28 04:28:39 PM PDT 24
Finished Jul 28 04:28:40 PM PDT 24
Peak memory 182696 kb
Host smart-ad984085-e2a8-4daf-9a03-13b5e8ca3234
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607182509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.3607182509
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.3652209747
Short name T559
Test name
Test status
Simulation time 87495138 ps
CPU time 0.54 seconds
Started Jul 28 04:28:41 PM PDT 24
Finished Jul 28 04:28:41 PM PDT 24
Peak memory 182088 kb
Host smart-3901b94c-e100-48ad-8c66-3317a77528e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652209747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.3652209747
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.3566687620
Short name T81
Test name
Test status
Simulation time 37939133 ps
CPU time 0.78 seconds
Started Jul 28 04:28:41 PM PDT 24
Finished Jul 28 04:28:42 PM PDT 24
Peak memory 193500 kb
Host smart-5b926df2-18ab-4069-8e96-942c3b419250
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566687620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.3566687620
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.615694617
Short name T566
Test name
Test status
Simulation time 113868266 ps
CPU time 1.12 seconds
Started Jul 28 04:28:38 PM PDT 24
Finished Jul 28 04:28:40 PM PDT 24
Peak memory 197240 kb
Host smart-da1b187e-8b0e-4883-9667-937ee76b0137
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615694617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.615694617
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.624737814
Short name T28
Test name
Test status
Simulation time 200780325 ps
CPU time 1.11 seconds
Started Jul 28 04:28:42 PM PDT 24
Finished Jul 28 04:28:46 PM PDT 24
Peak memory 194244 kb
Host smart-5d9ebdd9-38c9-447e-aafc-d805fdb800d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624737814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_in
tg_err.624737814
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1319914045
Short name T501
Test name
Test status
Simulation time 38881893 ps
CPU time 1.43 seconds
Started Jul 28 04:28:41 PM PDT 24
Finished Jul 28 04:28:42 PM PDT 24
Peak memory 197496 kb
Host smart-c69831f4-6a2f-4d55-bccf-99e77fde644c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319914045 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.1319914045
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.1144678459
Short name T84
Test name
Test status
Simulation time 12509865 ps
CPU time 0.54 seconds
Started Jul 28 04:28:46 PM PDT 24
Finished Jul 28 04:28:47 PM PDT 24
Peak memory 182552 kb
Host smart-4f29e086-4a7e-4061-81d3-8c6aa52060c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144678459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.1144678459
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2402609307
Short name T480
Test name
Test status
Simulation time 31516039 ps
CPU time 0.54 seconds
Started Jul 28 04:28:40 PM PDT 24
Finished Jul 28 04:28:41 PM PDT 24
Peak memory 183096 kb
Host smart-5c58e4a5-9637-4f2d-b87e-833e26e62681
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402609307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.2402609307
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.4169624285
Short name T544
Test name
Test status
Simulation time 22090993 ps
CPU time 0.76 seconds
Started Jul 28 04:28:42 PM PDT 24
Finished Jul 28 04:28:43 PM PDT 24
Peak memory 193404 kb
Host smart-370a3039-78fe-46e6-9c65-5a7d7cf9b198
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169624285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.4169624285
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.541420457
Short name T540
Test name
Test status
Simulation time 896740972 ps
CPU time 2.29 seconds
Started Jul 28 04:28:43 PM PDT 24
Finished Jul 28 04:28:45 PM PDT 24
Peak memory 197652 kb
Host smart-38922d36-a49e-43de-96ff-671a661d615d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541420457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.541420457
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1004128416
Short name T570
Test name
Test status
Simulation time 80934142 ps
CPU time 0.79 seconds
Started Jul 28 04:28:43 PM PDT 24
Finished Jul 28 04:28:44 PM PDT 24
Peak memory 193836 kb
Host smart-54bb5616-f078-41b2-9069-2cec1013e0ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004128416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.1004128416
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.107847501
Short name T571
Test name
Test status
Simulation time 84649877 ps
CPU time 0.84 seconds
Started Jul 28 04:28:43 PM PDT 24
Finished Jul 28 04:28:44 PM PDT 24
Peak memory 195636 kb
Host smart-1674f366-5c56-4038-9a4d-5998fc144a91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107847501 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.107847501
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.3941896354
Short name T460
Test name
Test status
Simulation time 13279744 ps
CPU time 0.53 seconds
Started Jul 28 04:28:39 PM PDT 24
Finished Jul 28 04:28:40 PM PDT 24
Peak memory 182616 kb
Host smart-829b7570-bb21-4370-97fe-6cfbbff8d747
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941896354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.3941896354
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2005888923
Short name T539
Test name
Test status
Simulation time 188262679 ps
CPU time 0.69 seconds
Started Jul 28 04:28:40 PM PDT 24
Finished Jul 28 04:28:41 PM PDT 24
Peak memory 191844 kb
Host smart-26ceb720-cf18-4899-a662-a05c4fd13b1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005888923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.2005888923
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.1641627602
Short name T457
Test name
Test status
Simulation time 80246951 ps
CPU time 1.55 seconds
Started Jul 28 04:28:40 PM PDT 24
Finished Jul 28 04:28:42 PM PDT 24
Peak memory 197524 kb
Host smart-46dd055f-178c-4a4d-9e25-c03e209a3561
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641627602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.1641627602
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.1769683836
Short name T484
Test name
Test status
Simulation time 48168117 ps
CPU time 0.82 seconds
Started Jul 28 04:28:41 PM PDT 24
Finished Jul 28 04:28:42 PM PDT 24
Peak memory 183088 kb
Host smart-c56cf00e-1692-44ca-9d1c-a34d2f45e3e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769683836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.1769683836
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.4219186278
Short name T475
Test name
Test status
Simulation time 54578480 ps
CPU time 1.37 seconds
Started Jul 28 04:28:51 PM PDT 24
Finished Jul 28 04:28:53 PM PDT 24
Peak memory 197388 kb
Host smart-98878b20-0e21-4118-8830-159def48fdda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219186278 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.4219186278
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.427881525
Short name T500
Test name
Test status
Simulation time 134196352 ps
CPU time 0.58 seconds
Started Jul 28 04:28:45 PM PDT 24
Finished Jul 28 04:28:45 PM PDT 24
Peak memory 182680 kb
Host smart-cd47622d-788b-4dc2-915a-d7102c9440bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427881525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.427881525
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3127551848
Short name T546
Test name
Test status
Simulation time 18988556 ps
CPU time 0.58 seconds
Started Jul 28 04:28:41 PM PDT 24
Finished Jul 28 04:28:42 PM PDT 24
Peak memory 182672 kb
Host smart-9f50d94d-c49e-4eef-85f6-794e5ca9657e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127551848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.3127551848
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.345902567
Short name T567
Test name
Test status
Simulation time 54430494 ps
CPU time 0.77 seconds
Started Jul 28 04:28:41 PM PDT 24
Finished Jul 28 04:28:42 PM PDT 24
Peak memory 191728 kb
Host smart-d4eb25ac-4a00-4eec-a6ae-84d57ac9a6e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345902567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_ti
mer_same_csr_outstanding.345902567
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.647071102
Short name T491
Test name
Test status
Simulation time 280104700 ps
CPU time 2.85 seconds
Started Jul 28 04:28:44 PM PDT 24
Finished Jul 28 04:28:47 PM PDT 24
Peak memory 197460 kb
Host smart-74f9f0c2-d807-4901-b6d6-fcb25d806666
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647071102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.647071102
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.2859341562
Short name T100
Test name
Test status
Simulation time 637589911 ps
CPU time 1.04 seconds
Started Jul 28 04:28:40 PM PDT 24
Finished Jul 28 04:28:41 PM PDT 24
Peak memory 183160 kb
Host smart-0c7b946e-a8e7-4ba9-a49e-8af3e49b0e4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859341562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.2859341562
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.2130317244
Short name T464
Test name
Test status
Simulation time 28059812 ps
CPU time 0.83 seconds
Started Jul 28 04:28:46 PM PDT 24
Finished Jul 28 04:28:47 PM PDT 24
Peak memory 196940 kb
Host smart-9c2babd6-8d27-40b1-9e52-4ffdde346d4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130317244 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.2130317244
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.2511271785
Short name T489
Test name
Test status
Simulation time 42941301 ps
CPU time 0.56 seconds
Started Jul 28 04:28:47 PM PDT 24
Finished Jul 28 04:28:48 PM PDT 24
Peak memory 182696 kb
Host smart-16e6b133-95cf-4deb-a0f8-7919064d3027
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511271785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.2511271785
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.185893294
Short name T459
Test name
Test status
Simulation time 13136582 ps
CPU time 0.56 seconds
Started Jul 28 04:28:46 PM PDT 24
Finished Jul 28 04:28:47 PM PDT 24
Peak memory 182668 kb
Host smart-0a3bb580-310c-4fb5-b067-735375f7d262
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185893294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.185893294
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3758152604
Short name T561
Test name
Test status
Simulation time 114847251 ps
CPU time 0.69 seconds
Started Jul 28 04:28:58 PM PDT 24
Finished Jul 28 04:28:58 PM PDT 24
Peak memory 193164 kb
Host smart-954c57cf-2da4-4ea9-8537-4b6adf526db0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758152604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.3758152604
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.1074858754
Short name T536
Test name
Test status
Simulation time 313911877 ps
CPU time 2.53 seconds
Started Jul 28 04:29:03 PM PDT 24
Finished Jul 28 04:29:06 PM PDT 24
Peak memory 197456 kb
Host smart-99ff85ee-51e7-4189-8be7-9fc647e91d2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074858754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.1074858754
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1204867125
Short name T476
Test name
Test status
Simulation time 42743683 ps
CPU time 0.78 seconds
Started Jul 28 04:28:46 PM PDT 24
Finished Jul 28 04:28:47 PM PDT 24
Peak memory 183384 kb
Host smart-02c68124-13f8-4eb9-8e54-5dfff5088645
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204867125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.1204867125
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.1059695343
Short name T530
Test name
Test status
Simulation time 39374891 ps
CPU time 1.67 seconds
Started Jul 28 04:28:45 PM PDT 24
Finished Jul 28 04:28:47 PM PDT 24
Peak memory 197896 kb
Host smart-6b37ad79-5f68-473b-bcdb-f63630ed7259
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059695343 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.1059695343
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.740277487
Short name T503
Test name
Test status
Simulation time 96685910 ps
CPU time 0.53 seconds
Started Jul 28 04:28:47 PM PDT 24
Finished Jul 28 04:28:47 PM PDT 24
Peak memory 182608 kb
Host smart-912cdab9-d7ea-465e-a669-826b689a8312
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740277487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.740277487
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.52888274
Short name T516
Test name
Test status
Simulation time 22394480 ps
CPU time 0.52 seconds
Started Jul 28 04:28:48 PM PDT 24
Finished Jul 28 04:28:49 PM PDT 24
Peak memory 182028 kb
Host smart-968d40a6-4cd3-40d5-9d69-ed15e54117d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52888274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.52888274
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.1121203495
Short name T497
Test name
Test status
Simulation time 69298869 ps
CPU time 0.62 seconds
Started Jul 28 04:28:54 PM PDT 24
Finished Jul 28 04:28:55 PM PDT 24
Peak memory 191592 kb
Host smart-fdce6158-f18b-49fa-b37e-419f3cf804eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121203495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.1121203495
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.2291460775
Short name T58
Test name
Test status
Simulation time 1332328548 ps
CPU time 2.12 seconds
Started Jul 28 04:28:51 PM PDT 24
Finished Jul 28 04:28:53 PM PDT 24
Peak memory 197424 kb
Host smart-68d660bc-e02e-4940-968d-a99383d0355a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291460775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.2291460775
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2531981514
Short name T487
Test name
Test status
Simulation time 389487189 ps
CPU time 1.33 seconds
Started Jul 28 04:28:59 PM PDT 24
Finished Jul 28 04:29:00 PM PDT 24
Peak memory 195352 kb
Host smart-c3aad052-92dd-4a79-bf11-b76c7bc606f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531981514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.2531981514
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.2922274358
Short name T45
Test name
Test status
Simulation time 152003612 ps
CPU time 0.86 seconds
Started Jul 28 04:21:51 PM PDT 24
Finished Jul 28 04:21:52 PM PDT 24
Peak memory 192648 kb
Host smart-c2109256-fdd8-4057-bcef-b6766ee0d8b4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922274358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.2922274358
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1795715417
Short name T557
Test name
Test status
Simulation time 1622317553 ps
CPU time 3.5 seconds
Started Jul 28 04:20:27 PM PDT 24
Finished Jul 28 04:20:31 PM PDT 24
Peak memory 192424 kb
Host smart-d5e062d1-1104-44cf-8627-c34848da0f99
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795715417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.1795715417
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.2291066951
Short name T578
Test name
Test status
Simulation time 22600667 ps
CPU time 0.56 seconds
Started Jul 28 04:22:24 PM PDT 24
Finished Jul 28 04:22:25 PM PDT 24
Peak memory 182224 kb
Host smart-527ba738-256b-499e-8b91-2d554b2752b5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291066951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.2291066951
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.76854919
Short name T535
Test name
Test status
Simulation time 22823644 ps
CPU time 0.69 seconds
Started Jul 28 04:22:00 PM PDT 24
Finished Jul 28 04:22:01 PM PDT 24
Peak memory 194504 kb
Host smart-18defdcc-182d-450c-aab4-4a9a0594e25c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76854919 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.76854919
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.2438928956
Short name T507
Test name
Test status
Simulation time 23955650 ps
CPU time 0.62 seconds
Started Jul 28 04:21:49 PM PDT 24
Finished Jul 28 04:21:50 PM PDT 24
Peak memory 183152 kb
Host smart-af3c54f4-76a8-49df-906e-5540ec65a47b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438928956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.2438928956
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.111770941
Short name T509
Test name
Test status
Simulation time 47938666 ps
CPU time 0.53 seconds
Started Jul 28 04:22:27 PM PDT 24
Finished Jul 28 04:22:27 PM PDT 24
Peak memory 182684 kb
Host smart-a8025d39-fbd7-4011-a5ab-bd8c66d938b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111770941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.111770941
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.545971685
Short name T519
Test name
Test status
Simulation time 171609989 ps
CPU time 0.71 seconds
Started Jul 28 04:25:33 PM PDT 24
Finished Jul 28 04:25:35 PM PDT 24
Peak memory 191452 kb
Host smart-0c0841a1-6bf7-4f85-9436-7a31ad90045b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545971685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_tim
er_same_csr_outstanding.545971685
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.1070090325
Short name T532
Test name
Test status
Simulation time 27373067 ps
CPU time 1.11 seconds
Started Jul 28 04:24:48 PM PDT 24
Finished Jul 28 04:24:49 PM PDT 24
Peak memory 195972 kb
Host smart-6acc21f5-fc64-49d4-acfe-92098f880872
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070090325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.1070090325
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.2668520964
Short name T512
Test name
Test status
Simulation time 52534838 ps
CPU time 0.61 seconds
Started Jul 28 04:28:53 PM PDT 24
Finished Jul 28 04:28:54 PM PDT 24
Peak memory 182672 kb
Host smart-c993d21d-9057-4863-b560-7be7d2613cc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668520964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.2668520964
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1705675068
Short name T511
Test name
Test status
Simulation time 23499714 ps
CPU time 0.55 seconds
Started Jul 28 04:28:48 PM PDT 24
Finished Jul 28 04:28:49 PM PDT 24
Peak memory 182704 kb
Host smart-1f306b5e-67d7-4353-9a4b-c5e0b2e6fe2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705675068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.1705675068
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.3268936882
Short name T463
Test name
Test status
Simulation time 91132615 ps
CPU time 0.55 seconds
Started Jul 28 04:28:46 PM PDT 24
Finished Jul 28 04:28:46 PM PDT 24
Peak memory 182084 kb
Host smart-74cb4807-49b5-4337-a542-47bc13ce0d03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268936882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.3268936882
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.283489079
Short name T474
Test name
Test status
Simulation time 15343814 ps
CPU time 0.58 seconds
Started Jul 28 04:28:52 PM PDT 24
Finished Jul 28 04:28:52 PM PDT 24
Peak memory 182664 kb
Host smart-7559a2f4-c879-47d7-a38f-529bce3e7eb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283489079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.283489079
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.3536104271
Short name T510
Test name
Test status
Simulation time 34264621 ps
CPU time 0.56 seconds
Started Jul 28 04:28:46 PM PDT 24
Finished Jul 28 04:28:46 PM PDT 24
Peak memory 182120 kb
Host smart-6008006d-ed1e-4a93-b4e3-ccc48565ed82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536104271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.3536104271
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.804972154
Short name T563
Test name
Test status
Simulation time 44159790 ps
CPU time 0.52 seconds
Started Jul 28 04:28:55 PM PDT 24
Finished Jul 28 04:28:56 PM PDT 24
Peak memory 182284 kb
Host smart-7f31335d-3d81-431d-85a1-aaed6dfb9854
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804972154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.804972154
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.4261131558
Short name T466
Test name
Test status
Simulation time 14666451 ps
CPU time 0.59 seconds
Started Jul 28 04:28:53 PM PDT 24
Finished Jul 28 04:28:53 PM PDT 24
Peak memory 182680 kb
Host smart-52286d98-e8e3-4e70-86d7-cf53e0c75a2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261131558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.4261131558
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.3590616871
Short name T533
Test name
Test status
Simulation time 20087575 ps
CPU time 0.53 seconds
Started Jul 28 04:28:50 PM PDT 24
Finished Jul 28 04:28:51 PM PDT 24
Peak memory 182400 kb
Host smart-a736ad28-b6b2-4817-a0da-a5b2c9dbc0b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590616871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.3590616871
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.3788942722
Short name T542
Test name
Test status
Simulation time 50414104 ps
CPU time 0.54 seconds
Started Jul 28 04:28:48 PM PDT 24
Finished Jul 28 04:28:49 PM PDT 24
Peak memory 182644 kb
Host smart-09fef87a-26b9-412b-bd91-3be094bd6835
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788942722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.3788942722
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.643597917
Short name T531
Test name
Test status
Simulation time 15821243 ps
CPU time 0.54 seconds
Started Jul 28 04:28:51 PM PDT 24
Finished Jul 28 04:28:51 PM PDT 24
Peak memory 182572 kb
Host smart-08521603-e8a5-451d-a93f-b56eabe5f779
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643597917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.643597917
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.523262258
Short name T91
Test name
Test status
Simulation time 26015946 ps
CPU time 0.67 seconds
Started Jul 28 04:21:50 PM PDT 24
Finished Jul 28 04:21:51 PM PDT 24
Peak memory 182756 kb
Host smart-740d33cd-204f-45a0-bced-b33b9d499adf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523262258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alias
ing.523262258
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.2061647442
Short name T99
Test name
Test status
Simulation time 292224598 ps
CPU time 3.1 seconds
Started Jul 28 04:24:59 PM PDT 24
Finished Jul 28 04:25:03 PM PDT 24
Peak memory 191560 kb
Host smart-b3b20b8d-ddf7-4a92-af6d-74bd318df69c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061647442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.2061647442
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.1376100896
Short name T87
Test name
Test status
Simulation time 20244086 ps
CPU time 0.62 seconds
Started Jul 28 04:23:20 PM PDT 24
Finished Jul 28 04:23:21 PM PDT 24
Peak memory 182764 kb
Host smart-7719df78-5fcc-4adf-9944-56f93670fd8c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376100896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.1376100896
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.36015991
Short name T575
Test name
Test status
Simulation time 69544059 ps
CPU time 0.68 seconds
Started Jul 28 04:25:15 PM PDT 24
Finished Jul 28 04:25:17 PM PDT 24
Peak memory 194572 kb
Host smart-ca9c7d56-7121-492f-92fa-d52b5d9caf2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36015991 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.36015991
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.1857688789
Short name T44
Test name
Test status
Simulation time 22811647 ps
CPU time 0.54 seconds
Started Jul 28 04:25:15 PM PDT 24
Finished Jul 28 04:25:16 PM PDT 24
Peak memory 182520 kb
Host smart-ad1907d6-bbe8-497b-88ba-bd0132130502
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857688789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.1857688789
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.4041474525
Short name T483
Test name
Test status
Simulation time 31269300 ps
CPU time 0.6 seconds
Started Jul 28 04:24:49 PM PDT 24
Finished Jul 28 04:24:50 PM PDT 24
Peak memory 180852 kb
Host smart-fced3d76-1c7f-4b6e-bcbb-bd3f37510e62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041474525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.4041474525
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.718077978
Short name T97
Test name
Test status
Simulation time 123328967 ps
CPU time 0.76 seconds
Started Jul 28 04:25:10 PM PDT 24
Finished Jul 28 04:25:11 PM PDT 24
Peak memory 191680 kb
Host smart-4a1f23d6-fa11-4d4c-a914-52fc7425a716
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718077978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_tim
er_same_csr_outstanding.718077978
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.4133085306
Short name T502
Test name
Test status
Simulation time 140158318 ps
CPU time 2.18 seconds
Started Jul 28 04:25:49 PM PDT 24
Finished Jul 28 04:25:52 PM PDT 24
Peak memory 197492 kb
Host smart-827aab79-dd24-4370-a381-6390d10c1f75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133085306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.4133085306
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.1861598598
Short name T514
Test name
Test status
Simulation time 81266344 ps
CPU time 0.74 seconds
Started Jul 28 04:24:37 PM PDT 24
Finished Jul 28 04:24:38 PM PDT 24
Peak memory 182860 kb
Host smart-40fcd259-9568-4ee6-9afe-46fe5533924a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861598598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.1861598598
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.886279803
Short name T547
Test name
Test status
Simulation time 16560579 ps
CPU time 0.54 seconds
Started Jul 28 04:28:51 PM PDT 24
Finished Jul 28 04:28:51 PM PDT 24
Peak memory 182108 kb
Host smart-c347e605-48ae-4c4a-be35-31ab8ac50d89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886279803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.886279803
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.2153859119
Short name T494
Test name
Test status
Simulation time 296860700 ps
CPU time 0.56 seconds
Started Jul 28 04:28:50 PM PDT 24
Finished Jul 28 04:28:51 PM PDT 24
Peak memory 182636 kb
Host smart-aaeb439d-ecf2-4765-99e3-c89c02aa28ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153859119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.2153859119
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.1974661476
Short name T451
Test name
Test status
Simulation time 42165533 ps
CPU time 0.55 seconds
Started Jul 28 04:28:57 PM PDT 24
Finished Jul 28 04:28:57 PM PDT 24
Peak memory 182652 kb
Host smart-f0f4db1e-2670-4355-bddb-a6cd86398d28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974661476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.1974661476
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3454211616
Short name T462
Test name
Test status
Simulation time 41359917 ps
CPU time 0.51 seconds
Started Jul 28 04:28:47 PM PDT 24
Finished Jul 28 04:28:48 PM PDT 24
Peak memory 182128 kb
Host smart-dfd54b59-804a-4cf9-a01b-763cef269f41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454211616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.3454211616
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.3739833976
Short name T525
Test name
Test status
Simulation time 42936529 ps
CPU time 0.55 seconds
Started Jul 28 04:28:47 PM PDT 24
Finished Jul 28 04:28:48 PM PDT 24
Peak memory 182828 kb
Host smart-06c67d3e-bda7-4663-a6a8-c1f790203ea4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739833976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.3739833976
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.1024609292
Short name T453
Test name
Test status
Simulation time 41458059 ps
CPU time 0.6 seconds
Started Jul 28 04:28:48 PM PDT 24
Finished Jul 28 04:28:49 PM PDT 24
Peak memory 182664 kb
Host smart-9e5dd572-a691-4dfd-8990-d83c60f48b4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024609292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.1024609292
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.4223563514
Short name T458
Test name
Test status
Simulation time 30759237 ps
CPU time 0.57 seconds
Started Jul 28 04:28:53 PM PDT 24
Finished Jul 28 04:28:54 PM PDT 24
Peak memory 182088 kb
Host smart-1d280136-bc39-4643-89bb-9d84b710806e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223563514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.4223563514
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.62924465
Short name T493
Test name
Test status
Simulation time 37841029 ps
CPU time 0.52 seconds
Started Jul 28 04:28:47 PM PDT 24
Finished Jul 28 04:28:48 PM PDT 24
Peak memory 182612 kb
Host smart-a9d319ca-9732-44b8-b372-0171a565e8bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62924465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.62924465
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.1310128446
Short name T468
Test name
Test status
Simulation time 155348529 ps
CPU time 0.56 seconds
Started Jul 28 04:29:01 PM PDT 24
Finished Jul 28 04:29:01 PM PDT 24
Peak memory 182676 kb
Host smart-fab4ee3d-2031-4eac-956f-b0968ebd49e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310128446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.1310128446
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.1255939888
Short name T499
Test name
Test status
Simulation time 15940998 ps
CPU time 0.56 seconds
Started Jul 28 04:29:03 PM PDT 24
Finished Jul 28 04:29:03 PM PDT 24
Peak memory 182584 kb
Host smart-08b0d562-f2e4-46cb-95cb-2399e56ad2ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255939888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.1255939888
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1477161350
Short name T556
Test name
Test status
Simulation time 13645070 ps
CPU time 0.61 seconds
Started Jul 28 04:24:44 PM PDT 24
Finished Jul 28 04:24:45 PM PDT 24
Peak memory 181760 kb
Host smart-f1d9c5c1-ba3b-4612-b5e5-2c34028ea252
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477161350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.1477161350
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.3394767140
Short name T479
Test name
Test status
Simulation time 103813645 ps
CPU time 1.52 seconds
Started Jul 28 04:21:09 PM PDT 24
Finished Jul 28 04:21:11 PM PDT 24
Peak memory 191432 kb
Host smart-0e72354f-29c9-45a1-ae50-e7e71aa3f3f0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394767140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.3394767140
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2861135561
Short name T506
Test name
Test status
Simulation time 38608785 ps
CPU time 0.53 seconds
Started Jul 28 04:24:44 PM PDT 24
Finished Jul 28 04:24:45 PM PDT 24
Peak memory 181688 kb
Host smart-5d0a4654-7ae6-4dee-8b54-a5733dc6e553
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861135561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.2861135561
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.940859768
Short name T505
Test name
Test status
Simulation time 51448968 ps
CPU time 1.06 seconds
Started Jul 28 04:20:55 PM PDT 24
Finished Jul 28 04:20:56 PM PDT 24
Peak memory 197412 kb
Host smart-b684fc8e-f453-4a0a-84c8-5cfb04a091b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940859768 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.940859768
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2654203209
Short name T528
Test name
Test status
Simulation time 15588972 ps
CPU time 0.56 seconds
Started Jul 28 04:24:53 PM PDT 24
Finished Jul 28 04:24:54 PM PDT 24
Peak memory 182440 kb
Host smart-b04f5a06-cee8-4a25-a0ad-7eac89e06287
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654203209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.2654203209
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.542757172
Short name T564
Test name
Test status
Simulation time 28388182 ps
CPU time 0.54 seconds
Started Jul 28 04:21:38 PM PDT 24
Finished Jul 28 04:21:39 PM PDT 24
Peak memory 182684 kb
Host smart-4ed3e366-9410-4259-a6f0-07f6282f4004
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542757172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.542757172
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.1551975021
Short name T568
Test name
Test status
Simulation time 90073586 ps
CPU time 0.76 seconds
Started Jul 28 04:24:56 PM PDT 24
Finished Jul 28 04:24:57 PM PDT 24
Peak memory 192312 kb
Host smart-496a8406-2d1a-41e1-acb0-3427656d2665
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551975021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.1551975021
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.3755492344
Short name T562
Test name
Test status
Simulation time 32670466 ps
CPU time 0.84 seconds
Started Jul 28 04:20:30 PM PDT 24
Finished Jul 28 04:20:31 PM PDT 24
Peak memory 196600 kb
Host smart-59fea5a7-771a-422c-b92a-fe51429fc79c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755492344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.3755492344
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.1491246763
Short name T101
Test name
Test status
Simulation time 279898099 ps
CPU time 1.08 seconds
Started Jul 28 04:23:37 PM PDT 24
Finished Jul 28 04:23:39 PM PDT 24
Peak memory 194684 kb
Host smart-bd15b475-d8d4-49d1-8c68-8ccf215d8ca6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491246763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.1491246763
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.2298402165
Short name T472
Test name
Test status
Simulation time 14860383 ps
CPU time 0.55 seconds
Started Jul 28 04:29:06 PM PDT 24
Finished Jul 28 04:29:06 PM PDT 24
Peak memory 182584 kb
Host smart-f57425ea-0635-4733-ac10-9cc9e255dead
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298402165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.2298402165
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.992704819
Short name T577
Test name
Test status
Simulation time 18433127 ps
CPU time 0.55 seconds
Started Jul 28 04:29:05 PM PDT 24
Finished Jul 28 04:29:06 PM PDT 24
Peak memory 182564 kb
Host smart-fcf2cd2b-bf2f-456b-ab50-ce5d8b3dfcb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992704819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.992704819
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.3878690265
Short name T481
Test name
Test status
Simulation time 62624542 ps
CPU time 0.51 seconds
Started Jul 28 04:28:58 PM PDT 24
Finished Jul 28 04:28:58 PM PDT 24
Peak memory 182120 kb
Host smart-5521efdf-c584-4127-b07d-219c321a4bad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878690265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.3878690265
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.2608758590
Short name T495
Test name
Test status
Simulation time 77704706 ps
CPU time 0.57 seconds
Started Jul 28 04:29:16 PM PDT 24
Finished Jul 28 04:29:16 PM PDT 24
Peak memory 182664 kb
Host smart-7aa7674a-250b-43a0-8c2e-3c032cc0a7fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608758590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.2608758590
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.3370168212
Short name T527
Test name
Test status
Simulation time 19301486 ps
CPU time 0.52 seconds
Started Jul 28 04:28:51 PM PDT 24
Finished Jul 28 04:28:52 PM PDT 24
Peak memory 182052 kb
Host smart-a1caac90-4fd1-48a2-97ba-193e2a99784f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370168212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.3370168212
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1172225070
Short name T548
Test name
Test status
Simulation time 112742102 ps
CPU time 0.57 seconds
Started Jul 28 04:28:52 PM PDT 24
Finished Jul 28 04:28:53 PM PDT 24
Peak memory 183060 kb
Host smart-116599a9-9754-4936-88fc-ac16e24e05b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172225070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.1172225070
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.1786088845
Short name T456
Test name
Test status
Simulation time 13987556 ps
CPU time 0.53 seconds
Started Jul 28 04:28:51 PM PDT 24
Finished Jul 28 04:28:52 PM PDT 24
Peak memory 182072 kb
Host smart-f0909583-48b1-4868-bb3d-38908259da60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786088845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.1786088845
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.1611345868
Short name T473
Test name
Test status
Simulation time 10636454 ps
CPU time 0.51 seconds
Started Jul 28 04:29:02 PM PDT 24
Finished Jul 28 04:29:03 PM PDT 24
Peak memory 182108 kb
Host smart-d9ae01f2-7d0c-4c6b-b0cc-f1c908a4b01a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611345868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.1611345868
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.3828796972
Short name T454
Test name
Test status
Simulation time 40763922 ps
CPU time 0.53 seconds
Started Jul 28 04:28:58 PM PDT 24
Finished Jul 28 04:28:59 PM PDT 24
Peak memory 182540 kb
Host smart-fd7623c7-51a0-4a0c-9faf-66faa97b1a20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828796972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.3828796972
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.3419045073
Short name T552
Test name
Test status
Simulation time 14610341 ps
CPU time 0.54 seconds
Started Jul 28 04:28:55 PM PDT 24
Finished Jul 28 04:28:56 PM PDT 24
Peak memory 182492 kb
Host smart-5f679afb-c629-4d15-9a1d-c9d7b29e8e9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419045073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.3419045073
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.647017559
Short name T549
Test name
Test status
Simulation time 139722052 ps
CPU time 1 seconds
Started Jul 28 04:22:13 PM PDT 24
Finished Jul 28 04:22:14 PM PDT 24
Peak memory 197348 kb
Host smart-5d44507a-9202-4af6-b25e-b0557dbe6b0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647017559 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.647017559
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.3999954690
Short name T80
Test name
Test status
Simulation time 18697532 ps
CPU time 0.58 seconds
Started Jul 28 04:25:00 PM PDT 24
Finished Jul 28 04:25:01 PM PDT 24
Peak memory 181556 kb
Host smart-86d2cd68-71e6-4848-8d68-9ae5a3d4cb99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999954690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.3999954690
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1152924686
Short name T461
Test name
Test status
Simulation time 39071399 ps
CPU time 0.54 seconds
Started Jul 28 04:25:31 PM PDT 24
Finished Jul 28 04:25:32 PM PDT 24
Peak memory 182440 kb
Host smart-dd40f057-a678-497e-b0d5-2709c10cd51f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152924686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.1152924686
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2757056218
Short name T59
Test name
Test status
Simulation time 59111541 ps
CPU time 0.7 seconds
Started Jul 28 04:25:31 PM PDT 24
Finished Jul 28 04:25:32 PM PDT 24
Peak memory 193248 kb
Host smart-4e762d96-def9-4e88-a8cf-61c53bfde3f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757056218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.2757056218
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.883021898
Short name T504
Test name
Test status
Simulation time 333252724 ps
CPU time 2.78 seconds
Started Jul 28 04:24:49 PM PDT 24
Finished Jul 28 04:24:53 PM PDT 24
Peak memory 195956 kb
Host smart-e5597b3c-815c-4136-84f3-bc1ecc6f4a87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883021898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.883021898
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3393355993
Short name T469
Test name
Test status
Simulation time 87951902 ps
CPU time 0.88 seconds
Started Jul 28 04:20:28 PM PDT 24
Finished Jul 28 04:20:29 PM PDT 24
Peak memory 194584 kb
Host smart-d55e73a1-0ae9-4572-8b27-5710073cc8bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393355993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.3393355993
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.1458283544
Short name T477
Test name
Test status
Simulation time 19873913 ps
CPU time 0.67 seconds
Started Jul 28 04:23:37 PM PDT 24
Finished Jul 28 04:23:38 PM PDT 24
Peak memory 193376 kb
Host smart-0c18aa65-182e-4f2a-807f-16bcd39db5f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458283544 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.1458283544
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1149281329
Short name T573
Test name
Test status
Simulation time 30804102 ps
CPU time 0.54 seconds
Started Jul 28 04:24:51 PM PDT 24
Finished Jul 28 04:24:52 PM PDT 24
Peak memory 182508 kb
Host smart-dee9eba0-7af8-4002-a2d9-040053d28451
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149281329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.1149281329
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.2338590113
Short name T522
Test name
Test status
Simulation time 20015486 ps
CPU time 0.56 seconds
Started Jul 28 04:24:53 PM PDT 24
Finished Jul 28 04:24:54 PM PDT 24
Peak memory 182616 kb
Host smart-63ceafe3-c673-498b-b3a1-0ae32b3e9174
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338590113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.2338590113
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.1157360204
Short name T96
Test name
Test status
Simulation time 168999217 ps
CPU time 0.73 seconds
Started Jul 28 04:24:55 PM PDT 24
Finished Jul 28 04:24:56 PM PDT 24
Peak memory 192192 kb
Host smart-59324bd9-c9fc-46c0-8a04-44ef0692eb3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157360204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.1157360204
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.652708228
Short name T485
Test name
Test status
Simulation time 370897665 ps
CPU time 1.26 seconds
Started Jul 28 04:22:52 PM PDT 24
Finished Jul 28 04:22:53 PM PDT 24
Peak memory 197148 kb
Host smart-e1fbcdc2-3978-423f-9fa2-504710691443
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652708228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.652708228
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.4280798508
Short name T482
Test name
Test status
Simulation time 113884129 ps
CPU time 1.37 seconds
Started Jul 28 04:25:00 PM PDT 24
Finished Jul 28 04:25:02 PM PDT 24
Peak memory 194344 kb
Host smart-a7eece74-4bea-4af4-8149-9529b0dd517f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280798508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.4280798508
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.909305365
Short name T518
Test name
Test status
Simulation time 215137927 ps
CPU time 0.84 seconds
Started Jul 28 04:21:47 PM PDT 24
Finished Jul 28 04:21:48 PM PDT 24
Peak memory 196968 kb
Host smart-5dffe870-309a-4ffa-87dc-4fdd1f78bef0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909305365 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.909305365
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.1592588728
Short name T488
Test name
Test status
Simulation time 189741788 ps
CPU time 0.55 seconds
Started Jul 28 04:20:24 PM PDT 24
Finished Jul 28 04:20:25 PM PDT 24
Peak memory 182784 kb
Host smart-cc5a7706-ed78-4424-b3a0-af7870eea085
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592588728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.1592588728
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.2436780303
Short name T452
Test name
Test status
Simulation time 55618241 ps
CPU time 0.56 seconds
Started Jul 28 04:25:15 PM PDT 24
Finished Jul 28 04:25:16 PM PDT 24
Peak memory 182564 kb
Host smart-f9307c66-74ec-4d1f-89e7-3018ce714a0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436780303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.2436780303
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.94747323
Short name T565
Test name
Test status
Simulation time 27901358 ps
CPU time 0.7 seconds
Started Jul 28 04:25:27 PM PDT 24
Finished Jul 28 04:25:28 PM PDT 24
Peak memory 193516 kb
Host smart-9fbf7d88-5a8f-4a39-b36e-8c251f19bb32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94747323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_time
r_same_csr_outstanding.94747323
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.1546844534
Short name T515
Test name
Test status
Simulation time 39817798 ps
CPU time 1.9 seconds
Started Jul 28 04:20:31 PM PDT 24
Finished Jul 28 04:20:33 PM PDT 24
Peak memory 197860 kb
Host smart-c70a8b91-3541-4892-840a-efb627762437
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546844534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.1546844534
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.2103076375
Short name T550
Test name
Test status
Simulation time 63497291 ps
CPU time 0.79 seconds
Started Jul 28 04:25:15 PM PDT 24
Finished Jul 28 04:25:16 PM PDT 24
Peak memory 183324 kb
Host smart-06d4e37c-80c7-47c1-acc5-a34a97ddf2f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103076375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.2103076375
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3595553379
Short name T32
Test name
Test status
Simulation time 28503968 ps
CPU time 0.67 seconds
Started Jul 28 04:25:47 PM PDT 24
Finished Jul 28 04:25:48 PM PDT 24
Peak memory 194296 kb
Host smart-efdc405d-45d3-4550-806a-4c5d4e216ec4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595553379 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.3595553379
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.3621659546
Short name T555
Test name
Test status
Simulation time 22798732 ps
CPU time 0.55 seconds
Started Jul 28 04:23:11 PM PDT 24
Finished Jul 28 04:23:12 PM PDT 24
Peak memory 183120 kb
Host smart-2c74626a-bdad-4983-8e4c-d64173607833
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621659546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.3621659546
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.1576974902
Short name T470
Test name
Test status
Simulation time 14959366 ps
CPU time 0.53 seconds
Started Jul 28 04:25:07 PM PDT 24
Finished Jul 28 04:25:08 PM PDT 24
Peak memory 182296 kb
Host smart-db3f16d7-9375-470f-81fe-b6b6b6090db8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576974902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.1576974902
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.3967026460
Short name T551
Test name
Test status
Simulation time 609611470 ps
CPU time 0.72 seconds
Started Jul 28 04:25:32 PM PDT 24
Finished Jul 28 04:25:33 PM PDT 24
Peak memory 192860 kb
Host smart-3d58b633-44e4-4eee-8d28-2c601b3f7302
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967026460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.3967026460
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.4074803538
Short name T455
Test name
Test status
Simulation time 29709229 ps
CPU time 1.39 seconds
Started Jul 28 04:25:04 PM PDT 24
Finished Jul 28 04:25:05 PM PDT 24
Peak memory 197448 kb
Host smart-1715ea55-5c1c-4571-9010-adaa055d662f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074803538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.4074803538
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.834369551
Short name T102
Test name
Test status
Simulation time 104101939 ps
CPU time 1.28 seconds
Started Jul 28 04:21:58 PM PDT 24
Finished Jul 28 04:22:00 PM PDT 24
Peak memory 194424 kb
Host smart-054dd90c-d0b4-4398-953f-42410d15da98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834369551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_int
g_err.834369551
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3675410969
Short name T574
Test name
Test status
Simulation time 34977863 ps
CPU time 1.43 seconds
Started Jul 28 04:28:38 PM PDT 24
Finished Jul 28 04:28:40 PM PDT 24
Peak memory 197492 kb
Host smart-a7ede705-1e9a-47ca-9be5-891d5371d0a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675410969 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.3675410969
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.1741723448
Short name T526
Test name
Test status
Simulation time 23511199 ps
CPU time 0.59 seconds
Started Jul 28 04:21:06 PM PDT 24
Finished Jul 28 04:21:06 PM PDT 24
Peak memory 182760 kb
Host smart-fcab1f3a-3e2c-4ddf-b101-6576d7c7fdee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741723448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.1741723448
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.266876279
Short name T537
Test name
Test status
Simulation time 34206317 ps
CPU time 0.56 seconds
Started Jul 28 04:21:04 PM PDT 24
Finished Jul 28 04:21:05 PM PDT 24
Peak memory 182152 kb
Host smart-998b0549-c374-4a5b-95fd-d49d397bc77a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266876279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.266876279
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.2345854071
Short name T83
Test name
Test status
Simulation time 38262729 ps
CPU time 0.58 seconds
Started Jul 28 04:28:34 PM PDT 24
Finished Jul 28 04:28:35 PM PDT 24
Peak memory 191528 kb
Host smart-5f7de0f3-c8eb-4733-acdb-69e728b490ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345854071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.2345854071
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.2236475318
Short name T47
Test name
Test status
Simulation time 85403429 ps
CPU time 1.59 seconds
Started Jul 28 04:20:16 PM PDT 24
Finished Jul 28 04:20:18 PM PDT 24
Peak memory 197424 kb
Host smart-9deac765-4296-4479-9654-2d495503253c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236475318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.2236475318
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.1452258801
Short name T558
Test name
Test status
Simulation time 84101454 ps
CPU time 1.13 seconds
Started Jul 28 04:20:17 PM PDT 24
Finished Jul 28 04:20:18 PM PDT 24
Peak memory 195424 kb
Host smart-ed8b999e-1581-4442-b12d-8edbb0e1953f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452258801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.1452258801
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.277096024
Short name T380
Test name
Test status
Simulation time 59120096780 ps
CPU time 45.94 seconds
Started Jul 28 04:22:03 PM PDT 24
Finished Jul 28 04:22:50 PM PDT 24
Peak memory 183720 kb
Host smart-aa505837-be5f-4bba-9423-7202a09b1b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277096024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.277096024
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.3808165721
Short name T415
Test name
Test status
Simulation time 88802022122 ps
CPU time 138.99 seconds
Started Jul 28 04:25:07 PM PDT 24
Finished Jul 28 04:27:26 PM PDT 24
Peak memory 183212 kb
Host smart-7504b89b-8817-4787-a73a-d74806b5d961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808165721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.3808165721
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.4288035565
Short name T276
Test name
Test status
Simulation time 610767625295 ps
CPU time 557.83 seconds
Started Jul 28 04:23:50 PM PDT 24
Finished Jul 28 04:33:08 PM PDT 24
Peak memory 191552 kb
Host smart-79e16882-8ca4-4db3-b408-1dfedc779396
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288035565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
4288035565
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.30490022
Short name T275
Test name
Test status
Simulation time 73114143446 ps
CPU time 95.03 seconds
Started Jul 28 04:24:47 PM PDT 24
Finished Jul 28 04:26:23 PM PDT 24
Peak memory 192840 kb
Host smart-29ae7731-4848-4fb3-8e4a-73bb18dd0256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30490022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.30490022
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.2543171669
Short name T17
Test name
Test status
Simulation time 327557365 ps
CPU time 0.88 seconds
Started Jul 28 04:21:49 PM PDT 24
Finished Jul 28 04:21:50 PM PDT 24
Peak memory 214764 kb
Host smart-e58aa466-0b6f-4622-8a25-d866e0d56d5a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543171669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.2543171669
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.599294681
Short name T11
Test name
Test status
Simulation time 145943592327 ps
CPU time 226.41 seconds
Started Jul 28 04:25:22 PM PDT 24
Finished Jul 28 04:29:08 PM PDT 24
Peak memory 194292 kb
Host smart-f5153fcf-6a7c-4bdb-bbdc-225608b919d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599294681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.599294681
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.481592824
Short name T384
Test name
Test status
Simulation time 29850656614 ps
CPU time 24.24 seconds
Started Jul 28 04:23:11 PM PDT 24
Finished Jul 28 04:23:36 PM PDT 24
Peak memory 183396 kb
Host smart-913f72fb-a83f-42d4-af0d-ead4a563ffec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481592824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.481592824
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.681817336
Short name T362
Test name
Test status
Simulation time 173608476 ps
CPU time 0.83 seconds
Started Jul 28 04:25:44 PM PDT 24
Finished Jul 28 04:25:46 PM PDT 24
Peak memory 181736 kb
Host smart-091135c6-699c-434e-804d-5407e66d81af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681817336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.681817336
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.1517590058
Short name T418
Test name
Test status
Simulation time 144587916738 ps
CPU time 206.46 seconds
Started Jul 28 04:28:59 PM PDT 24
Finished Jul 28 04:32:26 PM PDT 24
Peak memory 191552 kb
Host smart-a6410c5b-fadf-414b-8543-edf3c88e8d4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517590058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.1517590058
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.1405354469
Short name T35
Test name
Test status
Simulation time 15553788091 ps
CPU time 166.46 seconds
Started Jul 28 04:29:01 PM PDT 24
Finished Jul 28 04:31:47 PM PDT 24
Peak memory 198148 kb
Host smart-d9afa6a1-ff5c-4027-8ce5-db02ee08fe60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405354469 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_reset.1405354469
Directory /workspace/10.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.rv_timer_random.635166997
Short name T287
Test name
Test status
Simulation time 91822755740 ps
CPU time 211.77 seconds
Started Jul 28 04:29:28 PM PDT 24
Finished Jul 28 04:33:00 PM PDT 24
Peak memory 191512 kb
Host smart-7a528d9a-22bc-4a9b-a49b-c1cca60cdaa6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635166997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.635166997
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.4247339022
Short name T216
Test name
Test status
Simulation time 623289613241 ps
CPU time 395.97 seconds
Started Jul 28 04:29:39 PM PDT 24
Finished Jul 28 04:36:15 PM PDT 24
Peak memory 191484 kb
Host smart-f407c8ea-8945-4383-97e7-262563af160b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247339022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.4247339022
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.2363619792
Short name T40
Test name
Test status
Simulation time 488843915398 ps
CPU time 266.45 seconds
Started Jul 28 04:29:30 PM PDT 24
Finished Jul 28 04:33:56 PM PDT 24
Peak memory 191552 kb
Host smart-1022aca4-184a-4bac-b000-0e101f13d8d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363619792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.2363619792
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.3648276057
Short name T298
Test name
Test status
Simulation time 381748936697 ps
CPU time 293.74 seconds
Started Jul 28 04:29:40 PM PDT 24
Finished Jul 28 04:34:34 PM PDT 24
Peak memory 194984 kb
Host smart-7e2ad010-c226-488a-80e1-9c1ba152bea9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648276057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.3648276057
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.4102671620
Short name T167
Test name
Test status
Simulation time 167655181839 ps
CPU time 362.09 seconds
Started Jul 28 04:29:48 PM PDT 24
Finished Jul 28 04:35:50 PM PDT 24
Peak memory 183532 kb
Host smart-d2847858-2b6e-4023-b434-33a8c19461fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102671620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.4102671620
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.246219867
Short name T312
Test name
Test status
Simulation time 92746968265 ps
CPU time 149.29 seconds
Started Jul 28 04:29:37 PM PDT 24
Finished Jul 28 04:32:07 PM PDT 24
Peak memory 191520 kb
Host smart-e09ca72c-0a7b-46e7-bc88-f10c73db8437
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246219867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.246219867
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.2503597547
Short name T235
Test name
Test status
Simulation time 27800341097 ps
CPU time 40.72 seconds
Started Jul 28 04:29:29 PM PDT 24
Finished Jul 28 04:30:09 PM PDT 24
Peak memory 183152 kb
Host smart-3edc0f8d-bf83-4434-bc8c-05f3dc551b76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503597547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.2503597547
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.2138273956
Short name T177
Test name
Test status
Simulation time 92513870690 ps
CPU time 157.55 seconds
Started Jul 28 04:28:54 PM PDT 24
Finished Jul 28 04:31:32 PM PDT 24
Peak memory 183304 kb
Host smart-43703cdb-a7fc-488a-baf7-6147e3f6ff86
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138273956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.2138273956
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.3530593165
Short name T349
Test name
Test status
Simulation time 8468899805 ps
CPU time 10.19 seconds
Started Jul 28 04:29:02 PM PDT 24
Finished Jul 28 04:29:12 PM PDT 24
Peak memory 183368 kb
Host smart-980d8a63-6e54-4f91-b711-ea90ae03d391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530593165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.3530593165
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.570598153
Short name T337
Test name
Test status
Simulation time 39687775362 ps
CPU time 103.55 seconds
Started Jul 28 04:29:07 PM PDT 24
Finished Jul 28 04:30:51 PM PDT 24
Peak memory 191576 kb
Host smart-2402e641-c3c3-4bf8-9569-9ed1148a9061
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570598153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.570598153
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.1263060742
Short name T136
Test name
Test status
Simulation time 121254461916 ps
CPU time 50.44 seconds
Started Jul 28 04:28:59 PM PDT 24
Finished Jul 28 04:29:49 PM PDT 24
Peak memory 183380 kb
Host smart-c2e502f9-02b6-4169-8e5e-d559c2145633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263060742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.1263060742
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/110.rv_timer_random.2046336262
Short name T54
Test name
Test status
Simulation time 38874609581 ps
CPU time 121.62 seconds
Started Jul 28 04:29:30 PM PDT 24
Finished Jul 28 04:31:32 PM PDT 24
Peak memory 191552 kb
Host smart-b7f98aa7-f773-4081-9008-73dcc0a1c6e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046336262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.2046336262
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.648568805
Short name T311
Test name
Test status
Simulation time 307520785349 ps
CPU time 1459.87 seconds
Started Jul 28 04:29:31 PM PDT 24
Finished Jul 28 04:53:51 PM PDT 24
Peak memory 191888 kb
Host smart-6a9e7179-e10f-4a1d-802a-1dae7c9a6c49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648568805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.648568805
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.1344887374
Short name T180
Test name
Test status
Simulation time 232611087486 ps
CPU time 95.9 seconds
Started Jul 28 04:29:37 PM PDT 24
Finished Jul 28 04:31:13 PM PDT 24
Peak memory 191564 kb
Host smart-31b57250-f80a-4c96-8fea-386660b5e959
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344887374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.1344887374
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.4123599815
Short name T406
Test name
Test status
Simulation time 50942289991 ps
CPU time 71.93 seconds
Started Jul 28 04:30:40 PM PDT 24
Finished Jul 28 04:31:52 PM PDT 24
Peak memory 183084 kb
Host smart-6038fa5a-7046-4c1e-beca-243748194c6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123599815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.4123599815
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.513166821
Short name T360
Test name
Test status
Simulation time 742243041259 ps
CPU time 195.27 seconds
Started Jul 28 04:29:03 PM PDT 24
Finished Jul 28 04:32:18 PM PDT 24
Peak memory 183712 kb
Host smart-d0a9b02d-fc4e-4cbc-9483-70902bdc3a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513166821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.513166821
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.2050063671
Short name T408
Test name
Test status
Simulation time 81092499074 ps
CPU time 38.21 seconds
Started Jul 28 04:29:05 PM PDT 24
Finished Jul 28 04:29:43 PM PDT 24
Peak memory 183312 kb
Host smart-3e034dea-5f33-46d7-9d1a-cb1de2ad3ff4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050063671 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.2050063671
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.84066999
Short name T107
Test name
Test status
Simulation time 2416229107775 ps
CPU time 2229.12 seconds
Started Jul 28 04:29:01 PM PDT 24
Finished Jul 28 05:06:10 PM PDT 24
Peak memory 191512 kb
Host smart-af737b7a-2812-4186-9f99-deb5caab49e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84066999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all.84066999
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/120.rv_timer_random.724175893
Short name T111
Test name
Test status
Simulation time 151737377719 ps
CPU time 263.86 seconds
Started Jul 28 04:29:29 PM PDT 24
Finished Jul 28 04:33:53 PM PDT 24
Peak memory 191576 kb
Host smart-0eb142de-0cfe-428f-a805-7ad52fcd024c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724175893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.724175893
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.2039885077
Short name T183
Test name
Test status
Simulation time 70576989783 ps
CPU time 126.88 seconds
Started Jul 28 04:29:39 PM PDT 24
Finished Jul 28 04:31:46 PM PDT 24
Peak memory 191516 kb
Host smart-5f4eedf9-d465-4d26-ab7a-639f2354e664
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039885077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.2039885077
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.321679477
Short name T262
Test name
Test status
Simulation time 615577037488 ps
CPU time 269.11 seconds
Started Jul 28 04:29:50 PM PDT 24
Finished Jul 28 04:34:19 PM PDT 24
Peak memory 191556 kb
Host smart-0625cbae-a219-4279-88fb-5ecaa7b9ca84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321679477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.321679477
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.2686205631
Short name T192
Test name
Test status
Simulation time 269277353013 ps
CPU time 122.31 seconds
Started Jul 28 04:29:45 PM PDT 24
Finished Jul 28 04:31:47 PM PDT 24
Peak memory 191572 kb
Host smart-be81f6d6-3f81-44ea-b6c3-7c2f0f9ead36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686205631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.2686205631
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.2299824200
Short name T256
Test name
Test status
Simulation time 86706484302 ps
CPU time 117.44 seconds
Started Jul 28 04:29:44 PM PDT 24
Finished Jul 28 04:31:41 PM PDT 24
Peak memory 183408 kb
Host smart-ef4ad694-a414-4743-8076-8b5846aa2a1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299824200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.2299824200
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.3583887312
Short name T307
Test name
Test status
Simulation time 48512102649 ps
CPU time 158.25 seconds
Started Jul 28 04:29:42 PM PDT 24
Finished Jul 28 04:32:20 PM PDT 24
Peak memory 183416 kb
Host smart-45c989fb-ab2a-466d-9218-786e734e9eda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583887312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.3583887312
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.2185215909
Short name T176
Test name
Test status
Simulation time 167021767069 ps
CPU time 649.76 seconds
Started Jul 28 04:29:41 PM PDT 24
Finished Jul 28 04:40:31 PM PDT 24
Peak memory 191728 kb
Host smart-264fb41e-9c13-40d1-a2f3-f2f9d23d2abc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185215909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.2185215909
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.885682194
Short name T103
Test name
Test status
Simulation time 636552882524 ps
CPU time 165.53 seconds
Started Jul 28 04:29:48 PM PDT 24
Finished Jul 28 04:32:34 PM PDT 24
Peak memory 191544 kb
Host smart-b6eb0e51-a237-4568-ae2b-2080f78f5758
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885682194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.885682194
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.560636781
Short name T122
Test name
Test status
Simulation time 544811149823 ps
CPU time 895.62 seconds
Started Jul 28 04:28:54 PM PDT 24
Finished Jul 28 04:43:49 PM PDT 24
Peak memory 183368 kb
Host smart-32529dac-1ed2-4770-a9a4-5baba333a210
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560636781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.rv_timer_cfg_update_on_fly.560636781
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.65727257
Short name T367
Test name
Test status
Simulation time 10003447182 ps
CPU time 13.76 seconds
Started Jul 28 04:28:53 PM PDT 24
Finished Jul 28 04:29:07 PM PDT 24
Peak memory 183356 kb
Host smart-2c107155-ee24-4a1a-a839-70cf5c1bf915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65727257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.65727257
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.949055388
Short name T173
Test name
Test status
Simulation time 536481205640 ps
CPU time 255.36 seconds
Started Jul 28 04:29:08 PM PDT 24
Finished Jul 28 04:33:23 PM PDT 24
Peak memory 191616 kb
Host smart-c223d88b-ba22-4f5a-b208-26ed413bf430
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949055388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.949055388
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.2111180887
Short name T255
Test name
Test status
Simulation time 37728381304 ps
CPU time 79 seconds
Started Jul 28 04:28:57 PM PDT 24
Finished Jul 28 04:30:16 PM PDT 24
Peak memory 183384 kb
Host smart-5a40a387-9692-441d-a33e-6920b9ef8ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111180887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.2111180887
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.2037173601
Short name T355
Test name
Test status
Simulation time 151520817033 ps
CPU time 217.58 seconds
Started Jul 28 04:28:58 PM PDT 24
Finished Jul 28 04:32:36 PM PDT 24
Peak memory 191560 kb
Host smart-c835c41d-45b4-4d09-9a8e-b334af5aeeab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037173601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.2037173601
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/130.rv_timer_random.186770772
Short name T304
Test name
Test status
Simulation time 198965049477 ps
CPU time 61.91 seconds
Started Jul 28 04:29:44 PM PDT 24
Finished Jul 28 04:30:46 PM PDT 24
Peak memory 183228 kb
Host smart-9eb31c78-cfd4-4eb2-b8b3-0b3d0c07d9d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186770772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.186770772
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.2781774402
Short name T189
Test name
Test status
Simulation time 110987060133 ps
CPU time 408.31 seconds
Started Jul 28 04:29:54 PM PDT 24
Finished Jul 28 04:36:43 PM PDT 24
Peak memory 191504 kb
Host smart-cf680ebb-dc02-4f3c-9804-c813f6da96db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781774402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.2781774402
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.1931318833
Short name T368
Test name
Test status
Simulation time 213098197734 ps
CPU time 61.04 seconds
Started Jul 28 04:29:33 PM PDT 24
Finished Jul 28 04:30:34 PM PDT 24
Peak memory 183356 kb
Host smart-1bbeaf17-16fc-4653-9b7c-3160b5c0c944
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931318833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.1931318833
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.463308942
Short name T395
Test name
Test status
Simulation time 38551454615 ps
CPU time 418.52 seconds
Started Jul 28 04:29:37 PM PDT 24
Finished Jul 28 04:36:35 PM PDT 24
Peak memory 183352 kb
Host smart-ef20e028-b3e6-466e-b711-60fe9191754a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463308942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.463308942
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.3867729724
Short name T120
Test name
Test status
Simulation time 71606388472 ps
CPU time 230.38 seconds
Started Jul 28 04:29:44 PM PDT 24
Finished Jul 28 04:33:34 PM PDT 24
Peak memory 191548 kb
Host smart-238cc66a-8264-4039-b4c8-b6d843f4699b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867729724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.3867729724
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.1717223550
Short name T132
Test name
Test status
Simulation time 72669385017 ps
CPU time 58.9 seconds
Started Jul 28 04:29:39 PM PDT 24
Finished Jul 28 04:30:38 PM PDT 24
Peak memory 191540 kb
Host smart-7a781650-a749-48de-bf1d-3e9fb8c02c9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717223550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.1717223550
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.38950136
Short name T129
Test name
Test status
Simulation time 137364913756 ps
CPU time 876.31 seconds
Started Jul 28 04:29:34 PM PDT 24
Finished Jul 28 04:44:10 PM PDT 24
Peak memory 191540 kb
Host smart-c1e7c896-31b3-42ac-a2eb-3d45ec4954c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38950136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.38950136
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.3235884772
Short name T440
Test name
Test status
Simulation time 467381060901 ps
CPU time 198.01 seconds
Started Jul 28 04:29:33 PM PDT 24
Finished Jul 28 04:32:51 PM PDT 24
Peak memory 191524 kb
Host smart-dc68d1f8-fa9a-4ba1-a083-f200ab037fee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235884772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.3235884772
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.2936480655
Short name T447
Test name
Test status
Simulation time 232593131556 ps
CPU time 411.59 seconds
Started Jul 28 04:29:11 PM PDT 24
Finished Jul 28 04:36:03 PM PDT 24
Peak memory 183344 kb
Host smart-fdb1cfad-7e93-4408-9b6b-378b95d00518
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936480655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.2936480655
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.589076685
Short name T366
Test name
Test status
Simulation time 412208573085 ps
CPU time 314.59 seconds
Started Jul 28 04:29:10 PM PDT 24
Finished Jul 28 04:34:24 PM PDT 24
Peak memory 183376 kb
Host smart-e96c29e1-5e6f-44f9-8c33-7ecf67a643b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589076685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.589076685
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.299927473
Short name T425
Test name
Test status
Simulation time 183900333160 ps
CPU time 148.75 seconds
Started Jul 28 04:28:57 PM PDT 24
Finished Jul 28 04:31:26 PM PDT 24
Peak memory 183332 kb
Host smart-e79857de-5428-4447-901d-25ce9b85fd8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299927473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.299927473
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.2577550460
Short name T207
Test name
Test status
Simulation time 47646946194 ps
CPU time 74.11 seconds
Started Jul 28 04:29:06 PM PDT 24
Finished Jul 28 04:30:20 PM PDT 24
Peak memory 191544 kb
Host smart-a80ce011-4b7b-416f-9db4-664a8ac5b271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577550460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.2577550460
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.2893068584
Short name T174
Test name
Test status
Simulation time 1754303832000 ps
CPU time 1198.64 seconds
Started Jul 28 04:28:59 PM PDT 24
Finished Jul 28 04:48:58 PM PDT 24
Peak memory 191536 kb
Host smart-e9a4033c-7988-4b65-b132-9edd6279dfaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893068584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.2893068584
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/140.rv_timer_random.3914616103
Short name T2
Test name
Test status
Simulation time 415329879378 ps
CPU time 496.49 seconds
Started Jul 28 04:29:55 PM PDT 24
Finished Jul 28 04:38:12 PM PDT 24
Peak memory 191512 kb
Host smart-092313bb-eff4-4512-aae8-2c307be9b760
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914616103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.3914616103
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.260900766
Short name T201
Test name
Test status
Simulation time 789826944692 ps
CPU time 343.23 seconds
Started Jul 28 04:29:31 PM PDT 24
Finished Jul 28 04:35:14 PM PDT 24
Peak memory 191524 kb
Host smart-07f55673-1074-460c-94c8-6c624236142d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260900766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.260900766
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.3690670432
Short name T329
Test name
Test status
Simulation time 331407281783 ps
CPU time 155.38 seconds
Started Jul 28 04:29:41 PM PDT 24
Finished Jul 28 04:32:17 PM PDT 24
Peak memory 183348 kb
Host smart-b6e33cc4-6c15-47c5-8cc4-9c3150c1a076
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690670432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.3690670432
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.1310222485
Short name T209
Test name
Test status
Simulation time 665423922027 ps
CPU time 374.95 seconds
Started Jul 28 04:29:45 PM PDT 24
Finished Jul 28 04:36:00 PM PDT 24
Peak memory 191504 kb
Host smart-15531c0e-604b-483c-94cf-cac180d272ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310222485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.1310222485
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.812981418
Short name T188
Test name
Test status
Simulation time 164651174783 ps
CPU time 330.94 seconds
Started Jul 28 04:29:40 PM PDT 24
Finished Jul 28 04:35:11 PM PDT 24
Peak memory 191516 kb
Host smart-cc119c9e-5604-4ba9-bc90-f3b7e742ed79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812981418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.812981418
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.1212938074
Short name T431
Test name
Test status
Simulation time 38432623620 ps
CPU time 19.4 seconds
Started Jul 28 04:29:42 PM PDT 24
Finished Jul 28 04:30:02 PM PDT 24
Peak memory 183316 kb
Host smart-71817e6d-1898-4483-a99b-d7bdaba37713
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212938074 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.1212938074
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.1768613229
Short name T148
Test name
Test status
Simulation time 21941890137 ps
CPU time 36.68 seconds
Started Jul 28 04:29:33 PM PDT 24
Finished Jul 28 04:30:10 PM PDT 24
Peak memory 191544 kb
Host smart-21093cac-ad67-4eef-aeab-5ac93cfb91b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768613229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.1768613229
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.957858769
Short name T403
Test name
Test status
Simulation time 280513972874 ps
CPU time 245.37 seconds
Started Jul 28 04:29:12 PM PDT 24
Finished Jul 28 04:33:18 PM PDT 24
Peak memory 183332 kb
Host smart-c341263c-4fec-4579-bb2c-5f09a1a3ce68
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957858769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.rv_timer_cfg_update_on_fly.957858769
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.3520491820
Short name T438
Test name
Test status
Simulation time 171133594546 ps
CPU time 140.37 seconds
Started Jul 28 04:28:57 PM PDT 24
Finished Jul 28 04:31:17 PM PDT 24
Peak memory 183500 kb
Host smart-ba19e89f-38e4-4e8e-b9fa-ddff5fed0f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520491820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.3520491820
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.3524079781
Short name T175
Test name
Test status
Simulation time 389487160487 ps
CPU time 136.41 seconds
Started Jul 28 04:29:15 PM PDT 24
Finished Jul 28 04:31:32 PM PDT 24
Peak memory 191560 kb
Host smart-f6157a66-87b6-4835-b657-c1fbe77fe8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524079781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.3524079781
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.4031918125
Short name T105
Test name
Test status
Simulation time 876494579462 ps
CPU time 488.11 seconds
Started Jul 28 04:29:04 PM PDT 24
Finished Jul 28 04:37:12 PM PDT 24
Peak memory 191560 kb
Host smart-257eb373-0be7-437e-b4e5-d1edb624367f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031918125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.4031918125
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/151.rv_timer_random.3585378754
Short name T205
Test name
Test status
Simulation time 94450023220 ps
CPU time 71.43 seconds
Started Jul 28 04:29:32 PM PDT 24
Finished Jul 28 04:30:44 PM PDT 24
Peak memory 191536 kb
Host smart-83a9c169-5344-4896-80cc-ab12f6d1873b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585378754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.3585378754
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.2152093032
Short name T198
Test name
Test status
Simulation time 27632827239 ps
CPU time 26.87 seconds
Started Jul 28 04:29:49 PM PDT 24
Finished Jul 28 04:30:16 PM PDT 24
Peak memory 192748 kb
Host smart-c66a0b74-7226-4166-8336-7bbcc81d92ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152093032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.2152093032
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.3929052608
Short name T225
Test name
Test status
Simulation time 64144476793 ps
CPU time 116.3 seconds
Started Jul 28 04:29:56 PM PDT 24
Finished Jul 28 04:31:52 PM PDT 24
Peak memory 191536 kb
Host smart-66f2806b-7762-47b2-8e95-40a2ec027153
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929052608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.3929052608
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.331500285
Short name T163
Test name
Test status
Simulation time 477060942927 ps
CPU time 338.77 seconds
Started Jul 28 04:29:48 PM PDT 24
Finished Jul 28 04:35:26 PM PDT 24
Peak memory 191532 kb
Host smart-25a6fdc9-3995-4832-b247-b216b5aa5e47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331500285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.331500285
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.3462756914
Short name T338
Test name
Test status
Simulation time 12868152838 ps
CPU time 22.91 seconds
Started Jul 28 04:29:48 PM PDT 24
Finished Jul 28 04:30:11 PM PDT 24
Peak memory 183400 kb
Host smart-7bc3099d-49b3-4a3e-968f-05d88bf4b6a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462756914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.3462756914
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.1590415120
Short name T302
Test name
Test status
Simulation time 18504980844 ps
CPU time 6.47 seconds
Started Jul 28 04:29:43 PM PDT 24
Finished Jul 28 04:29:50 PM PDT 24
Peak memory 183504 kb
Host smart-b1e1ae3e-898f-42d7-ac39-6e15f7139c3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590415120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.1590415120
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.3672748347
Short name T341
Test name
Test status
Simulation time 610527732505 ps
CPU time 309.19 seconds
Started Jul 28 04:29:03 PM PDT 24
Finished Jul 28 04:34:12 PM PDT 24
Peak memory 183324 kb
Host smart-335f6c21-6121-4b7c-8420-69ff04298837
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672748347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.3672748347
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.42012764
Short name T371
Test name
Test status
Simulation time 712020851 ps
CPU time 1.66 seconds
Started Jul 28 04:29:15 PM PDT 24
Finished Jul 28 04:29:17 PM PDT 24
Peak memory 183128 kb
Host smart-cfdcfd5e-46cf-43a5-b7db-fc7edfd00121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42012764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.42012764
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.1315502663
Short name T241
Test name
Test status
Simulation time 384596808513 ps
CPU time 383.73 seconds
Started Jul 28 04:29:04 PM PDT 24
Finished Jul 28 04:35:28 PM PDT 24
Peak memory 193828 kb
Host smart-f6a64bdf-b88f-4977-b092-5d734c35a613
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315502663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.1315502663
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.4066311405
Short name T369
Test name
Test status
Simulation time 193120817 ps
CPU time 0.86 seconds
Started Jul 28 04:29:08 PM PDT 24
Finished Jul 28 04:29:09 PM PDT 24
Peak memory 183128 kb
Host smart-fbf058ae-5569-43ea-808f-c0d90e104b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066311405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.4066311405
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.3119235277
Short name T301
Test name
Test status
Simulation time 205604017871 ps
CPU time 1270.95 seconds
Started Jul 28 04:29:09 PM PDT 24
Finished Jul 28 04:50:20 PM PDT 24
Peak memory 196344 kb
Host smart-9c1eef71-948b-4108-8755-cf1d84f26efa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119235277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.3119235277
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/161.rv_timer_random.3137110038
Short name T53
Test name
Test status
Simulation time 382374477323 ps
CPU time 267.11 seconds
Started Jul 28 04:29:51 PM PDT 24
Finished Jul 28 04:34:18 PM PDT 24
Peak memory 191504 kb
Host smart-fb697788-6ad5-4d4d-9d87-ee5d56459928
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137110038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.3137110038
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.1494863579
Short name T242
Test name
Test status
Simulation time 51448741395 ps
CPU time 87.08 seconds
Started Jul 28 04:29:45 PM PDT 24
Finished Jul 28 04:31:12 PM PDT 24
Peak memory 191532 kb
Host smart-9608e312-a7fb-4038-a83f-ffd807bebd78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494863579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.1494863579
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.3611149746
Short name T234
Test name
Test status
Simulation time 79085900192 ps
CPU time 24.29 seconds
Started Jul 28 04:29:55 PM PDT 24
Finished Jul 28 04:30:20 PM PDT 24
Peak memory 183176 kb
Host smart-dcc48215-598b-4422-bd39-0c6d438f8cfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611149746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.3611149746
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.2077979933
Short name T117
Test name
Test status
Simulation time 164553972181 ps
CPU time 298.12 seconds
Started Jul 28 04:29:55 PM PDT 24
Finished Jul 28 04:34:53 PM PDT 24
Peak memory 191560 kb
Host smart-d973489c-5ece-46ca-a39f-66a3e24178b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077979933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.2077979933
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.3086126110
Short name T211
Test name
Test status
Simulation time 2716992241131 ps
CPU time 816.51 seconds
Started Jul 28 04:29:42 PM PDT 24
Finished Jul 28 04:43:18 PM PDT 24
Peak memory 191552 kb
Host smart-86018243-de58-477f-be22-79b46e66b1b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086126110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.3086126110
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.3171752420
Short name T219
Test name
Test status
Simulation time 188228689017 ps
CPU time 290.15 seconds
Started Jul 28 04:29:52 PM PDT 24
Finished Jul 28 04:34:43 PM PDT 24
Peak memory 191560 kb
Host smart-b28447e5-fa86-4e0e-8d48-c2c6e3a6809b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171752420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.3171752420
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.2876330571
Short name T196
Test name
Test status
Simulation time 155957036967 ps
CPU time 825.97 seconds
Started Jul 28 04:29:49 PM PDT 24
Finished Jul 28 04:43:35 PM PDT 24
Peak memory 191500 kb
Host smart-ed6eb9a8-2c47-4b44-b85f-b0043c759043
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876330571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.2876330571
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.2138784603
Short name T56
Test name
Test status
Simulation time 216562832346 ps
CPU time 353.58 seconds
Started Jul 28 04:29:09 PM PDT 24
Finished Jul 28 04:35:03 PM PDT 24
Peak memory 183348 kb
Host smart-0452398a-fa1d-4720-8e7a-092375ec51dd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138784603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.2138784603
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.3338539012
Short name T428
Test name
Test status
Simulation time 30582264478 ps
CPU time 48.02 seconds
Started Jul 28 04:29:04 PM PDT 24
Finished Jul 28 04:29:52 PM PDT 24
Peak memory 183416 kb
Host smart-1e31602a-3e6c-4c5e-878d-9108236cc744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338539012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.3338539012
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.1088627690
Short name T227
Test name
Test status
Simulation time 36836999352 ps
CPU time 15.41 seconds
Started Jul 28 04:29:12 PM PDT 24
Finished Jul 28 04:29:28 PM PDT 24
Peak memory 183352 kb
Host smart-61c4a2dd-7b00-4f7f-97ac-86782db37240
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088627690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.1088627690
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.1339428242
Short name T404
Test name
Test status
Simulation time 1594497554 ps
CPU time 2.29 seconds
Started Jul 28 04:29:19 PM PDT 24
Finished Jul 28 04:29:21 PM PDT 24
Peak memory 183252 kb
Host smart-2b3dd8d4-19ce-4083-ad19-a7927d353579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339428242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.1339428242
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.752478447
Short name T442
Test name
Test status
Simulation time 388029358850 ps
CPU time 420.24 seconds
Started Jul 28 04:29:51 PM PDT 24
Finished Jul 28 04:36:51 PM PDT 24
Peak memory 191552 kb
Host smart-a2707cce-fb50-4583-92ee-d2e5d8b4f1f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752478447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.752478447
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.2561577501
Short name T274
Test name
Test status
Simulation time 123102853459 ps
CPU time 58.67 seconds
Started Jul 28 04:29:43 PM PDT 24
Finished Jul 28 04:30:42 PM PDT 24
Peak memory 191512 kb
Host smart-1d1f7bd1-fa64-4dcb-82d7-4e3f45b6aa26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561577501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.2561577501
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.3103083664
Short name T140
Test name
Test status
Simulation time 83174819132 ps
CPU time 37.94 seconds
Started Jul 28 04:29:45 PM PDT 24
Finished Jul 28 04:30:23 PM PDT 24
Peak memory 183364 kb
Host smart-0b7003c4-871d-4213-ba5a-062added7666
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103083664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.3103083664
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.3229541909
Short name T75
Test name
Test status
Simulation time 207359852524 ps
CPU time 176.55 seconds
Started Jul 28 04:29:53 PM PDT 24
Finished Jul 28 04:32:50 PM PDT 24
Peak memory 191564 kb
Host smart-fa2854df-6d9a-4460-baeb-c9bf569135c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229541909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.3229541909
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.2811415453
Short name T184
Test name
Test status
Simulation time 1328537915286 ps
CPU time 1721.52 seconds
Started Jul 28 04:29:57 PM PDT 24
Finished Jul 28 04:58:39 PM PDT 24
Peak memory 191516 kb
Host smart-2d268809-f985-480e-a4bd-289e832f16a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811415453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.2811415453
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.1598447244
Short name T187
Test name
Test status
Simulation time 72575208762 ps
CPU time 104.7 seconds
Started Jul 28 04:29:49 PM PDT 24
Finished Jul 28 04:31:34 PM PDT 24
Peak memory 195256 kb
Host smart-0c810aba-f592-4d14-b151-c436a4a2b50c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598447244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.1598447244
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.3601720417
Short name T20
Test name
Test status
Simulation time 115638305805 ps
CPU time 97.72 seconds
Started Jul 28 04:29:16 PM PDT 24
Finished Jul 28 04:30:54 PM PDT 24
Peak memory 183368 kb
Host smart-3a495e9a-f2d3-4c41-952a-9d98b04122fd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601720417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.3601720417
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.782815743
Short name T353
Test name
Test status
Simulation time 218615648249 ps
CPU time 80.35 seconds
Started Jul 28 04:28:59 PM PDT 24
Finished Jul 28 04:30:20 PM PDT 24
Peak memory 183428 kb
Host smart-a0ef9dfb-401b-4167-818f-63f7309b4aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782815743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.782815743
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.3267397370
Short name T150
Test name
Test status
Simulation time 320915905216 ps
CPU time 1591.98 seconds
Started Jul 28 04:29:15 PM PDT 24
Finished Jul 28 04:55:47 PM PDT 24
Peak memory 191576 kb
Host smart-9db3e21b-8665-4a9a-b715-2eea7cd60a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267397370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.3267397370
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/180.rv_timer_random.1119267997
Short name T125
Test name
Test status
Simulation time 376957635356 ps
CPU time 690.52 seconds
Started Jul 28 04:29:58 PM PDT 24
Finished Jul 28 04:41:28 PM PDT 24
Peak memory 191732 kb
Host smart-b7abdf42-a1e1-4eb6-a9c8-0e52f0cf96a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119267997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.1119267997
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.818782303
Short name T322
Test name
Test status
Simulation time 620595279882 ps
CPU time 545.28 seconds
Started Jul 28 04:29:59 PM PDT 24
Finished Jul 28 04:39:04 PM PDT 24
Peak memory 191528 kb
Host smart-df02b319-809d-4277-ba95-2edfa06243ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818782303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.818782303
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.3805201296
Short name T331
Test name
Test status
Simulation time 694175235484 ps
CPU time 365.48 seconds
Started Jul 28 04:29:54 PM PDT 24
Finished Jul 28 04:36:00 PM PDT 24
Peak memory 191556 kb
Host smart-5ef59d32-27d6-41da-8ccd-2a2208cec434
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805201296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.3805201296
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.183091680
Short name T144
Test name
Test status
Simulation time 191018706029 ps
CPU time 559.5 seconds
Started Jul 28 04:29:55 PM PDT 24
Finished Jul 28 04:39:14 PM PDT 24
Peak memory 191572 kb
Host smart-8c44a64c-4f0e-4ee0-ab36-01a67c30ae67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183091680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.183091680
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.1711185341
Short name T433
Test name
Test status
Simulation time 243342469478 ps
CPU time 285.61 seconds
Started Jul 28 04:29:56 PM PDT 24
Finished Jul 28 04:34:41 PM PDT 24
Peak memory 191544 kb
Host smart-f5f9d240-938a-418a-b4a0-dcdcfc827b13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711185341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.1711185341
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.1905225525
Short name T328
Test name
Test status
Simulation time 249128604374 ps
CPU time 1534.14 seconds
Started Jul 28 04:29:43 PM PDT 24
Finished Jul 28 04:55:17 PM PDT 24
Peak memory 191552 kb
Host smart-97c77452-3a10-4ee3-9fb2-2f9af63be514
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905225525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.1905225525
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.2901562092
Short name T308
Test name
Test status
Simulation time 215340687066 ps
CPU time 114.96 seconds
Started Jul 28 04:29:49 PM PDT 24
Finished Jul 28 04:31:44 PM PDT 24
Peak memory 191552 kb
Host smart-38032584-f04c-49dd-a525-f918523ed2bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901562092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.2901562092
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.2373952793
Short name T55
Test name
Test status
Simulation time 139900445027 ps
CPU time 305.85 seconds
Started Jul 28 04:29:49 PM PDT 24
Finished Jul 28 04:34:55 PM PDT 24
Peak memory 191536 kb
Host smart-215d7d0f-d101-426b-bcea-d14db8219b2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373952793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.2373952793
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.3079366762
Short name T292
Test name
Test status
Simulation time 466558728735 ps
CPU time 261.07 seconds
Started Jul 28 04:29:06 PM PDT 24
Finished Jul 28 04:33:27 PM PDT 24
Peak memory 183356 kb
Host smart-e5966a74-4dfd-44de-bdc8-5d664b2a0151
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079366762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.3079366762
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.3473157912
Short name T352
Test name
Test status
Simulation time 146434468045 ps
CPU time 59.25 seconds
Started Jul 28 04:29:19 PM PDT 24
Finished Jul 28 04:30:18 PM PDT 24
Peak memory 183376 kb
Host smart-b1ae5a04-c422-40d5-a194-0ac70f707574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473157912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.3473157912
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.2830845604
Short name T441
Test name
Test status
Simulation time 107285563 ps
CPU time 0.58 seconds
Started Jul 28 04:29:14 PM PDT 24
Finished Jul 28 04:29:15 PM PDT 24
Peak memory 183156 kb
Host smart-2bd2d65c-5409-41c6-a6f7-1911d83ab9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830845604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.2830845604
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.1436326166
Short name T320
Test name
Test status
Simulation time 241964254842 ps
CPU time 344.15 seconds
Started Jul 28 04:29:17 PM PDT 24
Finished Jul 28 04:35:01 PM PDT 24
Peak memory 191616 kb
Host smart-0725b86c-ad3b-4a05-af89-8bdbb35e1b9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436326166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.1436326166
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all_with_rand_reset.3897099614
Short name T399
Test name
Test status
Simulation time 19939304849 ps
CPU time 167.54 seconds
Started Jul 28 04:29:09 PM PDT 24
Finished Jul 28 04:31:57 PM PDT 24
Peak memory 198116 kb
Host smart-969b69fa-8bcb-4e5f-9d98-23270c2d285c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897099614 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all_with_rand_reset.3897099614
Directory /workspace/19.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.949636162
Short name T270
Test name
Test status
Simulation time 1053690676095 ps
CPU time 417.24 seconds
Started Jul 28 04:30:00 PM PDT 24
Finished Jul 28 04:36:57 PM PDT 24
Peak memory 191568 kb
Host smart-e51e8d80-d01a-4630-be4e-894970249f67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949636162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.949636162
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.1072953360
Short name T141
Test name
Test status
Simulation time 1823681524433 ps
CPU time 706.09 seconds
Started Jul 28 04:29:51 PM PDT 24
Finished Jul 28 04:41:38 PM PDT 24
Peak memory 191564 kb
Host smart-417793d1-e88f-4c20-8a9f-e7d6e8f42db8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072953360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.1072953360
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.1069745661
Short name T170
Test name
Test status
Simulation time 10584129795 ps
CPU time 4.72 seconds
Started Jul 28 04:29:48 PM PDT 24
Finished Jul 28 04:29:52 PM PDT 24
Peak memory 183364 kb
Host smart-f2b2d365-b4d2-4fa8-8b67-c603f430a368
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069745661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.1069745661
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.2990918513
Short name T41
Test name
Test status
Simulation time 162624159194 ps
CPU time 182.07 seconds
Started Jul 28 04:29:51 PM PDT 24
Finished Jul 28 04:32:53 PM PDT 24
Peak memory 191564 kb
Host smart-3071d66d-bb3b-42a3-9d7e-d6a0582f646a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990918513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.2990918513
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.4293857718
Short name T325
Test name
Test status
Simulation time 57141347584 ps
CPU time 51.99 seconds
Started Jul 28 04:29:48 PM PDT 24
Finished Jul 28 04:30:40 PM PDT 24
Peak memory 183292 kb
Host smart-ea10489b-2e11-4061-b053-c08ed8536c19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293857718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.4293857718
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.1108488178
Short name T334
Test name
Test status
Simulation time 699748100082 ps
CPU time 319.38 seconds
Started Jul 28 04:29:52 PM PDT 24
Finished Jul 28 04:35:12 PM PDT 24
Peak memory 191504 kb
Host smart-4f95f088-843a-4722-8039-ec455c60d23a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108488178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.1108488178
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.1453575132
Short name T24
Test name
Test status
Simulation time 88516073847 ps
CPU time 550.01 seconds
Started Jul 28 04:29:50 PM PDT 24
Finished Jul 28 04:39:00 PM PDT 24
Peak memory 191552 kb
Host smart-9593880c-d650-4066-a6d8-cb4ac8d45ba2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453575132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.1453575132
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.1373861598
Short name T78
Test name
Test status
Simulation time 263873379014 ps
CPU time 241.36 seconds
Started Jul 28 04:25:06 PM PDT 24
Finished Jul 28 04:29:08 PM PDT 24
Peak memory 182588 kb
Host smart-f0e886aa-7352-41eb-81a0-33856e9eafac
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373861598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.1373861598
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.3317223548
Short name T410
Test name
Test status
Simulation time 46926214574 ps
CPU time 65.83 seconds
Started Jul 28 04:21:25 PM PDT 24
Finished Jul 28 04:22:31 PM PDT 24
Peak memory 183384 kb
Host smart-5d52f0d9-7bda-4ca8-ab9c-4c2e76296bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317223548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.3317223548
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.3613727985
Short name T294
Test name
Test status
Simulation time 115069251399 ps
CPU time 204.7 seconds
Started Jul 28 04:23:20 PM PDT 24
Finished Jul 28 04:26:45 PM PDT 24
Peak memory 191712 kb
Host smart-63ab79e4-d0b5-422e-a399-a13a1f00b393
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613727985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.3613727985
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.3139521004
Short name T348
Test name
Test status
Simulation time 135846337 ps
CPU time 0.97 seconds
Started Jul 28 04:24:59 PM PDT 24
Finished Jul 28 04:25:00 PM PDT 24
Peak memory 182820 kb
Host smart-981911f1-dbb9-4ef7-a41f-c15643183f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139521004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.3139521004
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.3537612287
Short name T16
Test name
Test status
Simulation time 526956881 ps
CPU time 0.95 seconds
Started Jul 28 04:20:53 PM PDT 24
Finished Jul 28 04:20:54 PM PDT 24
Peak memory 214796 kb
Host smart-b9caa45d-e154-402c-bb48-9333edb151da
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537612287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.3537612287
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.4149668369
Short name T397
Test name
Test status
Simulation time 140490811944 ps
CPU time 58.69 seconds
Started Jul 28 04:25:19 PM PDT 24
Finished Jul 28 04:26:18 PM PDT 24
Peak memory 183368 kb
Host smart-a9434362-3e80-4b40-b843-c90b263ec492
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149668369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
4149668369
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.3441707175
Short name T293
Test name
Test status
Simulation time 546837636253 ps
CPU time 522.26 seconds
Started Jul 28 04:29:15 PM PDT 24
Finished Jul 28 04:37:58 PM PDT 24
Peak memory 183312 kb
Host smart-d4341449-4f31-454e-a659-b5d75b683c04
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441707175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.3441707175
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.1284904423
Short name T365
Test name
Test status
Simulation time 182349111267 ps
CPU time 67.7 seconds
Started Jul 28 04:29:09 PM PDT 24
Finished Jul 28 04:30:17 PM PDT 24
Peak memory 183360 kb
Host smart-96439986-b981-40a8-b8ef-6fd91174ed2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284904423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.1284904423
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.1733002539
Short name T152
Test name
Test status
Simulation time 226169267792 ps
CPU time 728.4 seconds
Started Jul 28 04:29:12 PM PDT 24
Finished Jul 28 04:41:21 PM PDT 24
Peak memory 191568 kb
Host smart-e2991785-87af-4fc2-a48b-73a8e97ca27c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733002539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.1733002539
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.3945672709
Short name T346
Test name
Test status
Simulation time 92836559373 ps
CPU time 41.18 seconds
Started Jul 28 04:29:10 PM PDT 24
Finished Jul 28 04:29:51 PM PDT 24
Peak memory 191580 kb
Host smart-9612c783-876e-4c5e-9de3-b9622f53223e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945672709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.3945672709
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.2638965719
Short name T333
Test name
Test status
Simulation time 151110686886 ps
CPU time 142.56 seconds
Started Jul 28 04:29:09 PM PDT 24
Finished Jul 28 04:31:32 PM PDT 24
Peak memory 183344 kb
Host smart-1391cf7c-f2b2-46ba-b99e-82f0e9a19d68
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638965719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.2638965719
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.2827862698
Short name T374
Test name
Test status
Simulation time 162188284829 ps
CPU time 117.7 seconds
Started Jul 28 04:29:14 PM PDT 24
Finished Jul 28 04:31:11 PM PDT 24
Peak memory 183336 kb
Host smart-b38371b1-85d9-49c8-9644-8676f3fad876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827862698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.2827862698
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.1641772263
Short name T297
Test name
Test status
Simulation time 28722918835 ps
CPU time 47.63 seconds
Started Jul 28 04:29:03 PM PDT 24
Finished Jul 28 04:29:50 PM PDT 24
Peak memory 183308 kb
Host smart-c8bc3473-12e4-4629-9af0-b8e3e5bebc94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641772263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.1641772263
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.1266838705
Short name T243
Test name
Test status
Simulation time 2445276929121 ps
CPU time 1130.82 seconds
Started Jul 28 04:29:08 PM PDT 24
Finished Jul 28 04:48:00 PM PDT 24
Peak memory 191556 kb
Host smart-a0683bd1-250a-4c7f-a548-8999bc44aa1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266838705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.1266838705
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all_with_rand_reset.655226826
Short name T38
Test name
Test status
Simulation time 98598158812 ps
CPU time 278.96 seconds
Started Jul 28 04:29:13 PM PDT 24
Finished Jul 28 04:33:52 PM PDT 24
Peak memory 206252 kb
Host smart-5a6ccb85-0bc4-43be-a383-69d5fea52235
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655226826 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all_with_rand_reset.655226826
Directory /workspace/21.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.4011269258
Short name T330
Test name
Test status
Simulation time 82087773594 ps
CPU time 147.31 seconds
Started Jul 28 04:29:16 PM PDT 24
Finished Jul 28 04:31:43 PM PDT 24
Peak memory 183324 kb
Host smart-564db51d-3c41-4ba0-b526-41f9be58418d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011269258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.4011269258
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.3516394177
Short name T411
Test name
Test status
Simulation time 298089084385 ps
CPU time 215.64 seconds
Started Jul 28 04:29:17 PM PDT 24
Finished Jul 28 04:32:53 PM PDT 24
Peak memory 183376 kb
Host smart-a9b487f5-4036-48a5-a356-5dcd33115b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516394177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.3516394177
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.217697818
Short name T254
Test name
Test status
Simulation time 572351958469 ps
CPU time 289.23 seconds
Started Jul 28 04:29:19 PM PDT 24
Finished Jul 28 04:34:09 PM PDT 24
Peak memory 191564 kb
Host smart-01b1117d-acc0-4a9e-93b5-cc40dbfadbcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217697818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.217697818
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.2031836516
Short name T138
Test name
Test status
Simulation time 133223668057 ps
CPU time 19.62 seconds
Started Jul 28 04:29:16 PM PDT 24
Finished Jul 28 04:29:35 PM PDT 24
Peak memory 183356 kb
Host smart-a3e029f8-130a-4bf3-b74f-0f415190cf64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031836516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.2031836516
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all_with_rand_reset.4257252468
Short name T33
Test name
Test status
Simulation time 52920479126 ps
CPU time 558.24 seconds
Started Jul 28 04:29:15 PM PDT 24
Finished Jul 28 04:38:34 PM PDT 24
Peak memory 209264 kb
Host smart-b0e35058-b243-4e70-87b8-669ea271453b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257252468 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all_with_rand_reset.4257252468
Directory /workspace/22.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.1492475011
Short name T149
Test name
Test status
Simulation time 9226296156 ps
CPU time 14.98 seconds
Started Jul 28 04:29:20 PM PDT 24
Finished Jul 28 04:29:35 PM PDT 24
Peak memory 183344 kb
Host smart-447cadbf-f1a8-4e46-97fc-29b04096ca5d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492475011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.1492475011
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.470371693
Short name T363
Test name
Test status
Simulation time 588716543844 ps
CPU time 255.3 seconds
Started Jul 28 04:29:20 PM PDT 24
Finished Jul 28 04:33:35 PM PDT 24
Peak memory 183336 kb
Host smart-a1461355-9e4e-491d-ba60-c1807dd9c392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470371693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.470371693
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.1853674634
Short name T317
Test name
Test status
Simulation time 111951113817 ps
CPU time 72.39 seconds
Started Jul 28 04:29:14 PM PDT 24
Finished Jul 28 04:30:27 PM PDT 24
Peak memory 183356 kb
Host smart-76967865-85d1-4dc0-ae15-b7dc63f49a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853674634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.1853674634
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.2112949740
Short name T398
Test name
Test status
Simulation time 90973562305 ps
CPU time 141.85 seconds
Started Jul 28 04:29:18 PM PDT 24
Finished Jul 28 04:31:40 PM PDT 24
Peak memory 183376 kb
Host smart-f30e8cb9-0802-4bf3-b591-14775699b2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112949740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.2112949740
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.3365363914
Short name T437
Test name
Test status
Simulation time 76300176745 ps
CPU time 64.79 seconds
Started Jul 28 04:29:07 PM PDT 24
Finished Jul 28 04:30:12 PM PDT 24
Peak memory 183304 kb
Host smart-5cf8fec9-15ab-4d8b-99ae-4758c03e9c80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365363914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.3365363914
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.708390388
Short name T385
Test name
Test status
Simulation time 1305582857 ps
CPU time 1.27 seconds
Started Jul 28 04:29:19 PM PDT 24
Finished Jul 28 04:29:21 PM PDT 24
Peak memory 192472 kb
Host smart-065ea8d3-ae20-431b-bffb-5f3c3a1b12a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708390388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.708390388
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.3900700299
Short name T388
Test name
Test status
Simulation time 483962272031 ps
CPU time 189.21 seconds
Started Jul 28 04:29:22 PM PDT 24
Finished Jul 28 04:32:32 PM PDT 24
Peak memory 183380 kb
Host smart-120097c6-bba9-402f-b97d-3ebfd7430e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900700299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.3900700299
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.1653626127
Short name T220
Test name
Test status
Simulation time 213902463379 ps
CPU time 301.78 seconds
Started Jul 28 04:29:21 PM PDT 24
Finished Jul 28 04:34:23 PM PDT 24
Peak memory 191552 kb
Host smart-93222ac4-4c67-474e-a4dc-3dacbf1a4cb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653626127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.1653626127
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.3926375418
Short name T417
Test name
Test status
Simulation time 82065944878 ps
CPU time 84.61 seconds
Started Jul 28 04:29:15 PM PDT 24
Finished Jul 28 04:30:40 PM PDT 24
Peak memory 191516 kb
Host smart-5592f0e0-1c8b-4820-b000-68bf305f3405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926375418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.3926375418
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.1504555154
Short name T62
Test name
Test status
Simulation time 50077651913 ps
CPU time 71.31 seconds
Started Jul 28 04:29:15 PM PDT 24
Finished Jul 28 04:30:26 PM PDT 24
Peak memory 195232 kb
Host smart-a5c961ab-2232-4198-9626-a51f63767ca0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504555154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.1504555154
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.2174184884
Short name T354
Test name
Test status
Simulation time 355158360346 ps
CPU time 272.33 seconds
Started Jul 28 04:29:25 PM PDT 24
Finished Jul 28 04:33:58 PM PDT 24
Peak memory 183344 kb
Host smart-ec26c5ec-f060-45b5-905c-21a616f84479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174184884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.2174184884
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.1332369676
Short name T370
Test name
Test status
Simulation time 52551595 ps
CPU time 0.53 seconds
Started Jul 28 04:29:22 PM PDT 24
Finished Jul 28 04:29:22 PM PDT 24
Peak memory 183232 kb
Host smart-ce373b74-5b7a-45a2-aba2-55834e948e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332369676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.1332369676
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.1850047535
Short name T340
Test name
Test status
Simulation time 1477810941204 ps
CPU time 807.87 seconds
Started Jul 28 04:29:16 PM PDT 24
Finished Jul 28 04:42:44 PM PDT 24
Peak memory 191556 kb
Host smart-0e43798c-f699-4f6a-a5d2-e5c7a31cf2b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850047535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.1850047535
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.3222677854
Short name T213
Test name
Test status
Simulation time 296936933520 ps
CPU time 263.09 seconds
Started Jul 28 04:29:24 PM PDT 24
Finished Jul 28 04:33:48 PM PDT 24
Peak memory 183352 kb
Host smart-b7a35eeb-4db3-4843-a200-af028b8b6d1a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222677854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.3222677854
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.2587173257
Short name T413
Test name
Test status
Simulation time 375510584462 ps
CPU time 147.43 seconds
Started Jul 28 04:29:20 PM PDT 24
Finished Jul 28 04:31:47 PM PDT 24
Peak memory 183376 kb
Host smart-61d98f5c-9249-4139-acbe-036f79eabd48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587173257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.2587173257
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.3198928118
Short name T143
Test name
Test status
Simulation time 1895264401 ps
CPU time 21.06 seconds
Started Jul 28 04:29:25 PM PDT 24
Finished Jul 28 04:29:47 PM PDT 24
Peak memory 183308 kb
Host smart-d0c78f9d-d1a8-45b1-adb8-260d6695224c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198928118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.3198928118
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.2449317059
Short name T393
Test name
Test status
Simulation time 3126131890 ps
CPU time 5.56 seconds
Started Jul 28 04:29:15 PM PDT 24
Finished Jul 28 04:29:21 PM PDT 24
Peak memory 183336 kb
Host smart-cb42c92f-c2c2-463e-a715-f15dd5c2b475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449317059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.2449317059
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.1094670194
Short name T52
Test name
Test status
Simulation time 40358889914 ps
CPU time 61.8 seconds
Started Jul 28 04:29:21 PM PDT 24
Finished Jul 28 04:30:23 PM PDT 24
Peak memory 183408 kb
Host smart-3878091c-c3e8-4293-8aa0-beba19e43974
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094670194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.1094670194
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.3709881799
Short name T251
Test name
Test status
Simulation time 339076904183 ps
CPU time 510.58 seconds
Started Jul 28 04:29:17 PM PDT 24
Finished Jul 28 04:37:48 PM PDT 24
Peak memory 183328 kb
Host smart-13e990ff-9605-4e98-89c8-37ef9c83d486
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709881799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.3709881799
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.522707709
Short name T361
Test name
Test status
Simulation time 45104807378 ps
CPU time 61.72 seconds
Started Jul 28 04:29:22 PM PDT 24
Finished Jul 28 04:30:23 PM PDT 24
Peak memory 183376 kb
Host smart-c067830d-00e4-4c21-a162-06a9cca4f6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522707709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.522707709
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.1970567754
Short name T21
Test name
Test status
Simulation time 872810299 ps
CPU time 0.96 seconds
Started Jul 28 04:29:15 PM PDT 24
Finished Jul 28 04:29:17 PM PDT 24
Peak memory 183148 kb
Host smart-2c229879-83a7-4f83-aef7-b86ffa78937d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970567754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.1970567754
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.2567248125
Short name T443
Test name
Test status
Simulation time 325905511216 ps
CPU time 382.06 seconds
Started Jul 28 04:29:11 PM PDT 24
Finished Jul 28 04:35:34 PM PDT 24
Peak memory 191516 kb
Host smart-e88ada4c-e3d9-4a15-bb54-3dffc728730d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567248125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.2567248125
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.1578812462
Short name T390
Test name
Test status
Simulation time 21143272054 ps
CPU time 14.97 seconds
Started Jul 28 04:29:23 PM PDT 24
Finished Jul 28 04:29:38 PM PDT 24
Peak memory 183328 kb
Host smart-0e711501-60eb-4dc7-8907-21773deaa375
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578812462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.1578812462
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.4012908490
Short name T377
Test name
Test status
Simulation time 95714395106 ps
CPU time 125.29 seconds
Started Jul 28 04:29:17 PM PDT 24
Finished Jul 28 04:31:23 PM PDT 24
Peak memory 183328 kb
Host smart-e6fa57c6-b223-4909-9ed9-516738bae14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012908490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.4012908490
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.212249383
Short name T252
Test name
Test status
Simulation time 146821320059 ps
CPU time 86.41 seconds
Started Jul 28 04:29:18 PM PDT 24
Finished Jul 28 04:30:45 PM PDT 24
Peak memory 192000 kb
Host smart-bd71ad20-16f5-4a5d-8880-fbac545c37ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212249383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.212249383
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.3302900247
Short name T412
Test name
Test status
Simulation time 118480310500 ps
CPU time 54.71 seconds
Started Jul 28 04:29:21 PM PDT 24
Finished Jul 28 04:30:16 PM PDT 24
Peak memory 191560 kb
Host smart-9b6a5b7a-cffb-4062-99e4-1304fda83f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302900247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.3302900247
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.1543073745
Short name T229
Test name
Test status
Simulation time 230814969168 ps
CPU time 370.34 seconds
Started Jul 28 04:20:24 PM PDT 24
Finished Jul 28 04:26:35 PM PDT 24
Peak memory 183444 kb
Host smart-d4dbf7df-f02d-440a-8a00-06a80ce8ac73
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543073745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.1543073745
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.2414687532
Short name T351
Test name
Test status
Simulation time 426938241343 ps
CPU time 140.4 seconds
Started Jul 28 04:21:07 PM PDT 24
Finished Jul 28 04:23:27 PM PDT 24
Peak memory 183428 kb
Host smart-2b7882d6-4cae-4532-8767-92c846716a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414687532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.2414687532
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.624286542
Short name T285
Test name
Test status
Simulation time 307663363001 ps
CPU time 262.88 seconds
Started Jul 28 04:24:57 PM PDT 24
Finished Jul 28 04:29:20 PM PDT 24
Peak memory 191228 kb
Host smart-ce993747-58d7-462d-bb63-26b7aa8cd17f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624286542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.624286542
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.2502211204
Short name T373
Test name
Test status
Simulation time 27352679 ps
CPU time 0.55 seconds
Started Jul 28 04:20:27 PM PDT 24
Finished Jul 28 04:20:28 PM PDT 24
Peak memory 183172 kb
Host smart-3e24a9aa-5c63-46c3-a6c7-2a72c6f68588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502211204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.2502211204
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.3271063181
Short name T18
Test name
Test status
Simulation time 785625760 ps
CPU time 0.88 seconds
Started Jul 28 04:24:53 PM PDT 24
Finished Jul 28 04:24:54 PM PDT 24
Peak memory 214476 kb
Host smart-3f935f47-5c45-46a0-80d7-eddfc4b4299b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271063181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.3271063181
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.4264722520
Short name T318
Test name
Test status
Simulation time 1420599121228 ps
CPU time 539.99 seconds
Started Jul 28 04:24:52 PM PDT 24
Finished Jul 28 04:33:53 PM PDT 24
Peak memory 194884 kb
Host smart-c067d869-8c79-4de3-8637-6c0d5e7738a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264722520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
4264722520
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.2792994453
Short name T248
Test name
Test status
Simulation time 331253259899 ps
CPU time 154.53 seconds
Started Jul 28 04:29:22 PM PDT 24
Finished Jul 28 04:31:56 PM PDT 24
Peak memory 183352 kb
Host smart-d1661a59-3ae9-463a-b35e-af5a7364be12
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792994453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.2792994453
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.1739660963
Short name T389
Test name
Test status
Simulation time 14969461209 ps
CPU time 22.44 seconds
Started Jul 28 04:29:24 PM PDT 24
Finished Jul 28 04:29:46 PM PDT 24
Peak memory 183352 kb
Host smart-56e51b01-c09e-403d-9518-5e474a1d99be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739660963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.1739660963
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.205560325
Short name T289
Test name
Test status
Simulation time 102357856113 ps
CPU time 93.65 seconds
Started Jul 28 04:29:19 PM PDT 24
Finished Jul 28 04:30:53 PM PDT 24
Peak memory 191608 kb
Host smart-d7e835f5-017c-467a-a2dc-d1ea19d8ed48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205560325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.205560325
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.3570352044
Short name T423
Test name
Test status
Simulation time 55503050540 ps
CPU time 1571.7 seconds
Started Jul 28 04:29:24 PM PDT 24
Finished Jul 28 04:55:36 PM PDT 24
Peak memory 183520 kb
Host smart-70c87d42-f56c-4665-adfe-f1528dfc24b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570352044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.3570352044
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.527880332
Short name T134
Test name
Test status
Simulation time 647666077375 ps
CPU time 1403.3 seconds
Started Jul 28 04:29:19 PM PDT 24
Finished Jul 28 04:52:43 PM PDT 24
Peak memory 191564 kb
Host smart-190f6124-ac63-4c8e-a4bc-3849f1413b51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527880332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all.
527880332
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.987411615
Short name T383
Test name
Test status
Simulation time 17054987781 ps
CPU time 22.55 seconds
Started Jul 28 04:29:24 PM PDT 24
Finished Jul 28 04:29:47 PM PDT 24
Peak memory 183356 kb
Host smart-09fcb4ad-caa3-494b-b51b-52d73042f35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987411615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.987411615
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.3397621379
Short name T345
Test name
Test status
Simulation time 743413854414 ps
CPU time 1440.02 seconds
Started Jul 28 04:29:20 PM PDT 24
Finished Jul 28 04:53:20 PM PDT 24
Peak memory 191504 kb
Host smart-d4754a01-dcb0-4e6b-8d49-4b8bea181f81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397621379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.3397621379
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.2168587566
Short name T424
Test name
Test status
Simulation time 286384622880 ps
CPU time 118.61 seconds
Started Jul 28 04:29:30 PM PDT 24
Finished Jul 28 04:31:29 PM PDT 24
Peak memory 191584 kb
Host smart-4410b5f3-8351-4f4f-8102-431c0e9b6770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168587566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.2168587566
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.3934768001
Short name T64
Test name
Test status
Simulation time 184310004816 ps
CPU time 303.03 seconds
Started Jul 28 04:29:17 PM PDT 24
Finished Jul 28 04:34:20 PM PDT 24
Peak memory 195208 kb
Host smart-100527ee-bf7a-415e-8017-d8717fd1117a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934768001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.3934768001
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all_with_rand_reset.2327124960
Short name T37
Test name
Test status
Simulation time 80779574677 ps
CPU time 611.82 seconds
Started Jul 28 04:29:21 PM PDT 24
Finished Jul 28 04:39:33 PM PDT 24
Peak memory 207760 kb
Host smart-c2d07ea2-5da5-4b41-a5d4-0656370ea21e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327124960 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all_with_rand_reset.2327124960
Directory /workspace/31.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.3087345950
Short name T436
Test name
Test status
Simulation time 30991832348 ps
CPU time 45.65 seconds
Started Jul 28 04:29:21 PM PDT 24
Finished Jul 28 04:30:06 PM PDT 24
Peak memory 183364 kb
Host smart-15dd786f-53d2-4afa-98f3-b2ba7e82b810
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087345950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.3087345950
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.4063121729
Short name T407
Test name
Test status
Simulation time 102939202036 ps
CPU time 141.39 seconds
Started Jul 28 04:29:23 PM PDT 24
Finished Jul 28 04:31:44 PM PDT 24
Peak memory 183360 kb
Host smart-a8b1f4a9-c6e4-4b79-9c05-1d06fa79e470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063121729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.4063121729
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.991521863
Short name T446
Test name
Test status
Simulation time 1294235233682 ps
CPU time 1150.49 seconds
Started Jul 28 04:29:22 PM PDT 24
Finished Jul 28 04:48:32 PM PDT 24
Peak memory 191616 kb
Host smart-97279d71-baf6-4857-aa95-75d6bf45c053
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991521863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.991521863
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.3327976996
Short name T414
Test name
Test status
Simulation time 654005420 ps
CPU time 1.43 seconds
Started Jul 28 04:29:22 PM PDT 24
Finished Jul 28 04:29:23 PM PDT 24
Peak memory 183144 kb
Host smart-f4b54d9d-aed4-4a84-9e7f-58517512eeb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327976996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.3327976996
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.788715592
Short name T158
Test name
Test status
Simulation time 4272675770 ps
CPU time 6.5 seconds
Started Jul 28 04:29:21 PM PDT 24
Finished Jul 28 04:29:27 PM PDT 24
Peak memory 183404 kb
Host smart-75a97fd0-4b71-451d-89f6-da1f939fa235
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788715592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.rv_timer_cfg_update_on_fly.788715592
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.2658952871
Short name T379
Test name
Test status
Simulation time 23430270297 ps
CPU time 33.06 seconds
Started Jul 28 04:29:23 PM PDT 24
Finished Jul 28 04:29:56 PM PDT 24
Peak memory 183764 kb
Host smart-abd47ab6-a31f-41be-bd7c-461fd4a9e00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658952871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.2658952871
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.1820119833
Short name T249
Test name
Test status
Simulation time 23773932353 ps
CPU time 115.51 seconds
Started Jul 28 04:29:27 PM PDT 24
Finished Jul 28 04:31:22 PM PDT 24
Peak memory 191528 kb
Host smart-b349e1db-9dc0-42c5-bfd8-711d709d463b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820119833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.1820119833
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.2547367540
Short name T376
Test name
Test status
Simulation time 323087865 ps
CPU time 0.65 seconds
Started Jul 28 04:29:32 PM PDT 24
Finished Jul 28 04:29:33 PM PDT 24
Peak memory 183096 kb
Host smart-6a152db1-b206-4177-884c-f2b0b7dcb272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547367540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.2547367540
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.1579154443
Short name T217
Test name
Test status
Simulation time 1170671720297 ps
CPU time 574.82 seconds
Started Jul 28 04:29:21 PM PDT 24
Finished Jul 28 04:38:56 PM PDT 24
Peak memory 191560 kb
Host smart-0e8eebc6-ad59-4d01-a86d-cfb442d19176
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579154443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.1579154443
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all_with_rand_reset.753013208
Short name T39
Test name
Test status
Simulation time 25536656623 ps
CPU time 182.09 seconds
Started Jul 28 04:29:23 PM PDT 24
Finished Jul 28 04:32:25 PM PDT 24
Peak memory 198092 kb
Host smart-19ebd0d8-779e-455a-9621-d9fd52a6c45a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753013208 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all_with_rand_reset.753013208
Directory /workspace/33.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.3151624630
Short name T291
Test name
Test status
Simulation time 756269103649 ps
CPU time 1067 seconds
Started Jul 28 04:29:21 PM PDT 24
Finished Jul 28 04:47:08 PM PDT 24
Peak memory 183344 kb
Host smart-aa2ba7d3-56a1-4f87-a173-1af93723d003
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151624630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.3151624630
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.833992767
Short name T378
Test name
Test status
Simulation time 163382404047 ps
CPU time 210.57 seconds
Started Jul 28 04:29:28 PM PDT 24
Finished Jul 28 04:32:59 PM PDT 24
Peak memory 183372 kb
Host smart-d624bc56-3c54-4ddb-8a69-1a56b274a526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833992767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.833992767
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.2830966565
Short name T344
Test name
Test status
Simulation time 466574064635 ps
CPU time 399.84 seconds
Started Jul 28 04:29:23 PM PDT 24
Finished Jul 28 04:36:03 PM PDT 24
Peak memory 183352 kb
Host smart-b2733960-547a-4c49-9187-1dd9b397ca28
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830966565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.2830966565
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.3839813362
Short name T372
Test name
Test status
Simulation time 443563843021 ps
CPU time 185.5 seconds
Started Jul 28 04:29:37 PM PDT 24
Finished Jul 28 04:32:43 PM PDT 24
Peak memory 183320 kb
Host smart-a66c8437-95bb-4244-93ea-e5a0785614f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839813362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.3839813362
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.3710288693
Short name T426
Test name
Test status
Simulation time 58081837192 ps
CPU time 72.09 seconds
Started Jul 28 04:29:22 PM PDT 24
Finished Jul 28 04:30:35 PM PDT 24
Peak memory 183340 kb
Host smart-ed827f0a-fbc6-4b2f-a14b-5a2ed8d7edc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710288693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.3710288693
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.1943766808
Short name T295
Test name
Test status
Simulation time 577697864363 ps
CPU time 518.82 seconds
Started Jul 28 04:29:16 PM PDT 24
Finished Jul 28 04:37:55 PM PDT 24
Peak memory 183348 kb
Host smart-20f10c5a-9af4-4ad1-95df-80fbdd740071
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943766808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.1943766808
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.4264120679
Short name T434
Test name
Test status
Simulation time 479181880978 ps
CPU time 148.94 seconds
Started Jul 28 04:29:23 PM PDT 24
Finished Jul 28 04:31:52 PM PDT 24
Peak memory 183360 kb
Host smart-7cb1a0bb-5a6b-4536-8844-c8661a9936c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264120679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.4264120679
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.1826735666
Short name T267
Test name
Test status
Simulation time 395214781728 ps
CPU time 94.29 seconds
Started Jul 28 04:29:19 PM PDT 24
Finished Jul 28 04:30:53 PM PDT 24
Peak memory 183328 kb
Host smart-5ea1fce2-d113-4c82-9798-5b60007ce1f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826735666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.1826735666
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.225250860
Short name T432
Test name
Test status
Simulation time 268855471725 ps
CPU time 53.33 seconds
Started Jul 28 04:29:33 PM PDT 24
Finished Jul 28 04:30:27 PM PDT 24
Peak memory 195820 kb
Host smart-8c438176-56e9-4cd7-be8f-4bd9b78ae7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225250860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.225250860
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.1249235
Short name T323
Test name
Test status
Simulation time 354716328457 ps
CPU time 515.26 seconds
Started Jul 28 04:29:22 PM PDT 24
Finished Jul 28 04:37:58 PM PDT 24
Peak memory 183348 kb
Host smart-4fac63d3-6d01-4417-b149-f35b632edac5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
rv_timer_cfg_update_on_fly.1249235
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.1943162495
Short name T387
Test name
Test status
Simulation time 43947236169 ps
CPU time 64.74 seconds
Started Jul 28 04:29:20 PM PDT 24
Finished Jul 28 04:30:24 PM PDT 24
Peak memory 183332 kb
Host smart-77575241-ae1c-4ee9-a4d6-cfb6f5cbeb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943162495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.1943162495
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.1061010427
Short name T401
Test name
Test status
Simulation time 618585592 ps
CPU time 2.15 seconds
Started Jul 28 04:29:25 PM PDT 24
Finished Jul 28 04:29:28 PM PDT 24
Peak memory 191656 kb
Host smart-56f0430c-ed72-461f-a350-94d346b989f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061010427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.1061010427
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.2354095323
Short name T66
Test name
Test status
Simulation time 764113775436 ps
CPU time 621.3 seconds
Started Jul 28 04:29:24 PM PDT 24
Finished Jul 28 04:39:46 PM PDT 24
Peak memory 191556 kb
Host smart-b199cf64-39f3-4f56-9d45-3bf421fd2827
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354095323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.2354095323
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.217415578
Short name T422
Test name
Test status
Simulation time 62555296792 ps
CPU time 33 seconds
Started Jul 28 04:29:24 PM PDT 24
Finished Jul 28 04:29:57 PM PDT 24
Peak memory 183444 kb
Host smart-805ec292-3779-42dc-a5dd-394fcab42ec9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217415578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.rv_timer_cfg_update_on_fly.217415578
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.1733839883
Short name T421
Test name
Test status
Simulation time 97432101688 ps
CPU time 122.95 seconds
Started Jul 28 04:29:20 PM PDT 24
Finished Jul 28 04:31:23 PM PDT 24
Peak memory 183356 kb
Host smart-84c06d29-db4e-49eb-9ebd-90ca53ce24af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733839883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.1733839883
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.3437080719
Short name T332
Test name
Test status
Simulation time 43572992322 ps
CPU time 79.74 seconds
Started Jul 28 04:29:24 PM PDT 24
Finished Jul 28 04:30:44 PM PDT 24
Peak memory 194224 kb
Host smart-748a34f0-713b-4bc0-8ec6-3a53ef4ef414
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437080719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.3437080719
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.2658636700
Short name T23
Test name
Test status
Simulation time 299375984 ps
CPU time 0.65 seconds
Started Jul 28 04:29:21 PM PDT 24
Finished Jul 28 04:29:21 PM PDT 24
Peak memory 183168 kb
Host smart-c5e123fa-7419-4484-9756-ec659568a19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658636700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.2658636700
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.1772687615
Short name T394
Test name
Test status
Simulation time 203594669095 ps
CPU time 162.93 seconds
Started Jul 28 04:29:25 PM PDT 24
Finished Jul 28 04:32:08 PM PDT 24
Peak memory 183312 kb
Host smart-aa45fccc-f0d4-4236-95a1-caa319075b39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772687615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.1772687615
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all_with_rand_reset.1937003066
Short name T36
Test name
Test status
Simulation time 58370961947 ps
CPU time 115.38 seconds
Started Jul 28 04:29:22 PM PDT 24
Finished Jul 28 04:31:18 PM PDT 24
Peak memory 206260 kb
Host smart-ba5da303-b8b4-4474-9740-e745ab7f186d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937003066 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all_with_rand_reset.1937003066
Directory /workspace/38.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.3024524120
Short name T121
Test name
Test status
Simulation time 547754700899 ps
CPU time 129.26 seconds
Started Jul 28 04:29:19 PM PDT 24
Finished Jul 28 04:31:28 PM PDT 24
Peak memory 183332 kb
Host smart-47b1f393-6484-4540-8dd9-e92a467c4434
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024524120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.3024524120
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.1903517794
Short name T1
Test name
Test status
Simulation time 81990750568 ps
CPU time 104.67 seconds
Started Jul 28 04:29:21 PM PDT 24
Finished Jul 28 04:31:06 PM PDT 24
Peak memory 183356 kb
Host smart-0bacbe69-c048-4c60-bdad-066ff492ef34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903517794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.1903517794
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.9756804
Short name T210
Test name
Test status
Simulation time 168990022250 ps
CPU time 2932.03 seconds
Started Jul 28 04:29:22 PM PDT 24
Finished Jul 28 05:18:19 PM PDT 24
Peak memory 191556 kb
Host smart-62aa3c85-f2df-4b5d-9a22-ce8c8f9d92ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9756804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.9756804
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.3150691904
Short name T72
Test name
Test status
Simulation time 191734519 ps
CPU time 0.71 seconds
Started Jul 28 04:29:24 PM PDT 24
Finished Jul 28 04:29:25 PM PDT 24
Peak memory 191692 kb
Host smart-acac91d8-4410-4f8a-977a-64145358aa15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150691904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.3150691904
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.2591576936
Short name T448
Test name
Test status
Simulation time 42239026 ps
CPU time 0.57 seconds
Started Jul 28 04:29:25 PM PDT 24
Finished Jul 28 04:29:26 PM PDT 24
Peak memory 183080 kb
Host smart-e44576a7-bd17-4904-a929-c361c83ca97b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591576936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.2591576936
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.4233538596
Short name T357
Test name
Test status
Simulation time 486170190370 ps
CPU time 205.01 seconds
Started Jul 28 04:20:59 PM PDT 24
Finished Jul 28 04:24:24 PM PDT 24
Peak memory 183748 kb
Host smart-c1fb4223-7b3b-40af-9b37-f478b12182c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233538596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.4233538596
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.2746771582
Short name T264
Test name
Test status
Simulation time 20677270670 ps
CPU time 40.49 seconds
Started Jul 28 04:24:53 PM PDT 24
Finished Jul 28 04:25:34 PM PDT 24
Peak memory 191476 kb
Host smart-9b97bdec-66f8-48b7-b508-9b5f50581056
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746771582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.2746771582
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.3527866077
Short name T347
Test name
Test status
Simulation time 119020512 ps
CPU time 0.69 seconds
Started Jul 28 04:25:03 PM PDT 24
Finished Jul 28 04:25:04 PM PDT 24
Peak memory 183232 kb
Host smart-954e36c2-d010-4312-b0ec-54c69794a698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527866077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.3527866077
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.55354930
Short name T19
Test name
Test status
Simulation time 115597253 ps
CPU time 0.85 seconds
Started Jul 28 04:24:49 PM PDT 24
Finished Jul 28 04:24:51 PM PDT 24
Peak memory 211720 kb
Host smart-be9363d2-bfb3-4639-b708-454ef0b8f59d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55354930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.55354930
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.1979389578
Short name T50
Test name
Test status
Simulation time 94070870 ps
CPU time 0.58 seconds
Started Jul 28 04:25:12 PM PDT 24
Finished Jul 28 04:25:13 PM PDT 24
Peak memory 183140 kb
Host smart-85dfd9e5-3ef3-418b-9ccd-925e2382d079
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979389578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
1979389578
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all_with_rand_reset.3361524989
Short name T14
Test name
Test status
Simulation time 59448177432 ps
CPU time 319.2 seconds
Started Jul 28 04:21:03 PM PDT 24
Finished Jul 28 04:26:23 PM PDT 24
Peak memory 206252 kb
Host smart-a4f3a700-0e87-4d34-9ed5-5dfe7bb74761
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361524989 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all_with_rand_reset.3361524989
Directory /workspace/4.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.1922372643
Short name T280
Test name
Test status
Simulation time 174790554268 ps
CPU time 299.52 seconds
Started Jul 28 04:29:24 PM PDT 24
Finished Jul 28 04:34:24 PM PDT 24
Peak memory 183364 kb
Host smart-fa0225fb-29a9-4e8e-a6f8-a99900ef2dc7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922372643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.1922372643
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.4259536085
Short name T358
Test name
Test status
Simulation time 145992770509 ps
CPU time 202.04 seconds
Started Jul 28 04:29:24 PM PDT 24
Finished Jul 28 04:32:46 PM PDT 24
Peak memory 183316 kb
Host smart-a342b7d3-3630-44ac-ba5b-a5b30999051a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259536085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.4259536085
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.2839980506
Short name T419
Test name
Test status
Simulation time 23141463721 ps
CPU time 36.93 seconds
Started Jul 28 04:29:23 PM PDT 24
Finished Jul 28 04:30:00 PM PDT 24
Peak memory 183400 kb
Host smart-17565775-ec68-4beb-966c-c4dca60acda5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839980506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.2839980506
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.577863202
Short name T343
Test name
Test status
Simulation time 52453426622 ps
CPU time 224.95 seconds
Started Jul 28 04:29:21 PM PDT 24
Finished Jul 28 04:33:06 PM PDT 24
Peak memory 194748 kb
Host smart-fdca82af-7e03-45b3-ba0c-87cef5be0733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577863202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.577863202
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.1757642987
Short name T315
Test name
Test status
Simulation time 12114902936 ps
CPU time 20.34 seconds
Started Jul 28 04:29:23 PM PDT 24
Finished Jul 28 04:29:49 PM PDT 24
Peak memory 183432 kb
Host smart-5ad0cc54-ce91-453c-a93a-d2b9a9e21424
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757642987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.1757642987
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.3992458034
Short name T356
Test name
Test status
Simulation time 28558986059 ps
CPU time 44.81 seconds
Started Jul 28 04:29:28 PM PDT 24
Finished Jul 28 04:30:13 PM PDT 24
Peak memory 183356 kb
Host smart-68c239c8-c48a-4f29-8365-29f3e77b9ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992458034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.3992458034
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.3104836777
Short name T202
Test name
Test status
Simulation time 98310906999 ps
CPU time 83.2 seconds
Started Jul 28 04:29:24 PM PDT 24
Finished Jul 28 04:30:47 PM PDT 24
Peak memory 183316 kb
Host smart-7b746e7c-7948-4b78-9dc6-e84ff478149e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104836777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.3104836777
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.1761543373
Short name T429
Test name
Test status
Simulation time 915326071461 ps
CPU time 358.8 seconds
Started Jul 28 04:29:24 PM PDT 24
Finished Jul 28 04:35:22 PM PDT 24
Peak memory 191524 kb
Host smart-e2b9270c-1fae-4212-ab7d-f8e5ea57dfa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761543373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.1761543373
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.128087769
Short name T282
Test name
Test status
Simulation time 670125588875 ps
CPU time 353.56 seconds
Started Jul 28 04:30:29 PM PDT 24
Finished Jul 28 04:36:23 PM PDT 24
Peak memory 190748 kb
Host smart-14bed550-9d50-49e1-b6d0-7e7c70b61904
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128087769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all.
128087769
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all_with_rand_reset.2305996337
Short name T13
Test name
Test status
Simulation time 3752142807 ps
CPU time 42.57 seconds
Started Jul 28 04:29:22 PM PDT 24
Finished Jul 28 04:30:04 PM PDT 24
Peak memory 198112 kb
Host smart-005d4b0f-f037-42f9-9933-837be57189a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305996337 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all_with_rand_reset.2305996337
Directory /workspace/41.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.149967883
Short name T151
Test name
Test status
Simulation time 115592293761 ps
CPU time 60.97 seconds
Started Jul 28 04:29:23 PM PDT 24
Finished Jul 28 04:30:24 PM PDT 24
Peak memory 183308 kb
Host smart-be8cbaed-711c-4ab7-ad23-3c5af4bed4ab
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149967883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.rv_timer_cfg_update_on_fly.149967883
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_random.2972709554
Short name T162
Test name
Test status
Simulation time 150035648308 ps
CPU time 590.51 seconds
Started Jul 28 04:29:24 PM PDT 24
Finished Jul 28 04:39:15 PM PDT 24
Peak memory 191572 kb
Host smart-129d7e0b-6791-449f-b16d-eb178ba41494
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972709554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.2972709554
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.3586974401
Short name T284
Test name
Test status
Simulation time 75305632518 ps
CPU time 100.47 seconds
Started Jul 28 04:30:40 PM PDT 24
Finished Jul 28 04:32:21 PM PDT 24
Peak memory 191100 kb
Host smart-1782d270-b6f0-4b30-ab66-34be0c83590e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586974401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.3586974401
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.1051611289
Short name T445
Test name
Test status
Simulation time 889800363670 ps
CPU time 405.75 seconds
Started Jul 28 04:29:25 PM PDT 24
Finished Jul 28 04:36:11 PM PDT 24
Peak memory 195444 kb
Host smart-d0474a8e-3109-4ea0-8387-e3bcbf98b302
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051611289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.1051611289
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.253030115
Short name T119
Test name
Test status
Simulation time 19932020447 ps
CPU time 30.43 seconds
Started Jul 28 04:29:27 PM PDT 24
Finished Jul 28 04:29:57 PM PDT 24
Peak memory 183348 kb
Host smart-5b8973dd-99c5-4e0e-b19b-8c3c33a53994
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253030115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.rv_timer_cfg_update_on_fly.253030115
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.111252581
Short name T430
Test name
Test status
Simulation time 70530689430 ps
CPU time 110.06 seconds
Started Jul 28 04:29:34 PM PDT 24
Finished Jul 28 04:31:24 PM PDT 24
Peak memory 183332 kb
Host smart-14ccda1d-d5dd-4f1c-b426-8b77d33da192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111252581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.111252581
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.2435918021
Short name T214
Test name
Test status
Simulation time 257391552194 ps
CPU time 174.43 seconds
Started Jul 28 04:29:38 PM PDT 24
Finished Jul 28 04:32:33 PM PDT 24
Peak memory 191532 kb
Host smart-2a75ac95-22fc-473a-a1bd-aeb68646cb09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435918021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.2435918021
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.2113050382
Short name T142
Test name
Test status
Simulation time 342924014888 ps
CPU time 289.18 seconds
Started Jul 28 04:29:30 PM PDT 24
Finished Jul 28 04:34:19 PM PDT 24
Peak memory 191516 kb
Host smart-cddcf548-1214-47cc-8a35-0f30d23ea157
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113050382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.2113050382
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.1678434229
Short name T34
Test name
Test status
Simulation time 47956893342 ps
CPU time 398.41 seconds
Started Jul 28 04:29:25 PM PDT 24
Finished Jul 28 04:36:09 PM PDT 24
Peak memory 206296 kb
Host smart-e16cac7b-e6d0-4140-8bce-2041ba91f5f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678434229 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.1678434229
Directory /workspace/43.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.3853105174
Short name T400
Test name
Test status
Simulation time 15324341795 ps
CPU time 11.25 seconds
Started Jul 28 04:29:26 PM PDT 24
Finished Jul 28 04:29:38 PM PDT 24
Peak memory 183436 kb
Host smart-09b8bca3-da65-40e7-b660-733cc978d476
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853105174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.3853105174
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.1684819903
Short name T375
Test name
Test status
Simulation time 734095696359 ps
CPU time 111.42 seconds
Started Jul 28 04:29:24 PM PDT 24
Finished Jul 28 04:31:16 PM PDT 24
Peak memory 183340 kb
Host smart-b9230a69-c9fe-4b97-b1c9-6cc822e8f787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684819903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.1684819903
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.3550479796
Short name T416
Test name
Test status
Simulation time 114004780731 ps
CPU time 104.19 seconds
Started Jul 28 04:29:34 PM PDT 24
Finished Jul 28 04:31:19 PM PDT 24
Peak memory 183308 kb
Host smart-af2474a7-32dd-4d0a-9a43-f4ef86356319
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550479796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.3550479796
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.3921740728
Short name T76
Test name
Test status
Simulation time 91934766348 ps
CPU time 59.42 seconds
Started Jul 28 04:29:25 PM PDT 24
Finished Jul 28 04:30:25 PM PDT 24
Peak memory 183764 kb
Host smart-1df15781-83eb-4897-8d38-01643bc97634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921740728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.3921740728
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.3933864869
Short name T324
Test name
Test status
Simulation time 130400924422 ps
CPU time 231.76 seconds
Started Jul 28 04:29:43 PM PDT 24
Finished Jul 28 04:33:35 PM PDT 24
Peak memory 194712 kb
Host smart-e7d7faf7-4bcf-440d-86c6-63dc83af8d01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933864869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.3933864869
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.2952560579
Short name T110
Test name
Test status
Simulation time 128133806429 ps
CPU time 446.68 seconds
Started Jul 28 04:29:31 PM PDT 24
Finished Jul 28 04:36:58 PM PDT 24
Peak memory 183384 kb
Host smart-9b988f47-f236-4027-8922-ecfb2a2d26c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952560579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.2952560579
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.3350079658
Short name T253
Test name
Test status
Simulation time 1366398995944 ps
CPU time 2062.22 seconds
Started Jul 28 04:29:29 PM PDT 24
Finished Jul 28 05:03:52 PM PDT 24
Peak memory 191556 kb
Host smart-e707ff2d-5ea1-40f9-aeb9-678356c7967e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350079658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.3350079658
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.325561205
Short name T309
Test name
Test status
Simulation time 1329077424430 ps
CPU time 387.4 seconds
Started Jul 28 04:29:26 PM PDT 24
Finished Jul 28 04:35:54 PM PDT 24
Peak memory 183340 kb
Host smart-40a0af8e-a43d-4b85-9a97-be160e7a896f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325561205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.rv_timer_cfg_update_on_fly.325561205
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.1021795882
Short name T420
Test name
Test status
Simulation time 766525454840 ps
CPU time 305.78 seconds
Started Jul 28 04:29:29 PM PDT 24
Finished Jul 28 04:34:35 PM PDT 24
Peak memory 183376 kb
Host smart-88d9986a-b232-45ce-a729-398893b5b4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021795882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.1021795882
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.3041395884
Short name T145
Test name
Test status
Simulation time 1695520504 ps
CPU time 4.02 seconds
Started Jul 28 04:29:26 PM PDT 24
Finished Jul 28 04:29:35 PM PDT 24
Peak memory 183276 kb
Host smart-0e2abb1c-f4e3-4767-90df-0c898b9a795e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041395884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.3041395884
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.3871585245
Short name T194
Test name
Test status
Simulation time 33258460209 ps
CPU time 51.51 seconds
Started Jul 28 04:29:24 PM PDT 24
Finished Jul 28 04:30:16 PM PDT 24
Peak memory 183400 kb
Host smart-79dd1c70-1251-4697-b3c7-cb79b6be95db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871585245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.3871585245
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.3251938919
Short name T166
Test name
Test status
Simulation time 1460391774813 ps
CPU time 431.11 seconds
Started Jul 28 04:29:46 PM PDT 24
Finished Jul 28 04:36:57 PM PDT 24
Peak memory 191520 kb
Host smart-e6879226-0ba0-4fd5-8a79-74e06b12a033
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251938919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.3251938919
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.4020234564
Short name T204
Test name
Test status
Simulation time 84540037236 ps
CPU time 41.83 seconds
Started Jul 28 04:29:23 PM PDT 24
Finished Jul 28 04:30:05 PM PDT 24
Peak memory 183348 kb
Host smart-d0f6e0e6-49ae-4c70-990f-6adcd6c09dd0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020234564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.4020234564
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.824827000
Short name T402
Test name
Test status
Simulation time 368252087193 ps
CPU time 155.41 seconds
Started Jul 28 04:29:25 PM PDT 24
Finished Jul 28 04:32:01 PM PDT 24
Peak memory 183356 kb
Host smart-5df678f1-6c9f-4a5e-98a5-62034f0b342c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824827000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.824827000
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.3047757348
Short name T128
Test name
Test status
Simulation time 106602681254 ps
CPU time 126.91 seconds
Started Jul 28 04:29:31 PM PDT 24
Finished Jul 28 04:31:44 PM PDT 24
Peak memory 191520 kb
Host smart-5af08963-4200-4e64-947a-c54a7012acac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047757348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.3047757348
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.2975981914
Short name T199
Test name
Test status
Simulation time 21058406061 ps
CPU time 32.77 seconds
Started Jul 28 04:29:31 PM PDT 24
Finished Jul 28 04:30:04 PM PDT 24
Peak memory 183280 kb
Host smart-1c9429e4-268b-4b40-b5a3-2c0d7e4fea40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975981914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.2975981914
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.171088039
Short name T22
Test name
Test status
Simulation time 283071899848 ps
CPU time 225.2 seconds
Started Jul 28 04:29:42 PM PDT 24
Finished Jul 28 04:33:27 PM PDT 24
Peak memory 183292 kb
Host smart-5f2d997d-e6c0-4125-9180-eab2c4e7b60f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171088039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.rv_timer_cfg_update_on_fly.171088039
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.2898999255
Short name T364
Test name
Test status
Simulation time 169507246789 ps
CPU time 59.04 seconds
Started Jul 28 04:29:45 PM PDT 24
Finished Jul 28 04:30:44 PM PDT 24
Peak memory 183328 kb
Host smart-59b81d13-031d-4ac9-b6b1-b2c8614a817f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898999255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.2898999255
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.2632185938
Short name T342
Test name
Test status
Simulation time 24775931740 ps
CPU time 217.78 seconds
Started Jul 28 04:29:39 PM PDT 24
Finished Jul 28 04:33:17 PM PDT 24
Peak memory 183296 kb
Host smart-21dcf3ad-aae2-4367-b8dd-cee5fd10763f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632185938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.2632185938
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.2445080349
Short name T392
Test name
Test status
Simulation time 112479022 ps
CPU time 0.79 seconds
Started Jul 28 04:30:40 PM PDT 24
Finished Jul 28 04:30:41 PM PDT 24
Peak memory 191676 kb
Host smart-3aca4585-5b23-4aa0-bbdb-9a9ddd73351f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445080349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.2445080349
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.1653494602
Short name T130
Test name
Test status
Simulation time 271037904809 ps
CPU time 396.28 seconds
Started Jul 28 04:29:28 PM PDT 24
Finished Jul 28 04:36:04 PM PDT 24
Peak memory 183344 kb
Host smart-f4631757-f1f2-403c-bf5c-ca5691b29849
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653494602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.1653494602
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.3956667295
Short name T73
Test name
Test status
Simulation time 58292793077 ps
CPU time 81.66 seconds
Started Jul 28 04:29:50 PM PDT 24
Finished Jul 28 04:31:12 PM PDT 24
Peak memory 183356 kb
Host smart-85becedf-0847-4e64-8125-8817664c5d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956667295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.3956667295
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.2788098142
Short name T7
Test name
Test status
Simulation time 85253776981 ps
CPU time 513.85 seconds
Started Jul 28 04:29:45 PM PDT 24
Finished Jul 28 04:38:19 PM PDT 24
Peak memory 191528 kb
Host smart-3c1812b3-9756-4924-8de2-2da15a526b6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788098142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.2788098142
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.3877046851
Short name T8
Test name
Test status
Simulation time 7905104009 ps
CPU time 11.56 seconds
Started Jul 28 04:29:28 PM PDT 24
Finished Jul 28 04:29:40 PM PDT 24
Peak memory 183384 kb
Host smart-6248e565-ee8e-4c63-88c0-65d8b8ca5f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877046851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.3877046851
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.4129641154
Short name T245
Test name
Test status
Simulation time 1107716879409 ps
CPU time 774.14 seconds
Started Jul 28 04:29:45 PM PDT 24
Finished Jul 28 04:42:39 PM PDT 24
Peak memory 191512 kb
Host smart-50d36d4a-dcfa-4151-98a3-775f8565c400
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129641154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.4129641154
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all_with_rand_reset.36660848
Short name T409
Test name
Test status
Simulation time 302626476645 ps
CPU time 572.59 seconds
Started Jul 28 04:29:30 PM PDT 24
Finished Jul 28 04:39:03 PM PDT 24
Peak memory 207292 kb
Host smart-bb526546-dd91-48a2-ac59-baba21b6e88f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36660848 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all_with_rand_reset.36660848
Directory /workspace/49.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.3981541220
Short name T165
Test name
Test status
Simulation time 227882538700 ps
CPU time 350.88 seconds
Started Jul 28 04:22:20 PM PDT 24
Finished Jul 28 04:28:11 PM PDT 24
Peak memory 183524 kb
Host smart-05af60fa-b739-435f-bca8-6e7109cefed5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981541220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.3981541220
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.3770815674
Short name T396
Test name
Test status
Simulation time 92910718901 ps
CPU time 120.38 seconds
Started Jul 28 04:23:49 PM PDT 24
Finished Jul 28 04:25:49 PM PDT 24
Peak memory 183336 kb
Host smart-ed131066-c1d4-469e-b568-cc80c2b88d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770815674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.3770815674
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.2028157860
Short name T321
Test name
Test status
Simulation time 166822758029 ps
CPU time 61.76 seconds
Started Jul 28 04:23:35 PM PDT 24
Finished Jul 28 04:24:37 PM PDT 24
Peak memory 183512 kb
Host smart-0f038317-7099-4441-8b34-2b61e9c73bb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028157860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.2028157860
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.1585371048
Short name T350
Test name
Test status
Simulation time 132005904 ps
CPU time 0.74 seconds
Started Jul 28 04:24:49 PM PDT 24
Finished Jul 28 04:24:51 PM PDT 24
Peak memory 191364 kb
Host smart-404d7f3e-50d1-45ec-83c0-ca1b71e7fa75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585371048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.1585371048
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.1852390502
Short name T449
Test name
Test status
Simulation time 248539782972 ps
CPU time 384.04 seconds
Started Jul 28 04:29:25 PM PDT 24
Finished Jul 28 04:35:49 PM PDT 24
Peak memory 191504 kb
Host smart-2f992f05-ab5f-42ac-94e6-66a26f1b98e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852390502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.1852390502
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.673500933
Short name T386
Test name
Test status
Simulation time 35704653946 ps
CPU time 7.18 seconds
Started Jul 28 04:29:26 PM PDT 24
Finished Jul 28 04:29:33 PM PDT 24
Peak memory 183164 kb
Host smart-190d501a-553c-4982-a9c3-c3b5697f75a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673500933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.673500933
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.3596770984
Short name T186
Test name
Test status
Simulation time 317500417547 ps
CPU time 736.02 seconds
Started Jul 28 04:29:27 PM PDT 24
Finished Jul 28 04:41:43 PM PDT 24
Peak memory 191540 kb
Host smart-62cf7a31-2f37-4a4f-add5-3db4678aca4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596770984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.3596770984
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.1072159887
Short name T181
Test name
Test status
Simulation time 319338625685 ps
CPU time 655.01 seconds
Started Jul 28 04:29:45 PM PDT 24
Finished Jul 28 04:40:40 PM PDT 24
Peak memory 192548 kb
Host smart-374f679b-b9d8-4269-8f1b-dffd56e909c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072159887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.1072159887
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.1773339102
Short name T381
Test name
Test status
Simulation time 90786321406 ps
CPU time 182.32 seconds
Started Jul 28 04:29:30 PM PDT 24
Finished Jul 28 04:32:32 PM PDT 24
Peak memory 183352 kb
Host smart-7bd09b88-3c89-4306-947c-8b274b2b54b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773339102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.1773339102
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.3515374418
Short name T306
Test name
Test status
Simulation time 1807809681 ps
CPU time 3.01 seconds
Started Jul 28 04:29:31 PM PDT 24
Finished Jul 28 04:29:34 PM PDT 24
Peak memory 183132 kb
Host smart-18699dff-d764-45b8-bead-98b1bcdc8373
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515374418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.3515374418
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.66606028
Short name T218
Test name
Test status
Simulation time 310531059174 ps
CPU time 290.76 seconds
Started Jul 28 04:29:29 PM PDT 24
Finished Jul 28 04:34:20 PM PDT 24
Peak memory 195104 kb
Host smart-f490f923-7979-4824-8111-4025741f5a0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66606028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.66606028
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.3828526408
Short name T104
Test name
Test status
Simulation time 477189880409 ps
CPU time 659.25 seconds
Started Jul 28 04:29:32 PM PDT 24
Finished Jul 28 04:40:31 PM PDT 24
Peak memory 191528 kb
Host smart-47777d4c-29b3-4d1b-aae7-989b71a5d401
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828526408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.3828526408
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.182571480
Short name T257
Test name
Test status
Simulation time 568512343957 ps
CPU time 287.62 seconds
Started Jul 28 04:25:15 PM PDT 24
Finished Jul 28 04:30:02 PM PDT 24
Peak memory 183300 kb
Host smart-29af35f8-2ced-4277-bc26-d8009e7e20d9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182571480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.rv_timer_cfg_update_on_fly.182571480
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.1639096952
Short name T27
Test name
Test status
Simulation time 172027722327 ps
CPU time 218.85 seconds
Started Jul 28 04:21:07 PM PDT 24
Finished Jul 28 04:24:46 PM PDT 24
Peak memory 183428 kb
Host smart-7cd1d66d-6727-420b-b2f1-acda2e8800b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639096952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.1639096952
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.855731033
Short name T290
Test name
Test status
Simulation time 881422476620 ps
CPU time 976.79 seconds
Started Jul 28 04:24:55 PM PDT 24
Finished Jul 28 04:41:12 PM PDT 24
Peak memory 190668 kb
Host smart-e98c23d0-ecdd-4038-acb1-c3bdba95d457
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855731033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.855731033
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.283290268
Short name T296
Test name
Test status
Simulation time 92107181120 ps
CPU time 164.92 seconds
Started Jul 28 04:23:47 PM PDT 24
Finished Jul 28 04:26:32 PM PDT 24
Peak memory 183512 kb
Host smart-3ec6ba73-2343-4103-9f74-5e49d1d6a636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283290268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.283290268
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.3482976639
Short name T124
Test name
Test status
Simulation time 512675906501 ps
CPU time 369.76 seconds
Started Jul 28 04:29:34 PM PDT 24
Finished Jul 28 04:35:44 PM PDT 24
Peak memory 190976 kb
Host smart-9d4751f6-98d5-4fbd-bfa9-dd6a410f286e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482976639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.3482976639
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.42716724
Short name T224
Test name
Test status
Simulation time 155001287189 ps
CPU time 68.29 seconds
Started Jul 28 04:29:30 PM PDT 24
Finished Jul 28 04:30:38 PM PDT 24
Peak memory 191556 kb
Host smart-212be947-de50-4fbb-91c7-90905a6ece05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42716724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.42716724
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.3501084258
Short name T427
Test name
Test status
Simulation time 39666588270 ps
CPU time 311.5 seconds
Started Jul 28 04:30:39 PM PDT 24
Finished Jul 28 04:35:51 PM PDT 24
Peak memory 183076 kb
Host smart-0ba5602a-d846-404f-96b7-ce9ccf19a9de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501084258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.3501084258
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.1921150328
Short name T137
Test name
Test status
Simulation time 63370123813 ps
CPU time 245.07 seconds
Started Jul 28 04:29:25 PM PDT 24
Finished Jul 28 04:33:30 PM PDT 24
Peak memory 191512 kb
Host smart-b786fb16-c61a-49ac-921b-12310b824435
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921150328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.1921150328
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.2056917584
Short name T250
Test name
Test status
Simulation time 130528381610 ps
CPU time 468.92 seconds
Started Jul 28 04:29:34 PM PDT 24
Finished Jul 28 04:37:23 PM PDT 24
Peak memory 191504 kb
Host smart-b3fa5d21-9198-4c0e-85e6-6cc7cd24357c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056917584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.2056917584
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.1919899588
Short name T156
Test name
Test status
Simulation time 66600725122 ps
CPU time 158.09 seconds
Started Jul 28 04:30:40 PM PDT 24
Finished Jul 28 04:33:19 PM PDT 24
Peak memory 191284 kb
Host smart-2d16779f-7d6c-4344-bb21-a22ebe522ec6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919899588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.1919899588
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.473529312
Short name T261
Test name
Test status
Simulation time 39408700337 ps
CPU time 62.03 seconds
Started Jul 28 04:29:38 PM PDT 24
Finished Jul 28 04:30:40 PM PDT 24
Peak memory 183312 kb
Host smart-a86180d1-3b89-44d3-b574-af6166bc0e03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473529312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.473529312
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.969476422
Short name T172
Test name
Test status
Simulation time 144324421603 ps
CPU time 485.17 seconds
Started Jul 28 04:30:40 PM PDT 24
Finished Jul 28 04:38:46 PM PDT 24
Peak memory 191148 kb
Host smart-94e6f9db-e48e-4742-b55c-9085b9b66f11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969476422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.969476422
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.4157258043
Short name T193
Test name
Test status
Simulation time 162830853891 ps
CPU time 553.02 seconds
Started Jul 28 04:29:34 PM PDT 24
Finished Jul 28 04:38:47 PM PDT 24
Peak memory 191504 kb
Host smart-0973277a-516a-4d2c-a4ce-92b6c5b3c75f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157258043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.4157258043
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.3986332508
Short name T3
Test name
Test status
Simulation time 555978781070 ps
CPU time 228.37 seconds
Started Jul 28 04:23:27 PM PDT 24
Finished Jul 28 04:27:15 PM PDT 24
Peak memory 183364 kb
Host smart-f2860cf0-9735-4c43-b62f-01d1e29aacea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986332508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.3986332508
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.3781170684
Short name T159
Test name
Test status
Simulation time 580881286945 ps
CPU time 224.36 seconds
Started Jul 28 04:21:50 PM PDT 24
Finished Jul 28 04:25:34 PM PDT 24
Peak memory 191556 kb
Host smart-00185e50-cc77-4b7b-8249-ef41a06a773a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781170684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.3781170684
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.1049692143
Short name T435
Test name
Test status
Simulation time 10058447657 ps
CPU time 16.94 seconds
Started Jul 28 04:20:58 PM PDT 24
Finished Jul 28 04:21:15 PM PDT 24
Peak memory 194588 kb
Host smart-9f9099f5-cc89-442f-9ef9-6ef3eba0e11d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049692143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.1049692143
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.1692598681
Short name T232
Test name
Test status
Simulation time 576363804344 ps
CPU time 520.58 seconds
Started Jul 28 04:29:29 PM PDT 24
Finished Jul 28 04:38:09 PM PDT 24
Peak memory 191552 kb
Host smart-8a1e4784-abea-425d-840b-af9ae7aea072
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692598681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.1692598681
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.385940297
Short name T266
Test name
Test status
Simulation time 375101353170 ps
CPU time 516.93 seconds
Started Jul 28 04:29:30 PM PDT 24
Finished Jul 28 04:38:07 PM PDT 24
Peak memory 191712 kb
Host smart-3195f54e-4bb0-40fc-83ef-e7a3f8393ff4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385940297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.385940297
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.1085813255
Short name T339
Test name
Test status
Simulation time 54593384317 ps
CPU time 102.71 seconds
Started Jul 28 04:29:39 PM PDT 24
Finished Jul 28 04:31:22 PM PDT 24
Peak memory 191516 kb
Host smart-9f05d975-2034-421a-95c0-a0ee47d874bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085813255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.1085813255
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.3346130599
Short name T233
Test name
Test status
Simulation time 388651254027 ps
CPU time 573.78 seconds
Started Jul 28 04:29:27 PM PDT 24
Finished Jul 28 04:39:01 PM PDT 24
Peak memory 191520 kb
Host smart-3cd10827-8aab-4954-a4ab-6602a3ce9b43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346130599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.3346130599
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.2179229201
Short name T263
Test name
Test status
Simulation time 544829323983 ps
CPU time 293.18 seconds
Started Jul 28 04:29:27 PM PDT 24
Finished Jul 28 04:34:20 PM PDT 24
Peak memory 191564 kb
Host smart-fc64e108-7b5b-49e4-b289-bcd1d42a26cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179229201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.2179229201
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.1878119163
Short name T271
Test name
Test status
Simulation time 131496140009 ps
CPU time 254.44 seconds
Started Jul 28 04:29:33 PM PDT 24
Finished Jul 28 04:33:47 PM PDT 24
Peak memory 191576 kb
Host smart-e5fb3891-51c7-4c00-8968-cf85dddc7259
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878119163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.1878119163
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.2027406001
Short name T391
Test name
Test status
Simulation time 440892927 ps
CPU time 3.83 seconds
Started Jul 28 04:29:30 PM PDT 24
Finished Jul 28 04:29:34 PM PDT 24
Peak memory 183220 kb
Host smart-8b8bf489-9388-4bf4-8e3f-919adfe563ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027406001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.2027406001
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.1004097561
Short name T382
Test name
Test status
Simulation time 52793119675 ps
CPU time 97.56 seconds
Started Jul 28 04:21:35 PM PDT 24
Finished Jul 28 04:23:13 PM PDT 24
Peak memory 183412 kb
Host smart-b0e0e4e3-c07f-44c8-8331-11114ec6260d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004097561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.1004097561
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.2464652336
Short name T444
Test name
Test status
Simulation time 378103393833 ps
CPU time 205.11 seconds
Started Jul 28 04:25:02 PM PDT 24
Finished Jul 28 04:28:28 PM PDT 24
Peak memory 183344 kb
Host smart-ad213c93-e8cb-43e3-bfc4-f08cfec3fb0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464652336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.2464652336
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.4154039325
Short name T277
Test name
Test status
Simulation time 304659939985 ps
CPU time 184.89 seconds
Started Jul 28 04:21:10 PM PDT 24
Finished Jul 28 04:24:14 PM PDT 24
Peak memory 192624 kb
Host smart-bb5efdbd-3009-4b41-950d-6317b2cdfc6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154039325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.4154039325
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.2853374929
Short name T231
Test name
Test status
Simulation time 51126740198 ps
CPU time 78.89 seconds
Started Jul 28 04:20:14 PM PDT 24
Finished Jul 28 04:21:33 PM PDT 24
Peak memory 191600 kb
Host smart-cf86fe26-3c4d-4f9e-b7ca-ea524e6af4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853374929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.2853374929
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.1734909667
Short name T74
Test name
Test status
Simulation time 793776855084 ps
CPU time 562.7 seconds
Started Jul 28 04:24:37 PM PDT 24
Finished Jul 28 04:34:00 PM PDT 24
Peak memory 190636 kb
Host smart-81fb589c-d3de-46d3-b18f-f171df923d76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734909667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
1734909667
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/80.rv_timer_random.226931886
Short name T139
Test name
Test status
Simulation time 790383706778 ps
CPU time 407.11 seconds
Started Jul 28 04:29:32 PM PDT 24
Finished Jul 28 04:36:20 PM PDT 24
Peak memory 191528 kb
Host smart-95fe72af-6297-4492-9f6c-ddfaa1a6e847
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226931886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.226931886
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.2552350872
Short name T108
Test name
Test status
Simulation time 337398978801 ps
CPU time 212.98 seconds
Started Jul 28 04:30:38 PM PDT 24
Finished Jul 28 04:34:11 PM PDT 24
Peak memory 191284 kb
Host smart-de8fbad0-5057-4dfb-afba-66b65c1d635b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552350872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.2552350872
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.4225956455
Short name T268
Test name
Test status
Simulation time 439682959778 ps
CPU time 1158.16 seconds
Started Jul 28 04:29:46 PM PDT 24
Finished Jul 28 04:49:04 PM PDT 24
Peak memory 191544 kb
Host smart-4d826f59-7aa0-460b-bc41-d284453d9ed0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225956455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.4225956455
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.3584283813
Short name T228
Test name
Test status
Simulation time 968259108999 ps
CPU time 574.05 seconds
Started Jul 28 04:29:30 PM PDT 24
Finished Jul 28 04:39:04 PM PDT 24
Peak memory 194892 kb
Host smart-5d82174f-5c92-4905-893a-7c664fd1e02d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584283813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.3584283813
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.2103998027
Short name T161
Test name
Test status
Simulation time 212056014639 ps
CPU time 463.85 seconds
Started Jul 28 04:29:30 PM PDT 24
Finished Jul 28 04:37:14 PM PDT 24
Peak memory 191484 kb
Host smart-b52f5249-3c39-483b-a571-cbe632076ebf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103998027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.2103998027
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.2353214370
Short name T190
Test name
Test status
Simulation time 115408861864 ps
CPU time 186.08 seconds
Started Jul 28 04:29:53 PM PDT 24
Finished Jul 28 04:32:59 PM PDT 24
Peak memory 191516 kb
Host smart-ce2d3243-0a96-4818-b1a2-381ec22dde91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353214370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.2353214370
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.179169109
Short name T42
Test name
Test status
Simulation time 65145008931 ps
CPU time 65.64 seconds
Started Jul 28 04:29:31 PM PDT 24
Finished Jul 28 04:30:37 PM PDT 24
Peak memory 183760 kb
Host smart-c43c099b-0df0-49b3-9010-08d1226ff129
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179169109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.179169109
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.2155635771
Short name T288
Test name
Test status
Simulation time 115341315791 ps
CPU time 84.44 seconds
Started Jul 28 04:29:30 PM PDT 24
Finished Jul 28 04:30:55 PM PDT 24
Peak memory 191548 kb
Host smart-eb266c2a-b105-4d2c-bb7e-79576732a455
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155635771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.2155635771
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.2080917619
Short name T278
Test name
Test status
Simulation time 891473939976 ps
CPU time 422.99 seconds
Started Jul 28 04:24:37 PM PDT 24
Finished Jul 28 04:31:40 PM PDT 24
Peak memory 182248 kb
Host smart-617f320d-6ef9-42f7-8634-c3ef154353e1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080917619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.2080917619
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_random.248385314
Short name T26
Test name
Test status
Simulation time 42285065026 ps
CPU time 46.08 seconds
Started Jul 28 04:25:49 PM PDT 24
Finished Jul 28 04:26:35 PM PDT 24
Peak memory 191532 kb
Host smart-ce87a825-02db-41cd-b365-353bc99034ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248385314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.248385314
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.2799109158
Short name T405
Test name
Test status
Simulation time 131936259331 ps
CPU time 96.58 seconds
Started Jul 28 04:24:52 PM PDT 24
Finished Jul 28 04:26:28 PM PDT 24
Peak memory 195056 kb
Host smart-31d59d43-d64c-43be-9bad-2784848e137d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799109158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.2799109158
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.3284155453
Short name T439
Test name
Test status
Simulation time 388919291470 ps
CPU time 72.37 seconds
Started Jul 28 04:25:49 PM PDT 24
Finished Jul 28 04:27:02 PM PDT 24
Peak memory 183352 kb
Host smart-bf34bced-2d8f-4d36-8709-54fa68d5e5ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284155453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
3284155453
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/90.rv_timer_random.2560520756
Short name T147
Test name
Test status
Simulation time 151859621368 ps
CPU time 240.5 seconds
Started Jul 28 04:29:32 PM PDT 24
Finished Jul 28 04:33:32 PM PDT 24
Peak memory 191552 kb
Host smart-a8e6d5c8-1932-4ed1-8567-41776e285845
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560520756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.2560520756
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.2360664829
Short name T191
Test name
Test status
Simulation time 1281851030095 ps
CPU time 795.96 seconds
Started Jul 28 04:29:29 PM PDT 24
Finished Jul 28 04:42:45 PM PDT 24
Peak memory 191536 kb
Host smart-acadd823-7e83-4fc3-8dd2-e88c9f5d1ad8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360664829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.2360664829
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.3783521997
Short name T359
Test name
Test status
Simulation time 1634632995 ps
CPU time 9.24 seconds
Started Jul 28 04:29:39 PM PDT 24
Finished Jul 28 04:29:49 PM PDT 24
Peak memory 183292 kb
Host smart-208f4662-baa3-4bf1-b48b-83180415e0d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783521997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.3783521997
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.2126508267
Short name T327
Test name
Test status
Simulation time 48580254896 ps
CPU time 124.52 seconds
Started Jul 28 04:29:26 PM PDT 24
Finished Jul 28 04:31:31 PM PDT 24
Peak memory 191508 kb
Host smart-b659e55f-f30c-4603-8574-1c49febb3ddd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126508267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.2126508267
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.1667697782
Short name T223
Test name
Test status
Simulation time 363197031666 ps
CPU time 250.19 seconds
Started Jul 28 04:29:31 PM PDT 24
Finished Jul 28 04:33:42 PM PDT 24
Peak memory 191520 kb
Host smart-12af3038-4f06-4734-b280-ef2e5697888b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667697782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.1667697782
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.3912183405
Short name T335
Test name
Test status
Simulation time 45449282877 ps
CPU time 68.79 seconds
Started Jul 28 04:29:41 PM PDT 24
Finished Jul 28 04:30:50 PM PDT 24
Peak memory 183376 kb
Host smart-cd2b16b4-ab24-45d8-996e-e838be84fdd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912183405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.3912183405
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.1972682786
Short name T313
Test name
Test status
Simulation time 70026673296 ps
CPU time 91.86 seconds
Started Jul 28 04:30:39 PM PDT 24
Finished Jul 28 04:32:11 PM PDT 24
Peak memory 183076 kb
Host smart-2a5abd37-8c04-4ac5-a8d4-c17d5e292dd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972682786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.1972682786
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.1180437170
Short name T226
Test name
Test status
Simulation time 134515617413 ps
CPU time 102.78 seconds
Started Jul 28 04:29:32 PM PDT 24
Finished Jul 28 04:31:15 PM PDT 24
Peak memory 191712 kb
Host smart-002edb8a-23c9-4d58-a930-ae2e10de008e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180437170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.1180437170
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.2532458542
Short name T133
Test name
Test status
Simulation time 270993045943 ps
CPU time 237.45 seconds
Started Jul 28 04:29:41 PM PDT 24
Finished Jul 28 04:33:39 PM PDT 24
Peak memory 191712 kb
Host smart-0a49eee5-413e-40c5-a625-2ce5b2f6de18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532458542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.2532458542
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.3220476279
Short name T203
Test name
Test status
Simulation time 105884675873 ps
CPU time 891.47 seconds
Started Jul 28 04:29:30 PM PDT 24
Finished Jul 28 04:44:22 PM PDT 24
Peak memory 191576 kb
Host smart-5c5e43f7-cff1-4565-9a19-2062b0c1aac4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220476279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.3220476279
Directory /workspace/99.rv_timer_random/latest
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