Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
1420 |
1 |
|
T4 |
17 |
|
T12 |
65 |
|
T34 |
7 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
779 |
1 |
|
T4 |
7 |
|
T12 |
31 |
|
T34 |
2 |
auto[1] |
641 |
1 |
|
T4 |
10 |
|
T12 |
34 |
|
T34 |
5 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
541 |
1 |
|
T4 |
10 |
|
T12 |
24 |
|
T13 |
5 |
auto[1] |
879 |
1 |
|
T4 |
7 |
|
T12 |
41 |
|
T34 |
7 |
Summary for Variable cp_intr_test
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_test
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
825 |
1 |
|
T4 |
13 |
|
T12 |
41 |
|
T34 |
3 |
auto[1] |
595 |
1 |
|
T4 |
4 |
|
T12 |
24 |
|
T34 |
4 |
Summary for Cross intr_test_cg_cc
Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for intr_test_cg_cc
Bins
cp_intr | cp_intr_test | cp_intr_en | cp_intr_state | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
auto[0] |
284 |
1 |
|
T4 |
3 |
|
T12 |
11 |
|
T13 |
3 |
all_values[0] |
auto[0] |
auto[0] |
auto[1] |
152 |
1 |
|
T4 |
2 |
|
T12 |
10 |
|
T13 |
1 |
all_values[0] |
auto[0] |
auto[1] |
auto[0] |
257 |
1 |
|
T4 |
7 |
|
T12 |
13 |
|
T13 |
2 |
all_values[0] |
auto[0] |
auto[1] |
auto[1] |
132 |
1 |
|
T4 |
1 |
|
T12 |
7 |
|
T34 |
3 |
all_values[0] |
auto[1] |
auto[0] |
auto[1] |
343 |
1 |
|
T4 |
2 |
|
T12 |
10 |
|
T34 |
2 |
all_values[0] |
auto[1] |
auto[1] |
auto[1] |
252 |
1 |
|
T4 |
2 |
|
T12 |
14 |
|
T34 |
2 |
User Defined Cross Bins for intr_test_cg_cc
Excluded/Illegal bins
NAME | COUNT | STATUS |
test_1_state_0 |
0 |
Illegal |