Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.64 99.36 98.73 100.00 100.00 100.00 99.77


Total test records in report: 580
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T507 /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.2303615292 Jul 29 04:21:15 PM PDT 24 Jul 29 04:21:15 PM PDT 24 69240082 ps
T508 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.1749058888 Jul 29 04:25:02 PM PDT 24 Jul 29 04:25:03 PM PDT 24 30711545 ps
T509 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.4054178645 Jul 29 04:21:10 PM PDT 24 Jul 29 04:21:11 PM PDT 24 17182379 ps
T89 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1635518041 Jul 29 04:21:34 PM PDT 24 Jul 29 04:21:35 PM PDT 24 220673390 ps
T510 /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.1146039223 Jul 29 04:20:09 PM PDT 24 Jul 29 04:20:09 PM PDT 24 49652450 ps
T511 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.2093981997 Jul 29 04:19:38 PM PDT 24 Jul 29 04:19:42 PM PDT 24 3703485784 ps
T512 /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.3335263585 Jul 29 04:25:40 PM PDT 24 Jul 29 04:25:41 PM PDT 24 208512791 ps
T513 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.2993185219 Jul 29 04:19:36 PM PDT 24 Jul 29 04:19:38 PM PDT 24 674946402 ps
T514 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.754145045 Jul 29 04:25:56 PM PDT 24 Jul 29 04:25:57 PM PDT 24 16239080 ps
T515 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.2834913491 Jul 29 04:20:23 PM PDT 24 Jul 29 04:20:25 PM PDT 24 338560838 ps
T516 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.2293413164 Jul 29 04:25:04 PM PDT 24 Jul 29 04:25:05 PM PDT 24 218980968 ps
T517 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.3434214336 Jul 29 04:20:18 PM PDT 24 Jul 29 04:20:20 PM PDT 24 380625057 ps
T518 /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.3410591163 Jul 29 04:20:43 PM PDT 24 Jul 29 04:20:43 PM PDT 24 13307877 ps
T519 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.1172892794 Jul 29 04:20:23 PM PDT 24 Jul 29 04:20:24 PM PDT 24 36871120 ps
T520 /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1095099045 Jul 29 04:25:41 PM PDT 24 Jul 29 04:25:42 PM PDT 24 12931892 ps
T521 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.2593185340 Jul 29 04:25:03 PM PDT 24 Jul 29 04:25:04 PM PDT 24 45868406 ps
T69 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1793648792 Jul 29 04:25:26 PM PDT 24 Jul 29 04:25:27 PM PDT 24 39628485 ps
T522 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3244331070 Jul 29 04:20:22 PM PDT 24 Jul 29 04:20:23 PM PDT 24 87933665 ps
T523 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.4113698294 Jul 29 04:25:31 PM PDT 24 Jul 29 04:25:32 PM PDT 24 15490118 ps
T524 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.325429483 Jul 29 04:20:55 PM PDT 24 Jul 29 04:20:55 PM PDT 24 27271307 ps
T525 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3032381880 Jul 29 04:25:03 PM PDT 24 Jul 29 04:25:04 PM PDT 24 76585719 ps
T526 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.2797551373 Jul 29 04:21:09 PM PDT 24 Jul 29 04:21:10 PM PDT 24 65337218 ps
T527 /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.1686174742 Jul 29 04:19:31 PM PDT 24 Jul 29 04:19:33 PM PDT 24 193627267 ps
T528 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.3694120660 Jul 29 04:24:58 PM PDT 24 Jul 29 04:24:59 PM PDT 24 73887952 ps
T529 /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.1412442573 Jul 29 04:25:24 PM PDT 24 Jul 29 04:25:26 PM PDT 24 165285646 ps
T530 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.2027563292 Jul 29 04:20:23 PM PDT 24 Jul 29 04:20:23 PM PDT 24 13535432 ps
T531 /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3189434847 Jul 29 04:23:55 PM PDT 24 Jul 29 04:23:56 PM PDT 24 25252215 ps
T532 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.3775278566 Jul 29 04:25:04 PM PDT 24 Jul 29 04:25:04 PM PDT 24 42002973 ps
T533 /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.2071703439 Jul 29 04:24:59 PM PDT 24 Jul 29 04:25:01 PM PDT 24 157603356 ps
T534 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1768937504 Jul 29 04:25:28 PM PDT 24 Jul 29 04:25:29 PM PDT 24 66450233 ps
T535 /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.1388678912 Jul 29 04:20:25 PM PDT 24 Jul 29 04:20:27 PM PDT 24 22425332 ps
T536 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.2671179607 Jul 29 04:19:36 PM PDT 24 Jul 29 04:19:38 PM PDT 24 496508016 ps
T537 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.750629456 Jul 29 04:25:18 PM PDT 24 Jul 29 04:25:19 PM PDT 24 103924113 ps
T538 /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.4215429303 Jul 29 04:26:10 PM PDT 24 Jul 29 04:26:11 PM PDT 24 47414115 ps
T539 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.3898165499 Jul 29 04:19:42 PM PDT 24 Jul 29 04:19:43 PM PDT 24 146158171 ps
T540 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.3368252509 Jul 29 04:23:50 PM PDT 24 Jul 29 04:23:51 PM PDT 24 156824355 ps
T541 /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.4046576235 Jul 29 04:20:32 PM PDT 24 Jul 29 04:20:33 PM PDT 24 11475315 ps
T542 /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.4266537162 Jul 29 04:20:24 PM PDT 24 Jul 29 04:20:25 PM PDT 24 32163338 ps
T543 /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.2658300071 Jul 29 04:25:11 PM PDT 24 Jul 29 04:25:12 PM PDT 24 12678636 ps
T544 /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.562273254 Jul 29 04:25:31 PM PDT 24 Jul 29 04:25:34 PM PDT 24 358468949 ps
T545 /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.3107098036 Jul 29 04:20:29 PM PDT 24 Jul 29 04:20:30 PM PDT 24 40619621 ps
T70 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.4287882416 Jul 29 04:25:54 PM PDT 24 Jul 29 04:25:55 PM PDT 24 42609192 ps
T546 /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.815602647 Jul 29 04:19:35 PM PDT 24 Jul 29 04:19:38 PM PDT 24 1454403283 ps
T547 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3378073324 Jul 29 04:21:15 PM PDT 24 Jul 29 04:21:16 PM PDT 24 1428516421 ps
T548 /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.2346138356 Jul 29 04:20:04 PM PDT 24 Jul 29 04:20:05 PM PDT 24 14925590 ps
T549 /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.1707701305 Jul 29 04:20:29 PM PDT 24 Jul 29 04:20:30 PM PDT 24 29751716 ps
T550 /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3568621095 Jul 29 04:25:27 PM PDT 24 Jul 29 04:25:30 PM PDT 24 870110488 ps
T551 /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.977509451 Jul 29 04:20:39 PM PDT 24 Jul 29 04:20:40 PM PDT 24 39549935 ps
T552 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.2348105106 Jul 29 04:25:18 PM PDT 24 Jul 29 04:25:19 PM PDT 24 26711480 ps
T553 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.1699580347 Jul 29 04:20:21 PM PDT 24 Jul 29 04:20:23 PM PDT 24 729343312 ps
T554 /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.266476347 Jul 29 04:20:33 PM PDT 24 Jul 29 04:20:34 PM PDT 24 47782260 ps
T71 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2736163729 Jul 29 04:21:25 PM PDT 24 Jul 29 04:21:26 PM PDT 24 21404805 ps
T555 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.3652000387 Jul 29 04:23:15 PM PDT 24 Jul 29 04:23:16 PM PDT 24 52612922 ps
T556 /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.231896168 Jul 29 04:19:35 PM PDT 24 Jul 29 04:19:36 PM PDT 24 15241124 ps
T557 /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.513113411 Jul 29 04:23:09 PM PDT 24 Jul 29 04:23:10 PM PDT 24 15619184 ps
T558 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.3477301923 Jul 29 04:20:50 PM PDT 24 Jul 29 04:20:51 PM PDT 24 14691444 ps
T559 /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.3217686710 Jul 29 04:26:11 PM PDT 24 Jul 29 04:26:11 PM PDT 24 21254164 ps
T73 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.3688421139 Jul 29 04:25:38 PM PDT 24 Jul 29 04:25:39 PM PDT 24 26739641 ps
T560 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.3012314823 Jul 29 04:26:23 PM PDT 24 Jul 29 04:26:24 PM PDT 24 64933742 ps
T561 /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.2460161034 Jul 29 04:20:57 PM PDT 24 Jul 29 04:20:58 PM PDT 24 46482498 ps
T562 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.351573379 Jul 29 04:25:44 PM PDT 24 Jul 29 04:25:44 PM PDT 24 23832023 ps
T563 /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.2736845800 Jul 29 04:20:23 PM PDT 24 Jul 29 04:20:24 PM PDT 24 121923134 ps
T564 /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.4275532296 Jul 29 04:25:38 PM PDT 24 Jul 29 04:25:39 PM PDT 24 37411900 ps
T565 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1026784580 Jul 29 04:24:21 PM PDT 24 Jul 29 04:24:22 PM PDT 24 84328538 ps
T566 /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1779794768 Jul 29 04:20:21 PM PDT 24 Jul 29 04:20:22 PM PDT 24 120107030 ps
T567 /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.757438458 Jul 29 04:21:05 PM PDT 24 Jul 29 04:21:08 PM PDT 24 105810506 ps
T568 /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.213157797 Jul 29 04:21:12 PM PDT 24 Jul 29 04:21:13 PM PDT 24 50367306 ps
T569 /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.2890790245 Jul 29 04:25:56 PM PDT 24 Jul 29 04:25:58 PM PDT 24 81835250 ps
T570 /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.461542156 Jul 29 04:19:35 PM PDT 24 Jul 29 04:19:36 PM PDT 24 385003689 ps
T571 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.132843023 Jul 29 04:21:05 PM PDT 24 Jul 29 04:21:05 PM PDT 24 33043475 ps
T572 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.3922304234 Jul 29 04:22:48 PM PDT 24 Jul 29 04:22:49 PM PDT 24 23605323 ps
T573 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1623808429 Jul 29 04:27:07 PM PDT 24 Jul 29 04:27:08 PM PDT 24 11218730 ps
T574 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2051334236 Jul 29 04:22:39 PM PDT 24 Jul 29 04:22:41 PM PDT 24 85767003 ps
T575 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.1100041450 Jul 29 04:20:29 PM PDT 24 Jul 29 04:20:30 PM PDT 24 57899023 ps
T576 /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.3686460582 Jul 29 04:20:36 PM PDT 24 Jul 29 04:20:38 PM PDT 24 26504481 ps
T72 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.3803848913 Jul 29 04:20:55 PM PDT 24 Jul 29 04:20:55 PM PDT 24 21704525 ps
T577 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3149624745 Jul 29 04:21:13 PM PDT 24 Jul 29 04:21:16 PM PDT 24 150010412 ps
T578 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.2065570321 Jul 29 04:21:21 PM PDT 24 Jul 29 04:21:22 PM PDT 24 24700608 ps
T579 /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.142806987 Jul 29 04:21:32 PM PDT 24 Jul 29 04:21:33 PM PDT 24 18927573 ps
T580 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.680566345 Jul 29 04:22:04 PM PDT 24 Jul 29 04:22:05 PM PDT 24 16603907 ps

Test location /workspace/coverage/default/48.rv_timer_stress_all_with_rand_reset.3682878661
Short name T4
Test name
Test status
Simulation time 25923062748 ps
CPU time 99.1 seconds
Started Jul 29 04:25:25 PM PDT 24
Finished Jul 29 04:27:04 PM PDT 24
Peak memory 197940 kb
Host smart-0d50dec8-c02b-4208-9f3e-34c1fcebdd32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682878661 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all_with_rand_reset.3682878661
Directory /workspace/48.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rv_timer_random.2232815693
Short name T6
Test name
Test status
Simulation time 188100756859 ps
CPU time 912.65 seconds
Started Jul 29 04:22:38 PM PDT 24
Finished Jul 29 04:37:51 PM PDT 24
Peak memory 183572 kb
Host smart-f2fdaa84-b5fc-4bc8-95f2-a9595b59e9f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232815693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.2232815693
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.3125275770
Short name T97
Test name
Test status
Simulation time 3793820230806 ps
CPU time 2399.7 seconds
Started Jul 29 04:23:43 PM PDT 24
Finished Jul 29 05:03:43 PM PDT 24
Peak memory 191432 kb
Host smart-e9e02fa5-8650-4c55-baa8-fd595be90b1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125275770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.3125275770
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.376759402
Short name T14
Test name
Test status
Simulation time 107119920 ps
CPU time 0.81 seconds
Started Jul 29 04:19:36 PM PDT 24
Finished Jul 29 04:19:37 PM PDT 24
Peak memory 213568 kb
Host smart-badf7b7e-febe-4906-8d28-f4d6ad01a47a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376759402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.376759402
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.3825552653
Short name T177
Test name
Test status
Simulation time 2964333000388 ps
CPU time 2330.35 seconds
Started Jul 29 04:21:25 PM PDT 24
Finished Jul 29 05:00:16 PM PDT 24
Peak memory 191564 kb
Host smart-1bdb40eb-176d-47e8-97dd-e40665d259f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825552653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.3825552653
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.3404372911
Short name T133
Test name
Test status
Simulation time 1495024969177 ps
CPU time 1431.82 seconds
Started Jul 29 04:25:49 PM PDT 24
Finished Jul 29 04:49:42 PM PDT 24
Peak memory 191428 kb
Host smart-33424ac6-f08b-49d4-98b8-1acfb882dbd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404372911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.3404372911
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.3087691597
Short name T249
Test name
Test status
Simulation time 2791429926461 ps
CPU time 1368.92 seconds
Started Jul 29 04:25:46 PM PDT 24
Finished Jul 29 04:48:36 PM PDT 24
Peak memory 189988 kb
Host smart-7a7b888a-0a06-4808-8ad1-af1ed433966e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087691597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
3087691597
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.1975088526
Short name T141
Test name
Test status
Simulation time 4295321824068 ps
CPU time 3849.76 seconds
Started Jul 29 04:25:17 PM PDT 24
Finished Jul 29 05:29:27 PM PDT 24
Peak memory 195844 kb
Host smart-686abb7b-0b4e-494d-be95-e90238d1745c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975088526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.1975088526
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.4173136348
Short name T33
Test name
Test status
Simulation time 11307557 ps
CPU time 0.53 seconds
Started Jul 29 04:19:36 PM PDT 24
Finished Jul 29 04:19:37 PM PDT 24
Peak memory 182120 kb
Host smart-a5a173ec-296e-4587-a273-e76ad19d4f7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173136348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.4173136348
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.3796421189
Short name T176
Test name
Test status
Simulation time 383656668926 ps
CPU time 3056.85 seconds
Started Jul 29 04:24:03 PM PDT 24
Finished Jul 29 05:15:00 PM PDT 24
Peak memory 191448 kb
Host smart-2f811671-f430-483a-ad2f-85ed788877b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796421189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.3796421189
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.2889835930
Short name T148
Test name
Test status
Simulation time 1112609190850 ps
CPU time 4208.82 seconds
Started Jul 29 04:25:16 PM PDT 24
Finished Jul 29 05:35:26 PM PDT 24
Peak memory 190612 kb
Host smart-5440658c-4118-46d4-b064-43c0bb6e7080
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889835930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.2889835930
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.2189510572
Short name T28
Test name
Test status
Simulation time 122626381 ps
CPU time 1.12 seconds
Started Jul 29 04:20:25 PM PDT 24
Finished Jul 29 04:20:26 PM PDT 24
Peak memory 195344 kb
Host smart-91578bc0-b3dd-4980-93d4-b82ac4564c88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189510572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.2189510572
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/13.rv_timer_random.3056947447
Short name T10
Test name
Test status
Simulation time 1185030706980 ps
CPU time 1033.06 seconds
Started Jul 29 04:25:35 PM PDT 24
Finished Jul 29 04:42:49 PM PDT 24
Peak memory 190000 kb
Host smart-f0adc236-2dec-4995-afb1-f2dd1819eb04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056947447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.3056947447
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.4116386048
Short name T55
Test name
Test status
Simulation time 426367789955 ps
CPU time 1089.33 seconds
Started Jul 29 04:25:26 PM PDT 24
Finished Jul 29 04:43:36 PM PDT 24
Peak memory 190656 kb
Host smart-1ff3c9b5-7986-472a-b99b-c6c222d2d92f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116386048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.4116386048
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.3088168237
Short name T220
Test name
Test status
Simulation time 444142909982 ps
CPU time 726.91 seconds
Started Jul 29 04:22:36 PM PDT 24
Finished Jul 29 04:34:43 PM PDT 24
Peak memory 196084 kb
Host smart-f6f9bc25-82b8-42f4-917a-956c41077d1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088168237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.3088168237
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.3999326311
Short name T175
Test name
Test status
Simulation time 1312901332239 ps
CPU time 1386.82 seconds
Started Jul 29 04:25:25 PM PDT 24
Finished Jul 29 04:48:32 PM PDT 24
Peak memory 191364 kb
Host smart-e91c52fc-6588-4c21-9300-eb9e404f9bfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999326311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.3999326311
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.826679354
Short name T34
Test name
Test status
Simulation time 1103075068042 ps
CPU time 857.6 seconds
Started Jul 29 04:23:36 PM PDT 24
Finished Jul 29 04:37:54 PM PDT 24
Peak memory 191432 kb
Host smart-75b65927-2953-40aa-a14f-1f4f6a0e0730
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826679354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all.
826679354
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.2040647049
Short name T189
Test name
Test status
Simulation time 411631018437 ps
CPU time 2327.73 seconds
Started Jul 29 04:25:18 PM PDT 24
Finished Jul 29 05:04:06 PM PDT 24
Peak memory 195608 kb
Host smart-b31d61c3-5736-4fad-9ca5-1983c38443eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040647049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
2040647049
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/178.rv_timer_random.2377636333
Short name T226
Test name
Test status
Simulation time 2371304709521 ps
CPU time 749.58 seconds
Started Jul 29 04:26:50 PM PDT 24
Finished Jul 29 04:39:20 PM PDT 24
Peak memory 193736 kb
Host smart-d96bfa6e-8e46-4f04-ad2a-0fda3886704b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377636333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.2377636333
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.2798467939
Short name T156
Test name
Test status
Simulation time 3900201107513 ps
CPU time 1497.86 seconds
Started Jul 29 04:23:36 PM PDT 24
Finished Jul 29 04:48:35 PM PDT 24
Peak memory 191796 kb
Host smart-9f4203a9-185e-451a-9d59-938d62931f3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798467939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
2798467939
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.4247071882
Short name T92
Test name
Test status
Simulation time 299328545029 ps
CPU time 2617.61 seconds
Started Jul 29 04:25:11 PM PDT 24
Finished Jul 29 05:08:49 PM PDT 24
Peak memory 195992 kb
Host smart-4e775d57-b1ea-42e0-bc0e-b3e892593837
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247071882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.4247071882
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/165.rv_timer_random.3665382205
Short name T246
Test name
Test status
Simulation time 120820167344 ps
CPU time 292.93 seconds
Started Jul 29 04:25:44 PM PDT 24
Finished Jul 29 04:30:37 PM PDT 24
Peak memory 194480 kb
Host smart-01b8f5e9-97be-4349-9e97-95208952918c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665382205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.3665382205
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.2610062700
Short name T8
Test name
Test status
Simulation time 241524912442 ps
CPU time 189.4 seconds
Started Jul 29 04:25:00 PM PDT 24
Finished Jul 29 04:28:09 PM PDT 24
Peak memory 191452 kb
Host smart-b4851e60-42aa-4c86-96a7-8de5c183d16c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610062700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.2610062700
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random.349258982
Short name T183
Test name
Test status
Simulation time 202106883970 ps
CPU time 211.88 seconds
Started Jul 29 04:23:02 PM PDT 24
Finished Jul 29 04:26:34 PM PDT 24
Peak memory 191456 kb
Host smart-c9f4e919-eafd-4cfb-8f84-59cf2e2786b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349258982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.349258982
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.1515528620
Short name T208
Test name
Test status
Simulation time 451235861922 ps
CPU time 656.55 seconds
Started Jul 29 04:24:51 PM PDT 24
Finished Jul 29 04:35:48 PM PDT 24
Peak memory 191476 kb
Host smart-b6518d99-3947-42cf-974e-d87322f60c4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515528620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.1515528620
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.610113997
Short name T160
Test name
Test status
Simulation time 211784163343 ps
CPU time 971.17 seconds
Started Jul 29 04:25:02 PM PDT 24
Finished Jul 29 04:41:13 PM PDT 24
Peak memory 191468 kb
Host smart-19dd8ded-d0ec-4a42-a7e0-cb7155584432
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610113997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.610113997
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.845632758
Short name T99
Test name
Test status
Simulation time 392077836473 ps
CPU time 340.99 seconds
Started Jul 29 04:26:35 PM PDT 24
Finished Jul 29 04:32:17 PM PDT 24
Peak memory 191144 kb
Host smart-79bce5bb-7d02-4b2a-83e7-0e5f742899c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845632758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.845632758
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.3497004217
Short name T62
Test name
Test status
Simulation time 1318093395308 ps
CPU time 1779.93 seconds
Started Jul 29 04:21:43 PM PDT 24
Finished Jul 29 04:51:23 PM PDT 24
Peak memory 191472 kb
Host smart-9f53e7db-469f-43c5-9afc-76b1f810d791
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497004217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.3497004217
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_random.3955541973
Short name T260
Test name
Test status
Simulation time 364942848263 ps
CPU time 283.73 seconds
Started Jul 29 04:23:52 PM PDT 24
Finished Jul 29 04:28:36 PM PDT 24
Peak memory 191464 kb
Host smart-863c339d-eed4-4bd2-9e72-4a99d87352c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955541973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.3955541973
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.2472300175
Short name T56
Test name
Test status
Simulation time 332507322179 ps
CPU time 613.56 seconds
Started Jul 29 04:25:31 PM PDT 24
Finished Jul 29 04:35:45 PM PDT 24
Peak memory 191496 kb
Host smart-8ba1f0bd-3789-4c7a-8a7f-73fd932393e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472300175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
2472300175
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.1374656061
Short name T140
Test name
Test status
Simulation time 315484559679 ps
CPU time 485.48 seconds
Started Jul 29 04:25:13 PM PDT 24
Finished Jul 29 04:33:19 PM PDT 24
Peak memory 191452 kb
Host smart-99666424-ae16-432b-9336-1d59902abbf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374656061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.1374656061
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_random.522354034
Short name T93
Test name
Test status
Simulation time 66654409590 ps
CPU time 495.15 seconds
Started Jul 29 04:23:39 PM PDT 24
Finished Jul 29 04:31:54 PM PDT 24
Peak memory 191480 kb
Host smart-69ee8ba7-efc0-4bb5-a57d-387315d06936
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522354034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.522354034
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.1748513389
Short name T294
Test name
Test status
Simulation time 1999062971345 ps
CPU time 583.59 seconds
Started Jul 29 04:24:39 PM PDT 24
Finished Jul 29 04:34:23 PM PDT 24
Peak memory 191364 kb
Host smart-30d52656-45bb-4dd6-a337-c957c98d960e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748513389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.1748513389
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.176811724
Short name T265
Test name
Test status
Simulation time 993179234825 ps
CPU time 1448.89 seconds
Started Jul 29 04:25:47 PM PDT 24
Finished Jul 29 04:49:57 PM PDT 24
Peak memory 183272 kb
Host smart-7ac441c8-7898-4562-85ad-9667c8083697
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176811724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.176811724
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.1952685502
Short name T157
Test name
Test status
Simulation time 254423080835 ps
CPU time 827.5 seconds
Started Jul 29 04:25:39 PM PDT 24
Finished Jul 29 04:39:27 PM PDT 24
Peak memory 191392 kb
Host smart-a2453193-e472-484c-925c-33d995e8ccb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952685502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.1952685502
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.3600044958
Short name T210
Test name
Test status
Simulation time 1542353740735 ps
CPU time 1646.41 seconds
Started Jul 29 04:25:18 PM PDT 24
Finished Jul 29 04:52:45 PM PDT 24
Peak memory 191408 kb
Host smart-4dcf0f87-ac93-4363-88e3-c96ad318c79d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600044958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.3600044958
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/127.rv_timer_random.1632169387
Short name T329
Test name
Test status
Simulation time 126841586452 ps
CPU time 295.95 seconds
Started Jul 29 04:25:10 PM PDT 24
Finished Jul 29 04:30:06 PM PDT 24
Peak memory 195104 kb
Host smart-1797bb0f-c1ae-44a6-a0d8-1c02cb7f14c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632169387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.1632169387
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.4014566570
Short name T103
Test name
Test status
Simulation time 142425179533 ps
CPU time 538.47 seconds
Started Jul 29 04:26:50 PM PDT 24
Finished Jul 29 04:35:49 PM PDT 24
Peak memory 191120 kb
Host smart-cf1ba895-9528-4ce6-af08-cb01a9ac20bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014566570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.4014566570
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.2611897608
Short name T96
Test name
Test status
Simulation time 357543230574 ps
CPU time 799.76 seconds
Started Jul 29 04:26:50 PM PDT 24
Finished Jul 29 04:40:10 PM PDT 24
Peak memory 191088 kb
Host smart-2c7e69ac-3650-43d0-a150-57f5be9a66f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611897608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.2611897608
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random.2288812868
Short name T152
Test name
Test status
Simulation time 538152154095 ps
CPU time 531.07 seconds
Started Jul 29 04:20:24 PM PDT 24
Finished Jul 29 04:29:15 PM PDT 24
Peak memory 191376 kb
Host smart-8c129a33-c732-489c-b832-b174284313fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288812868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.2288812868
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.1692717727
Short name T305
Test name
Test status
Simulation time 275907681770 ps
CPU time 577.3 seconds
Started Jul 29 04:24:31 PM PDT 24
Finished Jul 29 04:34:09 PM PDT 24
Peak memory 191780 kb
Host smart-37c7a2ed-973d-46c1-9bea-f91c80c93b5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692717727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.1692717727
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.3260937316
Short name T137
Test name
Test status
Simulation time 436276280744 ps
CPU time 225.49 seconds
Started Jul 29 04:26:35 PM PDT 24
Finished Jul 29 04:30:21 PM PDT 24
Peak memory 191136 kb
Host smart-c04b3b07-9d69-4399-951d-3bce8f2057c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260937316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.3260937316
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.679040510
Short name T221
Test name
Test status
Simulation time 429240637653 ps
CPU time 770.15 seconds
Started Jul 29 04:22:05 PM PDT 24
Finished Jul 29 04:34:56 PM PDT 24
Peak memory 191572 kb
Host smart-ff430e1e-01c8-41c0-9cf5-1402344fc077
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679040510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all.
679040510
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_random.2601328906
Short name T231
Test name
Test status
Simulation time 638414959318 ps
CPU time 622.52 seconds
Started Jul 29 04:25:12 PM PDT 24
Finished Jul 29 04:35:35 PM PDT 24
Peak memory 191384 kb
Host smart-b244bf59-4905-489f-8363-6c52016da8bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601328906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.2601328906
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.4244268945
Short name T3
Test name
Test status
Simulation time 344786121341 ps
CPU time 541.75 seconds
Started Jul 29 04:21:57 PM PDT 24
Finished Jul 29 04:30:59 PM PDT 24
Peak memory 183224 kb
Host smart-2028ecd9-a745-4dda-8f41-2585a7c410a4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244268945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.4244268945
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.4190208105
Short name T171
Test name
Test status
Simulation time 347392164080 ps
CPU time 123.75 seconds
Started Jul 29 04:25:02 PM PDT 24
Finished Jul 29 04:27:05 PM PDT 24
Peak memory 191464 kb
Host smart-49155027-8446-4dd3-b47d-95b98e1a7aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190208105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.4190208105
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.795878449
Short name T350
Test name
Test status
Simulation time 43658722654 ps
CPU time 68.69 seconds
Started Jul 29 04:24:55 PM PDT 24
Finished Jul 29 04:26:05 PM PDT 24
Peak memory 181916 kb
Host smart-c1cde4be-31e7-4583-b1e3-4f3f4185ffc4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795878449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.rv_timer_cfg_update_on_fly.795878449
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/81.rv_timer_random.3447765758
Short name T143
Test name
Test status
Simulation time 58423935939 ps
CPU time 87.98 seconds
Started Jul 29 04:26:19 PM PDT 24
Finished Jul 29 04:27:47 PM PDT 24
Peak memory 194676 kb
Host smart-a080fdcb-fe43-4a2b-99f5-bbc8a97c0aed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447765758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.3447765758
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.3892215262
Short name T100
Test name
Test status
Simulation time 174082889232 ps
CPU time 147.92 seconds
Started Jul 29 04:24:49 PM PDT 24
Finished Jul 29 04:27:17 PM PDT 24
Peak memory 191464 kb
Host smart-09736ac4-368b-40e0-8192-f84fe6885601
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892215262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.3892215262
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.1225846260
Short name T169
Test name
Test status
Simulation time 263087615033 ps
CPU time 439.66 seconds
Started Jul 29 04:25:28 PM PDT 24
Finished Jul 29 04:32:48 PM PDT 24
Peak memory 191440 kb
Host smart-eeb04086-6a11-426b-8c7f-b3f7ffd8e5dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225846260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.1225846260
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.928623608
Short name T195
Test name
Test status
Simulation time 285411980778 ps
CPU time 454.74 seconds
Started Jul 29 04:25:37 PM PDT 24
Finished Jul 29 04:33:12 PM PDT 24
Peak memory 182864 kb
Host smart-de320b0e-3b49-488e-8183-95031e5c0cd5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928623608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.rv_timer_cfg_update_on_fly.928623608
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/177.rv_timer_random.64381032
Short name T205
Test name
Test status
Simulation time 354990798333 ps
CPU time 344.65 seconds
Started Jul 29 04:26:56 PM PDT 24
Finished Jul 29 04:32:40 PM PDT 24
Peak memory 191068 kb
Host smart-d42d2ecf-7f9d-4af1-b61c-cb4f7875be83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64381032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.64381032
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.3195460377
Short name T94
Test name
Test status
Simulation time 146511599784 ps
CPU time 496.29 seconds
Started Jul 29 04:25:47 PM PDT 24
Finished Jul 29 04:34:04 PM PDT 24
Peak memory 191412 kb
Host smart-2fc9e768-fac2-49ff-ba0f-32d67a027fbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195460377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.3195460377
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.3481610981
Short name T136
Test name
Test status
Simulation time 580471711067 ps
CPU time 555.1 seconds
Started Jul 29 04:25:45 PM PDT 24
Finished Jul 29 04:35:00 PM PDT 24
Peak memory 194932 kb
Host smart-26692093-b190-4ee8-9604-848799d6b920
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481610981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.3481610981
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.607432257
Short name T251
Test name
Test status
Simulation time 512489365370 ps
CPU time 306.54 seconds
Started Jul 29 04:25:25 PM PDT 24
Finished Jul 29 04:30:32 PM PDT 24
Peak memory 191480 kb
Host smart-cc9257c1-fb9c-4b5e-8629-6a77f61b19fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607432257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.607432257
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.1125975328
Short name T223
Test name
Test status
Simulation time 243529844612 ps
CPU time 1328.26 seconds
Started Jul 29 04:26:11 PM PDT 24
Finished Jul 29 04:48:19 PM PDT 24
Peak memory 191424 kb
Host smart-9b898dd5-7668-4cd9-8322-4fa1f9f2cc4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125975328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.1125975328
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.228572492
Short name T254
Test name
Test status
Simulation time 233950011779 ps
CPU time 97.47 seconds
Started Jul 29 04:24:26 PM PDT 24
Finished Jul 29 04:26:04 PM PDT 24
Peak memory 191488 kb
Host smart-2ab436fc-71d5-4272-a284-027b48618af5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228572492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.228572492
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.4213222575
Short name T112
Test name
Test status
Simulation time 80351863972 ps
CPU time 132.63 seconds
Started Jul 29 04:25:56 PM PDT 24
Finished Jul 29 04:28:08 PM PDT 24
Peak memory 191212 kb
Host smart-fe9000e5-0839-47a9-845e-85f4ddac10cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213222575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.4213222575
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.829835791
Short name T63
Test name
Test status
Simulation time 160046049 ps
CPU time 0.66 seconds
Started Jul 29 04:19:36 PM PDT 24
Finished Jul 29 04:19:38 PM PDT 24
Peak memory 181824 kb
Host smart-a83e9e0f-e7d7-43a0-bfc0-2b8f1af38adf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829835791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_re
set.829835791
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.2286183487
Short name T74
Test name
Test status
Simulation time 18643983 ps
CPU time 0.78 seconds
Started Jul 29 04:19:28 PM PDT 24
Finished Jul 29 04:19:29 PM PDT 24
Peak memory 193116 kb
Host smart-de47cf00-0412-444e-8646-e2160ab601a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286183487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.2286183487
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.467402895
Short name T324
Test name
Test status
Simulation time 52047788516 ps
CPU time 74.84 seconds
Started Jul 29 04:20:24 PM PDT 24
Finished Jul 29 04:21:39 PM PDT 24
Peak memory 183196 kb
Host smart-b4abbc33-ac16-41c5-ac0b-5f7733f82f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467402895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.467402895
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/112.rv_timer_random.1266230461
Short name T278
Test name
Test status
Simulation time 168654576118 ps
CPU time 255.49 seconds
Started Jul 29 04:24:55 PM PDT 24
Finished Jul 29 04:29:10 PM PDT 24
Peak memory 191468 kb
Host smart-32d19af8-1505-4ea3-bfb7-b60d87b3e2f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266230461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.1266230461
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.2897772005
Short name T190
Test name
Test status
Simulation time 76297162091 ps
CPU time 123.44 seconds
Started Jul 29 04:24:55 PM PDT 24
Finished Jul 29 04:26:58 PM PDT 24
Peak memory 191788 kb
Host smart-08f8f65e-d7a0-4c64-9de1-7643ba3ff19e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897772005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.2897772005
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.1702052253
Short name T360
Test name
Test status
Simulation time 27690747181 ps
CPU time 183.74 seconds
Started Jul 29 04:24:58 PM PDT 24
Finished Jul 29 04:28:01 PM PDT 24
Peak memory 191424 kb
Host smart-891708d7-a30b-4954-821f-4d8bd15465db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702052253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.1702052253
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.702124691
Short name T284
Test name
Test status
Simulation time 372332860955 ps
CPU time 572.67 seconds
Started Jul 29 04:25:22 PM PDT 24
Finished Jul 29 04:34:55 PM PDT 24
Peak memory 191448 kb
Host smart-504728f4-b507-4d47-b31c-cd0a9f579466
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702124691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.702124691
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.3831737757
Short name T197
Test name
Test status
Simulation time 680846917142 ps
CPU time 462.43 seconds
Started Jul 29 04:26:50 PM PDT 24
Finished Jul 29 04:34:33 PM PDT 24
Peak memory 191144 kb
Host smart-10207e4c-318c-45c6-84d9-d491472c8819
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831737757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.3831737757
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/150.rv_timer_random.193942674
Short name T121
Test name
Test status
Simulation time 82062046833 ps
CPU time 266.29 seconds
Started Jul 29 04:25:33 PM PDT 24
Finished Jul 29 04:29:59 PM PDT 24
Peak memory 191464 kb
Host smart-ab0bf6fd-a59f-40f2-b43b-7a625d4cb6d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193942674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.193942674
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.4229430723
Short name T151
Test name
Test status
Simulation time 155695798419 ps
CPU time 385.16 seconds
Started Jul 29 04:26:50 PM PDT 24
Finished Jul 29 04:33:16 PM PDT 24
Peak memory 191144 kb
Host smart-92b378ea-6bbe-4e2a-a04f-4c5a725eb20b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229430723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.4229430723
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.1409694820
Short name T217
Test name
Test status
Simulation time 271753623170 ps
CPU time 317.97 seconds
Started Jul 29 04:25:44 PM PDT 24
Finished Jul 29 04:31:02 PM PDT 24
Peak memory 191184 kb
Host smart-7b24653c-37e0-4d73-a937-e331d36a2b83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409694820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.1409694820
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random.1597215450
Short name T153
Test name
Test status
Simulation time 161964464995 ps
CPU time 989.3 seconds
Started Jul 29 04:25:26 PM PDT 24
Finished Jul 29 04:41:55 PM PDT 24
Peak memory 191448 kb
Host smart-9e26f45c-121e-45cb-bb97-c870aac707f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597215450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.1597215450
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.1338584788
Short name T347
Test name
Test status
Simulation time 60452698568 ps
CPU time 98.25 seconds
Started Jul 29 04:25:34 PM PDT 24
Finished Jul 29 04:27:13 PM PDT 24
Peak memory 191416 kb
Host smart-a2f99ce2-341b-40ed-98ba-31ad43f40ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338584788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.1338584788
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.1966633815
Short name T310
Test name
Test status
Simulation time 11669124426 ps
CPU time 22.19 seconds
Started Jul 29 04:23:55 PM PDT 24
Finished Jul 29 04:24:17 PM PDT 24
Peak memory 191828 kb
Host smart-ea9700d6-add8-47be-8956-ee9750bdcb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966633815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.1966633815
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_random.2341290660
Short name T272
Test name
Test status
Simulation time 343676663409 ps
CPU time 831.18 seconds
Started Jul 29 04:21:58 PM PDT 24
Finished Jul 29 04:35:49 PM PDT 24
Peak memory 191780 kb
Host smart-167b225c-d246-4aeb-84d6-c892ac6ef047
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341290660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.2341290660
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.2068847666
Short name T316
Test name
Test status
Simulation time 669994916269 ps
CPU time 249.73 seconds
Started Jul 29 04:25:56 PM PDT 24
Finished Jul 29 04:30:06 PM PDT 24
Peak memory 183036 kb
Host smart-665c87b8-1249-42cc-a08e-10b32b82fa07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068847666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.2068847666
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.1379964784
Short name T273
Test name
Test status
Simulation time 848876875093 ps
CPU time 301.29 seconds
Started Jul 29 04:23:02 PM PDT 24
Finished Jul 29 04:28:03 PM PDT 24
Peak memory 183204 kb
Host smart-8e2ef8f6-fd52-4d04-9c60-b427714ac175
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379964784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.1379964784
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.1046836249
Short name T166
Test name
Test status
Simulation time 361584925086 ps
CPU time 1065.03 seconds
Started Jul 29 04:24:58 PM PDT 24
Finished Jul 29 04:42:44 PM PDT 24
Peak memory 189796 kb
Host smart-c8f7d4ac-1742-48e2-9a60-e6fa7154ce4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046836249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.1046836249
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_random.4088541600
Short name T114
Test name
Test status
Simulation time 302019896450 ps
CPU time 141.36 seconds
Started Jul 29 04:25:05 PM PDT 24
Finished Jul 29 04:27:27 PM PDT 24
Peak memory 191388 kb
Host smart-30f7e414-1d45-445d-ae5b-9ec42cb3708e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088541600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.4088541600
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.201250910
Short name T162
Test name
Test status
Simulation time 416373504253 ps
CPU time 660.46 seconds
Started Jul 29 04:25:39 PM PDT 24
Finished Jul 29 04:36:40 PM PDT 24
Peak memory 191400 kb
Host smart-a488156d-995b-43b0-943a-e6fe1f3a0586
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201250910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.201250910
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.2055358690
Short name T303
Test name
Test status
Simulation time 83123830019 ps
CPU time 68.6 seconds
Started Jul 29 04:25:31 PM PDT 24
Finished Jul 29 04:26:40 PM PDT 24
Peak memory 183248 kb
Host smart-f34aeeba-88ca-4706-970c-6da9884fbc3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055358690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.2055358690
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.1737073613
Short name T88
Test name
Test status
Simulation time 73880746 ps
CPU time 1.1 seconds
Started Jul 29 04:20:24 PM PDT 24
Finished Jul 29 04:20:26 PM PDT 24
Peak memory 182772 kb
Host smart-8ec1bf12-3434-4d4e-8c6e-c7bbdaf50fb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737073613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.1737073613
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.2625402734
Short name T11
Test name
Test status
Simulation time 488804787391 ps
CPU time 721.52 seconds
Started Jul 29 04:19:35 PM PDT 24
Finished Jul 29 04:31:37 PM PDT 24
Peak memory 189636 kb
Host smart-04597fdd-8f8e-42b6-8e89-b68e6c116a29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625402734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
2625402734
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.769987427
Short name T101
Test name
Test status
Simulation time 1803447804609 ps
CPU time 429.2 seconds
Started Jul 29 04:19:35 PM PDT 24
Finished Jul 29 04:26:45 PM PDT 24
Peak memory 181504 kb
Host smart-9282aa7a-599f-4908-8b3c-cf3069dafc00
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769987427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.rv_timer_cfg_update_on_fly.769987427
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_random.4102797287
Short name T178
Test name
Test status
Simulation time 101169992243 ps
CPU time 83.37 seconds
Started Jul 29 04:20:37 PM PDT 24
Finished Jul 29 04:22:01 PM PDT 24
Peak memory 191104 kb
Host smart-1d50cca7-a29f-4094-8568-0521f408045e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102797287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.4102797287
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.3604968902
Short name T331
Test name
Test status
Simulation time 975496170347 ps
CPU time 281.6 seconds
Started Jul 29 04:24:33 PM PDT 24
Finished Jul 29 04:29:15 PM PDT 24
Peak memory 191584 kb
Host smart-50116e9e-431e-4d6f-9493-1fb778ebd782
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604968902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.3604968902
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.1860570060
Short name T222
Test name
Test status
Simulation time 70661336380 ps
CPU time 120.98 seconds
Started Jul 29 04:24:36 PM PDT 24
Finished Jul 29 04:26:37 PM PDT 24
Peak memory 191488 kb
Host smart-a9c69b78-3a8b-4944-8933-1f91c8cf7162
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860570060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.1860570060
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.1148715327
Short name T209
Test name
Test status
Simulation time 225155105535 ps
CPU time 552.4 seconds
Started Jul 29 04:22:05 PM PDT 24
Finished Jul 29 04:31:18 PM PDT 24
Peak memory 191568 kb
Host smart-1eb95641-dca5-49f0-abaf-c89d2f5130d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148715327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.1148715327
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/122.rv_timer_random.2728648242
Short name T108
Test name
Test status
Simulation time 121762774478 ps
CPU time 512.68 seconds
Started Jul 29 04:25:02 PM PDT 24
Finished Jul 29 04:33:35 PM PDT 24
Peak memory 191496 kb
Host smart-6a7a375c-ca62-47a3-874b-8b07899e04ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728648242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.2728648242
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.451205211
Short name T158
Test name
Test status
Simulation time 620857175791 ps
CPU time 1056.85 seconds
Started Jul 29 04:24:59 PM PDT 24
Finished Jul 29 04:42:36 PM PDT 24
Peak memory 191584 kb
Host smart-fd916ebf-f8ce-43ff-9040-8226e070e630
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451205211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.451205211
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.1732320236
Short name T262
Test name
Test status
Simulation time 479881019986 ps
CPU time 399.01 seconds
Started Jul 29 04:25:14 PM PDT 24
Finished Jul 29 04:31:53 PM PDT 24
Peak memory 183204 kb
Host smart-8e63a434-45d2-421a-91f6-fdb4317da18d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732320236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.1732320236
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/133.rv_timer_random.3554815910
Short name T346
Test name
Test status
Simulation time 273511673033 ps
CPU time 103.25 seconds
Started Jul 29 04:26:36 PM PDT 24
Finished Jul 29 04:28:20 PM PDT 24
Peak memory 191136 kb
Host smart-9deceefd-2af6-4e3a-9a90-406cce2d3c1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554815910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.3554815910
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.2808790503
Short name T299
Test name
Test status
Simulation time 222989093910 ps
CPU time 245.53 seconds
Started Jul 29 04:26:35 PM PDT 24
Finished Jul 29 04:30:42 PM PDT 24
Peak memory 190572 kb
Host smart-a4bae4ad-cf76-4e40-ba53-b37ea6a46403
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808790503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.2808790503
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.533550030
Short name T288
Test name
Test status
Simulation time 3753432397 ps
CPU time 3.29 seconds
Started Jul 29 04:25:36 PM PDT 24
Finished Jul 29 04:25:39 PM PDT 24
Peak memory 183076 kb
Host smart-a7927b5b-bbfb-43a5-9727-e7166e4710f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533550030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.533550030
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.321049810
Short name T233
Test name
Test status
Simulation time 92289748294 ps
CPU time 390.72 seconds
Started Jul 29 04:25:39 PM PDT 24
Finished Jul 29 04:32:10 PM PDT 24
Peak memory 191384 kb
Host smart-72b5180f-cdd6-4a75-a6e3-17aed39131c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321049810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.321049810
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.4191495618
Short name T358
Test name
Test status
Simulation time 363765647036 ps
CPU time 686.66 seconds
Started Jul 29 04:25:39 PM PDT 24
Finished Jul 29 04:37:05 PM PDT 24
Peak memory 191780 kb
Host smart-7f5b15c6-8bd6-423c-a069-d48b14608f6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191495618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.4191495618
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.702291703
Short name T311
Test name
Test status
Simulation time 114856835593 ps
CPU time 98.85 seconds
Started Jul 29 04:24:56 PM PDT 24
Finished Jul 29 04:26:35 PM PDT 24
Peak memory 182240 kb
Host smart-7162cba7-194f-4727-b41e-d919ef6b8f25
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702291703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.rv_timer_cfg_update_on_fly.702291703
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/180.rv_timer_random.2551871008
Short name T128
Test name
Test status
Simulation time 563451986596 ps
CPU time 415.24 seconds
Started Jul 29 04:26:50 PM PDT 24
Finished Jul 29 04:33:46 PM PDT 24
Peak memory 191120 kb
Host smart-102ca52e-68fb-4f77-9ec5-880190a02ca9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551871008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.2551871008
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.2493166403
Short name T83
Test name
Test status
Simulation time 141710421 ps
CPU time 0.87 seconds
Started Jul 29 04:25:11 PM PDT 24
Finished Jul 29 04:25:13 PM PDT 24
Peak memory 180896 kb
Host smart-459bc395-92fe-4e00-8fec-90e27c133402
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493166403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.2493166403
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/191.rv_timer_random.116630394
Short name T256
Test name
Test status
Simulation time 64440271196 ps
CPU time 89.04 seconds
Started Jul 29 04:25:54 PM PDT 24
Finished Jul 29 04:27:23 PM PDT 24
Peak memory 194580 kb
Host smart-bfe7adc1-0fb0-47b7-b233-d46f12ae05ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116630394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.116630394
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.1603078991
Short name T91
Test name
Test status
Simulation time 171563224201 ps
CPU time 283.62 seconds
Started Jul 29 04:25:54 PM PDT 24
Finished Jul 29 04:30:38 PM PDT 24
Peak memory 191408 kb
Host smart-71d54c45-494f-4d7e-8881-abcd5a08e1fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603078991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.1603078991
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random.1433791455
Short name T353
Test name
Test status
Simulation time 52370292136 ps
CPU time 26.44 seconds
Started Jul 29 04:25:31 PM PDT 24
Finished Jul 29 04:25:58 PM PDT 24
Peak memory 183252 kb
Host smart-beb48bd7-29df-43ce-84fb-911a9244c74c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433791455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.1433791455
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random.352187200
Short name T357
Test name
Test status
Simulation time 530012167481 ps
CPU time 563.79 seconds
Started Jul 29 04:21:46 PM PDT 24
Finished Jul 29 04:31:10 PM PDT 24
Peak memory 191488 kb
Host smart-c3c8cf7a-6f4d-4808-b2cb-481874af7d34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352187200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.352187200
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random.1845028092
Short name T348
Test name
Test status
Simulation time 68763431227 ps
CPU time 112.42 seconds
Started Jul 29 04:21:21 PM PDT 24
Finished Jul 29 04:23:14 PM PDT 24
Peak memory 183232 kb
Host smart-250e52d8-539b-4859-a250-caf1c8f10cd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845028092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.1845028092
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.2964816486
Short name T349
Test name
Test status
Simulation time 56076217648 ps
CPU time 97.21 seconds
Started Jul 29 04:21:57 PM PDT 24
Finished Jul 29 04:23:34 PM PDT 24
Peak memory 191828 kb
Host smart-0974198b-937b-4ea2-881a-1efedb7027ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964816486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.2964816486
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.1581310111
Short name T267
Test name
Test status
Simulation time 641248397157 ps
CPU time 823.56 seconds
Started Jul 29 04:22:12 PM PDT 24
Finished Jul 29 04:35:55 PM PDT 24
Peak memory 196424 kb
Host smart-de432252-05d4-4e56-ae60-bb224ea16e9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581310111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.1581310111
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.696338037
Short name T135
Test name
Test status
Simulation time 6488221833455 ps
CPU time 1466.13 seconds
Started Jul 29 04:22:49 PM PDT 24
Finished Jul 29 04:47:15 PM PDT 24
Peak memory 191432 kb
Host smart-83471d80-d635-4a88-9144-7683605e01e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696338037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all.
696338037
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.2039312767
Short name T154
Test name
Test status
Simulation time 127473255305 ps
CPU time 109.16 seconds
Started Jul 29 04:25:34 PM PDT 24
Finished Jul 29 04:27:24 PM PDT 24
Peak memory 182140 kb
Host smart-1793257a-d152-466e-8bca-94e1e2f71e9e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039312767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.2039312767
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.1144361980
Short name T39
Test name
Test status
Simulation time 42496343872 ps
CPU time 195.35 seconds
Started Jul 29 04:23:28 PM PDT 24
Finished Jul 29 04:26:43 PM PDT 24
Peak memory 198072 kb
Host smart-c903b745-fcdd-4182-9c56-9dca6afa2804
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144361980 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all_with_rand_reset.1144361980
Directory /workspace/45.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.rv_timer_random.2943571597
Short name T293
Test name
Test status
Simulation time 59626969852 ps
CPU time 84.04 seconds
Started Jul 29 04:25:20 PM PDT 24
Finished Jul 29 04:26:45 PM PDT 24
Peak memory 190620 kb
Host smart-ad6c0333-5710-426e-8768-615af52fa25e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943571597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.2943571597
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.4029200365
Short name T106
Test name
Test status
Simulation time 235969871375 ps
CPU time 472.35 seconds
Started Jul 29 04:24:28 PM PDT 24
Finished Jul 29 04:32:21 PM PDT 24
Peak memory 191448 kb
Host smart-9c7b8771-21cf-4f4c-82a2-56082e945718
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029200365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.4029200365
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3012507256
Short name T505
Test name
Test status
Simulation time 42683570 ps
CPU time 0.7 seconds
Started Jul 29 04:19:36 PM PDT 24
Finished Jul 29 04:19:38 PM PDT 24
Peak memory 180288 kb
Host smart-bdea2f7c-6c42-4e19-b2c3-bc9e6e0e7ff5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012507256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.3012507256
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.2093981997
Short name T511
Test name
Test status
Simulation time 3703485784 ps
CPU time 3.67 seconds
Started Jul 29 04:19:38 PM PDT 24
Finished Jul 29 04:19:42 PM PDT 24
Peak memory 191184 kb
Host smart-b0e02691-08a2-40c5-af1a-d58b0359563e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093981997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.2093981997
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.461542156
Short name T570
Test name
Test status
Simulation time 385003689 ps
CPU time 0.81 seconds
Started Jul 29 04:19:35 PM PDT 24
Finished Jul 29 04:19:36 PM PDT 24
Peak memory 196776 kb
Host smart-e101e103-d098-4301-b6a1-6558484d7e8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461542156 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.461542156
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.1146039223
Short name T510
Test name
Test status
Simulation time 49652450 ps
CPU time 0.59 seconds
Started Jul 29 04:20:09 PM PDT 24
Finished Jul 29 04:20:09 PM PDT 24
Peak memory 182652 kb
Host smart-4072696d-2f7f-4350-9439-7ffdca013590
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146039223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.1146039223
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.455933829
Short name T499
Test name
Test status
Simulation time 16084000 ps
CPU time 0.57 seconds
Started Jul 29 04:19:36 PM PDT 24
Finished Jul 29 04:19:38 PM PDT 24
Peak memory 182196 kb
Host smart-3c816693-4e23-4a30-b017-a29370d49b7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455933829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.455933829
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.3141982984
Short name T502
Test name
Test status
Simulation time 579411270 ps
CPU time 1.21 seconds
Started Jul 29 04:19:28 PM PDT 24
Finished Jul 29 04:19:29 PM PDT 24
Peak memory 196412 kb
Host smart-d6a582f6-20da-43a7-bc21-f888c3b471a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141982984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.3141982984
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.2671179607
Short name T536
Test name
Test status
Simulation time 496508016 ps
CPU time 1.31 seconds
Started Jul 29 04:19:36 PM PDT 24
Finished Jul 29 04:19:38 PM PDT 24
Peak memory 194128 kb
Host smart-ba49aca7-a09c-4a37-9268-b55d6c18fb27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671179607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.2671179607
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.4154426787
Short name T461
Test name
Test status
Simulation time 29874799 ps
CPU time 0.8 seconds
Started Jul 29 04:20:37 PM PDT 24
Finished Jul 29 04:20:38 PM PDT 24
Peak memory 191584 kb
Host smart-c1035fbe-d1c0-452c-9a98-79c83e4f6197
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154426787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.4154426787
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.815602647
Short name T546
Test name
Test status
Simulation time 1454403283 ps
CPU time 2.5 seconds
Started Jul 29 04:19:35 PM PDT 24
Finished Jul 29 04:19:38 PM PDT 24
Peak memory 190004 kb
Host smart-bd7c8de5-190e-4978-96f7-7eff21635e4d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815602647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_b
ash.815602647
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.3477301923
Short name T558
Test name
Test status
Simulation time 14691444 ps
CPU time 0.55 seconds
Started Jul 29 04:20:50 PM PDT 24
Finished Jul 29 04:20:51 PM PDT 24
Peak memory 182700 kb
Host smart-a5945018-70d2-4eff-a61d-7d3018a96c22
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477301923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.3477301923
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.1672307944
Short name T456
Test name
Test status
Simulation time 27179570 ps
CPU time 0.8 seconds
Started Jul 29 04:19:36 PM PDT 24
Finished Jul 29 04:19:37 PM PDT 24
Peak memory 196916 kb
Host smart-68455120-350c-42f5-9db3-1b30bdedd6a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672307944 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.1672307944
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.231896168
Short name T556
Test name
Test status
Simulation time 15241124 ps
CPU time 0.61 seconds
Started Jul 29 04:19:35 PM PDT 24
Finished Jul 29 04:19:36 PM PDT 24
Peak memory 181472 kb
Host smart-d290cdb2-5fbf-41a7-b276-801c139e77af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231896168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.231896168
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.3686460582
Short name T576
Test name
Test status
Simulation time 26504481 ps
CPU time 0.72 seconds
Started Jul 29 04:20:36 PM PDT 24
Finished Jul 29 04:20:38 PM PDT 24
Peak memory 189636 kb
Host smart-0bb830b4-5413-4e28-95de-793705af6d72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686460582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.3686460582
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.1686174742
Short name T527
Test name
Test status
Simulation time 193627267 ps
CPU time 2.14 seconds
Started Jul 29 04:19:31 PM PDT 24
Finished Jul 29 04:19:33 PM PDT 24
Peak memory 197412 kb
Host smart-2c136941-771e-4caf-adc3-fdbed6acdeca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686174742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.1686174742
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.2993185219
Short name T513
Test name
Test status
Simulation time 674946402 ps
CPU time 0.88 seconds
Started Jul 29 04:19:36 PM PDT 24
Finished Jul 29 04:19:38 PM PDT 24
Peak memory 190900 kb
Host smart-cd89c72c-708c-4ab1-ad5e-847dc93b7375
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993185219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.2993185219
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.1584687299
Short name T458
Test name
Test status
Simulation time 35969304 ps
CPU time 0.91 seconds
Started Jul 29 04:25:30 PM PDT 24
Finished Jul 29 04:25:31 PM PDT 24
Peak memory 196504 kb
Host smart-95acdae1-f9da-4183-bb26-1300e0dfb7d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584687299 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.1584687299
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.3688421139
Short name T73
Test name
Test status
Simulation time 26739641 ps
CPU time 0.54 seconds
Started Jul 29 04:25:38 PM PDT 24
Finished Jul 29 04:25:39 PM PDT 24
Peak memory 182708 kb
Host smart-65503ba2-9518-462f-b140-4597e2309cec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688421139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.3688421139
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.3773690336
Short name T482
Test name
Test status
Simulation time 47911020 ps
CPU time 0.57 seconds
Started Jul 29 04:25:13 PM PDT 24
Finished Jul 29 04:25:14 PM PDT 24
Peak memory 182496 kb
Host smart-9777f77d-6bfd-468a-85e9-3194f6c82ea8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773690336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.3773690336
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.1172892794
Short name T519
Test name
Test status
Simulation time 36871120 ps
CPU time 0.78 seconds
Started Jul 29 04:20:23 PM PDT 24
Finished Jul 29 04:20:24 PM PDT 24
Peak memory 192024 kb
Host smart-8478c5be-5e29-4638-a16e-d68fb6ca7215
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172892794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.1172892794
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.2293413164
Short name T516
Test name
Test status
Simulation time 218980968 ps
CPU time 1.21 seconds
Started Jul 29 04:25:04 PM PDT 24
Finished Jul 29 04:25:05 PM PDT 24
Peak memory 196944 kb
Host smart-2d10caec-5f5d-4bf7-a507-327db1f9de70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293413164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.2293413164
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.3335263585
Short name T512
Test name
Test status
Simulation time 208512791 ps
CPU time 1.38 seconds
Started Jul 29 04:25:40 PM PDT 24
Finished Jul 29 04:25:41 PM PDT 24
Peak memory 195404 kb
Host smart-204a0035-6671-4af2-8666-6e9845ead73d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335263585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.3335263585
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.4266537162
Short name T542
Test name
Test status
Simulation time 32163338 ps
CPU time 0.83 seconds
Started Jul 29 04:20:24 PM PDT 24
Finished Jul 29 04:20:25 PM PDT 24
Peak memory 194656 kb
Host smart-324a61c5-5b39-44c8-8db6-e4d260660b8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266537162 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.4266537162
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.257039287
Short name T87
Test name
Test status
Simulation time 11710471 ps
CPU time 0.58 seconds
Started Jul 29 04:20:15 PM PDT 24
Finished Jul 29 04:20:16 PM PDT 24
Peak memory 182636 kb
Host smart-a4ce1d64-8da6-4845-a432-11977d27f45d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257039287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.257039287
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.646276591
Short name T475
Test name
Test status
Simulation time 17092262 ps
CPU time 0.54 seconds
Started Jul 29 04:25:13 PM PDT 24
Finished Jul 29 04:25:14 PM PDT 24
Peak memory 182508 kb
Host smart-f6ffdd68-2200-45d7-9f55-a996ce263931
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646276591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.646276591
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3594678079
Short name T52
Test name
Test status
Simulation time 65137229 ps
CPU time 0.63 seconds
Started Jul 29 04:25:25 PM PDT 24
Finished Jul 29 04:25:26 PM PDT 24
Peak memory 191624 kb
Host smart-b3e44899-0a19-442a-84e5-e587988f3bef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594678079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.3594678079
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.1699580347
Short name T553
Test name
Test status
Simulation time 729343312 ps
CPU time 1.89 seconds
Started Jul 29 04:20:21 PM PDT 24
Finished Jul 29 04:20:23 PM PDT 24
Peak memory 197516 kb
Host smart-ad18ffa5-5b85-4839-a296-df0560bbd8d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699580347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.1699580347
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.2400076082
Short name T489
Test name
Test status
Simulation time 47454127 ps
CPU time 0.66 seconds
Started Jul 29 04:25:32 PM PDT 24
Finished Jul 29 04:25:33 PM PDT 24
Peak memory 193620 kb
Host smart-3dbbba40-ebe4-40a6-8f32-d3c44ce1b928
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400076082 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.2400076082
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1890964302
Short name T68
Test name
Test status
Simulation time 14041957 ps
CPU time 0.58 seconds
Started Jul 29 04:25:32 PM PDT 24
Finished Jul 29 04:25:33 PM PDT 24
Peak memory 182520 kb
Host smart-5070595a-a603-47f1-8efd-7aba59aec907
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890964302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.1890964302
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.4054178645
Short name T509
Test name
Test status
Simulation time 17182379 ps
CPU time 0.57 seconds
Started Jul 29 04:21:10 PM PDT 24
Finished Jul 29 04:21:11 PM PDT 24
Peak memory 182356 kb
Host smart-44b7603b-426f-43e2-9b2e-7919225e6c4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054178645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.4054178645
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.4171396474
Short name T500
Test name
Test status
Simulation time 95265743 ps
CPU time 0.64 seconds
Started Jul 29 04:25:12 PM PDT 24
Finished Jul 29 04:25:13 PM PDT 24
Peak memory 191264 kb
Host smart-eab3a960-7682-4fbd-9d82-7943e4101e7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171396474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.4171396474
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.1873075866
Short name T504
Test name
Test status
Simulation time 42622029 ps
CPU time 2 seconds
Started Jul 29 04:25:30 PM PDT 24
Finished Jul 29 04:25:33 PM PDT 24
Peak memory 197424 kb
Host smart-f6ac2f91-8c0b-4960-80d8-b385cffd59b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873075866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.1873075866
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.2834913491
Short name T515
Test name
Test status
Simulation time 338560838 ps
CPU time 1.35 seconds
Started Jul 29 04:20:23 PM PDT 24
Finished Jul 29 04:20:25 PM PDT 24
Peak memory 195520 kb
Host smart-d1872bfe-8196-4fb8-8520-03f68d4246fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834913491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.2834913491
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.818085278
Short name T495
Test name
Test status
Simulation time 36886848 ps
CPU time 0.91 seconds
Started Jul 29 04:23:15 PM PDT 24
Finished Jul 29 04:23:16 PM PDT 24
Peak memory 197176 kb
Host smart-cb508eca-616c-4f74-9abb-b534d6959301
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818085278 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.818085278
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.4113698294
Short name T523
Test name
Test status
Simulation time 15490118 ps
CPU time 0.52 seconds
Started Jul 29 04:25:31 PM PDT 24
Finished Jul 29 04:25:32 PM PDT 24
Peak memory 182508 kb
Host smart-9d2a23bb-e2bd-4ea0-af16-ea467ab49011
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113698294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.4113698294
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.2027563292
Short name T530
Test name
Test status
Simulation time 13535432 ps
CPU time 0.58 seconds
Started Jul 29 04:20:23 PM PDT 24
Finished Jul 29 04:20:23 PM PDT 24
Peak memory 182960 kb
Host smart-995c28db-9d57-4b39-8783-1646aaf051ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027563292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.2027563292
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1694698288
Short name T494
Test name
Test status
Simulation time 239993705 ps
CPU time 0.7 seconds
Started Jul 29 04:25:32 PM PDT 24
Finished Jul 29 04:25:33 PM PDT 24
Peak memory 193036 kb
Host smart-79fcd0a9-0f73-4fe6-a3dc-82c807970069
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694698288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.1694698288
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.3434214336
Short name T517
Test name
Test status
Simulation time 380625057 ps
CPU time 1.52 seconds
Started Jul 29 04:20:18 PM PDT 24
Finished Jul 29 04:20:20 PM PDT 24
Peak memory 197404 kb
Host smart-7e155964-a488-478c-b03d-89feebf94a89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434214336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.3434214336
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.2736845800
Short name T563
Test name
Test status
Simulation time 121923134 ps
CPU time 1.18 seconds
Started Jul 29 04:20:23 PM PDT 24
Finished Jul 29 04:20:24 PM PDT 24
Peak memory 194584 kb
Host smart-41ab68f8-dd0e-4508-9af5-1555c2b36af5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736845800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.2736845800
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.2830875035
Short name T481
Test name
Test status
Simulation time 30911544 ps
CPU time 1.23 seconds
Started Jul 29 04:25:42 PM PDT 24
Finished Jul 29 04:25:44 PM PDT 24
Peak memory 197468 kb
Host smart-40065315-2034-428b-95aa-a16611b5a455
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830875035 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.2830875035
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.4002083101
Short name T483
Test name
Test status
Simulation time 12065560 ps
CPU time 0.55 seconds
Started Jul 29 04:20:21 PM PDT 24
Finished Jul 29 04:20:22 PM PDT 24
Peak memory 182388 kb
Host smart-868bfdf5-dcf2-424a-9b37-ced8da4850fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002083101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.4002083101
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.611124488
Short name T464
Test name
Test status
Simulation time 174903664 ps
CPU time 0.51 seconds
Started Jul 29 04:25:18 PM PDT 24
Finished Jul 29 04:25:19 PM PDT 24
Peak memory 181976 kb
Host smart-ee606bd5-3949-4230-81ee-3b49e83a046d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611124488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.611124488
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.1343386664
Short name T47
Test name
Test status
Simulation time 21008978 ps
CPU time 0.63 seconds
Started Jul 29 04:21:09 PM PDT 24
Finished Jul 29 04:21:10 PM PDT 24
Peak memory 192000 kb
Host smart-5299d3ed-b6d8-4dee-a33f-50b158b317ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343386664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.1343386664
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.562273254
Short name T544
Test name
Test status
Simulation time 358468949 ps
CPU time 2.7 seconds
Started Jul 29 04:25:31 PM PDT 24
Finished Jul 29 04:25:34 PM PDT 24
Peak memory 197156 kb
Host smart-2eb8d126-5b6b-41da-8b79-2a0e64c44680
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562273254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.562273254
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.2874463973
Short name T29
Test name
Test status
Simulation time 303445258 ps
CPU time 1.06 seconds
Started Jul 29 04:21:49 PM PDT 24
Finished Jul 29 04:21:50 PM PDT 24
Peak memory 194856 kb
Host smart-9ab8777f-573b-45ed-aa1e-238342838ff4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874463973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.2874463973
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.442006010
Short name T469
Test name
Test status
Simulation time 149819164 ps
CPU time 0.71 seconds
Started Jul 29 04:25:56 PM PDT 24
Finished Jul 29 04:25:57 PM PDT 24
Peak memory 195212 kb
Host smart-3087247d-f830-43bd-aea1-2ed2382970d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442006010 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.442006010
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.4079080741
Short name T86
Test name
Test status
Simulation time 15875714 ps
CPU time 0.57 seconds
Started Jul 29 04:26:06 PM PDT 24
Finished Jul 29 04:26:07 PM PDT 24
Peak memory 181968 kb
Host smart-75877366-2bad-4be4-8a19-8dcb57f501ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079080741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.4079080741
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.754145045
Short name T514
Test name
Test status
Simulation time 16239080 ps
CPU time 0.51 seconds
Started Jul 29 04:25:56 PM PDT 24
Finished Jul 29 04:25:57 PM PDT 24
Peak memory 181956 kb
Host smart-7bc7657b-1884-447b-a0aa-104cdbe93a64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754145045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.754145045
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.3012314823
Short name T560
Test name
Test status
Simulation time 64933742 ps
CPU time 0.76 seconds
Started Jul 29 04:26:23 PM PDT 24
Finished Jul 29 04:26:24 PM PDT 24
Peak memory 193492 kb
Host smart-3dcf18cd-e652-4cad-8c79-2fbe3488ffde
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012314823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.3012314823
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.3368252509
Short name T540
Test name
Test status
Simulation time 156824355 ps
CPU time 1.09 seconds
Started Jul 29 04:23:50 PM PDT 24
Finished Jul 29 04:23:51 PM PDT 24
Peak memory 195396 kb
Host smart-fccf5f9f-c4b3-4c81-8156-a2627054f949
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368252509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.3368252509
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.33000632
Short name T488
Test name
Test status
Simulation time 128561016 ps
CPU time 1.12 seconds
Started Jul 29 04:20:23 PM PDT 24
Finished Jul 29 04:20:24 PM PDT 24
Peak memory 195368 kb
Host smart-b8fceb74-cc2f-4f81-b82a-631273d8f183
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33000632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_int
g_err.33000632
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.3217686710
Short name T559
Test name
Test status
Simulation time 21254164 ps
CPU time 0.7 seconds
Started Jul 29 04:26:11 PM PDT 24
Finished Jul 29 04:26:11 PM PDT 24
Peak memory 194932 kb
Host smart-061f09f8-7d20-4730-8b17-a16aea222fd6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217686710 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.3217686710
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.4287882416
Short name T70
Test name
Test status
Simulation time 42609192 ps
CPU time 0.57 seconds
Started Jul 29 04:25:54 PM PDT 24
Finished Jul 29 04:25:55 PM PDT 24
Peak memory 181760 kb
Host smart-ffe48453-8aa6-4d20-a970-1a65f8971109
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287882416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.4287882416
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.142806987
Short name T579
Test name
Test status
Simulation time 18927573 ps
CPU time 0.56 seconds
Started Jul 29 04:21:32 PM PDT 24
Finished Jul 29 04:21:33 PM PDT 24
Peak memory 182540 kb
Host smart-2c406446-9525-4993-9849-085e3be52cfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142806987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.142806987
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.927029612
Short name T491
Test name
Test status
Simulation time 54396716 ps
CPU time 0.58 seconds
Started Jul 29 04:25:41 PM PDT 24
Finished Jul 29 04:25:41 PM PDT 24
Peak memory 191444 kb
Host smart-a10ddc6b-4ed2-4df6-9c97-e2bae91d65ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927029612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_ti
mer_same_csr_outstanding.927029612
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3568621095
Short name T550
Test name
Test status
Simulation time 870110488 ps
CPU time 2.38 seconds
Started Jul 29 04:25:27 PM PDT 24
Finished Jul 29 04:25:30 PM PDT 24
Peak memory 196732 kb
Host smart-cdb39784-7fe2-4b87-a65c-e80460358f2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568621095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.3568621095
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.709670712
Short name T472
Test name
Test status
Simulation time 737309608 ps
CPU time 1.29 seconds
Started Jul 29 04:25:07 PM PDT 24
Finished Jul 29 04:25:08 PM PDT 24
Peak memory 195316 kb
Host smart-940f37a6-d741-498b-9b34-c548bf49895c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709670712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_in
tg_err.709670712
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.1377302455
Short name T471
Test name
Test status
Simulation time 97174411 ps
CPU time 1 seconds
Started Jul 29 04:25:03 PM PDT 24
Finished Jul 29 04:25:05 PM PDT 24
Peak memory 196160 kb
Host smart-96cf7254-8317-4d34-a6af-af9f17d5f59d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377302455 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.1377302455
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.2167249926
Short name T66
Test name
Test status
Simulation time 12829047 ps
CPU time 0.55 seconds
Started Jul 29 04:20:29 PM PDT 24
Finished Jul 29 04:20:30 PM PDT 24
Peak memory 182072 kb
Host smart-00153650-2f74-429c-be4c-d20c3e19c708
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167249926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.2167249926
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3551468900
Short name T452
Test name
Test status
Simulation time 101287828 ps
CPU time 0.54 seconds
Started Jul 29 04:21:36 PM PDT 24
Finished Jul 29 04:21:37 PM PDT 24
Peak memory 182368 kb
Host smart-4ce34847-659f-4ba5-a823-e7a75f41fe6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551468900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.3551468900
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.266476347
Short name T554
Test name
Test status
Simulation time 47782260 ps
CPU time 0.7 seconds
Started Jul 29 04:20:33 PM PDT 24
Finished Jul 29 04:20:34 PM PDT 24
Peak memory 192084 kb
Host smart-5f4a453a-a126-4dfe-b05d-b182fbc26699
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266476347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_ti
mer_same_csr_outstanding.266476347
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.4215429303
Short name T538
Test name
Test status
Simulation time 47414115 ps
CPU time 1.15 seconds
Started Jul 29 04:26:10 PM PDT 24
Finished Jul 29 04:26:11 PM PDT 24
Peak memory 197424 kb
Host smart-93a12f17-76a0-4807-be1a-81ec6eb77278
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215429303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.4215429303
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3032381880
Short name T525
Test name
Test status
Simulation time 76585719 ps
CPU time 0.75 seconds
Started Jul 29 04:25:03 PM PDT 24
Finished Jul 29 04:25:04 PM PDT 24
Peak memory 193624 kb
Host smart-50a4de8c-00ff-4869-b1f0-ed3162b5eec5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032381880 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.3032381880
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.1692514159
Short name T480
Test name
Test status
Simulation time 75371992 ps
CPU time 0.56 seconds
Started Jul 29 04:20:26 PM PDT 24
Finished Jul 29 04:20:27 PM PDT 24
Peak memory 182740 kb
Host smart-5949df5e-ff44-4c72-8e44-62442814184f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692514159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.1692514159
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.1528369386
Short name T455
Test name
Test status
Simulation time 50417935 ps
CPU time 0.54 seconds
Started Jul 29 04:20:25 PM PDT 24
Finished Jul 29 04:20:26 PM PDT 24
Peak memory 182560 kb
Host smart-ab4fd26f-e9fc-4ca1-ae1d-27f3fd1ba914
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528369386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.1528369386
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1552264555
Short name T486
Test name
Test status
Simulation time 31963609 ps
CPU time 0.68 seconds
Started Jul 29 04:23:38 PM PDT 24
Finished Jul 29 04:23:39 PM PDT 24
Peak memory 192420 kb
Host smart-66a00ea3-4733-4510-9739-e1743ee76eb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552264555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.1552264555
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.1409747256
Short name T493
Test name
Test status
Simulation time 307736342 ps
CPU time 1.1 seconds
Started Jul 29 04:20:31 PM PDT 24
Finished Jul 29 04:20:32 PM PDT 24
Peak memory 197112 kb
Host smart-cd7e46e5-e4fc-413f-9747-f59003f3e883
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409747256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.1409747256
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1026784580
Short name T565
Test name
Test status
Simulation time 84328538 ps
CPU time 1.13 seconds
Started Jul 29 04:24:21 PM PDT 24
Finished Jul 29 04:24:22 PM PDT 24
Peak memory 195496 kb
Host smart-b6b88906-79da-4d9f-b20a-96950a7cc3b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026784580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.1026784580
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.761703330
Short name T462
Test name
Test status
Simulation time 105494210 ps
CPU time 0.7 seconds
Started Jul 29 04:20:32 PM PDT 24
Finished Jul 29 04:20:33 PM PDT 24
Peak memory 195628 kb
Host smart-a561886c-b1d4-4a86-bc83-0777ba99be17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761703330 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.761703330
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.1707701305
Short name T549
Test name
Test status
Simulation time 29751716 ps
CPU time 0.54 seconds
Started Jul 29 04:20:29 PM PDT 24
Finished Jul 29 04:20:30 PM PDT 24
Peak memory 182000 kb
Host smart-b3d3a7e6-f24f-4dc1-850d-29fc930fdefe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707701305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.1707701305
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.1100041450
Short name T575
Test name
Test status
Simulation time 57899023 ps
CPU time 0.53 seconds
Started Jul 29 04:20:29 PM PDT 24
Finished Jul 29 04:20:30 PM PDT 24
Peak memory 182220 kb
Host smart-888855be-ee64-4ca7-92db-a795f876cec1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100041450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.1100041450
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.3265573965
Short name T32
Test name
Test status
Simulation time 71966602 ps
CPU time 0.59 seconds
Started Jul 29 04:25:44 PM PDT 24
Finished Jul 29 04:25:44 PM PDT 24
Peak memory 191352 kb
Host smart-21f6b2fa-8b06-4609-ae79-bb7893432b86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265573965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.3265573965
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.2890790245
Short name T569
Test name
Test status
Simulation time 81835250 ps
CPU time 1.15 seconds
Started Jul 29 04:25:56 PM PDT 24
Finished Jul 29 04:25:58 PM PDT 24
Peak memory 196976 kb
Host smart-3724cd63-f287-42af-b6a4-f62fa96de04d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890790245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.2890790245
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1768937504
Short name T534
Test name
Test status
Simulation time 66450233 ps
CPU time 1.08 seconds
Started Jul 29 04:25:28 PM PDT 24
Finished Jul 29 04:25:29 PM PDT 24
Peak memory 195008 kb
Host smart-fddd3ebf-ef1b-48e6-b4b0-2cd496206279
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768937504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.1768937504
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.1345154550
Short name T67
Test name
Test status
Simulation time 123159900 ps
CPU time 0.85 seconds
Started Jul 29 04:23:44 PM PDT 24
Finished Jul 29 04:23:45 PM PDT 24
Peak memory 192552 kb
Host smart-d8cef63b-be8e-41e6-b74e-74581c2fe488
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345154550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.1345154550
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.3898165499
Short name T539
Test name
Test status
Simulation time 146158171 ps
CPU time 1.47 seconds
Started Jul 29 04:19:42 PM PDT 24
Finished Jul 29 04:19:43 PM PDT 24
Peak memory 193100 kb
Host smart-51ab2b40-d31b-40db-b668-8f366e1f8325
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898165499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.3898165499
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.1309072218
Short name T468
Test name
Test status
Simulation time 18370925 ps
CPU time 0.61 seconds
Started Jul 29 04:23:23 PM PDT 24
Finished Jul 29 04:23:24 PM PDT 24
Peak memory 182672 kb
Host smart-c958f56e-efef-40d7-bee6-ee6db7f3c03c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309072218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.1309072218
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.4132485981
Short name T492
Test name
Test status
Simulation time 26141581 ps
CPU time 0.77 seconds
Started Jul 29 04:25:24 PM PDT 24
Finished Jul 29 04:25:26 PM PDT 24
Peak memory 193876 kb
Host smart-0057026a-8559-4cd2-9f76-33af70d10908
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132485981 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.4132485981
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.3074312601
Short name T64
Test name
Test status
Simulation time 14833298 ps
CPU time 0.58 seconds
Started Jul 29 04:20:26 PM PDT 24
Finished Jul 29 04:20:26 PM PDT 24
Peak memory 183068 kb
Host smart-bbc3fb5b-5ad3-4a13-acfe-c57a531d81ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074312601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.3074312601
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.325429483
Short name T524
Test name
Test status
Simulation time 27271307 ps
CPU time 0.63 seconds
Started Jul 29 04:20:55 PM PDT 24
Finished Jul 29 04:20:55 PM PDT 24
Peak memory 182936 kb
Host smart-339ab239-b42c-4235-ba31-419187afc3ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325429483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.325429483
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.3959076071
Short name T48
Test name
Test status
Simulation time 156427359 ps
CPU time 0.78 seconds
Started Jul 29 04:19:54 PM PDT 24
Finished Jul 29 04:19:55 PM PDT 24
Peak memory 193336 kb
Host smart-3dab779d-f6cc-416d-ac90-5ca270e0eb0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959076071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.3959076071
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.2971447561
Short name T459
Test name
Test status
Simulation time 24981861 ps
CPU time 1.17 seconds
Started Jul 29 04:20:36 PM PDT 24
Finished Jul 29 04:20:38 PM PDT 24
Peak memory 195172 kb
Host smart-64018459-d5d3-44c4-8c0d-9a6332d8212f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971447561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.2971447561
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.3972430068
Short name T490
Test name
Test status
Simulation time 352408137 ps
CPU time 1.3 seconds
Started Jul 29 04:20:36 PM PDT 24
Finished Jul 29 04:20:38 PM PDT 24
Peak memory 193264 kb
Host smart-0c97a51c-9f60-4366-ac6e-b61d3e73683b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972430068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.3972430068
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.4039949385
Short name T477
Test name
Test status
Simulation time 57837050 ps
CPU time 0.51 seconds
Started Jul 29 04:20:34 PM PDT 24
Finished Jul 29 04:20:34 PM PDT 24
Peak memory 182188 kb
Host smart-2c8e5853-269f-41d8-8492-b7c2093e47c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039949385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.4039949385
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1998343185
Short name T473
Test name
Test status
Simulation time 75444023 ps
CPU time 0.56 seconds
Started Jul 29 04:20:28 PM PDT 24
Finished Jul 29 04:20:29 PM PDT 24
Peak memory 181996 kb
Host smart-78700bb9-dd23-429e-afd9-e94795b1e64f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998343185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.1998343185
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.4046576235
Short name T541
Test name
Test status
Simulation time 11475315 ps
CPU time 0.52 seconds
Started Jul 29 04:20:32 PM PDT 24
Finished Jul 29 04:20:33 PM PDT 24
Peak memory 182028 kb
Host smart-fd241048-a39e-465a-b61e-03c39c4eb722
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046576235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.4046576235
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.3107098036
Short name T545
Test name
Test status
Simulation time 40619621 ps
CPU time 0.58 seconds
Started Jul 29 04:20:29 PM PDT 24
Finished Jul 29 04:20:30 PM PDT 24
Peak memory 182416 kb
Host smart-ed6fd814-50dd-459a-9b39-6e4f39136005
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107098036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.3107098036
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.213157797
Short name T568
Test name
Test status
Simulation time 50367306 ps
CPU time 0.57 seconds
Started Jul 29 04:21:12 PM PDT 24
Finished Jul 29 04:21:13 PM PDT 24
Peak memory 182932 kb
Host smart-1c747bd2-2786-48de-a7c9-3ed15f494cf0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213157797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.213157797
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.2912194902
Short name T479
Test name
Test status
Simulation time 75541459 ps
CPU time 0.58 seconds
Started Jul 29 04:20:35 PM PDT 24
Finished Jul 29 04:20:35 PM PDT 24
Peak memory 182604 kb
Host smart-c20b7843-a947-49f9-9c9d-002bf9aa7cb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912194902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.2912194902
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.3410591163
Short name T518
Test name
Test status
Simulation time 13307877 ps
CPU time 0.55 seconds
Started Jul 29 04:20:43 PM PDT 24
Finished Jul 29 04:20:43 PM PDT 24
Peak memory 182668 kb
Host smart-178c2a74-1636-4e88-84a1-12aa88cbf49f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410591163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.3410591163
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.680566345
Short name T580
Test name
Test status
Simulation time 16603907 ps
CPU time 0.56 seconds
Started Jul 29 04:22:04 PM PDT 24
Finished Jul 29 04:22:05 PM PDT 24
Peak memory 182504 kb
Host smart-a4d4f457-f60d-4033-b699-7676c08704f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680566345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.680566345
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1175090105
Short name T485
Test name
Test status
Simulation time 34435388 ps
CPU time 0.54 seconds
Started Jul 29 04:25:18 PM PDT 24
Finished Jul 29 04:25:19 PM PDT 24
Peak memory 182516 kb
Host smart-1c7e6276-5311-4bfa-a47e-a00617f5730f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175090105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.1175090105
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.1517680081
Short name T506
Test name
Test status
Simulation time 43596032 ps
CPU time 0.58 seconds
Started Jul 29 04:20:50 PM PDT 24
Finished Jul 29 04:20:51 PM PDT 24
Peak memory 182524 kb
Host smart-4b8823d6-45cd-432a-9fe3-28b35e25774f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517680081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.1517680081
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3434525754
Short name T31
Test name
Test status
Simulation time 56905938 ps
CPU time 0.79 seconds
Started Jul 29 04:24:59 PM PDT 24
Finished Jul 29 04:25:00 PM PDT 24
Peak memory 192396 kb
Host smart-c97b075a-9645-4ac5-8b0b-4bfc626f823b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434525754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.3434525754
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.3064834711
Short name T484
Test name
Test status
Simulation time 1907713202 ps
CPU time 1.51 seconds
Started Jul 29 04:20:32 PM PDT 24
Finished Jul 29 04:20:33 PM PDT 24
Peak memory 191124 kb
Host smart-c998c99e-548a-4ef9-99c5-844c286bee3b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064834711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.3064834711
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.4275532296
Short name T564
Test name
Test status
Simulation time 37411900 ps
CPU time 0.53 seconds
Started Jul 29 04:25:38 PM PDT 24
Finished Jul 29 04:25:39 PM PDT 24
Peak memory 182700 kb
Host smart-14f9bf64-28eb-4f6b-a388-85751f56e18e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275532296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.4275532296
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.3694120660
Short name T528
Test name
Test status
Simulation time 73887952 ps
CPU time 0.69 seconds
Started Jul 29 04:24:58 PM PDT 24
Finished Jul 29 04:24:59 PM PDT 24
Peak memory 193328 kb
Host smart-6817f56e-46e1-4422-86d3-2ecc6719833c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694120660 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.3694120660
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.1104413988
Short name T65
Test name
Test status
Simulation time 42502960 ps
CPU time 0.57 seconds
Started Jul 29 04:24:58 PM PDT 24
Finished Jul 29 04:24:59 PM PDT 24
Peak memory 181048 kb
Host smart-c5cf555b-2b7f-4148-91a3-dbec5b4b4ed8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104413988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.1104413988
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.2646393625
Short name T487
Test name
Test status
Simulation time 40801344 ps
CPU time 0.57 seconds
Started Jul 29 04:21:10 PM PDT 24
Finished Jul 29 04:21:11 PM PDT 24
Peak memory 182360 kb
Host smart-65a39685-b844-4132-b0f6-5ab11a679c9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646393625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.2646393625
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.4143784128
Short name T77
Test name
Test status
Simulation time 63711108 ps
CPU time 0.69 seconds
Started Jul 29 04:20:53 PM PDT 24
Finished Jul 29 04:20:53 PM PDT 24
Peak memory 192040 kb
Host smart-8d313840-6880-4c8e-a12a-f400d9e4e965
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143784128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.4143784128
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.2071703439
Short name T533
Test name
Test status
Simulation time 157603356 ps
CPU time 2.14 seconds
Started Jul 29 04:24:59 PM PDT 24
Finished Jul 29 04:25:01 PM PDT 24
Peak memory 197132 kb
Host smart-f04a7016-1a36-4c35-977c-88d7537f1b3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071703439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.2071703439
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.3151251722
Short name T498
Test name
Test status
Simulation time 135622863 ps
CPU time 1.31 seconds
Started Jul 29 04:25:24 PM PDT 24
Finished Jul 29 04:25:26 PM PDT 24
Peak memory 182172 kb
Host smart-6f34a272-ef52-4e97-a717-63fde633732f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151251722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.3151251722
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.1731501374
Short name T463
Test name
Test status
Simulation time 76686855 ps
CPU time 0.53 seconds
Started Jul 29 04:22:23 PM PDT 24
Finished Jul 29 04:22:24 PM PDT 24
Peak memory 182560 kb
Host smart-bd1495e7-ed48-45b1-bf0c-d6d881910361
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731501374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.1731501374
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.3156745916
Short name T503
Test name
Test status
Simulation time 14779524 ps
CPU time 0.6 seconds
Started Jul 29 04:20:51 PM PDT 24
Finished Jul 29 04:20:52 PM PDT 24
Peak memory 182444 kb
Host smart-def55f32-2257-41b4-b1e1-16dda2bae4bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156745916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.3156745916
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.750629456
Short name T537
Test name
Test status
Simulation time 103924113 ps
CPU time 0.55 seconds
Started Jul 29 04:25:18 PM PDT 24
Finished Jul 29 04:25:19 PM PDT 24
Peak memory 182544 kb
Host smart-cdfc626d-f28d-42e1-a014-a927741e9533
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750629456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.750629456
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.2593185340
Short name T521
Test name
Test status
Simulation time 45868406 ps
CPU time 0.58 seconds
Started Jul 29 04:25:03 PM PDT 24
Finished Jul 29 04:25:04 PM PDT 24
Peak memory 182400 kb
Host smart-d53856ee-4e5f-4f9d-aea0-efd038bc4a47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593185340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.2593185340
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.2348105106
Short name T552
Test name
Test status
Simulation time 26711480 ps
CPU time 0.53 seconds
Started Jul 29 04:25:18 PM PDT 24
Finished Jul 29 04:25:19 PM PDT 24
Peak memory 182528 kb
Host smart-ac4d5a0b-0728-47a6-9a22-e46bee78fe43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348105106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.2348105106
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2413256945
Short name T465
Test name
Test status
Simulation time 38936585 ps
CPU time 0.56 seconds
Started Jul 29 04:25:13 PM PDT 24
Finished Jul 29 04:25:14 PM PDT 24
Peak memory 182552 kb
Host smart-1f3ba5d4-7171-4d7d-bc6d-11073a6a8115
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413256945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.2413256945
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.4129185326
Short name T466
Test name
Test status
Simulation time 16621385 ps
CPU time 0.55 seconds
Started Jul 29 04:23:13 PM PDT 24
Finished Jul 29 04:23:13 PM PDT 24
Peak memory 182552 kb
Host smart-1c659773-94b0-431a-83fa-f072b8286a1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129185326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.4129185326
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.1550523466
Short name T474
Test name
Test status
Simulation time 41331470 ps
CPU time 0.52 seconds
Started Jul 29 04:25:13 PM PDT 24
Finished Jul 29 04:25:13 PM PDT 24
Peak memory 182012 kb
Host smart-1e3ebb42-d77b-475f-8735-71577424f19e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550523466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.1550523466
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.267953391
Short name T467
Test name
Test status
Simulation time 57494884 ps
CPU time 0.6 seconds
Started Jul 29 04:24:56 PM PDT 24
Finished Jul 29 04:24:58 PM PDT 24
Peak memory 181832 kb
Host smart-56c93965-98da-4791-9595-7f7d8b837cd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267953391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.267953391
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.2658300071
Short name T543
Test name
Test status
Simulation time 12678636 ps
CPU time 0.56 seconds
Started Jul 29 04:25:11 PM PDT 24
Finished Jul 29 04:25:12 PM PDT 24
Peak memory 179924 kb
Host smart-2b618c6b-3e33-4463-952b-715808e9c4b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658300071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.2658300071
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1793648792
Short name T69
Test name
Test status
Simulation time 39628485 ps
CPU time 0.78 seconds
Started Jul 29 04:25:26 PM PDT 24
Finished Jul 29 04:25:27 PM PDT 24
Peak memory 191420 kb
Host smart-7e6ee74d-c56f-41c7-b409-23181300c0f1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793648792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.1793648792
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.757438458
Short name T567
Test name
Test status
Simulation time 105810506 ps
CPU time 3.08 seconds
Started Jul 29 04:21:05 PM PDT 24
Finished Jul 29 04:21:08 PM PDT 24
Peak memory 191484 kb
Host smart-3d205be6-8915-417b-a214-d86d38010213
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757438458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_b
ash.757438458
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2736163729
Short name T71
Test name
Test status
Simulation time 21404805 ps
CPU time 0.57 seconds
Started Jul 29 04:21:25 PM PDT 24
Finished Jul 29 04:21:26 PM PDT 24
Peak memory 182868 kb
Host smart-7b0dfd4e-f4a1-4258-a01e-11f51311b585
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736163729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.2736163729
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3189434847
Short name T531
Test name
Test status
Simulation time 25252215 ps
CPU time 0.8 seconds
Started Jul 29 04:23:55 PM PDT 24
Finished Jul 29 04:23:56 PM PDT 24
Peak memory 195984 kb
Host smart-507cb381-3021-4917-8fe5-631ac5a95932
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189434847 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.3189434847
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.755103549
Short name T45
Test name
Test status
Simulation time 54233674 ps
CPU time 0.55 seconds
Started Jul 29 04:20:29 PM PDT 24
Finished Jul 29 04:20:30 PM PDT 24
Peak memory 182448 kb
Host smart-1b7868ad-9194-4dd6-9b80-850a9e986333
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755103549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.755103549
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.617414871
Short name T451
Test name
Test status
Simulation time 26086263 ps
CPU time 0.55 seconds
Started Jul 29 04:22:00 PM PDT 24
Finished Jul 29 04:22:01 PM PDT 24
Peak memory 182464 kb
Host smart-7f7ffc1e-837a-4443-9fb6-714188b41c9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617414871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.617414871
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.2957252113
Short name T49
Test name
Test status
Simulation time 30236855 ps
CPU time 0.73 seconds
Started Jul 29 04:23:56 PM PDT 24
Finished Jul 29 04:23:57 PM PDT 24
Peak memory 191616 kb
Host smart-320b1c97-12ed-42d9-a7d5-75fd6c50ed05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957252113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.2957252113
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2964940563
Short name T454
Test name
Test status
Simulation time 223126847 ps
CPU time 1.27 seconds
Started Jul 29 04:20:55 PM PDT 24
Finished Jul 29 04:20:57 PM PDT 24
Peak memory 197388 kb
Host smart-7abec3ad-c481-4057-86b1-9276c6ebf7fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964940563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.2964940563
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.1640984263
Short name T90
Test name
Test status
Simulation time 75179211 ps
CPU time 1.11 seconds
Started Jul 29 04:23:01 PM PDT 24
Finished Jul 29 04:23:03 PM PDT 24
Peak memory 195180 kb
Host smart-c82531e4-0df7-4499-9b4d-ab67aac6de2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640984263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.1640984263
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.3652000387
Short name T555
Test name
Test status
Simulation time 52612922 ps
CPU time 0.55 seconds
Started Jul 29 04:23:15 PM PDT 24
Finished Jul 29 04:23:16 PM PDT 24
Peak memory 182520 kb
Host smart-0ef29575-fdfc-45e7-a2aa-36d3ac231c39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652000387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.3652000387
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.3510055683
Short name T470
Test name
Test status
Simulation time 14721507 ps
CPU time 0.55 seconds
Started Jul 29 04:21:11 PM PDT 24
Finished Jul 29 04:21:12 PM PDT 24
Peak memory 182040 kb
Host smart-0ec8967c-609b-4380-8da0-0c6e84e0bcda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510055683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.3510055683
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.3357246120
Short name T476
Test name
Test status
Simulation time 44916480 ps
CPU time 0.51 seconds
Started Jul 29 04:26:23 PM PDT 24
Finished Jul 29 04:26:24 PM PDT 24
Peak memory 181992 kb
Host smart-cf6e31f1-aaf0-40b0-9f2e-eedce9058dd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357246120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.3357246120
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.3792258704
Short name T497
Test name
Test status
Simulation time 13048460 ps
CPU time 0.56 seconds
Started Jul 29 04:21:12 PM PDT 24
Finished Jul 29 04:21:12 PM PDT 24
Peak memory 182840 kb
Host smart-c591bbb3-fd21-46f7-af5f-24d60736b06c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792258704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.3792258704
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.351573379
Short name T562
Test name
Test status
Simulation time 23832023 ps
CPU time 0.57 seconds
Started Jul 29 04:25:44 PM PDT 24
Finished Jul 29 04:25:44 PM PDT 24
Peak memory 182532 kb
Host smart-2811f88a-cfb3-4290-8664-b7097fdfc8af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351573379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.351573379
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1623808429
Short name T573
Test name
Test status
Simulation time 11218730 ps
CPU time 0.52 seconds
Started Jul 29 04:27:07 PM PDT 24
Finished Jul 29 04:27:08 PM PDT 24
Peak memory 182540 kb
Host smart-091d74f6-7723-4f46-8090-d82bfa3a6b8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623808429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.1623808429
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.2797551373
Short name T526
Test name
Test status
Simulation time 65337218 ps
CPU time 0.56 seconds
Started Jul 29 04:21:09 PM PDT 24
Finished Jul 29 04:21:10 PM PDT 24
Peak memory 182060 kb
Host smart-8e4a2458-ff05-4dd3-b9db-fb314be7b178
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797551373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.2797551373
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.132843023
Short name T571
Test name
Test status
Simulation time 33043475 ps
CPU time 0.56 seconds
Started Jul 29 04:21:05 PM PDT 24
Finished Jul 29 04:21:05 PM PDT 24
Peak memory 182944 kb
Host smart-a757fe32-1a99-48f7-ba03-db7cd5d3cfb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132843023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.132843023
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.1711202519
Short name T453
Test name
Test status
Simulation time 13560645 ps
CPU time 0.51 seconds
Started Jul 29 04:27:03 PM PDT 24
Finished Jul 29 04:27:04 PM PDT 24
Peak memory 182220 kb
Host smart-9b24961a-f908-40b0-926c-dd115d2b4ccc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711202519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.1711202519
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.2907859179
Short name T478
Test name
Test status
Simulation time 79475210 ps
CPU time 0.51 seconds
Started Jul 29 04:27:03 PM PDT 24
Finished Jul 29 04:27:04 PM PDT 24
Peak memory 182228 kb
Host smart-b0709317-d533-4833-996e-4b0cc80e93df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907859179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.2907859179
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2051334236
Short name T574
Test name
Test status
Simulation time 85767003 ps
CPU time 1.14 seconds
Started Jul 29 04:22:39 PM PDT 24
Finished Jul 29 04:22:41 PM PDT 24
Peak memory 197456 kb
Host smart-e582783c-fb9f-4a82-b7e9-3cafa0cad8fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051334236 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.2051334236
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.2460161034
Short name T561
Test name
Test status
Simulation time 46482498 ps
CPU time 0.54 seconds
Started Jul 29 04:20:57 PM PDT 24
Finished Jul 29 04:20:58 PM PDT 24
Peak memory 182460 kb
Host smart-5adcf713-8b3a-48b7-9a26-6a01d13f1e68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460161034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.2460161034
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1095099045
Short name T520
Test name
Test status
Simulation time 12931892 ps
CPU time 0.52 seconds
Started Jul 29 04:25:41 PM PDT 24
Finished Jul 29 04:25:42 PM PDT 24
Peak memory 181996 kb
Host smart-a6e6389c-737b-4f9e-b638-08d21ced9855
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095099045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.1095099045
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1400472654
Short name T46
Test name
Test status
Simulation time 29957370 ps
CPU time 0.68 seconds
Started Jul 29 04:25:34 PM PDT 24
Finished Jul 29 04:25:34 PM PDT 24
Peak memory 192920 kb
Host smart-46da5854-5d34-451d-9e9e-d59859492df4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400472654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.1400472654
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.3248055401
Short name T53
Test name
Test status
Simulation time 78791382 ps
CPU time 0.93 seconds
Started Jul 29 04:25:34 PM PDT 24
Finished Jul 29 04:25:35 PM PDT 24
Peak memory 196728 kb
Host smart-b7410dd0-21f1-4aca-8e24-2f360d4ec55e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248055401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.3248055401
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1635518041
Short name T89
Test name
Test status
Simulation time 220673390 ps
CPU time 0.82 seconds
Started Jul 29 04:21:34 PM PDT 24
Finished Jul 29 04:21:35 PM PDT 24
Peak memory 193460 kb
Host smart-33b6e20c-43a4-4658-b3d2-38040f80bfad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635518041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.1635518041
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.513113411
Short name T557
Test name
Test status
Simulation time 15619184 ps
CPU time 0.6 seconds
Started Jul 29 04:23:09 PM PDT 24
Finished Jul 29 04:23:10 PM PDT 24
Peak memory 193116 kb
Host smart-7def6c0f-4759-4285-8be1-772ec1c7313f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513113411 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.513113411
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.3922304234
Short name T572
Test name
Test status
Simulation time 23605323 ps
CPU time 0.6 seconds
Started Jul 29 04:22:48 PM PDT 24
Finished Jul 29 04:22:49 PM PDT 24
Peak memory 182876 kb
Host smart-100e7a0d-549e-4704-abb1-30a16ae054c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922304234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.3922304234
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.3775278566
Short name T532
Test name
Test status
Simulation time 42002973 ps
CPU time 0.51 seconds
Started Jul 29 04:25:04 PM PDT 24
Finished Jul 29 04:25:04 PM PDT 24
Peak memory 182200 kb
Host smart-4d96b901-b9da-4bc8-bda9-e1c3c6a2b534
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775278566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.3775278566
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.1052202381
Short name T75
Test name
Test status
Simulation time 58072658 ps
CPU time 0.75 seconds
Started Jul 29 04:25:03 PM PDT 24
Finished Jul 29 04:25:04 PM PDT 24
Peak memory 192532 kb
Host smart-7a21f579-c72d-4655-a782-2d93d97feeaa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052202381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.1052202381
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.1412442573
Short name T529
Test name
Test status
Simulation time 165285646 ps
CPU time 1.99 seconds
Started Jul 29 04:25:24 PM PDT 24
Finished Jul 29 04:25:26 PM PDT 24
Peak memory 196732 kb
Host smart-d5ae799b-da25-4a1a-8a93-72d28205dee8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412442573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.1412442573
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.3825592317
Short name T496
Test name
Test status
Simulation time 69554663 ps
CPU time 1.07 seconds
Started Jul 29 04:22:48 PM PDT 24
Finished Jul 29 04:22:49 PM PDT 24
Peak memory 195208 kb
Host smart-c3ef9fa3-4888-42c4-85d7-10212b43026b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825592317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.3825592317
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.1749058888
Short name T508
Test name
Test status
Simulation time 30711545 ps
CPU time 0.75 seconds
Started Jul 29 04:25:02 PM PDT 24
Finished Jul 29 04:25:03 PM PDT 24
Peak memory 194868 kb
Host smart-71efc201-26e2-4676-87b0-9963db884289
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749058888 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.1749058888
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.2346138356
Short name T548
Test name
Test status
Simulation time 14925590 ps
CPU time 0.58 seconds
Started Jul 29 04:20:04 PM PDT 24
Finished Jul 29 04:20:05 PM PDT 24
Peak memory 182608 kb
Host smart-378b8ca2-e730-4c5b-abca-36968f8a402c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346138356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.2346138356
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.2960670031
Short name T501
Test name
Test status
Simulation time 23540000 ps
CPU time 0.55 seconds
Started Jul 29 04:21:15 PM PDT 24
Finished Jul 29 04:21:15 PM PDT 24
Peak memory 182424 kb
Host smart-dd6c79b8-4d6e-4702-8434-820fae5c2cbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960670031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.2960670031
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.2303615292
Short name T507
Test name
Test status
Simulation time 69240082 ps
CPU time 0.6 seconds
Started Jul 29 04:21:15 PM PDT 24
Finished Jul 29 04:21:15 PM PDT 24
Peak memory 191120 kb
Host smart-8984a7ec-015b-448a-b5bd-48121304eeb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303615292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.2303615292
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.2262998637
Short name T460
Test name
Test status
Simulation time 59405793 ps
CPU time 1.42 seconds
Started Jul 29 04:19:52 PM PDT 24
Finished Jul 29 04:19:54 PM PDT 24
Peak memory 197404 kb
Host smart-e40bc080-1101-4d60-9b7d-efe2946b1130
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262998637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.2262998637
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.3690949164
Short name T50
Test name
Test status
Simulation time 52885154 ps
CPU time 0.85 seconds
Started Jul 29 04:25:56 PM PDT 24
Finished Jul 29 04:25:57 PM PDT 24
Peak memory 192480 kb
Host smart-cf201f72-a174-4bee-ae96-2677e6bd2949
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690949164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.3690949164
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3244331070
Short name T522
Test name
Test status
Simulation time 87933665 ps
CPU time 0.77 seconds
Started Jul 29 04:20:22 PM PDT 24
Finished Jul 29 04:20:23 PM PDT 24
Peak memory 195304 kb
Host smart-6a00dd3a-514b-40b4-9efe-48331d7d6fff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244331070 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.3244331070
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.2065570321
Short name T578
Test name
Test status
Simulation time 24700608 ps
CPU time 0.58 seconds
Started Jul 29 04:21:21 PM PDT 24
Finished Jul 29 04:21:22 PM PDT 24
Peak memory 182704 kb
Host smart-9f95e263-c25f-44db-912a-171b7cac5cbe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065570321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.2065570321
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.299402531
Short name T457
Test name
Test status
Simulation time 27842485 ps
CPU time 0.57 seconds
Started Jul 29 04:22:43 PM PDT 24
Finished Jul 29 04:22:44 PM PDT 24
Peak memory 182532 kb
Host smart-d2595a0c-c089-4fb7-8bf9-e1ba0253d572
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299402531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.299402531
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.2591631368
Short name T76
Test name
Test status
Simulation time 19657280 ps
CPU time 0.68 seconds
Started Jul 29 04:25:03 PM PDT 24
Finished Jul 29 04:25:04 PM PDT 24
Peak memory 190404 kb
Host smart-11991f35-8663-4ad2-88b8-95d22e8663bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591631368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.2591631368
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3149624745
Short name T577
Test name
Test status
Simulation time 150010412 ps
CPU time 2.79 seconds
Started Jul 29 04:21:13 PM PDT 24
Finished Jul 29 04:21:16 PM PDT 24
Peak memory 197444 kb
Host smart-89a72232-ba49-46cd-93df-f53cb30531a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149624745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.3149624745
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.2041586573
Short name T30
Test name
Test status
Simulation time 91979524 ps
CPU time 1.08 seconds
Started Jul 29 04:24:47 PM PDT 24
Finished Jul 29 04:24:49 PM PDT 24
Peak memory 193932 kb
Host smart-145dd907-8797-4286-83fb-e2aad1869b40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041586573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.2041586573
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.1074393776
Short name T51
Test name
Test status
Simulation time 24991216 ps
CPU time 0.73 seconds
Started Jul 29 04:25:03 PM PDT 24
Finished Jul 29 04:25:04 PM PDT 24
Peak memory 193508 kb
Host smart-9146c04a-95b8-4a92-bf4b-128b39ceb050
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074393776 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.1074393776
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.3803848913
Short name T72
Test name
Test status
Simulation time 21704525 ps
CPU time 0.57 seconds
Started Jul 29 04:20:55 PM PDT 24
Finished Jul 29 04:20:55 PM PDT 24
Peak memory 182712 kb
Host smart-d3023953-4314-4eec-a6db-f2ba0df4b3eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803848913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.3803848913
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.977509451
Short name T551
Test name
Test status
Simulation time 39549935 ps
CPU time 0.55 seconds
Started Jul 29 04:20:39 PM PDT 24
Finished Jul 29 04:20:40 PM PDT 24
Peak memory 182000 kb
Host smart-396de5ea-a71c-41b8-ab49-7671369f6258
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977509451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.977509451
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1779794768
Short name T566
Test name
Test status
Simulation time 120107030 ps
CPU time 0.7 seconds
Started Jul 29 04:20:21 PM PDT 24
Finished Jul 29 04:20:22 PM PDT 24
Peak memory 193056 kb
Host smart-9a3e8d07-c971-44e4-a5d3-72aa3efc64b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779794768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.1779794768
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.1388678912
Short name T535
Test name
Test status
Simulation time 22425332 ps
CPU time 1.3 seconds
Started Jul 29 04:20:25 PM PDT 24
Finished Jul 29 04:20:27 PM PDT 24
Peak memory 197808 kb
Host smart-7639af92-a137-45d4-97d2-4a34b3f7f988
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388678912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.1388678912
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3378073324
Short name T547
Test name
Test status
Simulation time 1428516421 ps
CPU time 1.3 seconds
Started Jul 29 04:21:15 PM PDT 24
Finished Jul 29 04:21:16 PM PDT 24
Peak memory 195424 kb
Host smart-951d6ca0-64a0-45de-83c9-db954ab59258
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378073324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.3378073324
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.3631146228
Short name T322
Test name
Test status
Simulation time 558215388134 ps
CPU time 283.39 seconds
Started Jul 29 04:20:37 PM PDT 24
Finished Jul 29 04:25:21 PM PDT 24
Peak memory 182904 kb
Host smart-d524509a-8ff8-47c2-a5de-bebb43a8efa0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631146228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.3631146228
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.1201658024
Short name T423
Test name
Test status
Simulation time 124368930365 ps
CPU time 158.26 seconds
Started Jul 29 04:19:36 PM PDT 24
Finished Jul 29 04:22:14 PM PDT 24
Peak memory 182980 kb
Host smart-a0d3daac-8345-4514-8003-89a5d6123bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201658024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.1201658024
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.2759337673
Short name T253
Test name
Test status
Simulation time 512909795908 ps
CPU time 284.48 seconds
Started Jul 29 04:20:36 PM PDT 24
Finished Jul 29 04:25:21 PM PDT 24
Peak memory 189464 kb
Host smart-2de23de8-fc54-4c4a-8cf9-d90b8f6cea6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759337673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.2759337673
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.2679187442
Short name T396
Test name
Test status
Simulation time 30058227685 ps
CPU time 389.14 seconds
Started Jul 29 04:19:35 PM PDT 24
Finished Jul 29 04:26:05 PM PDT 24
Peak memory 182236 kb
Host smart-f715236d-1fae-43a3-9da8-d246641153b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679187442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.2679187442
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all_with_rand_reset.2644516784
Short name T36
Test name
Test status
Simulation time 158853403873 ps
CPU time 1612.64 seconds
Started Jul 29 04:19:35 PM PDT 24
Finished Jul 29 04:46:28 PM PDT 24
Peak memory 223144 kb
Host smart-d403cc67-0313-4af8-b46f-48fcd07365f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644516784 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all_with_rand_reset.2644516784
Directory /workspace/0.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.1106353309
Short name T389
Test name
Test status
Simulation time 110997324568 ps
CPU time 84.06 seconds
Started Jul 29 04:20:37 PM PDT 24
Finished Jul 29 04:22:01 PM PDT 24
Peak memory 182220 kb
Host smart-03bf2dc8-af11-4f2c-af85-9e9fe35a9f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106353309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.1106353309
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.3311285623
Short name T18
Test name
Test status
Simulation time 139156280 ps
CPU time 0.85 seconds
Started Jul 29 04:20:32 PM PDT 24
Finished Jul 29 04:20:33 PM PDT 24
Peak memory 213924 kb
Host smart-4dc5ffc0-ad7f-49d1-a229-4917df9a6ff9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311285623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.3311285623
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.894321783
Short name T44
Test name
Test status
Simulation time 1480507659 ps
CPU time 2.97 seconds
Started Jul 29 04:21:13 PM PDT 24
Finished Jul 29 04:21:16 PM PDT 24
Peak memory 183360 kb
Host smart-e427fc7d-2f36-43de-adbc-842210e6609a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894321783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.rv_timer_cfg_update_on_fly.894321783
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.1516408642
Short name T79
Test name
Test status
Simulation time 25619858722 ps
CPU time 25.17 seconds
Started Jul 29 04:23:01 PM PDT 24
Finished Jul 29 04:23:26 PM PDT 24
Peak memory 191472 kb
Host smart-b0f3856b-1e05-49bb-8fd8-3c805c590af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516408642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.1516408642
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.1432068594
Short name T397
Test name
Test status
Simulation time 173643325948 ps
CPU time 223.68 seconds
Started Jul 29 04:25:19 PM PDT 24
Finished Jul 29 04:29:03 PM PDT 24
Peak memory 194780 kb
Host smart-37d41316-72c8-405d-9270-8604189233e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432068594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.1432068594
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/100.rv_timer_random.2524498548
Short name T142
Test name
Test status
Simulation time 1491928242363 ps
CPU time 462.51 seconds
Started Jul 29 04:25:56 PM PDT 24
Finished Jul 29 04:33:39 PM PDT 24
Peak memory 191288 kb
Host smart-18c1af4e-990b-4906-9a0c-12f3386aed5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524498548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.2524498548
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.1010143285
Short name T318
Test name
Test status
Simulation time 53778920688 ps
CPU time 272.5 seconds
Started Jul 29 04:24:36 PM PDT 24
Finished Jul 29 04:29:08 PM PDT 24
Peak memory 183248 kb
Host smart-fa0e4ba7-9210-4e94-a90a-277f3486ce92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010143285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.1010143285
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.2057529248
Short name T283
Test name
Test status
Simulation time 10113246725 ps
CPU time 12.1 seconds
Started Jul 29 04:25:56 PM PDT 24
Finished Jul 29 04:26:09 PM PDT 24
Peak memory 183092 kb
Host smart-45efad78-04cc-4f79-8418-e625dfdc39e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057529248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.2057529248
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.1409132142
Short name T259
Test name
Test status
Simulation time 15534254753 ps
CPU time 144.7 seconds
Started Jul 29 04:24:35 PM PDT 24
Finished Jul 29 04:27:00 PM PDT 24
Peak memory 191780 kb
Host smart-4fb5d7be-ad13-474c-b723-efcbf0287fd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409132142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.1409132142
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.1173980673
Short name T296
Test name
Test status
Simulation time 183574634214 ps
CPU time 347.05 seconds
Started Jul 29 04:24:33 PM PDT 24
Finished Jul 29 04:30:20 PM PDT 24
Peak memory 191432 kb
Host smart-49a37b52-d94c-488a-a018-ff28d84b0461
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173980673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.1173980673
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.731408783
Short name T354
Test name
Test status
Simulation time 17202598090 ps
CPU time 28.6 seconds
Started Jul 29 04:24:45 PM PDT 24
Finished Jul 29 04:25:13 PM PDT 24
Peak memory 183272 kb
Host smart-b08914a1-3d2e-487f-96fb-60c3f259e1b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731408783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.731408783
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.382343910
Short name T174
Test name
Test status
Simulation time 18551275428 ps
CPU time 22.95 seconds
Started Jul 29 04:25:35 PM PDT 24
Finished Jul 29 04:25:58 PM PDT 24
Peak memory 182916 kb
Host smart-d2a612f4-1b12-4023-a937-951fc495a027
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382343910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.rv_timer_cfg_update_on_fly.382343910
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.526215978
Short name T365
Test name
Test status
Simulation time 91444676539 ps
CPU time 128.84 seconds
Started Jul 29 04:25:35 PM PDT 24
Finished Jul 29 04:27:44 PM PDT 24
Peak memory 182996 kb
Host smart-16eb0b90-f0f1-4320-ba14-c2e24653cad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526215978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.526215978
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.3381279781
Short name T279
Test name
Test status
Simulation time 78189257501 ps
CPU time 70.7 seconds
Started Jul 29 04:22:33 PM PDT 24
Finished Jul 29 04:23:44 PM PDT 24
Peak memory 183264 kb
Host smart-cc2b4835-931f-4eb3-9080-251ce26381cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381279781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.3381279781
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.2463650526
Short name T431
Test name
Test status
Simulation time 172326253240 ps
CPU time 55.06 seconds
Started Jul 29 04:23:27 PM PDT 24
Finished Jul 29 04:24:23 PM PDT 24
Peak memory 194728 kb
Host smart-d670de47-bdd3-439e-bee0-76344295a70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463650526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.2463650526
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/110.rv_timer_random.2306680217
Short name T105
Test name
Test status
Simulation time 68510878979 ps
CPU time 193.6 seconds
Started Jul 29 04:24:52 PM PDT 24
Finished Jul 29 04:28:06 PM PDT 24
Peak memory 191620 kb
Host smart-84276d19-a2a8-4c1c-b598-5f3807054a9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306680217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.2306680217
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.4015760428
Short name T323
Test name
Test status
Simulation time 31732541414 ps
CPU time 131.43 seconds
Started Jul 29 04:24:51 PM PDT 24
Finished Jul 29 04:27:03 PM PDT 24
Peak memory 183580 kb
Host smart-1c963e9c-33b8-485b-a00c-f9e5e6d65ddf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015760428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.4015760428
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.432463226
Short name T333
Test name
Test status
Simulation time 38864062522 ps
CPU time 53.06 seconds
Started Jul 29 04:24:52 PM PDT 24
Finished Jul 29 04:25:45 PM PDT 24
Peak memory 191748 kb
Host smart-fedc8979-c1cc-40fb-a8a4-b8c0c9b45fe4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432463226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.432463226
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.2807063307
Short name T165
Test name
Test status
Simulation time 521602274899 ps
CPU time 475.23 seconds
Started Jul 29 04:24:58 PM PDT 24
Finished Jul 29 04:32:53 PM PDT 24
Peak memory 191432 kb
Host smart-6a556ded-228a-4289-b7d8-79f2bf828fe1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807063307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.2807063307
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.800648243
Short name T300
Test name
Test status
Simulation time 103473428885 ps
CPU time 86.01 seconds
Started Jul 29 04:24:55 PM PDT 24
Finished Jul 29 04:26:21 PM PDT 24
Peak memory 183384 kb
Host smart-f44d23bd-6ba2-4ee4-a208-dfdbc25dd25b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800648243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.800648243
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.293228719
Short name T111
Test name
Test status
Simulation time 90563849243 ps
CPU time 134.63 seconds
Started Jul 29 04:24:59 PM PDT 24
Finished Jul 29 04:27:14 PM PDT 24
Peak memory 191624 kb
Host smart-beaec7f7-790d-487e-b796-ce0362051883
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293228719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.293228719
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.2901847969
Short name T22
Test name
Test status
Simulation time 11717083550 ps
CPU time 6.48 seconds
Started Jul 29 04:25:17 PM PDT 24
Finished Jul 29 04:25:23 PM PDT 24
Peak memory 183192 kb
Host smart-04a15380-cd51-4f4b-92ef-82251999fa55
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901847969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.2901847969
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.332861679
Short name T436
Test name
Test status
Simulation time 57251156888 ps
CPU time 46.32 seconds
Started Jul 29 04:25:34 PM PDT 24
Finished Jul 29 04:26:21 PM PDT 24
Peak memory 183292 kb
Host smart-67144f82-38c2-4bb9-87bf-5bfa4a9d6573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332861679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.332861679
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.4005599644
Short name T215
Test name
Test status
Simulation time 49592837183 ps
CPU time 796.23 seconds
Started Jul 29 04:25:35 PM PDT 24
Finished Jul 29 04:38:52 PM PDT 24
Peak memory 182988 kb
Host smart-a6690cdf-c5b1-4846-97ad-3179a7162fa3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005599644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.4005599644
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.1278789427
Short name T375
Test name
Test status
Simulation time 751566259 ps
CPU time 1.32 seconds
Started Jul 29 04:21:15 PM PDT 24
Finished Jul 29 04:21:16 PM PDT 24
Peak memory 194072 kb
Host smart-7df44d20-d5d7-4fa8-85de-ec3d637ae672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278789427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.1278789427
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all_with_rand_reset.3388356321
Short name T41
Test name
Test status
Simulation time 59510050717 ps
CPU time 233.51 seconds
Started Jul 29 04:25:35 PM PDT 24
Finished Jul 29 04:29:29 PM PDT 24
Peak memory 206112 kb
Host smart-86f4c0dc-cdcf-4ee4-996d-9d82b1644237
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388356321 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all_with_rand_reset.3388356321
Directory /workspace/12.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.rv_timer_random.98515961
Short name T243
Test name
Test status
Simulation time 221673108964 ps
CPU time 887.46 seconds
Started Jul 29 04:24:54 PM PDT 24
Finished Jul 29 04:39:41 PM PDT 24
Peak memory 183624 kb
Host smart-c53a5965-d5a0-4af1-8247-06b8ff93026a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98515961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.98515961
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.1879034821
Short name T248
Test name
Test status
Simulation time 268198385787 ps
CPU time 230.77 seconds
Started Jul 29 04:24:59 PM PDT 24
Finished Jul 29 04:28:50 PM PDT 24
Peak memory 193724 kb
Host smart-3e68faa4-8dea-49d4-a187-5ce0fe9039d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879034821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.1879034821
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.903920064
Short name T7
Test name
Test status
Simulation time 183269915712 ps
CPU time 606.32 seconds
Started Jul 29 04:25:13 PM PDT 24
Finished Jul 29 04:35:20 PM PDT 24
Peak memory 195528 kb
Host smart-2e30c2ab-e233-43ee-a334-a125442d0ff9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903920064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.903920064
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.3985849658
Short name T268
Test name
Test status
Simulation time 88656961810 ps
CPU time 74.63 seconds
Started Jul 29 04:25:14 PM PDT 24
Finished Jul 29 04:26:29 PM PDT 24
Peak memory 183344 kb
Host smart-4db5723f-82e1-45aa-84c1-7060f3ab76db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985849658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.3985849658
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.1816447551
Short name T434
Test name
Test status
Simulation time 410831865864 ps
CPU time 161.22 seconds
Started Jul 29 04:21:17 PM PDT 24
Finished Jul 29 04:23:58 PM PDT 24
Peak memory 183272 kb
Host smart-db1b8025-0003-49d9-876d-b99485184032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816447551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.1816447551
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.1978084118
Short name T110
Test name
Test status
Simulation time 76266283392 ps
CPU time 137.69 seconds
Started Jul 29 04:22:00 PM PDT 24
Finished Jul 29 04:24:17 PM PDT 24
Peak memory 191796 kb
Host smart-b4f952d1-31c9-4901-98a8-2764f46e164e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978084118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.1978084118
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.314032541
Short name T320
Test name
Test status
Simulation time 30859516566 ps
CPU time 16.08 seconds
Started Jul 29 04:26:05 PM PDT 24
Finished Jul 29 04:26:21 PM PDT 24
Peak memory 182928 kb
Host smart-16977546-26d0-4902-9577-0a85230fb7c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314032541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all.
314032541
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/130.rv_timer_random.3112089368
Short name T180
Test name
Test status
Simulation time 127214705854 ps
CPU time 58.24 seconds
Started Jul 29 04:26:35 PM PDT 24
Finished Jul 29 04:27:34 PM PDT 24
Peak memory 191120 kb
Host smart-32d3dd8f-2d3a-45e0-a8f6-6e9244d27e46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112089368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.3112089368
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.2515136179
Short name T425
Test name
Test status
Simulation time 516167989612 ps
CPU time 502.2 seconds
Started Jul 29 04:25:16 PM PDT 24
Finished Jul 29 04:33:39 PM PDT 24
Peak memory 191436 kb
Host smart-a0d64317-f62b-48eb-89f2-82f9e720f024
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515136179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.2515136179
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.3089431526
Short name T207
Test name
Test status
Simulation time 222582361807 ps
CPU time 144.28 seconds
Started Jul 29 04:25:15 PM PDT 24
Finished Jul 29 04:27:39 PM PDT 24
Peak memory 191440 kb
Host smart-2fe493f1-4fcb-4431-9590-0b4736861e1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089431526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.3089431526
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.794466205
Short name T275
Test name
Test status
Simulation time 98578974470 ps
CPU time 216.19 seconds
Started Jul 29 04:25:16 PM PDT 24
Finished Jul 29 04:28:52 PM PDT 24
Peak memory 194000 kb
Host smart-844943c2-bbcd-44a2-b87a-32fec66afecc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794466205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.794466205
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.3457612294
Short name T146
Test name
Test status
Simulation time 816218351326 ps
CPU time 478.12 seconds
Started Jul 29 04:26:34 PM PDT 24
Finished Jul 29 04:34:32 PM PDT 24
Peak memory 191136 kb
Host smart-a1fe5197-f772-455d-bf76-af52768a34fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457612294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.3457612294
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.596457812
Short name T269
Test name
Test status
Simulation time 226633655006 ps
CPU time 186.63 seconds
Started Jul 29 04:26:35 PM PDT 24
Finished Jul 29 04:29:41 PM PDT 24
Peak memory 191144 kb
Host smart-960c1494-2a37-4db6-b822-b97076a9a3dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596457812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.596457812
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.908308211
Short name T26
Test name
Test status
Simulation time 118878579556 ps
CPU time 166.09 seconds
Started Jul 29 04:25:24 PM PDT 24
Finished Jul 29 04:28:10 PM PDT 24
Peak memory 191476 kb
Host smart-9978699f-d9c3-4434-b19a-d2e1f6354159
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908308211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.908308211
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.1923532642
Short name T309
Test name
Test status
Simulation time 1510625982913 ps
CPU time 810.18 seconds
Started Jul 29 04:24:56 PM PDT 24
Finished Jul 29 04:38:27 PM PDT 24
Peak memory 182632 kb
Host smart-a65fa265-bfc0-438f-91ed-a90daa54e124
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923532642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.1923532642
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.2064011617
Short name T363
Test name
Test status
Simulation time 10240343215 ps
CPU time 15.04 seconds
Started Jul 29 04:21:39 PM PDT 24
Finished Jul 29 04:21:54 PM PDT 24
Peak memory 183280 kb
Host smart-83e3817a-6c61-4f4c-b37b-84c3e782f3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064011617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.2064011617
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.1871406143
Short name T227
Test name
Test status
Simulation time 165687080813 ps
CPU time 1175.77 seconds
Started Jul 29 04:21:17 PM PDT 24
Finished Jul 29 04:40:53 PM PDT 24
Peak memory 191372 kb
Host smart-c518f789-ac41-4c68-b84a-c942a8fcd410
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871406143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.1871406143
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.29947775
Short name T400
Test name
Test status
Simulation time 21825161 ps
CPU time 0.55 seconds
Started Jul 29 04:25:15 PM PDT 24
Finished Jul 29 04:25:15 PM PDT 24
Peak memory 182932 kb
Host smart-fbc5b3bb-41ef-4834-87d1-fe932bb49693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29947775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.29947775
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.2224454080
Short name T277
Test name
Test status
Simulation time 131605655482 ps
CPU time 216.96 seconds
Started Jul 29 04:25:15 PM PDT 24
Finished Jul 29 04:28:52 PM PDT 24
Peak memory 191408 kb
Host smart-765e9151-cfd1-4d35-a264-dea02e745ce0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224454080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.2224454080
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/140.rv_timer_random.4119761244
Short name T393
Test name
Test status
Simulation time 78550366361 ps
CPU time 854.03 seconds
Started Jul 29 04:26:35 PM PDT 24
Finished Jul 29 04:40:49 PM PDT 24
Peak memory 194952 kb
Host smart-dd4a222a-0538-4c20-8362-1a49610b32b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119761244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.4119761244
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.2224102414
Short name T407
Test name
Test status
Simulation time 257378522655 ps
CPU time 139.31 seconds
Started Jul 29 04:26:36 PM PDT 24
Finished Jul 29 04:28:55 PM PDT 24
Peak memory 191144 kb
Host smart-1795cf9f-a51d-4863-aad1-77b9c9c42dff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224102414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.2224102414
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.4123402385
Short name T122
Test name
Test status
Simulation time 286929481420 ps
CPU time 639.57 seconds
Started Jul 29 04:25:28 PM PDT 24
Finished Jul 29 04:36:08 PM PDT 24
Peak memory 191432 kb
Host smart-fe8fdf64-1cd9-4a9c-bbfb-19cfbf8cc146
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123402385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.4123402385
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.1575396879
Short name T80
Test name
Test status
Simulation time 16351760050 ps
CPU time 11.73 seconds
Started Jul 29 04:26:50 PM PDT 24
Finished Jul 29 04:27:02 PM PDT 24
Peak memory 182928 kb
Host smart-13ebdf1e-5e19-4301-bb5c-05e2de58a4b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575396879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.1575396879
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.3963938681
Short name T440
Test name
Test status
Simulation time 49561118419 ps
CPU time 1626.52 seconds
Started Jul 29 04:25:33 PM PDT 24
Finished Jul 29 04:52:39 PM PDT 24
Peak memory 183252 kb
Host smart-22f4ebea-e41d-40a1-8099-daaeb63d08d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963938681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.3963938681
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.2518141478
Short name T107
Test name
Test status
Simulation time 39816799076 ps
CPU time 375.26 seconds
Started Jul 29 04:26:36 PM PDT 24
Finished Jul 29 04:32:52 PM PDT 24
Peak memory 191144 kb
Host smart-3929624b-f3cf-4d07-97d6-69cc2a65bd00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518141478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.2518141478
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.458051798
Short name T247
Test name
Test status
Simulation time 102794986357 ps
CPU time 71.67 seconds
Started Jul 29 04:25:32 PM PDT 24
Finished Jul 29 04:26:44 PM PDT 24
Peak memory 183184 kb
Host smart-7814584b-1e2e-47c4-bea1-103ed3c5bb10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458051798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.458051798
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.436508872
Short name T362
Test name
Test status
Simulation time 32783481353 ps
CPU time 45.93 seconds
Started Jul 29 04:25:35 PM PDT 24
Finished Jul 29 04:26:22 PM PDT 24
Peak memory 181720 kb
Host smart-02f5dcde-2218-49bf-a68d-407cb84c131e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436508872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.436508872
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.1181547973
Short name T266
Test name
Test status
Simulation time 197844275655 ps
CPU time 137.41 seconds
Started Jul 29 04:22:04 PM PDT 24
Finished Jul 29 04:24:21 PM PDT 24
Peak memory 192620 kb
Host smart-1477d811-9e6e-437b-a9b4-6d59d149582d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181547973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.1181547973
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.2174815779
Short name T211
Test name
Test status
Simulation time 39120298083 ps
CPU time 48.44 seconds
Started Jul 29 04:26:05 PM PDT 24
Finished Jul 29 04:26:53 PM PDT 24
Peak memory 191148 kb
Host smart-a8f35838-a81d-4af2-96ec-34fcc3a44c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174815779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.2174815779
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/152.rv_timer_random.2867806864
Short name T403
Test name
Test status
Simulation time 71477429579 ps
CPU time 69.5 seconds
Started Jul 29 04:25:38 PM PDT 24
Finished Jul 29 04:26:47 PM PDT 24
Peak memory 183184 kb
Host smart-e1edba20-cc59-4e82-a044-6268528a7427
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867806864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.2867806864
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.3663716195
Short name T237
Test name
Test status
Simulation time 56914383133 ps
CPU time 95.24 seconds
Started Jul 29 04:25:43 PM PDT 24
Finished Jul 29 04:27:18 PM PDT 24
Peak memory 191440 kb
Host smart-711ee2c6-358c-4410-bcc6-6c501118c0f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663716195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.3663716195
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.1991056151
Short name T336
Test name
Test status
Simulation time 75289702909 ps
CPU time 385.99 seconds
Started Jul 29 04:25:44 PM PDT 24
Finished Jul 29 04:32:10 PM PDT 24
Peak memory 191440 kb
Host smart-1349c6b1-bfe6-4f31-a356-f47b548a234b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991056151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.1991056151
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.1408026726
Short name T219
Test name
Test status
Simulation time 49128516535 ps
CPU time 94.15 seconds
Started Jul 29 04:25:38 PM PDT 24
Finished Jul 29 04:27:12 PM PDT 24
Peak memory 191376 kb
Host smart-581fef4f-7ced-470b-aaf1-816d8559103c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408026726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.1408026726
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.2226667018
Short name T139
Test name
Test status
Simulation time 235117871317 ps
CPU time 1983.03 seconds
Started Jul 29 04:25:43 PM PDT 24
Finished Jul 29 04:58:47 PM PDT 24
Peak memory 191452 kb
Host smart-614780aa-affb-4764-a1ee-58917d8617e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226667018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.2226667018
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.1018588854
Short name T212
Test name
Test status
Simulation time 110345346237 ps
CPU time 563.07 seconds
Started Jul 29 04:25:44 PM PDT 24
Finished Jul 29 04:35:07 PM PDT 24
Peak memory 191456 kb
Host smart-75f8b73d-d96a-4831-8143-9670536c6155
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018588854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.1018588854
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.2911322033
Short name T230
Test name
Test status
Simulation time 108874493076 ps
CPU time 1203.68 seconds
Started Jul 29 04:26:50 PM PDT 24
Finished Jul 29 04:46:53 PM PDT 24
Peak memory 191144 kb
Host smart-2035d6a2-589a-4cd5-9c20-75e89e6b7674
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911322033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.2911322033
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.1807266760
Short name T290
Test name
Test status
Simulation time 1581032390927 ps
CPU time 810.45 seconds
Started Jul 29 04:26:06 PM PDT 24
Finished Jul 29 04:39:37 PM PDT 24
Peak memory 182968 kb
Host smart-608fa9de-05f1-4e83-8192-8cef6862f118
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807266760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.1807266760
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.2484411283
Short name T371
Test name
Test status
Simulation time 185750121626 ps
CPU time 141.19 seconds
Started Jul 29 04:26:05 PM PDT 24
Finished Jul 29 04:28:27 PM PDT 24
Peak memory 182952 kb
Host smart-235af6cb-9467-4324-8a24-8ae606a8f3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484411283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.2484411283
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.1261982477
Short name T163
Test name
Test status
Simulation time 59013413392 ps
CPU time 306.86 seconds
Started Jul 29 04:21:34 PM PDT 24
Finished Jul 29 04:26:41 PM PDT 24
Peak memory 191436 kb
Host smart-d9ceec68-e28c-4da8-b447-d71e8d74d3c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261982477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.1261982477
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.1679755683
Short name T341
Test name
Test status
Simulation time 23098809150 ps
CPU time 25.6 seconds
Started Jul 29 04:25:37 PM PDT 24
Finished Jul 29 04:26:03 PM PDT 24
Peak memory 191100 kb
Host smart-b339215d-b26b-406a-8ba2-163fc889e012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679755683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.1679755683
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.1280476317
Short name T186
Test name
Test status
Simulation time 635789756558 ps
CPU time 462.97 seconds
Started Jul 29 04:25:41 PM PDT 24
Finished Jul 29 04:33:24 PM PDT 24
Peak memory 191748 kb
Host smart-56628680-27af-4385-8b85-477fa1faecd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280476317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.1280476317
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.1820628334
Short name T292
Test name
Test status
Simulation time 374485049327 ps
CPU time 501 seconds
Started Jul 29 04:25:45 PM PDT 24
Finished Jul 29 04:34:06 PM PDT 24
Peak memory 191552 kb
Host smart-83a9a7af-d149-401b-9e28-d9ae5ae6f800
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820628334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.1820628334
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.230793866
Short name T242
Test name
Test status
Simulation time 105151326760 ps
CPU time 298.74 seconds
Started Jul 29 04:26:54 PM PDT 24
Finished Jul 29 04:31:54 PM PDT 24
Peak memory 189256 kb
Host smart-1799220f-db88-4d6a-8596-003dc19c7981
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230793866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.230793866
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.4202765655
Short name T252
Test name
Test status
Simulation time 687851683670 ps
CPU time 2006.92 seconds
Started Jul 29 04:26:55 PM PDT 24
Finished Jul 29 05:00:22 PM PDT 24
Peak memory 191004 kb
Host smart-54b9b9cb-0778-4d77-ad75-a78c7c14146c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202765655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.4202765655
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.3816588284
Short name T308
Test name
Test status
Simulation time 62233367781 ps
CPU time 45.7 seconds
Started Jul 29 04:26:55 PM PDT 24
Finished Jul 29 04:27:41 PM PDT 24
Peak memory 182452 kb
Host smart-a9489bc6-2629-45bd-b346-2ad74f0e5436
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816588284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.3816588284
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.1195599610
Short name T126
Test name
Test status
Simulation time 17314440318 ps
CPU time 194.71 seconds
Started Jul 29 04:26:54 PM PDT 24
Finished Jul 29 04:30:10 PM PDT 24
Peak memory 180756 kb
Host smart-59a6b6bd-5a02-4674-a0ae-9276d31792ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195599610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.1195599610
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.3146876960
Short name T444
Test name
Test status
Simulation time 89502235069 ps
CPU time 69.57 seconds
Started Jul 29 04:21:57 PM PDT 24
Finished Jul 29 04:23:07 PM PDT 24
Peak memory 183244 kb
Host smart-f5d36853-9334-4186-a834-105beecad421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146876960 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.3146876960
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.1007877885
Short name T228
Test name
Test status
Simulation time 32339459993 ps
CPU time 21.88 seconds
Started Jul 29 04:22:41 PM PDT 24
Finished Jul 29 04:23:03 PM PDT 24
Peak memory 194940 kb
Host smart-a21de251-b1cb-4a3e-b1c1-1b19c289312f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007877885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.1007877885
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.3459713636
Short name T359
Test name
Test status
Simulation time 383106957506 ps
CPU time 491.05 seconds
Started Jul 29 04:25:31 PM PDT 24
Finished Jul 29 04:33:43 PM PDT 24
Peak memory 191456 kb
Host smart-5bf7d3a8-55ee-4e24-8787-f86349c73263
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459713636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.3459713636
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/170.rv_timer_random.1123699048
Short name T115
Test name
Test status
Simulation time 127089214933 ps
CPU time 323.35 seconds
Started Jul 29 04:25:44 PM PDT 24
Finished Jul 29 04:31:08 PM PDT 24
Peak memory 191192 kb
Host smart-58ac87df-20f9-44d4-a2e5-f467af4bc327
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123699048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.1123699048
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.1605682718
Short name T19
Test name
Test status
Simulation time 261436475922 ps
CPU time 142.87 seconds
Started Jul 29 04:25:42 PM PDT 24
Finished Jul 29 04:28:05 PM PDT 24
Peak memory 191384 kb
Host smart-edb178ee-856c-450d-9bf9-d62f3c5e9ebe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605682718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.1605682718
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.3670598870
Short name T201
Test name
Test status
Simulation time 154744986691 ps
CPU time 896.28 seconds
Started Jul 29 04:26:50 PM PDT 24
Finished Jul 29 04:41:47 PM PDT 24
Peak memory 191096 kb
Host smart-58942bc1-a991-4c3a-8752-21343efa5df5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670598870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.3670598870
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.3200837278
Short name T170
Test name
Test status
Simulation time 183143945556 ps
CPU time 568.55 seconds
Started Jul 29 04:25:41 PM PDT 24
Finished Jul 29 04:35:10 PM PDT 24
Peak memory 191740 kb
Host smart-3a329558-630a-4ebf-b166-07e9c4af2809
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200837278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.3200837278
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.2974636018
Short name T159
Test name
Test status
Simulation time 47713475940 ps
CPU time 71.23 seconds
Started Jul 29 04:26:54 PM PDT 24
Finished Jul 29 04:28:07 PM PDT 24
Peak memory 188944 kb
Host smart-fba27de9-310a-4163-b516-e36fec8149ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974636018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.2974636018
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.1092428745
Short name T287
Test name
Test status
Simulation time 118848782689 ps
CPU time 1347.3 seconds
Started Jul 29 04:25:41 PM PDT 24
Finished Jul 29 04:48:08 PM PDT 24
Peak memory 191384 kb
Host smart-047ae226-1dee-42b8-bf0a-6a3e9c1e2ae0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092428745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.1092428745
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.578496387
Short name T326
Test name
Test status
Simulation time 24330360647 ps
CPU time 9.31 seconds
Started Jul 29 04:21:31 PM PDT 24
Finished Jul 29 04:21:40 PM PDT 24
Peak memory 183172 kb
Host smart-e9ee76b4-b6d3-426b-aa70-d8e33d0b765e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578496387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.rv_timer_cfg_update_on_fly.578496387
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.2566829362
Short name T379
Test name
Test status
Simulation time 576350871612 ps
CPU time 207.01 seconds
Started Jul 29 04:25:11 PM PDT 24
Finished Jul 29 04:28:39 PM PDT 24
Peak memory 181228 kb
Host smart-0ce49c96-f6af-4777-84b5-a3813826959c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566829362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.2566829362
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.2047171128
Short name T334
Test name
Test status
Simulation time 69963640342 ps
CPU time 115.56 seconds
Started Jul 29 04:22:27 PM PDT 24
Finished Jul 29 04:24:23 PM PDT 24
Peak memory 191468 kb
Host smart-713ae7b5-c27e-4e30-ad2d-c56006e91cde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047171128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.2047171128
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.3111194843
Short name T409
Test name
Test status
Simulation time 2294344487 ps
CPU time 3.51 seconds
Started Jul 29 04:25:10 PM PDT 24
Finished Jul 29 04:25:13 PM PDT 24
Peak memory 190560 kb
Host smart-bd17d29a-0af4-4147-94c1-fc600f8ae56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111194843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.3111194843
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.726429926
Short name T150
Test name
Test status
Simulation time 1402270556120 ps
CPU time 2623.2 seconds
Started Jul 29 04:21:24 PM PDT 24
Finished Jul 29 05:05:08 PM PDT 24
Peak memory 191468 kb
Host smart-d2add971-af36-44c4-bc5a-51d83ab37029
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726429926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all.
726429926
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/181.rv_timer_random.13305341
Short name T338
Test name
Test status
Simulation time 92100098290 ps
CPU time 45.77 seconds
Started Jul 29 04:25:47 PM PDT 24
Finished Jul 29 04:26:33 PM PDT 24
Peak memory 183224 kb
Host smart-1f394219-696b-468e-8129-a8f5018259f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13305341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.13305341
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.953729627
Short name T356
Test name
Test status
Simulation time 383784568050 ps
CPU time 100.26 seconds
Started Jul 29 04:25:47 PM PDT 24
Finished Jul 29 04:27:28 PM PDT 24
Peak memory 183264 kb
Host smart-2fd6d916-363a-43fa-b42d-01423e189997
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953729627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.953729627
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.3374099326
Short name T319
Test name
Test status
Simulation time 13514143482 ps
CPU time 9.71 seconds
Started Jul 29 04:25:47 PM PDT 24
Finished Jul 29 04:25:57 PM PDT 24
Peak memory 183196 kb
Host smart-bcb8c3d7-097f-41d7-9108-0ffa8850f87c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374099326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.3374099326
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.2248897755
Short name T339
Test name
Test status
Simulation time 237333547869 ps
CPU time 570.16 seconds
Started Jul 29 04:25:49 PM PDT 24
Finished Jul 29 04:35:20 PM PDT 24
Peak memory 191444 kb
Host smart-096fdddd-7db8-4f70-aa8f-fbe106e04a06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248897755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.2248897755
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.2760591878
Short name T145
Test name
Test status
Simulation time 760667710562 ps
CPU time 1610.49 seconds
Started Jul 29 04:25:45 PM PDT 24
Finished Jul 29 04:52:35 PM PDT 24
Peak memory 191384 kb
Host smart-376e9613-2f0d-4eb6-9578-09ee6cb889b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760591878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.2760591878
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.588025288
Short name T417
Test name
Test status
Simulation time 368516294577 ps
CPU time 198.03 seconds
Started Jul 29 04:25:46 PM PDT 24
Finished Jul 29 04:29:04 PM PDT 24
Peak memory 191388 kb
Host smart-da7093f4-6c4c-4c77-b32c-44b6f8750026
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588025288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.588025288
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.3380720185
Short name T439
Test name
Test status
Simulation time 497047124926 ps
CPU time 97.72 seconds
Started Jul 29 04:25:12 PM PDT 24
Finished Jul 29 04:26:50 PM PDT 24
Peak memory 182792 kb
Host smart-6fe8bf46-ec58-4ed3-a309-cb0836da4dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380720185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.3380720185
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.10036051
Short name T82
Test name
Test status
Simulation time 206538708890 ps
CPU time 191.89 seconds
Started Jul 29 04:21:31 PM PDT 24
Finished Jul 29 04:24:43 PM PDT 24
Peak memory 191480 kb
Host smart-f49dd84e-7473-4736-a6f6-4168a1754dbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10036051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.10036051
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.1392104452
Short name T2
Test name
Test status
Simulation time 58527811999 ps
CPU time 47.54 seconds
Started Jul 29 04:25:10 PM PDT 24
Finished Jul 29 04:25:57 PM PDT 24
Peak memory 190564 kb
Host smart-c700939d-3a37-42b8-ac99-5ace875daac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392104452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.1392104452
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.4059048554
Short name T24
Test name
Test status
Simulation time 89884077584 ps
CPU time 41.09 seconds
Started Jul 29 04:25:54 PM PDT 24
Finished Jul 29 04:26:36 PM PDT 24
Peak memory 183208 kb
Host smart-e0fdb1c1-2feb-47eb-a19f-2cdfddda72ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059048554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.4059048554
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.3672376456
Short name T402
Test name
Test status
Simulation time 48539344143 ps
CPU time 80.33 seconds
Started Jul 29 04:25:59 PM PDT 24
Finished Jul 29 04:27:20 PM PDT 24
Peak memory 191548 kb
Host smart-78aa9bdd-611d-4f4a-a390-e6c4ae35233e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672376456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.3672376456
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.1354469824
Short name T116
Test name
Test status
Simulation time 89957324349 ps
CPU time 148.72 seconds
Started Jul 29 04:25:54 PM PDT 24
Finished Jul 29 04:28:23 PM PDT 24
Peak memory 191400 kb
Host smart-c3dd1091-b306-4796-8561-c0939f00fad6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354469824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.1354469824
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.2030728136
Short name T419
Test name
Test status
Simulation time 18029789648 ps
CPU time 135.83 seconds
Started Jul 29 04:25:51 PM PDT 24
Finished Jul 29 04:28:07 PM PDT 24
Peak memory 183208 kb
Host smart-ed29fb63-7685-4119-aefd-534b594b3725
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030728136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.2030728136
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.925830604
Short name T132
Test name
Test status
Simulation time 208941757229 ps
CPU time 1701.02 seconds
Started Jul 29 04:27:05 PM PDT 24
Finished Jul 29 04:55:26 PM PDT 24
Peak memory 191408 kb
Host smart-6cfb8a3b-a5a1-4219-aa7c-0f4dd5a31cba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925830604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.925830604
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.1514121674
Short name T192
Test name
Test status
Simulation time 181793197047 ps
CPU time 268.92 seconds
Started Jul 29 04:25:50 PM PDT 24
Finished Jul 29 04:30:19 PM PDT 24
Peak memory 191456 kb
Host smart-2f09215f-0ba0-4367-ad64-db0fcbc59fa9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514121674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.1514121674
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.2834556854
Short name T181
Test name
Test status
Simulation time 1626889728343 ps
CPU time 1490.39 seconds
Started Jul 29 04:25:54 PM PDT 24
Finished Jul 29 04:50:44 PM PDT 24
Peak memory 193952 kb
Host smart-d05e0432-0527-4f8b-8c77-f71a42d7f893
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834556854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.2834556854
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.1008181087
Short name T232
Test name
Test status
Simulation time 113149529781 ps
CPU time 1624.35 seconds
Started Jul 29 04:25:54 PM PDT 24
Finished Jul 29 04:52:59 PM PDT 24
Peak memory 191400 kb
Host smart-efdf6b34-fbd0-4744-a68e-0d0491f00226
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008181087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.1008181087
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.2451002649
Short name T164
Test name
Test status
Simulation time 902843493321 ps
CPU time 865.62 seconds
Started Jul 29 04:26:23 PM PDT 24
Finished Jul 29 04:40:49 PM PDT 24
Peak memory 183244 kb
Host smart-4424ccee-3962-48b6-95df-9b32e6582662
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451002649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.2451002649
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.1732992368
Short name T415
Test name
Test status
Simulation time 88424936018 ps
CPU time 139.5 seconds
Started Jul 29 04:20:21 PM PDT 24
Finished Jul 29 04:22:41 PM PDT 24
Peak memory 183252 kb
Host smart-a0532a84-f12a-495c-a0fc-c20b0b68c606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732992368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.1732992368
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.2861837074
Short name T261
Test name
Test status
Simulation time 162845227763 ps
CPU time 88.41 seconds
Started Jul 29 04:25:01 PM PDT 24
Finished Jul 29 04:26:30 PM PDT 24
Peak memory 194368 kb
Host smart-f6719079-a823-489e-94bb-3c2876eb50c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861837074 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.2861837074
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.1209742642
Short name T15
Test name
Test status
Simulation time 90467166 ps
CPU time 0.9 seconds
Started Jul 29 04:25:44 PM PDT 24
Finished Jul 29 04:25:45 PM PDT 24
Peak memory 216280 kb
Host smart-677aed25-6508-449d-bffd-7ba77b360aac
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209742642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.1209742642
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.1055689415
Short name T194
Test name
Test status
Simulation time 319545692544 ps
CPU time 282.04 seconds
Started Jul 29 04:22:03 PM PDT 24
Finished Jul 29 04:26:45 PM PDT 24
Peak memory 183240 kb
Host smart-cd301736-6ad6-4a57-8716-be05e0589169
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055689415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.1055689415
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.695880447
Short name T81
Test name
Test status
Simulation time 167602736194 ps
CPU time 64.87 seconds
Started Jul 29 04:21:32 PM PDT 24
Finished Jul 29 04:22:38 PM PDT 24
Peak memory 181564 kb
Host smart-adb51a73-6230-48ef-874b-272248c33840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695880447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.695880447
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.3484478085
Short name T312
Test name
Test status
Simulation time 323079931022 ps
CPU time 415.63 seconds
Started Jul 29 04:25:12 PM PDT 24
Finished Jul 29 04:32:08 PM PDT 24
Peak memory 190992 kb
Host smart-bf79a818-bbc3-4897-9468-42524960b8d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484478085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.3484478085
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.3332775071
Short name T395
Test name
Test status
Simulation time 24908569149 ps
CPU time 14.72 seconds
Started Jul 29 04:25:11 PM PDT 24
Finished Jul 29 04:25:26 PM PDT 24
Peak memory 180916 kb
Host smart-2734dde6-67ab-4ef4-919e-23be7ec1c1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332775071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.3332775071
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.3835033440
Short name T378
Test name
Test status
Simulation time 21084763 ps
CPU time 0.55 seconds
Started Jul 29 04:24:11 PM PDT 24
Finished Jul 29 04:24:12 PM PDT 24
Peak memory 182928 kb
Host smart-22068054-4831-4af0-b2c5-0ff2b61d4c2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835033440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.3835033440
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.1201326526
Short name T330
Test name
Test status
Simulation time 692684618559 ps
CPU time 600.21 seconds
Started Jul 29 04:23:53 PM PDT 24
Finished Jul 29 04:33:53 PM PDT 24
Peak memory 183244 kb
Host smart-7747f611-21be-41b9-ab4b-3f53440ccc97
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201326526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.1201326526
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.3681504425
Short name T368
Test name
Test status
Simulation time 466095316842 ps
CPU time 126.04 seconds
Started Jul 29 04:25:25 PM PDT 24
Finished Jul 29 04:27:32 PM PDT 24
Peak memory 183184 kb
Host smart-64e0262b-c24b-4fbf-8c03-e29f32f52c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681504425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.3681504425
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.2488368238
Short name T258
Test name
Test status
Simulation time 33343518340 ps
CPU time 61.22 seconds
Started Jul 29 04:25:50 PM PDT 24
Finished Jul 29 04:26:51 PM PDT 24
Peak memory 183236 kb
Host smart-a8d8a4c8-98a1-4bd1-bee7-a7d1ea05698d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488368238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.2488368238
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.886044988
Short name T307
Test name
Test status
Simulation time 12558313844 ps
CPU time 12.45 seconds
Started Jul 29 04:23:03 PM PDT 24
Finished Jul 29 04:23:15 PM PDT 24
Peak memory 183368 kb
Host smart-a8acb292-900a-465a-ab3b-cc8e52440518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886044988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.886044988
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.3955302075
Short name T383
Test name
Test status
Simulation time 343810018886 ps
CPU time 493.46 seconds
Started Jul 29 04:25:03 PM PDT 24
Finished Jul 29 04:33:16 PM PDT 24
Peak memory 182244 kb
Host smart-d9ff5515-c1d1-4005-9841-ae894353045a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955302075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.3955302075
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.1201836415
Short name T123
Test name
Test status
Simulation time 296830012226 ps
CPU time 227 seconds
Started Jul 29 04:25:31 PM PDT 24
Finished Jul 29 04:29:19 PM PDT 24
Peak memory 182912 kb
Host smart-ac793e92-07d0-4feb-a76f-a71f3ed503ee
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201836415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.1201836415
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.3546485819
Short name T386
Test name
Test status
Simulation time 704866009649 ps
CPU time 260.36 seconds
Started Jul 29 04:25:12 PM PDT 24
Finished Jul 29 04:29:32 PM PDT 24
Peak memory 183192 kb
Host smart-25d6199f-ef1d-456c-859f-bd562cd88a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546485819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.3546485819
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.1385122304
Short name T437
Test name
Test status
Simulation time 84769873 ps
CPU time 0.65 seconds
Started Jul 29 04:25:26 PM PDT 24
Finished Jul 29 04:25:27 PM PDT 24
Peak memory 182740 kb
Host smart-266d72cd-c8cd-4e0c-938d-a5cff642661d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385122304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.1385122304
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.398119115
Short name T295
Test name
Test status
Simulation time 97866637407 ps
CPU time 164.12 seconds
Started Jul 29 04:25:25 PM PDT 24
Finished Jul 29 04:28:10 PM PDT 24
Peak memory 182988 kb
Host smart-f86cc85e-3f25-4b24-9084-bee324af02a2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398119115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.rv_timer_cfg_update_on_fly.398119115
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.2704155276
Short name T370
Test name
Test status
Simulation time 191105606680 ps
CPU time 196.1 seconds
Started Jul 29 04:25:22 PM PDT 24
Finished Jul 29 04:28:39 PM PDT 24
Peak memory 182260 kb
Host smart-7a02c998-5b68-4639-be82-689472059491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704155276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.2704155276
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.389262686
Short name T196
Test name
Test status
Simulation time 159064659330 ps
CPU time 1422.43 seconds
Started Jul 29 04:21:41 PM PDT 24
Finished Jul 29 04:45:24 PM PDT 24
Peak memory 191480 kb
Host smart-ccb1b6e2-bc75-4172-9ca0-b4458c226d60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389262686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.389262686
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.4073622927
Short name T84
Test name
Test status
Simulation time 61589382008 ps
CPU time 91.62 seconds
Started Jul 29 04:25:22 PM PDT 24
Finished Jul 29 04:26:54 PM PDT 24
Peak memory 182268 kb
Host smart-4ed90826-13b2-499e-9ffb-eddc33f72eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073622927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.4073622927
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.1184406114
Short name T441
Test name
Test status
Simulation time 551652386057 ps
CPU time 392.71 seconds
Started Jul 29 04:24:11 PM PDT 24
Finished Jul 29 04:30:44 PM PDT 24
Peak memory 191472 kb
Host smart-d0ecfc04-8a56-48a5-be74-6ee4c230c091
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184406114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.1184406114
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.3121105488
Short name T37
Test name
Test status
Simulation time 74730500002 ps
CPU time 463.54 seconds
Started Jul 29 04:24:52 PM PDT 24
Finished Jul 29 04:32:35 PM PDT 24
Peak memory 205540 kb
Host smart-82d76de0-2cda-48e6-86ee-c6696f1119f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121105488 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_reset.3121105488
Directory /workspace/23.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.1389330497
Short name T234
Test name
Test status
Simulation time 274842266422 ps
CPU time 422.32 seconds
Started Jul 29 04:25:19 PM PDT 24
Finished Jul 29 04:32:21 PM PDT 24
Peak memory 183012 kb
Host smart-149860ce-44f8-41e2-b77c-f4c98a0cca1b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389330497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.1389330497
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.1282067638
Short name T428
Test name
Test status
Simulation time 129960335291 ps
CPU time 198.34 seconds
Started Jul 29 04:25:41 PM PDT 24
Finished Jul 29 04:28:59 PM PDT 24
Peak memory 183200 kb
Host smart-799a259e-fcb5-457d-b89d-4767e24f4cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282067638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.1282067638
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.2383433651
Short name T274
Test name
Test status
Simulation time 432564806501 ps
CPU time 620.58 seconds
Started Jul 29 04:24:51 PM PDT 24
Finished Jul 29 04:35:12 PM PDT 24
Peak memory 190528 kb
Host smart-b674d922-bea8-46ae-b14d-a37ac7922276
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383433651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.2383433651
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.3662297379
Short name T281
Test name
Test status
Simulation time 507604197444 ps
CPU time 748.7 seconds
Started Jul 29 04:25:01 PM PDT 24
Finished Jul 29 04:37:30 PM PDT 24
Peak memory 193684 kb
Host smart-c7a9e326-c947-412c-9c3b-5cf930dd33cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662297379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.3662297379
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.2611278238
Short name T241
Test name
Test status
Simulation time 389681334563 ps
CPU time 267.7 seconds
Started Jul 29 04:25:43 PM PDT 24
Finished Jul 29 04:30:11 PM PDT 24
Peak memory 183252 kb
Host smart-aa18dec1-6283-449e-a77f-4c21b4628299
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611278238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.2611278238
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.876435738
Short name T374
Test name
Test status
Simulation time 80249342088 ps
CPU time 118.45 seconds
Started Jul 29 04:25:29 PM PDT 24
Finished Jul 29 04:27:28 PM PDT 24
Peak memory 183244 kb
Host smart-25e03bc9-7dee-42b7-a7a1-df576a60c46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876435738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.876435738
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.3599233611
Short name T102
Test name
Test status
Simulation time 290857693389 ps
CPU time 508.81 seconds
Started Jul 29 04:25:43 PM PDT 24
Finished Jul 29 04:34:12 PM PDT 24
Peak memory 183196 kb
Host smart-75933817-1991-4e27-9534-db7b94d4a415
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599233611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.3599233611
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.292989819
Short name T188
Test name
Test status
Simulation time 555671654203 ps
CPU time 186.66 seconds
Started Jul 29 04:21:44 PM PDT 24
Finished Jul 29 04:24:51 PM PDT 24
Peak memory 191448 kb
Host smart-a945f955-9032-44b5-a9a5-162418490422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292989819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.292989819
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.2244627667
Short name T328
Test name
Test status
Simulation time 105824136214 ps
CPU time 181.92 seconds
Started Jul 29 04:25:09 PM PDT 24
Finished Jul 29 04:28:12 PM PDT 24
Peak memory 182164 kb
Host smart-26cbf154-c53d-4804-8dbe-290a66c5a5bc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244627667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.2244627667
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.1235239611
Short name T364
Test name
Test status
Simulation time 76552169718 ps
CPU time 101.84 seconds
Started Jul 29 04:25:04 PM PDT 24
Finished Jul 29 04:26:46 PM PDT 24
Peak memory 182940 kb
Host smart-5f6e7392-d2be-4378-9a03-ea484d38cb09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235239611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.1235239611
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.3330576392
Short name T168
Test name
Test status
Simulation time 695978031139 ps
CPU time 1263.78 seconds
Started Jul 29 04:25:26 PM PDT 24
Finished Jul 29 04:46:30 PM PDT 24
Peak memory 190892 kb
Host smart-ef8c8bc4-0f51-4fa7-86cd-4ccef2c8d797
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330576392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.3330576392
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.842837723
Short name T448
Test name
Test status
Simulation time 96739364558 ps
CPU time 125.91 seconds
Started Jul 29 04:25:05 PM PDT 24
Finished Jul 29 04:27:11 PM PDT 24
Peak memory 194776 kb
Host smart-f2095334-312f-4644-be2d-7715217f10e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842837723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all.
842837723
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.2285920788
Short name T285
Test name
Test status
Simulation time 919522605004 ps
CPU time 443.7 seconds
Started Jul 29 04:21:57 PM PDT 24
Finished Jul 29 04:29:21 PM PDT 24
Peak memory 183224 kb
Host smart-8ad4ef33-140a-45ec-ab24-26472dda5765
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285920788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.2285920788
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.3255123622
Short name T366
Test name
Test status
Simulation time 128494171858 ps
CPU time 141.26 seconds
Started Jul 29 04:21:57 PM PDT 24
Finished Jul 29 04:24:18 PM PDT 24
Peak memory 183244 kb
Host smart-1704da8f-61c9-4065-95aa-8e4fe9349a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255123622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.3255123622
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.3437067965
Short name T435
Test name
Test status
Simulation time 27183992052 ps
CPU time 236.59 seconds
Started Jul 29 04:21:59 PM PDT 24
Finished Jul 29 04:25:55 PM PDT 24
Peak memory 183548 kb
Host smart-90c6321f-ee47-4f5d-8a91-bed9af2d71f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437067965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.3437067965
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.1340227558
Short name T250
Test name
Test status
Simulation time 266097522692 ps
CPU time 91.26 seconds
Started Jul 29 04:25:26 PM PDT 24
Finished Jul 29 04:26:58 PM PDT 24
Peak memory 182928 kb
Host smart-8bb8be8a-a721-4dbe-850b-b4ea5754b460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340227558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.1340227558
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all_with_rand_reset.3983979752
Short name T85
Test name
Test status
Simulation time 130310329820 ps
CPU time 379.14 seconds
Started Jul 29 04:25:25 PM PDT 24
Finished Jul 29 04:31:45 PM PDT 24
Peak memory 206064 kb
Host smart-022d11c1-72ad-4b41-8079-a94df2f80639
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983979752 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all_with_rand_reset.3983979752
Directory /workspace/28.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.203885133
Short name T380
Test name
Test status
Simulation time 340074260757 ps
CPU time 44.39 seconds
Started Jul 29 04:25:26 PM PDT 24
Finished Jul 29 04:26:11 PM PDT 24
Peak memory 182928 kb
Host smart-28ea1f15-3890-42eb-8a82-80269a3ffca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203885133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.203885133
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.3353800214
Short name T214
Test name
Test status
Simulation time 776212855907 ps
CPU time 3238.78 seconds
Started Jul 29 04:25:26 PM PDT 24
Finished Jul 29 05:19:25 PM PDT 24
Peak memory 190620 kb
Host smart-e1279b0b-2232-4889-81da-814aa352740c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353800214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.3353800214
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.3275474223
Short name T218
Test name
Test status
Simulation time 142427072950 ps
CPU time 229.63 seconds
Started Jul 29 04:22:34 PM PDT 24
Finished Jul 29 04:26:24 PM PDT 24
Peak memory 191528 kb
Host smart-eef07015-ebc0-44fe-93a5-a0f02219da89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275474223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.3275474223
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.3623740562
Short name T5
Test name
Test status
Simulation time 142300080010 ps
CPU time 203.45 seconds
Started Jul 29 04:26:55 PM PDT 24
Finished Jul 29 04:30:19 PM PDT 24
Peak memory 182740 kb
Host smart-5d850878-ff91-4bd6-9061-f7c6c96110fd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623740562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.3623740562
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.2774443675
Short name T421
Test name
Test status
Simulation time 119172246840 ps
CPU time 175.2 seconds
Started Jul 29 04:21:25 PM PDT 24
Finished Jul 29 04:24:20 PM PDT 24
Peak memory 183372 kb
Host smart-365c4af2-bf09-42a3-bccc-6236939f5f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774443675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.2774443675
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.230904950
Short name T187
Test name
Test status
Simulation time 60870173043 ps
CPU time 26.6 seconds
Started Jul 29 04:22:18 PM PDT 24
Finished Jul 29 04:22:45 PM PDT 24
Peak memory 183244 kb
Host smart-84d84cad-faf0-472c-88f3-61b315d0f142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230904950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.230904950
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.1438988139
Short name T17
Test name
Test status
Simulation time 259096085 ps
CPU time 0.9 seconds
Started Jul 29 04:20:33 PM PDT 24
Finished Jul 29 04:20:34 PM PDT 24
Peak memory 213928 kb
Host smart-72bce51b-a2b6-4b87-a894-985d581497ed
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438988139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.1438988139
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.2501819486
Short name T202
Test name
Test status
Simulation time 217800156348 ps
CPU time 338.17 seconds
Started Jul 29 04:25:30 PM PDT 24
Finished Jul 29 04:31:09 PM PDT 24
Peak memory 183184 kb
Host smart-7962c217-8769-42c0-a9af-5b5df3c8667b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501819486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.2501819486
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.3575597798
Short name T377
Test name
Test status
Simulation time 131613119983 ps
CPU time 170.05 seconds
Started Jul 29 04:21:57 PM PDT 24
Finished Jul 29 04:24:47 PM PDT 24
Peak memory 183252 kb
Host smart-61574630-ffc5-4ffe-9281-3aef170ad0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575597798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.3575597798
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.1074486549
Short name T173
Test name
Test status
Simulation time 1092625500464 ps
CPU time 583.48 seconds
Started Jul 29 04:22:00 PM PDT 24
Finished Jul 29 04:31:44 PM PDT 24
Peak memory 183420 kb
Host smart-62add2ba-8b77-4aa3-95d3-6238e89fb00b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074486549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.1074486549
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.2801248295
Short name T376
Test name
Test status
Simulation time 21218185383 ps
CPU time 15.77 seconds
Started Jul 29 04:25:23 PM PDT 24
Finished Jul 29 04:25:39 PM PDT 24
Peak memory 182208 kb
Host smart-a0ddf878-fe2c-461a-a96f-9a396ebb724a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801248295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.2801248295
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.1656908625
Short name T125
Test name
Test status
Simulation time 42090524985 ps
CPU time 57.77 seconds
Started Jul 29 04:22:10 PM PDT 24
Finished Jul 29 04:23:08 PM PDT 24
Peak memory 191456 kb
Host smart-59254cc1-e3a4-49b8-b0c6-b0597ffc5bc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656908625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.1656908625
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.586592004
Short name T314
Test name
Test status
Simulation time 4445372813 ps
CPU time 8.75 seconds
Started Jul 29 04:22:00 PM PDT 24
Finished Jul 29 04:22:09 PM PDT 24
Peak memory 183248 kb
Host smart-09f8fbd2-c838-44d0-9eb1-213c191120b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586592004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.586592004
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.3212611024
Short name T57
Test name
Test status
Simulation time 375136964649 ps
CPU time 390.35 seconds
Started Jul 29 04:25:31 PM PDT 24
Finished Jul 29 04:32:02 PM PDT 24
Peak memory 191100 kb
Host smart-ce0ab700-71db-473e-90e3-01365523a5d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212611024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.3212611024
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.3200113540
Short name T216
Test name
Test status
Simulation time 521188063200 ps
CPU time 252.96 seconds
Started Jul 29 04:22:09 PM PDT 24
Finished Jul 29 04:26:22 PM PDT 24
Peak memory 183268 kb
Host smart-3a58e0c1-16a4-454b-99ef-0196d0f076be
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200113540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.3200113540
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.2916132329
Short name T424
Test name
Test status
Simulation time 51999099914 ps
CPU time 74.55 seconds
Started Jul 29 04:25:27 PM PDT 24
Finished Jul 29 04:26:41 PM PDT 24
Peak memory 183000 kb
Host smart-2536e79a-1fb7-445c-bd3d-e13326586bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916132329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.2916132329
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.2065185127
Short name T342
Test name
Test status
Simulation time 218249032172 ps
CPU time 107.85 seconds
Started Jul 29 04:25:31 PM PDT 24
Finished Jul 29 04:27:19 PM PDT 24
Peak memory 191096 kb
Host smart-e035a308-420d-439f-ab4c-81e311cde2b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065185127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.2065185127
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.3098185070
Short name T325
Test name
Test status
Simulation time 639952508721 ps
CPU time 110.15 seconds
Started Jul 29 04:25:25 PM PDT 24
Finished Jul 29 04:27:15 PM PDT 24
Peak memory 191200 kb
Host smart-59a6bc27-0e61-450e-b017-9e4342d9a609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098185070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.3098185070
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.1073961294
Short name T61
Test name
Test status
Simulation time 22815833 ps
CPU time 0.66 seconds
Started Jul 29 04:25:26 PM PDT 24
Finished Jul 29 04:25:27 PM PDT 24
Peak memory 181860 kb
Host smart-420cad73-62e9-4cce-b4b9-96ced4cc111d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073961294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.1073961294
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.723019609
Short name T204
Test name
Test status
Simulation time 167302929984 ps
CPU time 79.02 seconds
Started Jul 29 04:25:37 PM PDT 24
Finished Jul 29 04:26:56 PM PDT 24
Peak memory 182892 kb
Host smart-f2a358f5-13fb-4d17-8e5a-32e9af25e7d7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723019609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.rv_timer_cfg_update_on_fly.723019609
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.2307339610
Short name T405
Test name
Test status
Simulation time 2659425263 ps
CPU time 3.94 seconds
Started Jul 29 04:25:32 PM PDT 24
Finished Jul 29 04:25:37 PM PDT 24
Peak memory 183040 kb
Host smart-49b626b1-a451-4d5d-ba6a-f57197852685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307339610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.2307339610
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.1240663222
Short name T332
Test name
Test status
Simulation time 62888345008 ps
CPU time 238.61 seconds
Started Jul 29 04:25:37 PM PDT 24
Finished Jul 29 04:29:36 PM PDT 24
Peak memory 182916 kb
Host smart-9a5f456d-47d7-4311-89c3-b203029a7725
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240663222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.1240663222
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.3048085296
Short name T406
Test name
Test status
Simulation time 170275358 ps
CPU time 0.84 seconds
Started Jul 29 04:25:31 PM PDT 24
Finished Jul 29 04:25:32 PM PDT 24
Peak memory 182700 kb
Host smart-bba9039b-89e3-4054-a69b-1df30dcbb743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048085296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.3048085296
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.3380954276
Short name T245
Test name
Test status
Simulation time 80989186703 ps
CPU time 203.91 seconds
Started Jul 29 04:25:31 PM PDT 24
Finished Jul 29 04:28:55 PM PDT 24
Peak memory 194708 kb
Host smart-6dec495b-ae59-4ab8-b8b7-bc0a02109a22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380954276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.3380954276
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.1254022963
Short name T149
Test name
Test status
Simulation time 412296227717 ps
CPU time 362.82 seconds
Started Jul 29 04:25:31 PM PDT 24
Finished Jul 29 04:31:34 PM PDT 24
Peak memory 183224 kb
Host smart-834830ae-55d3-40d1-8d51-c94abfdb0091
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254022963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.1254022963
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.4170183906
Short name T390
Test name
Test status
Simulation time 93454905876 ps
CPU time 73.87 seconds
Started Jul 29 04:22:21 PM PDT 24
Finished Jul 29 04:23:35 PM PDT 24
Peak memory 183280 kb
Host smart-fa614afd-5ce7-4200-9f0f-b545f8dbada4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170183906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.4170183906
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.3204747887
Short name T25
Test name
Test status
Simulation time 130588055151 ps
CPU time 59.99 seconds
Started Jul 29 04:25:36 PM PDT 24
Finished Jul 29 04:26:36 PM PDT 24
Peak memory 191116 kb
Host smart-8eff9807-5bd9-4a7b-9ef9-602cddf45063
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204747887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.3204747887
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.2042482373
Short name T414
Test name
Test status
Simulation time 18633757386 ps
CPU time 8.36 seconds
Started Jul 29 04:25:31 PM PDT 24
Finished Jul 29 04:25:40 PM PDT 24
Peak memory 182828 kb
Host smart-635a7eaf-7f91-4567-a60d-89e78d15c6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042482373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.2042482373
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.3810504670
Short name T185
Test name
Test status
Simulation time 1678825674798 ps
CPU time 553.95 seconds
Started Jul 29 04:22:23 PM PDT 24
Finished Jul 29 04:31:37 PM PDT 24
Peak memory 191500 kb
Host smart-352bbf79-2a70-44e8-bfd8-660d4e69498a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810504670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.3810504670
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all_with_rand_reset.760536437
Short name T35
Test name
Test status
Simulation time 16658661743 ps
CPU time 123.91 seconds
Started Jul 29 04:25:32 PM PDT 24
Finished Jul 29 04:27:36 PM PDT 24
Peak memory 197968 kb
Host smart-507fcd29-ff6c-462b-8ccf-b9d7a56cf211
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760536437 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all_with_rand_reset.760536437
Directory /workspace/34.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.2896366601
Short name T27
Test name
Test status
Simulation time 259738580646 ps
CPU time 220.04 seconds
Started Jul 29 04:25:13 PM PDT 24
Finished Jul 29 04:28:53 PM PDT 24
Peak memory 183224 kb
Host smart-1c813e64-cbb6-4f2c-9006-ab3f507dc9f3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896366601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.2896366601
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.3459903708
Short name T420
Test name
Test status
Simulation time 132178426016 ps
CPU time 95.41 seconds
Started Jul 29 04:23:54 PM PDT 24
Finished Jul 29 04:25:30 PM PDT 24
Peak memory 183260 kb
Host smart-2360025f-c758-4226-9f1d-113fb63d2f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459903708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.3459903708
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.3859395705
Short name T191
Test name
Test status
Simulation time 180650629915 ps
CPU time 298.34 seconds
Started Jul 29 04:25:45 PM PDT 24
Finished Jul 29 04:30:44 PM PDT 24
Peak memory 191168 kb
Host smart-f51198e4-c265-48ec-b77e-7a9af7fe9c9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859395705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.3859395705
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.2598803285
Short name T255
Test name
Test status
Simulation time 113520245935 ps
CPU time 55.55 seconds
Started Jul 29 04:23:44 PM PDT 24
Finished Jul 29 04:24:40 PM PDT 24
Peak memory 195276 kb
Host smart-4105a26c-85b0-4bf0-a32d-bc4a6596586d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598803285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.2598803285
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.2351750442
Short name T59
Test name
Test status
Simulation time 65564035 ps
CPU time 0.61 seconds
Started Jul 29 04:25:13 PM PDT 24
Finished Jul 29 04:25:13 PM PDT 24
Peak memory 183000 kb
Host smart-24398800-d71d-44ec-8ba4-67c9e2ae30e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351750442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.2351750442
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.1357476328
Short name T352
Test name
Test status
Simulation time 2325575748888 ps
CPU time 653.58 seconds
Started Jul 29 04:25:47 PM PDT 24
Finished Jul 29 04:36:41 PM PDT 24
Peak memory 183020 kb
Host smart-98689c92-d20a-4a3a-840c-ef770ec128eb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357476328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.1357476328
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.2589233538
Short name T442
Test name
Test status
Simulation time 32629788210 ps
CPU time 45.45 seconds
Started Jul 29 04:25:18 PM PDT 24
Finished Jul 29 04:26:04 PM PDT 24
Peak memory 183208 kb
Host smart-a0871fb3-0ca2-40f9-b57d-ad0eb2847e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589233538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.2589233538
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.4040932512
Short name T351
Test name
Test status
Simulation time 97255146436 ps
CPU time 96.17 seconds
Started Jul 29 04:25:46 PM PDT 24
Finished Jul 29 04:27:23 PM PDT 24
Peak memory 181708 kb
Host smart-81fb2388-4740-4b86-801b-2c842e4128d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040932512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.4040932512
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.3324207040
Short name T413
Test name
Test status
Simulation time 2239441877 ps
CPU time 1.12 seconds
Started Jul 29 04:22:32 PM PDT 24
Finished Jul 29 04:22:33 PM PDT 24
Peak memory 194032 kb
Host smart-84007866-af51-4db3-850f-abaca74ed37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324207040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.3324207040
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.1284576728
Short name T21
Test name
Test status
Simulation time 415550451545 ps
CPU time 512.1 seconds
Started Jul 29 04:25:21 PM PDT 24
Finished Jul 29 04:33:54 PM PDT 24
Peak memory 182408 kb
Host smart-c1a352f5-563b-4463-9db5-b8ce30804b97
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284576728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.1284576728
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.3393383791
Short name T422
Test name
Test status
Simulation time 334899155317 ps
CPU time 244.82 seconds
Started Jul 29 04:25:37 PM PDT 24
Finished Jul 29 04:29:42 PM PDT 24
Peak memory 182916 kb
Host smart-2c2dff90-8514-4287-ac2d-d9aa321e8aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393383791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.3393383791
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.870312282
Short name T306
Test name
Test status
Simulation time 340852490513 ps
CPU time 141.65 seconds
Started Jul 29 04:25:32 PM PDT 24
Finished Jul 29 04:27:54 PM PDT 24
Peak memory 191416 kb
Host smart-c1f52577-4aea-4d14-bdc8-1b948a2995fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870312282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.870312282
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.3396588846
Short name T388
Test name
Test status
Simulation time 138683650 ps
CPU time 0.8 seconds
Started Jul 29 04:22:31 PM PDT 24
Finished Jul 29 04:22:32 PM PDT 24
Peak memory 183056 kb
Host smart-7969de07-2d25-45ea-a069-a40bb8d1e3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396588846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.3396588846
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.3298158603
Short name T58
Test name
Test status
Simulation time 1335542713087 ps
CPU time 682.51 seconds
Started Jul 29 04:22:33 PM PDT 24
Finished Jul 29 04:33:56 PM PDT 24
Peak memory 196328 kb
Host smart-74a947e9-b88e-4843-867d-5d0aa64e930e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298158603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.3298158603
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.1560332058
Short name T224
Test name
Test status
Simulation time 1127116642666 ps
CPU time 559.97 seconds
Started Jul 29 04:25:45 PM PDT 24
Finished Jul 29 04:35:05 PM PDT 24
Peak memory 182956 kb
Host smart-3ed884fc-1402-4a12-a941-e4015db6b0fc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560332058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.1560332058
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.1037443566
Short name T382
Test name
Test status
Simulation time 555577309395 ps
CPU time 220.71 seconds
Started Jul 29 04:25:56 PM PDT 24
Finished Jul 29 04:29:37 PM PDT 24
Peak memory 182988 kb
Host smart-4553d1b3-33ba-4ea0-90b9-b32afecfbfd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037443566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.1037443566
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.2352053607
Short name T129
Test name
Test status
Simulation time 44729399893 ps
CPU time 76.83 seconds
Started Jul 29 04:25:42 PM PDT 24
Finished Jul 29 04:26:59 PM PDT 24
Peak memory 191424 kb
Host smart-4e32776a-0fa1-4901-b1f7-92759761c4af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352053607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.2352053607
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.4020699084
Short name T392
Test name
Test status
Simulation time 138236215825 ps
CPU time 195.82 seconds
Started Jul 29 04:25:42 PM PDT 24
Finished Jul 29 04:28:58 PM PDT 24
Peak memory 191420 kb
Host smart-c37f508f-22e8-4c20-a65a-94fcea0f57be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020699084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.4020699084
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.2827495151
Short name T263
Test name
Test status
Simulation time 26442402558 ps
CPU time 39.32 seconds
Started Jul 29 04:22:35 PM PDT 24
Finished Jul 29 04:23:14 PM PDT 24
Peak memory 183256 kb
Host smart-ba4dc90e-885d-490f-9aa2-e96770d57e38
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827495151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.2827495151
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.3747640723
Short name T411
Test name
Test status
Simulation time 281420752934 ps
CPU time 125.4 seconds
Started Jul 29 04:25:35 PM PDT 24
Finished Jul 29 04:27:41 PM PDT 24
Peak memory 182412 kb
Host smart-8c249962-8a92-454e-9651-2a5bc4af6a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747640723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.3747640723
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.4285898411
Short name T117
Test name
Test status
Simulation time 45805540263 ps
CPU time 73.3 seconds
Started Jul 29 04:22:37 PM PDT 24
Finished Jul 29 04:23:51 PM PDT 24
Peak memory 191460 kb
Host smart-3f67e594-f86d-4826-8893-ea403cfcfc6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285898411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.4285898411
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.978513544
Short name T361
Test name
Test status
Simulation time 1581174331730 ps
CPU time 771.64 seconds
Started Jul 29 04:25:37 PM PDT 24
Finished Jul 29 04:38:29 PM PDT 24
Peak memory 183020 kb
Host smart-5980d2a3-1534-4128-a20f-97f4e2b3f629
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978513544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.rv_timer_cfg_update_on_fly.978513544
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.2478335060
Short name T430
Test name
Test status
Simulation time 24075636363 ps
CPU time 33.54 seconds
Started Jul 29 04:25:37 PM PDT 24
Finished Jul 29 04:26:11 PM PDT 24
Peak memory 183076 kb
Host smart-13b8ec88-1410-4d4b-8dae-e1e4fb4db0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478335060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.2478335060
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.4250410748
Short name T344
Test name
Test status
Simulation time 29225595499 ps
CPU time 22.57 seconds
Started Jul 29 04:24:10 PM PDT 24
Finished Jul 29 04:24:32 PM PDT 24
Peak memory 183064 kb
Host smart-bda028b3-3c01-44d2-9c60-6677bab1836c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250410748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.4250410748
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.1688453284
Short name T119
Test name
Test status
Simulation time 22869815681 ps
CPU time 39.29 seconds
Started Jul 29 04:26:10 PM PDT 24
Finished Jul 29 04:26:50 PM PDT 24
Peak memory 183232 kb
Host smart-52bd123c-831b-40c8-9a6f-159bc2de0f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688453284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.1688453284
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.3997208856
Short name T16
Test name
Test status
Simulation time 192035883 ps
CPU time 0.83 seconds
Started Jul 29 04:25:13 PM PDT 24
Finished Jul 29 04:25:14 PM PDT 24
Peak memory 213772 kb
Host smart-b7eb3338-268b-4694-82f5-af09d91ae9aa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997208856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.3997208856
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.1668931374
Short name T391
Test name
Test status
Simulation time 270702652317 ps
CPU time 103.79 seconds
Started Jul 29 04:24:09 PM PDT 24
Finished Jul 29 04:25:53 PM PDT 24
Peak memory 183216 kb
Host smart-657ce3f9-42e4-4cc9-8373-6e893472ecb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668931374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
1668931374
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.3376318750
Short name T42
Test name
Test status
Simulation time 4911239684186 ps
CPU time 1193.13 seconds
Started Jul 29 04:25:41 PM PDT 24
Finished Jul 29 04:45:35 PM PDT 24
Peak memory 183252 kb
Host smart-76a5c4c8-31b6-47a7-9075-ca3ef036d362
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376318750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.3376318750
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.2038495345
Short name T381
Test name
Test status
Simulation time 372767754714 ps
CPU time 298.7 seconds
Started Jul 29 04:22:43 PM PDT 24
Finished Jul 29 04:27:41 PM PDT 24
Peak memory 183276 kb
Host smart-82347d45-221d-4b58-9fca-5992c79cb0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038495345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.2038495345
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.2344332562
Short name T206
Test name
Test status
Simulation time 134070148561 ps
CPU time 2283.16 seconds
Started Jul 29 04:25:41 PM PDT 24
Finished Jul 29 05:03:44 PM PDT 24
Peak memory 194956 kb
Host smart-4d006739-84c2-4861-9950-ab0288fc989e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344332562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.2344332562
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all_with_rand_reset.2315018175
Short name T38
Test name
Test status
Simulation time 224855305038 ps
CPU time 375.97 seconds
Started Jul 29 04:25:41 PM PDT 24
Finished Jul 29 04:31:57 PM PDT 24
Peak memory 206156 kb
Host smart-1133a720-cc7b-4c0f-a169-1fad7671dfa7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315018175 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all_with_rand_reset.2315018175
Directory /workspace/40.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.597394076
Short name T373
Test name
Test status
Simulation time 599291749279 ps
CPU time 233.25 seconds
Started Jul 29 04:25:40 PM PDT 24
Finished Jul 29 04:29:34 PM PDT 24
Peak memory 183272 kb
Host smart-3c1f787c-8a55-40e3-a600-0932924d847b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597394076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.597394076
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.1347712681
Short name T408
Test name
Test status
Simulation time 31035355393 ps
CPU time 13.67 seconds
Started Jul 29 04:25:41 PM PDT 24
Finished Jul 29 04:25:55 PM PDT 24
Peak memory 183172 kb
Host smart-98ceabdd-15ae-4ddc-8f4d-3f2ddced56fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347712681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.1347712681
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.2663437066
Short name T229
Test name
Test status
Simulation time 359167863069 ps
CPU time 381.5 seconds
Started Jul 29 04:22:52 PM PDT 24
Finished Jul 29 04:29:14 PM PDT 24
Peak memory 191796 kb
Host smart-9a26ec85-cee9-43d2-97df-43ea0b397413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663437066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.2663437066
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.1545383167
Short name T264
Test name
Test status
Simulation time 1841320016240 ps
CPU time 770.1 seconds
Started Jul 29 04:25:01 PM PDT 24
Finished Jul 29 04:37:52 PM PDT 24
Peak memory 181988 kb
Host smart-b6870cbe-2638-4cac-9044-4cadea45807a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545383167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.1545383167
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.2067669848
Short name T369
Test name
Test status
Simulation time 981146212137 ps
CPU time 344.65 seconds
Started Jul 29 04:25:01 PM PDT 24
Finished Jul 29 04:30:46 PM PDT 24
Peak memory 181936 kb
Host smart-a17537a9-d813-4df9-84ea-5ba38d940d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067669848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.2067669848
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.1587538967
Short name T343
Test name
Test status
Simulation time 87217589112 ps
CPU time 93.35 seconds
Started Jul 29 04:26:54 PM PDT 24
Finished Jul 29 04:28:29 PM PDT 24
Peak memory 180708 kb
Host smart-d306b37b-5eb4-4d69-a1e2-796b89c563c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587538967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.1587538967
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.831242420
Short name T398
Test name
Test status
Simulation time 77442115067 ps
CPU time 26.96 seconds
Started Jul 29 04:23:02 PM PDT 24
Finished Jul 29 04:23:29 PM PDT 24
Peak memory 194276 kb
Host smart-77e3945f-c501-4726-b5b8-1eb9ef250f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831242420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.831242420
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all_with_rand_reset.1424618219
Short name T40
Test name
Test status
Simulation time 13557085881 ps
CPU time 98.6 seconds
Started Jul 29 04:25:35 PM PDT 24
Finished Jul 29 04:27:14 PM PDT 24
Peak memory 197952 kb
Host smart-a9637423-7972-4935-9d6e-72a64360149e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424618219 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all_with_rand_reset.1424618219
Directory /workspace/42.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.46374552
Short name T449
Test name
Test status
Simulation time 453830453458 ps
CPU time 321.25 seconds
Started Jul 29 04:25:31 PM PDT 24
Finished Jul 29 04:30:53 PM PDT 24
Peak memory 183260 kb
Host smart-a3d1982f-4883-4bbf-b157-9b64b4552fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46374552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.46374552
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.2418691982
Short name T335
Test name
Test status
Simulation time 23758408194 ps
CPU time 40.58 seconds
Started Jul 29 04:25:34 PM PDT 24
Finished Jul 29 04:26:15 PM PDT 24
Peak memory 191424 kb
Host smart-e20b08f7-3482-4c10-9689-a757d6efcd07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418691982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.2418691982
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.2272783100
Short name T239
Test name
Test status
Simulation time 28823790413 ps
CPU time 49.29 seconds
Started Jul 29 04:25:13 PM PDT 24
Finished Jul 29 04:26:03 PM PDT 24
Peak memory 191476 kb
Host smart-d2e4f71e-1dca-4747-85d7-6f39af6ae1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272783100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.2272783100
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.2512029020
Short name T43
Test name
Test status
Simulation time 134816668453 ps
CPU time 50.23 seconds
Started Jul 29 04:23:19 PM PDT 24
Finished Jul 29 04:24:09 PM PDT 24
Peak memory 183612 kb
Host smart-39ed7ea6-9929-4d2e-9632-2c04b2713f68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512029020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.2512029020
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.1274954851
Short name T13
Test name
Test status
Simulation time 51250059965 ps
CPU time 228 seconds
Started Jul 29 04:25:50 PM PDT 24
Finished Jul 29 04:29:38 PM PDT 24
Peak memory 206152 kb
Host smart-6ebd7cc4-4976-4d1e-b740-1a104c6c5d41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274954851 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.1274954851
Directory /workspace/43.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.1714509642
Short name T340
Test name
Test status
Simulation time 34715031352 ps
CPU time 16.2 seconds
Started Jul 29 04:24:58 PM PDT 24
Finished Jul 29 04:25:15 PM PDT 24
Peak memory 181752 kb
Host smart-cd920974-75a0-4648-92f9-cc7783f6077c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714509642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.1714509642
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.3930406740
Short name T412
Test name
Test status
Simulation time 642810284700 ps
CPU time 174.62 seconds
Started Jul 29 04:25:14 PM PDT 24
Finished Jul 29 04:28:09 PM PDT 24
Peak memory 183224 kb
Host smart-5d999582-ba1a-4a67-8b40-8f946d1c3e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930406740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.3930406740
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.2481303862
Short name T20
Test name
Test status
Simulation time 932382920507 ps
CPU time 434.82 seconds
Started Jul 29 04:25:08 PM PDT 24
Finished Jul 29 04:32:23 PM PDT 24
Peak memory 191128 kb
Host smart-767aa20c-5dbc-47a7-a0d9-a73ef7091d86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481303862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.2481303862
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.1370425780
Short name T236
Test name
Test status
Simulation time 103535367529 ps
CPU time 138.38 seconds
Started Jul 29 04:25:10 PM PDT 24
Finished Jul 29 04:27:28 PM PDT 24
Peak memory 191136 kb
Host smart-6a9b60a0-ae64-49e6-a7c2-f59266f4ac28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370425780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.1370425780
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.1572995090
Short name T399
Test name
Test status
Simulation time 46997339 ps
CPU time 0.55 seconds
Started Jul 29 04:23:18 PM PDT 24
Finished Jul 29 04:23:18 PM PDT 24
Peak memory 183024 kb
Host smart-93da73d8-5ec0-42c8-9cc7-3d60a3e9006b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572995090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.1572995090
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.3313442585
Short name T416
Test name
Test status
Simulation time 40573444074 ps
CPU time 158.05 seconds
Started Jul 29 04:25:09 PM PDT 24
Finished Jul 29 04:27:47 PM PDT 24
Peak memory 197660 kb
Host smart-5af1335d-2d95-47fc-97ed-63a07dc48079
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313442585 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.3313442585
Directory /workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.540938406
Short name T304
Test name
Test status
Simulation time 127679675798 ps
CPU time 69.9 seconds
Started Jul 29 04:25:14 PM PDT 24
Finished Jul 29 04:26:24 PM PDT 24
Peak memory 183196 kb
Host smart-7b531b8d-bc80-48a6-b57d-966f14bd364e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540938406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.rv_timer_cfg_update_on_fly.540938406
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.661388942
Short name T367
Test name
Test status
Simulation time 113849678048 ps
CPU time 165.88 seconds
Started Jul 29 04:25:10 PM PDT 24
Finished Jul 29 04:27:56 PM PDT 24
Peak memory 182980 kb
Host smart-c86ca323-3c46-4b75-ba6f-1773d8072fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661388942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.661388942
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.2802731603
Short name T200
Test name
Test status
Simulation time 312434183052 ps
CPU time 631.22 seconds
Started Jul 29 04:25:10 PM PDT 24
Finished Jul 29 04:35:41 PM PDT 24
Peak memory 191128 kb
Host smart-3b96dc29-8738-4379-9d75-a9b93c81d18f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802731603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.2802731603
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.1294210509
Short name T182
Test name
Test status
Simulation time 377116750508 ps
CPU time 133.26 seconds
Started Jul 29 04:25:56 PM PDT 24
Finished Jul 29 04:28:10 PM PDT 24
Peak memory 183024 kb
Host smart-4723e1ed-9db4-4d33-86fb-3b5def160059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294210509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.1294210509
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.3743026703
Short name T289
Test name
Test status
Simulation time 976205215088 ps
CPU time 509.63 seconds
Started Jul 29 04:24:55 PM PDT 24
Finished Jul 29 04:33:26 PM PDT 24
Peak memory 181864 kb
Host smart-b502c6e6-61a9-4373-aca5-af7d37e724fa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743026703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.3743026703
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.1188934784
Short name T385
Test name
Test status
Simulation time 703439228288 ps
CPU time 264.23 seconds
Started Jul 29 04:25:08 PM PDT 24
Finished Jul 29 04:29:32 PM PDT 24
Peak memory 182936 kb
Host smart-1e7dc16b-cda2-4b42-be2c-723fb56f97a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188934784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.1188934784
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.3368047685
Short name T257
Test name
Test status
Simulation time 1676803978700 ps
CPU time 499.45 seconds
Started Jul 29 04:25:31 PM PDT 24
Finished Jul 29 04:33:51 PM PDT 24
Peak memory 191404 kb
Host smart-1cef55c3-7a05-4ab1-be57-4a8975193488
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368047685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.3368047685
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.1883878746
Short name T387
Test name
Test status
Simulation time 296890932 ps
CPU time 1.18 seconds
Started Jul 29 04:25:05 PM PDT 24
Finished Jul 29 04:25:06 PM PDT 24
Peak memory 191168 kb
Host smart-867a53a5-2af8-4fb9-98b0-d5aee95ff4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883878746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.1883878746
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.127587028
Short name T225
Test name
Test status
Simulation time 257738900246 ps
CPU time 380.49 seconds
Started Jul 29 04:25:02 PM PDT 24
Finished Jul 29 04:31:23 PM PDT 24
Peak memory 192856 kb
Host smart-d387ca21-6e87-4197-9339-cd980a2121f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127587028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all.
127587028
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.949380061
Short name T286
Test name
Test status
Simulation time 12316173302 ps
CPU time 20.05 seconds
Started Jul 29 04:23:34 PM PDT 24
Finished Jul 29 04:23:54 PM PDT 24
Peak memory 183232 kb
Host smart-0acc7e50-48d6-4ec4-bfaf-2e4d0d21afc7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949380061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.rv_timer_cfg_update_on_fly.949380061
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.3227893429
Short name T410
Test name
Test status
Simulation time 341591356886 ps
CPU time 123.42 seconds
Started Jul 29 04:25:12 PM PDT 24
Finished Jul 29 04:27:16 PM PDT 24
Peak memory 182892 kb
Host smart-ec4c0ed4-2141-48bc-a242-3c9c7d74c1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227893429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.3227893429
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.2744080275
Short name T345
Test name
Test status
Simulation time 615862447205 ps
CPU time 831.13 seconds
Started Jul 29 04:25:02 PM PDT 24
Finished Jul 29 04:38:54 PM PDT 24
Peak memory 189068 kb
Host smart-b7b871ff-b8d7-4e36-a1b7-96114e94b1f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744080275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.2744080275
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.3182389397
Short name T313
Test name
Test status
Simulation time 178857554983 ps
CPU time 56.14 seconds
Started Jul 29 04:25:11 PM PDT 24
Finished Jul 29 04:26:07 PM PDT 24
Peak memory 182884 kb
Host smart-b0d08843-5a81-4a6c-a826-e82974d6d2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182389397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.3182389397
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.4248263435
Short name T429
Test name
Test status
Simulation time 368056178928 ps
CPU time 136.06 seconds
Started Jul 29 04:25:05 PM PDT 24
Finished Jul 29 04:27:21 PM PDT 24
Peak memory 183016 kb
Host smart-070289bb-56f2-41f3-93cd-211b0c32620c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248263435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.4248263435
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.174225148
Short name T109
Test name
Test status
Simulation time 91761358864 ps
CPU time 128.31 seconds
Started Jul 29 04:25:05 PM PDT 24
Finished Jul 29 04:27:14 PM PDT 24
Peak memory 191396 kb
Host smart-689776c7-62fe-42a4-bb66-b62f12237874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174225148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.174225148
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.4283020570
Short name T78
Test name
Test status
Simulation time 404511545480 ps
CPU time 699.09 seconds
Started Jul 29 04:25:12 PM PDT 24
Finished Jul 29 04:36:51 PM PDT 24
Peak memory 183148 kb
Host smart-6586f219-e2e0-4393-91a0-e1f138fb98bb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283020570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.4283020570
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.3897874850
Short name T394
Test name
Test status
Simulation time 14439785445 ps
CPU time 21.05 seconds
Started Jul 29 04:25:04 PM PDT 24
Finished Jul 29 04:25:25 PM PDT 24
Peak memory 182932 kb
Host smart-a0c36665-9659-4bcf-911c-f6a7fc14f94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897874850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.3897874850
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.4064511946
Short name T184
Test name
Test status
Simulation time 34789102631 ps
CPU time 58.81 seconds
Started Jul 29 04:23:43 PM PDT 24
Finished Jul 29 04:24:42 PM PDT 24
Peak memory 191616 kb
Host smart-ff248df9-7fc1-46c6-8056-dbdad6c15d19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064511946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.4064511946
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.1675784775
Short name T372
Test name
Test status
Simulation time 584518192 ps
CPU time 0.68 seconds
Started Jul 29 04:23:47 PM PDT 24
Finished Jul 29 04:23:48 PM PDT 24
Peak memory 182956 kb
Host smart-ac6a82ad-bdac-49d1-b91f-a603baf3ec1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675784775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.1675784775
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.1650908316
Short name T203
Test name
Test status
Simulation time 146315528248 ps
CPU time 204.71 seconds
Started Jul 29 04:24:58 PM PDT 24
Finished Jul 29 04:28:23 PM PDT 24
Peak memory 194256 kb
Host smart-2a3c7b7a-84f1-40ac-9db2-53e6cf1da3d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650908316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.1650908316
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.2099953413
Short name T124
Test name
Test status
Simulation time 223566509385 ps
CPU time 363.36 seconds
Started Jul 29 04:25:34 PM PDT 24
Finished Jul 29 04:31:38 PM PDT 24
Peak memory 183128 kb
Host smart-769f21f9-9d03-412c-b550-22d51d53dcf6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099953413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.2099953413
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.2189031932
Short name T384
Test name
Test status
Simulation time 170312903443 ps
CPU time 219.82 seconds
Started Jul 29 04:25:30 PM PDT 24
Finished Jul 29 04:29:10 PM PDT 24
Peak memory 183012 kb
Host smart-08bd9173-8868-40f6-83a7-3761d6453eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189031932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.2189031932
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.220885386
Short name T134
Test name
Test status
Simulation time 889607169634 ps
CPU time 487.08 seconds
Started Jul 29 04:20:23 PM PDT 24
Finished Jul 29 04:28:30 PM PDT 24
Peak memory 191536 kb
Host smart-0db7095b-fd16-4d81-b77c-7643547616e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220885386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.220885386
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.2339464835
Short name T404
Test name
Test status
Simulation time 100028480 ps
CPU time 0.59 seconds
Started Jul 29 04:25:47 PM PDT 24
Finished Jul 29 04:25:48 PM PDT 24
Peak memory 182624 kb
Host smart-08b1cd5d-888d-48f8-a14b-ef2ed4364e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339464835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.2339464835
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.4151904578
Short name T445
Test name
Test status
Simulation time 769339836733 ps
CPU time 185.08 seconds
Started Jul 29 04:22:00 PM PDT 24
Finished Jul 29 04:25:05 PM PDT 24
Peak memory 183592 kb
Host smart-5258ad0a-5792-45b6-91f5-fcbce1bc6118
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151904578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
4151904578
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/50.rv_timer_random.3501899735
Short name T198
Test name
Test status
Simulation time 157432284452 ps
CPU time 131.68 seconds
Started Jul 29 04:26:10 PM PDT 24
Finished Jul 29 04:28:22 PM PDT 24
Peak memory 191332 kb
Host smart-fdfa0043-24cc-4495-8c7e-ad19a77b2a9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501899735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.3501899735
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.1625079718
Short name T446
Test name
Test status
Simulation time 716483190591 ps
CPU time 631.74 seconds
Started Jul 29 04:25:25 PM PDT 24
Finished Jul 29 04:35:57 PM PDT 24
Peak memory 191368 kb
Host smart-fca6eb82-2aa6-4b2d-8a18-0ec3d1ca35ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625079718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.1625079718
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.3343173144
Short name T301
Test name
Test status
Simulation time 15425622204 ps
CPU time 90.13 seconds
Started Jul 29 04:25:12 PM PDT 24
Finished Jul 29 04:26:42 PM PDT 24
Peak memory 182888 kb
Host smart-21eec5fb-b5bf-41c6-8132-f2e29019a914
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343173144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.3343173144
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.1575317961
Short name T118
Test name
Test status
Simulation time 130701049814 ps
CPU time 155.15 seconds
Started Jul 29 04:23:54 PM PDT 24
Finished Jul 29 04:26:29 PM PDT 24
Peak memory 183236 kb
Host smart-7960e0f3-7a3c-4dfe-9528-a56b0d253ab0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575317961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.1575317961
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.3695816404
Short name T447
Test name
Test status
Simulation time 8775987992 ps
CPU time 11.02 seconds
Started Jul 29 04:23:52 PM PDT 24
Finished Jul 29 04:24:03 PM PDT 24
Peak memory 183232 kb
Host smart-b0f54c45-7c31-42cc-8391-a41afc4577cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695816404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.3695816404
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.1736604861
Short name T120
Test name
Test status
Simulation time 126500086606 ps
CPU time 499.25 seconds
Started Jul 29 04:25:23 PM PDT 24
Finished Jul 29 04:33:42 PM PDT 24
Peak memory 191472 kb
Host smart-fcb6c147-cf04-4f30-a51d-1cedc55c5931
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736604861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.1736604861
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.3704145239
Short name T418
Test name
Test status
Simulation time 320091081093 ps
CPU time 170.58 seconds
Started Jul 29 04:25:26 PM PDT 24
Finished Jul 29 04:28:16 PM PDT 24
Peak memory 194124 kb
Host smart-111313a6-b35c-4726-aff7-5508c356e2fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704145239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.3704145239
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.2706541630
Short name T213
Test name
Test status
Simulation time 146153227302 ps
CPU time 56.34 seconds
Started Jul 29 04:26:11 PM PDT 24
Finished Jul 29 04:27:07 PM PDT 24
Peak memory 191424 kb
Host smart-31633d96-9c11-4263-8075-5237a51c7185
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706541630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.2706541630
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.1835238902
Short name T23
Test name
Test status
Simulation time 53792677944 ps
CPU time 146.72 seconds
Started Jul 29 04:25:23 PM PDT 24
Finished Jul 29 04:27:50 PM PDT 24
Peak memory 183272 kb
Host smart-9d2b605b-f11e-4351-8bef-d035f7697922
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835238902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.1835238902
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.1555621398
Short name T98
Test name
Test status
Simulation time 18930220601 ps
CPU time 17.34 seconds
Started Jul 29 04:25:04 PM PDT 24
Finished Jul 29 04:25:21 PM PDT 24
Peak memory 182872 kb
Host smart-cf00578d-95df-4ba2-8210-43fb665b6273
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555621398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.1555621398
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.1018205040
Short name T401
Test name
Test status
Simulation time 682610473742 ps
CPU time 196.17 seconds
Started Jul 29 04:22:37 PM PDT 24
Finished Jul 29 04:25:54 PM PDT 24
Peak memory 183260 kb
Host smart-dd548eec-e44a-45d9-b231-25e3e0b95c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018205040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.1018205040
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.2575645899
Short name T144
Test name
Test status
Simulation time 778191264095 ps
CPU time 398.44 seconds
Started Jul 29 04:21:25 PM PDT 24
Finished Jul 29 04:28:04 PM PDT 24
Peak memory 191456 kb
Host smart-a24f7214-e0b2-4475-b098-2e912194251f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575645899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.2575645899
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.3241270994
Short name T450
Test name
Test status
Simulation time 101832781 ps
CPU time 0.64 seconds
Started Jul 29 04:25:34 PM PDT 24
Finished Jul 29 04:25:35 PM PDT 24
Peak memory 183036 kb
Host smart-bd18a3af-1a96-4403-b994-de90cf36a05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241270994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.3241270994
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.1225228742
Short name T127
Test name
Test status
Simulation time 53289485 ps
CPU time 0.51 seconds
Started Jul 29 04:26:11 PM PDT 24
Finished Jul 29 04:26:11 PM PDT 24
Peak memory 182984 kb
Host smart-56bdba9e-b340-48de-b690-728aa206cd6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225228742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.1225228742
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.2339318146
Short name T199
Test name
Test status
Simulation time 76833332675 ps
CPU time 37.22 seconds
Started Jul 29 04:25:23 PM PDT 24
Finished Jul 29 04:26:00 PM PDT 24
Peak memory 183264 kb
Host smart-d4d6b784-8900-4383-8ea1-07becfe2e360
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339318146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.2339318146
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.19024327
Short name T315
Test name
Test status
Simulation time 125560666800 ps
CPU time 208.69 seconds
Started Jul 29 04:25:09 PM PDT 24
Finished Jul 29 04:28:38 PM PDT 24
Peak memory 190568 kb
Host smart-7540ead8-9388-4362-be2f-4216e73e96d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19024327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.19024327
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.3987950927
Short name T427
Test name
Test status
Simulation time 44778220280 ps
CPU time 66.05 seconds
Started Jul 29 04:25:18 PM PDT 24
Finished Jul 29 04:26:25 PM PDT 24
Peak memory 182092 kb
Host smart-eb375b0d-259d-4507-b38e-9862e66e616b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987950927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.3987950927
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.2005418989
Short name T179
Test name
Test status
Simulation time 131283291148 ps
CPU time 503.05 seconds
Started Jul 29 04:25:39 PM PDT 24
Finished Jul 29 04:34:03 PM PDT 24
Peak memory 191384 kb
Host smart-d8c24d1a-2a58-454a-a2b0-2caeaa3eca80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005418989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.2005418989
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.3011240840
Short name T433
Test name
Test status
Simulation time 12371463627 ps
CPU time 19.26 seconds
Started Jul 29 04:25:41 PM PDT 24
Finished Jul 29 04:26:00 PM PDT 24
Peak memory 191388 kb
Host smart-3f64aaa8-df08-42e7-b38b-663ea73509e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011240840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.3011240840
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.3149408923
Short name T167
Test name
Test status
Simulation time 278268153732 ps
CPU time 297.23 seconds
Started Jul 29 04:25:37 PM PDT 24
Finished Jul 29 04:30:35 PM PDT 24
Peak memory 182344 kb
Host smart-e4a9a16a-16be-4e41-917a-da561a368486
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149408923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.3149408923
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.1121655451
Short name T426
Test name
Test status
Simulation time 438419250174 ps
CPU time 313.74 seconds
Started Jul 29 04:25:11 PM PDT 24
Finished Jul 29 04:30:25 PM PDT 24
Peak memory 182892 kb
Host smart-01a3a5e8-f824-49b9-b1be-ccf2c9b885fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121655451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.1121655451
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.1372085732
Short name T298
Test name
Test status
Simulation time 587977525804 ps
CPU time 344.25 seconds
Started Jul 29 04:21:15 PM PDT 24
Finished Jul 29 04:26:59 PM PDT 24
Peak memory 191488 kb
Host smart-7fcc6495-ed3a-4b69-9ac1-df224a42efc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372085732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.1372085732
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.2524889127
Short name T271
Test name
Test status
Simulation time 10142747773 ps
CPU time 24.36 seconds
Started Jul 29 04:23:51 PM PDT 24
Finished Jul 29 04:24:15 PM PDT 24
Peak memory 183376 kb
Host smart-889ca5bb-31a3-4ea1-9244-eddb6786c1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524889127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.2524889127
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.441941646
Short name T244
Test name
Test status
Simulation time 206204623743 ps
CPU time 213.17 seconds
Started Jul 29 04:25:37 PM PDT 24
Finished Jul 29 04:29:10 PM PDT 24
Peak memory 193436 kb
Host smart-7adf9ce7-7164-4c7e-8fae-2668212270ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441941646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.441941646
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/70.rv_timer_random.2832406152
Short name T337
Test name
Test status
Simulation time 539964339403 ps
CPU time 705.57 seconds
Started Jul 29 04:25:32 PM PDT 24
Finished Jul 29 04:37:18 PM PDT 24
Peak memory 191460 kb
Host smart-ab32f9db-61cf-4e97-8896-b0546241a776
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832406152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.2832406152
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.1241593584
Short name T317
Test name
Test status
Simulation time 197503661973 ps
CPU time 241.92 seconds
Started Jul 29 04:24:08 PM PDT 24
Finished Jul 29 04:28:10 PM PDT 24
Peak memory 191584 kb
Host smart-3c368c5c-dd9c-4c7c-9e1f-194438adbbd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241593584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.1241593584
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.2740204035
Short name T302
Test name
Test status
Simulation time 28190427619 ps
CPU time 45.54 seconds
Started Jul 29 04:25:29 PM PDT 24
Finished Jul 29 04:26:15 PM PDT 24
Peak memory 191204 kb
Host smart-724c8266-3ed0-43af-b318-ea39f5f45d5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740204035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.2740204035
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.214039406
Short name T235
Test name
Test status
Simulation time 199053615283 ps
CPU time 227.45 seconds
Started Jul 29 04:25:29 PM PDT 24
Finished Jul 29 04:29:17 PM PDT 24
Peak memory 191192 kb
Host smart-977d74bb-f7e4-4410-ba69-201d31639738
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214039406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.214039406
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.582361994
Short name T280
Test name
Test status
Simulation time 150643405064 ps
CPU time 1841.53 seconds
Started Jul 29 04:25:39 PM PDT 24
Finished Jul 29 04:56:21 PM PDT 24
Peak memory 191400 kb
Host smart-774fd9ca-5b18-4f69-bcb4-d5a43880174a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582361994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.582361994
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.319913140
Short name T130
Test name
Test status
Simulation time 37203490929 ps
CPU time 43.6 seconds
Started Jul 29 04:24:07 PM PDT 24
Finished Jul 29 04:24:51 PM PDT 24
Peak memory 183252 kb
Host smart-8f016cf0-2bc3-4ca3-be65-6aef4366ba3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319913140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.319913140
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.1898211570
Short name T327
Test name
Test status
Simulation time 173469971431 ps
CPU time 202.92 seconds
Started Jul 29 04:24:08 PM PDT 24
Finished Jul 29 04:27:31 PM PDT 24
Peak memory 191476 kb
Host smart-d3305b04-a3b2-44fc-b024-f04b712556b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898211570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.1898211570
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.785258722
Short name T113
Test name
Test status
Simulation time 175368724775 ps
CPU time 139.7 seconds
Started Jul 29 04:24:08 PM PDT 24
Finished Jul 29 04:26:28 PM PDT 24
Peak memory 195140 kb
Host smart-7ff28568-64b2-4c2a-9c10-e7baa62eac58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785258722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.785258722
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.185238137
Short name T282
Test name
Test status
Simulation time 264438947418 ps
CPU time 231.38 seconds
Started Jul 29 04:24:13 PM PDT 24
Finished Jul 29 04:28:04 PM PDT 24
Peak memory 183336 kb
Host smart-1511d837-bde0-443a-a1de-51191a329bfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185238137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.185238137
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.3294204466
Short name T9
Test name
Test status
Simulation time 122683534383 ps
CPU time 202.22 seconds
Started Jul 29 04:21:50 PM PDT 24
Finished Jul 29 04:25:12 PM PDT 24
Peak memory 183324 kb
Host smart-3eea256c-d6b2-4975-b163-45ce7edecc7a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294204466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.3294204466
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.2860298915
Short name T443
Test name
Test status
Simulation time 5434121645 ps
CPU time 4.48 seconds
Started Jul 29 04:25:36 PM PDT 24
Finished Jul 29 04:25:41 PM PDT 24
Peak memory 182840 kb
Host smart-d7b29b4f-d58f-4752-86fa-0d6f7a2c6481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860298915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.2860298915
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.1464443409
Short name T193
Test name
Test status
Simulation time 295594389756 ps
CPU time 127.16 seconds
Started Jul 29 04:21:09 PM PDT 24
Finished Jul 29 04:23:16 PM PDT 24
Peak memory 183252 kb
Host smart-acfcbb15-ae2f-45a0-989b-fd17c566f209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464443409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.1464443409
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.2241795150
Short name T60
Test name
Test status
Simulation time 2581169918237 ps
CPU time 1181.75 seconds
Started Jul 29 04:25:15 PM PDT 24
Finished Jul 29 04:44:57 PM PDT 24
Peak memory 191428 kb
Host smart-ca3a2b26-05bf-4235-88f0-707c4963345a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241795150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
2241795150
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/80.rv_timer_random.3296949403
Short name T104
Test name
Test status
Simulation time 395389730260 ps
CPU time 240.46 seconds
Started Jul 29 04:26:05 PM PDT 24
Finished Jul 29 04:30:05 PM PDT 24
Peak memory 191144 kb
Host smart-b9524ee0-89de-4597-b883-634993c84bfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296949403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.3296949403
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.2711806035
Short name T270
Test name
Test status
Simulation time 336837802237 ps
CPU time 413.26 seconds
Started Jul 29 04:26:04 PM PDT 24
Finished Jul 29 04:32:58 PM PDT 24
Peak memory 191152 kb
Host smart-0e666b7c-12f2-4da0-aff7-ad20d865816c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711806035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.2711806035
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.3158060962
Short name T297
Test name
Test status
Simulation time 280984708333 ps
CPU time 660.67 seconds
Started Jul 29 04:25:47 PM PDT 24
Finished Jul 29 04:36:48 PM PDT 24
Peak memory 191420 kb
Host smart-a902674d-3d6f-4033-98c2-534048793aa8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158060962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.3158060962
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.1644993364
Short name T321
Test name
Test status
Simulation time 17368348596 ps
CPU time 29.13 seconds
Started Jul 29 04:25:56 PM PDT 24
Finished Jul 29 04:26:26 PM PDT 24
Peak memory 182388 kb
Host smart-f9421770-f6b6-4132-b5e0-437bab2e9ffd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644993364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.1644993364
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.2824518292
Short name T161
Test name
Test status
Simulation time 240248200128 ps
CPU time 132.26 seconds
Started Jul 29 04:25:51 PM PDT 24
Finished Jul 29 04:28:03 PM PDT 24
Peak memory 191484 kb
Host smart-00846e3c-ab70-4248-a533-713b11f514ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824518292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.2824518292
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.2149593538
Short name T1
Test name
Test status
Simulation time 240259660223 ps
CPU time 655.98 seconds
Started Jul 29 04:26:05 PM PDT 24
Finished Jul 29 04:37:01 PM PDT 24
Peak memory 191144 kb
Host smart-8d4c983c-e851-43bf-8ea0-e483e0110aad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149593538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.2149593538
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.3739447407
Short name T291
Test name
Test status
Simulation time 135278469576 ps
CPU time 243.33 seconds
Started Jul 29 04:24:19 PM PDT 24
Finished Jul 29 04:28:22 PM PDT 24
Peak memory 191748 kb
Host smart-aaa3a9ed-acbf-4119-8d31-53dde5f38bb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739447407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.3739447407
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.1567719688
Short name T240
Test name
Test status
Simulation time 93056929503 ps
CPU time 570.22 seconds
Started Jul 29 04:26:04 PM PDT 24
Finished Jul 29 04:35:35 PM PDT 24
Peak memory 194380 kb
Host smart-7a802ef0-9cd2-46b2-adab-1a7edbfabbc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567719688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.1567719688
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.3733157273
Short name T355
Test name
Test status
Simulation time 9826966952 ps
CPU time 17.54 seconds
Started Jul 29 04:25:17 PM PDT 24
Finished Jul 29 04:25:35 PM PDT 24
Peak memory 181960 kb
Host smart-ccfda1c6-ee31-45b3-9794-a11d858f9884
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733157273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.3733157273
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.923418701
Short name T438
Test name
Test status
Simulation time 35749095207 ps
CPU time 31.18 seconds
Started Jul 29 04:25:17 PM PDT 24
Finished Jul 29 04:25:48 PM PDT 24
Peak memory 183248 kb
Host smart-1d25b46e-2300-4752-906a-86a753e29717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923418701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.923418701
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.2598031971
Short name T138
Test name
Test status
Simulation time 459553205850 ps
CPU time 612.43 seconds
Started Jul 29 04:25:01 PM PDT 24
Finished Jul 29 04:35:13 PM PDT 24
Peak memory 191384 kb
Host smart-1724c312-08ca-47f2-bd9f-a94d537f98a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598031971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.2598031971
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.4182615727
Short name T276
Test name
Test status
Simulation time 124158272613 ps
CPU time 310.33 seconds
Started Jul 29 04:25:35 PM PDT 24
Finished Jul 29 04:30:45 PM PDT 24
Peak memory 191100 kb
Host smart-fa2753a8-9f4e-41e3-bd13-a74d64ca9f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182615727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.4182615727
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.3355011076
Short name T54
Test name
Test status
Simulation time 3485746304 ps
CPU time 4.2 seconds
Started Jul 29 04:23:20 PM PDT 24
Finished Jul 29 04:23:25 PM PDT 24
Peak memory 183060 kb
Host smart-65f4ca7f-a394-4967-97d4-a4be356b2929
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355011076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
3355011076
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all_with_rand_reset.3255681757
Short name T12
Test name
Test status
Simulation time 49520368027 ps
CPU time 100.7 seconds
Started Jul 29 04:21:13 PM PDT 24
Finished Jul 29 04:22:54 PM PDT 24
Peak memory 206472 kb
Host smart-677cc9b6-0bcd-4f00-ad6c-047a5de17999
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255681757 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all_with_rand_reset.3255681757
Directory /workspace/9.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.3435569712
Short name T155
Test name
Test status
Simulation time 98194084372 ps
CPU time 48.45 seconds
Started Jul 29 04:24:30 PM PDT 24
Finished Jul 29 04:25:18 PM PDT 24
Peak memory 183084 kb
Host smart-25f311d1-3a91-4eaa-8184-127378b1008b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435569712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.3435569712
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.294338848
Short name T238
Test name
Test status
Simulation time 116333831969 ps
CPU time 291.14 seconds
Started Jul 29 04:25:56 PM PDT 24
Finished Jul 29 04:30:47 PM PDT 24
Peak memory 193792 kb
Host smart-f05fed6a-006e-4382-b376-489520f8290e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294338848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.294338848
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.2399537051
Short name T131
Test name
Test status
Simulation time 94166853438 ps
CPU time 84.84 seconds
Started Jul 29 04:24:29 PM PDT 24
Finished Jul 29 04:25:54 PM PDT 24
Peak memory 191472 kb
Host smart-a7470055-513f-494f-9fa7-83402e253ec3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399537051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.2399537051
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.614723758
Short name T432
Test name
Test status
Simulation time 151098606326 ps
CPU time 235.94 seconds
Started Jul 29 04:24:30 PM PDT 24
Finished Jul 29 04:28:26 PM PDT 24
Peak memory 191452 kb
Host smart-e61ca93f-fbe4-414e-bfd7-dd10b5f3e355
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614723758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.614723758
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.2847662237
Short name T172
Test name
Test status
Simulation time 402378448569 ps
CPU time 587.71 seconds
Started Jul 29 04:26:10 PM PDT 24
Finished Jul 29 04:35:59 PM PDT 24
Peak memory 190540 kb
Host smart-c1556485-a7af-44ad-8720-1f53e91450d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847662237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.2847662237
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.2443549015
Short name T95
Test name
Test status
Simulation time 128158311877 ps
CPU time 260.91 seconds
Started Jul 29 04:25:46 PM PDT 24
Finished Jul 29 04:30:08 PM PDT 24
Peak memory 190620 kb
Host smart-f26bc589-65a8-4bfd-85d1-59565da6c3c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443549015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.2443549015
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.2777364835
Short name T147
Test name
Test status
Simulation time 99415561006 ps
CPU time 154.87 seconds
Started Jul 29 04:24:28 PM PDT 24
Finished Jul 29 04:27:03 PM PDT 24
Peak memory 191372 kb
Host smart-e620b5b5-72d6-4a91-b832-ab5ae57efd45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777364835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.2777364835
Directory /workspace/99.rv_timer_random/latest
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