Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.61 99.36 98.73 100.00 100.00 100.00 99.55


Total test records in report: 586
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T511 /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1738744303 Jul 30 06:10:47 PM PDT 24 Jul 30 06:10:48 PM PDT 24 18601664 ps
T512 /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.221518541 Jul 30 06:10:58 PM PDT 24 Jul 30 06:10:59 PM PDT 24 37973359 ps
T513 /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.1245770378 Jul 30 06:10:55 PM PDT 24 Jul 30 06:10:56 PM PDT 24 89389708 ps
T514 /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.3834656626 Jul 30 06:11:00 PM PDT 24 Jul 30 06:11:01 PM PDT 24 56891376 ps
T515 /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.1854685795 Jul 30 06:10:49 PM PDT 24 Jul 30 06:10:50 PM PDT 24 14326685 ps
T516 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.4137487260 Jul 30 06:10:57 PM PDT 24 Jul 30 06:10:57 PM PDT 24 39113359 ps
T517 /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.3635245019 Jul 30 06:10:45 PM PDT 24 Jul 30 06:10:45 PM PDT 24 15746241 ps
T518 /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.678363311 Jul 30 06:10:47 PM PDT 24 Jul 30 06:10:48 PM PDT 24 21067050 ps
T519 /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.3276103826 Jul 30 06:10:55 PM PDT 24 Jul 30 06:10:55 PM PDT 24 19447269 ps
T520 /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.2533881809 Jul 30 06:11:03 PM PDT 24 Jul 30 06:11:04 PM PDT 24 39147312 ps
T521 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1428106205 Jul 30 06:10:49 PM PDT 24 Jul 30 06:10:50 PM PDT 24 80775555 ps
T522 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.4287281258 Jul 30 06:10:49 PM PDT 24 Jul 30 06:10:50 PM PDT 24 17755964 ps
T523 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.4174120835 Jul 30 06:10:45 PM PDT 24 Jul 30 06:10:46 PM PDT 24 86457510 ps
T524 /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3069471125 Jul 30 06:10:51 PM PDT 24 Jul 30 06:10:51 PM PDT 24 17034541 ps
T525 /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.1291873064 Jul 30 06:10:37 PM PDT 24 Jul 30 06:10:38 PM PDT 24 32649368 ps
T526 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.2454385202 Jul 30 06:10:50 PM PDT 24 Jul 30 06:10:51 PM PDT 24 46219843 ps
T527 /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.2268581103 Jul 30 06:10:43 PM PDT 24 Jul 30 06:10:44 PM PDT 24 25863746 ps
T100 /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.153291100 Jul 30 06:10:57 PM PDT 24 Jul 30 06:10:59 PM PDT 24 833101024 ps
T528 /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.1813349099 Jul 30 06:10:58 PM PDT 24 Jul 30 06:11:00 PM PDT 24 343148345 ps
T529 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.4200390288 Jul 30 06:10:47 PM PDT 24 Jul 30 06:10:48 PM PDT 24 29440899 ps
T530 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2375501065 Jul 30 06:10:34 PM PDT 24 Jul 30 06:10:36 PM PDT 24 194849732 ps
T531 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.731521539 Jul 30 06:10:40 PM PDT 24 Jul 30 06:10:41 PM PDT 24 22551888 ps
T532 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.786628315 Jul 30 06:10:44 PM PDT 24 Jul 30 06:10:46 PM PDT 24 398060290 ps
T533 /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.101309460 Jul 30 06:10:39 PM PDT 24 Jul 30 06:10:40 PM PDT 24 38521793 ps
T534 /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.4142565737 Jul 30 06:10:56 PM PDT 24 Jul 30 06:10:57 PM PDT 24 25267291 ps
T535 /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.1879377985 Jul 30 06:10:50 PM PDT 24 Jul 30 06:10:52 PM PDT 24 35680497 ps
T536 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.861216970 Jul 30 06:10:42 PM PDT 24 Jul 30 06:10:43 PM PDT 24 82676952 ps
T537 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1970199004 Jul 30 06:10:58 PM PDT 24 Jul 30 06:10:59 PM PDT 24 130901571 ps
T101 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.793938284 Jul 30 06:10:52 PM PDT 24 Jul 30 06:10:53 PM PDT 24 76955204 ps
T538 /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.4269156236 Jul 30 06:10:48 PM PDT 24 Jul 30 06:10:49 PM PDT 24 266462029 ps
T539 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.2931046762 Jul 30 06:11:04 PM PDT 24 Jul 30 06:11:04 PM PDT 24 21520939 ps
T540 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.933428633 Jul 30 06:10:56 PM PDT 24 Jul 30 06:10:57 PM PDT 24 14578766 ps
T541 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.3192652336 Jul 30 06:10:37 PM PDT 24 Jul 30 06:10:38 PM PDT 24 21349584 ps
T542 /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.951864351 Jul 30 06:10:48 PM PDT 24 Jul 30 06:10:50 PM PDT 24 147633432 ps
T543 /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.3733076237 Jul 30 06:10:49 PM PDT 24 Jul 30 06:10:50 PM PDT 24 120936849 ps
T544 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.3655347921 Jul 30 06:11:00 PM PDT 24 Jul 30 06:11:01 PM PDT 24 43289994 ps
T545 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1880279999 Jul 30 06:10:46 PM PDT 24 Jul 30 06:10:47 PM PDT 24 378603006 ps
T546 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.3499604050 Jul 30 06:10:45 PM PDT 24 Jul 30 06:10:47 PM PDT 24 113071371 ps
T86 /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.4255676984 Jul 30 06:10:43 PM PDT 24 Jul 30 06:10:44 PM PDT 24 38159221 ps
T547 /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.623443681 Jul 30 06:10:49 PM PDT 24 Jul 30 06:10:51 PM PDT 24 123325812 ps
T548 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.542081745 Jul 30 06:11:01 PM PDT 24 Jul 30 06:11:02 PM PDT 24 51321791 ps
T87 /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.3758446735 Jul 30 06:10:45 PM PDT 24 Jul 30 06:10:46 PM PDT 24 31901641 ps
T549 /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.439283005 Jul 30 06:10:53 PM PDT 24 Jul 30 06:10:54 PM PDT 24 66933174 ps
T550 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.65793750 Jul 30 06:11:02 PM PDT 24 Jul 30 06:11:02 PM PDT 24 13240668 ps
T551 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.2658870270 Jul 30 06:10:49 PM PDT 24 Jul 30 06:10:49 PM PDT 24 18712736 ps
T102 /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1279942590 Jul 30 06:10:55 PM PDT 24 Jul 30 06:10:57 PM PDT 24 172446938 ps
T552 /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.3561692766 Jul 30 06:10:40 PM PDT 24 Jul 30 06:10:41 PM PDT 24 25252245 ps
T88 /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.2199933285 Jul 30 06:10:57 PM PDT 24 Jul 30 06:10:58 PM PDT 24 12631164 ps
T553 /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2275030456 Jul 30 06:10:37 PM PDT 24 Jul 30 06:10:38 PM PDT 24 1036228981 ps
T89 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.126518743 Jul 30 06:10:54 PM PDT 24 Jul 30 06:10:55 PM PDT 24 51091399 ps
T554 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.297165786 Jul 30 06:10:52 PM PDT 24 Jul 30 06:10:55 PM PDT 24 1502501080 ps
T555 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.3444187541 Jul 30 06:11:05 PM PDT 24 Jul 30 06:11:05 PM PDT 24 39648619 ps
T556 /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.2535581352 Jul 30 06:10:53 PM PDT 24 Jul 30 06:10:54 PM PDT 24 94207055 ps
T90 /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.58162750 Jul 30 06:10:49 PM PDT 24 Jul 30 06:10:50 PM PDT 24 251957339 ps
T557 /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.686869133 Jul 30 06:10:47 PM PDT 24 Jul 30 06:10:48 PM PDT 24 71683664 ps
T558 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.2123774856 Jul 30 06:10:51 PM PDT 24 Jul 30 06:10:51 PM PDT 24 18920430 ps
T103 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.2668364579 Jul 30 06:10:48 PM PDT 24 Jul 30 06:10:49 PM PDT 24 52263751 ps
T559 /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.2201957311 Jul 30 06:10:49 PM PDT 24 Jul 30 06:10:51 PM PDT 24 171319323 ps
T560 /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.4249753870 Jul 30 06:10:53 PM PDT 24 Jul 30 06:10:54 PM PDT 24 90903350 ps
T561 /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.2728682958 Jul 30 06:10:42 PM PDT 24 Jul 30 06:10:43 PM PDT 24 14075137 ps
T562 /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2096932699 Jul 30 06:10:58 PM PDT 24 Jul 30 06:10:59 PM PDT 24 67158017 ps
T563 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.643570456 Jul 30 06:10:55 PM PDT 24 Jul 30 06:10:56 PM PDT 24 286598635 ps
T564 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3114109663 Jul 30 06:10:41 PM PDT 24 Jul 30 06:10:43 PM PDT 24 74728195 ps
T565 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.110307803 Jul 30 06:10:47 PM PDT 24 Jul 30 06:10:48 PM PDT 24 461179569 ps
T566 /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.3203075346 Jul 30 06:11:07 PM PDT 24 Jul 30 06:11:08 PM PDT 24 53929917 ps
T567 /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.461913272 Jul 30 06:10:58 PM PDT 24 Jul 30 06:10:59 PM PDT 24 14387672 ps
T568 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.2842293248 Jul 30 06:11:01 PM PDT 24 Jul 30 06:11:01 PM PDT 24 24493208 ps
T569 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.8401839 Jul 30 06:10:51 PM PDT 24 Jul 30 06:10:52 PM PDT 24 236564351 ps
T570 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3133192294 Jul 30 06:10:41 PM PDT 24 Jul 30 06:10:42 PM PDT 24 17906953 ps
T571 /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.4206944661 Jul 30 06:10:33 PM PDT 24 Jul 30 06:10:34 PM PDT 24 13228384 ps
T572 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.961972859 Jul 30 06:10:40 PM PDT 24 Jul 30 06:10:41 PM PDT 24 38749800 ps
T573 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.325330406 Jul 30 06:10:33 PM PDT 24 Jul 30 06:10:35 PM PDT 24 717757027 ps
T574 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.391374118 Jul 30 06:11:03 PM PDT 24 Jul 30 06:11:03 PM PDT 24 19271391 ps
T575 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.1834377299 Jul 30 06:10:39 PM PDT 24 Jul 30 06:10:40 PM PDT 24 97919265 ps
T576 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.69464726 Jul 30 06:10:33 PM PDT 24 Jul 30 06:10:34 PM PDT 24 47318846 ps
T577 /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.1598460075 Jul 30 06:10:59 PM PDT 24 Jul 30 06:11:01 PM PDT 24 93474967 ps
T578 /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.2543346614 Jul 30 06:10:49 PM PDT 24 Jul 30 06:10:49 PM PDT 24 33340220 ps
T579 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.3834145117 Jul 30 06:10:59 PM PDT 24 Jul 30 06:10:59 PM PDT 24 16465051 ps
T580 /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.978886152 Jul 30 06:10:54 PM PDT 24 Jul 30 06:10:54 PM PDT 24 80855277 ps
T581 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.3226441232 Jul 30 06:10:58 PM PDT 24 Jul 30 06:10:59 PM PDT 24 25758907 ps
T91 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.514533046 Jul 30 06:10:47 PM PDT 24 Jul 30 06:10:48 PM PDT 24 16970252 ps
T582 /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.857036802 Jul 30 06:10:46 PM PDT 24 Jul 30 06:10:47 PM PDT 24 57336343 ps
T583 /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.868199137 Jul 30 06:10:35 PM PDT 24 Jul 30 06:10:39 PM PDT 24 373273229 ps
T584 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.2293636942 Jul 30 06:11:03 PM PDT 24 Jul 30 06:11:03 PM PDT 24 35534966 ps
T585 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.939519372 Jul 30 06:10:56 PM PDT 24 Jul 30 06:10:57 PM PDT 24 39714039 ps
T586 /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.1987700536 Jul 30 06:10:51 PM PDT 24 Jul 30 06:10:52 PM PDT 24 19888735 ps

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.1939529850
Short name T5
Test name
Test status
Simulation time 1114882553603 ps
CPU time 609.23 seconds
Started Jul 30 06:11:38 PM PDT 24
Finished Jul 30 06:21:48 PM PDT 24
Peak memory 183504 kb
Host smart-248ff237-be10-421a-b676-045cd6ba7e36
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939529850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.1939529850
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all_with_rand_reset.2650437367
Short name T12
Test name
Test status
Simulation time 113174587519 ps
CPU time 377.15 seconds
Started Jul 30 06:11:39 PM PDT 24
Finished Jul 30 06:17:57 PM PDT 24
Peak memory 206296 kb
Host smart-3ef75557-f381-466b-9bc7-e729e65ce9bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650437367 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all_with_rand_reset.2650437367
Directory /workspace/11.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.2323069298
Short name T125
Test name
Test status
Simulation time 2936149979316 ps
CPU time 2304.67 seconds
Started Jul 30 06:11:39 PM PDT 24
Finished Jul 30 06:50:04 PM PDT 24
Peak memory 191672 kb
Host smart-d8b85177-7328-478d-9de3-5e9ce6c789e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323069298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.2323069298
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.1607509583
Short name T29
Test name
Test status
Simulation time 147908234 ps
CPU time 1.44 seconds
Started Jul 30 06:10:44 PM PDT 24
Finished Jul 30 06:10:45 PM PDT 24
Peak memory 195708 kb
Host smart-c11d8067-2aa8-4a66-9f3e-16b79936823e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607509583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.1607509583
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.3898207648
Short name T65
Test name
Test status
Simulation time 1986972625461 ps
CPU time 1110.58 seconds
Started Jul 30 06:11:40 PM PDT 24
Finished Jul 30 06:30:11 PM PDT 24
Peak memory 191696 kb
Host smart-f91fb0bf-6012-401e-abe6-cc62caee293d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898207648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.3898207648
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.3374997221
Short name T68
Test name
Test status
Simulation time 581175986044 ps
CPU time 770.07 seconds
Started Jul 30 06:11:27 PM PDT 24
Finished Jul 30 06:24:17 PM PDT 24
Peak memory 191648 kb
Host smart-06917051-082c-4e72-bd5e-0f299b19c75e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374997221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.3374997221
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.3640394566
Short name T141
Test name
Test status
Simulation time 1601043027309 ps
CPU time 2690.69 seconds
Started Jul 30 06:11:23 PM PDT 24
Finished Jul 30 06:56:16 PM PDT 24
Peak memory 191648 kb
Host smart-d83428e5-f979-41d4-85e4-72657c6e7134
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640394566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
3640394566
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.2649392126
Short name T33
Test name
Test status
Simulation time 31630538 ps
CPU time 0.52 seconds
Started Jul 30 06:10:53 PM PDT 24
Finished Jul 30 06:10:54 PM PDT 24
Peak memory 182948 kb
Host smart-922802ce-b51e-4717-82b9-a84840a7aec5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649392126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.2649392126
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.3892540327
Short name T34
Test name
Test status
Simulation time 243254521338 ps
CPU time 1002.56 seconds
Started Jul 30 06:11:24 PM PDT 24
Finished Jul 30 06:28:07 PM PDT 24
Peak memory 191712 kb
Host smart-8e14da01-0e81-4d65-8556-170a4485c525
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892540327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.3892540327
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.1155971851
Short name T169
Test name
Test status
Simulation time 1325853901856 ps
CPU time 2014.98 seconds
Started Jul 30 06:11:22 PM PDT 24
Finished Jul 30 06:44:58 PM PDT 24
Peak memory 191696 kb
Host smart-4acb949e-87f9-48fe-b3a5-25232970015b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155971851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.1155971851
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.1330063022
Short name T207
Test name
Test status
Simulation time 4770072936949 ps
CPU time 3936.81 seconds
Started Jul 30 06:11:38 PM PDT 24
Finished Jul 30 07:17:15 PM PDT 24
Peak memory 191616 kb
Host smart-af0a2e4d-de8d-46cd-aef4-cd192ee92240
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330063022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.1330063022
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.1960651002
Short name T291
Test name
Test status
Simulation time 238976662775 ps
CPU time 413.05 seconds
Started Jul 30 06:11:32 PM PDT 24
Finished Jul 30 06:18:26 PM PDT 24
Peak memory 194848 kb
Host smart-09daf4b1-e872-44c8-b783-f76f05c9343a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960651002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.1960651002
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.1640896388
Short name T114
Test name
Test status
Simulation time 1449481112419 ps
CPU time 851.36 seconds
Started Jul 30 06:11:07 PM PDT 24
Finished Jul 30 06:25:19 PM PDT 24
Peak memory 191672 kb
Host smart-3aa84654-67ac-4f68-9b83-7dbcd0eefec2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640896388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
1640896388
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.496425313
Short name T15
Test name
Test status
Simulation time 442002175 ps
CPU time 0.99 seconds
Started Jul 30 06:11:01 PM PDT 24
Finished Jul 30 06:11:02 PM PDT 24
Peak memory 215108 kb
Host smart-c1207651-64e5-4efb-b4d8-cc92cfb1a291
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496425313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.496425313
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.280588707
Short name T247
Test name
Test status
Simulation time 1835772371728 ps
CPU time 1568.51 seconds
Started Jul 30 06:11:32 PM PDT 24
Finished Jul 30 06:37:41 PM PDT 24
Peak memory 191700 kb
Host smart-4b940ba6-7d6e-4d09-8217-f7f7d6b2813e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280588707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all.
280588707
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.3790633398
Short name T35
Test name
Test status
Simulation time 198771120389 ps
CPU time 1335.89 seconds
Started Jul 30 06:11:26 PM PDT 24
Finished Jul 30 06:33:42 PM PDT 24
Peak memory 191684 kb
Host smart-b4ee42f2-69b5-440e-aa27-c9b657c1ca0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790633398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.3790633398
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.3455229443
Short name T201
Test name
Test status
Simulation time 2359100117100 ps
CPU time 1807.2 seconds
Started Jul 30 06:11:43 PM PDT 24
Finished Jul 30 06:41:51 PM PDT 24
Peak memory 191700 kb
Host smart-84d60236-3a3c-4f98-b4b6-40f234cc5640
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455229443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.3455229443
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/61.rv_timer_random.2235324634
Short name T21
Test name
Test status
Simulation time 404019697591 ps
CPU time 609.99 seconds
Started Jul 30 06:11:56 PM PDT 24
Finished Jul 30 06:22:06 PM PDT 24
Peak memory 191704 kb
Host smart-c14c61b1-cf01-4126-8a27-422fa8852e41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235324634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.2235324634
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.1386469043
Short name T195
Test name
Test status
Simulation time 764139945624 ps
CPU time 929.76 seconds
Started Jul 30 06:11:33 PM PDT 24
Finished Jul 30 06:27:03 PM PDT 24
Peak memory 191684 kb
Host smart-a17bf16d-3be4-4ba8-a674-7d336441e5d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386469043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.1386469043
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.3678082506
Short name T170
Test name
Test status
Simulation time 2068004068636 ps
CPU time 4762.39 seconds
Started Jul 30 06:11:19 PM PDT 24
Finished Jul 30 07:30:41 PM PDT 24
Peak memory 191656 kb
Host smart-226761de-69ea-4e2f-927b-297617040f74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678082506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
3678082506
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.366761951
Short name T200
Test name
Test status
Simulation time 454055885049 ps
CPU time 1933.59 seconds
Started Jul 30 06:11:28 PM PDT 24
Finished Jul 30 06:43:42 PM PDT 24
Peak memory 191664 kb
Host smart-5fca76e8-a3ab-44e9-bd93-944894754b2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366761951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all.
366761951
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.4044345302
Short name T69
Test name
Test status
Simulation time 712357395414 ps
CPU time 1025.97 seconds
Started Jul 30 06:11:20 PM PDT 24
Finished Jul 30 06:28:26 PM PDT 24
Peak memory 191632 kb
Host smart-e852f92a-1fe3-48a2-9ffc-a1076a1921fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044345302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.4044345302
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/194.rv_timer_random.4192293165
Short name T108
Test name
Test status
Simulation time 158473628665 ps
CPU time 1194.23 seconds
Started Jul 30 06:13:55 PM PDT 24
Finished Jul 30 06:33:50 PM PDT 24
Peak memory 191692 kb
Host smart-f61ab1a5-d693-479f-9b73-27753aaa7e57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192293165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.4192293165
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.1411973999
Short name T208
Test name
Test status
Simulation time 816167208060 ps
CPU time 1661.46 seconds
Started Jul 30 06:11:34 PM PDT 24
Finished Jul 30 06:39:16 PM PDT 24
Peak memory 191676 kb
Host smart-5a79cb0c-b85c-4bff-84f1-2c784b5055e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411973999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.1411973999
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/14.rv_timer_random.239666779
Short name T217
Test name
Test status
Simulation time 149867356961 ps
CPU time 1153.57 seconds
Started Jul 30 06:11:21 PM PDT 24
Finished Jul 30 06:30:35 PM PDT 24
Peak memory 191660 kb
Host smart-0f798750-fb55-4389-9aa1-371fcc024312
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239666779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.239666779
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.3443283309
Short name T189
Test name
Test status
Simulation time 332615763010 ps
CPU time 283.01 seconds
Started Jul 30 06:11:54 PM PDT 24
Finished Jul 30 06:16:37 PM PDT 24
Peak memory 191672 kb
Host smart-3dcc1977-83d4-4615-8f29-61ac13efa362
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443283309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.3443283309
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.653464746
Short name T113
Test name
Test status
Simulation time 369639795483 ps
CPU time 748.8 seconds
Started Jul 30 06:11:58 PM PDT 24
Finished Jul 30 06:24:27 PM PDT 24
Peak memory 191652 kb
Host smart-ca9daffd-d7ac-4932-aa72-0562aa60b5ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653464746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.653464746
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.658965649
Short name T165
Test name
Test status
Simulation time 912394890985 ps
CPU time 1264.94 seconds
Started Jul 30 06:12:10 PM PDT 24
Finished Jul 30 06:33:15 PM PDT 24
Peak memory 191676 kb
Host smart-5e17ec2e-cc57-46fb-ad76-bdb09219578c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658965649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.658965649
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.20035491
Short name T323
Test name
Test status
Simulation time 264216996612 ps
CPU time 1084.57 seconds
Started Jul 30 06:11:37 PM PDT 24
Finished Jul 30 06:29:42 PM PDT 24
Peak memory 191656 kb
Host smart-1c1d280d-aef7-4365-bf33-ec0bc1a36718
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20035491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all.20035491
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/135.rv_timer_random.514955188
Short name T283
Test name
Test status
Simulation time 160268427746 ps
CPU time 456.28 seconds
Started Jul 30 06:13:01 PM PDT 24
Finished Jul 30 06:20:37 PM PDT 24
Peak memory 191672 kb
Host smart-34cbfc45-a95a-4f70-a6d3-21cae595d95c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514955188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.514955188
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.4080882625
Short name T243
Test name
Test status
Simulation time 163585302675 ps
CPU time 548.34 seconds
Started Jul 30 06:13:44 PM PDT 24
Finished Jul 30 06:22:52 PM PDT 24
Peak memory 191680 kb
Host smart-816136fa-917f-46f5-816e-bbf37e018310
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080882625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.4080882625
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.286531958
Short name T203
Test name
Test status
Simulation time 681494125256 ps
CPU time 649.92 seconds
Started Jul 30 06:14:04 PM PDT 24
Finished Jul 30 06:24:54 PM PDT 24
Peak memory 191608 kb
Host smart-85332906-61cb-4e44-9f2d-42c3c47af678
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286531958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.286531958
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.58162750
Short name T90
Test name
Test status
Simulation time 251957339 ps
CPU time 0.65 seconds
Started Jul 30 06:10:49 PM PDT 24
Finished Jul 30 06:10:50 PM PDT 24
Peak memory 182940 kb
Host smart-b4e34957-d123-44e8-b277-564624724613
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58162750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_aliasi
ng.58162750
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/default/117.rv_timer_random.1412412234
Short name T134
Test name
Test status
Simulation time 121443197953 ps
CPU time 559.22 seconds
Started Jul 30 06:12:46 PM PDT 24
Finished Jul 30 06:22:05 PM PDT 24
Peak memory 191700 kb
Host smart-1227ea9d-e6df-4784-a5b9-3f397023a9f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412412234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.1412412234
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.3501739827
Short name T224
Test name
Test status
Simulation time 165379348097 ps
CPU time 1010.92 seconds
Started Jul 30 06:12:51 PM PDT 24
Finished Jul 30 06:29:42 PM PDT 24
Peak memory 191696 kb
Host smart-11a369d5-c96a-4f1e-90f0-a4d913a76de4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501739827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.3501739827
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.1853950218
Short name T176
Test name
Test status
Simulation time 104340535264 ps
CPU time 410.4 seconds
Started Jul 30 06:12:58 PM PDT 24
Finished Jul 30 06:19:48 PM PDT 24
Peak memory 191596 kb
Host smart-b6dfa1e5-b36f-42fa-84f1-5923ad6f3fa9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853950218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.1853950218
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.3905934058
Short name T311
Test name
Test status
Simulation time 163536429145 ps
CPU time 403.79 seconds
Started Jul 30 06:13:06 PM PDT 24
Finished Jul 30 06:19:50 PM PDT 24
Peak memory 191644 kb
Host smart-a2f727a3-1684-4833-95b1-bf6e869842e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905934058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.3905934058
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.2115101455
Short name T106
Test name
Test status
Simulation time 353975246431 ps
CPU time 164.13 seconds
Started Jul 30 06:13:53 PM PDT 24
Finished Jul 30 06:16:37 PM PDT 24
Peak memory 183472 kb
Host smart-bbe3e46f-919e-4a31-a937-f6e8ea9194be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115101455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.2115101455
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random.3074519972
Short name T216
Test name
Test status
Simulation time 648968313882 ps
CPU time 478.13 seconds
Started Jul 30 06:11:45 PM PDT 24
Finished Jul 30 06:19:43 PM PDT 24
Peak memory 191628 kb
Host smart-0c839667-5d34-4445-877b-d042341563d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074519972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.3074519972
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.1365157692
Short name T166
Test name
Test status
Simulation time 451253011839 ps
CPU time 392.26 seconds
Started Jul 30 06:11:08 PM PDT 24
Finished Jul 30 06:17:41 PM PDT 24
Peak memory 183380 kb
Host smart-3e551ee2-c1a2-4fe3-868e-cc17a0c6cd14
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365157692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.1365157692
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/128.rv_timer_random.662836130
Short name T60
Test name
Test status
Simulation time 127209882842 ps
CPU time 510.87 seconds
Started Jul 30 06:12:55 PM PDT 24
Finished Jul 30 06:21:26 PM PDT 24
Peak memory 191652 kb
Host smart-24f8c403-1c75-4875-b7dc-7a6ee8566bfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662836130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.662836130
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.1984897756
Short name T270
Test name
Test status
Simulation time 174377442599 ps
CPU time 244.9 seconds
Started Jul 30 06:13:18 PM PDT 24
Finished Jul 30 06:17:23 PM PDT 24
Peak memory 193984 kb
Host smart-7871e5e1-071c-4b34-880a-d287beae8b90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984897756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.1984897756
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.1135360483
Short name T324
Test name
Test status
Simulation time 1404756323928 ps
CPU time 926.21 seconds
Started Jul 30 06:13:51 PM PDT 24
Finished Jul 30 06:29:17 PM PDT 24
Peak memory 191684 kb
Host smart-260ff05f-e461-4bb7-8e0a-51c42dd02357
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135360483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.1135360483
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.2543795434
Short name T154
Test name
Test status
Simulation time 95763381789 ps
CPU time 1123.58 seconds
Started Jul 30 06:13:56 PM PDT 24
Finished Jul 30 06:32:40 PM PDT 24
Peak memory 191644 kb
Host smart-9ec394b1-b328-4d70-aca7-bb700f8ca460
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543795434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.2543795434
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.670682802
Short name T214
Test name
Test status
Simulation time 631674550267 ps
CPU time 1120.14 seconds
Started Jul 30 06:13:59 PM PDT 24
Finished Jul 30 06:32:40 PM PDT 24
Peak memory 191648 kb
Host smart-96aa9df6-ca63-4607-bbdb-c22205ae04b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670682802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.670682802
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.197312339
Short name T143
Test name
Test status
Simulation time 1804860583143 ps
CPU time 691.5 seconds
Started Jul 30 06:11:06 PM PDT 24
Finished Jul 30 06:22:38 PM PDT 24
Peak memory 191668 kb
Host smart-c708e6eb-ab2a-4775-b958-54e480bbe52b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197312339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.197312339
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/60.rv_timer_random.2965680730
Short name T138
Test name
Test status
Simulation time 316006951016 ps
CPU time 340.86 seconds
Started Jul 30 06:11:55 PM PDT 24
Finished Jul 30 06:17:36 PM PDT 24
Peak memory 191672 kb
Host smart-72c1b013-a13d-4004-be1e-c6d10b2b3e5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965680730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.2965680730
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.4058825714
Short name T285
Test name
Test status
Simulation time 139537031889 ps
CPU time 371.83 seconds
Started Jul 30 06:12:03 PM PDT 24
Finished Jul 30 06:18:15 PM PDT 24
Peak memory 195096 kb
Host smart-c4f251c6-fb29-408e-afa7-ac6699d6fde5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058825714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.4058825714
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/80.rv_timer_random.170791564
Short name T235
Test name
Test status
Simulation time 528424061060 ps
CPU time 480.91 seconds
Started Jul 30 06:12:10 PM PDT 24
Finished Jul 30 06:20:11 PM PDT 24
Peak memory 191660 kb
Host smart-9aed6c23-df67-4969-baa4-a15499f9a48f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170791564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.170791564
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random.384142324
Short name T255
Test name
Test status
Simulation time 113343826119 ps
CPU time 89.07 seconds
Started Jul 30 06:11:07 PM PDT 24
Finished Jul 30 06:12:36 PM PDT 24
Peak memory 191692 kb
Host smart-a0c15818-ba08-417d-8ae2-13cefc36ba49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384142324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.384142324
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.2069728425
Short name T2
Test name
Test status
Simulation time 391631331340 ps
CPU time 543.27 seconds
Started Jul 30 06:12:43 PM PDT 24
Finished Jul 30 06:21:47 PM PDT 24
Peak memory 191720 kb
Host smart-61a561ea-5b59-46f1-baeb-d367714d11c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069728425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.2069728425
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.3195751772
Short name T321
Test name
Test status
Simulation time 83332030524 ps
CPU time 346.56 seconds
Started Jul 30 06:12:49 PM PDT 24
Finished Jul 30 06:18:36 PM PDT 24
Peak memory 191672 kb
Host smart-65776ec6-3a0e-4d36-a422-6cc6ce876e2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195751772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.3195751772
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.1196601820
Short name T25
Test name
Test status
Simulation time 129374592115 ps
CPU time 102.31 seconds
Started Jul 30 06:12:56 PM PDT 24
Finished Jul 30 06:14:38 PM PDT 24
Peak memory 191620 kb
Host smart-5676965d-6da0-40c6-9103-768101e799ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196601820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.1196601820
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.4265904013
Short name T148
Test name
Test status
Simulation time 1288141139745 ps
CPU time 999.3 seconds
Started Jul 30 06:11:21 PM PDT 24
Finished Jul 30 06:28:00 PM PDT 24
Peak memory 197124 kb
Host smart-c2221416-d88c-4e28-bd4e-d800beec7f76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265904013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.4265904013
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/140.rv_timer_random.940387863
Short name T161
Test name
Test status
Simulation time 68295819196 ps
CPU time 114.69 seconds
Started Jul 30 06:13:08 PM PDT 24
Finished Jul 30 06:15:03 PM PDT 24
Peak memory 191660 kb
Host smart-b5dd15b3-3180-4845-8cd2-c729aa4e635a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940387863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.940387863
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.1130516862
Short name T222
Test name
Test status
Simulation time 768390642971 ps
CPU time 752.67 seconds
Started Jul 30 06:13:08 PM PDT 24
Finished Jul 30 06:25:41 PM PDT 24
Peak memory 191656 kb
Host smart-da947f5d-4242-4d10-8442-0399dff3b3d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130516862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.1130516862
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.581630094
Short name T278
Test name
Test status
Simulation time 148531778332 ps
CPU time 1321.94 seconds
Started Jul 30 06:13:10 PM PDT 24
Finished Jul 30 06:35:12 PM PDT 24
Peak memory 191708 kb
Host smart-28c4cd53-bbbc-4026-aa81-6eaaf5101823
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581630094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.581630094
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.2738734243
Short name T232
Test name
Test status
Simulation time 866369930579 ps
CPU time 568.38 seconds
Started Jul 30 06:13:40 PM PDT 24
Finished Jul 30 06:23:09 PM PDT 24
Peak memory 191688 kb
Host smart-62e79369-fd39-4737-ac30-118d44af6842
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738734243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.2738734243
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.3184332363
Short name T287
Test name
Test status
Simulation time 2943648951996 ps
CPU time 891.47 seconds
Started Jul 30 06:11:40 PM PDT 24
Finished Jul 30 06:26:32 PM PDT 24
Peak memory 196216 kb
Host smart-81c8e506-f22b-496f-9cd0-322d15e3b370
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184332363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.3184332363
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/196.rv_timer_random.843587663
Short name T263
Test name
Test status
Simulation time 640860879207 ps
CPU time 208.72 seconds
Started Jul 30 06:14:00 PM PDT 24
Finished Jul 30 06:17:29 PM PDT 24
Peak memory 191652 kb
Host smart-48479dfa-59ac-4864-b581-6e72c4a63a92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843587663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.843587663
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random.3914073614
Short name T236
Test name
Test status
Simulation time 195868522579 ps
CPU time 536.53 seconds
Started Jul 30 06:11:36 PM PDT 24
Finished Jul 30 06:20:33 PM PDT 24
Peak memory 191664 kb
Host smart-9d189ac2-61a2-424b-979e-79c162d7a5c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914073614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.3914073614
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.4236871667
Short name T230
Test name
Test status
Simulation time 1161148554885 ps
CPU time 584.61 seconds
Started Jul 30 06:11:39 PM PDT 24
Finished Jul 30 06:21:24 PM PDT 24
Peak memory 191600 kb
Host smart-4a262510-f90c-49f2-8e0e-5be68fdcd8ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236871667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.4236871667
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/73.rv_timer_random.2056772253
Short name T156
Test name
Test status
Simulation time 246065521879 ps
CPU time 1000.48 seconds
Started Jul 30 06:12:07 PM PDT 24
Finished Jul 30 06:28:47 PM PDT 24
Peak memory 191704 kb
Host smart-352216a1-f6fd-40b9-9cbb-97d09503c5ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056772253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.2056772253
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.3851049551
Short name T55
Test name
Test status
Simulation time 19630361 ps
CPU time 0.64 seconds
Started Jul 30 06:10:46 PM PDT 24
Finished Jul 30 06:10:47 PM PDT 24
Peak memory 192020 kb
Host smart-71ee9aed-22fd-475e-a37c-0bc64776b0ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851049551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.3851049551
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rv_timer_random.3420955791
Short name T314
Test name
Test status
Simulation time 340983845651 ps
CPU time 403.4 seconds
Started Jul 30 06:11:21 PM PDT 24
Finished Jul 30 06:18:04 PM PDT 24
Peak memory 191636 kb
Host smart-ec480716-29f4-4c95-998a-735524f0cc2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420955791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.3420955791
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all_with_rand_reset.2814041357
Short name T24
Test name
Test status
Simulation time 163326934020 ps
CPU time 1689.93 seconds
Started Jul 30 06:11:13 PM PDT 24
Finished Jul 30 06:39:23 PM PDT 24
Peak memory 220660 kb
Host smart-767c6c1e-fe4f-48f2-8015-76617efd6958
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814041357 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all_with_rand_reset.2814041357
Directory /workspace/0.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.173745826
Short name T139
Test name
Test status
Simulation time 469333009863 ps
CPU time 193.16 seconds
Started Jul 30 06:11:26 PM PDT 24
Finished Jul 30 06:14:40 PM PDT 24
Peak memory 183496 kb
Host smart-ee4ab996-3740-4b93-9a1c-345d756e04bf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173745826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.rv_timer_cfg_update_on_fly.173745826
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/131.rv_timer_random.4087042330
Short name T227
Test name
Test status
Simulation time 913558038360 ps
CPU time 414.89 seconds
Started Jul 30 06:12:55 PM PDT 24
Finished Jul 30 06:19:50 PM PDT 24
Peak memory 191692 kb
Host smart-1d72bdc3-a172-4102-8a78-eb16742c5666
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087042330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.4087042330
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.2325925653
Short name T122
Test name
Test status
Simulation time 554998426892 ps
CPU time 509.79 seconds
Started Jul 30 06:13:03 PM PDT 24
Finished Jul 30 06:21:33 PM PDT 24
Peak memory 194712 kb
Host smart-1144fbb7-8228-4ef4-a375-f91eeece1e90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325925653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.2325925653
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.3149677927
Short name T310
Test name
Test status
Simulation time 161329038934 ps
CPU time 1100.59 seconds
Started Jul 30 06:13:11 PM PDT 24
Finished Jul 30 06:31:32 PM PDT 24
Peak memory 191676 kb
Host smart-6bdcfd58-1e97-4775-82ef-403c23fa8c50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149677927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.3149677927
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.1223841165
Short name T340
Test name
Test status
Simulation time 183613325104 ps
CPU time 251.05 seconds
Started Jul 30 06:13:21 PM PDT 24
Finished Jul 30 06:17:32 PM PDT 24
Peak memory 191596 kb
Host smart-6915b79b-8896-4bed-8654-62df759a93b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223841165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.1223841165
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.1402691896
Short name T183
Test name
Test status
Simulation time 207185745884 ps
CPU time 199.45 seconds
Started Jul 30 06:13:47 PM PDT 24
Finished Jul 30 06:17:06 PM PDT 24
Peak memory 191692 kb
Host smart-f700a883-1f72-42f0-8a84-5f5577c2f095
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402691896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.1402691896
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random.1938109678
Short name T218
Test name
Test status
Simulation time 820753129872 ps
CPU time 214.75 seconds
Started Jul 30 06:11:21 PM PDT 24
Finished Jul 30 06:14:56 PM PDT 24
Peak memory 191632 kb
Host smart-89810ca8-359a-4ce6-9c6f-836453e75a64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938109678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.1938109678
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.2509236955
Short name T351
Test name
Test status
Simulation time 19874806205 ps
CPU time 10.25 seconds
Started Jul 30 06:11:32 PM PDT 24
Finished Jul 30 06:11:42 PM PDT 24
Peak memory 195704 kb
Host smart-fb2beeec-4b6f-446f-b035-8bbcc020db67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509236955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.2509236955
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.3299617164
Short name T150
Test name
Test status
Simulation time 1857997173643 ps
CPU time 704.15 seconds
Started Jul 30 06:11:39 PM PDT 24
Finished Jul 30 06:23:23 PM PDT 24
Peak memory 183428 kb
Host smart-b80d9e0c-db22-477a-8014-cc1bec9f284e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299617164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.3299617164
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_random.2287689295
Short name T304
Test name
Test status
Simulation time 54447752192 ps
CPU time 86.46 seconds
Started Jul 30 06:11:41 PM PDT 24
Finished Jul 30 06:13:08 PM PDT 24
Peak memory 195060 kb
Host smart-af4338bd-b681-44df-a39e-15fec9a26989
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287689295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.2287689295
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.2112830512
Short name T107
Test name
Test status
Simulation time 627689845092 ps
CPU time 290.78 seconds
Started Jul 30 06:11:40 PM PDT 24
Finished Jul 30 06:16:31 PM PDT 24
Peak memory 183432 kb
Host smart-b991092c-ed86-4804-8cc2-d281ccbf5e3b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112830512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.2112830512
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.2096081521
Short name T66
Test name
Test status
Simulation time 231774600383 ps
CPU time 101.79 seconds
Started Jul 30 06:11:36 PM PDT 24
Finished Jul 30 06:13:18 PM PDT 24
Peak memory 191644 kb
Host smart-74b49b86-ee57-47d6-8a51-57ecaae39478
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096081521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.2096081521
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.1275874170
Short name T246
Test name
Test status
Simulation time 553940595761 ps
CPU time 963.13 seconds
Started Jul 30 06:11:38 PM PDT 24
Finished Jul 30 06:27:41 PM PDT 24
Peak memory 191660 kb
Host smart-11a7396d-49e8-42d7-9c1e-8f22b33a0128
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275874170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.1275874170
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1279942590
Short name T102
Test name
Test status
Simulation time 172446938 ps
CPU time 1.4 seconds
Started Jul 30 06:10:55 PM PDT 24
Finished Jul 30 06:10:57 PM PDT 24
Peak memory 195728 kb
Host smart-64ad286a-34e3-4f3c-ab53-dde5f78f0f33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279942590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.1279942590
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/101.rv_timer_random.3099511144
Short name T198
Test name
Test status
Simulation time 322019647875 ps
CPU time 184.96 seconds
Started Jul 30 06:12:35 PM PDT 24
Finished Jul 30 06:15:40 PM PDT 24
Peak memory 191644 kb
Host smart-639bf29c-6c3f-4743-b3d4-4a11beb47a67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099511144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.3099511144
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.2416933350
Short name T336
Test name
Test status
Simulation time 70975990263 ps
CPU time 101.62 seconds
Started Jul 30 06:12:32 PM PDT 24
Finished Jul 30 06:14:14 PM PDT 24
Peak memory 191676 kb
Host smart-8e3a422c-2818-4f9d-be8f-71184bb34684
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416933350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.2416933350
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.4107377304
Short name T187
Test name
Test status
Simulation time 1405369081251 ps
CPU time 364.69 seconds
Started Jul 30 06:12:36 PM PDT 24
Finished Jul 30 06:18:41 PM PDT 24
Peak memory 191692 kb
Host smart-fcdc3183-9160-4faf-879a-cd1545ed1503
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107377304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.4107377304
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.105388371
Short name T26
Test name
Test status
Simulation time 1162263645582 ps
CPU time 342.17 seconds
Started Jul 30 06:12:38 PM PDT 24
Finished Jul 30 06:18:20 PM PDT 24
Peak memory 191648 kb
Host smart-e37358fc-5557-435f-8726-a2474f7670b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105388371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.105388371
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.89225751
Short name T349
Test name
Test status
Simulation time 142688934097 ps
CPU time 222.56 seconds
Started Jul 30 06:12:49 PM PDT 24
Finished Jul 30 06:16:31 PM PDT 24
Peak memory 195232 kb
Host smart-5f41b381-8352-415a-822f-ed19db7cdf8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89225751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.89225751
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.1547308926
Short name T162
Test name
Test status
Simulation time 148889734883 ps
CPU time 79.47 seconds
Started Jul 30 06:11:20 PM PDT 24
Finished Jul 30 06:12:40 PM PDT 24
Peak memory 183464 kb
Host smart-3b7ba66e-0b56-4f9e-a37b-6bc18d4d98e3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547308926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.1547308926
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all_with_rand_reset.2948363344
Short name T39
Test name
Test status
Simulation time 110163728411 ps
CPU time 275.1 seconds
Started Jul 30 06:11:21 PM PDT 24
Finished Jul 30 06:15:56 PM PDT 24
Peak memory 206308 kb
Host smart-05d06c33-370a-4803-9cf4-f6d01ce6c97a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948363344 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all_with_rand_reset.2948363344
Directory /workspace/12.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rv_timer_random.2059265138
Short name T175
Test name
Test status
Simulation time 395180121512 ps
CPU time 201.92 seconds
Started Jul 30 06:11:34 PM PDT 24
Finished Jul 30 06:14:56 PM PDT 24
Peak memory 191620 kb
Host smart-b97e2fdb-9d8f-47d3-952c-9e560fda16f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059265138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.2059265138
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.1294297317
Short name T110
Test name
Test status
Simulation time 243970055701 ps
CPU time 995.23 seconds
Started Jul 30 06:11:18 PM PDT 24
Finished Jul 30 06:27:54 PM PDT 24
Peak memory 183452 kb
Host smart-2cf8983c-8a78-4557-8cc7-7fa7809376d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294297317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.1294297317
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/143.rv_timer_random.3616545571
Short name T252
Test name
Test status
Simulation time 514449765871 ps
CPU time 196.59 seconds
Started Jul 30 06:13:06 PM PDT 24
Finished Jul 30 06:16:23 PM PDT 24
Peak memory 191644 kb
Host smart-c8e69333-df5e-423b-9a9f-6298c2177dbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616545571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.3616545571
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random.1249901381
Short name T186
Test name
Test status
Simulation time 113232786661 ps
CPU time 202.06 seconds
Started Jul 30 06:11:21 PM PDT 24
Finished Jul 30 06:14:43 PM PDT 24
Peak memory 191560 kb
Host smart-7b8df26e-5e26-4363-b47b-3c4578a26d1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249901381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.1249901381
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.837859219
Short name T250
Test name
Test status
Simulation time 407989783356 ps
CPU time 604.59 seconds
Started Jul 30 06:13:29 PM PDT 24
Finished Jul 30 06:23:34 PM PDT 24
Peak memory 191672 kb
Host smart-2d2ace4a-e880-48e4-8e7a-a65285729f86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837859219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.837859219
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.2556764596
Short name T266
Test name
Test status
Simulation time 241828418095 ps
CPU time 270.66 seconds
Started Jul 30 06:11:22 PM PDT 24
Finished Jul 30 06:15:53 PM PDT 24
Peak memory 183456 kb
Host smart-c2ed7691-324b-4b38-8bfb-29e98b54a234
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556764596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.2556764596
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/181.rv_timer_random.2506183795
Short name T127
Test name
Test status
Simulation time 65382874682 ps
CPU time 104.31 seconds
Started Jul 30 06:13:51 PM PDT 24
Finished Jul 30 06:15:36 PM PDT 24
Peak memory 191616 kb
Host smart-ce637514-d23a-4698-a14a-17aa29dbc4d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506183795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.2506183795
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.952282901
Short name T47
Test name
Test status
Simulation time 6155518414 ps
CPU time 31.27 seconds
Started Jul 30 06:13:48 PM PDT 24
Finished Jul 30 06:14:20 PM PDT 24
Peak memory 183412 kb
Host smart-5a08d165-629a-4839-be90-040383eaba03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952282901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.952282901
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.3545669714
Short name T223
Test name
Test status
Simulation time 236108411235 ps
CPU time 999.67 seconds
Started Jul 30 06:13:49 PM PDT 24
Finished Jul 30 06:30:29 PM PDT 24
Peak memory 195100 kb
Host smart-fa608ba7-b145-4ca4-a930-4fedbae05782
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545669714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.3545669714
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.668722907
Short name T294
Test name
Test status
Simulation time 58747027450 ps
CPU time 145.17 seconds
Started Jul 30 06:13:51 PM PDT 24
Finished Jul 30 06:16:16 PM PDT 24
Peak memory 191808 kb
Host smart-512ff079-57de-4800-8dc2-1e30a92a74cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668722907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.668722907
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.391924500
Short name T144
Test name
Test status
Simulation time 853615093548 ps
CPU time 1099.5 seconds
Started Jul 30 06:11:20 PM PDT 24
Finished Jul 30 06:29:40 PM PDT 24
Peak memory 183464 kb
Host smart-34153a8a-33b4-45a2-89fd-9e9aef5f81bb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391924500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.rv_timer_cfg_update_on_fly.391924500
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_random.1616720533
Short name T277
Test name
Test status
Simulation time 312013909354 ps
CPU time 351.75 seconds
Started Jul 30 06:11:40 PM PDT 24
Finished Jul 30 06:17:32 PM PDT 24
Peak memory 191620 kb
Host smart-19eaa57f-404c-4303-95c8-64cf5f335d70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616720533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.1616720533
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.2071547954
Short name T350
Test name
Test status
Simulation time 26143488620 ps
CPU time 49.04 seconds
Started Jul 30 06:11:39 PM PDT 24
Finished Jul 30 06:12:29 PM PDT 24
Peak memory 183376 kb
Host smart-ef24f952-552b-434f-905e-79ae8aba5630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071547954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.2071547954
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.2680491014
Short name T302
Test name
Test status
Simulation time 139069302885 ps
CPU time 42.56 seconds
Started Jul 30 06:11:46 PM PDT 24
Finished Jul 30 06:12:29 PM PDT 24
Peak memory 183468 kb
Host smart-a41ddef1-1a1a-420e-b643-c422ff6e9c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680491014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.2680491014
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_random.1642483573
Short name T257
Test name
Test status
Simulation time 737571087026 ps
CPU time 1321.27 seconds
Started Jul 30 06:11:25 PM PDT 24
Finished Jul 30 06:33:26 PM PDT 24
Peak memory 191716 kb
Host smart-72fa01b1-85cc-4563-827d-4fb7526642b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642483573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.1642483573
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.2100551181
Short name T229
Test name
Test status
Simulation time 422159190799 ps
CPU time 535.64 seconds
Started Jul 30 06:11:11 PM PDT 24
Finished Jul 30 06:20:07 PM PDT 24
Peak memory 191692 kb
Host smart-77ed2a55-e910-4e13-b70e-018520681136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100551181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.2100551181
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_random.2567164880
Short name T73
Test name
Test status
Simulation time 118039271684 ps
CPU time 225.29 seconds
Started Jul 30 06:11:40 PM PDT 24
Finished Jul 30 06:15:26 PM PDT 24
Peak memory 191620 kb
Host smart-45ad1847-6642-4348-a065-93203cc5d20f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567164880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.2567164880
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.2575899535
Short name T164
Test name
Test status
Simulation time 163167061027 ps
CPU time 279.16 seconds
Started Jul 30 06:12:08 PM PDT 24
Finished Jul 30 06:16:47 PM PDT 24
Peak memory 191612 kb
Host smart-ef495963-525e-4589-a208-c9e22816d6ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575899535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.2575899535
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3114109663
Short name T564
Test name
Test status
Simulation time 74728195 ps
CPU time 1.43 seconds
Started Jul 30 06:10:41 PM PDT 24
Finished Jul 30 06:10:43 PM PDT 24
Peak memory 194120 kb
Host smart-dad41c71-9b71-4344-9f62-508c04001ee5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114109663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.3114109663
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.1687683643
Short name T486
Test name
Test status
Simulation time 19141382 ps
CPU time 0.59 seconds
Started Jul 30 06:10:49 PM PDT 24
Finished Jul 30 06:10:50 PM PDT 24
Peak memory 183024 kb
Host smart-935ec538-a7e8-44e6-b75f-977931586a80
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687683643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.1687683643
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.3561692766
Short name T552
Test name
Test status
Simulation time 25252245 ps
CPU time 1.13 seconds
Started Jul 30 06:10:40 PM PDT 24
Finished Jul 30 06:10:41 PM PDT 24
Peak memory 197736 kb
Host smart-7a76ed2c-9c41-4cdb-bc21-06ea2b004865
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561692766 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.3561692766
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.3574084984
Short name T78
Test name
Test status
Simulation time 17463708 ps
CPU time 0.56 seconds
Started Jul 30 06:10:37 PM PDT 24
Finished Jul 30 06:10:38 PM PDT 24
Peak memory 182880 kb
Host smart-fa4416cb-5a9a-4317-9059-2479df7fd134
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574084984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.3574084984
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.3192652336
Short name T541
Test name
Test status
Simulation time 21349584 ps
CPU time 0.53 seconds
Started Jul 30 06:10:37 PM PDT 24
Finished Jul 30 06:10:38 PM PDT 24
Peak memory 182212 kb
Host smart-816672f9-0609-4a3c-951a-cf6c888d5cc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192652336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.3192652336
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2375501065
Short name T530
Test name
Test status
Simulation time 194849732 ps
CPU time 1.86 seconds
Started Jul 30 06:10:34 PM PDT 24
Finished Jul 30 06:10:36 PM PDT 24
Peak memory 197648 kb
Host smart-096525f5-fb20-4fff-ae7d-1978486aff43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375501065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.2375501065
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.3353167523
Short name T510
Test name
Test status
Simulation time 91441806 ps
CPU time 1.19 seconds
Started Jul 30 06:10:49 PM PDT 24
Finished Jul 30 06:10:51 PM PDT 24
Peak memory 183432 kb
Host smart-eb7c3266-848d-4d18-b0f3-324be8b78bb4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353167523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.3353167523
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.2658870270
Short name T551
Test name
Test status
Simulation time 18712736 ps
CPU time 0.61 seconds
Started Jul 30 06:10:49 PM PDT 24
Finished Jul 30 06:10:49 PM PDT 24
Peak memory 182788 kb
Host smart-22f06d0b-3934-4450-8fb3-7b3390d14334
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658870270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.2658870270
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.868199137
Short name T583
Test name
Test status
Simulation time 373273229 ps
CPU time 3.67 seconds
Started Jul 30 06:10:35 PM PDT 24
Finished Jul 30 06:10:39 PM PDT 24
Peak memory 194208 kb
Host smart-a6796428-4a03-418f-b1aa-2b5e6b5ef1e7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868199137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_b
ash.868199137
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1821733013
Short name T82
Test name
Test status
Simulation time 21064973 ps
CPU time 0.57 seconds
Started Jul 30 06:10:39 PM PDT 24
Finished Jul 30 06:10:40 PM PDT 24
Peak memory 182956 kb
Host smart-bc4aea82-d8e3-4562-9e11-f9355c57e465
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821733013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.1821733013
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.3060840691
Short name T505
Test name
Test status
Simulation time 25835525 ps
CPU time 0.82 seconds
Started Jul 30 06:10:37 PM PDT 24
Finished Jul 30 06:10:38 PM PDT 24
Peak memory 196472 kb
Host smart-20169e62-dafe-4380-949e-b7f1bf951a4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060840691 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.3060840691
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.1291873064
Short name T525
Test name
Test status
Simulation time 32649368 ps
CPU time 0.57 seconds
Started Jul 30 06:10:37 PM PDT 24
Finished Jul 30 06:10:38 PM PDT 24
Peak memory 182572 kb
Host smart-7e7f10d2-a57e-4dde-a94c-e3eeaa2900f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291873064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.1291873064
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.1688230576
Short name T468
Test name
Test status
Simulation time 33802225 ps
CPU time 0.52 seconds
Started Jul 30 06:10:47 PM PDT 24
Finished Jul 30 06:10:48 PM PDT 24
Peak memory 182312 kb
Host smart-36d0d4e0-1097-4408-9d26-00aa2b87b7e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688230576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.1688230576
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.2407192065
Short name T77
Test name
Test status
Simulation time 145066516 ps
CPU time 0.76 seconds
Started Jul 30 06:10:52 PM PDT 24
Finished Jul 30 06:10:53 PM PDT 24
Peak memory 194224 kb
Host smart-3d828edd-d379-4b12-a7e7-e3a9729b0e7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407192065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.2407192065
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.2334087179
Short name T487
Test name
Test status
Simulation time 262115413 ps
CPU time 2.4 seconds
Started Jul 30 06:10:44 PM PDT 24
Finished Jul 30 06:10:46 PM PDT 24
Peak memory 197680 kb
Host smart-ec26e1e7-da35-456d-88d9-97ae9b158705
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334087179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.2334087179
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.786628315
Short name T532
Test name
Test status
Simulation time 398060290 ps
CPU time 1.39 seconds
Started Jul 30 06:10:44 PM PDT 24
Finished Jul 30 06:10:46 PM PDT 24
Peak memory 195308 kb
Host smart-57d7deb0-1031-45bc-9dac-f2b77d1e9161
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786628315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_int
g_err.786628315
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.4287281258
Short name T522
Test name
Test status
Simulation time 17755964 ps
CPU time 0.71 seconds
Started Jul 30 06:10:49 PM PDT 24
Finished Jul 30 06:10:50 PM PDT 24
Peak memory 195708 kb
Host smart-b0108cba-cb3f-423b-99de-0d983e0b9ef8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287281258 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.4287281258
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.1135379448
Short name T477
Test name
Test status
Simulation time 14839491 ps
CPU time 0.57 seconds
Started Jul 30 06:10:48 PM PDT 24
Finished Jul 30 06:10:49 PM PDT 24
Peak memory 182700 kb
Host smart-8f2c115e-50d4-4cef-9e76-85c6b47c73b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135379448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.1135379448
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1428106205
Short name T521
Test name
Test status
Simulation time 80775555 ps
CPU time 0.59 seconds
Started Jul 30 06:10:49 PM PDT 24
Finished Jul 30 06:10:50 PM PDT 24
Peak memory 182788 kb
Host smart-04764f62-4b48-4885-bc01-d04565761dd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428106205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.1428106205
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.4261736949
Short name T79
Test name
Test status
Simulation time 23256410 ps
CPU time 0.83 seconds
Started Jul 30 06:10:52 PM PDT 24
Finished Jul 30 06:10:53 PM PDT 24
Peak memory 193584 kb
Host smart-84d5fc4a-6fe0-4dac-9a8e-f82ffc839e35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261736949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.4261736949
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.3499604050
Short name T546
Test name
Test status
Simulation time 113071371 ps
CPU time 1.92 seconds
Started Jul 30 06:10:45 PM PDT 24
Finished Jul 30 06:10:47 PM PDT 24
Peak memory 197664 kb
Host smart-95d08c4e-52e6-440f-886e-e5251207d910
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499604050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.3499604050
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.4269156236
Short name T538
Test name
Test status
Simulation time 266462029 ps
CPU time 0.76 seconds
Started Jul 30 06:10:48 PM PDT 24
Finished Jul 30 06:10:49 PM PDT 24
Peak memory 195240 kb
Host smart-f0a8e020-5686-48fc-bcdc-5c80579d6481
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269156236 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.4269156236
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.3635245019
Short name T517
Test name
Test status
Simulation time 15746241 ps
CPU time 0.6 seconds
Started Jul 30 06:10:45 PM PDT 24
Finished Jul 30 06:10:45 PM PDT 24
Peak memory 182948 kb
Host smart-676e65f1-b4dc-496c-a24c-0e7262d72847
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635245019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.3635245019
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.4249753870
Short name T560
Test name
Test status
Simulation time 90903350 ps
CPU time 0.53 seconds
Started Jul 30 06:10:53 PM PDT 24
Finished Jul 30 06:10:54 PM PDT 24
Peak memory 182684 kb
Host smart-e13942fc-1e70-41f1-8f83-932b1d9f6079
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249753870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.4249753870
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3069471125
Short name T524
Test name
Test status
Simulation time 17034541 ps
CPU time 0.69 seconds
Started Jul 30 06:10:51 PM PDT 24
Finished Jul 30 06:10:51 PM PDT 24
Peak memory 193304 kb
Host smart-857cad1e-dfc4-44e0-a409-bccd64b8cb72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069471125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.3069471125
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.297165786
Short name T554
Test name
Test status
Simulation time 1502501080 ps
CPU time 2.35 seconds
Started Jul 30 06:10:52 PM PDT 24
Finished Jul 30 06:10:55 PM PDT 24
Peak memory 197696 kb
Host smart-7bac8d2b-355d-430a-9613-b7f1f377f6da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297165786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.297165786
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.1748198623
Short name T99
Test name
Test status
Simulation time 117704308 ps
CPU time 1.39 seconds
Started Jul 30 06:10:46 PM PDT 24
Finished Jul 30 06:10:47 PM PDT 24
Peak memory 195720 kb
Host smart-b33d3d0c-11e8-4786-8054-fbab487c9bb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748198623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.1748198623
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.2773482230
Short name T503
Test name
Test status
Simulation time 42049532 ps
CPU time 1.89 seconds
Started Jul 30 06:10:46 PM PDT 24
Finished Jul 30 06:10:48 PM PDT 24
Peak memory 197784 kb
Host smart-a0a16d0d-d4df-4e7a-a925-245cfe9eccb6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773482230 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.2773482230
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2648834079
Short name T81
Test name
Test status
Simulation time 13038187 ps
CPU time 0.57 seconds
Started Jul 30 06:10:55 PM PDT 24
Finished Jul 30 06:10:56 PM PDT 24
Peak memory 182932 kb
Host smart-a5b50e7d-d2dd-4c5d-83c1-33888ad93b3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648834079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.2648834079
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.2454385202
Short name T526
Test name
Test status
Simulation time 46219843 ps
CPU time 0.58 seconds
Started Jul 30 06:10:50 PM PDT 24
Finished Jul 30 06:10:51 PM PDT 24
Peak memory 182848 kb
Host smart-530a7253-809d-49e3-b5e6-02281780140e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454385202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.2454385202
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.4200390288
Short name T529
Test name
Test status
Simulation time 29440899 ps
CPU time 0.72 seconds
Started Jul 30 06:10:47 PM PDT 24
Finished Jul 30 06:10:48 PM PDT 24
Peak memory 192396 kb
Host smart-f398733a-50ea-4154-b627-1d4c956405f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200390288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.4200390288
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.2273561947
Short name T467
Test name
Test status
Simulation time 59231103 ps
CPU time 1.55 seconds
Started Jul 30 06:10:48 PM PDT 24
Finished Jul 30 06:10:49 PM PDT 24
Peak memory 197728 kb
Host smart-4a9d5dbf-5ee6-4483-86e6-16a58a5a6e62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273561947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.2273561947
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.555464806
Short name T473
Test name
Test status
Simulation time 135788624 ps
CPU time 0.77 seconds
Started Jul 30 06:10:51 PM PDT 24
Finished Jul 30 06:10:52 PM PDT 24
Peak memory 196196 kb
Host smart-84d32fc9-ef3e-40a0-8816-1bf0ad667347
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555464806 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.555464806
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.1763551626
Short name T83
Test name
Test status
Simulation time 11748734 ps
CPU time 0.59 seconds
Started Jul 30 06:10:52 PM PDT 24
Finished Jul 30 06:10:53 PM PDT 24
Peak memory 182888 kb
Host smart-bbf740f7-5656-4420-afe6-3fe867d38a16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763551626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.1763551626
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.933428633
Short name T540
Test name
Test status
Simulation time 14578766 ps
CPU time 0.53 seconds
Started Jul 30 06:10:56 PM PDT 24
Finished Jul 30 06:10:57 PM PDT 24
Peak memory 182256 kb
Host smart-0efe910a-11e6-4729-b513-cd5185d1b528
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933428633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.933428633
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.8401839
Short name T569
Test name
Test status
Simulation time 236564351 ps
CPU time 0.7 seconds
Started Jul 30 06:10:51 PM PDT 24
Finished Jul 30 06:10:52 PM PDT 24
Peak memory 192456 kb
Host smart-43c3e514-b43b-43b1-b1db-2b10c5acc343
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8401839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_t
imer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_time
r_same_csr_outstanding.8401839
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.1373791104
Short name T474
Test name
Test status
Simulation time 104222223 ps
CPU time 1.55 seconds
Started Jul 30 06:10:48 PM PDT 24
Finished Jul 30 06:10:49 PM PDT 24
Peak memory 197664 kb
Host smart-67bae1ed-0764-4bb9-a22e-bbc7374c7edf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373791104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.1373791104
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.153291100
Short name T100
Test name
Test status
Simulation time 833101024 ps
CPU time 1.31 seconds
Started Jul 30 06:10:57 PM PDT 24
Finished Jul 30 06:10:59 PM PDT 24
Peak memory 183496 kb
Host smart-05007079-09b2-4b98-92d4-622f3a902710
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153291100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_in
tg_err.153291100
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.2472093475
Short name T490
Test name
Test status
Simulation time 20443535 ps
CPU time 0.71 seconds
Started Jul 30 06:10:55 PM PDT 24
Finished Jul 30 06:10:56 PM PDT 24
Peak memory 194948 kb
Host smart-9fda71d7-d344-4942-98ce-0388ae46ddf7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472093475 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.2472093475
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.3096813251
Short name T488
Test name
Test status
Simulation time 14486131 ps
CPU time 0.55 seconds
Started Jul 30 06:10:59 PM PDT 24
Finished Jul 30 06:10:59 PM PDT 24
Peak memory 182768 kb
Host smart-d17e9142-2327-4591-80e5-ebb0681f4b91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096813251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.3096813251
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.1215423021
Short name T92
Test name
Test status
Simulation time 70945559 ps
CPU time 0.79 seconds
Started Jul 30 06:10:53 PM PDT 24
Finished Jul 30 06:10:54 PM PDT 24
Peak memory 193780 kb
Host smart-86e0ce33-7962-4d93-a8d6-2e67989dd09d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215423021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.1215423021
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2783480196
Short name T457
Test name
Test status
Simulation time 1109882468 ps
CPU time 2.22 seconds
Started Jul 30 06:10:56 PM PDT 24
Finished Jul 30 06:10:59 PM PDT 24
Peak memory 197640 kb
Host smart-b3e4c2fa-3908-4d91-9e52-e71b48433acc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783480196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.2783480196
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.1045930015
Short name T495
Test name
Test status
Simulation time 378594548 ps
CPU time 1.08 seconds
Started Jul 30 06:10:48 PM PDT 24
Finished Jul 30 06:10:49 PM PDT 24
Peak memory 183368 kb
Host smart-52980921-bd9f-40ed-add9-1d04fea822f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045930015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.1045930015
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.439283005
Short name T549
Test name
Test status
Simulation time 66933174 ps
CPU time 0.69 seconds
Started Jul 30 06:10:53 PM PDT 24
Finished Jul 30 06:10:54 PM PDT 24
Peak memory 194244 kb
Host smart-8ab563e9-021e-4294-b8b4-fa99f21daaa1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439283005 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.439283005
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.1245770378
Short name T513
Test name
Test status
Simulation time 89389708 ps
CPU time 0.59 seconds
Started Jul 30 06:10:55 PM PDT 24
Finished Jul 30 06:10:56 PM PDT 24
Peak memory 182952 kb
Host smart-01258776-329f-401f-8bb3-0a9adb2cde4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245770378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.1245770378
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.3269590145
Short name T476
Test name
Test status
Simulation time 19300809 ps
CPU time 0.56 seconds
Started Jul 30 06:10:50 PM PDT 24
Finished Jul 30 06:10:51 PM PDT 24
Peak memory 182724 kb
Host smart-2998c106-6b47-4d0a-b427-ddbf6320df24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269590145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.3269590145
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.354600027
Short name T504
Test name
Test status
Simulation time 61762161 ps
CPU time 0.61 seconds
Started Jul 30 06:10:51 PM PDT 24
Finished Jul 30 06:10:52 PM PDT 24
Peak memory 191920 kb
Host smart-1024d0aa-1c78-418b-ae17-305194ecd964
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354600027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_ti
mer_same_csr_outstanding.354600027
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.4193169928
Short name T496
Test name
Test status
Simulation time 162614340 ps
CPU time 1.83 seconds
Started Jul 30 06:10:56 PM PDT 24
Finished Jul 30 06:10:58 PM PDT 24
Peak memory 197652 kb
Host smart-8d164c97-8bb5-489c-90a3-ddc7cfcd78ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193169928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.4193169928
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.2668364579
Short name T103
Test name
Test status
Simulation time 52263751 ps
CPU time 0.82 seconds
Started Jul 30 06:10:48 PM PDT 24
Finished Jul 30 06:10:49 PM PDT 24
Peak memory 193448 kb
Host smart-bfc9bf8c-b2c3-4dc0-93bc-38ce1364d54a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668364579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.2668364579
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.2535581352
Short name T556
Test name
Test status
Simulation time 94207055 ps
CPU time 0.65 seconds
Started Jul 30 06:10:53 PM PDT 24
Finished Jul 30 06:10:54 PM PDT 24
Peak memory 194044 kb
Host smart-2857ec07-271e-42ef-a6f3-d729251df963
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535581352 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.2535581352
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.3834145117
Short name T579
Test name
Test status
Simulation time 16465051 ps
CPU time 0.55 seconds
Started Jul 30 06:10:59 PM PDT 24
Finished Jul 30 06:10:59 PM PDT 24
Peak memory 182744 kb
Host smart-6203bb2f-d2f6-40f3-a6ce-513f0a4d33db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834145117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.3834145117
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.831459697
Short name T466
Test name
Test status
Simulation time 39046675 ps
CPU time 0.53 seconds
Started Jul 30 06:10:56 PM PDT 24
Finished Jul 30 06:10:57 PM PDT 24
Peak memory 182216 kb
Host smart-b31b579d-e796-4ded-8321-d7a20061a9ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831459697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.831459697
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.296036925
Short name T94
Test name
Test status
Simulation time 20234439 ps
CPU time 0.61 seconds
Started Jul 30 06:10:49 PM PDT 24
Finished Jul 30 06:10:50 PM PDT 24
Peak memory 191536 kb
Host smart-77e26932-cc1d-49dc-84a9-8cb2b60b417b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296036925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_ti
mer_same_csr_outstanding.296036925
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.1734290588
Short name T464
Test name
Test status
Simulation time 137691781 ps
CPU time 2.78 seconds
Started Jul 30 06:10:52 PM PDT 24
Finished Jul 30 06:10:55 PM PDT 24
Peak memory 197704 kb
Host smart-e5161e70-caac-4aa4-9f6a-82610445e77d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734290588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.1734290588
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.978886152
Short name T580
Test name
Test status
Simulation time 80855277 ps
CPU time 0.85 seconds
Started Jul 30 06:10:54 PM PDT 24
Finished Jul 30 06:10:54 PM PDT 24
Peak memory 194176 kb
Host smart-e16acc3d-aa11-437f-9777-38f2d12e39e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978886152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_in
tg_err.978886152
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.928686000
Short name T480
Test name
Test status
Simulation time 136976768 ps
CPU time 0.67 seconds
Started Jul 30 06:10:57 PM PDT 24
Finished Jul 30 06:10:58 PM PDT 24
Peak memory 194648 kb
Host smart-03f17af6-be73-4da4-881a-d3d9ebe41730
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928686000 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.928686000
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.126518743
Short name T89
Test name
Test status
Simulation time 51091399 ps
CPU time 0.57 seconds
Started Jul 30 06:10:54 PM PDT 24
Finished Jul 30 06:10:55 PM PDT 24
Peak memory 182956 kb
Host smart-0434df10-dcb9-4447-9650-e0c3c2ff467e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126518743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.126518743
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.556274634
Short name T461
Test name
Test status
Simulation time 232654896 ps
CPU time 0.59 seconds
Started Jul 30 06:11:05 PM PDT 24
Finished Jul 30 06:11:05 PM PDT 24
Peak memory 182772 kb
Host smart-22ca1a25-647c-42cd-bd99-6555dc26355f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556274634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.556274634
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2595573908
Short name T93
Test name
Test status
Simulation time 67935902 ps
CPU time 0.89 seconds
Started Jul 30 06:10:53 PM PDT 24
Finished Jul 30 06:10:54 PM PDT 24
Peak memory 193748 kb
Host smart-8ff50367-1866-47ec-a527-5ea799298b2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595573908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.2595573908
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.1813349099
Short name T528
Test name
Test status
Simulation time 343148345 ps
CPU time 1.63 seconds
Started Jul 30 06:10:58 PM PDT 24
Finished Jul 30 06:11:00 PM PDT 24
Peak memory 197616 kb
Host smart-531f5242-2bf6-4219-9ecf-bf21578f5cb0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813349099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.1813349099
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.1598460075
Short name T577
Test name
Test status
Simulation time 93474967 ps
CPU time 1.05 seconds
Started Jul 30 06:10:59 PM PDT 24
Finished Jul 30 06:11:01 PM PDT 24
Peak memory 195564 kb
Host smart-4ce8ac96-7460-4830-a44b-f18e6abd3747
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598460075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.1598460075
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.697637839
Short name T491
Test name
Test status
Simulation time 33185127 ps
CPU time 1.43 seconds
Started Jul 30 06:10:54 PM PDT 24
Finished Jul 30 06:10:55 PM PDT 24
Peak memory 197764 kb
Host smart-ee2cb57d-2de2-4a0f-bcd3-279d69e1dee0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697637839 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.697637839
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.4142565737
Short name T534
Test name
Test status
Simulation time 25267291 ps
CPU time 0.61 seconds
Started Jul 30 06:10:56 PM PDT 24
Finished Jul 30 06:10:57 PM PDT 24
Peak memory 182900 kb
Host smart-36e302d8-7d28-4af0-b0b7-89dac4cbec45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142565737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.4142565737
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.1987700536
Short name T586
Test name
Test status
Simulation time 19888735 ps
CPU time 0.52 seconds
Started Jul 30 06:10:51 PM PDT 24
Finished Jul 30 06:10:52 PM PDT 24
Peak memory 182788 kb
Host smart-9b9393d2-3fa5-423b-8f12-6d197051d98d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987700536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.1987700536
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3354602661
Short name T95
Test name
Test status
Simulation time 32684876 ps
CPU time 0.7 seconds
Started Jul 30 06:10:57 PM PDT 24
Finished Jul 30 06:10:58 PM PDT 24
Peak memory 191860 kb
Host smart-265e09c4-c348-48e6-9efd-70b5a89027fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354602661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.3354602661
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.643570456
Short name T563
Test name
Test status
Simulation time 286598635 ps
CPU time 1.81 seconds
Started Jul 30 06:10:55 PM PDT 24
Finished Jul 30 06:10:56 PM PDT 24
Peak memory 197684 kb
Host smart-a5589326-b187-4be1-b6f0-ce7a4a02125d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643570456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.643570456
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.793938284
Short name T101
Test name
Test status
Simulation time 76955204 ps
CPU time 1.06 seconds
Started Jul 30 06:10:52 PM PDT 24
Finished Jul 30 06:10:53 PM PDT 24
Peak memory 195356 kb
Host smart-f77c476d-9ef0-481e-a732-21f55ffde547
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793938284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_in
tg_err.793938284
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.799259799
Short name T469
Test name
Test status
Simulation time 65588945 ps
CPU time 0.81 seconds
Started Jul 30 06:10:57 PM PDT 24
Finished Jul 30 06:10:58 PM PDT 24
Peak memory 196656 kb
Host smart-1372d1b1-fb7e-4890-8f2f-b58bf42e0ecc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799259799 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.799259799
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.2199933285
Short name T88
Test name
Test status
Simulation time 12631164 ps
CPU time 0.58 seconds
Started Jul 30 06:10:57 PM PDT 24
Finished Jul 30 06:10:58 PM PDT 24
Peak memory 182896 kb
Host smart-c0a6f91e-0e79-4781-a718-5087c5d7140d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199933285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.2199933285
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.3226441232
Short name T581
Test name
Test status
Simulation time 25758907 ps
CPU time 0.56 seconds
Started Jul 30 06:10:58 PM PDT 24
Finished Jul 30 06:10:59 PM PDT 24
Peak memory 182776 kb
Host smart-0cc92d7a-15fa-4aab-8c76-a1609a1fa41c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226441232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.3226441232
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2096932699
Short name T562
Test name
Test status
Simulation time 67158017 ps
CPU time 0.64 seconds
Started Jul 30 06:10:58 PM PDT 24
Finished Jul 30 06:10:59 PM PDT 24
Peak memory 192140 kb
Host smart-be7b4359-227b-4772-b8bf-657c8ba9f1eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096932699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.2096932699
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.1803976700
Short name T499
Test name
Test status
Simulation time 50336723 ps
CPU time 1.23 seconds
Started Jul 30 06:10:57 PM PDT 24
Finished Jul 30 06:10:59 PM PDT 24
Peak memory 197452 kb
Host smart-dc2cb7fb-2b6d-4cf8-9131-619925026b77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803976700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.1803976700
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1970199004
Short name T537
Test name
Test status
Simulation time 130901571 ps
CPU time 0.8 seconds
Started Jul 30 06:10:58 PM PDT 24
Finished Jul 30 06:10:59 PM PDT 24
Peak memory 183408 kb
Host smart-cc8b2da5-f135-494a-bcec-95b987e09b1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970199004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.1970199004
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.3758446735
Short name T87
Test name
Test status
Simulation time 31901641 ps
CPU time 0.8 seconds
Started Jul 30 06:10:45 PM PDT 24
Finished Jul 30 06:10:46 PM PDT 24
Peak memory 192988 kb
Host smart-3c403326-604e-41ce-81f8-3f5862df2356
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758446735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.3758446735
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1470453302
Short name T96
Test name
Test status
Simulation time 371800354 ps
CPU time 2.53 seconds
Started Jul 30 06:10:39 PM PDT 24
Finished Jul 30 06:10:42 PM PDT 24
Peak memory 191348 kb
Host smart-d7b7faf5-6e2a-4724-a3df-488606872dac
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470453302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.1470453302
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.1189348654
Short name T32
Test name
Test status
Simulation time 72884607 ps
CPU time 0.54 seconds
Started Jul 30 06:10:52 PM PDT 24
Finished Jul 30 06:10:53 PM PDT 24
Peak memory 182936 kb
Host smart-79b85d70-f7b0-4aab-a947-74ced2fa6a0b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189348654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.1189348654
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.1834377299
Short name T575
Test name
Test status
Simulation time 97919265 ps
CPU time 0.86 seconds
Started Jul 30 06:10:39 PM PDT 24
Finished Jul 30 06:10:40 PM PDT 24
Peak memory 196632 kb
Host smart-c259d880-542c-4b70-bcb9-369b95f80f82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834377299 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.1834377299
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.2646108870
Short name T497
Test name
Test status
Simulation time 12284286 ps
CPU time 0.54 seconds
Started Jul 30 06:10:47 PM PDT 24
Finished Jul 30 06:10:47 PM PDT 24
Peak memory 182640 kb
Host smart-690628bf-9966-4655-91f1-82624018ba1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646108870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.2646108870
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.2972673873
Short name T458
Test name
Test status
Simulation time 19297357 ps
CPU time 0.54 seconds
Started Jul 30 06:10:46 PM PDT 24
Finished Jul 30 06:10:47 PM PDT 24
Peak memory 182712 kb
Host smart-448d7824-45bc-4c40-bf81-ab1f3dcacb1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972673873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.2972673873
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.3733076237
Short name T543
Test name
Test status
Simulation time 120936849 ps
CPU time 0.59 seconds
Started Jul 30 06:10:49 PM PDT 24
Finished Jul 30 06:10:50 PM PDT 24
Peak memory 191528 kb
Host smart-bc15413e-ce29-4edf-b576-70da1d7a0ce3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733076237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.3733076237
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.325330406
Short name T573
Test name
Test status
Simulation time 717757027 ps
CPU time 1.75 seconds
Started Jul 30 06:10:33 PM PDT 24
Finished Jul 30 06:10:35 PM PDT 24
Peak memory 197704 kb
Host smart-f7f03c85-d863-41fa-85a2-d0cfe4cdb82f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325330406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.325330406
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2275030456
Short name T553
Test name
Test status
Simulation time 1036228981 ps
CPU time 1.13 seconds
Started Jul 30 06:10:37 PM PDT 24
Finished Jul 30 06:10:38 PM PDT 24
Peak memory 195356 kb
Host smart-2c4c3a01-9e41-4969-b077-254f30198b02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275030456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.2275030456
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.3655347921
Short name T544
Test name
Test status
Simulation time 43289994 ps
CPU time 0.54 seconds
Started Jul 30 06:11:00 PM PDT 24
Finished Jul 30 06:11:01 PM PDT 24
Peak memory 182080 kb
Host smart-99dde922-1c59-4035-949c-a465bfb55f63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655347921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.3655347921
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.4137487260
Short name T516
Test name
Test status
Simulation time 39113359 ps
CPU time 0.52 seconds
Started Jul 30 06:10:57 PM PDT 24
Finished Jul 30 06:10:57 PM PDT 24
Peak memory 182168 kb
Host smart-e522791b-f75e-404e-9881-decb848a5f36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137487260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.4137487260
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.221518541
Short name T512
Test name
Test status
Simulation time 37973359 ps
CPU time 0.53 seconds
Started Jul 30 06:10:58 PM PDT 24
Finished Jul 30 06:10:59 PM PDT 24
Peak memory 182220 kb
Host smart-65a4333a-84d7-4685-895e-d67807d6db9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221518541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.221518541
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.2197026668
Short name T508
Test name
Test status
Simulation time 14432539 ps
CPU time 0.56 seconds
Started Jul 30 06:10:55 PM PDT 24
Finished Jul 30 06:10:55 PM PDT 24
Peak memory 182744 kb
Host smart-3b5e79b1-d306-428a-aabb-4db7f263663a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197026668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.2197026668
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.3834656626
Short name T514
Test name
Test status
Simulation time 56891376 ps
CPU time 0.53 seconds
Started Jul 30 06:11:00 PM PDT 24
Finished Jul 30 06:11:01 PM PDT 24
Peak memory 182224 kb
Host smart-e7c5feee-a01f-4122-a2f5-b5290103fc10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834656626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.3834656626
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.3143336080
Short name T472
Test name
Test status
Simulation time 42258157 ps
CPU time 0.55 seconds
Started Jul 30 06:10:56 PM PDT 24
Finished Jul 30 06:10:57 PM PDT 24
Peak memory 182780 kb
Host smart-9daedd96-d924-42a0-93f8-3bce48987edb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143336080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.3143336080
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.856505594
Short name T481
Test name
Test status
Simulation time 44455214 ps
CPU time 0.53 seconds
Started Jul 30 06:10:56 PM PDT 24
Finished Jul 30 06:10:56 PM PDT 24
Peak memory 182208 kb
Host smart-d380356c-a1d5-461a-96cf-8eb1125e6020
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856505594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.856505594
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.2296234468
Short name T470
Test name
Test status
Simulation time 55141841 ps
CPU time 0.63 seconds
Started Jul 30 06:10:57 PM PDT 24
Finished Jul 30 06:10:58 PM PDT 24
Peak memory 182768 kb
Host smart-761087eb-d092-4496-9cf7-25e915e6a50e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296234468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.2296234468
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2317213220
Short name T485
Test name
Test status
Simulation time 56062133 ps
CPU time 0.58 seconds
Started Jul 30 06:10:57 PM PDT 24
Finished Jul 30 06:10:58 PM PDT 24
Peak memory 182732 kb
Host smart-8b83402d-4c70-47e2-a5f1-7c4efc01fb6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317213220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.2317213220
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.939519372
Short name T585
Test name
Test status
Simulation time 39714039 ps
CPU time 0.56 seconds
Started Jul 30 06:10:56 PM PDT 24
Finished Jul 30 06:10:57 PM PDT 24
Peak memory 182232 kb
Host smart-db2951a5-8143-4b00-b31d-230a1cf22592
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939519372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.939519372
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3133192294
Short name T570
Test name
Test status
Simulation time 17906953 ps
CPU time 0.71 seconds
Started Jul 30 06:10:41 PM PDT 24
Finished Jul 30 06:10:42 PM PDT 24
Peak memory 182868 kb
Host smart-d1deca84-6e80-47a5-a913-6f93f1a0f91a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133192294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.3133192294
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.2201957311
Short name T559
Test name
Test status
Simulation time 171319323 ps
CPU time 1.54 seconds
Started Jul 30 06:10:49 PM PDT 24
Finished Jul 30 06:10:51 PM PDT 24
Peak memory 192192 kb
Host smart-d1186b4c-249a-4864-902f-3c42dda0bbc0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201957311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.2201957311
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.678363311
Short name T518
Test name
Test status
Simulation time 21067050 ps
CPU time 0.58 seconds
Started Jul 30 06:10:47 PM PDT 24
Finished Jul 30 06:10:48 PM PDT 24
Peak memory 182968 kb
Host smart-8933a001-df9e-49d7-9430-da8aa7406dce
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678363311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_re
set.678363311
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.861216970
Short name T536
Test name
Test status
Simulation time 82676952 ps
CPU time 1.1 seconds
Started Jul 30 06:10:42 PM PDT 24
Finished Jul 30 06:10:43 PM PDT 24
Peak memory 197716 kb
Host smart-939555e7-5f4a-4175-a950-288129f18dcf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861216970 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.861216970
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.69464726
Short name T576
Test name
Test status
Simulation time 47318846 ps
CPU time 0.51 seconds
Started Jul 30 06:10:33 PM PDT 24
Finished Jul 30 06:10:34 PM PDT 24
Peak memory 182940 kb
Host smart-ae81d974-bdf6-476e-a036-fefbc3db5c36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69464726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.69464726
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.4206944661
Short name T571
Test name
Test status
Simulation time 13228384 ps
CPU time 0.56 seconds
Started Jul 30 06:10:33 PM PDT 24
Finished Jul 30 06:10:34 PM PDT 24
Peak memory 182644 kb
Host smart-e1dceaff-6114-499f-a4b9-33bfee7ff92e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206944661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.4206944661
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.857036802
Short name T582
Test name
Test status
Simulation time 57336343 ps
CPU time 0.7 seconds
Started Jul 30 06:10:46 PM PDT 24
Finished Jul 30 06:10:47 PM PDT 24
Peak memory 192256 kb
Host smart-afa9ae99-aa72-4780-b26f-8bd251922112
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857036802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_tim
er_same_csr_outstanding.857036802
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3290668090
Short name T484
Test name
Test status
Simulation time 46754389 ps
CPU time 2.42 seconds
Started Jul 30 06:10:46 PM PDT 24
Finished Jul 30 06:10:49 PM PDT 24
Peak memory 197732 kb
Host smart-c6bc75d2-2b2c-4b99-ac53-407fdadc9835
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290668090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.3290668090
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.101309460
Short name T533
Test name
Test status
Simulation time 38521793 ps
CPU time 0.83 seconds
Started Jul 30 06:10:39 PM PDT 24
Finished Jul 30 06:10:40 PM PDT 24
Peak memory 194048 kb
Host smart-582644cc-6581-4c2b-be04-606f78998f1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101309460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_int
g_err.101309460
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.3017964562
Short name T507
Test name
Test status
Simulation time 44649923 ps
CPU time 0.59 seconds
Started Jul 30 06:11:01 PM PDT 24
Finished Jul 30 06:11:02 PM PDT 24
Peak memory 182648 kb
Host smart-356d25ba-bb37-4fc4-8e6d-921f7cad9179
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017964562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.3017964562
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.461913272
Short name T567
Test name
Test status
Simulation time 14387672 ps
CPU time 0.55 seconds
Started Jul 30 06:10:58 PM PDT 24
Finished Jul 30 06:10:59 PM PDT 24
Peak memory 182708 kb
Host smart-38a69dec-7c5a-45c1-8ef9-6aad47ea15d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461913272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.461913272
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.543017677
Short name T459
Test name
Test status
Simulation time 43102056 ps
CPU time 0.56 seconds
Started Jul 30 06:11:03 PM PDT 24
Finished Jul 30 06:11:03 PM PDT 24
Peak memory 182744 kb
Host smart-39750e08-41e6-4fe5-ae5f-969d5dab819d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543017677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.543017677
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1650782005
Short name T460
Test name
Test status
Simulation time 13846848 ps
CPU time 0.61 seconds
Started Jul 30 06:10:56 PM PDT 24
Finished Jul 30 06:10:56 PM PDT 24
Peak memory 182656 kb
Host smart-bf21cbe4-df24-410a-97f6-0bf0ba71cb30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650782005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.1650782005
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.391374118
Short name T574
Test name
Test status
Simulation time 19271391 ps
CPU time 0.56 seconds
Started Jul 30 06:11:03 PM PDT 24
Finished Jul 30 06:11:03 PM PDT 24
Peak memory 182760 kb
Host smart-fa5b1d76-01b7-4898-a341-19d72d56347d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391374118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.391374118
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.3444187541
Short name T555
Test name
Test status
Simulation time 39648619 ps
CPU time 0.54 seconds
Started Jul 30 06:11:05 PM PDT 24
Finished Jul 30 06:11:05 PM PDT 24
Peak memory 182792 kb
Host smart-b7e5fb9b-8e05-4401-a5c2-e0cc64980b2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444187541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.3444187541
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.3203075346
Short name T566
Test name
Test status
Simulation time 53929917 ps
CPU time 0.53 seconds
Started Jul 30 06:11:07 PM PDT 24
Finished Jul 30 06:11:08 PM PDT 24
Peak memory 182592 kb
Host smart-83cb8524-e8ca-4e0b-b136-3f01519ff336
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203075346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.3203075346
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.1610228334
Short name T456
Test name
Test status
Simulation time 67913226 ps
CPU time 0.52 seconds
Started Jul 30 06:11:18 PM PDT 24
Finished Jul 30 06:11:19 PM PDT 24
Peak memory 182148 kb
Host smart-336f1b68-db0d-4b48-8889-bdd9d425c06f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610228334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.1610228334
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.2309125392
Short name T506
Test name
Test status
Simulation time 26301382 ps
CPU time 0.59 seconds
Started Jul 30 06:11:05 PM PDT 24
Finished Jul 30 06:11:05 PM PDT 24
Peak memory 182788 kb
Host smart-f33e3302-ea92-47c7-b1ad-ed43f448282f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309125392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.2309125392
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.560644117
Short name T478
Test name
Test status
Simulation time 15469687 ps
CPU time 0.57 seconds
Started Jul 30 06:10:59 PM PDT 24
Finished Jul 30 06:11:00 PM PDT 24
Peak memory 182752 kb
Host smart-630ce056-734f-422f-b22e-71a717f1a8f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560644117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.560644117
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.399707327
Short name T493
Test name
Test status
Simulation time 17370040 ps
CPU time 0.62 seconds
Started Jul 30 06:10:40 PM PDT 24
Finished Jul 30 06:10:40 PM PDT 24
Peak memory 182904 kb
Host smart-b1717de2-11ab-44de-8ba9-0c56dd353498
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399707327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alias
ing.399707327
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.2416536469
Short name T492
Test name
Test status
Simulation time 661363936 ps
CPU time 1.44 seconds
Started Jul 30 06:10:40 PM PDT 24
Finished Jul 30 06:10:42 PM PDT 24
Peak memory 191324 kb
Host smart-decea3a3-0e07-44c4-b003-37e87c6c84f8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416536469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.2416536469
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.731521539
Short name T531
Test name
Test status
Simulation time 22551888 ps
CPU time 0.59 seconds
Started Jul 30 06:10:40 PM PDT 24
Finished Jul 30 06:10:41 PM PDT 24
Peak memory 182972 kb
Host smart-0ac408e6-b42e-4968-9198-3094262a1290
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731521539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_re
set.731521539
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3060990755
Short name T501
Test name
Test status
Simulation time 152951814 ps
CPU time 0.95 seconds
Started Jul 30 06:10:39 PM PDT 24
Finished Jul 30 06:10:40 PM PDT 24
Peak memory 197568 kb
Host smart-bf755df4-ef81-45af-98da-74756434ceb9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060990755 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.3060990755
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.78810921
Short name T76
Test name
Test status
Simulation time 36892701 ps
CPU time 0.53 seconds
Started Jul 30 06:10:44 PM PDT 24
Finished Jul 30 06:10:45 PM PDT 24
Peak memory 182660 kb
Host smart-5fd500a5-4c7f-47f3-86ad-740e95a2b0f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78810921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.78810921
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.2543346614
Short name T578
Test name
Test status
Simulation time 33340220 ps
CPU time 0.53 seconds
Started Jul 30 06:10:49 PM PDT 24
Finished Jul 30 06:10:49 PM PDT 24
Peak memory 182484 kb
Host smart-bf2ef6fc-dffa-47a9-b093-94d1c537a05a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543346614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.2543346614
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.1190258938
Short name T80
Test name
Test status
Simulation time 13803925 ps
CPU time 0.6 seconds
Started Jul 30 06:10:40 PM PDT 24
Finished Jul 30 06:10:40 PM PDT 24
Peak memory 192160 kb
Host smart-8ad376ad-2792-4075-89cf-d85839203184
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190258938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.1190258938
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1428516498
Short name T498
Test name
Test status
Simulation time 387790264 ps
CPU time 1.63 seconds
Started Jul 30 06:10:54 PM PDT 24
Finished Jul 30 06:10:56 PM PDT 24
Peak memory 197624 kb
Host smart-7a0c42fb-c49c-4111-8827-4d54884790b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428516498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.1428516498
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.110307803
Short name T565
Test name
Test status
Simulation time 461179569 ps
CPU time 1.4 seconds
Started Jul 30 06:10:47 PM PDT 24
Finished Jul 30 06:10:48 PM PDT 24
Peak memory 183452 kb
Host smart-c881dec3-3a0c-4ad2-b90d-542fd9540a01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110307803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_int
g_err.110307803
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.2293636942
Short name T584
Test name
Test status
Simulation time 35534966 ps
CPU time 0.54 seconds
Started Jul 30 06:11:03 PM PDT 24
Finished Jul 30 06:11:03 PM PDT 24
Peak memory 182248 kb
Host smart-38a3b1e2-0f36-4bdf-af19-292b9721a002
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293636942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.2293636942
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.3016364353
Short name T475
Test name
Test status
Simulation time 14851744 ps
CPU time 0.57 seconds
Started Jul 30 06:11:08 PM PDT 24
Finished Jul 30 06:11:09 PM PDT 24
Peak memory 182696 kb
Host smart-9ab03946-02b2-4f3e-bb88-40a68e40a63a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016364353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.3016364353
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.2533881809
Short name T520
Test name
Test status
Simulation time 39147312 ps
CPU time 0.55 seconds
Started Jul 30 06:11:03 PM PDT 24
Finished Jul 30 06:11:04 PM PDT 24
Peak memory 182708 kb
Host smart-b312c8ed-be60-4f43-bb20-5f6980c79754
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533881809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.2533881809
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.1090583140
Short name T462
Test name
Test status
Simulation time 30754135 ps
CPU time 0.57 seconds
Started Jul 30 06:11:02 PM PDT 24
Finished Jul 30 06:11:03 PM PDT 24
Peak memory 182740 kb
Host smart-4c9cc3de-a4c9-44b2-b0f0-25e4c6e9afd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090583140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.1090583140
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.2842293248
Short name T568
Test name
Test status
Simulation time 24493208 ps
CPU time 0.57 seconds
Started Jul 30 06:11:01 PM PDT 24
Finished Jul 30 06:11:01 PM PDT 24
Peak memory 182744 kb
Host smart-e15d2c25-3db2-41a1-8013-263fd44c75eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842293248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.2842293248
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.65793750
Short name T550
Test name
Test status
Simulation time 13240668 ps
CPU time 0.58 seconds
Started Jul 30 06:11:02 PM PDT 24
Finished Jul 30 06:11:02 PM PDT 24
Peak memory 182776 kb
Host smart-12526d0a-9443-4ae8-ab6e-38f9dbaf73d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65793750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.65793750
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.542081745
Short name T548
Test name
Test status
Simulation time 51321791 ps
CPU time 0.59 seconds
Started Jul 30 06:11:01 PM PDT 24
Finished Jul 30 06:11:02 PM PDT 24
Peak memory 182812 kb
Host smart-71769ee3-d0ba-4e69-b996-489886893a5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542081745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.542081745
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.1054442534
Short name T502
Test name
Test status
Simulation time 41713593 ps
CPU time 0.58 seconds
Started Jul 30 06:11:03 PM PDT 24
Finished Jul 30 06:11:03 PM PDT 24
Peak memory 182744 kb
Host smart-59875dce-7037-4774-b543-ccd341ee6669
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054442534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.1054442534
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.1051587726
Short name T465
Test name
Test status
Simulation time 114787486 ps
CPU time 0.58 seconds
Started Jul 30 06:11:00 PM PDT 24
Finished Jul 30 06:11:01 PM PDT 24
Peak memory 182460 kb
Host smart-3242bd88-c166-4b34-bc58-64b1bdc0d9f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051587726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.1051587726
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.2931046762
Short name T539
Test name
Test status
Simulation time 21520939 ps
CPU time 0.55 seconds
Started Jul 30 06:11:04 PM PDT 24
Finished Jul 30 06:11:04 PM PDT 24
Peak memory 182760 kb
Host smart-448aa6a7-0588-4cb7-9f3c-7e64dc2f394e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931046762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.2931046762
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.1090960663
Short name T479
Test name
Test status
Simulation time 86020163 ps
CPU time 1.08 seconds
Started Jul 30 06:10:41 PM PDT 24
Finished Jul 30 06:10:43 PM PDT 24
Peak memory 197636 kb
Host smart-cfd0779b-e49e-472b-910d-42d2e780734f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090960663 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.1090960663
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.3788708667
Short name T85
Test name
Test status
Simulation time 35021591 ps
CPU time 0.62 seconds
Started Jul 30 06:10:39 PM PDT 24
Finished Jul 30 06:10:40 PM PDT 24
Peak memory 182936 kb
Host smart-2c780114-1f67-40b7-ade3-d2361391dda5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788708667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.3788708667
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.644178287
Short name T509
Test name
Test status
Simulation time 17067407 ps
CPU time 0.58 seconds
Started Jul 30 06:10:44 PM PDT 24
Finished Jul 30 06:10:45 PM PDT 24
Peak memory 182792 kb
Host smart-7983bdbb-2ab8-4285-9180-d10b0eafb4ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644178287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.644178287
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1738744303
Short name T511
Test name
Test status
Simulation time 18601664 ps
CPU time 0.67 seconds
Started Jul 30 06:10:47 PM PDT 24
Finished Jul 30 06:10:48 PM PDT 24
Peak memory 192916 kb
Host smart-d231214f-6565-4469-825b-487330ce1507
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738744303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.1738744303
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.951864351
Short name T542
Test name
Test status
Simulation time 147633432 ps
CPU time 1.48 seconds
Started Jul 30 06:10:48 PM PDT 24
Finished Jul 30 06:10:50 PM PDT 24
Peak memory 197656 kb
Host smart-5d707557-e53a-412d-b38d-908bbb2b4632
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951864351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.951864351
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1880279999
Short name T545
Test name
Test status
Simulation time 378603006 ps
CPU time 1.33 seconds
Started Jul 30 06:10:46 PM PDT 24
Finished Jul 30 06:10:47 PM PDT 24
Peak memory 195468 kb
Host smart-98ebb1ee-ef3a-42ae-95cc-d5803b5d2a2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880279999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.1880279999
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.4157059692
Short name T489
Test name
Test status
Simulation time 14301312 ps
CPU time 0.62 seconds
Started Jul 30 06:10:45 PM PDT 24
Finished Jul 30 06:10:46 PM PDT 24
Peak memory 193292 kb
Host smart-b2d11c09-69ce-44db-9c6a-f98dcb6c6df0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157059692 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.4157059692
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.2121502309
Short name T482
Test name
Test status
Simulation time 16117076 ps
CPU time 0.59 seconds
Started Jul 30 06:10:47 PM PDT 24
Finished Jul 30 06:10:48 PM PDT 24
Peak memory 182992 kb
Host smart-214c9fca-f148-46c7-8a40-b17afbf2d839
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121502309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.2121502309
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.961972859
Short name T572
Test name
Test status
Simulation time 38749800 ps
CPU time 0.55 seconds
Started Jul 30 06:10:40 PM PDT 24
Finished Jul 30 06:10:41 PM PDT 24
Peak memory 182736 kb
Host smart-9073e6db-77ef-4990-be2e-e960258c7778
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961972859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.961972859
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.686869133
Short name T557
Test name
Test status
Simulation time 71683664 ps
CPU time 0.63 seconds
Started Jul 30 06:10:47 PM PDT 24
Finished Jul 30 06:10:48 PM PDT 24
Peak memory 192384 kb
Host smart-fbd86345-d0a3-4af4-94e5-ceba21544595
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686869133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_tim
er_same_csr_outstanding.686869133
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.3306186807
Short name T500
Test name
Test status
Simulation time 68103894 ps
CPU time 1.76 seconds
Started Jul 30 06:10:43 PM PDT 24
Finished Jul 30 06:10:45 PM PDT 24
Peak memory 197708 kb
Host smart-d6ccd587-9983-40dc-a0fb-e5bd711236e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306186807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.3306186807
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.2481279803
Short name T98
Test name
Test status
Simulation time 58018780 ps
CPU time 0.91 seconds
Started Jul 30 06:10:39 PM PDT 24
Finished Jul 30 06:10:40 PM PDT 24
Peak memory 194036 kb
Host smart-3fe70c3e-70a6-45dd-8f83-841e2b594c3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481279803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.2481279803
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.4174120835
Short name T523
Test name
Test status
Simulation time 86457510 ps
CPU time 0.79 seconds
Started Jul 30 06:10:45 PM PDT 24
Finished Jul 30 06:10:46 PM PDT 24
Peak memory 195504 kb
Host smart-4ad2ea7c-a416-47be-8398-7a79dffe6b87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174120835 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.4174120835
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.4255676984
Short name T86
Test name
Test status
Simulation time 38159221 ps
CPU time 0.57 seconds
Started Jul 30 06:10:43 PM PDT 24
Finished Jul 30 06:10:44 PM PDT 24
Peak memory 182964 kb
Host smart-540a46d5-4b59-4b20-bb72-90d23dbc0732
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255676984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.4255676984
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.3276103826
Short name T519
Test name
Test status
Simulation time 19447269 ps
CPU time 0.6 seconds
Started Jul 30 06:10:55 PM PDT 24
Finished Jul 30 06:10:55 PM PDT 24
Peak memory 182752 kb
Host smart-bf141483-aae3-4c3a-a1f5-8afff2f17039
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276103826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.3276103826
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.2268581103
Short name T527
Test name
Test status
Simulation time 25863746 ps
CPU time 0.63 seconds
Started Jul 30 06:10:43 PM PDT 24
Finished Jul 30 06:10:44 PM PDT 24
Peak memory 192180 kb
Host smart-be6de840-2eaa-44ff-89d2-405be226f121
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268581103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.2268581103
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.167512801
Short name T483
Test name
Test status
Simulation time 83992205 ps
CPU time 1.26 seconds
Started Jul 30 06:10:50 PM PDT 24
Finished Jul 30 06:10:56 PM PDT 24
Peak memory 197536 kb
Host smart-a33c38eb-c809-4912-b08d-02ec0b4c71f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167512801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.167512801
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.3527014107
Short name T31
Test name
Test status
Simulation time 48880835 ps
CPU time 0.85 seconds
Started Jul 30 06:10:46 PM PDT 24
Finished Jul 30 06:10:47 PM PDT 24
Peak memory 193988 kb
Host smart-91485d83-ee78-4275-9b1c-60cc81171dad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527014107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.3527014107
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.2871143372
Short name T494
Test name
Test status
Simulation time 81263845 ps
CPU time 1 seconds
Started Jul 30 06:10:49 PM PDT 24
Finished Jul 30 06:10:51 PM PDT 24
Peak memory 196684 kb
Host smart-9a5f66ce-7fdc-4fe4-bca4-0f07c0c1e008
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871143372 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.2871143372
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.514533046
Short name T91
Test name
Test status
Simulation time 16970252 ps
CPU time 0.59 seconds
Started Jul 30 06:10:47 PM PDT 24
Finished Jul 30 06:10:48 PM PDT 24
Peak memory 182888 kb
Host smart-bb39e9cc-43f8-4277-b0cf-df3ff1a9e96b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514533046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.514533046
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.2670706799
Short name T471
Test name
Test status
Simulation time 58604571 ps
CPU time 0.56 seconds
Started Jul 30 06:10:43 PM PDT 24
Finished Jul 30 06:10:44 PM PDT 24
Peak memory 182816 kb
Host smart-a42135fd-f8c7-4389-b702-5855b87a3161
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670706799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.2670706799
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.2123774856
Short name T558
Test name
Test status
Simulation time 18920430 ps
CPU time 0.63 seconds
Started Jul 30 06:10:51 PM PDT 24
Finished Jul 30 06:10:51 PM PDT 24
Peak memory 192112 kb
Host smart-695f8d2f-ac32-4b46-b0f3-486ec1c2479a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123774856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.2123774856
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.534186455
Short name T463
Test name
Test status
Simulation time 164766130 ps
CPU time 1.51 seconds
Started Jul 30 06:10:43 PM PDT 24
Finished Jul 30 06:10:45 PM PDT 24
Peak memory 197676 kb
Host smart-1de468a8-0156-4931-b4e5-4a6367c2d696
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534186455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.534186455
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.623443681
Short name T547
Test name
Test status
Simulation time 123325812 ps
CPU time 1.09 seconds
Started Jul 30 06:10:49 PM PDT 24
Finished Jul 30 06:10:51 PM PDT 24
Peak memory 183592 kb
Host smart-46c0ae56-e383-41f1-b693-c5fb399229e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623443681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_int
g_err.623443681
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.1854685795
Short name T515
Test name
Test status
Simulation time 14326685 ps
CPU time 0.65 seconds
Started Jul 30 06:10:49 PM PDT 24
Finished Jul 30 06:10:50 PM PDT 24
Peak memory 193996 kb
Host smart-2a64d0b0-80a1-4f60-9ed6-e6066e5f94a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854685795 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.1854685795
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.1379530210
Short name T84
Test name
Test status
Simulation time 33051875 ps
CPU time 0.58 seconds
Started Jul 30 06:10:45 PM PDT 24
Finished Jul 30 06:10:46 PM PDT 24
Peak memory 182940 kb
Host smart-e2ec8802-8843-40a6-bf9a-51e278feb586
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379530210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.1379530210
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.2728682958
Short name T561
Test name
Test status
Simulation time 14075137 ps
CPU time 0.58 seconds
Started Jul 30 06:10:42 PM PDT 24
Finished Jul 30 06:10:43 PM PDT 24
Peak memory 182208 kb
Host smart-dfeb3ca9-b8bd-41b6-8933-f9e287e5c614
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728682958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.2728682958
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.652006006
Short name T54
Test name
Test status
Simulation time 281098585 ps
CPU time 0.82 seconds
Started Jul 30 06:10:45 PM PDT 24
Finished Jul 30 06:10:46 PM PDT 24
Peak memory 191920 kb
Host smart-21ef57f4-78ac-46db-93a5-eb3798f22e5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652006006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_tim
er_same_csr_outstanding.652006006
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.1879377985
Short name T535
Test name
Test status
Simulation time 35680497 ps
CPU time 1.78 seconds
Started Jul 30 06:10:50 PM PDT 24
Finished Jul 30 06:10:52 PM PDT 24
Peak memory 197636 kb
Host smart-f063e1e2-ce1c-4368-b050-fe141d0df3d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879377985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.1879377985
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.1768294367
Short name T30
Test name
Test status
Simulation time 167860041 ps
CPU time 0.86 seconds
Started Jul 30 06:10:43 PM PDT 24
Finished Jul 30 06:10:44 PM PDT 24
Peak memory 193976 kb
Host smart-ad5c46d1-d8c4-410b-a773-28dabb5b4adf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768294367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.1768294367
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.693743593
Short name T326
Test name
Test status
Simulation time 727859106040 ps
CPU time 629.16 seconds
Started Jul 30 06:11:33 PM PDT 24
Finished Jul 30 06:22:02 PM PDT 24
Peak memory 183404 kb
Host smart-460bb27c-5563-497c-97f7-d65e2de9ec3e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693743593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.rv_timer_cfg_update_on_fly.693743593
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.2627517665
Short name T385
Test name
Test status
Simulation time 229209683332 ps
CPU time 345.42 seconds
Started Jul 30 06:11:00 PM PDT 24
Finished Jul 30 06:16:46 PM PDT 24
Peak memory 183492 kb
Host smart-adbf1386-c539-402e-9a77-7429380a680a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627517665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.2627517665
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.3637964177
Short name T384
Test name
Test status
Simulation time 46679526 ps
CPU time 0.58 seconds
Started Jul 30 06:11:18 PM PDT 24
Finished Jul 30 06:11:19 PM PDT 24
Peak memory 183132 kb
Host smart-265bad34-7f54-47cd-ae43-35674cb62c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637964177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.3637964177
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.3964252504
Short name T396
Test name
Test status
Simulation time 210055844581 ps
CPU time 278.91 seconds
Started Jul 30 06:11:05 PM PDT 24
Finished Jul 30 06:15:44 PM PDT 24
Peak memory 183464 kb
Host smart-3c405996-3114-4e13-9079-62f2dccfb16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964252504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.3964252504
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.2851905917
Short name T260
Test name
Test status
Simulation time 312155362184 ps
CPU time 157.26 seconds
Started Jul 30 06:11:06 PM PDT 24
Finished Jul 30 06:13:43 PM PDT 24
Peak memory 191652 kb
Host smart-f866896a-2f77-4eac-9040-1d7b359df6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851905917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.2851905917
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.3888372641
Short name T18
Test name
Test status
Simulation time 64387742 ps
CPU time 0.85 seconds
Started Jul 30 06:11:06 PM PDT 24
Finished Jul 30 06:11:07 PM PDT 24
Peak memory 214032 kb
Host smart-7440ca4e-1949-4d53-8fd0-f29f9682836c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888372641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.3888372641
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.3070851583
Short name T433
Test name
Test status
Simulation time 57868240497 ps
CPU time 45.47 seconds
Started Jul 30 06:11:34 PM PDT 24
Finished Jul 30 06:12:19 PM PDT 24
Peak memory 183400 kb
Host smart-adcd9f17-f4b6-41f8-9004-050b9abe4f0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070851583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
3070851583
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all_with_rand_reset.2145806959
Short name T38
Test name
Test status
Simulation time 210383069662 ps
CPU time 448.46 seconds
Started Jul 30 06:11:07 PM PDT 24
Finished Jul 30 06:18:36 PM PDT 24
Peak memory 206396 kb
Host smart-8f22c1bb-a6bd-45e1-a9b7-02cabaee1b9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145806959 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all_with_rand_reset.2145806959
Directory /workspace/1.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.1223167765
Short name T20
Test name
Test status
Simulation time 69216751286 ps
CPU time 90.93 seconds
Started Jul 30 06:11:22 PM PDT 24
Finished Jul 30 06:12:53 PM PDT 24
Peak memory 183432 kb
Host smart-897a61f3-f641-423e-9de8-81db225495f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223167765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.1223167765
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.4194873499
Short name T450
Test name
Test status
Simulation time 132373567682 ps
CPU time 269.65 seconds
Started Jul 30 06:11:35 PM PDT 24
Finished Jul 30 06:16:04 PM PDT 24
Peak memory 183360 kb
Host smart-ce45ac0c-ed36-4e6d-9867-202feb066a41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194873499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.4194873499
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.1658399502
Short name T364
Test name
Test status
Simulation time 1303184722 ps
CPU time 2.29 seconds
Started Jul 30 06:11:21 PM PDT 24
Finished Jul 30 06:11:23 PM PDT 24
Peak memory 183420 kb
Host smart-83d63ef8-f938-46cd-8cfc-3d2ddb8ee128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658399502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.1658399502
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/100.rv_timer_random.3199754785
Short name T234
Test name
Test status
Simulation time 159750035462 ps
CPU time 69.09 seconds
Started Jul 30 06:12:27 PM PDT 24
Finished Jul 30 06:13:36 PM PDT 24
Peak memory 191664 kb
Host smart-33a7def4-10ef-4291-abf9-f202247f6607
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199754785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.3199754785
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.2837432178
Short name T129
Test name
Test status
Simulation time 437779947667 ps
CPU time 972.3 seconds
Started Jul 30 06:12:35 PM PDT 24
Finished Jul 30 06:28:47 PM PDT 24
Peak memory 191692 kb
Host smart-d0bb4d6a-7408-4682-b19b-a3ed33885a06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837432178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.2837432178
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.3582104825
Short name T358
Test name
Test status
Simulation time 140949873934 ps
CPU time 132.87 seconds
Started Jul 30 06:12:33 PM PDT 24
Finished Jul 30 06:14:46 PM PDT 24
Peak memory 191640 kb
Host smart-8fecc786-b178-4e57-b13b-81216a82f04c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582104825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.3582104825
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.3775007611
Short name T171
Test name
Test status
Simulation time 643639270964 ps
CPU time 544.99 seconds
Started Jul 30 06:12:38 PM PDT 24
Finished Jul 30 06:21:43 PM PDT 24
Peak memory 191676 kb
Host smart-ee2809fc-1f92-4cf4-aad0-652571f4af96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775007611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.3775007611
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.3858939636
Short name T121
Test name
Test status
Simulation time 733717815 ps
CPU time 1.56 seconds
Started Jul 30 06:12:38 PM PDT 24
Finished Jul 30 06:12:40 PM PDT 24
Peak memory 183144 kb
Host smart-a88ddc7a-48c2-4792-a54d-976fc9596bed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858939636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.3858939636
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.4220873784
Short name T231
Test name
Test status
Simulation time 307671186895 ps
CPU time 204.6 seconds
Started Jul 30 06:12:37 PM PDT 24
Finished Jul 30 06:16:01 PM PDT 24
Peak memory 191700 kb
Host smart-c158272d-41f0-4b05-84d2-685ecec7b6f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220873784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.4220873784
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.3509517889
Short name T432
Test name
Test status
Simulation time 3307987325 ps
CPU time 5.56 seconds
Started Jul 30 06:11:18 PM PDT 24
Finished Jul 30 06:11:24 PM PDT 24
Peak memory 183380 kb
Host smart-da2f982b-15fb-4a98-bbf2-72397c9746dc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509517889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.3509517889
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.1380873961
Short name T371
Test name
Test status
Simulation time 66461040640 ps
CPU time 82.95 seconds
Started Jul 30 06:11:30 PM PDT 24
Finished Jul 30 06:12:53 PM PDT 24
Peak memory 183500 kb
Host smart-6786803b-9717-4838-982d-5d11a04afea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380873961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.1380873961
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.1350381531
Short name T72
Test name
Test status
Simulation time 23357313836 ps
CPU time 12.13 seconds
Started Jul 30 06:11:21 PM PDT 24
Finished Jul 30 06:11:33 PM PDT 24
Peak memory 183452 kb
Host smart-17f5f726-485a-4fcc-9a00-b83ccb3977d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350381531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.1350381531
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.2993139194
Short name T3
Test name
Test status
Simulation time 45879634672 ps
CPU time 35.36 seconds
Started Jul 30 06:11:25 PM PDT 24
Finished Jul 30 06:12:00 PM PDT 24
Peak memory 183424 kb
Host smart-2a5b0df2-cb37-44ab-aff8-3a20fe203508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993139194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.2993139194
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/110.rv_timer_random.1119508020
Short name T342
Test name
Test status
Simulation time 222221591835 ps
CPU time 123.07 seconds
Started Jul 30 06:12:43 PM PDT 24
Finished Jul 30 06:14:47 PM PDT 24
Peak memory 191616 kb
Host smart-42b8dc34-ec55-4999-91b3-023baf70ce0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119508020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.1119508020
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.3154686713
Short name T135
Test name
Test status
Simulation time 90546374982 ps
CPU time 165.4 seconds
Started Jul 30 06:12:49 PM PDT 24
Finished Jul 30 06:15:35 PM PDT 24
Peak memory 191676 kb
Host smart-d1e703be-25a2-440b-98c9-706e64e1ec9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154686713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.3154686713
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.3673758992
Short name T329
Test name
Test status
Simulation time 272849129259 ps
CPU time 1800.94 seconds
Started Jul 30 06:12:43 PM PDT 24
Finished Jul 30 06:42:45 PM PDT 24
Peak memory 191608 kb
Host smart-232fe240-ad62-4764-b300-014791ddc62f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673758992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.3673758992
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.586787720
Short name T423
Test name
Test status
Simulation time 58940049136 ps
CPU time 54.97 seconds
Started Jul 30 06:12:42 PM PDT 24
Finished Jul 30 06:13:37 PM PDT 24
Peak memory 183416 kb
Host smart-0cbdacd3-db32-420d-b9e4-ea074f74dfa4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586787720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.586787720
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.3310975011
Short name T300
Test name
Test status
Simulation time 68881824337 ps
CPU time 92.77 seconds
Started Jul 30 06:12:40 PM PDT 24
Finished Jul 30 06:14:13 PM PDT 24
Peak memory 191656 kb
Host smart-53bc4c14-172a-4069-a0fb-f1a4c04cc8c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310975011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.3310975011
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.931656451
Short name T312
Test name
Test status
Simulation time 422239398126 ps
CPU time 193.03 seconds
Started Jul 30 06:12:42 PM PDT 24
Finished Jul 30 06:15:55 PM PDT 24
Peak memory 191648 kb
Host smart-667b9f61-b559-4f31-be31-de960746c5f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931656451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.931656451
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.3854732211
Short name T8
Test name
Test status
Simulation time 170756729128 ps
CPU time 1038.47 seconds
Started Jul 30 06:12:41 PM PDT 24
Finished Jul 30 06:30:00 PM PDT 24
Peak memory 191820 kb
Host smart-a93da26d-08e2-4d3d-8e7a-02f69b7b863a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854732211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.3854732211
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.2300879652
Short name T377
Test name
Test status
Simulation time 470572756579 ps
CPU time 162.65 seconds
Started Jul 30 06:11:38 PM PDT 24
Finished Jul 30 06:14:21 PM PDT 24
Peak memory 183436 kb
Host smart-7e783b5b-63eb-4870-b1d2-184bcb919ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300879652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.2300879652
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.1693707380
Short name T305
Test name
Test status
Simulation time 421080184251 ps
CPU time 1685.44 seconds
Started Jul 30 06:11:30 PM PDT 24
Finished Jul 30 06:39:36 PM PDT 24
Peak memory 191612 kb
Host smart-dc3d0f55-cfef-442d-895a-0275bdd482bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693707380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.1693707380
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.34131486
Short name T373
Test name
Test status
Simulation time 1426179447 ps
CPU time 1.44 seconds
Started Jul 30 06:11:23 PM PDT 24
Finished Jul 30 06:11:24 PM PDT 24
Peak memory 191640 kb
Host smart-e233cbf2-b1d0-4777-a217-ed871b36c8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34131486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.34131486
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.850005290
Short name T97
Test name
Test status
Simulation time 1312930714914 ps
CPU time 582.23 seconds
Started Jul 30 06:11:26 PM PDT 24
Finished Jul 30 06:21:09 PM PDT 24
Peak memory 195360 kb
Host smart-61d23019-5922-4ad0-bba7-2eae27dfab64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850005290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all.
850005290
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/120.rv_timer_random.1947823539
Short name T42
Test name
Test status
Simulation time 85417978696 ps
CPU time 788.03 seconds
Started Jul 30 06:12:51 PM PDT 24
Finished Jul 30 06:25:59 PM PDT 24
Peak memory 191636 kb
Host smart-9aef222a-f473-4f12-97fc-4edf9c4c4c49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947823539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.1947823539
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.2660713998
Short name T109
Test name
Test status
Simulation time 1250080496733 ps
CPU time 531.29 seconds
Started Jul 30 06:12:47 PM PDT 24
Finished Jul 30 06:21:39 PM PDT 24
Peak memory 191624 kb
Host smart-aa881940-32e5-4d4b-b4f5-cfbce9a9709d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660713998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.2660713998
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.3452345026
Short name T137
Test name
Test status
Simulation time 239512315834 ps
CPU time 359.16 seconds
Started Jul 30 06:12:48 PM PDT 24
Finished Jul 30 06:18:47 PM PDT 24
Peak memory 191704 kb
Host smart-490b1441-877b-42ee-9494-7e51757788d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452345026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.3452345026
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.3461424262
Short name T221
Test name
Test status
Simulation time 243323054728 ps
CPU time 227.65 seconds
Started Jul 30 06:12:49 PM PDT 24
Finished Jul 30 06:16:37 PM PDT 24
Peak memory 191664 kb
Host smart-5e42de8c-a5a0-4f9b-8e90-38580ec91c20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461424262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.3461424262
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.3769235785
Short name T313
Test name
Test status
Simulation time 72661857773 ps
CPU time 108.17 seconds
Started Jul 30 06:12:49 PM PDT 24
Finished Jul 30 06:14:38 PM PDT 24
Peak memory 191644 kb
Host smart-50d5f501-a916-4c78-be42-38466e950ed7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769235785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.3769235785
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.1966194343
Short name T290
Test name
Test status
Simulation time 46715060689 ps
CPU time 517.23 seconds
Started Jul 30 06:12:52 PM PDT 24
Finished Jul 30 06:21:29 PM PDT 24
Peak memory 191680 kb
Host smart-1242b9aa-fde9-4453-8711-1bc952d91682
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966194343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.1966194343
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.905556417
Short name T282
Test name
Test status
Simulation time 100978604097 ps
CPU time 153.63 seconds
Started Jul 30 06:12:54 PM PDT 24
Finished Jul 30 06:15:28 PM PDT 24
Peak memory 195588 kb
Host smart-425bcb02-d064-4cd3-8923-17f9bfbb29cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905556417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.905556417
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.2147445355
Short name T184
Test name
Test status
Simulation time 358952580515 ps
CPU time 556.87 seconds
Started Jul 30 06:11:19 PM PDT 24
Finished Jul 30 06:20:36 PM PDT 24
Peak memory 183436 kb
Host smart-9c4b453c-0f8e-482f-bc26-629118cddd2c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147445355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.2147445355
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.3479215359
Short name T431
Test name
Test status
Simulation time 525895066388 ps
CPU time 116.7 seconds
Started Jul 30 06:11:18 PM PDT 24
Finished Jul 30 06:13:15 PM PDT 24
Peak memory 183444 kb
Host smart-29e17f83-be37-4fe7-ad36-2a9497538e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479215359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.3479215359
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.787445776
Short name T301
Test name
Test status
Simulation time 9519321782 ps
CPU time 105.76 seconds
Started Jul 30 06:11:19 PM PDT 24
Finished Jul 30 06:13:05 PM PDT 24
Peak memory 183496 kb
Host smart-ea45bd8d-b473-45ef-819e-a385cd754e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787445776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.787445776
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.3447357852
Short name T115
Test name
Test status
Simulation time 362536794213 ps
CPU time 122.44 seconds
Started Jul 30 06:12:51 PM PDT 24
Finished Jul 30 06:14:53 PM PDT 24
Peak memory 191708 kb
Host smart-212f6b64-2470-4890-9574-9cbe49aa5274
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447357852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.3447357852
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.2237230725
Short name T438
Test name
Test status
Simulation time 780697766600 ps
CPU time 203.21 seconds
Started Jul 30 06:12:56 PM PDT 24
Finished Jul 30 06:16:20 PM PDT 24
Peak memory 193572 kb
Host smart-6c67061a-f98b-436d-8fff-831c6c3bb224
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237230725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.2237230725
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.131694628
Short name T345
Test name
Test status
Simulation time 28045954405 ps
CPU time 60.02 seconds
Started Jul 30 06:12:56 PM PDT 24
Finished Jul 30 06:13:56 PM PDT 24
Peak memory 183420 kb
Host smart-f02b5060-5b14-409e-b53e-d65eac66c932
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131694628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.131694628
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.145547719
Short name T292
Test name
Test status
Simulation time 4031213676 ps
CPU time 3.41 seconds
Started Jul 30 06:13:02 PM PDT 24
Finished Jul 30 06:13:06 PM PDT 24
Peak memory 183456 kb
Host smart-1c07bd49-e519-4326-8f7c-84d822c341fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145547719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.145547719
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.421613280
Short name T145
Test name
Test status
Simulation time 103623346015 ps
CPU time 55.71 seconds
Started Jul 30 06:11:22 PM PDT 24
Finished Jul 30 06:12:18 PM PDT 24
Peak memory 183456 kb
Host smart-7fce762f-8d50-40cb-9004-041d17e62b0d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421613280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.rv_timer_cfg_update_on_fly.421613280
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.3826724215
Short name T365
Test name
Test status
Simulation time 243146843376 ps
CPU time 185.96 seconds
Started Jul 30 06:11:26 PM PDT 24
Finished Jul 30 06:14:32 PM PDT 24
Peak memory 183444 kb
Host smart-b21bd854-8cb4-4d49-9a89-aee0bb0be399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826724215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.3826724215
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all_with_rand_reset.1492450886
Short name T37
Test name
Test status
Simulation time 8726253849 ps
CPU time 75.34 seconds
Started Jul 30 06:11:19 PM PDT 24
Finished Jul 30 06:12:34 PM PDT 24
Peak memory 198192 kb
Host smart-49319fa5-016b-4008-aa11-571eb7b3f6dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492450886 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all_with_rand_reset.1492450886
Directory /workspace/14.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/141.rv_timer_random.967418138
Short name T168
Test name
Test status
Simulation time 121001713237 ps
CPU time 35.55 seconds
Started Jul 30 06:13:06 PM PDT 24
Finished Jul 30 06:13:42 PM PDT 24
Peak memory 183284 kb
Host smart-33a61be2-1425-409b-9871-c4df697de983
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967418138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.967418138
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.970985463
Short name T238
Test name
Test status
Simulation time 470300580542 ps
CPU time 1679.95 seconds
Started Jul 30 06:13:16 PM PDT 24
Finished Jul 30 06:41:16 PM PDT 24
Peak memory 191656 kb
Host smart-a5e3a5f5-5069-4388-84a8-c8d42fb2051c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970985463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.970985463
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.776752521
Short name T400
Test name
Test status
Simulation time 83029820517 ps
CPU time 75.99 seconds
Started Jul 30 06:13:17 PM PDT 24
Finished Jul 30 06:14:33 PM PDT 24
Peak memory 183424 kb
Host smart-7154033e-5852-4440-9b67-52071d34b5a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776752521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.776752521
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.4025020478
Short name T265
Test name
Test status
Simulation time 4139777311 ps
CPU time 8.32 seconds
Started Jul 30 06:13:14 PM PDT 24
Finished Jul 30 06:13:23 PM PDT 24
Peak memory 183436 kb
Host smart-ae87d45d-bbaf-4c9e-8ca7-0ca1ff9b5dfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025020478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.4025020478
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.1068825107
Short name T133
Test name
Test status
Simulation time 208270980831 ps
CPU time 274.12 seconds
Started Jul 30 06:13:16 PM PDT 24
Finished Jul 30 06:17:50 PM PDT 24
Peak memory 191672 kb
Host smart-256b9d8a-dc8b-4ecb-afb1-6a5919273f95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068825107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.1068825107
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.26964206
Short name T303
Test name
Test status
Simulation time 245125839165 ps
CPU time 431.79 seconds
Started Jul 30 06:11:31 PM PDT 24
Finished Jul 30 06:18:43 PM PDT 24
Peak memory 183480 kb
Host smart-f74b39b5-3ae6-4515-aa85-ded3f14d1537
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26964206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.rv_timer_cfg_update_on_fly.26964206
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.2590990312
Short name T367
Test name
Test status
Simulation time 112548207491 ps
CPU time 172.2 seconds
Started Jul 30 06:11:39 PM PDT 24
Finished Jul 30 06:14:32 PM PDT 24
Peak memory 183488 kb
Host smart-81670dff-a941-45fa-824f-d85319a57156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590990312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.2590990312
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.3242201799
Short name T445
Test name
Test status
Simulation time 131881489966 ps
CPU time 398.42 seconds
Started Jul 30 06:11:23 PM PDT 24
Finished Jul 30 06:18:01 PM PDT 24
Peak memory 183464 kb
Host smart-2a4bde93-e89a-4427-bd1d-8a724fd90315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242201799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.3242201799
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.2283916119
Short name T362
Test name
Test status
Simulation time 341297859021 ps
CPU time 520.34 seconds
Started Jul 30 06:11:37 PM PDT 24
Finished Jul 30 06:20:17 PM PDT 24
Peak memory 191696 kb
Host smart-72c185aa-cb16-4181-9e39-bba2ae273dad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283916119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.2283916119
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.455476171
Short name T13
Test name
Test status
Simulation time 170607715373 ps
CPU time 286.39 seconds
Started Jul 30 06:11:21 PM PDT 24
Finished Jul 30 06:16:08 PM PDT 24
Peak memory 206336 kb
Host smart-22ba73b4-b237-4955-b4a2-cb8847d5e407
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455476171 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all_with_rand_reset.455476171
Directory /workspace/15.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.rv_timer_random.675108655
Short name T361
Test name
Test status
Simulation time 424995971896 ps
CPU time 220.01 seconds
Started Jul 30 06:13:14 PM PDT 24
Finished Jul 30 06:16:55 PM PDT 24
Peak memory 191608 kb
Host smart-ba1e361f-75b4-4cf5-944f-938269f65308
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675108655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.675108655
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.773418222
Short name T248
Test name
Test status
Simulation time 188823380976 ps
CPU time 497.72 seconds
Started Jul 30 06:13:17 PM PDT 24
Finished Jul 30 06:21:35 PM PDT 24
Peak memory 191632 kb
Host smart-7bfb9197-cb05-4b29-9a06-c491731794fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773418222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.773418222
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.3719471438
Short name T46
Test name
Test status
Simulation time 319896117955 ps
CPU time 171.42 seconds
Started Jul 30 06:13:13 PM PDT 24
Finished Jul 30 06:16:05 PM PDT 24
Peak memory 191640 kb
Host smart-86fe7bc3-19a0-47da-a112-4481068bfabd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719471438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.3719471438
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.1326051564
Short name T269
Test name
Test status
Simulation time 17641722327 ps
CPU time 8.22 seconds
Started Jul 30 06:13:18 PM PDT 24
Finished Jul 30 06:13:26 PM PDT 24
Peak memory 183384 kb
Host smart-ef5b72b7-1155-47d8-96ed-a9be26758e9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326051564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.1326051564
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.2768376908
Short name T296
Test name
Test status
Simulation time 321069170547 ps
CPU time 287.65 seconds
Started Jul 30 06:13:19 PM PDT 24
Finished Jul 30 06:18:07 PM PDT 24
Peak memory 191676 kb
Host smart-b1a05127-8147-4582-af45-efdce1d1d32e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768376908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.2768376908
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.1364138339
Short name T347
Test name
Test status
Simulation time 330713182316 ps
CPU time 170.77 seconds
Started Jul 30 06:13:18 PM PDT 24
Finished Jul 30 06:16:09 PM PDT 24
Peak memory 191680 kb
Host smart-b4b39333-15aa-4a00-a7ea-b92a2ceafd3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364138339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.1364138339
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.3478375802
Short name T251
Test name
Test status
Simulation time 80023384534 ps
CPU time 120.93 seconds
Started Jul 30 06:13:20 PM PDT 24
Finished Jul 30 06:15:21 PM PDT 24
Peak memory 191628 kb
Host smart-b8050e32-e752-44b8-8db6-88363100b969
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478375802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.3478375802
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.601130845
Short name T185
Test name
Test status
Simulation time 151327564945 ps
CPU time 1866.03 seconds
Started Jul 30 06:13:20 PM PDT 24
Finished Jul 30 06:44:27 PM PDT 24
Peak memory 191616 kb
Host smart-cc6c9553-18fd-4e68-9250-0580b29de289
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601130845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.601130845
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.4144224213
Short name T338
Test name
Test status
Simulation time 56215640664 ps
CPU time 32.24 seconds
Started Jul 30 06:11:21 PM PDT 24
Finished Jul 30 06:11:54 PM PDT 24
Peak memory 183484 kb
Host smart-7947c52e-88f8-42fa-9806-342844e2129d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144224213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.4144224213
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.1515818649
Short name T7
Test name
Test status
Simulation time 526941747630 ps
CPU time 215.82 seconds
Started Jul 30 06:11:18 PM PDT 24
Finished Jul 30 06:14:54 PM PDT 24
Peak memory 183444 kb
Host smart-b51479be-71f5-4065-9699-ffaca2836fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515818649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.1515818649
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.2814599287
Short name T237
Test name
Test status
Simulation time 50421941804 ps
CPU time 72.83 seconds
Started Jul 30 06:11:38 PM PDT 24
Finished Jul 30 06:12:51 PM PDT 24
Peak memory 191600 kb
Host smart-6ca4d96d-b0d2-4194-bf91-a7a15b6a27f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814599287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.2814599287
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.1574627018
Short name T182
Test name
Test status
Simulation time 41342147430 ps
CPU time 360.45 seconds
Started Jul 30 06:11:38 PM PDT 24
Finished Jul 30 06:17:39 PM PDT 24
Peak memory 183408 kb
Host smart-f4fab7bf-aef7-4f81-85a8-6a6ad4847db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574627018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.1574627018
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.3838331153
Short name T309
Test name
Test status
Simulation time 460089448428 ps
CPU time 117.82 seconds
Started Jul 30 06:13:26 PM PDT 24
Finished Jul 30 06:15:24 PM PDT 24
Peak memory 183392 kb
Host smart-418b7c9b-422b-422e-b0c8-5861b841bcbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838331153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.3838331153
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.1180869544
Short name T155
Test name
Test status
Simulation time 328455393402 ps
CPU time 412.39 seconds
Started Jul 30 06:13:25 PM PDT 24
Finished Jul 30 06:20:18 PM PDT 24
Peak memory 191696 kb
Host smart-92c90e95-3501-4f61-8c46-09ef3ef5d433
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180869544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.1180869544
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.255655171
Short name T9
Test name
Test status
Simulation time 21152304892 ps
CPU time 34.75 seconds
Started Jul 30 06:13:26 PM PDT 24
Finished Jul 30 06:14:00 PM PDT 24
Peak memory 183500 kb
Host smart-d42a404f-c5f9-469c-84d1-85f7337c9f53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255655171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.255655171
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.133443999
Short name T276
Test name
Test status
Simulation time 1794525077365 ps
CPU time 519.91 seconds
Started Jul 30 06:13:23 PM PDT 24
Finished Jul 30 06:22:03 PM PDT 24
Peak memory 191668 kb
Host smart-461e6922-f061-4c06-8cdb-e261842f7061
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133443999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.133443999
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.1394729230
Short name T206
Test name
Test status
Simulation time 88920169430 ps
CPU time 329.06 seconds
Started Jul 30 06:13:31 PM PDT 24
Finished Jul 30 06:19:00 PM PDT 24
Peak memory 191640 kb
Host smart-3270c1ea-70e3-45fa-97bf-5d127446237f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394729230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.1394729230
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.2617667806
Short name T75
Test name
Test status
Simulation time 219737458184 ps
CPU time 105.59 seconds
Started Jul 30 06:13:30 PM PDT 24
Finished Jul 30 06:15:16 PM PDT 24
Peak memory 191660 kb
Host smart-7cea7f08-0c55-41fa-b5f2-f4681f37922b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617667806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.2617667806
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.1016003642
Short name T298
Test name
Test status
Simulation time 154026243450 ps
CPU time 721.35 seconds
Started Jul 30 06:13:33 PM PDT 24
Finished Jul 30 06:25:34 PM PDT 24
Peak memory 191588 kb
Host smart-cea4bcc9-d6ad-425a-9a44-b45f02a6faf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016003642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.1016003642
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.3309113888
Short name T317
Test name
Test status
Simulation time 142710373219 ps
CPU time 122.11 seconds
Started Jul 30 06:13:34 PM PDT 24
Finished Jul 30 06:15:36 PM PDT 24
Peak memory 191652 kb
Host smart-00f2a579-19af-4562-92bb-f4b5f36fd392
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309113888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.3309113888
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.2698524383
Short name T320
Test name
Test status
Simulation time 131083604328 ps
CPU time 542.09 seconds
Started Jul 30 06:13:32 PM PDT 24
Finished Jul 30 06:22:35 PM PDT 24
Peak memory 191672 kb
Host smart-629420f4-ec79-4e70-8ea9-964a2031e918
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698524383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.2698524383
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.1029008004
Short name T178
Test name
Test status
Simulation time 205215997973 ps
CPU time 337.04 seconds
Started Jul 30 06:11:20 PM PDT 24
Finished Jul 30 06:16:57 PM PDT 24
Peak memory 183468 kb
Host smart-f03aa05c-2b8f-4eb1-aea2-970cf4729f96
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029008004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.1029008004
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.3067889589
Short name T435
Test name
Test status
Simulation time 59096836061 ps
CPU time 44.01 seconds
Started Jul 30 06:11:36 PM PDT 24
Finished Jul 30 06:12:21 PM PDT 24
Peak memory 183492 kb
Host smart-b687ec39-131a-40a3-b484-4e8de3f0f4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067889589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.3067889589
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.2627982242
Short name T288
Test name
Test status
Simulation time 826418863793 ps
CPU time 1504.36 seconds
Started Jul 30 06:11:34 PM PDT 24
Finished Jul 30 06:36:39 PM PDT 24
Peak memory 191684 kb
Host smart-0625b39f-c66a-4207-b46c-e5382fc099f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627982242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.2627982242
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.3270312741
Short name T404
Test name
Test status
Simulation time 5233125590 ps
CPU time 4.58 seconds
Started Jul 30 06:11:39 PM PDT 24
Finished Jul 30 06:11:44 PM PDT 24
Peak memory 194800 kb
Host smart-49b784b1-f2d9-4f4e-a44a-081fd6c4393e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270312741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.3270312741
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.4167649841
Short name T428
Test name
Test status
Simulation time 232904482074 ps
CPU time 122.62 seconds
Started Jul 30 06:13:37 PM PDT 24
Finished Jul 30 06:15:40 PM PDT 24
Peak memory 191812 kb
Host smart-7bec129d-203a-429c-8436-b4df54f95e2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167649841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.4167649841
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.1167819285
Short name T215
Test name
Test status
Simulation time 387750132208 ps
CPU time 119.83 seconds
Started Jul 30 06:13:36 PM PDT 24
Finished Jul 30 06:15:36 PM PDT 24
Peak memory 191636 kb
Host smart-ab166363-9980-4320-b26d-7300ab5b4685
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167819285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.1167819285
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.2989960163
Short name T274
Test name
Test status
Simulation time 453160560002 ps
CPU time 642.42 seconds
Started Jul 30 06:13:37 PM PDT 24
Finished Jul 30 06:24:19 PM PDT 24
Peak memory 191652 kb
Host smart-7f60f112-7d1e-4bfb-989b-46e41dc1c69a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989960163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.2989960163
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.183141333
Short name T163
Test name
Test status
Simulation time 436534850059 ps
CPU time 304.87 seconds
Started Jul 30 06:13:42 PM PDT 24
Finished Jul 30 06:18:47 PM PDT 24
Peak memory 191664 kb
Host smart-0af38e45-4927-43ed-b49e-a2a5f996d7b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183141333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.183141333
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.3031100652
Short name T116
Test name
Test status
Simulation time 20816188166 ps
CPU time 75.53 seconds
Started Jul 30 06:13:43 PM PDT 24
Finished Jul 30 06:14:59 PM PDT 24
Peak memory 191656 kb
Host smart-afc05680-fafc-4cf8-b263-7574ed299b77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031100652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.3031100652
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.3908541131
Short name T228
Test name
Test status
Simulation time 140026616367 ps
CPU time 65.22 seconds
Started Jul 30 06:13:43 PM PDT 24
Finished Jul 30 06:14:48 PM PDT 24
Peak memory 191652 kb
Host smart-4f8328ab-46b7-449f-bd83-ca68150fcc8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908541131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.3908541131
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.3181895899
Short name T192
Test name
Test status
Simulation time 164533272381 ps
CPU time 729.84 seconds
Started Jul 30 06:13:44 PM PDT 24
Finished Jul 30 06:25:54 PM PDT 24
Peak memory 193772 kb
Host smart-08f53d3a-1477-40b5-ae37-b5770ecff4f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181895899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.3181895899
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.560308592
Short name T173
Test name
Test status
Simulation time 123815336256 ps
CPU time 104.2 seconds
Started Jul 30 06:11:35 PM PDT 24
Finished Jul 30 06:13:19 PM PDT 24
Peak memory 183376 kb
Host smart-d1c9fbe9-28a6-4dc2-8f0c-e13f94356c18
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560308592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.rv_timer_cfg_update_on_fly.560308592
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.1018854838
Short name T388
Test name
Test status
Simulation time 636016268372 ps
CPU time 256.04 seconds
Started Jul 30 06:11:34 PM PDT 24
Finished Jul 30 06:15:50 PM PDT 24
Peak memory 183424 kb
Host smart-86d692fe-fe53-478e-9e20-5f02ad9702c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018854838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.1018854838
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.3697562752
Short name T268
Test name
Test status
Simulation time 227917342195 ps
CPU time 185.54 seconds
Started Jul 30 06:11:36 PM PDT 24
Finished Jul 30 06:14:42 PM PDT 24
Peak memory 191656 kb
Host smart-dd75f226-ee09-4347-bb92-212027cc816e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697562752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.3697562752
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.4062377074
Short name T395
Test name
Test status
Simulation time 77344121 ps
CPU time 0.57 seconds
Started Jul 30 06:11:21 PM PDT 24
Finished Jul 30 06:11:21 PM PDT 24
Peak memory 183244 kb
Host smart-78df80ac-9818-4b44-a59c-8466101998bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062377074 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.4062377074
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.3465898913
Short name T53
Test name
Test status
Simulation time 58992518744 ps
CPU time 415.33 seconds
Started Jul 30 06:11:33 PM PDT 24
Finished Jul 30 06:18:28 PM PDT 24
Peak memory 206404 kb
Host smart-29fca6c2-fb50-4cb0-958d-ecde27881f9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465898913 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all_with_rand_reset.3465898913
Directory /workspace/18.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.rv_timer_random.2964674349
Short name T151
Test name
Test status
Simulation time 474916328668 ps
CPU time 290.67 seconds
Started Jul 30 06:13:48 PM PDT 24
Finished Jul 30 06:18:39 PM PDT 24
Peak memory 191628 kb
Host smart-3f436aea-332e-46f7-8a57-b4a57bf87a53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964674349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.2964674349
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.1362862013
Short name T348
Test name
Test status
Simulation time 90851432463 ps
CPU time 637.96 seconds
Started Jul 30 06:13:54 PM PDT 24
Finished Jul 30 06:24:32 PM PDT 24
Peak memory 183472 kb
Host smart-71f0e2af-834e-4886-96f9-f97961d608ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362862013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.1362862013
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.2105003286
Short name T439
Test name
Test status
Simulation time 21044869865 ps
CPU time 10.46 seconds
Started Jul 30 06:13:56 PM PDT 24
Finished Jul 30 06:14:07 PM PDT 24
Peak memory 183444 kb
Host smart-4ac87101-ae41-408c-969d-91c6adc56567
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105003286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.2105003286
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.699451017
Short name T427
Test name
Test status
Simulation time 474658573598 ps
CPU time 80.29 seconds
Started Jul 30 06:11:21 PM PDT 24
Finished Jul 30 06:12:42 PM PDT 24
Peak memory 183440 kb
Host smart-2edd767c-10f0-4fd7-9773-532230a0ee7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699451017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.699451017
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.638701314
Short name T62
Test name
Test status
Simulation time 87395129876 ps
CPU time 72.16 seconds
Started Jul 30 06:11:34 PM PDT 24
Finished Jul 30 06:12:46 PM PDT 24
Peak memory 191604 kb
Host smart-9dced81e-1aaf-4a2a-be64-cfddcebdbc62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638701314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.638701314
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.2322034078
Short name T119
Test name
Test status
Simulation time 124458150488 ps
CPU time 246.1 seconds
Started Jul 30 06:13:51 PM PDT 24
Finished Jul 30 06:17:58 PM PDT 24
Peak memory 191584 kb
Host smart-bbe6a008-4e30-4c80-9e09-e9b5067425d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322034078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.2322034078
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.3886052484
Short name T328
Test name
Test status
Simulation time 228674932543 ps
CPU time 82.17 seconds
Started Jul 30 06:13:51 PM PDT 24
Finished Jul 30 06:15:14 PM PDT 24
Peak memory 183484 kb
Host smart-0f1ff37e-33e7-4834-8815-dce86a76f893
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886052484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.3886052484
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.763113206
Short name T27
Test name
Test status
Simulation time 249538375137 ps
CPU time 429.29 seconds
Started Jul 30 06:13:53 PM PDT 24
Finished Jul 30 06:21:02 PM PDT 24
Peak memory 191616 kb
Host smart-5c36e21e-4ed8-499d-8652-72d7664ce915
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763113206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.763113206
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.3822607925
Short name T335
Test name
Test status
Simulation time 247180404639 ps
CPU time 200.93 seconds
Started Jul 30 06:13:54 PM PDT 24
Finished Jul 30 06:17:15 PM PDT 24
Peak memory 191672 kb
Host smart-c369ff2d-2b24-48ef-9f18-20bd55c190bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822607925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.3822607925
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.2885518796
Short name T197
Test name
Test status
Simulation time 18085970251 ps
CPU time 43.64 seconds
Started Jul 30 06:13:56 PM PDT 24
Finished Jul 30 06:14:40 PM PDT 24
Peak memory 194684 kb
Host smart-87e0263f-be3a-4fb3-b4f1-69c252a66b5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885518796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.2885518796
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.849624774
Short name T354
Test name
Test status
Simulation time 280053010338 ps
CPU time 993.44 seconds
Started Jul 30 06:14:00 PM PDT 24
Finished Jul 30 06:30:34 PM PDT 24
Peak memory 191668 kb
Host smart-b00bcd63-0401-458f-ab96-c011c649d56f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849624774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.849624774
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.3159437831
Short name T111
Test name
Test status
Simulation time 499727523731 ps
CPU time 401.23 seconds
Started Jul 30 06:11:27 PM PDT 24
Finished Jul 30 06:18:08 PM PDT 24
Peak memory 183348 kb
Host smart-61aa184d-1123-43da-9c0e-68d0665aa916
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159437831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.3159437831
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.2632036871
Short name T413
Test name
Test status
Simulation time 135223054873 ps
CPU time 195.6 seconds
Started Jul 30 06:11:06 PM PDT 24
Finished Jul 30 06:14:22 PM PDT 24
Peak memory 183440 kb
Host smart-4e02ece3-b992-436a-b85f-e4776f90b2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632036871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.2632036871
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.3012604839
Short name T59
Test name
Test status
Simulation time 46050068481 ps
CPU time 357.85 seconds
Started Jul 30 06:11:14 PM PDT 24
Finished Jul 30 06:17:12 PM PDT 24
Peak memory 191592 kb
Host smart-bf5349c9-b138-4386-8e35-f1bdab4b3078
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012604839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.3012604839
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.609357037
Short name T375
Test name
Test status
Simulation time 301405342 ps
CPU time 1.15 seconds
Started Jul 30 06:11:06 PM PDT 24
Finished Jul 30 06:11:08 PM PDT 24
Peak memory 192988 kb
Host smart-613cb101-309f-4aa2-8bcf-634ccd059a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609357037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.609357037
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.914403336
Short name T19
Test name
Test status
Simulation time 444788626 ps
CPU time 1.14 seconds
Started Jul 30 06:11:33 PM PDT 24
Finished Jul 30 06:11:34 PM PDT 24
Peak memory 214996 kb
Host smart-6e2e6386-798d-4750-8ff1-1ae9df507ecb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914403336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.914403336
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.2192751379
Short name T446
Test name
Test status
Simulation time 135709780452 ps
CPU time 205.76 seconds
Started Jul 30 06:11:08 PM PDT 24
Finished Jul 30 06:14:34 PM PDT 24
Peak memory 183388 kb
Host smart-8fa9ff54-297f-418f-af92-d5f15031325b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192751379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
2192751379
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.762601417
Short name T43
Test name
Test status
Simulation time 1177927321923 ps
CPU time 597.69 seconds
Started Jul 30 06:11:21 PM PDT 24
Finished Jul 30 06:21:19 PM PDT 24
Peak memory 183400 kb
Host smart-199087f9-e3ba-4257-b94d-dcb66dcbf585
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762601417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.rv_timer_cfg_update_on_fly.762601417
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.969108617
Short name T399
Test name
Test status
Simulation time 635548951700 ps
CPU time 260.15 seconds
Started Jul 30 06:11:39 PM PDT 24
Finished Jul 30 06:16:00 PM PDT 24
Peak memory 183368 kb
Host smart-3ea24ffe-3ec7-4a8b-a228-d87101f2e995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969108617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.969108617
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.1048195167
Short name T10
Test name
Test status
Simulation time 42333738172 ps
CPU time 83.85 seconds
Started Jul 30 06:11:36 PM PDT 24
Finished Jul 30 06:12:59 PM PDT 24
Peak memory 183432 kb
Host smart-ccd42251-870f-4233-8667-a34e602108e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048195167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.1048195167
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.2569501394
Short name T402
Test name
Test status
Simulation time 84105985 ps
CPU time 1.33 seconds
Started Jul 30 06:11:22 PM PDT 24
Finished Jul 30 06:11:24 PM PDT 24
Peak memory 183424 kb
Host smart-02299a3f-cc1a-4c35-95cc-e0016c15ec5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569501394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.2569501394
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.40088585
Short name T397
Test name
Test status
Simulation time 786101347446 ps
CPU time 234.01 seconds
Started Jul 30 06:11:42 PM PDT 24
Finished Jul 30 06:15:36 PM PDT 24
Peak memory 191624 kb
Host smart-79b407f7-f107-41e5-83db-b462a180f994
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40088585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all.40088585
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.1929607052
Short name T124
Test name
Test status
Simulation time 258694587748 ps
CPU time 414.67 seconds
Started Jul 30 06:11:40 PM PDT 24
Finished Jul 30 06:18:35 PM PDT 24
Peak memory 183376 kb
Host smart-b8ce8eaf-821b-4e1f-b1fd-3c860e48260d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929607052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.1929607052
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.80333814
Short name T378
Test name
Test status
Simulation time 251657423319 ps
CPU time 164.91 seconds
Started Jul 30 06:11:22 PM PDT 24
Finished Jul 30 06:14:07 PM PDT 24
Peak memory 183508 kb
Host smart-1acf2f87-3dd7-455b-a4e7-d9ed86732430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80333814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.80333814
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.268555638
Short name T343
Test name
Test status
Simulation time 4584547927143 ps
CPU time 573.25 seconds
Started Jul 30 06:11:42 PM PDT 24
Finished Jul 30 06:21:15 PM PDT 24
Peak memory 191660 kb
Host smart-992c3253-3111-4aab-a57e-4a69ea8ea428
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268555638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all.
268555638
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.2009300787
Short name T253
Test name
Test status
Simulation time 142827038726 ps
CPU time 139.56 seconds
Started Jul 30 06:11:19 PM PDT 24
Finished Jul 30 06:13:39 PM PDT 24
Peak memory 183436 kb
Host smart-d9738bf9-8a96-49b5-9138-00e76e12cfde
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009300787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.2009300787
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.1656878183
Short name T453
Test name
Test status
Simulation time 84415288174 ps
CPU time 117.38 seconds
Started Jul 30 06:11:23 PM PDT 24
Finished Jul 30 06:13:20 PM PDT 24
Peak memory 183480 kb
Host smart-ce5e1717-7968-447f-a08b-f75a73149046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656878183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.1656878183
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.3151706272
Short name T126
Test name
Test status
Simulation time 2976111484578 ps
CPU time 752.19 seconds
Started Jul 30 06:11:23 PM PDT 24
Finished Jul 30 06:23:55 PM PDT 24
Peak memory 191664 kb
Host smart-ffc487dd-f5be-459c-b900-f0894e8c5619
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151706272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.3151706272
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.34889195
Short name T441
Test name
Test status
Simulation time 32068681426 ps
CPU time 106.41 seconds
Started Jul 30 06:11:40 PM PDT 24
Finished Jul 30 06:13:27 PM PDT 24
Peak memory 193920 kb
Host smart-e2b5eea6-b966-42b3-ab99-80781cffc7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34889195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.34889195
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all_with_rand_reset.78307367
Short name T420
Test name
Test status
Simulation time 92437346767 ps
CPU time 193.58 seconds
Started Jul 30 06:11:20 PM PDT 24
Finished Jul 30 06:14:34 PM PDT 24
Peak memory 198152 kb
Host smart-49ba5e2a-672e-44e2-ae48-c37206a94b69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78307367 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all_with_rand_reset.78307367
Directory /workspace/22.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.2700560998
Short name T191
Test name
Test status
Simulation time 135821573241 ps
CPU time 154.58 seconds
Started Jul 30 06:11:41 PM PDT 24
Finished Jul 30 06:14:16 PM PDT 24
Peak memory 183428 kb
Host smart-b74872ec-47bf-4230-b1cb-941bc07f0117
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700560998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.2700560998
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.2831122919
Short name T416
Test name
Test status
Simulation time 30477965164 ps
CPU time 38.59 seconds
Started Jul 30 06:11:44 PM PDT 24
Finished Jul 30 06:12:23 PM PDT 24
Peak memory 183388 kb
Host smart-36456e29-daf3-4659-a563-7dc85e3211fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831122919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.2831122919
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.3047465577
Short name T267
Test name
Test status
Simulation time 244073461076 ps
CPU time 474.83 seconds
Started Jul 30 06:11:22 PM PDT 24
Finished Jul 30 06:19:17 PM PDT 24
Peak memory 191688 kb
Host smart-6d45e112-4231-408e-98ef-0d64ee382734
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047465577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.3047465577
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.1317881974
Short name T284
Test name
Test status
Simulation time 7172224653 ps
CPU time 11.56 seconds
Started Jul 30 06:11:41 PM PDT 24
Finished Jul 30 06:11:53 PM PDT 24
Peak memory 183360 kb
Host smart-68a3ef13-ad24-4aae-8075-e5f06b5583e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317881974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.1317881974
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.4117643825
Short name T157
Test name
Test status
Simulation time 96945332476 ps
CPU time 50.53 seconds
Started Jul 30 06:11:26 PM PDT 24
Finished Jul 30 06:12:17 PM PDT 24
Peak memory 183432 kb
Host smart-8318eb5e-3f50-4c42-a34d-82546bd493af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117643825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.4117643825
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.135454351
Short name T360
Test name
Test status
Simulation time 70039659579 ps
CPU time 40.91 seconds
Started Jul 30 06:11:28 PM PDT 24
Finished Jul 30 06:12:09 PM PDT 24
Peak memory 183412 kb
Host smart-540ac25c-032c-41a6-8b1e-6a6d580294ce
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135454351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.rv_timer_cfg_update_on_fly.135454351
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.11277634
Short name T369
Test name
Test status
Simulation time 286053853174 ps
CPU time 192.41 seconds
Started Jul 30 06:11:32 PM PDT 24
Finished Jul 30 06:14:45 PM PDT 24
Peak memory 183488 kb
Host smart-5233214a-3abf-4511-95bf-01b0ff9f8747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11277634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.11277634
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.2317899107
Short name T233
Test name
Test status
Simulation time 564134072236 ps
CPU time 300.78 seconds
Started Jul 30 06:11:36 PM PDT 24
Finished Jul 30 06:16:37 PM PDT 24
Peak memory 191552 kb
Host smart-5b8ff58e-77f5-4685-8746-d82b3fc56f69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317899107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.2317899107
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.1647349679
Short name T315
Test name
Test status
Simulation time 186269231746 ps
CPU time 769.72 seconds
Started Jul 30 06:11:25 PM PDT 24
Finished Jul 30 06:24:15 PM PDT 24
Peak memory 191680 kb
Host smart-36b1bf3f-22ed-4314-9797-30bba3fff7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647349679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.1647349679
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.3756141947
Short name T414
Test name
Test status
Simulation time 224995376624 ps
CPU time 317.26 seconds
Started Jul 30 06:11:38 PM PDT 24
Finished Jul 30 06:16:55 PM PDT 24
Peak memory 191588 kb
Host smart-9fa1d096-fc9d-437b-b639-168169944ad7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756141947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.3756141947
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.848039325
Short name T295
Test name
Test status
Simulation time 268864991365 ps
CPU time 133.41 seconds
Started Jul 30 06:11:39 PM PDT 24
Finished Jul 30 06:13:53 PM PDT 24
Peak memory 183456 kb
Host smart-87768e3a-f51c-4a44-9bcd-e823c0b818f5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848039325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.rv_timer_cfg_update_on_fly.848039325
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.12684646
Short name T372
Test name
Test status
Simulation time 17989096074 ps
CPU time 8.06 seconds
Started Jul 30 06:11:47 PM PDT 24
Finished Jul 30 06:11:55 PM PDT 24
Peak memory 183476 kb
Host smart-c277c667-5b4c-4ccf-8d8d-0a3c4ea9a09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12684646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.12684646
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.2727982376
Short name T344
Test name
Test status
Simulation time 400010028686 ps
CPU time 830.17 seconds
Started Jul 30 06:11:27 PM PDT 24
Finished Jul 30 06:25:17 PM PDT 24
Peak memory 191644 kb
Host smart-bbc99034-3659-4ae9-a3f7-f1efbc4a8432
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727982376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.2727982376
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.1503063560
Short name T271
Test name
Test status
Simulation time 356788522982 ps
CPU time 421.83 seconds
Started Jul 30 06:11:26 PM PDT 24
Finished Jul 30 06:18:28 PM PDT 24
Peak memory 183460 kb
Host smart-11d93d86-22f1-4c4e-a69f-c2742a005781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503063560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.1503063560
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.2343926173
Short name T118
Test name
Test status
Simulation time 1958091128842 ps
CPU time 981.18 seconds
Started Jul 30 06:11:25 PM PDT 24
Finished Jul 30 06:27:46 PM PDT 24
Peak memory 183516 kb
Host smart-aea0e161-aef8-4bb1-81b5-b4dc5390981b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343926173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.2343926173
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.1852854105
Short name T379
Test name
Test status
Simulation time 349974403294 ps
CPU time 163.16 seconds
Started Jul 30 06:11:25 PM PDT 24
Finished Jul 30 06:14:08 PM PDT 24
Peak memory 183520 kb
Host smart-559201d4-9a5b-4d42-919c-128631e96be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852854105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.1852854105
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.3247005556
Short name T341
Test name
Test status
Simulation time 509511865566 ps
CPU time 613.15 seconds
Started Jul 30 06:11:26 PM PDT 24
Finished Jul 30 06:21:39 PM PDT 24
Peak memory 191644 kb
Host smart-0c0c91be-1afa-40bd-9a69-a756763f1074
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247005556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.3247005556
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.1475734895
Short name T193
Test name
Test status
Simulation time 289043129466 ps
CPU time 434.05 seconds
Started Jul 30 06:11:24 PM PDT 24
Finished Jul 30 06:18:38 PM PDT 24
Peak memory 183492 kb
Host smart-401e919c-73d9-48a0-9a04-13ac600b3457
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475734895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.1475734895
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.2570045553
Short name T389
Test name
Test status
Simulation time 59206490125 ps
CPU time 78.67 seconds
Started Jul 30 06:11:24 PM PDT 24
Finished Jul 30 06:12:43 PM PDT 24
Peak memory 183468 kb
Host smart-b5b8c44d-16cf-4b1b-8af2-6443cbdc5e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570045553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.2570045553
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.3196571625
Short name T226
Test name
Test status
Simulation time 1865077957 ps
CPU time 1.28 seconds
Started Jul 30 06:11:43 PM PDT 24
Finished Jul 30 06:11:44 PM PDT 24
Peak memory 192304 kb
Host smart-4847d0b1-3de2-4081-924a-644a833001ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196571625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.3196571625
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.1441652771
Short name T67
Test name
Test status
Simulation time 186017439332 ps
CPU time 180.58 seconds
Started Jul 30 06:11:24 PM PDT 24
Finished Jul 30 06:14:25 PM PDT 24
Peak memory 183512 kb
Host smart-e54731a4-cd51-4920-814c-895218c5ef0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441652771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.1441652771
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.1606229891
Short name T332
Test name
Test status
Simulation time 1180153321911 ps
CPU time 858.4 seconds
Started Jul 30 06:11:38 PM PDT 24
Finished Jul 30 06:25:56 PM PDT 24
Peak memory 183448 kb
Host smart-9495acc2-877e-43de-8d3f-5bf1ba9d3bff
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606229891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.1606229891
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.808527083
Short name T410
Test name
Test status
Simulation time 94837740459 ps
CPU time 110.82 seconds
Started Jul 30 06:11:40 PM PDT 24
Finished Jul 30 06:13:31 PM PDT 24
Peak memory 183516 kb
Host smart-1714f29a-cb63-4252-b9ca-cdc95c8fb98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808527083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.808527083
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.75456090
Short name T105
Test name
Test status
Simulation time 223499508456 ps
CPU time 205.29 seconds
Started Jul 30 06:11:45 PM PDT 24
Finished Jul 30 06:15:10 PM PDT 24
Peak memory 191644 kb
Host smart-4ac57771-cc60-4f5b-8c64-48ef78933c12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75456090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.75456090
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.476908544
Short name T353
Test name
Test status
Simulation time 24221662945 ps
CPU time 570.85 seconds
Started Jul 30 06:11:44 PM PDT 24
Finished Jul 30 06:21:15 PM PDT 24
Peak memory 183412 kb
Host smart-0f6b198b-07d2-49ef-ac2c-b22637931a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476908544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.476908544
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.4005936995
Short name T455
Test name
Test status
Simulation time 1442403854789 ps
CPU time 761.11 seconds
Started Jul 30 06:11:24 PM PDT 24
Finished Jul 30 06:24:06 PM PDT 24
Peak memory 191716 kb
Host smart-b62d81fa-80ad-4e6c-a952-f882651de73b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005936995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.4005936995
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.1363918319
Short name T239
Test name
Test status
Simulation time 50482418502 ps
CPU time 24.28 seconds
Started Jul 30 06:11:25 PM PDT 24
Finished Jul 30 06:11:50 PM PDT 24
Peak memory 183376 kb
Host smart-ee653619-c13a-4a58-9299-5ff4cac6968a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363918319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.1363918319
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.2711438778
Short name T44
Test name
Test status
Simulation time 157646046553 ps
CPU time 233.41 seconds
Started Jul 30 06:11:32 PM PDT 24
Finished Jul 30 06:15:25 PM PDT 24
Peak memory 183444 kb
Host smart-b791d856-a9a9-4426-8246-058870ace77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711438778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.2711438778
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.1217697890
Short name T11
Test name
Test status
Simulation time 12428036767 ps
CPU time 5.67 seconds
Started Jul 30 06:11:46 PM PDT 24
Finished Jul 30 06:11:52 PM PDT 24
Peak memory 183508 kb
Host smart-bef85de3-b0f6-4622-b0ec-52e0e22b7216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217697890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.1217697890
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.631838788
Short name T159
Test name
Test status
Simulation time 322211367157 ps
CPU time 264.26 seconds
Started Jul 30 06:11:33 PM PDT 24
Finished Jul 30 06:15:57 PM PDT 24
Peak memory 195316 kb
Host smart-355a8607-6cc3-4a9f-9ef2-ec3ed994f76e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631838788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all.
631838788
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.3164021360
Short name T130
Test name
Test status
Simulation time 18238116578 ps
CPU time 16.55 seconds
Started Jul 30 06:11:20 PM PDT 24
Finished Jul 30 06:11:36 PM PDT 24
Peak memory 183404 kb
Host smart-d3efea0f-26c8-4220-a9d4-777e2c2ed981
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164021360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.3164021360
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.4089266755
Short name T390
Test name
Test status
Simulation time 138801291967 ps
CPU time 176.9 seconds
Started Jul 30 06:11:05 PM PDT 24
Finished Jul 30 06:14:02 PM PDT 24
Peak memory 183444 kb
Host smart-1d67e421-7860-477c-85aa-d2bd63308818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089266755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.4089266755
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.2192422726
Short name T443
Test name
Test status
Simulation time 36676616069 ps
CPU time 33.87 seconds
Started Jul 30 06:11:30 PM PDT 24
Finished Jul 30 06:12:04 PM PDT 24
Peak memory 183348 kb
Host smart-b0928dad-8393-44ba-84cd-bbad89318c24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192422726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.2192422726
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.2065409246
Short name T16
Test name
Test status
Simulation time 172478888 ps
CPU time 0.75 seconds
Started Jul 30 06:11:35 PM PDT 24
Finished Jul 30 06:11:35 PM PDT 24
Peak memory 214000 kb
Host smart-db97720a-4175-474c-88ff-42e05b61b86d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065409246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.2065409246
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.2217120589
Short name T451
Test name
Test status
Simulation time 896800215685 ps
CPU time 315.11 seconds
Started Jul 30 06:11:16 PM PDT 24
Finished Jul 30 06:16:31 PM PDT 24
Peak memory 191592 kb
Host smart-544217ad-3011-42b5-b6fe-c34fe6a9eab5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217120589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
2217120589
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all_with_rand_reset.1714021763
Short name T14
Test name
Test status
Simulation time 234182205046 ps
CPU time 430.7 seconds
Started Jul 30 06:11:13 PM PDT 24
Finished Jul 30 06:18:24 PM PDT 24
Peak memory 206340 kb
Host smart-6a6bb446-4c2a-4756-a4f6-b570da5975eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714021763 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all_with_rand_reset.1714021763
Directory /workspace/3.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.7067807
Short name T425
Test name
Test status
Simulation time 1102982447605 ps
CPU time 548.32 seconds
Started Jul 30 06:11:25 PM PDT 24
Finished Jul 30 06:20:33 PM PDT 24
Peak memory 183476 kb
Host smart-41bcdf5c-bba2-4b77-bb39-9c3f4bdef9f5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7067807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
rv_timer_cfg_update_on_fly.7067807
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.1481681153
Short name T429
Test name
Test status
Simulation time 295858126908 ps
CPU time 223.21 seconds
Started Jul 30 06:11:39 PM PDT 24
Finished Jul 30 06:15:22 PM PDT 24
Peak memory 183488 kb
Host smart-81ffa7ac-4775-47ce-80b6-fcab23680907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481681153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.1481681153
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.4085492279
Short name T322
Test name
Test status
Simulation time 615502350582 ps
CPU time 367.71 seconds
Started Jul 30 06:11:24 PM PDT 24
Finished Jul 30 06:17:32 PM PDT 24
Peak memory 191676 kb
Host smart-186b5ea9-659a-4c21-a450-95aaaafec3ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085492279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.4085492279
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.3925161470
Short name T319
Test name
Test status
Simulation time 168640741593 ps
CPU time 85.06 seconds
Started Jul 30 06:11:24 PM PDT 24
Finished Jul 30 06:12:49 PM PDT 24
Peak memory 191672 kb
Host smart-5c8bca8a-6b6d-4104-b9be-38ceb7191ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925161470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.3925161470
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.2131563942
Short name T391
Test name
Test status
Simulation time 86581351893 ps
CPU time 33.78 seconds
Started Jul 30 06:11:33 PM PDT 24
Finished Jul 30 06:12:07 PM PDT 24
Peak memory 183448 kb
Host smart-324eb698-3e8e-489e-b2e9-1f0e87d53086
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131563942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.2131563942
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all_with_rand_reset.23867450
Short name T434
Test name
Test status
Simulation time 60647151267 ps
CPU time 479.29 seconds
Started Jul 30 06:11:25 PM PDT 24
Finished Jul 30 06:19:24 PM PDT 24
Peak memory 206424 kb
Host smart-5160458b-1044-4f14-ac2f-9e1386ca5314
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23867450 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all_with_rand_reset.23867450
Directory /workspace/30.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.1800422424
Short name T447
Test name
Test status
Simulation time 86196645683 ps
CPU time 61.05 seconds
Started Jul 30 06:11:41 PM PDT 24
Finished Jul 30 06:12:42 PM PDT 24
Peak memory 183484 kb
Host smart-cce704a8-505a-4861-bfa1-4a63a032e117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800422424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.1800422424
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.1601156244
Short name T262
Test name
Test status
Simulation time 582875711796 ps
CPU time 220.62 seconds
Started Jul 30 06:11:38 PM PDT 24
Finished Jul 30 06:15:19 PM PDT 24
Peak memory 191632 kb
Host smart-100255cd-8328-4df7-946e-2ab4484feb65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601156244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.1601156244
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.2318995539
Short name T71
Test name
Test status
Simulation time 1724925176923 ps
CPU time 689.14 seconds
Started Jul 30 06:11:40 PM PDT 24
Finished Jul 30 06:23:09 PM PDT 24
Peak memory 196220 kb
Host smart-3b9d1ad3-555d-4b7b-b1f7-080f8b494e8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318995539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.2318995539
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.3085793366
Short name T240
Test name
Test status
Simulation time 90294898912 ps
CPU time 150.29 seconds
Started Jul 30 06:11:29 PM PDT 24
Finished Jul 30 06:13:59 PM PDT 24
Peak memory 183440 kb
Host smart-ff630960-1477-4275-ab66-2bdc0dedea06
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085793366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.3085793366
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.461967931
Short name T440
Test name
Test status
Simulation time 325295997182 ps
CPU time 245.69 seconds
Started Jul 30 06:11:34 PM PDT 24
Finished Jul 30 06:15:39 PM PDT 24
Peak memory 183464 kb
Host smart-f21b30a2-469f-4d88-b088-9a212a63844a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461967931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.461967931
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.2222842813
Short name T194
Test name
Test status
Simulation time 608614769243 ps
CPU time 398.07 seconds
Started Jul 30 06:11:27 PM PDT 24
Finished Jul 30 06:18:05 PM PDT 24
Peak memory 191644 kb
Host smart-367d825e-5add-4daf-bdf4-9315d8608b23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222842813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.2222842813
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.2604401080
Short name T356
Test name
Test status
Simulation time 35734416833 ps
CPU time 116.58 seconds
Started Jul 30 06:11:33 PM PDT 24
Finished Jul 30 06:13:30 PM PDT 24
Peak memory 191668 kb
Host smart-029b6f97-f847-4c76-9fe0-dc15682143af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604401080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.2604401080
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.644180852
Short name T333
Test name
Test status
Simulation time 158291008816 ps
CPU time 247.05 seconds
Started Jul 30 06:11:24 PM PDT 24
Finished Jul 30 06:15:32 PM PDT 24
Peak memory 183452 kb
Host smart-d62aedc0-8afd-46ab-adde-cbd1be2a4a76
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644180852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.rv_timer_cfg_update_on_fly.644180852
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.4180788871
Short name T418
Test name
Test status
Simulation time 214009877979 ps
CPU time 158.97 seconds
Started Jul 30 06:11:27 PM PDT 24
Finished Jul 30 06:14:06 PM PDT 24
Peak memory 183468 kb
Host smart-057c366a-6642-427d-a439-e6df622e161f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180788871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.4180788871
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.1629444189
Short name T174
Test name
Test status
Simulation time 116414605546 ps
CPU time 53.34 seconds
Started Jul 30 06:11:40 PM PDT 24
Finished Jul 30 06:12:34 PM PDT 24
Peak memory 183456 kb
Host smart-603c7f86-2bab-4b5d-ac27-5378ccf841a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629444189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.1629444189
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.3474477380
Short name T449
Test name
Test status
Simulation time 740739588 ps
CPU time 3.01 seconds
Started Jul 30 06:11:28 PM PDT 24
Finished Jul 30 06:11:32 PM PDT 24
Peak memory 183408 kb
Host smart-85f37a24-952c-4727-baaa-6fb9eb2ab0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474477380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.3474477380
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all_with_rand_reset.2393287742
Short name T52
Test name
Test status
Simulation time 37353683939 ps
CPU time 164.82 seconds
Started Jul 30 06:11:41 PM PDT 24
Finished Jul 30 06:14:26 PM PDT 24
Peak memory 198156 kb
Host smart-079bf6b4-1bf8-4434-b7fb-74361384d165
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393287742 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all_with_rand_reset.2393287742
Directory /workspace/33.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.1766574239
Short name T249
Test name
Test status
Simulation time 848045042744 ps
CPU time 450.34 seconds
Started Jul 30 06:11:29 PM PDT 24
Finished Jul 30 06:18:59 PM PDT 24
Peak memory 183436 kb
Host smart-170d182e-bf34-4941-851e-8bbed7078958
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766574239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.1766574239
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.2690302206
Short name T411
Test name
Test status
Simulation time 33420221261 ps
CPU time 52.65 seconds
Started Jul 30 06:11:28 PM PDT 24
Finished Jul 30 06:12:20 PM PDT 24
Peak memory 183460 kb
Host smart-d57f2b0c-1c1e-4c79-b14e-4218210d755b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690302206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.2690302206
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.3053887714
Short name T220
Test name
Test status
Simulation time 73133913558 ps
CPU time 1362.79 seconds
Started Jul 30 06:11:23 PM PDT 24
Finished Jul 30 06:34:06 PM PDT 24
Peak memory 191640 kb
Host smart-6b8777a3-2c76-4b8b-921d-80542ea8a6db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053887714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.3053887714
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.1784864448
Short name T412
Test name
Test status
Simulation time 181220171 ps
CPU time 1.02 seconds
Started Jul 30 06:11:39 PM PDT 24
Finished Jul 30 06:11:40 PM PDT 24
Peak memory 183232 kb
Host smart-ecbca125-a890-457e-bfb8-e1f87855427b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784864448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.1784864448
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.4062496971
Short name T381
Test name
Test status
Simulation time 341507141079 ps
CPU time 244.05 seconds
Started Jul 30 06:11:42 PM PDT 24
Finished Jul 30 06:15:46 PM PDT 24
Peak memory 183408 kb
Host smart-c2aeb5c1-a678-4ed7-be72-d85e8c9987f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062496971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.4062496971
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.4029481349
Short name T339
Test name
Test status
Simulation time 271783337193 ps
CPU time 181.53 seconds
Started Jul 30 06:11:23 PM PDT 24
Finished Jul 30 06:14:25 PM PDT 24
Peak memory 191648 kb
Host smart-89e0caed-ed12-4dcf-9e8c-3ddafca22e46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029481349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.4029481349
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.3875928678
Short name T28
Test name
Test status
Simulation time 433890613 ps
CPU time 0.69 seconds
Started Jul 30 06:11:33 PM PDT 24
Finished Jul 30 06:11:34 PM PDT 24
Peak memory 183208 kb
Host smart-1dd6ebef-7ec8-45a9-8c8e-4507caaa1ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875928678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.3875928678
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.4166962626
Short name T167
Test name
Test status
Simulation time 554579159366 ps
CPU time 1087.98 seconds
Started Jul 30 06:11:40 PM PDT 24
Finished Jul 30 06:29:49 PM PDT 24
Peak memory 191584 kb
Host smart-5262263f-e5a5-41ae-8a1e-b436d557d9ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166962626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.4166962626
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.3246340136
Short name T199
Test name
Test status
Simulation time 98562360865 ps
CPU time 151.66 seconds
Started Jul 30 06:11:44 PM PDT 24
Finished Jul 30 06:14:16 PM PDT 24
Peak memory 183356 kb
Host smart-55765f59-9a65-40c0-a85c-6353769a63a4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246340136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.3246340136
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.1052107748
Short name T382
Test name
Test status
Simulation time 167666971409 ps
CPU time 215.56 seconds
Started Jul 30 06:11:39 PM PDT 24
Finished Jul 30 06:15:15 PM PDT 24
Peak memory 183368 kb
Host smart-e3c8e4a7-5377-4ba8-815e-9142ec934260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052107748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.1052107748
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.1537329393
Short name T366
Test name
Test status
Simulation time 92004956 ps
CPU time 0.71 seconds
Started Jul 30 06:11:33 PM PDT 24
Finished Jul 30 06:11:34 PM PDT 24
Peak memory 183184 kb
Host smart-644b342e-1c5e-4445-a9ad-b68d7b495bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537329393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.1537329393
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.119714883
Short name T179
Test name
Test status
Simulation time 372078799930 ps
CPU time 455.17 seconds
Started Jul 30 06:11:41 PM PDT 24
Finished Jul 30 06:19:16 PM PDT 24
Peak memory 183380 kb
Host smart-472b2864-a71c-4650-b8c7-3195c04b013e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119714883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.rv_timer_cfg_update_on_fly.119714883
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.3260708437
Short name T424
Test name
Test status
Simulation time 36299425682 ps
CPU time 25.08 seconds
Started Jul 30 06:11:43 PM PDT 24
Finished Jul 30 06:12:08 PM PDT 24
Peak memory 183512 kb
Host smart-604ef3c4-6631-4888-a9de-86dd7b1997b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260708437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.3260708437
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.2050514495
Short name T147
Test name
Test status
Simulation time 223551096331 ps
CPU time 199.16 seconds
Started Jul 30 06:11:43 PM PDT 24
Finished Jul 30 06:15:02 PM PDT 24
Peak memory 191700 kb
Host smart-be6c006b-414a-4b48-9b36-aeb28a205770
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050514495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.2050514495
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.3462912885
Short name T45
Test name
Test status
Simulation time 56946050175 ps
CPU time 65.98 seconds
Started Jul 30 06:11:35 PM PDT 24
Finished Jul 30 06:12:41 PM PDT 24
Peak memory 183464 kb
Host smart-d6698f4c-5c08-4cbc-bf04-916b9affe3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462912885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.3462912885
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.3815668056
Short name T6
Test name
Test status
Simulation time 428638592406 ps
CPU time 110.16 seconds
Started Jul 30 06:11:37 PM PDT 24
Finished Jul 30 06:13:27 PM PDT 24
Peak memory 183448 kb
Host smart-6805131f-af6d-4402-9426-df0eb7eccc86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815668056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.3815668056
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.2250318258
Short name T415
Test name
Test status
Simulation time 285621208547 ps
CPU time 118.05 seconds
Started Jul 30 06:11:39 PM PDT 24
Finished Jul 30 06:13:37 PM PDT 24
Peak memory 183428 kb
Host smart-cf275f48-b35d-40d1-9431-7f606a5dd8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250318258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.2250318258
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.2956569257
Short name T406
Test name
Test status
Simulation time 199730333518 ps
CPU time 408.05 seconds
Started Jul 30 06:11:37 PM PDT 24
Finished Jul 30 06:18:25 PM PDT 24
Peak memory 193756 kb
Host smart-7765cace-4860-46bb-a766-6da3a3bd9b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956569257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.2956569257
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.81856851
Short name T407
Test name
Test status
Simulation time 73763534532 ps
CPU time 118.38 seconds
Started Jul 30 06:11:40 PM PDT 24
Finished Jul 30 06:13:39 PM PDT 24
Peak memory 195368 kb
Host smart-b1366337-9d51-4aec-9934-eff1c7549321
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81856851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all.81856851
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all_with_rand_reset.424346091
Short name T421
Test name
Test status
Simulation time 95772537589 ps
CPU time 212.81 seconds
Started Jul 30 06:11:40 PM PDT 24
Finished Jul 30 06:15:13 PM PDT 24
Peak memory 198116 kb
Host smart-43d4ca7c-ea68-48cf-8706-e91c8c5b26d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424346091 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all_with_rand_reset.424346091
Directory /workspace/38.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.388627146
Short name T359
Test name
Test status
Simulation time 96001136057 ps
CPU time 142.73 seconds
Started Jul 30 06:11:40 PM PDT 24
Finished Jul 30 06:14:03 PM PDT 24
Peak memory 183168 kb
Host smart-7325a0b8-f29f-45b4-bb4f-40b011163c38
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388627146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.rv_timer_cfg_update_on_fly.388627146
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_random.1758562314
Short name T205
Test name
Test status
Simulation time 427117713949 ps
CPU time 276.03 seconds
Started Jul 30 06:11:42 PM PDT 24
Finished Jul 30 06:16:18 PM PDT 24
Peak memory 191616 kb
Host smart-b8a980f3-a714-419a-854a-920bdcf70f61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758562314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.1758562314
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.3578180965
Short name T417
Test name
Test status
Simulation time 43089252 ps
CPU time 0.53 seconds
Started Jul 30 06:11:36 PM PDT 24
Finished Jul 30 06:11:36 PM PDT 24
Peak memory 183216 kb
Host smart-3d4a2d3a-cc79-498c-a0d4-922571d98109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578180965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.3578180965
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.799178126
Short name T452
Test name
Test status
Simulation time 21640668 ps
CPU time 0.56 seconds
Started Jul 30 06:11:43 PM PDT 24
Finished Jul 30 06:11:43 PM PDT 24
Peak memory 183148 kb
Host smart-14b32a1a-bfe6-478e-a819-21f9017bceff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799178126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all.
799178126
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all_with_rand_reset.576182348
Short name T454
Test name
Test status
Simulation time 76665688687 ps
CPU time 773.82 seconds
Started Jul 30 06:11:36 PM PDT 24
Finished Jul 30 06:24:30 PM PDT 24
Peak memory 209888 kb
Host smart-4c32608b-2d6e-48a8-9d4b-25d7e5acf639
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576182348 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all_with_rand_reset.576182348
Directory /workspace/39.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.1023298581
Short name T280
Test name
Test status
Simulation time 99636070201 ps
CPU time 57.06 seconds
Started Jul 30 06:11:07 PM PDT 24
Finished Jul 30 06:12:04 PM PDT 24
Peak memory 183460 kb
Host smart-fbfb4800-2b83-4845-b383-6605555dd7a5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023298581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.1023298581
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.3389936196
Short name T436
Test name
Test status
Simulation time 78199080540 ps
CPU time 27.77 seconds
Started Jul 30 06:11:40 PM PDT 24
Finished Jul 30 06:12:08 PM PDT 24
Peak memory 183424 kb
Host smart-b8e4beff-c87d-4e87-9561-731ee85b2246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389936196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.3389936196
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.3252789295
Short name T281
Test name
Test status
Simulation time 1002910634348 ps
CPU time 525.86 seconds
Started Jul 30 06:11:06 PM PDT 24
Finished Jul 30 06:19:52 PM PDT 24
Peak memory 191652 kb
Host smart-069d7a5f-3b0f-4d44-bd08-98b29985e276
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252789295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.3252789295
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.3211797354
Short name T405
Test name
Test status
Simulation time 43982073475 ps
CPU time 42.05 seconds
Started Jul 30 06:11:30 PM PDT 24
Finished Jul 30 06:12:12 PM PDT 24
Peak memory 194464 kb
Host smart-e58b7cd0-c5ed-46e6-8a27-5f3f030574eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211797354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.3211797354
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.433200741
Short name T17
Test name
Test status
Simulation time 210919791 ps
CPU time 0.82 seconds
Started Jul 30 06:11:15 PM PDT 24
Finished Jul 30 06:11:16 PM PDT 24
Peak memory 214564 kb
Host smart-38108f60-cd52-42b6-b507-38cfe943ef92
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433200741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.433200741
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.1533477630
Short name T316
Test name
Test status
Simulation time 194889506215 ps
CPU time 342.16 seconds
Started Jul 30 06:11:40 PM PDT 24
Finished Jul 30 06:17:22 PM PDT 24
Peak memory 183444 kb
Host smart-4278fc65-3f43-4266-b49c-e0d4ad75d482
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533477630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.1533477630
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.2715300639
Short name T63
Test name
Test status
Simulation time 184400550159 ps
CPU time 276.27 seconds
Started Jul 30 06:11:38 PM PDT 24
Finished Jul 30 06:16:14 PM PDT 24
Peak memory 183444 kb
Host smart-1a06e43e-c2ab-4b51-9c10-e490d48d4ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715300639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.2715300639
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.2350209748
Short name T136
Test name
Test status
Simulation time 5551656932 ps
CPU time 3.55 seconds
Started Jul 30 06:11:36 PM PDT 24
Finished Jul 30 06:11:40 PM PDT 24
Peak memory 191652 kb
Host smart-ba9716ba-78aa-4251-8b99-669992437c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350209748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.2350209748
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.3238789645
Short name T422
Test name
Test status
Simulation time 261240042866 ps
CPU time 389.13 seconds
Started Jul 30 06:11:43 PM PDT 24
Finished Jul 30 06:18:12 PM PDT 24
Peak memory 183444 kb
Host smart-46c3d671-c4bd-44a0-92ca-1c1b7636c312
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238789645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.3238789645
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.722995569
Short name T368
Test name
Test status
Simulation time 73616504916 ps
CPU time 104.24 seconds
Started Jul 30 06:11:41 PM PDT 24
Finished Jul 30 06:13:26 PM PDT 24
Peak memory 183452 kb
Host smart-38e133e1-2354-4828-9c1f-6dc3e314daf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722995569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.722995569
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.4189377637
Short name T1
Test name
Test status
Simulation time 128890970706 ps
CPU time 54.12 seconds
Started Jul 30 06:11:37 PM PDT 24
Finished Jul 30 06:12:32 PM PDT 24
Peak memory 183444 kb
Host smart-9f08e99a-2e61-4bf3-9d26-8bc413fabfcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189377637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.4189377637
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.3199746574
Short name T363
Test name
Test status
Simulation time 25228235271 ps
CPU time 57.78 seconds
Started Jul 30 06:11:37 PM PDT 24
Finished Jul 30 06:12:35 PM PDT 24
Peak memory 195000 kb
Host smart-889d5821-3080-40b6-90ab-0f562c8b114f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199746574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.3199746574
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.1430092418
Short name T104
Test name
Test status
Simulation time 173555619472 ps
CPU time 340.58 seconds
Started Jul 30 06:11:41 PM PDT 24
Finished Jul 30 06:17:21 PM PDT 24
Peak memory 196236 kb
Host smart-13340c47-078a-4cd3-8805-40889ddefcd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430092418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.1430092418
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all_with_rand_reset.1582976620
Short name T50
Test name
Test status
Simulation time 53985254661 ps
CPU time 371.79 seconds
Started Jul 30 06:11:32 PM PDT 24
Finished Jul 30 06:17:44 PM PDT 24
Peak memory 198016 kb
Host smart-f8f764e9-a155-487b-a246-8c4a2494d159
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582976620 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all_with_rand_reset.1582976620
Directory /workspace/41.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.429985599
Short name T177
Test name
Test status
Simulation time 196490945297 ps
CPU time 303.92 seconds
Started Jul 30 06:11:40 PM PDT 24
Finished Jul 30 06:16:44 PM PDT 24
Peak memory 183416 kb
Host smart-a5f514c3-dc77-4c94-8af6-5a0bfbd69b96
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429985599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.rv_timer_cfg_update_on_fly.429985599
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.3447686399
Short name T437
Test name
Test status
Simulation time 59260132235 ps
CPU time 93.45 seconds
Started Jul 30 06:11:30 PM PDT 24
Finished Jul 30 06:13:04 PM PDT 24
Peak memory 183424 kb
Host smart-938d0071-41f4-4596-b2b6-fc66c61ff286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447686399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.3447686399
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.4061103608
Short name T181
Test name
Test status
Simulation time 48523850418 ps
CPU time 21.79 seconds
Started Jul 30 06:11:40 PM PDT 24
Finished Jul 30 06:12:02 PM PDT 24
Peak memory 183456 kb
Host smart-8d676695-3722-4f76-9027-d27b6f939bc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061103608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.4061103608
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.4028989295
Short name T58
Test name
Test status
Simulation time 72284677240 ps
CPU time 103.87 seconds
Started Jul 30 06:11:37 PM PDT 24
Finished Jul 30 06:13:21 PM PDT 24
Peak memory 191644 kb
Host smart-e224b082-eb13-4617-8cf0-6fa3181ab831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028989295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.4028989295
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.533102095
Short name T242
Test name
Test status
Simulation time 4128445822994 ps
CPU time 1487.43 seconds
Started Jul 30 06:11:40 PM PDT 24
Finished Jul 30 06:36:28 PM PDT 24
Peak memory 191672 kb
Host smart-ee27b3f6-c097-47d5-aa1d-661bdd17652a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533102095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all.
533102095
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.2486963430
Short name T146
Test name
Test status
Simulation time 19277396689 ps
CPU time 27.65 seconds
Started Jul 30 06:11:40 PM PDT 24
Finished Jul 30 06:12:08 PM PDT 24
Peak memory 183388 kb
Host smart-e98a6d15-d67b-471f-ac0d-1f01e78fb11f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486963430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.2486963430
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.1559995232
Short name T374
Test name
Test status
Simulation time 391956321290 ps
CPU time 164.67 seconds
Started Jul 30 06:11:36 PM PDT 24
Finished Jul 30 06:14:20 PM PDT 24
Peak memory 183452 kb
Host smart-b76d96bf-be1b-4c8b-b1e6-dee2144c071c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559995232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.1559995232
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.159003526
Short name T259
Test name
Test status
Simulation time 16304044093 ps
CPU time 34.25 seconds
Started Jul 30 06:11:41 PM PDT 24
Finished Jul 30 06:12:15 PM PDT 24
Peak memory 183496 kb
Host smart-a27c991a-05d7-4c9c-981d-2fe3739919b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159003526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.159003526
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.1099826441
Short name T401
Test name
Test status
Simulation time 340451581160 ps
CPU time 150.08 seconds
Started Jul 30 06:11:36 PM PDT 24
Finished Jul 30 06:14:06 PM PDT 24
Peak memory 183468 kb
Host smart-18f7b63c-2508-40a5-8d69-c70c03a29291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099826441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.1099826441
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.3665997286
Short name T210
Test name
Test status
Simulation time 567970352156 ps
CPU time 505.02 seconds
Started Jul 30 06:11:46 PM PDT 24
Finished Jul 30 06:20:11 PM PDT 24
Peak memory 183444 kb
Host smart-6078e129-672c-4b75-8893-35a7b37b5c37
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665997286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.3665997286
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.87581613
Short name T380
Test name
Test status
Simulation time 130906446711 ps
CPU time 172.61 seconds
Started Jul 30 06:11:37 PM PDT 24
Finished Jul 30 06:14:30 PM PDT 24
Peak memory 183440 kb
Host smart-681a4f21-a2b9-4bfe-9918-06c9bb37fc84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87581613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.87581613
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.1985068364
Short name T202
Test name
Test status
Simulation time 446164807058 ps
CPU time 230.85 seconds
Started Jul 30 06:11:37 PM PDT 24
Finished Jul 30 06:15:28 PM PDT 24
Peak memory 191696 kb
Host smart-5f73c18f-de55-42d7-bd7c-908c365dd078
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985068364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.1985068364
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.2061903852
Short name T370
Test name
Test status
Simulation time 43989011 ps
CPU time 0.57 seconds
Started Jul 30 06:11:39 PM PDT 24
Finished Jul 30 06:11:40 PM PDT 24
Peak memory 183260 kb
Host smart-8920fb68-7ed1-4efe-b4e4-d99f80e8a121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061903852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.2061903852
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.1171616179
Short name T36
Test name
Test status
Simulation time 65574698112 ps
CPU time 511.56 seconds
Started Jul 30 06:11:39 PM PDT 24
Finished Jul 30 06:20:11 PM PDT 24
Peak memory 206388 kb
Host smart-70a7d1a8-c317-47f2-9c39-25ab0dba41d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171616179 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.1171616179
Directory /workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.2541261174
Short name T357
Test name
Test status
Simulation time 499057191848 ps
CPU time 267.73 seconds
Started Jul 30 06:11:48 PM PDT 24
Finished Jul 30 06:16:16 PM PDT 24
Peak memory 183428 kb
Host smart-2f46e676-c3e3-4220-87ba-cb46182184b2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541261174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.2541261174
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.238870889
Short name T430
Test name
Test status
Simulation time 596818872219 ps
CPU time 231.58 seconds
Started Jul 30 06:11:33 PM PDT 24
Finished Jul 30 06:15:25 PM PDT 24
Peak memory 183448 kb
Host smart-86cb01e6-4fdf-4b1e-813b-08533ac9911e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238870889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.238870889
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.1184760203
Short name T293
Test name
Test status
Simulation time 70724797056 ps
CPU time 273.68 seconds
Started Jul 30 06:11:41 PM PDT 24
Finished Jul 30 06:16:14 PM PDT 24
Peak memory 191656 kb
Host smart-2b3373d8-26f8-43fd-be59-6bb409b51f56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184760203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.1184760203
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.2055720832
Short name T51
Test name
Test status
Simulation time 70521257837 ps
CPU time 435.6 seconds
Started Jul 30 06:11:39 PM PDT 24
Finished Jul 30 06:18:55 PM PDT 24
Peak memory 206356 kb
Host smart-1950ce7c-d04a-4855-822e-46dc27609966
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055720832 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all_with_rand_reset.2055720832
Directory /workspace/45.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.3419627706
Short name T57
Test name
Test status
Simulation time 1853244401500 ps
CPU time 909.62 seconds
Started Jul 30 06:11:50 PM PDT 24
Finished Jul 30 06:27:00 PM PDT 24
Peak memory 183448 kb
Host smart-21bc88f4-908f-4934-8cf4-d8cc4e961d30
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419627706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.3419627706
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.2604275926
Short name T386
Test name
Test status
Simulation time 201831848974 ps
CPU time 280.78 seconds
Started Jul 30 06:11:37 PM PDT 24
Finished Jul 30 06:16:18 PM PDT 24
Peak memory 183388 kb
Host smart-93385b3a-f167-400a-bb54-e01c309e5091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604275926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.2604275926
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.3401604233
Short name T49
Test name
Test status
Simulation time 97423612435 ps
CPU time 85.94 seconds
Started Jul 30 06:11:44 PM PDT 24
Finished Jul 30 06:13:10 PM PDT 24
Peak memory 191628 kb
Host smart-5103b1b2-4e95-46f2-b16c-d51d0051a73f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401604233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.3401604233
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.1109468401
Short name T209
Test name
Test status
Simulation time 3061793120 ps
CPU time 2.94 seconds
Started Jul 30 06:11:45 PM PDT 24
Finished Jul 30 06:11:48 PM PDT 24
Peak memory 183480 kb
Host smart-31c72950-cbba-4f9b-ae7c-1dad784ca2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109468401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.1109468401
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.729936002
Short name T383
Test name
Test status
Simulation time 254047358064 ps
CPU time 376.38 seconds
Started Jul 30 06:11:37 PM PDT 24
Finished Jul 30 06:17:53 PM PDT 24
Peak memory 191720 kb
Host smart-730b3507-9248-4190-bc39-5839e842a2a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729936002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all.
729936002
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.338809155
Short name T74
Test name
Test status
Simulation time 340371168628 ps
CPU time 579.69 seconds
Started Jul 30 06:11:34 PM PDT 24
Finished Jul 30 06:21:14 PM PDT 24
Peak memory 183432 kb
Host smart-f6570c4c-1300-42f5-9bd3-e77ade0fd4a2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338809155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.rv_timer_cfg_update_on_fly.338809155
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.1223706720
Short name T408
Test name
Test status
Simulation time 98995086414 ps
CPU time 26.85 seconds
Started Jul 30 06:11:46 PM PDT 24
Finished Jul 30 06:12:13 PM PDT 24
Peak memory 183476 kb
Host smart-0beb8663-4912-440e-982d-68050ffb4d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223706720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.1223706720
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.4196319822
Short name T120
Test name
Test status
Simulation time 454958726673 ps
CPU time 635.46 seconds
Started Jul 30 06:11:42 PM PDT 24
Finished Jul 30 06:22:18 PM PDT 24
Peak memory 191676 kb
Host smart-0a091e52-4f82-460d-a1b3-99afc5bd4867
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196319822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.4196319822
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.1882253922
Short name T387
Test name
Test status
Simulation time 175651006 ps
CPU time 0.7 seconds
Started Jul 30 06:11:34 PM PDT 24
Finished Jul 30 06:11:35 PM PDT 24
Peak memory 191912 kb
Host smart-77edd1d3-eedb-4ebe-899c-903b95b34c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882253922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.1882253922
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all_with_rand_reset.1685639886
Short name T41
Test name
Test status
Simulation time 63234045382 ps
CPU time 140.62 seconds
Started Jul 30 06:11:40 PM PDT 24
Finished Jul 30 06:14:01 PM PDT 24
Peak memory 198184 kb
Host smart-b4be51c0-bdfc-46d7-a3bc-cce65e51ed12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685639886 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all_with_rand_reset.1685639886
Directory /workspace/47.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.2229522425
Short name T149
Test name
Test status
Simulation time 3968290198158 ps
CPU time 1266.86 seconds
Started Jul 30 06:11:37 PM PDT 24
Finished Jul 30 06:32:44 PM PDT 24
Peak memory 183448 kb
Host smart-269667d6-5462-46dd-87a6-22b5862bcb35
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229522425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.2229522425
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.2501075074
Short name T403
Test name
Test status
Simulation time 169498725459 ps
CPU time 212.28 seconds
Started Jul 30 06:11:44 PM PDT 24
Finished Jul 30 06:15:16 PM PDT 24
Peak memory 183452 kb
Host smart-ebc3201f-f2d7-4a7a-969f-64b8f5c7409a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501075074 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.2501075074
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.1647939001
Short name T160
Test name
Test status
Simulation time 135671828528 ps
CPU time 1692.5 seconds
Started Jul 30 06:11:34 PM PDT 24
Finished Jul 30 06:39:47 PM PDT 24
Peak memory 191676 kb
Host smart-4d142865-ef15-4643-af41-35429e2153f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647939001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.1647939001
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.3670982047
Short name T331
Test name
Test status
Simulation time 556701228296 ps
CPU time 375.17 seconds
Started Jul 30 06:11:40 PM PDT 24
Finished Jul 30 06:17:55 PM PDT 24
Peak memory 191632 kb
Host smart-a33f029f-a5ad-4a01-99f2-75931fd4f5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670982047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.3670982047
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.1245697709
Short name T299
Test name
Test status
Simulation time 19949414096 ps
CPU time 11.01 seconds
Started Jul 30 06:11:40 PM PDT 24
Finished Jul 30 06:11:51 PM PDT 24
Peak memory 183460 kb
Host smart-386c1607-aa20-4e84-a7f1-9bdeb8a23af3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245697709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.1245697709
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.1929794873
Short name T4
Test name
Test status
Simulation time 24592178595 ps
CPU time 39.68 seconds
Started Jul 30 06:11:43 PM PDT 24
Finished Jul 30 06:12:23 PM PDT 24
Peak memory 183504 kb
Host smart-fa8eb176-1355-4191-8b07-c65ba725a703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929794873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.1929794873
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.3822438943
Short name T419
Test name
Test status
Simulation time 30230522513 ps
CPU time 30.91 seconds
Started Jul 30 06:11:40 PM PDT 24
Finished Jul 30 06:12:11 PM PDT 24
Peak memory 183504 kb
Host smart-609f04f3-11bd-436c-8422-b2d23683afb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822438943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.3822438943
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.1016999647
Short name T318
Test name
Test status
Simulation time 42639316791 ps
CPU time 71.82 seconds
Started Jul 30 06:11:45 PM PDT 24
Finished Jul 30 06:12:56 PM PDT 24
Peak memory 191664 kb
Host smart-e71fbb7e-7126-4d00-bceb-a0ee1624c13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016999647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.1016999647
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.1879391764
Short name T376
Test name
Test status
Simulation time 2910828321 ps
CPU time 4.84 seconds
Started Jul 30 06:11:47 PM PDT 24
Finished Jul 30 06:11:52 PM PDT 24
Peak memory 192528 kb
Host smart-04941228-ea14-4fa2-9509-f7e09a80a4ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879391764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.1879391764
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.2626767785
Short name T140
Test name
Test status
Simulation time 326460344820 ps
CPU time 146.82 seconds
Started Jul 30 06:11:18 PM PDT 24
Finished Jul 30 06:13:45 PM PDT 24
Peak memory 183436 kb
Host smart-09d04551-3d97-4d2d-b7c0-eb839bc08139
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626767785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.2626767785
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.2276018331
Short name T393
Test name
Test status
Simulation time 104110366524 ps
CPU time 114.44 seconds
Started Jul 30 06:11:13 PM PDT 24
Finished Jul 30 06:13:08 PM PDT 24
Peak memory 183616 kb
Host smart-84b93fea-0bb8-47a9-9469-ca4b525fdb63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276018331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.2276018331
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.2981100912
Short name T254
Test name
Test status
Simulation time 447084077523 ps
CPU time 2006.56 seconds
Started Jul 30 06:11:26 PM PDT 24
Finished Jul 30 06:44:53 PM PDT 24
Peak memory 191556 kb
Host smart-18ad2836-bbca-4faf-9dcf-5c78040bfc32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981100912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.2981100912
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.2107119225
Short name T61
Test name
Test status
Simulation time 51327053720 ps
CPU time 426.47 seconds
Started Jul 30 06:11:40 PM PDT 24
Finished Jul 30 06:18:46 PM PDT 24
Peak memory 183424 kb
Host smart-fcb8d9d5-901a-467c-8071-34ab419f4d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107119225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.2107119225
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.2301909701
Short name T70
Test name
Test status
Simulation time 276740618124 ps
CPU time 589.58 seconds
Started Jul 30 06:11:12 PM PDT 24
Finished Jul 30 06:21:02 PM PDT 24
Peak memory 195588 kb
Host smart-cad1c2bf-5691-4e9c-a42a-7de8bf4e0f3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301909701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
2301909701
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/50.rv_timer_random.190425196
Short name T219
Test name
Test status
Simulation time 79381484236 ps
CPU time 47.06 seconds
Started Jul 30 06:11:44 PM PDT 24
Finished Jul 30 06:12:31 PM PDT 24
Peak memory 183452 kb
Host smart-129a7c2b-4c2d-423f-9639-464ba157d123
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190425196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.190425196
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.1309664243
Short name T330
Test name
Test status
Simulation time 73637174716 ps
CPU time 74.1 seconds
Started Jul 30 06:11:46 PM PDT 24
Finished Jul 30 06:13:00 PM PDT 24
Peak memory 191648 kb
Host smart-1da3454c-04e4-46c6-adec-768d3de6bdd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309664243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.1309664243
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.629410205
Short name T444
Test name
Test status
Simulation time 15000338854 ps
CPU time 4.98 seconds
Started Jul 30 06:11:47 PM PDT 24
Finished Jul 30 06:11:52 PM PDT 24
Peak memory 183436 kb
Host smart-976cd689-70a9-4763-8b87-9836e2367fcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629410205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.629410205
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.989191395
Short name T306
Test name
Test status
Simulation time 43964214275 ps
CPU time 74.71 seconds
Started Jul 30 06:11:56 PM PDT 24
Finished Jul 30 06:13:11 PM PDT 24
Peak memory 191688 kb
Host smart-8e193bea-84f5-4c55-923c-cc682a7868d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989191395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.989191395
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.3404703132
Short name T256
Test name
Test status
Simulation time 269069702811 ps
CPU time 169.94 seconds
Started Jul 30 06:11:55 PM PDT 24
Finished Jul 30 06:14:45 PM PDT 24
Peak memory 191696 kb
Host smart-92e9c879-fecd-4148-894d-b97449de256a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404703132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.3404703132
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.461780842
Short name T123
Test name
Test status
Simulation time 365851166107 ps
CPU time 92.8 seconds
Started Jul 30 06:11:48 PM PDT 24
Finished Jul 30 06:13:21 PM PDT 24
Peak memory 191672 kb
Host smart-bc76ba4a-3372-4a36-bf95-24f883ea05f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461780842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.461780842
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.3912915826
Short name T261
Test name
Test status
Simulation time 216789290416 ps
CPU time 387.51 seconds
Started Jul 30 06:11:55 PM PDT 24
Finished Jul 30 06:18:23 PM PDT 24
Peak memory 191612 kb
Host smart-25b771f7-7688-4484-aba5-ebc7e6536bc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912915826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.3912915826
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.1942734201
Short name T56
Test name
Test status
Simulation time 86392365754 ps
CPU time 133.93 seconds
Started Jul 30 06:11:55 PM PDT 24
Finished Jul 30 06:14:09 PM PDT 24
Peak memory 191704 kb
Host smart-6657814e-0001-4375-8e1c-f3622496f5eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942734201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.1942734201
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.738018789
Short name T204
Test name
Test status
Simulation time 299177594661 ps
CPU time 132.57 seconds
Started Jul 30 06:11:54 PM PDT 24
Finished Jul 30 06:14:06 PM PDT 24
Peak memory 194432 kb
Host smart-94324d44-bb96-4c8d-b7e5-b34086adf09a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738018789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.738018789
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.2036389241
Short name T448
Test name
Test status
Simulation time 252801230661 ps
CPU time 394.19 seconds
Started Jul 30 06:11:24 PM PDT 24
Finished Jul 30 06:17:58 PM PDT 24
Peak memory 183424 kb
Host smart-08502e74-c150-4acb-91db-e77dcdc0d3fd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036389241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.2036389241
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.1063158905
Short name T394
Test name
Test status
Simulation time 167037204631 ps
CPU time 127.15 seconds
Started Jul 30 06:11:09 PM PDT 24
Finished Jul 30 06:13:16 PM PDT 24
Peak memory 183444 kb
Host smart-421e68f2-2272-4362-9248-76896913aa21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063158905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.1063158905
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.46986075
Short name T172
Test name
Test status
Simulation time 214990071429 ps
CPU time 414.08 seconds
Started Jul 30 06:11:10 PM PDT 24
Finished Jul 30 06:18:04 PM PDT 24
Peak memory 191700 kb
Host smart-e0abca6b-754a-4d52-acec-6f5430f7655d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46986075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.46986075
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.403487661
Short name T308
Test name
Test status
Simulation time 75972141819 ps
CPU time 33.98 seconds
Started Jul 30 06:11:25 PM PDT 24
Finished Jul 30 06:11:59 PM PDT 24
Peak memory 194132 kb
Host smart-65afc2bb-e696-43c4-bf8e-704c983b1f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403487661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.403487661
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.2704749521
Short name T273
Test name
Test status
Simulation time 102939412073 ps
CPU time 130.45 seconds
Started Jul 30 06:11:29 PM PDT 24
Finished Jul 30 06:13:39 PM PDT 24
Peak memory 195528 kb
Host smart-864075b0-a40a-4927-9370-5063529e1c24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704749521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
2704749521
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/62.rv_timer_random.3137294638
Short name T245
Test name
Test status
Simulation time 218365167070 ps
CPU time 959.4 seconds
Started Jul 30 06:11:59 PM PDT 24
Finished Jul 30 06:27:59 PM PDT 24
Peak memory 183488 kb
Host smart-def91f58-b033-41ba-a847-858ccf751192
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137294638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.3137294638
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.700770411
Short name T307
Test name
Test status
Simulation time 270291263874 ps
CPU time 1282.66 seconds
Started Jul 30 06:11:56 PM PDT 24
Finished Jul 30 06:33:19 PM PDT 24
Peak memory 191584 kb
Host smart-25e0ccc0-919a-45bf-af63-e454b35fbc11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700770411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.700770411
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.1046312977
Short name T153
Test name
Test status
Simulation time 383746947595 ps
CPU time 415.86 seconds
Started Jul 30 06:11:56 PM PDT 24
Finished Jul 30 06:18:52 PM PDT 24
Peak memory 191676 kb
Host smart-2457217b-fac7-4a4c-b440-eeeff2e0e8f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046312977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.1046312977
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.3382614465
Short name T286
Test name
Test status
Simulation time 457577304519 ps
CPU time 332.26 seconds
Started Jul 30 06:11:57 PM PDT 24
Finished Jul 30 06:17:29 PM PDT 24
Peak memory 191620 kb
Host smart-5df7b529-2cae-4e73-a79a-23067995e263
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382614465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.3382614465
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.1650639769
Short name T346
Test name
Test status
Simulation time 111793368301 ps
CPU time 498.76 seconds
Started Jul 30 06:12:02 PM PDT 24
Finished Jul 30 06:20:21 PM PDT 24
Peak memory 191672 kb
Host smart-9941d55a-c59b-45d0-9b4b-8081599b00bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650639769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.1650639769
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.3442571866
Short name T355
Test name
Test status
Simulation time 94127360168 ps
CPU time 45.12 seconds
Started Jul 30 06:12:02 PM PDT 24
Finished Jul 30 06:12:47 PM PDT 24
Peak memory 183500 kb
Host smart-da725fc2-b66e-4930-8e32-ad9f5514e874
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442571866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.3442571866
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.229238078
Short name T258
Test name
Test status
Simulation time 114100209445 ps
CPU time 163.88 seconds
Started Jul 30 06:11:09 PM PDT 24
Finished Jul 30 06:13:53 PM PDT 24
Peak memory 183428 kb
Host smart-ca4df568-a2c8-447b-8c8b-53e5a1a9bb73
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229238078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.rv_timer_cfg_update_on_fly.229238078
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.3093286230
Short name T392
Test name
Test status
Simulation time 81836962154 ps
CPU time 14.18 seconds
Started Jul 30 06:11:07 PM PDT 24
Finished Jul 30 06:11:22 PM PDT 24
Peak memory 183484 kb
Host smart-49f6d86d-d769-42e6-b66b-056d415fc918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093286230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.3093286230
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.1835666131
Short name T180
Test name
Test status
Simulation time 121427448834 ps
CPU time 36.05 seconds
Started Jul 30 06:11:10 PM PDT 24
Finished Jul 30 06:11:46 PM PDT 24
Peak memory 191696 kb
Host smart-3e650b29-42ed-4a81-bb8f-4ea6d19f80e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835666131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.1835666131
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.3569020002
Short name T409
Test name
Test status
Simulation time 563371923 ps
CPU time 0.68 seconds
Started Jul 30 06:11:17 PM PDT 24
Finished Jul 30 06:11:18 PM PDT 24
Peak memory 183204 kb
Host smart-fb461705-e51d-463d-abf7-cc1e252f1999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569020002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.3569020002
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.2939778817
Short name T158
Test name
Test status
Simulation time 16101074629 ps
CPU time 26.16 seconds
Started Jul 30 06:12:01 PM PDT 24
Finished Jul 30 06:12:27 PM PDT 24
Peak memory 191664 kb
Host smart-c636fa3c-1d64-49eb-803d-c4091a41f8ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939778817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.2939778817
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.272045635
Short name T190
Test name
Test status
Simulation time 427276282513 ps
CPU time 429.62 seconds
Started Jul 30 06:12:07 PM PDT 24
Finished Jul 30 06:19:17 PM PDT 24
Peak memory 191672 kb
Host smart-f7f79420-a4c4-454e-bb44-9a078a5f39a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272045635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.272045635
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.1148306085
Short name T212
Test name
Test status
Simulation time 137244686294 ps
CPU time 482.18 seconds
Started Jul 30 06:12:07 PM PDT 24
Finished Jul 30 06:20:09 PM PDT 24
Peak memory 191684 kb
Host smart-a28ce2a0-c7dd-4643-97f5-556cb99bfc59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148306085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.1148306085
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.1189663445
Short name T128
Test name
Test status
Simulation time 298177929552 ps
CPU time 397.48 seconds
Started Jul 30 06:12:08 PM PDT 24
Finished Jul 30 06:18:45 PM PDT 24
Peak memory 191696 kb
Host smart-b17db160-ea9f-4d2e-8cc9-d0b0e60f7d83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189663445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.1189663445
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.3387867065
Short name T48
Test name
Test status
Simulation time 20204379157 ps
CPU time 3.36 seconds
Started Jul 30 06:12:06 PM PDT 24
Finished Jul 30 06:12:10 PM PDT 24
Peak memory 183316 kb
Host smart-4cc12e38-83a6-43c1-95e6-7dd7d57afff8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387867065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.3387867065
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.2920912378
Short name T211
Test name
Test status
Simulation time 155692435098 ps
CPU time 250.87 seconds
Started Jul 30 06:12:06 PM PDT 24
Finished Jul 30 06:16:17 PM PDT 24
Peak memory 191660 kb
Host smart-1f298af2-4b2c-438c-8e3e-9b54ef5ddec3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920912378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.2920912378
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.2750581467
Short name T225
Test name
Test status
Simulation time 152566716003 ps
CPU time 166.94 seconds
Started Jul 30 06:12:06 PM PDT 24
Finished Jul 30 06:14:53 PM PDT 24
Peak memory 191688 kb
Host smart-643f211b-8359-47db-b090-0a6c4360d123
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750581467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.2750581467
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.3116427946
Short name T337
Test name
Test status
Simulation time 8194633159 ps
CPU time 15.25 seconds
Started Jul 30 06:11:27 PM PDT 24
Finished Jul 30 06:11:42 PM PDT 24
Peak memory 183436 kb
Host smart-a71c018d-8003-40c0-a1bf-7ce7d876f003
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116427946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.3116427946
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.3276395815
Short name T398
Test name
Test status
Simulation time 456136454406 ps
CPU time 176 seconds
Started Jul 30 06:11:15 PM PDT 24
Finished Jul 30 06:14:11 PM PDT 24
Peak memory 183464 kb
Host smart-c8d135ec-8de3-41bd-85e4-c093ae760a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276395815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.3276395815
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.1059255121
Short name T289
Test name
Test status
Simulation time 272870134531 ps
CPU time 328.71 seconds
Started Jul 30 06:11:24 PM PDT 24
Finished Jul 30 06:16:52 PM PDT 24
Peak memory 191676 kb
Host smart-1c7389be-6122-4aed-b7e5-8ae358b01d4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059255121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.1059255121
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.177522371
Short name T297
Test name
Test status
Simulation time 33422825778 ps
CPU time 50.74 seconds
Started Jul 30 06:11:17 PM PDT 24
Finished Jul 30 06:12:07 PM PDT 24
Peak memory 191656 kb
Host smart-d332003d-64c2-4fd6-9c24-ce08d892f38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177522371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.177522371
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.1594210561
Short name T272
Test name
Test status
Simulation time 243329245841 ps
CPU time 333.07 seconds
Started Jul 30 06:11:12 PM PDT 24
Finished Jul 30 06:16:45 PM PDT 24
Peak memory 195536 kb
Host smart-1bf040fa-483d-4a04-b8cb-2400dd418237
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594210561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
1594210561
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/81.rv_timer_random.745902867
Short name T188
Test name
Test status
Simulation time 115183288247 ps
CPU time 3273.28 seconds
Started Jul 30 06:12:13 PM PDT 24
Finished Jul 30 07:06:47 PM PDT 24
Peak memory 194220 kb
Host smart-241bd5d5-2fd9-459a-8bcf-86ed756eb630
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745902867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.745902867
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.2201939855
Short name T22
Test name
Test status
Simulation time 563181225704 ps
CPU time 268.28 seconds
Started Jul 30 06:12:18 PM PDT 24
Finished Jul 30 06:16:46 PM PDT 24
Peak memory 195144 kb
Host smart-b96cfa60-93c0-4f99-ba29-daedecafe191
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201939855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.2201939855
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.611593437
Short name T112
Test name
Test status
Simulation time 1397106271575 ps
CPU time 683.85 seconds
Started Jul 30 06:12:16 PM PDT 24
Finished Jul 30 06:23:40 PM PDT 24
Peak memory 191668 kb
Host smart-9916a365-244b-4d57-8fbb-6419fc61da06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611593437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.611593437
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.1318283343
Short name T132
Test name
Test status
Simulation time 329324544835 ps
CPU time 163.37 seconds
Started Jul 30 06:12:15 PM PDT 24
Finished Jul 30 06:14:58 PM PDT 24
Peak memory 191652 kb
Host smart-6f9e20e8-8788-4ba2-b6cf-2b399629b348
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318283343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.1318283343
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.685306532
Short name T327
Test name
Test status
Simulation time 19088410527 ps
CPU time 25.61 seconds
Started Jul 30 06:12:17 PM PDT 24
Finished Jul 30 06:12:42 PM PDT 24
Peak memory 183268 kb
Host smart-9ac86ee2-6324-4fe3-bfed-23eba96d58b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685306532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.685306532
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.380163985
Short name T131
Test name
Test status
Simulation time 745338847075 ps
CPU time 275.35 seconds
Started Jul 30 06:12:19 PM PDT 24
Finished Jul 30 06:16:55 PM PDT 24
Peak memory 191600 kb
Host smart-f5c0df86-be92-4a7c-8a22-17f5d64131cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380163985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.380163985
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.933898843
Short name T264
Test name
Test status
Simulation time 303589032231 ps
CPU time 134.93 seconds
Started Jul 30 06:12:17 PM PDT 24
Finished Jul 30 06:14:32 PM PDT 24
Peak memory 191644 kb
Host smart-2dc71f58-9ecd-4a62-ad98-ac5e20e020f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933898843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.933898843
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.853198717
Short name T426
Test name
Test status
Simulation time 39961842297 ps
CPU time 67.86 seconds
Started Jul 30 06:12:19 PM PDT 24
Finished Jul 30 06:13:27 PM PDT 24
Peak memory 191696 kb
Host smart-407dbbdd-dc14-4feb-9589-1ccb0d6d8701
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853198717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.853198717
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.4223794404
Short name T244
Test name
Test status
Simulation time 381077776439 ps
CPU time 287.86 seconds
Started Jul 30 06:12:20 PM PDT 24
Finished Jul 30 06:17:08 PM PDT 24
Peak memory 191628 kb
Host smart-f6492bad-3f76-4f80-9c00-84ee219d5660
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223794404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.4223794404
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.2093688601
Short name T279
Test name
Test status
Simulation time 544534451415 ps
CPU time 490.77 seconds
Started Jul 30 06:11:10 PM PDT 24
Finished Jul 30 06:19:21 PM PDT 24
Peak memory 183380 kb
Host smart-80448e9a-25f5-4998-adca-d616a3479428
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093688601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.2093688601
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.1264696239
Short name T64
Test name
Test status
Simulation time 865202884454 ps
CPU time 260.46 seconds
Started Jul 30 06:11:16 PM PDT 24
Finished Jul 30 06:15:37 PM PDT 24
Peak memory 183504 kb
Host smart-d190df0e-7578-496e-8689-41a5c5b6f653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264696239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.1264696239
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.887343889
Short name T325
Test name
Test status
Simulation time 318542488981 ps
CPU time 167.04 seconds
Started Jul 30 06:11:07 PM PDT 24
Finished Jul 30 06:13:55 PM PDT 24
Peak memory 191576 kb
Host smart-4884313f-1b13-4545-8f14-96683f5cbe65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887343889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.887343889
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.2129744467
Short name T352
Test name
Test status
Simulation time 77331932093 ps
CPU time 102.48 seconds
Started Jul 30 06:11:35 PM PDT 24
Finished Jul 30 06:13:18 PM PDT 24
Peak memory 191684 kb
Host smart-7793113d-53d5-4d40-b0ad-18b415a2dd94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129744467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.2129744467
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all_with_rand_reset.3835453486
Short name T40
Test name
Test status
Simulation time 55357754177 ps
CPU time 496.87 seconds
Started Jul 30 06:11:16 PM PDT 24
Finished Jul 30 06:19:33 PM PDT 24
Peak memory 206384 kb
Host smart-e445c362-2d79-4a5e-8558-2b095138df90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835453486 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all_with_rand_reset.3835453486
Directory /workspace/9.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.306371667
Short name T23
Test name
Test status
Simulation time 143380441990 ps
CPU time 64.76 seconds
Started Jul 30 06:12:17 PM PDT 24
Finished Jul 30 06:13:22 PM PDT 24
Peak memory 183452 kb
Host smart-ef04c694-e8e8-4739-beda-06567057632f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306371667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.306371667
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.4192333153
Short name T241
Test name
Test status
Simulation time 330536202299 ps
CPU time 521.44 seconds
Started Jul 30 06:12:18 PM PDT 24
Finished Jul 30 06:21:00 PM PDT 24
Peak memory 191616 kb
Host smart-03dd7a05-9ff7-45de-9062-f4077dd1b145
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192333153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.4192333153
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.1987567312
Short name T152
Test name
Test status
Simulation time 2097614204989 ps
CPU time 407.27 seconds
Started Jul 30 06:12:25 PM PDT 24
Finished Jul 30 06:19:12 PM PDT 24
Peak memory 191148 kb
Host smart-b6a5d0af-6808-4e14-afba-ec17d636ff25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987567312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.1987567312
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.1671327742
Short name T442
Test name
Test status
Simulation time 56025859330 ps
CPU time 52.51 seconds
Started Jul 30 06:12:25 PM PDT 24
Finished Jul 30 06:13:17 PM PDT 24
Peak memory 182992 kb
Host smart-057ce8f1-c064-4371-9453-8029e65b0425
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671327742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.1671327742
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.2160915434
Short name T213
Test name
Test status
Simulation time 30158401062 ps
CPU time 35.45 seconds
Started Jul 30 06:12:23 PM PDT 24
Finished Jul 30 06:12:58 PM PDT 24
Peak memory 191600 kb
Host smart-f9c3e218-b365-41ca-a7de-851f9bd87b52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160915434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.2160915434
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.922911768
Short name T142
Test name
Test status
Simulation time 161820027561 ps
CPU time 738.53 seconds
Started Jul 30 06:12:25 PM PDT 24
Finished Jul 30 06:24:44 PM PDT 24
Peak memory 191592 kb
Host smart-152bbb61-4912-4794-bf6d-95ca26acdd5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922911768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.922911768
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.1372689263
Short name T196
Test name
Test status
Simulation time 102783990000 ps
CPU time 157.3 seconds
Started Jul 30 06:12:25 PM PDT 24
Finished Jul 30 06:15:03 PM PDT 24
Peak memory 191688 kb
Host smart-925b9712-4ba5-461d-be36-02a88d34cc5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372689263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.1372689263
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.1055546207
Short name T275
Test name
Test status
Simulation time 46581561602 ps
CPU time 72.19 seconds
Started Jul 30 06:12:26 PM PDT 24
Finished Jul 30 06:13:38 PM PDT 24
Peak memory 191688 kb
Host smart-a2144523-8fa4-4b0a-b495-57bd2013ab1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055546207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.1055546207
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.3139233105
Short name T334
Test name
Test status
Simulation time 115532891104 ps
CPU time 297.02 seconds
Started Jul 30 06:12:26 PM PDT 24
Finished Jul 30 06:17:23 PM PDT 24
Peak memory 191616 kb
Host smart-59b06ef3-9e8c-489b-afa6-08096e317855
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139233105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.3139233105
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.85049324
Short name T117
Test name
Test status
Simulation time 597168733160 ps
CPU time 498.41 seconds
Started Jul 30 06:12:27 PM PDT 24
Finished Jul 30 06:20:45 PM PDT 24
Peak memory 191644 kb
Host smart-d6c93a69-a901-41ba-bb68-0fd83cc4cacc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85049324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.85049324
Directory /workspace/99.rv_timer_random/latest
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