Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.62 99.36 98.73 100.00 100.00 100.00 99.66


Total test records in report: 577
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T507 /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.2035934833 Jul 31 04:44:56 PM PDT 24 Jul 31 04:44:56 PM PDT 24 14212056 ps
T508 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.2606491360 Jul 31 04:45:17 PM PDT 24 Jul 31 04:45:18 PM PDT 24 134546706 ps
T509 /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.2144756174 Jul 31 04:45:07 PM PDT 24 Jul 31 04:45:08 PM PDT 24 14922333 ps
T64 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.3944758242 Jul 31 04:45:12 PM PDT 24 Jul 31 04:45:13 PM PDT 24 43063671 ps
T510 /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.1229516143 Jul 31 04:45:02 PM PDT 24 Jul 31 04:45:03 PM PDT 24 38161579 ps
T511 /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.3430112847 Jul 31 04:45:20 PM PDT 24 Jul 31 04:45:21 PM PDT 24 162585973 ps
T512 /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.1405277370 Jul 31 04:44:58 PM PDT 24 Jul 31 04:44:58 PM PDT 24 19615594 ps
T513 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.331036585 Jul 31 04:45:32 PM PDT 24 Jul 31 04:45:32 PM PDT 24 115555815 ps
T514 /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3632239270 Jul 31 04:45:11 PM PDT 24 Jul 31 04:45:12 PM PDT 24 31726961 ps
T515 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.2460328035 Jul 31 04:45:32 PM PDT 24 Jul 31 04:45:33 PM PDT 24 28798318 ps
T516 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.922972207 Jul 31 04:44:51 PM PDT 24 Jul 31 04:44:52 PM PDT 24 35634221 ps
T517 /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.3940088810 Jul 31 04:45:28 PM PDT 24 Jul 31 04:45:30 PM PDT 24 150707100 ps
T518 /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.546298948 Jul 31 04:45:27 PM PDT 24 Jul 31 04:45:27 PM PDT 24 35372916 ps
T519 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.2149653549 Jul 31 04:45:08 PM PDT 24 Jul 31 04:45:14 PM PDT 24 56633951 ps
T520 /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.503331843 Jul 31 04:44:57 PM PDT 24 Jul 31 04:44:58 PM PDT 24 24511964 ps
T521 /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.2106657281 Jul 31 04:44:49 PM PDT 24 Jul 31 04:44:50 PM PDT 24 29963265 ps
T522 /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.3445875502 Jul 31 04:45:23 PM PDT 24 Jul 31 04:45:24 PM PDT 24 139936333 ps
T65 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.2237312090 Jul 31 04:45:27 PM PDT 24 Jul 31 04:45:28 PM PDT 24 12823398 ps
T523 /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.2819376789 Jul 31 04:45:10 PM PDT 24 Jul 31 04:45:11 PM PDT 24 137932298 ps
T524 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1732005783 Jul 31 04:45:19 PM PDT 24 Jul 31 04:45:20 PM PDT 24 21217733 ps
T525 /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.377211093 Jul 31 04:44:59 PM PDT 24 Jul 31 04:44:59 PM PDT 24 18004730 ps
T526 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.3091344497 Jul 31 04:45:12 PM PDT 24 Jul 31 04:45:14 PM PDT 24 908264354 ps
T527 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.3877360316 Jul 31 04:44:59 PM PDT 24 Jul 31 04:45:00 PM PDT 24 14050903 ps
T82 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1192109404 Jul 31 04:45:09 PM PDT 24 Jul 31 04:45:10 PM PDT 24 236882890 ps
T66 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.3186322784 Jul 31 04:45:06 PM PDT 24 Jul 31 04:45:07 PM PDT 24 36079376 ps
T528 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.2162457418 Jul 31 04:45:25 PM PDT 24 Jul 31 04:45:27 PM PDT 24 63765806 ps
T529 /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.4210492197 Jul 31 04:45:10 PM PDT 24 Jul 31 04:45:11 PM PDT 24 14976435 ps
T530 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3401215216 Jul 31 04:44:57 PM PDT 24 Jul 31 04:44:58 PM PDT 24 49588020 ps
T531 /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.3945125202 Jul 31 04:45:15 PM PDT 24 Jul 31 04:45:16 PM PDT 24 42233525 ps
T532 /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.925261817 Jul 31 04:44:57 PM PDT 24 Jul 31 04:45:00 PM PDT 24 506807342 ps
T67 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.3003980842 Jul 31 04:45:17 PM PDT 24 Jul 31 04:45:18 PM PDT 24 49713204 ps
T533 /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2870564741 Jul 31 04:44:56 PM PDT 24 Jul 31 04:44:58 PM PDT 24 439956228 ps
T534 /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.268099750 Jul 31 04:44:50 PM PDT 24 Jul 31 04:44:51 PM PDT 24 47255493 ps
T535 /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.4190788650 Jul 31 04:45:15 PM PDT 24 Jul 31 04:45:15 PM PDT 24 55457136 ps
T536 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.3576914617 Jul 31 04:45:00 PM PDT 24 Jul 31 04:45:00 PM PDT 24 89836659 ps
T537 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1702119460 Jul 31 04:45:08 PM PDT 24 Jul 31 04:45:09 PM PDT 24 25729216 ps
T538 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2189934116 Jul 31 04:45:17 PM PDT 24 Jul 31 04:45:18 PM PDT 24 47420010 ps
T539 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.637272932 Jul 31 04:45:25 PM PDT 24 Jul 31 04:45:26 PM PDT 24 127949017 ps
T540 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.1043877181 Jul 31 04:45:14 PM PDT 24 Jul 31 04:45:15 PM PDT 24 304690621 ps
T541 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.1428107923 Jul 31 04:45:12 PM PDT 24 Jul 31 04:45:13 PM PDT 24 30797309 ps
T542 /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.1650887851 Jul 31 04:45:22 PM PDT 24 Jul 31 04:45:23 PM PDT 24 77033887 ps
T543 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.3154359936 Jul 31 04:45:30 PM PDT 24 Jul 31 04:45:31 PM PDT 24 43711819 ps
T544 /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.1929135616 Jul 31 04:45:04 PM PDT 24 Jul 31 04:45:07 PM PDT 24 496275748 ps
T545 /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.2452179967 Jul 31 04:45:21 PM PDT 24 Jul 31 04:45:22 PM PDT 24 126296857 ps
T546 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.3163116226 Jul 31 04:45:18 PM PDT 24 Jul 31 04:45:19 PM PDT 24 23284949 ps
T547 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.2151953167 Jul 31 04:45:08 PM PDT 24 Jul 31 04:45:09 PM PDT 24 41749210 ps
T548 /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.3842488275 Jul 31 04:44:50 PM PDT 24 Jul 31 04:44:51 PM PDT 24 52857470 ps
T549 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.2693184474 Jul 31 04:44:52 PM PDT 24 Jul 31 04:44:53 PM PDT 24 72603627 ps
T550 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.3506534552 Jul 31 04:45:09 PM PDT 24 Jul 31 04:45:10 PM PDT 24 57064294 ps
T551 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2432050196 Jul 31 04:44:49 PM PDT 24 Jul 31 04:44:50 PM PDT 24 69718395 ps
T552 /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3006582632 Jul 31 04:44:55 PM PDT 24 Jul 31 04:44:56 PM PDT 24 15580502 ps
T553 /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.3377957197 Jul 31 04:44:51 PM PDT 24 Jul 31 04:44:54 PM PDT 24 48684162 ps
T83 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.2242262280 Jul 31 04:44:56 PM PDT 24 Jul 31 04:44:57 PM PDT 24 169358287 ps
T554 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.2828730227 Jul 31 04:45:09 PM PDT 24 Jul 31 04:45:10 PM PDT 24 52480766 ps
T555 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.4063637115 Jul 31 04:44:55 PM PDT 24 Jul 31 04:44:57 PM PDT 24 151470721 ps
T556 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.1841337557 Jul 31 04:45:26 PM PDT 24 Jul 31 04:45:26 PM PDT 24 23083284 ps
T557 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.327509345 Jul 31 04:45:27 PM PDT 24 Jul 31 04:45:27 PM PDT 24 45536424 ps
T558 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.1395587941 Jul 31 04:44:53 PM PDT 24 Jul 31 04:44:54 PM PDT 24 240737949 ps
T559 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.4149335721 Jul 31 04:45:11 PM PDT 24 Jul 31 04:45:12 PM PDT 24 12149303 ps
T560 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2622767727 Jul 31 04:45:17 PM PDT 24 Jul 31 04:45:18 PM PDT 24 76968467 ps
T561 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.966986479 Jul 31 04:45:22 PM PDT 24 Jul 31 04:45:22 PM PDT 24 69136931 ps
T562 /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.3365765913 Jul 31 04:45:19 PM PDT 24 Jul 31 04:45:20 PM PDT 24 12014028 ps
T563 /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.1947573408 Jul 31 04:45:07 PM PDT 24 Jul 31 04:45:07 PM PDT 24 36746199 ps
T564 /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.458421151 Jul 31 04:45:07 PM PDT 24 Jul 31 04:45:08 PM PDT 24 25922976 ps
T565 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.2586290577 Jul 31 04:45:12 PM PDT 24 Jul 31 04:45:12 PM PDT 24 102322218 ps
T566 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.474793996 Jul 31 04:44:55 PM PDT 24 Jul 31 04:44:57 PM PDT 24 138513403 ps
T567 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1916671848 Jul 31 04:45:09 PM PDT 24 Jul 31 04:45:11 PM PDT 24 134467004 ps
T568 /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.1842426693 Jul 31 04:45:07 PM PDT 24 Jul 31 04:45:09 PM PDT 24 705014645 ps
T569 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3265461431 Jul 31 04:45:03 PM PDT 24 Jul 31 04:45:04 PM PDT 24 214333349 ps
T570 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.3850532577 Jul 31 04:44:59 PM PDT 24 Jul 31 04:44:59 PM PDT 24 21823119 ps
T571 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.1717479779 Jul 31 04:45:03 PM PDT 24 Jul 31 04:45:04 PM PDT 24 56673109 ps
T572 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.2851662042 Jul 31 04:44:51 PM PDT 24 Jul 31 04:44:53 PM PDT 24 69562919 ps
T573 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.3322612298 Jul 31 04:45:01 PM PDT 24 Jul 31 04:45:02 PM PDT 24 13620555 ps
T574 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.15823025 Jul 31 04:45:03 PM PDT 24 Jul 31 04:45:04 PM PDT 24 16644109 ps
T575 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.913201339 Jul 31 04:45:00 PM PDT 24 Jul 31 04:45:05 PM PDT 24 10616693 ps
T576 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.274365273 Jul 31 04:45:18 PM PDT 24 Jul 31 04:45:20 PM PDT 24 28427467 ps
T577 /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.1325248874 Jul 31 04:45:08 PM PDT 24 Jul 31 04:45:09 PM PDT 24 14559447 ps

Test location /workspace/coverage/default/0.rv_timer_stress_all_with_rand_reset.3695415985
Short name T3
Test name
Test status
Simulation time 107638484778 ps
CPU time 196.23 seconds
Started Jul 31 04:23:54 PM PDT 24
Finished Jul 31 04:27:10 PM PDT 24
Peak memory 206132 kb
Host smart-9f964ae0-e0a5-4769-acec-9c7e4491a221
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695415985 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all_with_rand_reset.3695415985
Directory /workspace/0.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.2576796729
Short name T6
Test name
Test status
Simulation time 1023899641336 ps
CPU time 2178.34 seconds
Started Jul 31 04:27:48 PM PDT 24
Finished Jul 31 05:04:07 PM PDT 24
Peak memory 191408 kb
Host smart-80850cbb-b12a-4c5c-9e3c-61feed6b93de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576796729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.2576796729
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.1876874765
Short name T27
Test name
Test status
Simulation time 42046333 ps
CPU time 0.8 seconds
Started Jul 31 04:45:25 PM PDT 24
Finished Jul 31 04:45:26 PM PDT 24
Peak memory 193368 kb
Host smart-5cab164e-0e8a-4f69-8d23-3990f99fd0fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876874765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.1876874765
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.4259848765
Short name T135
Test name
Test status
Simulation time 2302184361161 ps
CPU time 6348.16 seconds
Started Jul 31 04:28:08 PM PDT 24
Finished Jul 31 06:13:57 PM PDT 24
Peak memory 195516 kb
Host smart-0d97ff5a-b53f-48e5-b337-f5abe1d7374d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259848765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.4259848765
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.720270331
Short name T151
Test name
Test status
Simulation time 3680666808968 ps
CPU time 4241.49 seconds
Started Jul 31 04:28:20 PM PDT 24
Finished Jul 31 05:39:02 PM PDT 24
Peak memory 196372 kb
Host smart-e1eb0f44-31cf-4b49-9c1a-8b7402b93f94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720270331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all.
720270331
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.2670884312
Short name T177
Test name
Test status
Simulation time 2064139614819 ps
CPU time 1372.49 seconds
Started Jul 31 04:28:17 PM PDT 24
Finished Jul 31 04:51:10 PM PDT 24
Peak memory 196480 kb
Host smart-af3d07fd-3e5a-4a14-b00b-004823340ed5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670884312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.2670884312
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.4088414201
Short name T52
Test name
Test status
Simulation time 602117038613 ps
CPU time 1327.22 seconds
Started Jul 31 04:27:59 PM PDT 24
Finished Jul 31 04:50:07 PM PDT 24
Peak memory 195516 kb
Host smart-2be4bd4d-5693-47ff-9e3f-1a189a8433b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088414201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.4088414201
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.3987139351
Short name T178
Test name
Test status
Simulation time 2622135554245 ps
CPU time 1828.92 seconds
Started Jul 31 04:27:55 PM PDT 24
Finished Jul 31 04:58:25 PM PDT 24
Peak memory 191452 kb
Host smart-182041b3-0f3e-413d-a86e-6d231905b890
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987139351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.3987139351
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.4082562466
Short name T45
Test name
Test status
Simulation time 34373045 ps
CPU time 0.58 seconds
Started Jul 31 04:45:02 PM PDT 24
Finished Jul 31 04:45:03 PM PDT 24
Peak memory 182688 kb
Host smart-edbe6637-cb8b-4f0e-8197-53cecb2ddc06
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082562466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.4082562466
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.4167427433
Short name T48
Test name
Test status
Simulation time 502587147090 ps
CPU time 786.94 seconds
Started Jul 31 04:27:41 PM PDT 24
Finished Jul 31 04:40:48 PM PDT 24
Peak memory 191448 kb
Host smart-bbccb59e-969f-46fd-a64d-16b01611d1ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167427433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.4167427433
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.3393455080
Short name T172
Test name
Test status
Simulation time 518193094448 ps
CPU time 1195.37 seconds
Started Jul 31 04:27:34 PM PDT 24
Finished Jul 31 04:47:30 PM PDT 24
Peak memory 191452 kb
Host smart-06929131-5121-4802-b404-d65fe3ef8b4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393455080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.3393455080
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.1604256920
Short name T157
Test name
Test status
Simulation time 1013891290893 ps
CPU time 1381.97 seconds
Started Jul 31 04:27:23 PM PDT 24
Finished Jul 31 04:50:25 PM PDT 24
Peak memory 191404 kb
Host smart-2cd05289-696d-427d-872d-c5c3e576e884
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604256920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
1604256920
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.3155135936
Short name T208
Test name
Test status
Simulation time 999021348609 ps
CPU time 3029.62 seconds
Started Jul 31 04:27:58 PM PDT 24
Finished Jul 31 05:18:28 PM PDT 24
Peak memory 191432 kb
Host smart-e1796fd7-96d2-4b32-b30c-d7a006425e51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155135936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.3155135936
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.3211083171
Short name T92
Test name
Test status
Simulation time 3236450959902 ps
CPU time 1672.3 seconds
Started Jul 31 04:28:10 PM PDT 24
Finished Jul 31 04:56:02 PM PDT 24
Peak memory 191500 kb
Host smart-9721c2af-5e03-45cd-bc0c-e521ca687cdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211083171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.3211083171
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.1351720895
Short name T14
Test name
Test status
Simulation time 112252465 ps
CPU time 0.79 seconds
Started Jul 31 04:24:41 PM PDT 24
Finished Jul 31 04:24:42 PM PDT 24
Peak memory 212556 kb
Host smart-7ab45dcf-aa22-4433-a434-16bc79017ce4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351720895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.1351720895
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.3656490448
Short name T152
Test name
Test status
Simulation time 1373175838213 ps
CPU time 2233.68 seconds
Started Jul 31 04:27:31 PM PDT 24
Finished Jul 31 05:04:45 PM PDT 24
Peak memory 191484 kb
Host smart-607b52d7-db9a-4b38-bab1-29c41b979cc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656490448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.3656490448
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/132.rv_timer_random.1723295308
Short name T89
Test name
Test status
Simulation time 277499627605 ps
CPU time 298.28 seconds
Started Jul 31 04:28:50 PM PDT 24
Finished Jul 31 04:33:49 PM PDT 24
Peak memory 191460 kb
Host smart-8c482739-bbf7-4ab5-9913-5b68b88027eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723295308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.1723295308
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.620521260
Short name T300
Test name
Test status
Simulation time 2059735558397 ps
CPU time 1287.24 seconds
Started Jul 31 04:27:36 PM PDT 24
Finished Jul 31 04:49:03 PM PDT 24
Peak memory 191464 kb
Host smart-cfa15258-6bfa-4d28-929a-f3ebe4fbf756
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620521260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all.
620521260
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.1069029752
Short name T49
Test name
Test status
Simulation time 1240464238201 ps
CPU time 925.92 seconds
Started Jul 31 04:20:41 PM PDT 24
Finished Jul 31 04:36:07 PM PDT 24
Peak memory 195856 kb
Host smart-07e8007f-a516-4a34-aea9-305024bfd3d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069029752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
1069029752
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.2048658809
Short name T236
Test name
Test status
Simulation time 3024574046892 ps
CPU time 2464.07 seconds
Started Jul 31 04:24:55 PM PDT 24
Finished Jul 31 05:06:00 PM PDT 24
Peak memory 191444 kb
Host smart-0012ae3c-8ecd-4d74-be79-040b2bcbaa0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048658809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
2048658809
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/181.rv_timer_random.1083276999
Short name T155
Test name
Test status
Simulation time 237902855630 ps
CPU time 206.81 seconds
Started Jul 31 04:29:07 PM PDT 24
Finished Jul 31 04:32:34 PM PDT 24
Peak memory 191516 kb
Host smart-44f7cdb9-da9d-4732-acf6-b80edad221e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083276999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.1083276999
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.1601666746
Short name T196
Test name
Test status
Simulation time 3181971754178 ps
CPU time 1968.7 seconds
Started Jul 31 04:28:11 PM PDT 24
Finished Jul 31 05:01:01 PM PDT 24
Peak memory 191436 kb
Host smart-6636c0e1-81d2-4898-adba-94954ae67a94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601666746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.1601666746
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_random.1336967075
Short name T255
Test name
Test status
Simulation time 149147397123 ps
CPU time 314.79 seconds
Started Jul 31 04:28:04 PM PDT 24
Finished Jul 31 04:33:18 PM PDT 24
Peak memory 191500 kb
Host smart-f27c95c1-f0b3-418a-ba2c-e12c3593f054
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336967075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.1336967075
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random.833575304
Short name T87
Test name
Test status
Simulation time 540353332987 ps
CPU time 516 seconds
Started Jul 31 04:28:12 PM PDT 24
Finished Jul 31 04:36:48 PM PDT 24
Peak memory 191480 kb
Host smart-9b394116-6efd-4163-b7d7-02c87fe186dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833575304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.833575304
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/90.rv_timer_random.2824312008
Short name T244
Test name
Test status
Simulation time 434078086102 ps
CPU time 925.77 seconds
Started Jul 31 04:28:34 PM PDT 24
Finished Jul 31 04:44:00 PM PDT 24
Peak memory 191496 kb
Host smart-ae529ebe-ed0c-47a0-99a9-487d1aa95e8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824312008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.2824312008
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.3223685208
Short name T98
Test name
Test status
Simulation time 458629387892 ps
CPU time 447.5 seconds
Started Jul 31 04:28:39 PM PDT 24
Finished Jul 31 04:36:07 PM PDT 24
Peak memory 191404 kb
Host smart-8e5f6032-f106-4afc-913e-79c8676c0910
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223685208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.3223685208
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.1607616002
Short name T182
Test name
Test status
Simulation time 1464194464325 ps
CPU time 639.32 seconds
Started Jul 31 04:28:51 PM PDT 24
Finished Jul 31 04:39:31 PM PDT 24
Peak memory 191508 kb
Host smart-d2f90545-78f7-403d-a36e-30a7779cb4e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607616002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.1607616002
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.307017956
Short name T131
Test name
Test status
Simulation time 1045898478778 ps
CPU time 345.2 seconds
Started Jul 31 04:27:42 PM PDT 24
Finished Jul 31 04:33:27 PM PDT 24
Peak memory 183228 kb
Host smart-f70db1da-b718-40b6-b7e2-c5986b26aaf6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307017956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.rv_timer_cfg_update_on_fly.307017956
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.672076412
Short name T50
Test name
Test status
Simulation time 529521035739 ps
CPU time 910.96 seconds
Started Jul 31 04:28:23 PM PDT 24
Finished Jul 31 04:43:34 PM PDT 24
Peak memory 191404 kb
Host smart-a91874ff-33cd-4b07-8fc6-9b24489e0bb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672076412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all.
672076412
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/88.rv_timer_random.2870304360
Short name T189
Test name
Test status
Simulation time 258992162058 ps
CPU time 1234.92 seconds
Started Jul 31 04:28:37 PM PDT 24
Finished Jul 31 04:49:13 PM PDT 24
Peak memory 191484 kb
Host smart-6e6851e4-fb57-42f9-a84b-9c49b8ff5bca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870304360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.2870304360
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.3785580404
Short name T233
Test name
Test status
Simulation time 917116509002 ps
CPU time 1821.48 seconds
Started Jul 31 04:28:34 PM PDT 24
Finished Jul 31 04:58:55 PM PDT 24
Peak memory 191488 kb
Host smart-e803ff33-da1d-4acf-b6de-c07adec0584c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785580404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.3785580404
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.589980451
Short name T234
Test name
Test status
Simulation time 215698739927 ps
CPU time 1074.04 seconds
Started Jul 31 04:27:51 PM PDT 24
Finished Jul 31 04:45:45 PM PDT 24
Peak memory 194396 kb
Host smart-f8cfca86-ef88-4748-aa23-03748da15f7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589980451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all.
589980451
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_random.3341845547
Short name T225
Test name
Test status
Simulation time 212337109596 ps
CPU time 193.57 seconds
Started Jul 31 04:27:58 PM PDT 24
Finished Jul 31 04:31:12 PM PDT 24
Peak memory 191480 kb
Host smart-d8505ad0-1fe2-4ca5-8305-8359ba43407b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341845547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.3341845547
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.1533057510
Short name T219
Test name
Test status
Simulation time 381024559230 ps
CPU time 1000.04 seconds
Started Jul 31 04:28:11 PM PDT 24
Finished Jul 31 04:44:51 PM PDT 24
Peak memory 195328 kb
Host smart-7600ff30-fc39-4c7e-9afd-2b28f58a300e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533057510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.1533057510
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/68.rv_timer_random.3867668751
Short name T137
Test name
Test status
Simulation time 576289034268 ps
CPU time 342.13 seconds
Started Jul 31 04:28:25 PM PDT 24
Finished Jul 31 04:34:07 PM PDT 24
Peak memory 191424 kb
Host smart-25e5914a-0dcb-47c0-af69-d971a9d7bc10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867668751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.3867668751
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.2835686367
Short name T19
Test name
Test status
Simulation time 170152758575 ps
CPU time 626.65 seconds
Started Jul 31 04:28:45 PM PDT 24
Finished Jul 31 04:39:12 PM PDT 24
Peak memory 183240 kb
Host smart-bb5df70b-3921-449e-927f-14999815400f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835686367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.2835686367
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random.1854788040
Short name T204
Test name
Test status
Simulation time 145968673280 ps
CPU time 206.41 seconds
Started Jul 31 04:26:22 PM PDT 24
Finished Jul 31 04:29:48 PM PDT 24
Peak memory 191376 kb
Host smart-967334be-42a9-4d7d-a663-c02a6a31948f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854788040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.1854788040
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.484925209
Short name T164
Test name
Test status
Simulation time 266553641851 ps
CPU time 166.49 seconds
Started Jul 31 04:28:45 PM PDT 24
Finished Jul 31 04:31:32 PM PDT 24
Peak memory 191456 kb
Host smart-a5652cab-3148-4cf4-a631-e7831362e505
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484925209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.484925209
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.238869461
Short name T159
Test name
Test status
Simulation time 155501449371 ps
CPU time 428.93 seconds
Started Jul 31 04:28:57 PM PDT 24
Finished Jul 31 04:36:06 PM PDT 24
Peak memory 191468 kb
Host smart-de88c1af-d543-47b0-9a81-009612d9c870
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238869461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.238869461
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.338477006
Short name T145
Test name
Test status
Simulation time 704348150401 ps
CPU time 745.51 seconds
Started Jul 31 04:28:27 PM PDT 24
Finished Jul 31 04:40:52 PM PDT 24
Peak memory 191512 kb
Host smart-20f445af-0e0b-4c4a-9f01-729c7cf8e6ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338477006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.338477006
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.694293730
Short name T506
Test name
Test status
Simulation time 66616471 ps
CPU time 1.06 seconds
Started Jul 31 04:44:53 PM PDT 24
Finished Jul 31 04:44:54 PM PDT 24
Peak memory 183268 kb
Host smart-28105d03-0085-451c-bf14-4133d5560f6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694293730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_in
tg_err.694293730
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.2319236281
Short name T227
Test name
Test status
Simulation time 261177071208 ps
CPU time 361.49 seconds
Started Jul 31 04:24:41 PM PDT 24
Finished Jul 31 04:30:43 PM PDT 24
Peak memory 190960 kb
Host smart-4babf8b1-66bb-4dda-84ed-cc764de5133f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319236281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
2319236281
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/153.rv_timer_random.2566085135
Short name T110
Test name
Test status
Simulation time 137023632759 ps
CPU time 814.72 seconds
Started Jul 31 04:28:56 PM PDT 24
Finished Jul 31 04:42:31 PM PDT 24
Peak memory 183260 kb
Host smart-e2f76c13-0e10-4ff8-8e9b-8ecd6d9ea1b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566085135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.2566085135
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.1127224459
Short name T269
Test name
Test status
Simulation time 614919073412 ps
CPU time 662.06 seconds
Started Jul 31 04:29:03 PM PDT 24
Finished Jul 31 04:40:06 PM PDT 24
Peak memory 191488 kb
Host smart-0aeede95-01fd-4889-a74c-1e28a0439b4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127224459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.1127224459
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.41304774
Short name T105
Test name
Test status
Simulation time 456873846550 ps
CPU time 237.41 seconds
Started Jul 31 04:28:01 PM PDT 24
Finished Jul 31 04:31:58 PM PDT 24
Peak memory 183248 kb
Host smart-980796ba-a7af-479a-973d-5b9fa70e035d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41304774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.rv_timer_cfg_update_on_fly.41304774
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.2787627190
Short name T47
Test name
Test status
Simulation time 1181982436102 ps
CPU time 1486.23 seconds
Started Jul 31 04:28:03 PM PDT 24
Finished Jul 31 04:52:50 PM PDT 24
Peak memory 191380 kb
Host smart-423158bd-e055-4ce6-8e09-29fe707017a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787627190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.2787627190
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/59.rv_timer_random.3361271899
Short name T248
Test name
Test status
Simulation time 246891879102 ps
CPU time 408.1 seconds
Started Jul 31 04:28:26 PM PDT 24
Finished Jul 31 04:35:14 PM PDT 24
Peak memory 191516 kb
Host smart-c0dc10b2-227e-457f-b45c-266d9f81e051
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361271899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.3361271899
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.1909087719
Short name T294
Test name
Test status
Simulation time 190798566437 ps
CPU time 811.19 seconds
Started Jul 31 04:28:41 PM PDT 24
Finished Jul 31 04:42:12 PM PDT 24
Peak memory 191536 kb
Host smart-94c601e6-fa8a-4841-85bc-d207b8fa63fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909087719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.1909087719
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.372481677
Short name T186
Test name
Test status
Simulation time 122056382029 ps
CPU time 255.9 seconds
Started Jul 31 04:28:42 PM PDT 24
Finished Jul 31 04:32:58 PM PDT 24
Peak memory 191452 kb
Host smart-bbbd5025-258c-4136-8baa-519a20a7797d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372481677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.372481677
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.1560756773
Short name T206
Test name
Test status
Simulation time 39609951395 ps
CPU time 32.41 seconds
Started Jul 31 04:27:34 PM PDT 24
Finished Jul 31 04:28:07 PM PDT 24
Peak memory 183024 kb
Host smart-e43aab31-7d4d-4477-adb0-79f3d255cc31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560756773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.1560756773
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/152.rv_timer_random.167042403
Short name T162
Test name
Test status
Simulation time 122579629186 ps
CPU time 144.75 seconds
Started Jul 31 04:28:59 PM PDT 24
Finished Jul 31 04:31:24 PM PDT 24
Peak memory 191444 kb
Host smart-f69bcf43-1801-4cb1-b913-3ff712a38fe7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167042403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.167042403
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.3567108555
Short name T339
Test name
Test status
Simulation time 35213915891 ps
CPU time 59.99 seconds
Started Jul 31 04:28:59 PM PDT 24
Finished Jul 31 04:29:59 PM PDT 24
Peak memory 191468 kb
Host smart-c94a658f-a99a-4d88-a013-25f10ac5835c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567108555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.3567108555
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.2561460248
Short name T272
Test name
Test status
Simulation time 147077689891 ps
CPU time 531.31 seconds
Started Jul 31 04:29:33 PM PDT 24
Finished Jul 31 04:38:24 PM PDT 24
Peak memory 191472 kb
Host smart-b08959a0-59e8-4e7b-90d6-f12c129d3dba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561460248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.2561460248
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.140073614
Short name T168
Test name
Test status
Simulation time 314676125318 ps
CPU time 632.89 seconds
Started Jul 31 04:27:48 PM PDT 24
Finished Jul 31 04:38:21 PM PDT 24
Peak memory 191480 kb
Host smart-0eeeffed-c606-47bb-becd-0ee863d8b2c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140073614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all.
140073614
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_random.3702597608
Short name T112
Test name
Test status
Simulation time 341973455076 ps
CPU time 257.63 seconds
Started Jul 31 04:27:48 PM PDT 24
Finished Jul 31 04:32:06 PM PDT 24
Peak memory 191472 kb
Host smart-e95e83ed-967d-404a-871a-9b532933a303
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702597608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.3702597608
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.3894267607
Short name T324
Test name
Test status
Simulation time 622944100538 ps
CPU time 1126.63 seconds
Started Jul 31 04:28:00 PM PDT 24
Finished Jul 31 04:46:47 PM PDT 24
Peak memory 191420 kb
Host smart-23bdf838-f7d9-47d0-8599-0b371af0d7c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894267607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.3894267607
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/69.rv_timer_random.3584050999
Short name T174
Test name
Test status
Simulation time 1549153940946 ps
CPU time 1103.64 seconds
Started Jul 31 04:28:25 PM PDT 24
Finished Jul 31 04:46:49 PM PDT 24
Peak memory 193696 kb
Host smart-3e49db50-b918-4419-a42b-e31adf200fb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584050999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.3584050999
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2876739712
Short name T60
Test name
Test status
Simulation time 31298970 ps
CPU time 0.59 seconds
Started Jul 31 04:45:03 PM PDT 24
Finished Jul 31 04:45:04 PM PDT 24
Peak memory 192208 kb
Host smart-be58590f-3176-4291-91c4-a28997797926
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876739712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.2876739712
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.132014086
Short name T149
Test name
Test status
Simulation time 100901725548 ps
CPU time 132.19 seconds
Started Jul 31 04:24:41 PM PDT 24
Finished Jul 31 04:26:54 PM PDT 24
Peak memory 182804 kb
Host smart-a964dcfb-ef86-4560-b70d-4b0b0ee37247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132014086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.132014086
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.3224597779
Short name T147
Test name
Test status
Simulation time 223389099570 ps
CPU time 366.87 seconds
Started Jul 31 04:20:59 PM PDT 24
Finished Jul 31 04:27:06 PM PDT 24
Peak memory 183056 kb
Host smart-351f0ebb-ff8a-4c81-91a8-876827eccf2b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224597779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.3224597779
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_random.1391780432
Short name T104
Test name
Test status
Simulation time 84311156011 ps
CPU time 157.57 seconds
Started Jul 31 04:27:30 PM PDT 24
Finished Jul 31 04:30:08 PM PDT 24
Peak memory 191432 kb
Host smart-0af0e600-121a-42fe-940e-d62464c89c03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391780432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.1391780432
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random.924636278
Short name T266
Test name
Test status
Simulation time 102981049459 ps
CPU time 150.43 seconds
Started Jul 31 04:27:30 PM PDT 24
Finished Jul 31 04:30:01 PM PDT 24
Peak memory 194692 kb
Host smart-f4b41064-97a1-4bb8-bc2a-38b69912d5b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924636278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.924636278
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random.231193362
Short name T122
Test name
Test status
Simulation time 79249065781 ps
CPU time 111.32 seconds
Started Jul 31 04:27:34 PM PDT 24
Finished Jul 31 04:29:25 PM PDT 24
Peak memory 191432 kb
Host smart-aa2e20a9-765d-4f32-97d9-2b32dc1d34e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231193362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.231193362
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.125961425
Short name T286
Test name
Test status
Simulation time 812579822005 ps
CPU time 753.5 seconds
Started Jul 31 04:28:52 PM PDT 24
Finished Jul 31 04:41:26 PM PDT 24
Peak memory 191432 kb
Host smart-e85775ae-a86d-43e8-99bc-89ace8dd6fef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125961425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.125961425
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random.427838955
Short name T262
Test name
Test status
Simulation time 366556237638 ps
CPU time 213.98 seconds
Started Jul 31 04:27:35 PM PDT 24
Finished Jul 31 04:31:09 PM PDT 24
Peak memory 191456 kb
Host smart-d27b9ae8-f66b-4516-8c77-4317cf33c335
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427838955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.427838955
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.2715569447
Short name T179
Test name
Test status
Simulation time 272060406337 ps
CPU time 346.34 seconds
Started Jul 31 04:29:06 PM PDT 24
Finished Jul 31 04:34:52 PM PDT 24
Peak memory 191448 kb
Host smart-6df6583c-153f-4e52-9f3d-3251cd2189d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715569447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.2715569447
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.3982902563
Short name T363
Test name
Test status
Simulation time 774193136365 ps
CPU time 759.15 seconds
Started Jul 31 04:29:07 PM PDT 24
Finished Jul 31 04:41:47 PM PDT 24
Peak memory 194156 kb
Host smart-726c1b24-e969-4484-9979-fd4232631bad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982902563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.3982902563
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random.1561777578
Short name T242
Test name
Test status
Simulation time 663288666722 ps
CPU time 321.35 seconds
Started Jul 31 04:27:56 PM PDT 24
Finished Jul 31 04:33:17 PM PDT 24
Peak memory 191500 kb
Host smart-55e3ba78-094c-4549-9301-2a9f791b3027
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561777578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.1561777578
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.1176249238
Short name T292
Test name
Test status
Simulation time 310455212983 ps
CPU time 437.16 seconds
Started Jul 31 04:28:05 PM PDT 24
Finished Jul 31 04:35:22 PM PDT 24
Peak memory 191500 kb
Host smart-9fec9ad0-12d4-430f-98a2-454c4210539a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176249238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.1176249238
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.3582780906
Short name T173
Test name
Test status
Simulation time 422132121470 ps
CPU time 285.87 seconds
Started Jul 31 04:28:12 PM PDT 24
Finished Jul 31 04:32:58 PM PDT 24
Peak memory 191504 kb
Host smart-6be940c2-0f2e-49d0-af31-ba58188fdca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582780906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.3582780906
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_random.4106170308
Short name T276
Test name
Test status
Simulation time 957674746101 ps
CPU time 536.04 seconds
Started Jul 31 04:28:13 PM PDT 24
Finished Jul 31 04:37:09 PM PDT 24
Peak memory 191576 kb
Host smart-c78e4f36-7ead-4041-843c-ce73fe8973ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106170308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.4106170308
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random.3775673203
Short name T200
Test name
Test status
Simulation time 187412660231 ps
CPU time 162.18 seconds
Started Jul 31 04:28:16 PM PDT 24
Finished Jul 31 04:30:59 PM PDT 24
Peak memory 191456 kb
Host smart-c0cf44e9-74a7-49e9-a5c0-b8de0b6adb47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775673203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.3775673203
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.1021942667
Short name T193
Test name
Test status
Simulation time 295939053022 ps
CPU time 1429.47 seconds
Started Jul 31 04:28:27 PM PDT 24
Finished Jul 31 04:52:17 PM PDT 24
Peak memory 193996 kb
Host smart-12dd5714-3555-4aba-9dd3-00fa03173987
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021942667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.1021942667
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.3094886334
Short name T201
Test name
Test status
Simulation time 220447605529 ps
CPU time 643.44 seconds
Started Jul 31 04:28:35 PM PDT 24
Finished Jul 31 04:39:19 PM PDT 24
Peak memory 191480 kb
Host smart-7f3b9200-d549-4bf1-92e0-cb3e6a95036a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094886334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.3094886334
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1192109404
Short name T82
Test name
Test status
Simulation time 236882890 ps
CPU time 1.12 seconds
Started Jul 31 04:45:09 PM PDT 24
Finished Jul 31 04:45:10 PM PDT 24
Peak memory 195340 kb
Host smart-e4ebc337-d33d-4bb3-bae6-6e3aba4fa8ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192109404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.1192109404
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.563931956
Short name T214
Test name
Test status
Simulation time 732384639192 ps
CPU time 290.85 seconds
Started Jul 31 04:23:31 PM PDT 24
Finished Jul 31 04:28:22 PM PDT 24
Peak memory 188976 kb
Host smart-025b27ac-0624-45c5-adde-1a14abccfdc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563931956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.563931956
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/118.rv_timer_random.3606990877
Short name T169
Test name
Test status
Simulation time 306726364017 ps
CPU time 142.07 seconds
Started Jul 31 04:28:45 PM PDT 24
Finished Jul 31 04:31:07 PM PDT 24
Peak memory 191464 kb
Host smart-ae3b18a2-6ac5-4a2a-a36f-42b375fa0aca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606990877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.3606990877
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.4105829675
Short name T114
Test name
Test status
Simulation time 251233414071 ps
CPU time 538.42 seconds
Started Jul 31 04:28:45 PM PDT 24
Finished Jul 31 04:37:43 PM PDT 24
Peak memory 191504 kb
Host smart-c15eff8d-0ca0-4d77-8f7f-d176b6dc1660
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105829675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.4105829675
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.490623904
Short name T407
Test name
Test status
Simulation time 7704880822633 ps
CPU time 1811.27 seconds
Started Jul 31 04:27:31 PM PDT 24
Finished Jul 31 04:57:42 PM PDT 24
Peak memory 183284 kb
Host smart-e6e09541-e334-483e-a7be-c4f69ee2c98c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490623904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.rv_timer_cfg_update_on_fly.490623904
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/124.rv_timer_random.879663420
Short name T328
Test name
Test status
Simulation time 620931511107 ps
CPU time 868.4 seconds
Started Jul 31 04:28:44 PM PDT 24
Finished Jul 31 04:43:13 PM PDT 24
Peak memory 191484 kb
Host smart-8e4d3427-86e2-4af2-90d4-c4b974d435f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879663420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.879663420
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random.2527389823
Short name T26
Test name
Test status
Simulation time 99187007385 ps
CPU time 132.62 seconds
Started Jul 31 04:27:29 PM PDT 24
Finished Jul 31 04:29:42 PM PDT 24
Peak memory 191476 kb
Host smart-88a86603-8320-45f9-b20b-6907190ef7aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527389823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.2527389823
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.3620378691
Short name T181
Test name
Test status
Simulation time 479390184969 ps
CPU time 1027.37 seconds
Started Jul 31 04:28:51 PM PDT 24
Finished Jul 31 04:45:58 PM PDT 24
Peak memory 191520 kb
Host smart-3f7e4371-167e-4c47-8300-bbf27bcb19ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620378691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.3620378691
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.362839111
Short name T121
Test name
Test status
Simulation time 5140376486 ps
CPU time 4.7 seconds
Started Jul 31 04:27:35 PM PDT 24
Finished Jul 31 04:27:40 PM PDT 24
Peak memory 183248 kb
Host smart-395c8d92-4d2c-478e-80f7-8016dc1cd047
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362839111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.rv_timer_cfg_update_on_fly.362839111
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.2236682625
Short name T1
Test name
Test status
Simulation time 2618364726435 ps
CPU time 1138.96 seconds
Started Jul 31 04:27:36 PM PDT 24
Finished Jul 31 04:46:35 PM PDT 24
Peak memory 191448 kb
Host smart-6e109567-bda1-4075-8783-fae897cc826c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236682625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.2236682625
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/163.rv_timer_random.1181625896
Short name T84
Test name
Test status
Simulation time 599310870955 ps
CPU time 464.6 seconds
Started Jul 31 04:29:01 PM PDT 24
Finished Jul 31 04:36:46 PM PDT 24
Peak memory 191424 kb
Host smart-606172a9-4a87-4db7-be39-7234f393b1a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181625896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.1181625896
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.1088996581
Short name T327
Test name
Test status
Simulation time 135390811383 ps
CPU time 245.25 seconds
Started Jul 31 04:29:05 PM PDT 24
Finished Jul 31 04:33:10 PM PDT 24
Peak memory 191452 kb
Host smart-8607cae7-a06e-4075-8668-cc0892eb0b57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088996581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.1088996581
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.445728198
Short name T148
Test name
Test status
Simulation time 198608015459 ps
CPU time 177.34 seconds
Started Jul 31 04:29:03 PM PDT 24
Finished Jul 31 04:32:01 PM PDT 24
Peak memory 191472 kb
Host smart-081957b4-7956-4aed-a94a-b49670bfc900
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445728198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.445728198
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.833667914
Short name T360
Test name
Test status
Simulation time 62671638880 ps
CPU time 106.41 seconds
Started Jul 31 04:29:10 PM PDT 24
Finished Jul 31 04:30:56 PM PDT 24
Peak memory 191456 kb
Host smart-66692a3a-55a2-4134-a38f-0534fd8cf2d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833667914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.833667914
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.4077853002
Short name T267
Test name
Test status
Simulation time 118779368637 ps
CPU time 469.08 seconds
Started Jul 31 04:29:12 PM PDT 24
Finished Jul 31 04:37:01 PM PDT 24
Peak memory 194128 kb
Host smart-4480ae95-dd80-4f27-950a-6d5a8c65ab54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077853002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.4077853002
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.3535917167
Short name T132
Test name
Test status
Simulation time 102454900798 ps
CPU time 172.92 seconds
Started Jul 31 04:29:11 PM PDT 24
Finished Jul 31 04:32:04 PM PDT 24
Peak memory 191436 kb
Host smart-14d283f1-df7a-44d7-9385-cd9a53d1bd4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535917167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.3535917167
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random.2632993322
Short name T94
Test name
Test status
Simulation time 340148179733 ps
CPU time 942.4 seconds
Started Jul 31 04:27:55 PM PDT 24
Finished Jul 31 04:43:37 PM PDT 24
Peak memory 191416 kb
Host smart-528b5c23-3c30-4b5d-b031-4038f8037006
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632993322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.2632993322
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.3701580732
Short name T299
Test name
Test status
Simulation time 2542633742646 ps
CPU time 1303 seconds
Started Jul 31 04:27:56 PM PDT 24
Finished Jul 31 04:49:40 PM PDT 24
Peak memory 183268 kb
Host smart-b87ba57b-796c-48d1-9acc-9d0c4d2a5c19
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701580732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.3701580732
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_random.2023574760
Short name T231
Test name
Test status
Simulation time 86405737099 ps
CPU time 70.37 seconds
Started Jul 31 04:28:02 PM PDT 24
Finished Jul 31 04:29:13 PM PDT 24
Peak memory 191472 kb
Host smart-b4448518-134f-4005-9ba0-dcc2dc5e3e7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023574760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.2023574760
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.1522662792
Short name T171
Test name
Test status
Simulation time 170300156097 ps
CPU time 1521.63 seconds
Started Jul 31 04:28:02 PM PDT 24
Finished Jul 31 04:53:24 PM PDT 24
Peak memory 191484 kb
Host smart-fe737fd6-b966-4990-9acc-9d4747b56560
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522662792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.1522662792
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_random.1872727394
Short name T239
Test name
Test status
Simulation time 124393405504 ps
CPU time 344.99 seconds
Started Jul 31 04:28:06 PM PDT 24
Finished Jul 31 04:33:51 PM PDT 24
Peak memory 191432 kb
Host smart-c6a82282-0d05-40b6-9e87-331921e22731
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872727394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.1872727394
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.3243200258
Short name T153
Test name
Test status
Simulation time 42685353940 ps
CPU time 70.57 seconds
Started Jul 31 04:28:10 PM PDT 24
Finished Jul 31 04:29:21 PM PDT 24
Peak memory 191428 kb
Host smart-9b608232-4a13-480d-abcb-15ae82080b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243200258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.3243200258
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.3249458910
Short name T222
Test name
Test status
Simulation time 5942739770 ps
CPU time 10.72 seconds
Started Jul 31 04:28:17 PM PDT 24
Finished Jul 31 04:28:28 PM PDT 24
Peak memory 183204 kb
Host smart-b81be069-91fb-4976-b7e8-e7846e7b1dc8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249458910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.3249458910
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_random.1502755635
Short name T128
Test name
Test status
Simulation time 135912812367 ps
CPU time 84.25 seconds
Started Jul 31 04:28:17 PM PDT 24
Finished Jul 31 04:29:42 PM PDT 24
Peak memory 195584 kb
Host smart-23e1242a-7bac-43f5-877a-fd6b8bdb2083
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502755635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.1502755635
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.1357452626
Short name T175
Test name
Test status
Simulation time 574293237888 ps
CPU time 811.94 seconds
Started Jul 31 04:28:22 PM PDT 24
Finished Jul 31 04:41:55 PM PDT 24
Peak memory 191448 kb
Host smart-b7048630-5327-4718-b4a8-1586e5340477
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357452626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.1357452626
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.277789408
Short name T211
Test name
Test status
Simulation time 145618103257 ps
CPU time 136.71 seconds
Started Jul 31 04:28:29 PM PDT 24
Finished Jul 31 04:30:45 PM PDT 24
Peak memory 191488 kb
Host smart-af710f7d-64c4-48de-8b6d-1df99836bfde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277789408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.277789408
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.608763030
Short name T190
Test name
Test status
Simulation time 40929440633 ps
CPU time 69.02 seconds
Started Jul 31 04:27:22 PM PDT 24
Finished Jul 31 04:28:31 PM PDT 24
Peak memory 183312 kb
Host smart-04efb35f-34be-4247-a2c7-48a1386d158a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608763030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.rv_timer_cfg_update_on_fly.608763030
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/96.rv_timer_random.3705350695
Short name T288
Test name
Test status
Simulation time 47557865288 ps
CPU time 73.53 seconds
Started Jul 31 04:28:36 PM PDT 24
Finished Jul 31 04:29:50 PM PDT 24
Peak memory 191472 kb
Host smart-8124ae6b-fbd0-4cd9-8bfe-970587c8af9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705350695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.3705350695
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.470374787
Short name T344
Test name
Test status
Simulation time 96597822374 ps
CPU time 89.95 seconds
Started Jul 31 04:28:43 PM PDT 24
Finished Jul 31 04:30:13 PM PDT 24
Peak memory 191404 kb
Host smart-085047f8-4bf2-40bc-a2f0-415a430d6d45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470374787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.470374787
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.2144756174
Short name T509
Test name
Test status
Simulation time 14922333 ps
CPU time 0.61 seconds
Started Jul 31 04:45:07 PM PDT 24
Finished Jul 31 04:45:08 PM PDT 24
Peak memory 191956 kb
Host smart-5f4f1cb2-99a6-4c3a-95e6-a3a55d939aec
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144756174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.2144756174
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.4063637115
Short name T555
Test name
Test status
Simulation time 151470721 ps
CPU time 1.55 seconds
Started Jul 31 04:44:55 PM PDT 24
Finished Jul 31 04:44:57 PM PDT 24
Peak memory 182940 kb
Host smart-c75bd713-b139-4766-ba64-2d5b7ebf3c51
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063637115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.4063637115
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.2035934833
Short name T507
Test name
Test status
Simulation time 14212056 ps
CPU time 0.59 seconds
Started Jul 31 04:44:56 PM PDT 24
Finished Jul 31 04:44:56 PM PDT 24
Peak memory 182740 kb
Host smart-fbaea6f5-5d79-4adc-8529-0088edfb50fe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035934833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.2035934833
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.592984860
Short name T496
Test name
Test status
Simulation time 204403174 ps
CPU time 0.83 seconds
Started Jul 31 04:45:12 PM PDT 24
Finished Jul 31 04:45:13 PM PDT 24
Peak memory 197100 kb
Host smart-8d6b2bc9-5f25-44d0-b323-c4616c78e215
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592984860 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.592984860
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.3759329875
Short name T42
Test name
Test status
Simulation time 29521948 ps
CPU time 0.59 seconds
Started Jul 31 04:45:03 PM PDT 24
Finished Jul 31 04:45:04 PM PDT 24
Peak memory 182884 kb
Host smart-b3f5788a-4f86-484a-9db4-9d3e5f5f6131
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759329875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.3759329875
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.3502108806
Short name T463
Test name
Test status
Simulation time 17082236 ps
CPU time 0.57 seconds
Started Jul 31 04:44:58 PM PDT 24
Finished Jul 31 04:45:08 PM PDT 24
Peak memory 182508 kb
Host smart-d5c50d6c-8ef7-45c0-aee0-dc349f20a893
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502108806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.3502108806
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.3842488275
Short name T548
Test name
Test status
Simulation time 52857470 ps
CPU time 0.68 seconds
Started Jul 31 04:44:50 PM PDT 24
Finished Jul 31 04:44:51 PM PDT 24
Peak memory 193088 kb
Host smart-b3390c34-7033-47ac-bd02-acb0eac927b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842488275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.3842488275
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.3091344497
Short name T526
Test name
Test status
Simulation time 908264354 ps
CPU time 2.37 seconds
Started Jul 31 04:45:12 PM PDT 24
Finished Jul 31 04:45:14 PM PDT 24
Peak memory 197468 kb
Host smart-dffe037d-1b2f-4b6c-9edf-d61a64ddb9e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091344497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.3091344497
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.474793996
Short name T566
Test name
Test status
Simulation time 138513403 ps
CPU time 1.29 seconds
Started Jul 31 04:44:55 PM PDT 24
Finished Jul 31 04:44:57 PM PDT 24
Peak memory 195624 kb
Host smart-593a6bf3-d715-47ae-8f13-fc7ecef520c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474793996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_int
g_err.474793996
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.2851662042
Short name T572
Test name
Test status
Simulation time 69562919 ps
CPU time 0.83 seconds
Started Jul 31 04:44:51 PM PDT 24
Finished Jul 31 04:44:53 PM PDT 24
Peak memory 192716 kb
Host smart-73a3c61a-4fa9-4427-95d9-d3e38e5000d2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851662042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.2851662042
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.3940088810
Short name T517
Test name
Test status
Simulation time 150707100 ps
CPU time 1.55 seconds
Started Jul 31 04:45:28 PM PDT 24
Finished Jul 31 04:45:30 PM PDT 24
Peak memory 192148 kb
Host smart-492192fd-1f65-4941-92c3-b85bccb1adf6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940088810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.3940088810
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.3576914617
Short name T536
Test name
Test status
Simulation time 89836659 ps
CPU time 0.55 seconds
Started Jul 31 04:45:00 PM PDT 24
Finished Jul 31 04:45:00 PM PDT 24
Peak memory 182764 kb
Host smart-c605645a-576f-40fd-879a-fb25fd2c7626
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576914617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.3576914617
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.2693184474
Short name T549
Test name
Test status
Simulation time 72603627 ps
CPU time 0.69 seconds
Started Jul 31 04:44:52 PM PDT 24
Finished Jul 31 04:44:53 PM PDT 24
Peak memory 194740 kb
Host smart-5d19eb65-c16c-40c1-8c47-a779fed0eb2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693184474 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.2693184474
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.1405277370
Short name T512
Test name
Test status
Simulation time 19615594 ps
CPU time 0.56 seconds
Started Jul 31 04:44:58 PM PDT 24
Finished Jul 31 04:44:58 PM PDT 24
Peak memory 182420 kb
Host smart-e3369ddf-3472-43e7-8c4b-05b33b9dde2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405277370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.1405277370
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.2239516318
Short name T460
Test name
Test status
Simulation time 16415089 ps
CPU time 0.56 seconds
Started Jul 31 04:44:53 PM PDT 24
Finished Jul 31 04:44:54 PM PDT 24
Peak memory 182632 kb
Host smart-78a81a06-b5db-4722-9193-3a68866e3019
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239516318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.2239516318
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.2106657281
Short name T521
Test name
Test status
Simulation time 29963265 ps
CPU time 0.59 seconds
Started Jul 31 04:44:49 PM PDT 24
Finished Jul 31 04:44:50 PM PDT 24
Peak memory 191968 kb
Host smart-dc06daeb-18b7-4d97-b0ef-d6ad60bfbe49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106657281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.2106657281
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.3377957197
Short name T553
Test name
Test status
Simulation time 48684162 ps
CPU time 2.35 seconds
Started Jul 31 04:44:51 PM PDT 24
Finished Jul 31 04:44:54 PM PDT 24
Peak memory 197500 kb
Host smart-e4c7fb93-cf15-4d1c-9307-324ce64153e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377957197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.3377957197
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.1395587941
Short name T558
Test name
Test status
Simulation time 240737949 ps
CPU time 1.33 seconds
Started Jul 31 04:44:53 PM PDT 24
Finished Jul 31 04:44:54 PM PDT 24
Peak memory 183244 kb
Host smart-e0dc9314-2aa1-4fc1-bd3e-5b296cb7dd01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395587941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.1395587941
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.3854328056
Short name T465
Test name
Test status
Simulation time 24629209 ps
CPU time 1.02 seconds
Started Jul 31 04:45:06 PM PDT 24
Finished Jul 31 04:45:07 PM PDT 24
Peak memory 197404 kb
Host smart-189e6cf9-6202-4634-956f-77d944063d7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854328056 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.3854328056
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.4257719143
Short name T479
Test name
Test status
Simulation time 14202549 ps
CPU time 0.58 seconds
Started Jul 31 04:45:10 PM PDT 24
Finished Jul 31 04:45:11 PM PDT 24
Peak memory 182768 kb
Host smart-52294994-078a-4f1f-8904-2cec3cba8737
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257719143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.4257719143
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.2509391558
Short name T462
Test name
Test status
Simulation time 16988051 ps
CPU time 0.54 seconds
Started Jul 31 04:45:09 PM PDT 24
Finished Jul 31 04:45:09 PM PDT 24
Peak memory 182624 kb
Host smart-e4b30b8c-ef2d-4f80-b926-8e7ec721338f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509391558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.2509391558
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1592183057
Short name T486
Test name
Test status
Simulation time 304079982 ps
CPU time 2.86 seconds
Started Jul 31 04:45:05 PM PDT 24
Finished Jul 31 04:45:08 PM PDT 24
Peak memory 197480 kb
Host smart-78b5db0f-80db-40e1-b1b6-91fb78ade663
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592183057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.1592183057
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.3444159149
Short name T76
Test name
Test status
Simulation time 147900308 ps
CPU time 1.11 seconds
Started Jul 31 04:45:10 PM PDT 24
Finished Jul 31 04:45:11 PM PDT 24
Peak memory 195096 kb
Host smart-5d3b13fe-765d-45ef-ad73-1e3a32d51c35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444159149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.3444159149
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.3556615637
Short name T31
Test name
Test status
Simulation time 18285479 ps
CPU time 0.59 seconds
Started Jul 31 04:45:24 PM PDT 24
Finished Jul 31 04:45:24 PM PDT 24
Peak memory 192916 kb
Host smart-90ebc8ed-8073-481a-94c3-a8135c527da1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556615637 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.3556615637
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.4186416072
Short name T56
Test name
Test status
Simulation time 43296794 ps
CPU time 0.57 seconds
Started Jul 31 04:45:11 PM PDT 24
Finished Jul 31 04:45:11 PM PDT 24
Peak memory 182700 kb
Host smart-a15a6cda-dee0-4e4d-b806-a5aed97c92c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186416072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.4186416072
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.1229516143
Short name T510
Test name
Test status
Simulation time 38161579 ps
CPU time 0.54 seconds
Started Jul 31 04:45:02 PM PDT 24
Finished Jul 31 04:45:03 PM PDT 24
Peak memory 182556 kb
Host smart-7d93ed2f-0036-4123-b833-6bf967ec514e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229516143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.1229516143
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3613076289
Short name T32
Test name
Test status
Simulation time 43989531 ps
CPU time 0.79 seconds
Started Jul 31 04:44:58 PM PDT 24
Finished Jul 31 04:44:59 PM PDT 24
Peak memory 193596 kb
Host smart-22f2eab8-daa7-4643-9119-5c8189e7e789
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613076289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.3613076289
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.1043877181
Short name T540
Test name
Test status
Simulation time 304690621 ps
CPU time 1.07 seconds
Started Jul 31 04:45:14 PM PDT 24
Finished Jul 31 04:45:15 PM PDT 24
Peak memory 197324 kb
Host smart-f3a1dce4-4ff3-41ab-afef-1e2cb523c736
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043877181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.1043877181
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.1612989212
Short name T77
Test name
Test status
Simulation time 231296493 ps
CPU time 0.98 seconds
Started Jul 31 04:44:51 PM PDT 24
Finished Jul 31 04:44:53 PM PDT 24
Peak memory 183256 kb
Host smart-4f31f724-260b-4916-a667-511a67e0bdd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612989212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.1612989212
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.2149653549
Short name T519
Test name
Test status
Simulation time 56633951 ps
CPU time 0.8 seconds
Started Jul 31 04:45:08 PM PDT 24
Finished Jul 31 04:45:14 PM PDT 24
Peak memory 196904 kb
Host smart-efba5515-608f-44d0-9b61-9b8b02e1d00a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149653549 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.2149653549
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2361061576
Short name T62
Test name
Test status
Simulation time 32724457 ps
CPU time 0.6 seconds
Started Jul 31 04:44:56 PM PDT 24
Finished Jul 31 04:44:57 PM PDT 24
Peak memory 182792 kb
Host smart-23ca1243-154e-440b-b6ec-2a84fde4f4de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361061576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.2361061576
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.3289785798
Short name T483
Test name
Test status
Simulation time 11137192 ps
CPU time 0.5 seconds
Started Jul 31 04:44:50 PM PDT 24
Finished Jul 31 04:44:51 PM PDT 24
Peak memory 182064 kb
Host smart-3219a152-977a-4d16-b17c-1e7efb898ef3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289785798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.3289785798
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.70102383
Short name T487
Test name
Test status
Simulation time 118544687 ps
CPU time 0.61 seconds
Started Jul 31 04:44:50 PM PDT 24
Finished Jul 31 04:44:51 PM PDT 24
Peak memory 192216 kb
Host smart-a7654b53-5bbd-419c-b616-c4b24836a306
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70102383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_tim
er_same_csr_outstanding.70102383
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.925261817
Short name T532
Test name
Test status
Simulation time 506807342 ps
CPU time 2.53 seconds
Started Jul 31 04:44:57 PM PDT 24
Finished Jul 31 04:45:00 PM PDT 24
Peak memory 197456 kb
Host smart-0f04b7a2-077d-40c7-ba8b-218977b53187
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925261817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.925261817
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.1962652443
Short name T29
Test name
Test status
Simulation time 339036118 ps
CPU time 1.05 seconds
Started Jul 31 04:45:26 PM PDT 24
Finished Jul 31 04:45:27 PM PDT 24
Peak memory 195100 kb
Host smart-e67361b1-de18-46db-85a3-58fe0053d0c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962652443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.1962652443
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2619099616
Short name T493
Test name
Test status
Simulation time 23202466 ps
CPU time 0.71 seconds
Started Jul 31 04:45:18 PM PDT 24
Finished Jul 31 04:45:19 PM PDT 24
Peak memory 194392 kb
Host smart-a2c5ecb4-bedf-4cf0-aa56-5a3e5f4b06b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619099616 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.2619099616
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3839794400
Short name T469
Test name
Test status
Simulation time 42528967 ps
CPU time 0.54 seconds
Started Jul 31 04:44:51 PM PDT 24
Finished Jul 31 04:44:52 PM PDT 24
Peak memory 182800 kb
Host smart-eb811a43-4f0c-4b05-ad9c-38b8e4bb62ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839794400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.3839794400
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.1717479779
Short name T571
Test name
Test status
Simulation time 56673109 ps
CPU time 0.59 seconds
Started Jul 31 04:45:03 PM PDT 24
Finished Jul 31 04:45:04 PM PDT 24
Peak memory 182520 kb
Host smart-e3739a1e-8103-4e5f-b789-a0677cd60e10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717479779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.1717479779
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.2460328035
Short name T515
Test name
Test status
Simulation time 28798318 ps
CPU time 0.7 seconds
Started Jul 31 04:45:32 PM PDT 24
Finished Jul 31 04:45:33 PM PDT 24
Peak memory 191704 kb
Host smart-34547c79-1638-4edd-9375-b2c1cc938bcb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460328035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.2460328035
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.1986673768
Short name T39
Test name
Test status
Simulation time 163992908 ps
CPU time 3.03 seconds
Started Jul 31 04:44:52 PM PDT 24
Finished Jul 31 04:45:00 PM PDT 24
Peak memory 197492 kb
Host smart-c2ec04c7-0de0-44b4-bd8a-080fae124bb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986673768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.1986673768
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.3430112847
Short name T511
Test name
Test status
Simulation time 162585973 ps
CPU time 0.82 seconds
Started Jul 31 04:45:20 PM PDT 24
Finished Jul 31 04:45:21 PM PDT 24
Peak memory 193708 kb
Host smart-621c24c4-11d1-4b39-aecb-1847d9b98d6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430112847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.3430112847
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.200410317
Short name T474
Test name
Test status
Simulation time 81867278 ps
CPU time 0.73 seconds
Started Jul 31 04:45:09 PM PDT 24
Finished Jul 31 04:45:10 PM PDT 24
Peak memory 194772 kb
Host smart-1d8b5e38-2ff0-4c6c-9776-e81666b888f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200410317 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.200410317
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3006582632
Short name T552
Test name
Test status
Simulation time 15580502 ps
CPU time 0.56 seconds
Started Jul 31 04:44:55 PM PDT 24
Finished Jul 31 04:44:56 PM PDT 24
Peak memory 182784 kb
Host smart-dd3e9d5a-f96c-4653-8677-63b2932374f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006582632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.3006582632
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.4190788650
Short name T535
Test name
Test status
Simulation time 55457136 ps
CPU time 0.54 seconds
Started Jul 31 04:45:15 PM PDT 24
Finished Jul 31 04:45:15 PM PDT 24
Peak memory 182540 kb
Host smart-5a468110-1ef0-4bf8-bedc-cc1431f2b08b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190788650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.4190788650
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.1655794302
Short name T70
Test name
Test status
Simulation time 213372012 ps
CPU time 0.82 seconds
Started Jul 31 04:45:20 PM PDT 24
Finished Jul 31 04:45:21 PM PDT 24
Peak memory 191840 kb
Host smart-9218b1c4-d681-448d-8f41-eba452f260e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655794302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.1655794302
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.1807200017
Short name T475
Test name
Test status
Simulation time 51507206 ps
CPU time 2.45 seconds
Started Jul 31 04:45:17 PM PDT 24
Finished Jul 31 04:45:19 PM PDT 24
Peak memory 197592 kb
Host smart-5feeabf3-5496-45ae-b29b-c406f9903e39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807200017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.1807200017
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.4224170808
Short name T30
Test name
Test status
Simulation time 105146395 ps
CPU time 0.65 seconds
Started Jul 31 04:45:19 PM PDT 24
Finished Jul 31 04:45:20 PM PDT 24
Peak memory 193752 kb
Host smart-1f9234bb-34c2-4b7c-90bd-3af4a6bec6fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224170808 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.4224170808
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.2419071644
Short name T43
Test name
Test status
Simulation time 13310365 ps
CPU time 0.57 seconds
Started Jul 31 04:45:20 PM PDT 24
Finished Jul 31 04:45:21 PM PDT 24
Peak memory 182776 kb
Host smart-bd3ba6db-7a10-401a-a5da-f63cc5f1a410
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419071644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.2419071644
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.3322612298
Short name T573
Test name
Test status
Simulation time 13620555 ps
CPU time 0.6 seconds
Started Jul 31 04:45:01 PM PDT 24
Finished Jul 31 04:45:02 PM PDT 24
Peak memory 182072 kb
Host smart-94c0593a-4198-4b4c-a81a-293a1881eaab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322612298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.3322612298
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.2606491360
Short name T508
Test name
Test status
Simulation time 134546706 ps
CPU time 0.78 seconds
Started Jul 31 04:45:17 PM PDT 24
Finished Jul 31 04:45:18 PM PDT 24
Peak memory 193380 kb
Host smart-094e6315-3f6e-40b7-b86c-5584c3ec6b8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606491360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.2606491360
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1916671848
Short name T567
Test name
Test status
Simulation time 134467004 ps
CPU time 2.37 seconds
Started Jul 31 04:45:09 PM PDT 24
Finished Jul 31 04:45:11 PM PDT 24
Peak memory 197544 kb
Host smart-574b48f4-484a-456e-82f0-4222bbae3f22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916671848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.1916671848
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.412445513
Short name T478
Test name
Test status
Simulation time 26787838 ps
CPU time 1.17 seconds
Started Jul 31 04:45:05 PM PDT 24
Finished Jul 31 04:45:06 PM PDT 24
Peak memory 197324 kb
Host smart-66a8de23-27b9-4982-8bf1-d78bd02c76cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412445513 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.412445513
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.913201339
Short name T575
Test name
Test status
Simulation time 10616693 ps
CPU time 0.52 seconds
Started Jul 31 04:45:00 PM PDT 24
Finished Jul 31 04:45:05 PM PDT 24
Peak memory 182444 kb
Host smart-988f12f5-4675-47ef-8403-f57240fb16e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913201339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.913201339
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.377211093
Short name T525
Test name
Test status
Simulation time 18004730 ps
CPU time 0.55 seconds
Started Jul 31 04:44:59 PM PDT 24
Finished Jul 31 04:44:59 PM PDT 24
Peak memory 182656 kb
Host smart-4d24d723-6971-418f-bedb-94b1707ac0bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377211093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.377211093
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1272251030
Short name T503
Test name
Test status
Simulation time 105956167 ps
CPU time 0.62 seconds
Started Jul 31 04:45:03 PM PDT 24
Finished Jul 31 04:45:04 PM PDT 24
Peak memory 191392 kb
Host smart-2b5d32ff-52f6-41dd-8b72-876536d2edaf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272251030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.1272251030
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.1929135616
Short name T544
Test name
Test status
Simulation time 496275748 ps
CPU time 2.39 seconds
Started Jul 31 04:45:04 PM PDT 24
Finished Jul 31 04:45:07 PM PDT 24
Peak memory 197484 kb
Host smart-2341579d-1559-4807-8355-489fc3064d53
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929135616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.1929135616
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2870564741
Short name T533
Test name
Test status
Simulation time 439956228 ps
CPU time 1.06 seconds
Started Jul 31 04:44:56 PM PDT 24
Finished Jul 31 04:44:58 PM PDT 24
Peak memory 195188 kb
Host smart-f9049a64-1afa-4e0d-a019-0381b8c3a7a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870564741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.2870564741
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.1303644584
Short name T505
Test name
Test status
Simulation time 171710902 ps
CPU time 0.97 seconds
Started Jul 31 04:45:03 PM PDT 24
Finished Jul 31 04:45:06 PM PDT 24
Peak memory 197356 kb
Host smart-f42417de-bf22-41eb-b12a-5d642d1461bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303644584 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.1303644584
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.966986479
Short name T561
Test name
Test status
Simulation time 69136931 ps
CPU time 0.56 seconds
Started Jul 31 04:45:22 PM PDT 24
Finished Jul 31 04:45:22 PM PDT 24
Peak memory 182748 kb
Host smart-2c9e351f-754c-48e3-8765-4bafa9d0b877
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966986479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.966986479
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1702119460
Short name T537
Test name
Test status
Simulation time 25729216 ps
CPU time 0.51 seconds
Started Jul 31 04:45:08 PM PDT 24
Finished Jul 31 04:45:09 PM PDT 24
Peak memory 182088 kb
Host smart-0eaedc58-9ba6-451a-9066-f44488cd2ab8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702119460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.1702119460
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.3805686974
Short name T55
Test name
Test status
Simulation time 40009565 ps
CPU time 0.79 seconds
Started Jul 31 04:45:26 PM PDT 24
Finished Jul 31 04:45:27 PM PDT 24
Peak memory 193316 kb
Host smart-740566f4-102e-43ca-baf9-e4e70e21dc41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805686974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.3805686974
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.3745937935
Short name T472
Test name
Test status
Simulation time 214863551 ps
CPU time 1.34 seconds
Started Jul 31 04:45:09 PM PDT 24
Finished Jul 31 04:45:10 PM PDT 24
Peak memory 196444 kb
Host smart-6757248f-6e3e-4ffd-97ff-1441c8919fb5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745937935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.3745937935
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.2936834388
Short name T78
Test name
Test status
Simulation time 90191445 ps
CPU time 0.8 seconds
Started Jul 31 04:45:28 PM PDT 24
Finished Jul 31 04:45:29 PM PDT 24
Peak memory 183116 kb
Host smart-99543e73-18bd-4d50-a4ad-5f7eafb2ae4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936834388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.2936834388
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.925100681
Short name T489
Test name
Test status
Simulation time 22913624 ps
CPU time 0.97 seconds
Started Jul 31 04:45:31 PM PDT 24
Finished Jul 31 04:45:32 PM PDT 24
Peak memory 197436 kb
Host smart-84f36415-13d1-4e00-a7a9-eddcaca87ca1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925100681 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.925100681
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.1781288503
Short name T75
Test name
Test status
Simulation time 14643841 ps
CPU time 0.52 seconds
Started Jul 31 04:45:24 PM PDT 24
Finished Jul 31 04:45:24 PM PDT 24
Peak memory 182432 kb
Host smart-c62b05cb-9ad4-48c1-863a-553247e04611
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781288503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.1781288503
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.1163448038
Short name T504
Test name
Test status
Simulation time 14036979 ps
CPU time 0.58 seconds
Started Jul 31 04:45:32 PM PDT 24
Finished Jul 31 04:45:33 PM PDT 24
Peak memory 182556 kb
Host smart-1748b8e7-ce77-49d1-a4c8-e2715c666541
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163448038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.1163448038
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.2452179967
Short name T545
Test name
Test status
Simulation time 126296857 ps
CPU time 0.8 seconds
Started Jul 31 04:45:21 PM PDT 24
Finished Jul 31 04:45:22 PM PDT 24
Peak memory 191644 kb
Host smart-b5a197cb-1af8-4e8a-a520-afbcae7d285a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452179967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.2452179967
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.274365273
Short name T576
Test name
Test status
Simulation time 28427467 ps
CPU time 1.41 seconds
Started Jul 31 04:45:18 PM PDT 24
Finished Jul 31 04:45:20 PM PDT 24
Peak memory 197616 kb
Host smart-105f124d-5a5a-4412-b423-ccfa8938e86e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274365273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.274365273
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.2162457418
Short name T528
Test name
Test status
Simulation time 63765806 ps
CPU time 1.61 seconds
Started Jul 31 04:45:25 PM PDT 24
Finished Jul 31 04:45:27 PM PDT 24
Peak memory 197652 kb
Host smart-ead8d91b-6f50-4a76-9427-4021da4d02e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162457418 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.2162457418
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.1624287351
Short name T57
Test name
Test status
Simulation time 13547690 ps
CPU time 0.6 seconds
Started Jul 31 04:45:34 PM PDT 24
Finished Jul 31 04:45:35 PM PDT 24
Peak memory 182780 kb
Host smart-1f98e9e5-91c9-4204-81ea-2c3d78484c71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624287351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.1624287351
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.637272932
Short name T539
Test name
Test status
Simulation time 127949017 ps
CPU time 0.54 seconds
Started Jul 31 04:45:25 PM PDT 24
Finished Jul 31 04:45:26 PM PDT 24
Peak memory 182476 kb
Host smart-6144727e-e80d-4258-af7c-a90d6a7b8843
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637272932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.637272932
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.3365765913
Short name T562
Test name
Test status
Simulation time 12014028 ps
CPU time 0.62 seconds
Started Jul 31 04:45:19 PM PDT 24
Finished Jul 31 04:45:20 PM PDT 24
Peak memory 192260 kb
Host smart-98614d32-a6cc-45ec-96f5-e1aa2cff1092
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365765913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.3365765913
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.1704933631
Short name T480
Test name
Test status
Simulation time 60598705 ps
CPU time 1.55 seconds
Started Jul 31 04:45:17 PM PDT 24
Finished Jul 31 04:45:19 PM PDT 24
Peak memory 197540 kb
Host smart-41a64b5c-dcdb-449f-a108-356b33dad517
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704933631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.1704933631
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1154147186
Short name T81
Test name
Test status
Simulation time 91779666 ps
CPU time 1.13 seconds
Started Jul 31 04:45:28 PM PDT 24
Finished Jul 31 04:45:29 PM PDT 24
Peak memory 194136 kb
Host smart-5f65fa45-b91f-4995-a5eb-8f7a5711a310
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154147186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.1154147186
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.3865704900
Short name T491
Test name
Test status
Simulation time 20007508 ps
CPU time 0.63 seconds
Started Jul 31 04:45:05 PM PDT 24
Finished Jul 31 04:45:06 PM PDT 24
Peak memory 192072 kb
Host smart-37c34cd0-f9d1-4259-b88f-5c60dbc8796a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865704900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.3865704900
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.2826651067
Short name T68
Test name
Test status
Simulation time 120227189 ps
CPU time 2.21 seconds
Started Jul 31 04:45:21 PM PDT 24
Finished Jul 31 04:45:24 PM PDT 24
Peak memory 191112 kb
Host smart-255c464d-cce5-4b8c-96a6-68a628587bb7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826651067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.2826651067
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.2828730227
Short name T554
Test name
Test status
Simulation time 52480766 ps
CPU time 0.87 seconds
Started Jul 31 04:45:09 PM PDT 24
Finished Jul 31 04:45:10 PM PDT 24
Peak memory 197172 kb
Host smart-64aee0b0-f3b3-48c7-abe6-4d0790bb9ff8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828730227 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.2828730227
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.1794943406
Short name T63
Test name
Test status
Simulation time 16876394 ps
CPU time 0.58 seconds
Started Jul 31 04:45:14 PM PDT 24
Finished Jul 31 04:45:14 PM PDT 24
Peak memory 182740 kb
Host smart-08453e3c-c12b-4533-9557-656a93746868
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794943406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.1794943406
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.4149335721
Short name T559
Test name
Test status
Simulation time 12149303 ps
CPU time 0.52 seconds
Started Jul 31 04:45:11 PM PDT 24
Finished Jul 31 04:45:12 PM PDT 24
Peak memory 182528 kb
Host smart-b1228b2c-4ce5-4d23-9ef2-3dd65b722089
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149335721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.4149335721
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.3034522870
Short name T72
Test name
Test status
Simulation time 80223018 ps
CPU time 0.79 seconds
Started Jul 31 04:44:56 PM PDT 24
Finished Jul 31 04:44:57 PM PDT 24
Peak memory 193556 kb
Host smart-6f6f9cd3-bfa1-4cce-bc06-ca657d38ecd8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034522870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.3034522870
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.1974247743
Short name T490
Test name
Test status
Simulation time 657436213 ps
CPU time 1.42 seconds
Started Jul 31 04:44:50 PM PDT 24
Finished Jul 31 04:44:52 PM PDT 24
Peak memory 197460 kb
Host smart-4497e841-c8e6-4e4b-864a-3b212bedcb98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974247743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.1974247743
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.97693641
Short name T46
Test name
Test status
Simulation time 60948208 ps
CPU time 0.85 seconds
Started Jul 31 04:44:51 PM PDT 24
Finished Jul 31 04:44:52 PM PDT 24
Peak memory 193612 kb
Host smart-43c405c1-07ee-4f3b-a4a0-a583dcb73864
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97693641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_intg
_err.97693641
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.1428107923
Short name T541
Test name
Test status
Simulation time 30797309 ps
CPU time 0.51 seconds
Started Jul 31 04:45:12 PM PDT 24
Finished Jul 31 04:45:13 PM PDT 24
Peak memory 182012 kb
Host smart-6aad9c50-2847-47b4-9669-c972f77c8d9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428107923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.1428107923
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.3026562617
Short name T461
Test name
Test status
Simulation time 21683503 ps
CPU time 0.52 seconds
Started Jul 31 04:45:24 PM PDT 24
Finished Jul 31 04:45:25 PM PDT 24
Peak memory 182052 kb
Host smart-ac62f84f-935f-4850-9845-8ae5806ff1b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026562617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.3026562617
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.914630968
Short name T457
Test name
Test status
Simulation time 12041988 ps
CPU time 0.54 seconds
Started Jul 31 04:45:11 PM PDT 24
Finished Jul 31 04:45:11 PM PDT 24
Peak memory 182592 kb
Host smart-7fdb637c-45ff-46b9-8eac-32a8f642f101
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914630968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.914630968
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.4109470470
Short name T456
Test name
Test status
Simulation time 24220978 ps
CPU time 0.55 seconds
Started Jul 31 04:45:18 PM PDT 24
Finished Jul 31 04:45:19 PM PDT 24
Peak memory 182612 kb
Host smart-4525420a-755a-40c2-8304-9c7ca85edc9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109470470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.4109470470
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.926473275
Short name T497
Test name
Test status
Simulation time 17428917 ps
CPU time 0.56 seconds
Started Jul 31 04:45:25 PM PDT 24
Finished Jul 31 04:45:26 PM PDT 24
Peak memory 182548 kb
Host smart-5b33143d-ea70-4c11-a613-01dc76d56197
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926473275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.926473275
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.2184455475
Short name T471
Test name
Test status
Simulation time 25216891 ps
CPU time 0.54 seconds
Started Jul 31 04:45:28 PM PDT 24
Finished Jul 31 04:45:28 PM PDT 24
Peak memory 182024 kb
Host smart-24ddcb27-8992-4d65-82d5-28031f2ee453
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184455475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.2184455475
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.458421151
Short name T564
Test name
Test status
Simulation time 25922976 ps
CPU time 0.53 seconds
Started Jul 31 04:45:07 PM PDT 24
Finished Jul 31 04:45:08 PM PDT 24
Peak memory 182012 kb
Host smart-19d5d9b2-5fe1-4ea9-8a08-5e5496cf7607
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458421151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.458421151
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.3154359936
Short name T543
Test name
Test status
Simulation time 43711819 ps
CPU time 0.53 seconds
Started Jul 31 04:45:30 PM PDT 24
Finished Jul 31 04:45:31 PM PDT 24
Peak memory 182044 kb
Host smart-a0abfaaa-7003-4e03-9f8c-92ee8725f55a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154359936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.3154359936
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.3345347979
Short name T467
Test name
Test status
Simulation time 14777676 ps
CPU time 0.55 seconds
Started Jul 31 04:45:24 PM PDT 24
Finished Jul 31 04:45:24 PM PDT 24
Peak memory 182536 kb
Host smart-2fd01dd6-63d1-487c-aac1-4b11450c886a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345347979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.3345347979
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.15823025
Short name T574
Test name
Test status
Simulation time 16644109 ps
CPU time 0.56 seconds
Started Jul 31 04:45:03 PM PDT 24
Finished Jul 31 04:45:04 PM PDT 24
Peak memory 182556 kb
Host smart-a7380645-e17f-4343-95e1-ab69e99d40d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15823025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.15823025
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.360583036
Short name T61
Test name
Test status
Simulation time 24803001 ps
CPU time 0.76 seconds
Started Jul 31 04:45:00 PM PDT 24
Finished Jul 31 04:45:01 PM PDT 24
Peak memory 192612 kb
Host smart-806ecff7-5b84-4972-8fd2-4bc83628b0d6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360583036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alias
ing.360583036
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.2083036415
Short name T470
Test name
Test status
Simulation time 1664285114 ps
CPU time 3.68 seconds
Started Jul 31 04:44:52 PM PDT 24
Finished Jul 31 04:44:56 PM PDT 24
Peak memory 191144 kb
Host smart-61e55e50-7454-4ac7-979d-338b60acd7f5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083036415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.2083036415
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3897408235
Short name T54
Test name
Test status
Simulation time 14422026 ps
CPU time 0.6 seconds
Started Jul 31 04:45:08 PM PDT 24
Finished Jul 31 04:45:09 PM PDT 24
Peak memory 182792 kb
Host smart-b39c3b8c-e81e-4ba6-bac9-5355ec01abf9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897408235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.3897408235
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.3850532577
Short name T570
Test name
Test status
Simulation time 21823119 ps
CPU time 0.68 seconds
Started Jul 31 04:44:59 PM PDT 24
Finished Jul 31 04:44:59 PM PDT 24
Peak memory 194460 kb
Host smart-4e9cae90-5a4a-4cce-a849-af1d24939e94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850532577 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.3850532577
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.2586290577
Short name T565
Test name
Test status
Simulation time 102322218 ps
CPU time 0.55 seconds
Started Jul 31 04:45:12 PM PDT 24
Finished Jul 31 04:45:12 PM PDT 24
Peak memory 182460 kb
Host smart-a9a31d11-0d17-4ee8-af31-ead4a7ad6c3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586290577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.2586290577
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.1947573408
Short name T563
Test name
Test status
Simulation time 36746199 ps
CPU time 0.53 seconds
Started Jul 31 04:45:07 PM PDT 24
Finished Jul 31 04:45:07 PM PDT 24
Peak memory 182568 kb
Host smart-31216733-ad22-4681-8812-810f1b9c0457
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947573408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.1947573408
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.2122987562
Short name T73
Test name
Test status
Simulation time 33068256 ps
CPU time 0.61 seconds
Started Jul 31 04:44:50 PM PDT 24
Finished Jul 31 04:44:52 PM PDT 24
Peak memory 192016 kb
Host smart-93ad46d8-f8bd-481c-a5ff-37cd559d0389
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122987562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.2122987562
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3759467912
Short name T501
Test name
Test status
Simulation time 133799976 ps
CPU time 1.73 seconds
Started Jul 31 04:44:52 PM PDT 24
Finished Jul 31 04:44:54 PM PDT 24
Peak memory 197520 kb
Host smart-70cc4236-3e5f-4381-ae12-e74f42b0f3b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759467912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.3759467912
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.3445875502
Short name T522
Test name
Test status
Simulation time 139936333 ps
CPU time 0.79 seconds
Started Jul 31 04:45:23 PM PDT 24
Finished Jul 31 04:45:24 PM PDT 24
Peak memory 193860 kb
Host smart-81e85188-46d6-4299-bab9-a6ddcb02333d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445875502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.3445875502
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.1650887851
Short name T542
Test name
Test status
Simulation time 77033887 ps
CPU time 0.55 seconds
Started Jul 31 04:45:22 PM PDT 24
Finished Jul 31 04:45:23 PM PDT 24
Peak memory 182528 kb
Host smart-b4cf47ec-d964-4d72-9447-96917f6c59c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650887851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.1650887851
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.1214446454
Short name T495
Test name
Test status
Simulation time 14164164 ps
CPU time 0.57 seconds
Started Jul 31 04:45:04 PM PDT 24
Finished Jul 31 04:45:04 PM PDT 24
Peak memory 182564 kb
Host smart-d31fb510-1781-4ab1-a79f-a4d370838828
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214446454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.1214446454
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.3506534552
Short name T550
Test name
Test status
Simulation time 57064294 ps
CPU time 0.54 seconds
Started Jul 31 04:45:09 PM PDT 24
Finished Jul 31 04:45:10 PM PDT 24
Peak memory 182652 kb
Host smart-79cfbe07-a420-412f-888b-106d934992d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506534552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.3506534552
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.2151953167
Short name T547
Test name
Test status
Simulation time 41749210 ps
CPU time 0.52 seconds
Started Jul 31 04:45:08 PM PDT 24
Finished Jul 31 04:45:09 PM PDT 24
Peak memory 182684 kb
Host smart-3d2c1df5-166a-4f44-8141-0c585d2035ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151953167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.2151953167
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.3993143268
Short name T484
Test name
Test status
Simulation time 17378457 ps
CPU time 0.57 seconds
Started Jul 31 04:45:18 PM PDT 24
Finished Jul 31 04:45:19 PM PDT 24
Peak memory 182584 kb
Host smart-22b5d3b1-7bf0-4ff5-80f1-309c9b2abbc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993143268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.3993143268
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2189934116
Short name T538
Test name
Test status
Simulation time 47420010 ps
CPU time 0.56 seconds
Started Jul 31 04:45:17 PM PDT 24
Finished Jul 31 04:45:18 PM PDT 24
Peak memory 182580 kb
Host smart-dcaafd27-71cf-43a0-8b55-e68082f3e297
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189934116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.2189934116
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.3419351903
Short name T481
Test name
Test status
Simulation time 39871680 ps
CPU time 0.63 seconds
Started Jul 31 04:45:24 PM PDT 24
Finished Jul 31 04:45:25 PM PDT 24
Peak memory 181796 kb
Host smart-b0ce18e8-022a-4840-94d3-8c201ca8937a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419351903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.3419351903
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.3183023076
Short name T458
Test name
Test status
Simulation time 51404398 ps
CPU time 0.55 seconds
Started Jul 31 04:45:13 PM PDT 24
Finished Jul 31 04:45:13 PM PDT 24
Peak memory 182564 kb
Host smart-30b48536-e396-4975-92cb-33ecb2646856
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183023076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.3183023076
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.466642532
Short name T498
Test name
Test status
Simulation time 12500798 ps
CPU time 0.55 seconds
Started Jul 31 04:45:27 PM PDT 24
Finished Jul 31 04:45:28 PM PDT 24
Peak memory 182512 kb
Host smart-93f70ed2-4ddb-4ee9-8576-0da281eba57e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466642532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.466642532
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.4210492197
Short name T529
Test name
Test status
Simulation time 14976435 ps
CPU time 0.57 seconds
Started Jul 31 04:45:10 PM PDT 24
Finished Jul 31 04:45:11 PM PDT 24
Peak memory 182584 kb
Host smart-0abadc4f-68a5-4467-80df-a3c9eedecc94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210492197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.4210492197
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.3186322784
Short name T66
Test name
Test status
Simulation time 36079376 ps
CPU time 0.79 seconds
Started Jul 31 04:45:06 PM PDT 24
Finished Jul 31 04:45:07 PM PDT 24
Peak memory 192620 kb
Host smart-86f4cb78-9535-4c53-a8a6-5419c3dcb801
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186322784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.3186322784
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.2999770381
Short name T476
Test name
Test status
Simulation time 181666446 ps
CPU time 1.51 seconds
Started Jul 31 04:45:09 PM PDT 24
Finished Jul 31 04:45:15 PM PDT 24
Peak memory 191128 kb
Host smart-cae53250-d6f5-41b5-948a-fab5b9b0947e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999770381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.2999770381
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.1312264703
Short name T59
Test name
Test status
Simulation time 47469699 ps
CPU time 0.54 seconds
Started Jul 31 04:44:53 PM PDT 24
Finished Jul 31 04:44:54 PM PDT 24
Peak memory 182772 kb
Host smart-bf615070-b2e3-4fd4-b981-1212f3fc6d0a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312264703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.1312264703
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3851413667
Short name T473
Test name
Test status
Simulation time 17521559 ps
CPU time 0.67 seconds
Started Jul 31 04:45:10 PM PDT 24
Finished Jul 31 04:45:11 PM PDT 24
Peak memory 194308 kb
Host smart-3f085403-ea0f-4e80-a5e4-aa8e58cede13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851413667 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.3851413667
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.3003980842
Short name T67
Test name
Test status
Simulation time 49713204 ps
CPU time 0.54 seconds
Started Jul 31 04:45:17 PM PDT 24
Finished Jul 31 04:45:18 PM PDT 24
Peak memory 182668 kb
Host smart-a167a8ee-f145-4ad5-a842-81abc223bacc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003980842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.3003980842
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.503331843
Short name T520
Test name
Test status
Simulation time 24511964 ps
CPU time 0.58 seconds
Started Jul 31 04:44:57 PM PDT 24
Finished Jul 31 04:44:58 PM PDT 24
Peak memory 182732 kb
Host smart-e0207e03-a8d9-4615-ae78-8a1e2d79e590
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503331843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.503331843
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.268099750
Short name T534
Test name
Test status
Simulation time 47255493 ps
CPU time 0.65 seconds
Started Jul 31 04:44:50 PM PDT 24
Finished Jul 31 04:44:51 PM PDT 24
Peak memory 191992 kb
Host smart-3918d577-77dd-4f7e-aa3f-9ba2373f4431
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268099750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_tim
er_same_csr_outstanding.268099750
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2622767727
Short name T560
Test name
Test status
Simulation time 76968467 ps
CPU time 1.06 seconds
Started Jul 31 04:45:17 PM PDT 24
Finished Jul 31 04:45:18 PM PDT 24
Peak memory 197184 kb
Host smart-8f15aa32-ac0e-4da3-8ddc-998d878d6a9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622767727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.2622767727
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2064337149
Short name T79
Test name
Test status
Simulation time 442897615 ps
CPU time 0.85 seconds
Started Jul 31 04:45:19 PM PDT 24
Finished Jul 31 04:45:20 PM PDT 24
Peak memory 183316 kb
Host smart-8e34f190-2253-441a-a646-fdf015fc823e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064337149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.2064337149
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.3163116226
Short name T546
Test name
Test status
Simulation time 23284949 ps
CPU time 0.59 seconds
Started Jul 31 04:45:18 PM PDT 24
Finished Jul 31 04:45:19 PM PDT 24
Peak memory 182564 kb
Host smart-dc0e0382-ee11-43b4-9935-39a27188efe1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163116226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.3163116226
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.2318101264
Short name T499
Test name
Test status
Simulation time 94297104 ps
CPU time 0.54 seconds
Started Jul 31 04:45:27 PM PDT 24
Finished Jul 31 04:45:28 PM PDT 24
Peak memory 182568 kb
Host smart-47949001-9a04-4c84-ab2d-300e55f196c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318101264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.2318101264
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.546298948
Short name T518
Test name
Test status
Simulation time 35372916 ps
CPU time 0.57 seconds
Started Jul 31 04:45:27 PM PDT 24
Finished Jul 31 04:45:27 PM PDT 24
Peak memory 182620 kb
Host smart-6b0507e4-6ece-422e-ab92-1a17be5cf366
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546298948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.546298948
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.3190000887
Short name T494
Test name
Test status
Simulation time 90858487 ps
CPU time 0.57 seconds
Started Jul 31 04:45:06 PM PDT 24
Finished Jul 31 04:45:06 PM PDT 24
Peak memory 182720 kb
Host smart-24a305fd-78a9-4041-bca4-f222215ccf60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190000887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.3190000887
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.331036585
Short name T513
Test name
Test status
Simulation time 115555815 ps
CPU time 0.52 seconds
Started Jul 31 04:45:32 PM PDT 24
Finished Jul 31 04:45:32 PM PDT 24
Peak memory 182104 kb
Host smart-12f82e11-0419-43e6-9f4f-8ecc6e38c227
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331036585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.331036585
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1732005783
Short name T524
Test name
Test status
Simulation time 21217733 ps
CPU time 0.51 seconds
Started Jul 31 04:45:19 PM PDT 24
Finished Jul 31 04:45:20 PM PDT 24
Peak memory 182020 kb
Host smart-9d278478-3b00-4a5a-8755-caa4b33701f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732005783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.1732005783
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.2715249145
Short name T482
Test name
Test status
Simulation time 13351017 ps
CPU time 0.52 seconds
Started Jul 31 04:45:08 PM PDT 24
Finished Jul 31 04:45:09 PM PDT 24
Peak memory 182256 kb
Host smart-5f20a117-e1d9-4908-a245-d474d0bbc549
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715249145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.2715249145
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.1841337557
Short name T556
Test name
Test status
Simulation time 23083284 ps
CPU time 0.53 seconds
Started Jul 31 04:45:26 PM PDT 24
Finished Jul 31 04:45:26 PM PDT 24
Peak memory 182084 kb
Host smart-93cf3e28-e939-474c-a206-6b8cdb72cd72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841337557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.1841337557
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.327509345
Short name T557
Test name
Test status
Simulation time 45536424 ps
CPU time 0.56 seconds
Started Jul 31 04:45:27 PM PDT 24
Finished Jul 31 04:45:27 PM PDT 24
Peak memory 182580 kb
Host smart-8d565ef0-0542-49b2-90fc-33216fc421e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327509345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.327509345
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.2373601856
Short name T464
Test name
Test status
Simulation time 19786968 ps
CPU time 0.55 seconds
Started Jul 31 04:45:21 PM PDT 24
Finished Jul 31 04:45:22 PM PDT 24
Peak memory 182620 kb
Host smart-b4b6bef4-0fec-4dab-80af-da7797005ac0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373601856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.2373601856
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2432050196
Short name T551
Test name
Test status
Simulation time 69718395 ps
CPU time 0.87 seconds
Started Jul 31 04:44:49 PM PDT 24
Finished Jul 31 04:44:50 PM PDT 24
Peak memory 196932 kb
Host smart-729b07c0-f510-489f-8359-e5da57e426f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432050196 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.2432050196
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.2063459934
Short name T44
Test name
Test status
Simulation time 15752341 ps
CPU time 0.59 seconds
Started Jul 31 04:45:09 PM PDT 24
Finished Jul 31 04:45:15 PM PDT 24
Peak memory 182880 kb
Host smart-fe7aad79-a8ce-48c6-9131-5c6a2a9cabc1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063459934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.2063459934
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.3953501289
Short name T466
Test name
Test status
Simulation time 44822046 ps
CPU time 0.55 seconds
Started Jul 31 04:44:50 PM PDT 24
Finished Jul 31 04:44:51 PM PDT 24
Peak memory 182744 kb
Host smart-edd92696-d162-49a8-9dd6-b95bda300bd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953501289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.3953501289
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1341486834
Short name T58
Test name
Test status
Simulation time 151846287 ps
CPU time 0.6 seconds
Started Jul 31 04:44:59 PM PDT 24
Finished Jul 31 04:45:00 PM PDT 24
Peak memory 191708 kb
Host smart-36224bbc-cbb6-4fff-a8dd-230104888d65
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341486834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.1341486834
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.1842426693
Short name T568
Test name
Test status
Simulation time 705014645 ps
CPU time 2.63 seconds
Started Jul 31 04:45:07 PM PDT 24
Finished Jul 31 04:45:09 PM PDT 24
Peak memory 197516 kb
Host smart-6fd6bc9a-7b4f-4ba8-9af8-d39646dadf6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842426693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.1842426693
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3265461431
Short name T569
Test name
Test status
Simulation time 214333349 ps
CPU time 0.82 seconds
Started Jul 31 04:45:03 PM PDT 24
Finished Jul 31 04:45:04 PM PDT 24
Peak memory 193560 kb
Host smart-60e1343b-40b2-4d88-b5e0-2c83ef2a3312
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265461431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.3265461431
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3632239270
Short name T514
Test name
Test status
Simulation time 31726961 ps
CPU time 1.39 seconds
Started Jul 31 04:45:11 PM PDT 24
Finished Jul 31 04:45:12 PM PDT 24
Peak memory 197592 kb
Host smart-3527bfeb-dd45-4b8a-9253-24f579049457
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632239270 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.3632239270
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.3944758242
Short name T64
Test name
Test status
Simulation time 43063671 ps
CPU time 0.57 seconds
Started Jul 31 04:45:12 PM PDT 24
Finished Jul 31 04:45:13 PM PDT 24
Peak memory 182856 kb
Host smart-d0b33b7e-d5f9-4e41-ae76-7aa61ddad0d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944758242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.3944758242
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.3877360316
Short name T527
Test name
Test status
Simulation time 14050903 ps
CPU time 0.53 seconds
Started Jul 31 04:44:59 PM PDT 24
Finished Jul 31 04:45:00 PM PDT 24
Peak memory 182580 kb
Host smart-3844dc26-532e-4d95-8670-c8df784f28d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877360316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.3877360316
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.1488028405
Short name T71
Test name
Test status
Simulation time 21633213 ps
CPU time 0.82 seconds
Started Jul 31 04:44:53 PM PDT 24
Finished Jul 31 04:44:54 PM PDT 24
Peak memory 191676 kb
Host smart-1f138d34-089a-4c57-b9d1-f228bfd02c9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488028405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.1488028405
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.5567812
Short name T500
Test name
Test status
Simulation time 32445489 ps
CPU time 1 seconds
Started Jul 31 04:45:16 PM PDT 24
Finished Jul 31 04:45:17 PM PDT 24
Peak memory 196672 kb
Host smart-130c9932-2e72-4792-87fd-cc3cd705aea2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5567812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.5567812
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.2662421780
Short name T28
Test name
Test status
Simulation time 141258446 ps
CPU time 0.8 seconds
Started Jul 31 04:45:00 PM PDT 24
Finished Jul 31 04:45:01 PM PDT 24
Peak memory 183100 kb
Host smart-d4d09c66-c89e-497f-abd3-373857c37127
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662421780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.2662421780
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.3499030716
Short name T468
Test name
Test status
Simulation time 33652070 ps
CPU time 1.44 seconds
Started Jul 31 04:45:03 PM PDT 24
Finished Jul 31 04:45:10 PM PDT 24
Peak memory 197560 kb
Host smart-fe7e9c7d-cd50-4a4e-8321-d87bedca3640
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499030716 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.3499030716
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.2612781049
Short name T492
Test name
Test status
Simulation time 36807438 ps
CPU time 0.57 seconds
Started Jul 31 04:45:07 PM PDT 24
Finished Jul 31 04:45:08 PM PDT 24
Peak memory 182788 kb
Host smart-84193fd3-6fe3-45f3-bec9-30689d5cc1d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612781049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.2612781049
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.3945125202
Short name T531
Test name
Test status
Simulation time 42233525 ps
CPU time 0.52 seconds
Started Jul 31 04:45:15 PM PDT 24
Finished Jul 31 04:45:16 PM PDT 24
Peak memory 182480 kb
Host smart-c7e523de-555a-4445-aa65-ecbf20cc92fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945125202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.3945125202
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.2540914011
Short name T74
Test name
Test status
Simulation time 15946488 ps
CPU time 0.6 seconds
Started Jul 31 04:45:05 PM PDT 24
Finished Jul 31 04:45:06 PM PDT 24
Peak memory 191644 kb
Host smart-d05745b9-eabc-4dd4-be93-7c9867f35683
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540914011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.2540914011
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.1524408193
Short name T455
Test name
Test status
Simulation time 43913100 ps
CPU time 1.89 seconds
Started Jul 31 04:44:51 PM PDT 24
Finished Jul 31 04:44:54 PM PDT 24
Peak memory 197488 kb
Host smart-7bf116a0-df9f-4cf1-9007-a6c7dfc3d7d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524408193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.1524408193
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.2819376789
Short name T523
Test name
Test status
Simulation time 137932298 ps
CPU time 1.07 seconds
Started Jul 31 04:45:10 PM PDT 24
Finished Jul 31 04:45:11 PM PDT 24
Peak memory 195020 kb
Host smart-f2a2d42c-ed28-4f3b-9718-97d649f344c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819376789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.2819376789
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3401215216
Short name T530
Test name
Test status
Simulation time 49588020 ps
CPU time 0.62 seconds
Started Jul 31 04:44:57 PM PDT 24
Finished Jul 31 04:44:58 PM PDT 24
Peak memory 193640 kb
Host smart-9255951f-bfd6-4fea-a54b-9985594b1a41
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401215216 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.3401215216
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.2237312090
Short name T65
Test name
Test status
Simulation time 12823398 ps
CPU time 0.56 seconds
Started Jul 31 04:45:27 PM PDT 24
Finished Jul 31 04:45:28 PM PDT 24
Peak memory 182744 kb
Host smart-73e403dc-a225-4c10-82e0-2cc537a8211a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237312090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.2237312090
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.1325248874
Short name T577
Test name
Test status
Simulation time 14559447 ps
CPU time 0.55 seconds
Started Jul 31 04:45:08 PM PDT 24
Finished Jul 31 04:45:09 PM PDT 24
Peak memory 182104 kb
Host smart-70d9c45e-a29a-4feb-b430-b3fca8d8d8b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325248874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.1325248874
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.3274554662
Short name T485
Test name
Test status
Simulation time 36538324 ps
CPU time 0.79 seconds
Started Jul 31 04:45:33 PM PDT 24
Finished Jul 31 04:45:34 PM PDT 24
Peak memory 190940 kb
Host smart-3f5eee09-e500-4e96-ba8f-32542841c86a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274554662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.3274554662
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.890409780
Short name T488
Test name
Test status
Simulation time 271678052 ps
CPU time 1.69 seconds
Started Jul 31 04:45:07 PM PDT 24
Finished Jul 31 04:45:09 PM PDT 24
Peak memory 197404 kb
Host smart-14340c12-cf42-46d5-b5c4-d234560b2fa8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890409780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.890409780
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.2349346414
Short name T80
Test name
Test status
Simulation time 43189508 ps
CPU time 0.8 seconds
Started Jul 31 04:45:03 PM PDT 24
Finished Jul 31 04:45:04 PM PDT 24
Peak memory 183320 kb
Host smart-faa808ee-f23d-4672-bcdf-c7b81d5c020b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349346414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.2349346414
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.1662753816
Short name T502
Test name
Test status
Simulation time 66661680 ps
CPU time 0.65 seconds
Started Jul 31 04:45:12 PM PDT 24
Finished Jul 31 04:45:13 PM PDT 24
Peak memory 194272 kb
Host smart-6c2b1a5d-d27d-4d71-b74d-472e8749fc3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662753816 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.1662753816
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.922972207
Short name T516
Test name
Test status
Simulation time 35634221 ps
CPU time 0.59 seconds
Started Jul 31 04:44:51 PM PDT 24
Finished Jul 31 04:44:52 PM PDT 24
Peak memory 182780 kb
Host smart-82db2e21-7ab5-40ea-ab8d-401d9de6366d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922972207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.922972207
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.2883115436
Short name T477
Test name
Test status
Simulation time 27394634 ps
CPU time 0.55 seconds
Started Jul 31 04:45:21 PM PDT 24
Finished Jul 31 04:45:22 PM PDT 24
Peak memory 182012 kb
Host smart-1d0904e5-efec-44f1-a521-66180e6210e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883115436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.2883115436
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.676335570
Short name T69
Test name
Test status
Simulation time 55955482 ps
CPU time 0.59 seconds
Started Jul 31 04:45:00 PM PDT 24
Finished Jul 31 04:45:01 PM PDT 24
Peak memory 191992 kb
Host smart-f78a9d69-d4ae-4da7-b3b8-d3c6dde1a122
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676335570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_tim
er_same_csr_outstanding.676335570
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.1437782040
Short name T459
Test name
Test status
Simulation time 26070467 ps
CPU time 1.33 seconds
Started Jul 31 04:45:04 PM PDT 24
Finished Jul 31 04:45:06 PM PDT 24
Peak memory 197564 kb
Host smart-4afd9162-7773-414d-bd34-5d7d2c85a8dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437782040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.1437782040
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.2242262280
Short name T83
Test name
Test status
Simulation time 169358287 ps
CPU time 1.35 seconds
Started Jul 31 04:44:56 PM PDT 24
Finished Jul 31 04:44:57 PM PDT 24
Peak memory 195328 kb
Host smart-1281e2ff-d4b5-4e8b-b6e1-80a5941ee830
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242262280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.2242262280
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.2085384740
Short name T213
Test name
Test status
Simulation time 60348415779 ps
CPU time 29.78 seconds
Started Jul 31 04:24:59 PM PDT 24
Finished Jul 31 04:25:29 PM PDT 24
Peak memory 183224 kb
Host smart-c51bccb5-bfa1-4e5e-b8ee-11c762915f2b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085384740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.2085384740
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.2474894630
Short name T451
Test name
Test status
Simulation time 112812676105 ps
CPU time 82.41 seconds
Started Jul 31 04:20:52 PM PDT 24
Finished Jul 31 04:22:14 PM PDT 24
Peak memory 182988 kb
Host smart-f9e7cdfb-02b2-42ad-86d7-10ddb30fbb46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474894630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.2474894630
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.1993951447
Short name T124
Test name
Test status
Simulation time 38609727493 ps
CPU time 35.09 seconds
Started Jul 31 04:25:00 PM PDT 24
Finished Jul 31 04:25:35 PM PDT 24
Peak memory 183232 kb
Host smart-9b769e8f-c69e-4a49-bdc0-7cbbf8346ef1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993951447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.1993951447
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.1872277596
Short name T373
Test name
Test status
Simulation time 147853912510 ps
CPU time 209.42 seconds
Started Jul 31 04:24:54 PM PDT 24
Finished Jul 31 04:28:24 PM PDT 24
Peak memory 183280 kb
Host smart-f52b2f2c-ded8-4e9b-a672-0dfc7217c23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872277596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.1872277596
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.1296967913
Short name T274
Test name
Test status
Simulation time 221805169551 ps
CPU time 874.58 seconds
Started Jul 31 04:24:20 PM PDT 24
Finished Jul 31 04:38:55 PM PDT 24
Peak memory 191452 kb
Host smart-67733e99-14da-4e89-9a0b-f8bc7c93b53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296967913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.1296967913
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.128839548
Short name T15
Test name
Test status
Simulation time 72908762 ps
CPU time 0.9 seconds
Started Jul 31 04:24:41 PM PDT 24
Finished Jul 31 04:24:42 PM PDT 24
Peak memory 212016 kb
Host smart-084baba1-1333-41de-91a8-363b16a51f7c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128839548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.128839548
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all_with_rand_reset.2103814781
Short name T34
Test name
Test status
Simulation time 59485888999 ps
CPU time 454.94 seconds
Started Jul 31 04:23:47 PM PDT 24
Finished Jul 31 04:31:23 PM PDT 24
Peak memory 206100 kb
Host smart-82ae4463-03bc-42ad-9710-c35e6abd8c0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103814781 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all_with_rand_reset.2103814781
Directory /workspace/1.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.4269662856
Short name T445
Test name
Test status
Simulation time 5172176227 ps
CPU time 8.38 seconds
Started Jul 31 04:27:33 PM PDT 24
Finished Jul 31 04:27:42 PM PDT 24
Peak memory 183244 kb
Host smart-de72d488-a552-498a-9012-ea0976c9cfb2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269662856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.4269662856
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.4098752309
Short name T388
Test name
Test status
Simulation time 193808281843 ps
CPU time 217.31 seconds
Started Jul 31 04:27:28 PM PDT 24
Finished Jul 31 04:31:06 PM PDT 24
Peak memory 183264 kb
Host smart-57640c0e-9ab4-405c-8a5a-919dc15db8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098752309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.4098752309
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.1559580885
Short name T448
Test name
Test status
Simulation time 406528594 ps
CPU time 0.7 seconds
Started Jul 31 04:27:28 PM PDT 24
Finished Jul 31 04:27:29 PM PDT 24
Peak memory 191720 kb
Host smart-998bbfe4-7a18-4343-a1af-b82d85e00629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559580885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.1559580885
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/100.rv_timer_random.3572568536
Short name T304
Test name
Test status
Simulation time 20185883245 ps
CPU time 42.41 seconds
Started Jul 31 04:28:40 PM PDT 24
Finished Jul 31 04:29:23 PM PDT 24
Peak memory 183216 kb
Host smart-ad6d1195-f9ea-4acd-8ad0-ba7a4f897c01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572568536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.3572568536
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.3877609920
Short name T271
Test name
Test status
Simulation time 382705562665 ps
CPU time 2236.6 seconds
Started Jul 31 04:28:39 PM PDT 24
Finished Jul 31 05:05:56 PM PDT 24
Peak memory 191456 kb
Host smart-8edc2a3e-1bc9-45fa-90fe-80caee65b8bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877609920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.3877609920
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.3188771010
Short name T107
Test name
Test status
Simulation time 27286248313 ps
CPU time 38.17 seconds
Started Jul 31 04:28:39 PM PDT 24
Finished Jul 31 04:29:17 PM PDT 24
Peak memory 183212 kb
Host smart-a783ed4c-6e79-4568-bcbd-e0c21efe6ad9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188771010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.3188771010
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.670180904
Short name T357
Test name
Test status
Simulation time 733832242933 ps
CPU time 410.66 seconds
Started Jul 31 04:28:40 PM PDT 24
Finished Jul 31 04:35:30 PM PDT 24
Peak memory 191424 kb
Host smart-961bd354-9e5e-40ff-8b6d-b2a276c0255f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670180904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.670180904
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.1399394594
Short name T320
Test name
Test status
Simulation time 829409615 ps
CPU time 1.24 seconds
Started Jul 31 04:28:39 PM PDT 24
Finished Jul 31 04:28:41 PM PDT 24
Peak memory 182988 kb
Host smart-076c09db-ec6b-4528-97c1-4e6bdec6131c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399394594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.1399394594
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.2084408630
Short name T163
Test name
Test status
Simulation time 91878644776 ps
CPU time 218.57 seconds
Started Jul 31 04:28:40 PM PDT 24
Finished Jul 31 04:32:19 PM PDT 24
Peak memory 191388 kb
Host smart-1e5ade4b-eba4-429e-9f2e-1adc138b45f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084408630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.2084408630
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.1066034291
Short name T332
Test name
Test status
Simulation time 71112649613 ps
CPU time 106.25 seconds
Started Jul 31 04:28:38 PM PDT 24
Finished Jul 31 04:30:25 PM PDT 24
Peak memory 191488 kb
Host smart-e62dee85-0c2d-41fb-a89f-332c42730dbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066034291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.1066034291
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.3646787776
Short name T397
Test name
Test status
Simulation time 2754050198 ps
CPU time 4.79 seconds
Started Jul 31 04:27:29 PM PDT 24
Finished Jul 31 04:27:34 PM PDT 24
Peak memory 183204 kb
Host smart-52d14156-8aeb-45bc-8aca-a44daa19034d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646787776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.3646787776
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.2672678621
Short name T415
Test name
Test status
Simulation time 49783076865 ps
CPU time 63.91 seconds
Started Jul 31 04:27:28 PM PDT 24
Finished Jul 31 04:28:32 PM PDT 24
Peak memory 183228 kb
Host smart-03bff00e-d04d-4984-b396-05d33f09d15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672678621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.2672678621
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/110.rv_timer_random.602639238
Short name T335
Test name
Test status
Simulation time 700644673550 ps
CPU time 265.15 seconds
Started Jul 31 04:28:43 PM PDT 24
Finished Jul 31 04:33:09 PM PDT 24
Peak memory 191468 kb
Host smart-bbe310e4-8351-41c9-9ad1-54b3c1e5bfd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602639238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.602639238
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.3162342115
Short name T250
Test name
Test status
Simulation time 162985305078 ps
CPU time 337.39 seconds
Started Jul 31 04:28:44 PM PDT 24
Finished Jul 31 04:34:22 PM PDT 24
Peak memory 191400 kb
Host smart-ebbab8fa-1082-40b4-bb9a-d17738aca2f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162342115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.3162342115
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.362025940
Short name T260
Test name
Test status
Simulation time 153101910389 ps
CPU time 59.31 seconds
Started Jul 31 04:28:44 PM PDT 24
Finished Jul 31 04:29:43 PM PDT 24
Peak memory 191496 kb
Host smart-8ee50572-8e59-4729-ba88-fb270e36dbb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362025940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.362025940
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.2068648482
Short name T346
Test name
Test status
Simulation time 71997428228 ps
CPU time 126.3 seconds
Started Jul 31 04:29:02 PM PDT 24
Finished Jul 31 04:31:08 PM PDT 24
Peak memory 194012 kb
Host smart-98ccd10a-73dd-460f-b7e1-ebae29e9c5c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068648482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.2068648482
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.4233723097
Short name T307
Test name
Test status
Simulation time 73133395797 ps
CPU time 247.15 seconds
Started Jul 31 04:28:44 PM PDT 24
Finished Jul 31 04:32:51 PM PDT 24
Peak memory 191456 kb
Host smart-a62d403f-c5cb-4337-bdb0-7a3bfe7a17ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233723097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.4233723097
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.179424065
Short name T293
Test name
Test status
Simulation time 56838289735 ps
CPU time 89.03 seconds
Started Jul 31 04:28:48 PM PDT 24
Finished Jul 31 04:30:17 PM PDT 24
Peak memory 191448 kb
Host smart-d6d127e6-3f46-436c-8275-f14110ed1717
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179424065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.179424065
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.3485622082
Short name T117
Test name
Test status
Simulation time 256626960901 ps
CPU time 472.56 seconds
Started Jul 31 04:28:46 PM PDT 24
Finished Jul 31 04:36:39 PM PDT 24
Peak memory 191404 kb
Host smart-c6b32498-f536-4bf6-a325-8aeea1faea21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485622082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.3485622082
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.2735880114
Short name T449
Test name
Test status
Simulation time 427571674374 ps
CPU time 259.95 seconds
Started Jul 31 04:28:52 PM PDT 24
Finished Jul 31 04:33:12 PM PDT 24
Peak memory 191504 kb
Host smart-2be5f8a2-df55-4234-a04f-f911aef814dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735880114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.2735880114
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.872332331
Short name T383
Test name
Test status
Simulation time 108973436967 ps
CPU time 44.71 seconds
Started Jul 31 04:27:34 PM PDT 24
Finished Jul 31 04:28:19 PM PDT 24
Peak memory 183016 kb
Host smart-476f0a90-9a66-4412-8ec5-52a697eb8367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872332331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.872332331
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.2432079306
Short name T256
Test name
Test status
Simulation time 28318655963 ps
CPU time 14.41 seconds
Started Jul 31 04:27:31 PM PDT 24
Finished Jul 31 04:27:46 PM PDT 24
Peak memory 183228 kb
Host smart-e70d0397-bc3d-48f3-b4d4-1bc23aa4170b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432079306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.2432079306
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.852847233
Short name T180
Test name
Test status
Simulation time 1011209892398 ps
CPU time 1977.03 seconds
Started Jul 31 04:27:31 PM PDT 24
Finished Jul 31 05:00:29 PM PDT 24
Peak memory 196012 kb
Host smart-e9c080fa-cff8-47f1-8ab3-ef139169232e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852847233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all.
852847233
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/120.rv_timer_random.26139554
Short name T313
Test name
Test status
Simulation time 26828535810 ps
CPU time 45.57 seconds
Started Jul 31 04:28:48 PM PDT 24
Finished Jul 31 04:29:34 PM PDT 24
Peak memory 183256 kb
Host smart-1e61cfbe-cac9-4f7b-8c02-3aece25bbf35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26139554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.26139554
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.1751071288
Short name T95
Test name
Test status
Simulation time 5903921806 ps
CPU time 8.48 seconds
Started Jul 31 04:28:50 PM PDT 24
Finished Jul 31 04:28:58 PM PDT 24
Peak memory 183032 kb
Host smart-20473de2-9047-404d-961b-f414b0f328ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751071288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.1751071288
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.3730614226
Short name T334
Test name
Test status
Simulation time 53108143560 ps
CPU time 88.99 seconds
Started Jul 31 04:28:46 PM PDT 24
Finished Jul 31 04:30:16 PM PDT 24
Peak memory 191484 kb
Host smart-3882eb80-9a6d-4576-900d-3010d850dd26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730614226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.3730614226
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.386394153
Short name T185
Test name
Test status
Simulation time 319190909541 ps
CPU time 1015.15 seconds
Started Jul 31 04:28:47 PM PDT 24
Finished Jul 31 04:45:42 PM PDT 24
Peak memory 191476 kb
Host smart-005e8807-6b65-4033-8589-adfc135193d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386394153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.386394153
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.1534689972
Short name T264
Test name
Test status
Simulation time 661721423255 ps
CPU time 605.92 seconds
Started Jul 31 04:29:01 PM PDT 24
Finished Jul 31 04:39:07 PM PDT 24
Peak memory 195668 kb
Host smart-25e8cd17-5352-4f9c-ada6-b15575c967e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534689972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.1534689972
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.3698616596
Short name T96
Test name
Test status
Simulation time 205602910247 ps
CPU time 29.07 seconds
Started Jul 31 04:28:50 PM PDT 24
Finished Jul 31 04:29:19 PM PDT 24
Peak memory 183264 kb
Host smart-9dcd5a3c-b5cb-450b-acf9-4fbebf4e7dc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698616596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.3698616596
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.3474944753
Short name T9
Test name
Test status
Simulation time 68600428882 ps
CPU time 121.69 seconds
Started Jul 31 04:28:59 PM PDT 24
Finished Jul 31 04:31:01 PM PDT 24
Peak memory 191452 kb
Host smart-08c143d9-a75f-4936-aca1-b18a8f32fc6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474944753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.3474944753
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.3289369384
Short name T287
Test name
Test status
Simulation time 111193193062 ps
CPU time 182.24 seconds
Started Jul 31 04:28:51 PM PDT 24
Finished Jul 31 04:31:53 PM PDT 24
Peak memory 191444 kb
Host smart-b6df308a-0f0f-459b-9e40-ce8a5c27e473
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289369384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.3289369384
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.1119991168
Short name T282
Test name
Test status
Simulation time 85893013915 ps
CPU time 141.36 seconds
Started Jul 31 04:27:36 PM PDT 24
Finished Jul 31 04:29:57 PM PDT 24
Peak memory 183244 kb
Host smart-49e17556-3b97-41e5-9203-006fb22f01bf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119991168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.1119991168
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.2503681915
Short name T411
Test name
Test status
Simulation time 98247045138 ps
CPU time 146.65 seconds
Started Jul 31 04:27:37 PM PDT 24
Finished Jul 31 04:30:04 PM PDT 24
Peak memory 183220 kb
Host smart-57e9f55c-5021-45c3-8628-43f1bbb4e150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503681915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.2503681915
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.607923462
Short name T116
Test name
Test status
Simulation time 14098247612 ps
CPU time 82.83 seconds
Started Jul 31 04:27:37 PM PDT 24
Finished Jul 31 04:29:00 PM PDT 24
Peak memory 183260 kb
Host smart-6d6b4406-4d4f-41a2-b36a-b05741c62db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607923462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.607923462
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.636210319
Short name T133
Test name
Test status
Simulation time 866000504972 ps
CPU time 563.92 seconds
Started Jul 31 04:27:35 PM PDT 24
Finished Jul 31 04:36:59 PM PDT 24
Peak memory 191532 kb
Host smart-62e49a8e-d110-4172-b2eb-8310b7fba7f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636210319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all.
636210319
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/130.rv_timer_random.1502939941
Short name T319
Test name
Test status
Simulation time 270618098930 ps
CPU time 76.91 seconds
Started Jul 31 04:28:50 PM PDT 24
Finished Jul 31 04:30:07 PM PDT 24
Peak memory 183284 kb
Host smart-80ea3ad9-e433-4efc-be85-cd69dca438c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502939941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.1502939941
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.4264945026
Short name T246
Test name
Test status
Simulation time 128289025488 ps
CPU time 109.36 seconds
Started Jul 31 04:28:55 PM PDT 24
Finished Jul 31 04:30:45 PM PDT 24
Peak memory 191452 kb
Host smart-63933c94-58b5-4762-970f-a0536e8a24be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264945026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.4264945026
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.4121600758
Short name T108
Test name
Test status
Simulation time 216335587715 ps
CPU time 202.06 seconds
Started Jul 31 04:28:51 PM PDT 24
Finished Jul 31 04:32:13 PM PDT 24
Peak memory 191428 kb
Host smart-30d44ebd-cc3b-4c4a-bd60-3f120eda6b79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121600758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.4121600758
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.2240210605
Short name T93
Test name
Test status
Simulation time 153280086329 ps
CPU time 2889.76 seconds
Started Jul 31 04:28:56 PM PDT 24
Finished Jul 31 05:17:06 PM PDT 24
Peak memory 191444 kb
Host smart-4612cf76-7499-4dab-baca-1480d8e2caca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240210605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.2240210605
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.818214882
Short name T265
Test name
Test status
Simulation time 294573456773 ps
CPU time 185.51 seconds
Started Jul 31 04:28:52 PM PDT 24
Finished Jul 31 04:31:57 PM PDT 24
Peak memory 191516 kb
Host smart-3969b951-1ba1-4baf-970f-77346024f4fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818214882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.818214882
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.3605485504
Short name T331
Test name
Test status
Simulation time 10258329898 ps
CPU time 12.13 seconds
Started Jul 31 04:28:56 PM PDT 24
Finished Jul 31 04:29:08 PM PDT 24
Peak memory 191452 kb
Host smart-60cd1740-4006-4b38-8bed-5de8e907f091
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605485504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.3605485504
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.1646725982
Short name T366
Test name
Test status
Simulation time 287003781629 ps
CPU time 136.45 seconds
Started Jul 31 04:27:35 PM PDT 24
Finished Jul 31 04:29:52 PM PDT 24
Peak memory 183260 kb
Host smart-98d38750-a8ea-43f5-9663-875ef6f8e680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646725982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.1646725982
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.3349543055
Short name T228
Test name
Test status
Simulation time 136824416496 ps
CPU time 210.03 seconds
Started Jul 31 04:27:35 PM PDT 24
Finished Jul 31 04:31:06 PM PDT 24
Peak memory 191480 kb
Host smart-16d56c40-ab62-445e-9c51-55b7f7e64647
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349543055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.3349543055
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.2243805275
Short name T394
Test name
Test status
Simulation time 878959396 ps
CPU time 1.35 seconds
Started Jul 31 04:27:37 PM PDT 24
Finished Jul 31 04:27:39 PM PDT 24
Peak memory 191320 kb
Host smart-b0211141-85ad-45f0-8d60-6e2b91526cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243805275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.2243805275
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/140.rv_timer_random.3230966436
Short name T258
Test name
Test status
Simulation time 115920764682 ps
CPU time 56.09 seconds
Started Jul 31 04:28:55 PM PDT 24
Finished Jul 31 04:29:51 PM PDT 24
Peak memory 183300 kb
Host smart-f87dbb7d-a323-4473-a56c-86ca709fd7d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230966436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.3230966436
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.1735010595
Short name T433
Test name
Test status
Simulation time 90677525090 ps
CPU time 912.48 seconds
Started Jul 31 04:28:53 PM PDT 24
Finished Jul 31 04:44:06 PM PDT 24
Peak memory 183252 kb
Host smart-42c425e9-3318-44ad-a42c-f4c081497205
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735010595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.1735010595
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.4101895757
Short name T111
Test name
Test status
Simulation time 126772041964 ps
CPU time 72.18 seconds
Started Jul 31 04:28:52 PM PDT 24
Finished Jul 31 04:30:04 PM PDT 24
Peak memory 191432 kb
Host smart-e672dcb9-f04f-4d7c-a7a7-51b5c68c2e14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101895757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.4101895757
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.618064304
Short name T362
Test name
Test status
Simulation time 404861058092 ps
CPU time 165.3 seconds
Started Jul 31 04:28:59 PM PDT 24
Finished Jul 31 04:31:44 PM PDT 24
Peak memory 191444 kb
Host smart-95276a2e-f771-4a49-b1b1-9e11189f1c7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618064304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.618064304
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.294448369
Short name T22
Test name
Test status
Simulation time 142909546012 ps
CPU time 58.89 seconds
Started Jul 31 04:28:55 PM PDT 24
Finished Jul 31 04:29:54 PM PDT 24
Peak memory 191492 kb
Host smart-df6b44ae-727e-48f9-95ba-ca756bd240b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294448369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.294448369
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.3994482242
Short name T345
Test name
Test status
Simulation time 435794675260 ps
CPU time 215 seconds
Started Jul 31 04:29:12 PM PDT 24
Finished Jul 31 04:32:47 PM PDT 24
Peak memory 191452 kb
Host smart-ce1007e6-b361-4c7a-aeea-8833e5adc27c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994482242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.3994482242
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.147472008
Short name T422
Test name
Test status
Simulation time 86690506754 ps
CPU time 75.68 seconds
Started Jul 31 04:28:56 PM PDT 24
Finished Jul 31 04:30:12 PM PDT 24
Peak memory 183284 kb
Host smart-b01358f3-bcbb-4aff-9c2d-d72ccf68c1d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147472008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.147472008
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.1709343579
Short name T349
Test name
Test status
Simulation time 5256857142 ps
CPU time 8.24 seconds
Started Jul 31 04:28:58 PM PDT 24
Finished Jul 31 04:29:07 PM PDT 24
Peak memory 183220 kb
Host smart-60ba18b9-7b74-47c1-8da4-e0d31db418d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709343579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.1709343579
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.3467646039
Short name T315
Test name
Test status
Simulation time 140238471651 ps
CPU time 237.59 seconds
Started Jul 31 04:28:56 PM PDT 24
Finished Jul 31 04:32:53 PM PDT 24
Peak memory 191408 kb
Host smart-7e622520-717b-478f-a9a1-d7088e4214d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467646039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.3467646039
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.3114482369
Short name T144
Test name
Test status
Simulation time 266947201162 ps
CPU time 131.71 seconds
Started Jul 31 04:27:35 PM PDT 24
Finished Jul 31 04:29:47 PM PDT 24
Peak memory 183264 kb
Host smart-ecb6328b-dd4f-4993-9162-91b06a3f300c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114482369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.3114482369
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.3884820029
Short name T410
Test name
Test status
Simulation time 24419036848 ps
CPU time 18.4 seconds
Started Jul 31 04:27:36 PM PDT 24
Finished Jul 31 04:27:55 PM PDT 24
Peak memory 183296 kb
Host smart-6acb5e74-ea1f-4603-9b24-54c071d29472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884820029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.3884820029
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.1695846333
Short name T24
Test name
Test status
Simulation time 275619456656 ps
CPU time 169.04 seconds
Started Jul 31 04:27:37 PM PDT 24
Finished Jul 31 04:30:27 PM PDT 24
Peak memory 191476 kb
Host smart-382c6964-83be-4b4f-9552-0bf9224253aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695846333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.1695846333
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.1641933022
Short name T396
Test name
Test status
Simulation time 204358857 ps
CPU time 2.01 seconds
Started Jul 31 04:27:35 PM PDT 24
Finished Jul 31 04:27:37 PM PDT 24
Peak memory 183248 kb
Host smart-83c0cdeb-aa9a-48d1-a60d-0b8ed814ba58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641933022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.1641933022
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.402162169
Short name T36
Test name
Test status
Simulation time 86313521542 ps
CPU time 435.9 seconds
Started Jul 31 04:27:36 PM PDT 24
Finished Jul 31 04:34:52 PM PDT 24
Peak memory 206212 kb
Host smart-9aae5509-ffb3-4d88-a957-e262dabb4953
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402162169 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all_with_rand_reset.402162169
Directory /workspace/15.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.rv_timer_random.358654569
Short name T312
Test name
Test status
Simulation time 188873529050 ps
CPU time 1053.53 seconds
Started Jul 31 04:29:41 PM PDT 24
Finished Jul 31 04:47:15 PM PDT 24
Peak memory 191452 kb
Host smart-18747618-9604-4232-8f13-ed70730792e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358654569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.358654569
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.2043647021
Short name T205
Test name
Test status
Simulation time 85869311131 ps
CPU time 123.72 seconds
Started Jul 31 04:28:59 PM PDT 24
Finished Jul 31 04:31:02 PM PDT 24
Peak memory 191452 kb
Host smart-e02afac7-23e7-4efa-b7da-fcdbe0a581e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043647021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.2043647021
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.1382503322
Short name T314
Test name
Test status
Simulation time 71120393704 ps
CPU time 16.84 seconds
Started Jul 31 04:28:55 PM PDT 24
Finished Jul 31 04:29:12 PM PDT 24
Peak memory 183284 kb
Host smart-31682748-67f3-40f5-91ce-96cd02ec1af5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382503322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.1382503322
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.355980947
Short name T167
Test name
Test status
Simulation time 319455362171 ps
CPU time 1587.77 seconds
Started Jul 31 04:28:56 PM PDT 24
Finished Jul 31 04:55:24 PM PDT 24
Peak memory 191484 kb
Host smart-e9664681-b147-4769-be1f-c4c7b11b8dc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355980947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.355980947
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.2539924069
Short name T270
Test name
Test status
Simulation time 108238680648 ps
CPU time 148.71 seconds
Started Jul 31 04:28:56 PM PDT 24
Finished Jul 31 04:31:25 PM PDT 24
Peak memory 194024 kb
Host smart-18145204-4d11-4129-b668-ef5c4e9de05b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539924069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.2539924069
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.2782361328
Short name T268
Test name
Test status
Simulation time 39052395290 ps
CPU time 36 seconds
Started Jul 31 04:29:42 PM PDT 24
Finished Jul 31 04:30:18 PM PDT 24
Peak memory 183268 kb
Host smart-9d06bcb7-af3b-44ec-ade1-17026ac57900
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782361328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.2782361328
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.2388060730
Short name T306
Test name
Test status
Simulation time 497341760306 ps
CPU time 257.22 seconds
Started Jul 31 04:28:59 PM PDT 24
Finished Jul 31 04:33:16 PM PDT 24
Peak memory 191444 kb
Host smart-b9873fea-f7ff-4304-8a59-2ef9a7c4e968
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388060730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.2388060730
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.2258347485
Short name T85
Test name
Test status
Simulation time 37491923909 ps
CPU time 35.46 seconds
Started Jul 31 04:27:37 PM PDT 24
Finished Jul 31 04:28:12 PM PDT 24
Peak memory 183260 kb
Host smart-31eee792-3a8b-46d0-ba83-6211db8383b5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258347485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.2258347485
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.392182970
Short name T401
Test name
Test status
Simulation time 114195408483 ps
CPU time 173.37 seconds
Started Jul 31 04:27:36 PM PDT 24
Finished Jul 31 04:30:29 PM PDT 24
Peak memory 183296 kb
Host smart-860e1689-e83c-4af8-8833-800f1d04fd27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392182970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.392182970
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.3680254612
Short name T408
Test name
Test status
Simulation time 472899542 ps
CPU time 1.33 seconds
Started Jul 31 04:27:35 PM PDT 24
Finished Jul 31 04:27:36 PM PDT 24
Peak memory 183212 kb
Host smart-c8be9812-7f45-4584-bea8-6a9616465d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680254612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.3680254612
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.668212667
Short name T141
Test name
Test status
Simulation time 2158121772990 ps
CPU time 940.21 seconds
Started Jul 31 04:27:37 PM PDT 24
Finished Jul 31 04:43:17 PM PDT 24
Peak memory 191448 kb
Host smart-ff29ff12-ad9d-48a2-9947-21c1b636c245
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668212667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all.
668212667
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/160.rv_timer_random.4125479405
Short name T444
Test name
Test status
Simulation time 104957772051 ps
CPU time 171.12 seconds
Started Jul 31 04:28:59 PM PDT 24
Finished Jul 31 04:31:50 PM PDT 24
Peak memory 191452 kb
Host smart-bb03c779-176c-4e00-9c1b-fad514dd3af5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125479405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.4125479405
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.1153919710
Short name T20
Test name
Test status
Simulation time 169969508896 ps
CPU time 216.48 seconds
Started Jul 31 04:29:01 PM PDT 24
Finished Jul 31 04:32:38 PM PDT 24
Peak memory 191452 kb
Host smart-d81ce990-a7fc-47f3-82c1-9a32f71b5dfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153919710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.1153919710
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.1962100158
Short name T338
Test name
Test status
Simulation time 25714084992 ps
CPU time 39.5 seconds
Started Jul 31 04:29:02 PM PDT 24
Finished Jul 31 04:29:41 PM PDT 24
Peak memory 183260 kb
Host smart-c5c81d21-e517-42ec-9322-78560f211c22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962100158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.1962100158
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.1016406536
Short name T280
Test name
Test status
Simulation time 170438993451 ps
CPU time 132.69 seconds
Started Jul 31 04:29:01 PM PDT 24
Finished Jul 31 04:31:13 PM PDT 24
Peak memory 191500 kb
Host smart-88ef869b-c487-47ec-819d-060a7baca75b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016406536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.1016406536
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.226226622
Short name T340
Test name
Test status
Simulation time 425883917123 ps
CPU time 185.71 seconds
Started Jul 31 04:29:10 PM PDT 24
Finished Jul 31 04:32:15 PM PDT 24
Peak memory 191444 kb
Host smart-1366a93a-1973-4da1-bf2a-d586a02e9c3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226226622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.226226622
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.1590556780
Short name T209
Test name
Test status
Simulation time 165956263051 ps
CPU time 390.66 seconds
Started Jul 31 04:29:02 PM PDT 24
Finished Jul 31 04:35:33 PM PDT 24
Peak memory 192748 kb
Host smart-245c6712-d768-46c8-8692-c73914f3e936
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590556780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.1590556780
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.584850898
Short name T353
Test name
Test status
Simulation time 64103373147 ps
CPU time 26.37 seconds
Started Jul 31 04:27:36 PM PDT 24
Finished Jul 31 04:28:03 PM PDT 24
Peak memory 183276 kb
Host smart-9e8e5f46-d077-491a-8f84-6d9e04c6a124
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584850898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.rv_timer_cfg_update_on_fly.584850898
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.3156610285
Short name T404
Test name
Test status
Simulation time 719337872120 ps
CPU time 274.61 seconds
Started Jul 31 04:27:40 PM PDT 24
Finished Jul 31 04:32:15 PM PDT 24
Peak memory 183240 kb
Host smart-572b6d77-096f-4c10-b9c3-262966df8841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156610285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.3156610285
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.1368146510
Short name T129
Test name
Test status
Simulation time 33021056670 ps
CPU time 33.11 seconds
Started Jul 31 04:27:36 PM PDT 24
Finished Jul 31 04:28:09 PM PDT 24
Peak memory 183268 kb
Host smart-e4d1be2a-c071-45e2-a9a8-6abd95517b9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368146510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.1368146510
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.1363492279
Short name T281
Test name
Test status
Simulation time 30223928086 ps
CPU time 49.4 seconds
Started Jul 31 04:27:35 PM PDT 24
Finished Jul 31 04:28:24 PM PDT 24
Peak memory 183368 kb
Host smart-00a2178f-93ed-45ff-b970-999db0d1c088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363492279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.1363492279
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.3645238085
Short name T347
Test name
Test status
Simulation time 190282129046 ps
CPU time 172.8 seconds
Started Jul 31 04:29:02 PM PDT 24
Finished Jul 31 04:31:55 PM PDT 24
Peak memory 193772 kb
Host smart-2abb5c08-c760-44aa-89c1-881a7c6e45be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645238085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.3645238085
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.4063546230
Short name T118
Test name
Test status
Simulation time 522955407740 ps
CPU time 376.56 seconds
Started Jul 31 04:29:03 PM PDT 24
Finished Jul 31 04:35:19 PM PDT 24
Peak memory 191480 kb
Host smart-08bc6b5f-1728-407a-aecf-48c77763c6a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063546230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.4063546230
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.2593257928
Short name T413
Test name
Test status
Simulation time 18039912297 ps
CPU time 30.68 seconds
Started Jul 31 04:29:03 PM PDT 24
Finished Jul 31 04:29:33 PM PDT 24
Peak memory 183228 kb
Host smart-b11a972c-025c-4315-afaa-8108a3f0a2bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593257928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.2593257928
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.687909571
Short name T40
Test name
Test status
Simulation time 24035000430 ps
CPU time 37.5 seconds
Started Jul 31 04:29:02 PM PDT 24
Finished Jul 31 04:29:40 PM PDT 24
Peak memory 183068 kb
Host smart-3bf79897-c823-4b30-80a5-9b35d9ee5615
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687909571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.687909571
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.769747517
Short name T139
Test name
Test status
Simulation time 764392543036 ps
CPU time 996.05 seconds
Started Jul 31 04:29:04 PM PDT 24
Finished Jul 31 04:45:40 PM PDT 24
Peak memory 191488 kb
Host smart-1de46224-04bb-468f-b5d1-b37b587fc74e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769747517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.769747517
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.971627654
Short name T103
Test name
Test status
Simulation time 71634153486 ps
CPU time 2135.35 seconds
Started Jul 31 04:29:07 PM PDT 24
Finished Jul 31 05:04:43 PM PDT 24
Peak memory 191464 kb
Host smart-653f0bea-cea6-465a-ae84-8646abbc467f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971627654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.971627654
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.282473294
Short name T106
Test name
Test status
Simulation time 96251296584 ps
CPU time 131.36 seconds
Started Jul 31 04:29:09 PM PDT 24
Finished Jul 31 04:31:20 PM PDT 24
Peak memory 191816 kb
Host smart-a70c3a61-b4f1-4f29-a78b-427f90044411
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282473294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.282473294
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.2165362106
Short name T187
Test name
Test status
Simulation time 10340553234 ps
CPU time 16.1 seconds
Started Jul 31 04:29:10 PM PDT 24
Finished Jul 31 04:29:26 PM PDT 24
Peak memory 183248 kb
Host smart-2ed42607-d28c-45ec-bd58-d5b1e1eeae78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165362106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.2165362106
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.1443066713
Short name T387
Test name
Test status
Simulation time 34402904252 ps
CPU time 53.97 seconds
Started Jul 31 04:27:41 PM PDT 24
Finished Jul 31 04:28:35 PM PDT 24
Peak memory 183248 kb
Host smart-d97b46df-7f5d-4fca-a770-fa50c19eabb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443066713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.1443066713
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.333006798
Short name T311
Test name
Test status
Simulation time 309315806683 ps
CPU time 160.54 seconds
Started Jul 31 04:27:45 PM PDT 24
Finished Jul 31 04:30:26 PM PDT 24
Peak memory 191444 kb
Host smart-c99f46dc-ce12-479b-848b-77aac21092bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333006798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.333006798
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.1339666396
Short name T195
Test name
Test status
Simulation time 94638298421 ps
CPU time 148.83 seconds
Started Jul 31 04:27:41 PM PDT 24
Finished Jul 31 04:30:10 PM PDT 24
Peak memory 191476 kb
Host smart-0273af7e-b459-4ccb-8091-29b8635c49ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339666396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.1339666396
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.3093879380
Short name T203
Test name
Test status
Simulation time 447837122602 ps
CPU time 1123.26 seconds
Started Jul 31 04:27:41 PM PDT 24
Finished Jul 31 04:46:25 PM PDT 24
Peak memory 191492 kb
Host smart-4230af15-c630-4908-b413-aad483976818
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093879380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.3093879380
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/180.rv_timer_random.847550811
Short name T210
Test name
Test status
Simulation time 20617155257 ps
CPU time 112.54 seconds
Started Jul 31 04:29:08 PM PDT 24
Finished Jul 31 04:31:01 PM PDT 24
Peak memory 183232 kb
Host smart-a1748c3f-eaec-43b4-a6ee-d93c175fd560
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847550811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.847550811
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.3728565533
Short name T416
Test name
Test status
Simulation time 142295962109 ps
CPU time 310.5 seconds
Started Jul 31 04:29:07 PM PDT 24
Finished Jul 31 04:34:18 PM PDT 24
Peak memory 191496 kb
Host smart-fe788239-5585-47dc-ba32-0351dfe20007
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728565533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.3728565533
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.2742433866
Short name T2
Test name
Test status
Simulation time 281975573211 ps
CPU time 689.66 seconds
Started Jul 31 04:29:07 PM PDT 24
Finished Jul 31 04:40:37 PM PDT 24
Peak memory 191424 kb
Host smart-0b8bb09d-d9f7-4f88-a1ef-8b34020b9c33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742433866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.2742433866
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.613222625
Short name T409
Test name
Test status
Simulation time 35769931349 ps
CPU time 67.77 seconds
Started Jul 31 04:29:06 PM PDT 24
Finished Jul 31 04:30:14 PM PDT 24
Peak memory 183260 kb
Host smart-87500e25-4196-40dc-ab6c-5a9aed6f6489
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613222625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.613222625
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.1948994118
Short name T192
Test name
Test status
Simulation time 351879951393 ps
CPU time 77.32 seconds
Started Jul 31 04:29:07 PM PDT 24
Finished Jul 31 04:30:24 PM PDT 24
Peak memory 191500 kb
Host smart-e98c4871-b175-4d0c-8460-35112315f864
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948994118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.1948994118
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.3918389191
Short name T434
Test name
Test status
Simulation time 118897913047 ps
CPU time 126.72 seconds
Started Jul 31 04:29:09 PM PDT 24
Finished Jul 31 04:31:16 PM PDT 24
Peak memory 191452 kb
Host smart-8a05f522-4d67-4735-8fea-9f99c563fb17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918389191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.3918389191
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.100809664
Short name T437
Test name
Test status
Simulation time 39795035834 ps
CPU time 79.07 seconds
Started Jul 31 04:29:09 PM PDT 24
Finished Jul 31 04:30:28 PM PDT 24
Peak memory 191452 kb
Host smart-6f038374-5092-4907-8d65-e1bb1ca8ccde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100809664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.100809664
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.193246575
Short name T25
Test name
Test status
Simulation time 12598146767 ps
CPU time 21.01 seconds
Started Jul 31 04:27:42 PM PDT 24
Finished Jul 31 04:28:03 PM PDT 24
Peak memory 183312 kb
Host smart-c5bdf2a1-dbe9-428c-ae61-96bab8d5acda
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193246575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.rv_timer_cfg_update_on_fly.193246575
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.2528561303
Short name T399
Test name
Test status
Simulation time 204831776776 ps
CPU time 302.47 seconds
Started Jul 31 04:27:43 PM PDT 24
Finished Jul 31 04:32:46 PM PDT 24
Peak memory 183228 kb
Host smart-25105e2f-9e33-4daa-968f-006bb45e209e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528561303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.2528561303
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.2130660135
Short name T441
Test name
Test status
Simulation time 54225361399 ps
CPU time 89.94 seconds
Started Jul 31 04:27:41 PM PDT 24
Finished Jul 31 04:29:11 PM PDT 24
Peak memory 191532 kb
Host smart-3624b52c-a56e-4691-b3d3-c1d6a63777de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130660135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.2130660135
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.767583686
Short name T395
Test name
Test status
Simulation time 914453635 ps
CPU time 0.93 seconds
Started Jul 31 04:27:42 PM PDT 24
Finished Jul 31 04:27:43 PM PDT 24
Peak memory 183052 kb
Host smart-a8db69ca-3df0-47fd-94ff-15c7b4564b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767583686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.767583686
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all_with_rand_reset.1486820870
Short name T35
Test name
Test status
Simulation time 39455506027 ps
CPU time 200.92 seconds
Started Jul 31 04:27:41 PM PDT 24
Finished Jul 31 04:31:03 PM PDT 24
Peak memory 197944 kb
Host smart-cd002189-a7c2-4846-b758-565a304e53bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486820870 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all_with_rand_reset.1486820870
Directory /workspace/19.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.4063721085
Short name T343
Test name
Test status
Simulation time 221323185930 ps
CPU time 849.53 seconds
Started Jul 31 04:29:06 PM PDT 24
Finished Jul 31 04:43:15 PM PDT 24
Peak memory 194544 kb
Host smart-b34bc1f6-bcd9-4d48-b47e-31914608a900
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063721085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.4063721085
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.1186850911
Short name T161
Test name
Test status
Simulation time 64812248700 ps
CPU time 279.78 seconds
Started Jul 31 04:29:07 PM PDT 24
Finished Jul 31 04:33:47 PM PDT 24
Peak memory 191444 kb
Host smart-6d87c69f-7241-4779-b5cc-5e678e07d34c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186850911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.1186850911
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.2281930937
Short name T191
Test name
Test status
Simulation time 443910080865 ps
CPU time 479.05 seconds
Started Jul 31 04:29:11 PM PDT 24
Finished Jul 31 04:37:11 PM PDT 24
Peak memory 191412 kb
Host smart-90446820-7584-41bd-b6ab-27eb51001233
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281930937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.2281930937
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.1313801188
Short name T99
Test name
Test status
Simulation time 144767838309 ps
CPU time 562.8 seconds
Started Jul 31 04:29:18 PM PDT 24
Finished Jul 31 04:38:41 PM PDT 24
Peak memory 191584 kb
Host smart-cea04d23-786b-4a75-87a1-1fafebda8455
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313801188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.1313801188
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.1880288499
Short name T86
Test name
Test status
Simulation time 191943205371 ps
CPU time 810.14 seconds
Started Jul 31 04:29:14 PM PDT 24
Finished Jul 31 04:42:44 PM PDT 24
Peak memory 191484 kb
Host smart-3b02ef5a-5833-4d2d-8937-e003db9990c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880288499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.1880288499
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.3698099497
Short name T220
Test name
Test status
Simulation time 519357142066 ps
CPU time 159.79 seconds
Started Jul 31 04:29:13 PM PDT 24
Finished Jul 31 04:31:53 PM PDT 24
Peak memory 183248 kb
Host smart-6d43bb80-2815-41dc-8507-f35eb94146c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698099497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.3698099497
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.3150309555
Short name T428
Test name
Test status
Simulation time 28992188766 ps
CPU time 45.72 seconds
Started Jul 31 04:29:11 PM PDT 24
Finished Jul 31 04:29:57 PM PDT 24
Peak memory 191408 kb
Host smart-57e6017b-554e-4c3a-980d-acd027110bae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150309555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.3150309555
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.1196727105
Short name T429
Test name
Test status
Simulation time 44410689167 ps
CPU time 189.25 seconds
Started Jul 31 04:29:12 PM PDT 24
Finished Jul 31 04:32:21 PM PDT 24
Peak memory 183260 kb
Host smart-ba07c4cc-804a-4aeb-8c32-92ac64087559
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196727105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.1196727105
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.860913226
Short name T361
Test name
Test status
Simulation time 2154461276240 ps
CPU time 437.52 seconds
Started Jul 31 04:23:47 PM PDT 24
Finished Jul 31 04:31:05 PM PDT 24
Peak memory 183224 kb
Host smart-7a42033f-aa45-43d5-8c2c-68552ca15d72
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860913226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.rv_timer_cfg_update_on_fly.860913226
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.57896717
Short name T430
Test name
Test status
Simulation time 508952376300 ps
CPU time 208.66 seconds
Started Jul 31 04:22:15 PM PDT 24
Finished Jul 31 04:25:44 PM PDT 24
Peak memory 183280 kb
Host smart-cdb33584-30d1-4ded-8c6e-fafbe9789a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57896717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.57896717
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.2038523478
Short name T101
Test name
Test status
Simulation time 132718122222 ps
CPU time 204.66 seconds
Started Jul 31 04:23:47 PM PDT 24
Finished Jul 31 04:27:12 PM PDT 24
Peak memory 191416 kb
Host smart-453d40c5-c769-47fb-aef9-f75dff40dddf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038523478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.2038523478
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.206099065
Short name T302
Test name
Test status
Simulation time 39836917847 ps
CPU time 61.57 seconds
Started Jul 31 04:23:59 PM PDT 24
Finished Jul 31 04:25:00 PM PDT 24
Peak memory 194588 kb
Host smart-8885e392-926f-4903-ab88-19a627dc1243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206099065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.206099065
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.3100181053
Short name T13
Test name
Test status
Simulation time 364675798 ps
CPU time 0.89 seconds
Started Jul 31 04:23:32 PM PDT 24
Finished Jul 31 04:23:33 PM PDT 24
Peak memory 213864 kb
Host smart-bfaa26d0-f27a-4b11-b8ef-6494e8efb45f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100181053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.3100181053
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.803063506
Short name T217
Test name
Test status
Simulation time 542550256273 ps
CPU time 292.84 seconds
Started Jul 31 04:27:41 PM PDT 24
Finished Jul 31 04:32:34 PM PDT 24
Peak memory 183292 kb
Host smart-59ad35ab-74b7-4df4-92d9-8ac14be63dee
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803063506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.rv_timer_cfg_update_on_fly.803063506
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.4290009989
Short name T365
Test name
Test status
Simulation time 255914443497 ps
CPU time 171.87 seconds
Started Jul 31 04:27:42 PM PDT 24
Finished Jul 31 04:30:34 PM PDT 24
Peak memory 183612 kb
Host smart-a2f8abde-7921-4099-bde3-a047e8626422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290009989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.4290009989
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.3255212375
Short name T245
Test name
Test status
Simulation time 135495588432 ps
CPU time 156.95 seconds
Started Jul 31 04:27:44 PM PDT 24
Finished Jul 31 04:30:21 PM PDT 24
Peak memory 191408 kb
Host smart-d87544ed-a39d-40a4-bcf9-7c0357ebe445
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255212375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.3255212375
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.3187697504
Short name T326
Test name
Test status
Simulation time 69364973659 ps
CPU time 108.41 seconds
Started Jul 31 04:27:50 PM PDT 24
Finished Jul 31 04:29:39 PM PDT 24
Peak memory 191456 kb
Host smart-85cab3fc-3d2b-43d8-ad6b-065c01dc6d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187697504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.3187697504
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.1377572597
Short name T240
Test name
Test status
Simulation time 252524140340 ps
CPU time 403.84 seconds
Started Jul 31 04:27:50 PM PDT 24
Finished Jul 31 04:34:34 PM PDT 24
Peak memory 183244 kb
Host smart-49f0b84c-285e-4ecc-b595-c012ef100a51
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377572597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.1377572597
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.2167401543
Short name T406
Test name
Test status
Simulation time 90676237819 ps
CPU time 62.49 seconds
Started Jul 31 04:27:48 PM PDT 24
Finished Jul 31 04:28:51 PM PDT 24
Peak memory 183308 kb
Host smart-d29d4a9f-478f-4ec1-9e01-9f71a4a5f8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167401543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.2167401543
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.3946087936
Short name T359
Test name
Test status
Simulation time 276097045570 ps
CPU time 110.98 seconds
Started Jul 31 04:27:47 PM PDT 24
Finished Jul 31 04:29:38 PM PDT 24
Peak memory 195140 kb
Host smart-0fffe1f1-6525-4409-ae66-41dcede93814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946087936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.3946087936
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.3322137360
Short name T183
Test name
Test status
Simulation time 27808958798 ps
CPU time 46.1 seconds
Started Jul 31 04:27:49 PM PDT 24
Finished Jul 31 04:28:35 PM PDT 24
Peak memory 183252 kb
Host smart-d6d1bd07-7e88-4f52-9628-24d574b772cf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322137360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.3322137360
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.1281727518
Short name T423
Test name
Test status
Simulation time 884272627360 ps
CPU time 306.38 seconds
Started Jul 31 04:27:50 PM PDT 24
Finished Jul 31 04:32:56 PM PDT 24
Peak memory 183248 kb
Host smart-0e82dd49-7479-41f8-aad8-e62e0a1384a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281727518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.1281727518
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.4005529729
Short name T113
Test name
Test status
Simulation time 107892170198 ps
CPU time 410.27 seconds
Started Jul 31 04:27:48 PM PDT 24
Finished Jul 31 04:34:38 PM PDT 24
Peak memory 191492 kb
Host smart-40247968-d471-4fbf-aefb-6c2577ae9a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005529729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.4005529729
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.3050381576
Short name T341
Test name
Test status
Simulation time 78092245181 ps
CPU time 115.63 seconds
Started Jul 31 04:27:49 PM PDT 24
Finished Jul 31 04:29:45 PM PDT 24
Peak memory 183176 kb
Host smart-c9305800-7584-4378-98c3-44121c0884c1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050381576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.3050381576
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.2070094120
Short name T377
Test name
Test status
Simulation time 179704681754 ps
CPU time 109.47 seconds
Started Jul 31 04:27:49 PM PDT 24
Finished Jul 31 04:29:38 PM PDT 24
Peak memory 183304 kb
Host smart-7de00797-47db-46fb-9383-94ae6d0b47c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070094120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.2070094120
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.380374762
Short name T350
Test name
Test status
Simulation time 67099739332 ps
CPU time 119.72 seconds
Started Jul 31 04:27:48 PM PDT 24
Finished Jul 31 04:29:48 PM PDT 24
Peak memory 191420 kb
Host smart-b1857f77-45cb-466a-85cd-d968e2f1921e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380374762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.380374762
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.536429639
Short name T238
Test name
Test status
Simulation time 18612156996 ps
CPU time 28.22 seconds
Started Jul 31 04:27:55 PM PDT 24
Finished Jul 31 04:28:23 PM PDT 24
Peak memory 191424 kb
Host smart-7664e693-663e-49dd-9b30-06853f3662b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536429639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.536429639
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.4137147533
Short name T321
Test name
Test status
Simulation time 368422958129 ps
CPU time 1145.15 seconds
Started Jul 31 04:27:48 PM PDT 24
Finished Jul 31 04:46:53 PM PDT 24
Peak memory 195948 kb
Host smart-f7961b11-20db-484d-99f3-94fb7f528037
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137147533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.4137147533
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.2780703209
Short name T254
Test name
Test status
Simulation time 27208554541 ps
CPU time 47.3 seconds
Started Jul 31 04:27:48 PM PDT 24
Finished Jul 31 04:28:35 PM PDT 24
Peak memory 183260 kb
Host smart-0184632d-2ca5-4549-9aaa-ff3c91d0a40b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780703209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.2780703209
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.4017395672
Short name T446
Test name
Test status
Simulation time 60907666560 ps
CPU time 46.68 seconds
Started Jul 31 04:27:47 PM PDT 24
Finished Jul 31 04:28:34 PM PDT 24
Peak memory 183340 kb
Host smart-ff33de9b-b8c1-4314-9bae-2a115172da1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017395672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.4017395672
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.945389632
Short name T431
Test name
Test status
Simulation time 49965422423 ps
CPU time 381.63 seconds
Started Jul 31 04:27:48 PM PDT 24
Finished Jul 31 04:34:10 PM PDT 24
Peak memory 183212 kb
Host smart-f32aa559-740b-40f9-af57-f14f584c67c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945389632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.945389632
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.2950923725
Short name T337
Test name
Test status
Simulation time 51312491679 ps
CPU time 53.77 seconds
Started Jul 31 04:27:49 PM PDT 24
Finished Jul 31 04:28:43 PM PDT 24
Peak memory 183212 kb
Host smart-c34d55d1-6f54-46f6-9565-afea083d59dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950923725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.2950923725
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.2881364027
Short name T298
Test name
Test status
Simulation time 315665622672 ps
CPU time 1265 seconds
Started Jul 31 04:27:50 PM PDT 24
Finished Jul 31 04:48:55 PM PDT 24
Peak memory 191436 kb
Host smart-50848bec-bc51-4c2c-b86e-96a00779a2ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881364027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.2881364027
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.429647584
Short name T443
Test name
Test status
Simulation time 33059592928 ps
CPU time 27.79 seconds
Started Jul 31 04:27:50 PM PDT 24
Finished Jul 31 04:28:18 PM PDT 24
Peak memory 183244 kb
Host smart-6689d03e-d615-4e14-a08b-1fdb69d91298
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429647584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.rv_timer_cfg_update_on_fly.429647584
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.4189056955
Short name T421
Test name
Test status
Simulation time 533394560502 ps
CPU time 248.31 seconds
Started Jul 31 04:27:49 PM PDT 24
Finished Jul 31 04:31:58 PM PDT 24
Peak memory 183280 kb
Host smart-cc413ffb-8029-47ce-bdb3-556af72357ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189056955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.4189056955
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.3548174083
Short name T109
Test name
Test status
Simulation time 291269939722 ps
CPU time 155.09 seconds
Started Jul 31 04:27:48 PM PDT 24
Finished Jul 31 04:30:24 PM PDT 24
Peak memory 191508 kb
Host smart-2d589163-3432-4400-b526-dcf3ff0bdd5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548174083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.3548174083
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.1309593702
Short name T303
Test name
Test status
Simulation time 29554958690 ps
CPU time 32.88 seconds
Started Jul 31 04:27:55 PM PDT 24
Finished Jul 31 04:28:28 PM PDT 24
Peak memory 191420 kb
Host smart-dfa58d00-db5e-49c3-b997-404bd7423828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309593702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.1309593702
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.3712237874
Short name T391
Test name
Test status
Simulation time 83443149510 ps
CPU time 131.23 seconds
Started Jul 31 04:27:48 PM PDT 24
Finished Jul 31 04:30:00 PM PDT 24
Peak memory 183272 kb
Host smart-d36ab7c9-29ea-4aef-8b80-dd5ec54316e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712237874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.3712237874
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.287397736
Short name T308
Test name
Test status
Simulation time 1170225135007 ps
CPU time 662.41 seconds
Started Jul 31 04:27:55 PM PDT 24
Finished Jul 31 04:38:58 PM PDT 24
Peak memory 183252 kb
Host smart-a479c270-1218-4ec2-be4f-639caf5c37c6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287397736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.rv_timer_cfg_update_on_fly.287397736
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.1765426886
Short name T389
Test name
Test status
Simulation time 282408219043 ps
CPU time 98.24 seconds
Started Jul 31 04:27:55 PM PDT 24
Finished Jul 31 04:29:33 PM PDT 24
Peak memory 183256 kb
Host smart-b8ed2808-8511-45d9-a761-e395a02bff70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765426886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.1765426886
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.907642151
Short name T261
Test name
Test status
Simulation time 127787777072 ps
CPU time 212.03 seconds
Started Jul 31 04:27:55 PM PDT 24
Finished Jul 31 04:31:27 PM PDT 24
Peak memory 191488 kb
Host smart-769773f5-041e-43f8-8d5d-e30c3d030101
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907642151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.907642151
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.2865825662
Short name T412
Test name
Test status
Simulation time 761910143 ps
CPU time 0.89 seconds
Started Jul 31 04:27:55 PM PDT 24
Finished Jul 31 04:27:55 PM PDT 24
Peak memory 192756 kb
Host smart-85c84527-17e1-4d26-b37f-48c2dfbee8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865825662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.2865825662
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.1572286830
Short name T419
Test name
Test status
Simulation time 119965620585 ps
CPU time 47.38 seconds
Started Jul 31 04:27:55 PM PDT 24
Finished Jul 31 04:28:42 PM PDT 24
Peak memory 183216 kb
Host smart-7f1d7547-0e5b-4bc1-9385-fe9516e98054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572286830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.1572286830
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.1400945045
Short name T277
Test name
Test status
Simulation time 171963252837 ps
CPU time 260.52 seconds
Started Jul 31 04:27:55 PM PDT 24
Finished Jul 31 04:32:15 PM PDT 24
Peak memory 183256 kb
Host smart-753a27ac-6640-44b4-a0fd-2047184ce454
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400945045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.1400945045
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.594107544
Short name T252
Test name
Test status
Simulation time 23662392226 ps
CPU time 826.27 seconds
Started Jul 31 04:27:55 PM PDT 24
Finished Jul 31 04:41:42 PM PDT 24
Peak memory 183356 kb
Host smart-f068c847-991f-4ce1-8b98-565c319c12eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594107544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.594107544
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.2865867276
Short name T329
Test name
Test status
Simulation time 85373248201 ps
CPU time 45.63 seconds
Started Jul 31 04:27:55 PM PDT 24
Finished Jul 31 04:28:41 PM PDT 24
Peak memory 183280 kb
Host smart-812da941-d32d-4329-abea-04b2e36da772
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865867276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.2865867276
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.418720492
Short name T436
Test name
Test status
Simulation time 113547991754 ps
CPU time 172.66 seconds
Started Jul 31 04:27:59 PM PDT 24
Finished Jul 31 04:30:52 PM PDT 24
Peak memory 183016 kb
Host smart-552b3891-0e08-46e8-bceb-e757a4ba1bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418720492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.418720492
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.2946352036
Short name T368
Test name
Test status
Simulation time 51822365 ps
CPU time 0.63 seconds
Started Jul 31 04:27:55 PM PDT 24
Finished Jul 31 04:27:56 PM PDT 24
Peak memory 183040 kb
Host smart-77a8ac0b-2ea5-4acf-b437-640c111ac198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946352036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.2946352036
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.816252497
Short name T18
Test name
Test status
Simulation time 1033794257250 ps
CPU time 544.29 seconds
Started Jul 31 04:28:01 PM PDT 24
Finished Jul 31 04:37:05 PM PDT 24
Peak memory 191460 kb
Host smart-0c58e05f-7fee-4d14-9e80-82510dd81b2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816252497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all.
816252497
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.128027168
Short name T125
Test name
Test status
Simulation time 331613464929 ps
CPU time 562.12 seconds
Started Jul 31 04:27:56 PM PDT 24
Finished Jul 31 04:37:18 PM PDT 24
Peak memory 183236 kb
Host smart-6bd21093-c1e9-4fda-be49-20ff85b5afc7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128027168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.rv_timer_cfg_update_on_fly.128027168
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.921300315
Short name T439
Test name
Test status
Simulation time 95674370288 ps
CPU time 129.72 seconds
Started Jul 31 04:27:57 PM PDT 24
Finished Jul 31 04:30:07 PM PDT 24
Peak memory 183284 kb
Host smart-88150a1c-de4e-430b-8dd7-533a8a7a9318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921300315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.921300315
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.2363393545
Short name T138
Test name
Test status
Simulation time 135034788729 ps
CPU time 118.02 seconds
Started Jul 31 04:27:57 PM PDT 24
Finished Jul 31 04:29:55 PM PDT 24
Peak memory 191464 kb
Host smart-c2bef08a-3f5a-41c4-b8df-313395ce8fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363393545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.2363393545
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all_with_rand_reset.1397260754
Short name T11
Test name
Test status
Simulation time 35725768706 ps
CPU time 257.65 seconds
Started Jul 31 04:27:57 PM PDT 24
Finished Jul 31 04:32:15 PM PDT 24
Peak memory 206180 kb
Host smart-d28e4c4b-8038-4c79-af78-d030510e6975
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397260754 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all_with_rand_reset.1397260754
Directory /workspace/29.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.2773471276
Short name T197
Test name
Test status
Simulation time 32064001201 ps
CPU time 53.72 seconds
Started Jul 31 04:25:48 PM PDT 24
Finished Jul 31 04:26:42 PM PDT 24
Peak memory 183236 kb
Host smart-e8856de1-b0eb-410b-b67c-c862c8be5a86
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773471276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.2773471276
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.981027265
Short name T390
Test name
Test status
Simulation time 109246733429 ps
CPU time 169.82 seconds
Started Jul 31 04:21:00 PM PDT 24
Finished Jul 31 04:23:50 PM PDT 24
Peak memory 183224 kb
Host smart-00591035-64c5-4302-abad-8195dc8aab72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981027265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.981027265
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.4278729226
Short name T91
Test name
Test status
Simulation time 322365875151 ps
CPU time 657.97 seconds
Started Jul 31 04:20:12 PM PDT 24
Finished Jul 31 04:31:10 PM PDT 24
Peak memory 191472 kb
Host smart-8129cec5-6069-4ec8-8e29-d7d4aaa51ef9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278729226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.4278729226
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.3048623447
Short name T371
Test name
Test status
Simulation time 12679074705 ps
CPU time 197.98 seconds
Started Jul 31 04:21:52 PM PDT 24
Finished Jul 31 04:25:10 PM PDT 24
Peak memory 191448 kb
Host smart-143a351d-2f6c-4631-84e1-577c7d971f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048623447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.3048623447
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.3491674051
Short name T17
Test name
Test status
Simulation time 43490503 ps
CPU time 0.76 seconds
Started Jul 31 04:25:37 PM PDT 24
Finished Jul 31 04:25:38 PM PDT 24
Peak memory 213456 kb
Host smart-736527d2-abd8-423b-9f40-f2946aea8072
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491674051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.3491674051
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.301510748
Short name T232
Test name
Test status
Simulation time 161006583591 ps
CPU time 136.83 seconds
Started Jul 31 04:27:58 PM PDT 24
Finished Jul 31 04:30:15 PM PDT 24
Peak memory 183276 kb
Host smart-125b8e11-d20a-4d13-a728-d4d267928543
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301510748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.rv_timer_cfg_update_on_fly.301510748
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.2691315955
Short name T41
Test name
Test status
Simulation time 66288705117 ps
CPU time 43.14 seconds
Started Jul 31 04:27:58 PM PDT 24
Finished Jul 31 04:28:41 PM PDT 24
Peak memory 183228 kb
Host smart-a9775e6b-7cb9-47ff-984e-b5f4dc46ce54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691315955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.2691315955
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.1614513140
Short name T176
Test name
Test status
Simulation time 657176078466 ps
CPU time 1040.41 seconds
Started Jul 31 04:27:56 PM PDT 24
Finished Jul 31 04:45:17 PM PDT 24
Peak memory 191492 kb
Host smart-5ed1f789-db2d-4057-bf46-0ab309b81069
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614513140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.1614513140
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.571313662
Short name T418
Test name
Test status
Simulation time 213777387602 ps
CPU time 114.59 seconds
Started Jul 31 04:28:00 PM PDT 24
Finished Jul 31 04:29:55 PM PDT 24
Peak memory 191352 kb
Host smart-94e25f27-ee42-4ed5-ae8d-042b9ed104a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571313662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.571313662
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all_with_rand_reset.2285565043
Short name T33
Test name
Test status
Simulation time 79200053765 ps
CPU time 154.75 seconds
Started Jul 31 04:28:00 PM PDT 24
Finished Jul 31 04:30:35 PM PDT 24
Peak memory 206100 kb
Host smart-8fb186bf-744c-45cd-89fa-dfb580318218
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285565043 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all_with_rand_reset.2285565043
Directory /workspace/30.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.3492114574
Short name T354
Test name
Test status
Simulation time 337319238164 ps
CPU time 570.45 seconds
Started Jul 31 04:28:02 PM PDT 24
Finished Jul 31 04:37:33 PM PDT 24
Peak memory 183204 kb
Host smart-a39af157-e803-411b-9dd7-61a2badad63d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492114574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.3492114574
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.1951301330
Short name T381
Test name
Test status
Simulation time 656773599386 ps
CPU time 270.32 seconds
Started Jul 31 04:27:59 PM PDT 24
Finished Jul 31 04:32:30 PM PDT 24
Peak memory 183240 kb
Host smart-c9f91a11-b914-4c06-9bd8-33bd0a3fdb29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951301330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.1951301330
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.33352529
Short name T291
Test name
Test status
Simulation time 122500822810 ps
CPU time 137.82 seconds
Started Jul 31 04:28:00 PM PDT 24
Finished Jul 31 04:30:18 PM PDT 24
Peak memory 191420 kb
Host smart-f958cf80-2ce3-4f5e-9471-b6e316662b30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33352529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.33352529
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.2993681395
Short name T352
Test name
Test status
Simulation time 37545034388 ps
CPU time 55.82 seconds
Started Jul 31 04:28:00 PM PDT 24
Finished Jul 31 04:28:56 PM PDT 24
Peak memory 183256 kb
Host smart-51adf14b-b702-4895-bfb4-e4550115051d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993681395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.2993681395
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.968534896
Short name T120
Test name
Test status
Simulation time 265712022201 ps
CPU time 370.4 seconds
Started Jul 31 04:28:02 PM PDT 24
Finished Jul 31 04:34:12 PM PDT 24
Peak memory 191532 kb
Host smart-b8ba68a8-34dc-4136-be45-7f8a0f2bdd71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968534896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all.
968534896
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.2728810245
Short name T364
Test name
Test status
Simulation time 55556273005 ps
CPU time 70.65 seconds
Started Jul 31 04:28:01 PM PDT 24
Finished Jul 31 04:29:12 PM PDT 24
Peak memory 183256 kb
Host smart-11a22de6-1a74-4276-9a6b-711a65d15ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728810245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.2728810245
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.1634353159
Short name T243
Test name
Test status
Simulation time 85828537721 ps
CPU time 64.85 seconds
Started Jul 31 04:28:00 PM PDT 24
Finished Jul 31 04:29:05 PM PDT 24
Peak memory 191468 kb
Host smart-bd79248f-811f-4732-a823-4a022df1e244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634353159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.1634353159
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all_with_rand_reset.289331566
Short name T37
Test name
Test status
Simulation time 14159504844 ps
CPU time 79.25 seconds
Started Jul 31 04:28:00 PM PDT 24
Finished Jul 31 04:29:19 PM PDT 24
Peak memory 197984 kb
Host smart-0f782dc0-7edd-499d-8df8-7004e03ecb3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289331566 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all_with_rand_reset.289331566
Directory /workspace/32.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.3180152234
Short name T127
Test name
Test status
Simulation time 340385128687 ps
CPU time 233.09 seconds
Started Jul 31 04:28:02 PM PDT 24
Finished Jul 31 04:31:55 PM PDT 24
Peak memory 183280 kb
Host smart-20db3884-1b04-4c8c-84f3-417eacbb44bd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180152234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.3180152234
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.974658563
Short name T5
Test name
Test status
Simulation time 111693746366 ps
CPU time 73.28 seconds
Started Jul 31 04:27:59 PM PDT 24
Finished Jul 31 04:29:13 PM PDT 24
Peak memory 183356 kb
Host smart-2522e044-096c-42df-a8b0-762ad2b62d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974658563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.974658563
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.2819532826
Short name T452
Test name
Test status
Simulation time 39950445478 ps
CPU time 36.53 seconds
Started Jul 31 04:28:01 PM PDT 24
Finished Jul 31 04:28:38 PM PDT 24
Peak memory 191456 kb
Host smart-d1df33ce-9979-444b-ba4f-7dc95d493f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819532826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.2819532826
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.2851109390
Short name T143
Test name
Test status
Simulation time 4065876762701 ps
CPU time 1003.18 seconds
Started Jul 31 04:28:03 PM PDT 24
Finished Jul 31 04:44:46 PM PDT 24
Peak memory 183176 kb
Host smart-643695f2-375d-45d6-bc80-7e630071ed20
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851109390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.2851109390
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.2986059311
Short name T440
Test name
Test status
Simulation time 183389729441 ps
CPU time 199.71 seconds
Started Jul 31 04:27:59 PM PDT 24
Finished Jul 31 04:31:19 PM PDT 24
Peak memory 183312 kb
Host smart-78678ddf-982b-4ed8-b947-6e9047db4cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986059311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.2986059311
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.2294861672
Short name T241
Test name
Test status
Simulation time 13172359509 ps
CPU time 20.6 seconds
Started Jul 31 04:28:00 PM PDT 24
Finished Jul 31 04:28:21 PM PDT 24
Peak memory 183052 kb
Host smart-a909e940-6cfd-40ac-aa76-7b43fa82263a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294861672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.2294861672
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.3873755043
Short name T146
Test name
Test status
Simulation time 32788659825 ps
CPU time 68.78 seconds
Started Jul 31 04:28:03 PM PDT 24
Finished Jul 31 04:29:12 PM PDT 24
Peak memory 183180 kb
Host smart-6da1c3ed-cccf-4001-8f94-bacec95a8259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873755043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.3873755043
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.3279259071
Short name T218
Test name
Test status
Simulation time 501110062946 ps
CPU time 2308.51 seconds
Started Jul 31 04:28:05 PM PDT 24
Finished Jul 31 05:06:34 PM PDT 24
Peak memory 191484 kb
Host smart-d9a97362-c640-4692-90c3-979400b350ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279259071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.3279259071
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.128212542
Short name T229
Test name
Test status
Simulation time 257337077174 ps
CPU time 429.67 seconds
Started Jul 31 04:28:04 PM PDT 24
Finished Jul 31 04:35:14 PM PDT 24
Peak memory 183264 kb
Host smart-a4b68105-597b-4bab-a7ff-b58c312cfeb4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128212542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.rv_timer_cfg_update_on_fly.128212542
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.3327731802
Short name T420
Test name
Test status
Simulation time 890197553138 ps
CPU time 117.22 seconds
Started Jul 31 04:28:10 PM PDT 24
Finished Jul 31 04:30:07 PM PDT 24
Peak memory 183316 kb
Host smart-9a518ea5-3a13-43be-9467-cdafbeb55383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327731802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.3327731802
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.186329463
Short name T165
Test name
Test status
Simulation time 119861537644 ps
CPU time 591.88 seconds
Started Jul 31 04:28:04 PM PDT 24
Finished Jul 31 04:37:56 PM PDT 24
Peak memory 194824 kb
Host smart-d40ab633-2bd3-4f3b-acc7-bbfe01f1cc1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186329463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.186329463
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.2268258636
Short name T119
Test name
Test status
Simulation time 26685214346 ps
CPU time 38.35 seconds
Started Jul 31 04:28:04 PM PDT 24
Finished Jul 31 04:28:42 PM PDT 24
Peak memory 183256 kb
Host smart-bc975788-3a71-4ce1-9ed4-c1f984bd6935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268258636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.2268258636
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.212007544
Short name T400
Test name
Test status
Simulation time 4349709197086 ps
CPU time 616.71 seconds
Started Jul 31 04:28:06 PM PDT 24
Finished Jul 31 04:38:22 PM PDT 24
Peak memory 191476 kb
Host smart-02f139b3-8805-4917-975b-beaf8a9ea5e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212007544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all.
212007544
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.3013622590
Short name T156
Test name
Test status
Simulation time 93292589114 ps
CPU time 165.98 seconds
Started Jul 31 04:28:05 PM PDT 24
Finished Jul 31 04:30:51 PM PDT 24
Peak memory 183248 kb
Host smart-a182cbd8-c6e3-48be-94e5-010a5e778a61
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013622590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.3013622590
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.3904808151
Short name T454
Test name
Test status
Simulation time 83030102557 ps
CPU time 103.39 seconds
Started Jul 31 04:28:05 PM PDT 24
Finished Jul 31 04:29:49 PM PDT 24
Peak memory 183620 kb
Host smart-1362d1fa-8675-47d1-8088-c63d72ec3087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904808151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.3904808151
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.612107431
Short name T198
Test name
Test status
Simulation time 155626745747 ps
CPU time 184.63 seconds
Started Jul 31 04:28:06 PM PDT 24
Finished Jul 31 04:31:11 PM PDT 24
Peak memory 191412 kb
Host smart-67304040-2ad7-4f44-a66d-868c6afb9784
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612107431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.612107431
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.523035943
Short name T348
Test name
Test status
Simulation time 34080523673 ps
CPU time 31.83 seconds
Started Jul 31 04:28:05 PM PDT 24
Finished Jul 31 04:28:37 PM PDT 24
Peak memory 183200 kb
Host smart-75f69526-4db0-407f-9ad7-135b65f1965c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523035943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.523035943
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.1761405865
Short name T330
Test name
Test status
Simulation time 716603436940 ps
CPU time 265.36 seconds
Started Jul 31 04:28:05 PM PDT 24
Finished Jul 31 04:32:31 PM PDT 24
Peak memory 183240 kb
Host smart-5fe138e5-2f5f-4f89-90b9-252221ec7f06
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761405865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.1761405865
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.2604443388
Short name T403
Test name
Test status
Simulation time 548372806892 ps
CPU time 176.03 seconds
Started Jul 31 04:28:07 PM PDT 24
Finished Jul 31 04:31:03 PM PDT 24
Peak memory 183340 kb
Host smart-8c9a69dd-f4bd-42f6-b0b7-0d94784a240b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604443388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.2604443388
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.3951794469
Short name T297
Test name
Test status
Simulation time 456436119778 ps
CPU time 652.03 seconds
Started Jul 31 04:28:06 PM PDT 24
Finished Jul 31 04:38:58 PM PDT 24
Peak memory 194092 kb
Host smart-20a67ab5-c98c-4a31-bed6-1d267fee7dec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951794469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.3951794469
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.1917443802
Short name T247
Test name
Test status
Simulation time 34893444962 ps
CPU time 28.84 seconds
Started Jul 31 04:28:06 PM PDT 24
Finished Jul 31 04:28:35 PM PDT 24
Peak memory 183280 kb
Host smart-36a30ba2-89aa-4d41-98d3-e5977d4f871c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917443802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.1917443802
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.3722478301
Short name T318
Test name
Test status
Simulation time 344618060453 ps
CPU time 529.93 seconds
Started Jul 31 04:28:06 PM PDT 24
Finished Jul 31 04:36:56 PM PDT 24
Peak memory 183292 kb
Host smart-eda7e4d0-580d-4109-916f-f6fa21043275
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722478301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.3722478301
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.2926001089
Short name T393
Test name
Test status
Simulation time 126366777303 ps
CPU time 19.42 seconds
Started Jul 31 04:28:05 PM PDT 24
Finished Jul 31 04:28:25 PM PDT 24
Peak memory 183256 kb
Host smart-9d9b64ad-1aba-4ba1-bbb0-88cede19e31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926001089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.2926001089
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.1977674452
Short name T249
Test name
Test status
Simulation time 226657701891 ps
CPU time 1115.12 seconds
Started Jul 31 04:28:05 PM PDT 24
Finished Jul 31 04:46:41 PM PDT 24
Peak memory 191540 kb
Host smart-fd991f1b-1ffb-467b-9677-859dbc832365
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977674452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.1977674452
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.2162695757
Short name T305
Test name
Test status
Simulation time 82666456882 ps
CPU time 63.38 seconds
Started Jul 31 04:28:06 PM PDT 24
Finished Jul 31 04:29:09 PM PDT 24
Peak memory 193192 kb
Host smart-2f08b16d-f9fd-4801-b7cc-7a197a63f24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162695757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.2162695757
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.589812123
Short name T53
Test name
Test status
Simulation time 70620102 ps
CPU time 0.51 seconds
Started Jul 31 04:28:06 PM PDT 24
Finished Jul 31 04:28:06 PM PDT 24
Peak memory 182524 kb
Host smart-c1efc3ba-28f4-4186-a611-5a71c62c929f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589812123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all.
589812123
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.1268407173
Short name T4
Test name
Test status
Simulation time 493265203495 ps
CPU time 262.41 seconds
Started Jul 31 04:28:10 PM PDT 24
Finished Jul 31 04:32:33 PM PDT 24
Peak memory 183236 kb
Host smart-5fd56e4a-3240-4bef-a788-c1c75278170a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268407173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.1268407173
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.1472504206
Short name T379
Test name
Test status
Simulation time 43365127522 ps
CPU time 55.2 seconds
Started Jul 31 04:28:10 PM PDT 24
Finished Jul 31 04:29:05 PM PDT 24
Peak memory 183316 kb
Host smart-9b52df9f-8d30-4ffb-b88c-4361d446c93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472504206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.1472504206
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.1839351023
Short name T259
Test name
Test status
Simulation time 1355175859250 ps
CPU time 1126.01 seconds
Started Jul 31 04:22:44 PM PDT 24
Finished Jul 31 04:41:30 PM PDT 24
Peak memory 183268 kb
Host smart-d1df3bc3-c5f5-41d1-b5bd-8cdbd8cb8302
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839351023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.1839351023
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.26792600
Short name T447
Test name
Test status
Simulation time 527456690242 ps
CPU time 283.8 seconds
Started Jul 31 04:24:46 PM PDT 24
Finished Jul 31 04:29:30 PM PDT 24
Peak memory 181964 kb
Host smart-ea663c79-cc40-483c-811c-2f522ad65465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26792600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.26792600
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.679075221
Short name T316
Test name
Test status
Simulation time 84271537545 ps
CPU time 1370.53 seconds
Started Jul 31 04:24:57 PM PDT 24
Finished Jul 31 04:47:48 PM PDT 24
Peak memory 191052 kb
Host smart-93dc70f4-a262-4564-836f-e9898f145b2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679075221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.679075221
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.312621475
Short name T263
Test name
Test status
Simulation time 20800810139 ps
CPU time 34.23 seconds
Started Jul 31 04:25:08 PM PDT 24
Finished Jul 31 04:25:42 PM PDT 24
Peak memory 183328 kb
Host smart-6024e310-f3eb-48f4-9c10-5e8e4cd4bdb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312621475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.312621475
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.1714569035
Short name T16
Test name
Test status
Simulation time 160119996 ps
CPU time 0.91 seconds
Started Jul 31 04:24:51 PM PDT 24
Finished Jul 31 04:24:53 PM PDT 24
Peak memory 214036 kb
Host smart-3d0c6890-d819-4c82-9f7e-478068a94375
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714569035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.1714569035
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.336802458
Short name T226
Test name
Test status
Simulation time 527162176236 ps
CPU time 2648.12 seconds
Started Jul 31 04:21:40 PM PDT 24
Finished Jul 31 05:05:49 PM PDT 24
Peak memory 191484 kb
Host smart-ac625811-87aa-41f9-ab2c-fd2a7adb0f0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336802458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.336802458
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all_with_rand_reset.109017844
Short name T38
Test name
Test status
Simulation time 28814998260 ps
CPU time 211.05 seconds
Started Jul 31 04:25:08 PM PDT 24
Finished Jul 31 04:28:39 PM PDT 24
Peak memory 197992 kb
Host smart-d66d4ba1-8f13-48f5-9841-37796f3af43a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109017844 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all_with_rand_reset.109017844
Directory /workspace/4.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.3508497460
Short name T194
Test name
Test status
Simulation time 245364030772 ps
CPU time 433.88 seconds
Started Jul 31 04:28:19 PM PDT 24
Finished Jul 31 04:35:33 PM PDT 24
Peak memory 183244 kb
Host smart-858fe654-9d14-4cec-b9bf-8af29e4916fe
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508497460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.3508497460
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.2816536913
Short name T385
Test name
Test status
Simulation time 58543005579 ps
CPU time 84.52 seconds
Started Jul 31 04:28:06 PM PDT 24
Finished Jul 31 04:29:31 PM PDT 24
Peak memory 183288 kb
Host smart-b39b47cd-b0ab-4ec7-aaae-d0a16f92c46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816536913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.2816536913
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.2296173354
Short name T284
Test name
Test status
Simulation time 579414962528 ps
CPU time 676.04 seconds
Started Jul 31 04:28:06 PM PDT 24
Finished Jul 31 04:39:22 PM PDT 24
Peak memory 191460 kb
Host smart-00af0877-b6d7-4588-9090-afc1dc0ab61b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296173354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.2296173354
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.3385312962
Short name T453
Test name
Test status
Simulation time 52368063580 ps
CPU time 18.57 seconds
Started Jul 31 04:28:11 PM PDT 24
Finished Jul 31 04:28:30 PM PDT 24
Peak memory 183104 kb
Host smart-197eb582-1cc2-4823-9985-7f023f730e12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385312962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.3385312962
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.906084232
Short name T285
Test name
Test status
Simulation time 268331632189 ps
CPU time 297.85 seconds
Started Jul 31 04:28:14 PM PDT 24
Finished Jul 31 04:33:12 PM PDT 24
Peak memory 183268 kb
Host smart-f0d9e6fe-a714-49d4-a83b-cdeaa1278605
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906084232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.rv_timer_cfg_update_on_fly.906084232
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.3408708340
Short name T382
Test name
Test status
Simulation time 69370328955 ps
CPU time 51.38 seconds
Started Jul 31 04:28:11 PM PDT 24
Finished Jul 31 04:29:03 PM PDT 24
Peak memory 183280 kb
Host smart-00914107-252f-4005-8d70-2c3eaed09557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408708340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.3408708340
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.3594928764
Short name T355
Test name
Test status
Simulation time 68359482991 ps
CPU time 119.19 seconds
Started Jul 31 04:28:11 PM PDT 24
Finished Jul 31 04:30:10 PM PDT 24
Peak memory 191484 kb
Host smart-ac772b78-954d-436d-a370-bfb8276368f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594928764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.3594928764
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.525653431
Short name T369
Test name
Test status
Simulation time 1971773951 ps
CPU time 3.44 seconds
Started Jul 31 04:28:11 PM PDT 24
Finished Jul 31 04:28:15 PM PDT 24
Peak memory 183200 kb
Host smart-87ce156a-c165-4187-acb3-11957d840281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525653431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.525653431
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.2517647883
Short name T115
Test name
Test status
Simulation time 721548155967 ps
CPU time 371.51 seconds
Started Jul 31 04:28:12 PM PDT 24
Finished Jul 31 04:34:24 PM PDT 24
Peak memory 183200 kb
Host smart-8ada78c2-dfb1-48d7-84ba-800aeaeebdf7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517647883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.2517647883
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.1741487011
Short name T380
Test name
Test status
Simulation time 23376961187 ps
CPU time 19.11 seconds
Started Jul 31 04:28:11 PM PDT 24
Finished Jul 31 04:28:31 PM PDT 24
Peak memory 183256 kb
Host smart-9708b637-a220-4445-bd3a-a25abbe2fb7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741487011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.1741487011
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.157609366
Short name T289
Test name
Test status
Simulation time 13322484959 ps
CPU time 18.14 seconds
Started Jul 31 04:28:13 PM PDT 24
Finished Jul 31 04:28:31 PM PDT 24
Peak memory 183120 kb
Host smart-a66da314-5542-4435-819c-5530c86b4c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157609366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.157609366
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.3899889868
Short name T442
Test name
Test status
Simulation time 9652270499 ps
CPU time 4.62 seconds
Started Jul 31 04:28:13 PM PDT 24
Finished Jul 31 04:28:18 PM PDT 24
Peak memory 183244 kb
Host smart-6a381df8-4595-4778-b92b-c37648b6fdd3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899889868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.3899889868
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.3858703997
Short name T372
Test name
Test status
Simulation time 211097335751 ps
CPU time 167.64 seconds
Started Jul 31 04:28:12 PM PDT 24
Finished Jul 31 04:31:00 PM PDT 24
Peak memory 183284 kb
Host smart-694d8ebe-f017-4ab1-a45e-5d750b174468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858703997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.3858703997
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.87902214
Short name T398
Test name
Test status
Simulation time 357229274 ps
CPU time 0.62 seconds
Started Jul 31 04:28:16 PM PDT 24
Finished Jul 31 04:28:16 PM PDT 24
Peak memory 183048 kb
Host smart-5d7f1622-40a7-422d-acc3-4eb65851d2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87902214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.87902214
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.159670284
Short name T432
Test name
Test status
Simulation time 50994560 ps
CPU time 0.65 seconds
Started Jul 31 04:28:14 PM PDT 24
Finished Jul 31 04:28:14 PM PDT 24
Peak memory 183004 kb
Host smart-bcfad2a5-42a6-4995-9435-9474490bee8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159670284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all.
159670284
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.440696594
Short name T12
Test name
Test status
Simulation time 105572404810 ps
CPU time 891.37 seconds
Started Jul 31 04:28:15 PM PDT 24
Finished Jul 31 04:43:07 PM PDT 24
Peak memory 210316 kb
Host smart-e2b58de0-aeb3-4910-a323-a631959b0b78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440696594 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.440696594
Directory /workspace/43.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.1887814887
Short name T402
Test name
Test status
Simulation time 27058940219 ps
CPU time 11.87 seconds
Started Jul 31 04:28:19 PM PDT 24
Finished Jul 31 04:28:31 PM PDT 24
Peak memory 183228 kb
Host smart-eff90367-1c0b-4619-a3ff-3588d8462a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887814887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.1887814887
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.1071503555
Short name T424
Test name
Test status
Simulation time 613526960 ps
CPU time 1.01 seconds
Started Jul 31 04:28:17 PM PDT 24
Finished Jul 31 04:28:18 PM PDT 24
Peak memory 183084 kb
Host smart-3149b02d-d6fa-4f68-8d06-2dea070553e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071503555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.1071503555
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.866443751
Short name T97
Test name
Test status
Simulation time 859910121059 ps
CPU time 287.12 seconds
Started Jul 31 04:28:20 PM PDT 24
Finished Jul 31 04:33:07 PM PDT 24
Peak memory 183260 kb
Host smart-f33f88c6-5d54-4620-9d0f-dafd261efbae
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866443751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.rv_timer_cfg_update_on_fly.866443751
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.717085143
Short name T425
Test name
Test status
Simulation time 206731854856 ps
CPU time 72.33 seconds
Started Jul 31 04:28:17 PM PDT 24
Finished Jul 31 04:29:30 PM PDT 24
Peak memory 183276 kb
Host smart-e7c35112-4b0e-46ab-8546-5189a534c629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717085143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.717085143
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.890699316
Short name T336
Test name
Test status
Simulation time 51166420327 ps
CPU time 1725.37 seconds
Started Jul 31 04:28:18 PM PDT 24
Finished Jul 31 04:57:04 PM PDT 24
Peak memory 191428 kb
Host smart-aca67725-9cc4-48f5-94d0-0a2e944ee4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890699316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.890699316
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.767081633
Short name T235
Test name
Test status
Simulation time 479509090985 ps
CPU time 676.24 seconds
Started Jul 31 04:28:22 PM PDT 24
Finished Jul 31 04:39:38 PM PDT 24
Peak memory 183360 kb
Host smart-43bc2021-aad8-4e60-a50e-ac039c75e609
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767081633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.rv_timer_cfg_update_on_fly.767081633
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.122151260
Short name T376
Test name
Test status
Simulation time 36315914382 ps
CPU time 25.19 seconds
Started Jul 31 04:28:32 PM PDT 24
Finished Jul 31 04:28:57 PM PDT 24
Peak memory 183232 kb
Host smart-5d5032dc-11db-4b79-989c-3c680bf0b6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122151260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.122151260
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.2194036755
Short name T325
Test name
Test status
Simulation time 216017889852 ps
CPU time 73.78 seconds
Started Jul 31 04:28:19 PM PDT 24
Finished Jul 31 04:29:33 PM PDT 24
Peak memory 191412 kb
Host smart-f4be32cb-546e-4c84-b260-3a5c2061389f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194036755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.2194036755
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.2066965658
Short name T126
Test name
Test status
Simulation time 36626376396 ps
CPU time 61.04 seconds
Started Jul 31 04:28:18 PM PDT 24
Finished Jul 31 04:29:19 PM PDT 24
Peak memory 191556 kb
Host smart-a8edce66-8bdc-4bb2-8772-c29055925ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066965658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.2066965658
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.3505445505
Short name T417
Test name
Test status
Simulation time 226840362 ps
CPU time 0.56 seconds
Started Jul 31 04:28:19 PM PDT 24
Finished Jul 31 04:28:20 PM PDT 24
Peak memory 182964 kb
Host smart-68973e2c-d1af-4ed6-a66b-edaf1a4e9b62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505445505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.3505445505
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.4028880432
Short name T251
Test name
Test status
Simulation time 202275061738 ps
CPU time 308.11 seconds
Started Jul 31 04:28:22 PM PDT 24
Finished Jul 31 04:33:30 PM PDT 24
Peak memory 183272 kb
Host smart-60f44941-cc2f-4dda-8658-532d1ae2f3ae
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028880432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.4028880432
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.1566567327
Short name T435
Test name
Test status
Simulation time 99290203755 ps
CPU time 125.17 seconds
Started Jul 31 04:28:17 PM PDT 24
Finished Jul 31 04:30:22 PM PDT 24
Peak memory 183300 kb
Host smart-72f2b09b-aad4-44c1-a170-02ca1596931e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566567327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.1566567327
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.4268987527
Short name T221
Test name
Test status
Simulation time 576221171628 ps
CPU time 609.54 seconds
Started Jul 31 04:28:17 PM PDT 24
Finished Jul 31 04:38:27 PM PDT 24
Peak memory 191436 kb
Host smart-cc4dcc9c-60a0-4b01-ac53-9ea19701ce87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268987527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.4268987527
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.1273898781
Short name T100
Test name
Test status
Simulation time 87113716112 ps
CPU time 38.84 seconds
Started Jul 31 04:28:18 PM PDT 24
Finished Jul 31 04:28:57 PM PDT 24
Peak memory 183192 kb
Host smart-939ab26d-be09-49f6-883b-d78e5278f532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273898781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.1273898781
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.1017110205
Short name T323
Test name
Test status
Simulation time 152957899290 ps
CPU time 128.36 seconds
Started Jul 31 04:28:24 PM PDT 24
Finished Jul 31 04:30:33 PM PDT 24
Peak memory 183252 kb
Host smart-a8bb4576-fd73-4858-930f-6cc4bf8a6177
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017110205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.1017110205
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.2999969684
Short name T427
Test name
Test status
Simulation time 213701909432 ps
CPU time 71.75 seconds
Started Jul 31 04:28:16 PM PDT 24
Finished Jul 31 04:29:28 PM PDT 24
Peak memory 183252 kb
Host smart-2251a1ab-6891-4966-8fcb-e705d9c69129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999969684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.2999969684
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.199773047
Short name T279
Test name
Test status
Simulation time 87650528509 ps
CPU time 510.47 seconds
Started Jul 31 04:28:18 PM PDT 24
Finished Jul 31 04:36:49 PM PDT 24
Peak memory 193860 kb
Host smart-d6f7fd0f-7691-4093-a506-2b9a9e5bdee9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199773047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.199773047
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.4254206626
Short name T295
Test name
Test status
Simulation time 43817764840 ps
CPU time 72.8 seconds
Started Jul 31 04:28:21 PM PDT 24
Finished Jul 31 04:29:34 PM PDT 24
Peak memory 191468 kb
Host smart-35739150-0036-45fa-90f0-24caf31e25d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254206626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.4254206626
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.3448558167
Short name T378
Test name
Test status
Simulation time 1194089508117 ps
CPU time 315.06 seconds
Started Jul 31 04:28:23 PM PDT 24
Finished Jul 31 04:33:39 PM PDT 24
Peak memory 183296 kb
Host smart-b9acc6d1-c1ba-44b9-b627-8f9c06d8fe9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448558167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.3448558167
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.3619623358
Short name T230
Test name
Test status
Simulation time 7937262766 ps
CPU time 5.04 seconds
Started Jul 31 04:28:27 PM PDT 24
Finished Jul 31 04:28:32 PM PDT 24
Peak memory 183244 kb
Host smart-42ed7f93-681c-430e-89c1-6abef237dcea
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619623358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.3619623358
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.3297537318
Short name T370
Test name
Test status
Simulation time 185505979696 ps
CPU time 149.32 seconds
Started Jul 31 04:28:23 PM PDT 24
Finished Jul 31 04:30:53 PM PDT 24
Peak memory 183264 kb
Host smart-aaba89f1-5709-4594-880b-b00e77e5ff77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297537318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.3297537318
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.3082825451
Short name T310
Test name
Test status
Simulation time 168454888006 ps
CPU time 182.71 seconds
Started Jul 31 04:28:25 PM PDT 24
Finished Jul 31 04:31:28 PM PDT 24
Peak memory 191400 kb
Host smart-7882fed3-5a5f-42d5-a5f1-cf62b29a5857
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082825451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.3082825451
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.1480690076
Short name T392
Test name
Test status
Simulation time 33712998365 ps
CPU time 15.48 seconds
Started Jul 31 04:28:26 PM PDT 24
Finished Jul 31 04:28:41 PM PDT 24
Peak memory 195548 kb
Host smart-93ee8f0b-f15b-4b02-bd42-3095a36a3d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480690076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.1480690076
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.1244458002
Short name T207
Test name
Test status
Simulation time 445969608765 ps
CPU time 1312.77 seconds
Started Jul 31 04:28:22 PM PDT 24
Finished Jul 31 04:50:15 PM PDT 24
Peak memory 195388 kb
Host smart-1545cf80-6502-4723-a40c-8f7f5e1636d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244458002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.1244458002
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.3034869628
Short name T253
Test name
Test status
Simulation time 192674776762 ps
CPU time 324.19 seconds
Started Jul 31 04:25:37 PM PDT 24
Finished Jul 31 04:31:02 PM PDT 24
Peak memory 182936 kb
Host smart-40f822c4-b71e-4aae-96b8-5d92f909c44c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034869628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.3034869628
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.844094998
Short name T375
Test name
Test status
Simulation time 87645868421 ps
CPU time 62.4 seconds
Started Jul 31 04:24:40 PM PDT 24
Finished Jul 31 04:25:43 PM PDT 24
Peak memory 182284 kb
Host smart-6e7b1ce7-6ad9-41ea-90c4-72be978dbe83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844094998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.844094998
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.73712721
Short name T199
Test name
Test status
Simulation time 108550140523 ps
CPU time 159.12 seconds
Started Jul 31 04:25:07 PM PDT 24
Finished Jul 31 04:27:46 PM PDT 24
Peak memory 191516 kb
Host smart-71e35797-80f1-43b7-84d4-58f0a07d046e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73712721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.73712721
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.4047794469
Short name T384
Test name
Test status
Simulation time 210974639 ps
CPU time 1.29 seconds
Started Jul 31 04:22:02 PM PDT 24
Finished Jul 31 04:22:03 PM PDT 24
Peak memory 191416 kb
Host smart-5a0e7ee1-bef2-456d-a354-778483103f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047794469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.4047794469
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.3687701055
Short name T351
Test name
Test status
Simulation time 253465697759 ps
CPU time 466.42 seconds
Started Jul 31 04:23:46 PM PDT 24
Finished Jul 31 04:31:33 PM PDT 24
Peak memory 191464 kb
Host smart-3246c0d8-c0b7-4550-9051-b59d9ae9e83c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687701055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
3687701055
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/50.rv_timer_random.2399462319
Short name T358
Test name
Test status
Simulation time 82956736357 ps
CPU time 453.09 seconds
Started Jul 31 04:28:24 PM PDT 24
Finished Jul 31 04:35:57 PM PDT 24
Peak memory 191440 kb
Host smart-9f6c5eaf-ef1d-4406-822e-bcb5d1c74fab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399462319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.2399462319
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.127309519
Short name T296
Test name
Test status
Simulation time 471640807064 ps
CPU time 275.97 seconds
Started Jul 31 04:28:32 PM PDT 24
Finished Jul 31 04:33:08 PM PDT 24
Peak memory 191580 kb
Host smart-3bcbee0f-dbcf-47f5-a92d-f6d6095b0a4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127309519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.127309519
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.4071528246
Short name T273
Test name
Test status
Simulation time 645630505235 ps
CPU time 825.63 seconds
Started Jul 31 04:28:22 PM PDT 24
Finished Jul 31 04:42:08 PM PDT 24
Peak memory 191540 kb
Host smart-1e31ca98-f8da-4c28-8fae-1384e863a18b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071528246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.4071528246
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.3572120071
Short name T140
Test name
Test status
Simulation time 254008101018 ps
CPU time 700.84 seconds
Started Jul 31 04:28:23 PM PDT 24
Finished Jul 31 04:40:04 PM PDT 24
Peak memory 194028 kb
Host smart-3368bd90-8488-44b4-a8a5-1fe7b11272e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572120071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.3572120071
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.771628181
Short name T317
Test name
Test status
Simulation time 206242611175 ps
CPU time 236.51 seconds
Started Jul 31 04:28:21 PM PDT 24
Finished Jul 31 04:32:18 PM PDT 24
Peak memory 191420 kb
Host smart-6a98493e-6071-44b3-8660-b32b7d0038e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771628181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.771628181
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.317539429
Short name T257
Test name
Test status
Simulation time 1959284872159 ps
CPU time 2763.37 seconds
Started Jul 31 04:28:22 PM PDT 24
Finished Jul 31 05:14:25 PM PDT 24
Peak memory 191460 kb
Host smart-db7c1858-aa99-4254-926c-1cf55d33f2a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317539429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.317539429
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.747543180
Short name T278
Test name
Test status
Simulation time 513329793769 ps
CPU time 284.88 seconds
Started Jul 31 04:28:22 PM PDT 24
Finished Jul 31 04:33:07 PM PDT 24
Peak memory 191492 kb
Host smart-ff359ae7-ee27-4226-8bb5-a9efcd7a160e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747543180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.747543180
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.2311806618
Short name T90
Test name
Test status
Simulation time 91117331573 ps
CPU time 77.07 seconds
Started Jul 31 04:28:22 PM PDT 24
Finished Jul 31 04:29:40 PM PDT 24
Peak memory 183340 kb
Host smart-681c82b6-94c7-483a-a757-0cddb5a49d91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311806618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.2311806618
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.3856463865
Short name T21
Test name
Test status
Simulation time 1160728208002 ps
CPU time 628.38 seconds
Started Jul 31 04:27:21 PM PDT 24
Finished Jul 31 04:37:50 PM PDT 24
Peak memory 183276 kb
Host smart-8100ac5b-b495-4455-ac72-f1ce4c7d5024
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856463865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.3856463865
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.186808137
Short name T386
Test name
Test status
Simulation time 42483823990 ps
CPU time 19.68 seconds
Started Jul 31 04:23:46 PM PDT 24
Finished Jul 31 04:24:06 PM PDT 24
Peak memory 183228 kb
Host smart-2844660a-b021-481e-8878-cddf8ea6be40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186808137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.186808137
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.2836173790
Short name T223
Test name
Test status
Simulation time 801759403720 ps
CPU time 567.26 seconds
Started Jul 31 04:24:41 PM PDT 24
Finished Jul 31 04:34:09 PM PDT 24
Peak memory 191480 kb
Host smart-cd12d2d8-df09-44e8-876a-c42e0fbfe257
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836173790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.2836173790
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.2990279153
Short name T374
Test name
Test status
Simulation time 637329477 ps
CPU time 0.75 seconds
Started Jul 31 04:27:22 PM PDT 24
Finished Jul 31 04:27:23 PM PDT 24
Peak memory 183084 kb
Host smart-c2abc848-83d2-488f-9dbf-6e562557325e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990279153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.2990279153
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.644007982
Short name T158
Test name
Test status
Simulation time 127223937137 ps
CPU time 180.28 seconds
Started Jul 31 04:28:28 PM PDT 24
Finished Jul 31 04:31:29 PM PDT 24
Peak memory 191460 kb
Host smart-abc9c654-941b-44b0-84e6-49b3dc05daa8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644007982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.644007982
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.335193282
Short name T136
Test name
Test status
Simulation time 532910146377 ps
CPU time 468.69 seconds
Started Jul 31 04:28:24 PM PDT 24
Finished Jul 31 04:36:13 PM PDT 24
Peak memory 191404 kb
Host smart-359098bc-c22c-4df6-b777-137f01e52e9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335193282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.335193282
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.677864313
Short name T102
Test name
Test status
Simulation time 88521171655 ps
CPU time 220.82 seconds
Started Jul 31 04:28:27 PM PDT 24
Finished Jul 31 04:32:08 PM PDT 24
Peak memory 191520 kb
Host smart-5692ee04-bf58-42b2-bde5-8c1a1ab5030a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677864313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.677864313
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.2380795719
Short name T150
Test name
Test status
Simulation time 165773087885 ps
CPU time 234.2 seconds
Started Jul 31 04:28:21 PM PDT 24
Finished Jul 31 04:32:16 PM PDT 24
Peak memory 183276 kb
Host smart-1c8676e5-16ec-46b4-bd00-bd15b57cfc8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380795719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.2380795719
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.1035084680
Short name T342
Test name
Test status
Simulation time 24200781338 ps
CPU time 20.58 seconds
Started Jul 31 04:28:24 PM PDT 24
Finished Jul 31 04:28:45 PM PDT 24
Peak memory 183212 kb
Host smart-55656ad6-50e3-4ed7-a4ff-4c531827b60c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035084680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.1035084680
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.3275488665
Short name T212
Test name
Test status
Simulation time 133350086057 ps
CPU time 63.75 seconds
Started Jul 31 04:28:24 PM PDT 24
Finished Jul 31 04:29:28 PM PDT 24
Peak memory 183228 kb
Host smart-47ca327a-22fa-4be4-9d74-34660a2a859c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275488665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.3275488665
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.1553291521
Short name T202
Test name
Test status
Simulation time 59072834433 ps
CPU time 84.42 seconds
Started Jul 31 04:27:23 PM PDT 24
Finished Jul 31 04:28:47 PM PDT 24
Peak memory 183248 kb
Host smart-8ff571f0-2722-4d51-8844-5cd74178573b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553291521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.1553291521
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.3911173217
Short name T405
Test name
Test status
Simulation time 43551063176 ps
CPU time 58.56 seconds
Started Jul 31 04:27:22 PM PDT 24
Finished Jul 31 04:28:21 PM PDT 24
Peak memory 183240 kb
Host smart-845cbd5e-2166-4313-82f6-7706ac42fda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911173217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.3911173217
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.1778117227
Short name T188
Test name
Test status
Simulation time 69359270521 ps
CPU time 389.66 seconds
Started Jul 31 04:27:23 PM PDT 24
Finished Jul 31 04:33:53 PM PDT 24
Peak memory 191516 kb
Host smart-893302a1-bbba-4694-b398-6dd06412155a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778117227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.1778117227
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.3336759430
Short name T450
Test name
Test status
Simulation time 97473242 ps
CPU time 0.65 seconds
Started Jul 31 04:27:22 PM PDT 24
Finished Jul 31 04:27:23 PM PDT 24
Peak memory 182936 kb
Host smart-c3781dbb-98fe-4892-b204-b39f5767ba17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336759430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.3336759430
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.653056324
Short name T51
Test name
Test status
Simulation time 304966915421 ps
CPU time 136.73 seconds
Started Jul 31 04:27:23 PM PDT 24
Finished Jul 31 04:29:40 PM PDT 24
Peak memory 194976 kb
Host smart-77d9dfd3-cea7-4b1a-b9ce-d03bbfe20ed6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653056324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.653056324
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/70.rv_timer_random.221228882
Short name T134
Test name
Test status
Simulation time 81848687664 ps
CPU time 299.48 seconds
Started Jul 31 04:28:24 PM PDT 24
Finished Jul 31 04:33:23 PM PDT 24
Peak memory 191428 kb
Host smart-8f313302-5601-4671-9939-c66da70b8c39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221228882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.221228882
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.3093179380
Short name T438
Test name
Test status
Simulation time 162565784396 ps
CPU time 76.07 seconds
Started Jul 31 04:28:28 PM PDT 24
Finished Jul 31 04:29:44 PM PDT 24
Peak memory 191456 kb
Host smart-e22859cc-e832-430e-9776-90faf47074f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093179380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.3093179380
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.3223467425
Short name T309
Test name
Test status
Simulation time 22585572592 ps
CPU time 32.76 seconds
Started Jul 31 04:28:29 PM PDT 24
Finished Jul 31 04:29:02 PM PDT 24
Peak memory 183220 kb
Host smart-48eaa138-b774-4a71-bcfb-a6d9890e6575
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223467425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.3223467425
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.3636028073
Short name T166
Test name
Test status
Simulation time 196333697651 ps
CPU time 546.28 seconds
Started Jul 31 04:28:27 PM PDT 24
Finished Jul 31 04:37:34 PM PDT 24
Peak memory 191492 kb
Host smart-384cc381-91e7-4fe2-be04-57a04c02b965
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636028073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.3636028073
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.2934769935
Short name T7
Test name
Test status
Simulation time 1288368267939 ps
CPU time 651.45 seconds
Started Jul 31 04:28:28 PM PDT 24
Finished Jul 31 04:39:20 PM PDT 24
Peak memory 191460 kb
Host smart-fb15fc03-4472-4311-82e0-ed5fd61c3d58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934769935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.2934769935
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.4151459776
Short name T88
Test name
Test status
Simulation time 94775855345 ps
CPU time 525.39 seconds
Started Jul 31 04:28:28 PM PDT 24
Finished Jul 31 04:37:14 PM PDT 24
Peak memory 191460 kb
Host smart-e3dae16a-3cf6-4778-bd9e-2e43bc82a7b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151459776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.4151459776
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.2238941143
Short name T130
Test name
Test status
Simulation time 167711940751 ps
CPU time 71.18 seconds
Started Jul 31 04:28:30 PM PDT 24
Finished Jul 31 04:29:42 PM PDT 24
Peak memory 183280 kb
Host smart-a54feb05-dcc8-42dd-b957-814a3fdbae69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238941143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.2238941143
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.1724933520
Short name T283
Test name
Test status
Simulation time 160414611219 ps
CPU time 45.11 seconds
Started Jul 31 04:28:37 PM PDT 24
Finished Jul 31 04:29:22 PM PDT 24
Peak memory 193800 kb
Host smart-f101499b-4f76-49d9-ac24-d60268abfc0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724933520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.1724933520
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.2371215355
Short name T290
Test name
Test status
Simulation time 337740784118 ps
CPU time 155.94 seconds
Started Jul 31 04:28:29 PM PDT 24
Finished Jul 31 04:31:05 PM PDT 24
Peak memory 191464 kb
Host smart-afbc8642-96e0-48f0-bc3b-4a7c638f2769
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371215355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.2371215355
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.2695817758
Short name T23
Test name
Test status
Simulation time 147402602465 ps
CPU time 200.34 seconds
Started Jul 31 04:27:22 PM PDT 24
Finished Jul 31 04:30:43 PM PDT 24
Peak memory 183260 kb
Host smart-8d0ff4e8-db08-4b0d-8983-7c7acb3fa60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695817758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.2695817758
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.2267167819
Short name T333
Test name
Test status
Simulation time 209017538072 ps
CPU time 135.54 seconds
Started Jul 31 04:27:30 PM PDT 24
Finished Jul 31 04:29:45 PM PDT 24
Peak memory 191436 kb
Host smart-bf56a3db-81fd-4b9b-ad4f-dfabf7ee72ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267167819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.2267167819
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.2020939333
Short name T367
Test name
Test status
Simulation time 14802159 ps
CPU time 0.51 seconds
Started Jul 31 04:27:28 PM PDT 24
Finished Jul 31 04:27:29 PM PDT 24
Peak memory 182992 kb
Host smart-e6c80fc1-1042-4b10-acf6-ffeacef15061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020939333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.2020939333
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.4215079423
Short name T426
Test name
Test status
Simulation time 126640998 ps
CPU time 0.58 seconds
Started Jul 31 04:27:28 PM PDT 24
Finished Jul 31 04:27:29 PM PDT 24
Peak memory 183000 kb
Host smart-bcc078d3-3746-4872-9a12-efcac60b0b38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215079423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
4215079423
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/80.rv_timer_random.548559137
Short name T237
Test name
Test status
Simulation time 125317610070 ps
CPU time 334.57 seconds
Started Jul 31 04:28:36 PM PDT 24
Finished Jul 31 04:34:11 PM PDT 24
Peak memory 191472 kb
Host smart-ad3ea431-9768-482b-926f-7d9939a261dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548559137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.548559137
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.1089490114
Short name T8
Test name
Test status
Simulation time 599368630157 ps
CPU time 201.74 seconds
Started Jul 31 04:28:34 PM PDT 24
Finished Jul 31 04:31:56 PM PDT 24
Peak memory 191420 kb
Host smart-20c385be-cf81-4c64-b529-3a2ca85a5c02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089490114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.1089490114
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.2223793279
Short name T322
Test name
Test status
Simulation time 18776218163 ps
CPU time 6.12 seconds
Started Jul 31 04:28:35 PM PDT 24
Finished Jul 31 04:28:41 PM PDT 24
Peak memory 183212 kb
Host smart-0c47f87f-6fe6-4fff-836b-029d5ff85f71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223793279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.2223793279
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.1597873823
Short name T142
Test name
Test status
Simulation time 161135291850 ps
CPU time 557.95 seconds
Started Jul 31 04:28:33 PM PDT 24
Finished Jul 31 04:37:51 PM PDT 24
Peak memory 191468 kb
Host smart-ba7e65f8-30e8-4bef-a4d0-6e5334a3adee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597873823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.1597873823
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.3293370936
Short name T184
Test name
Test status
Simulation time 103526540831 ps
CPU time 121.73 seconds
Started Jul 31 04:28:36 PM PDT 24
Finished Jul 31 04:30:38 PM PDT 24
Peak memory 191432 kb
Host smart-c9d39b64-1dfc-43c3-bb58-2cacec891839
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293370936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.3293370936
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.176480454
Short name T10
Test name
Test status
Simulation time 80936737396 ps
CPU time 64.88 seconds
Started Jul 31 04:28:38 PM PDT 24
Finished Jul 31 04:29:43 PM PDT 24
Peak memory 191444 kb
Host smart-feb408f4-549e-4a51-b241-a14ba4ca4456
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176480454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.176480454
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.2055813246
Short name T356
Test name
Test status
Simulation time 914646618601 ps
CPU time 667.32 seconds
Started Jul 31 04:28:33 PM PDT 24
Finished Jul 31 04:39:41 PM PDT 24
Peak memory 191460 kb
Host smart-4dbf10ac-d0fe-4294-94bd-d406ad371ee3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055813246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.2055813246
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.2984284394
Short name T275
Test name
Test status
Simulation time 225244651075 ps
CPU time 981.34 seconds
Started Jul 31 04:28:37 PM PDT 24
Finished Jul 31 04:44:59 PM PDT 24
Peak memory 191464 kb
Host smart-04e0cf57-9722-4494-8470-e0e0d5cfc754
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984284394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.2984284394
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.61419725
Short name T170
Test name
Test status
Simulation time 11292990615 ps
CPU time 18.93 seconds
Started Jul 31 04:27:28 PM PDT 24
Finished Jul 31 04:27:47 PM PDT 24
Peak memory 183248 kb
Host smart-fc1b7ed1-38cc-4bbf-a8f5-94a070e3b236
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61419725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
rv_timer_cfg_update_on_fly.61419725
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_random.4113424682
Short name T154
Test name
Test status
Simulation time 113920449106 ps
CPU time 1124.16 seconds
Started Jul 31 04:27:22 PM PDT 24
Finished Jul 31 04:46:07 PM PDT 24
Peak memory 191500 kb
Host smart-2aa33c39-c92f-45d2-82ea-9b81bb98b8ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113424682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.4113424682
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.3011571207
Short name T215
Test name
Test status
Simulation time 393553416826 ps
CPU time 356.67 seconds
Started Jul 31 04:27:23 PM PDT 24
Finished Jul 31 04:33:20 PM PDT 24
Peak memory 191472 kb
Host smart-798ef05d-87e0-410c-94da-b98e9358aea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011571207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.3011571207
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.3231402209
Short name T224
Test name
Test status
Simulation time 8092012268062 ps
CPU time 1204.1 seconds
Started Jul 31 04:27:29 PM PDT 24
Finished Jul 31 04:47:33 PM PDT 24
Peak memory 195900 kb
Host smart-f4737ab1-7635-443f-b94c-4bf9b8ddef3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231402209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
3231402209
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/92.rv_timer_random.439679525
Short name T216
Test name
Test status
Simulation time 132663340155 ps
CPU time 687.14 seconds
Started Jul 31 04:28:32 PM PDT 24
Finished Jul 31 04:40:00 PM PDT 24
Peak memory 191480 kb
Host smart-e3b94e74-fd45-4cbc-bb09-f8108cc525a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439679525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.439679525
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.4093631058
Short name T160
Test name
Test status
Simulation time 260437006721 ps
CPU time 228.37 seconds
Started Jul 31 04:28:38 PM PDT 24
Finished Jul 31 04:32:26 PM PDT 24
Peak memory 191540 kb
Host smart-e88094fa-d526-488f-ae2f-7c51cb830bed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093631058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.4093631058
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.23665903
Short name T123
Test name
Test status
Simulation time 1717615558869 ps
CPU time 418.07 seconds
Started Jul 31 04:28:40 PM PDT 24
Finished Jul 31 04:35:38 PM PDT 24
Peak memory 191512 kb
Host smart-17af7d73-3689-4b2d-8b00-69d23e5e72d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23665903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.23665903
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.861601337
Short name T301
Test name
Test status
Simulation time 3830181299 ps
CPU time 6.33 seconds
Started Jul 31 04:28:34 PM PDT 24
Finished Jul 31 04:28:41 PM PDT 24
Peak memory 183296 kb
Host smart-f07df8d6-14de-4151-9a83-836a427e2514
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861601337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.861601337
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.2488685809
Short name T414
Test name
Test status
Simulation time 67000725818 ps
CPU time 123.73 seconds
Started Jul 31 04:28:33 PM PDT 24
Finished Jul 31 04:30:37 PM PDT 24
Peak memory 183252 kb
Host smart-59cbb3ff-c81c-40fe-97d9-32fc0d612776
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488685809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.2488685809
Directory /workspace/99.rv_timer_random/latest
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