Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.57 99.36 98.73 100.00 100.00 100.00 99.32


Total test records in report: 579
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T507 /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1354301854 Aug 01 04:54:22 PM PDT 24 Aug 01 04:54:23 PM PDT 24 58634711 ps
T71 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1572167285 Aug 01 04:54:18 PM PDT 24 Aug 01 04:54:19 PM PDT 24 24813939 ps
T508 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.4030822928 Aug 01 04:54:20 PM PDT 24 Aug 01 04:54:21 PM PDT 24 97056966 ps
T509 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.2622798309 Aug 01 04:54:43 PM PDT 24 Aug 01 04:54:44 PM PDT 24 31326251 ps
T72 /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.103050255 Aug 01 04:54:43 PM PDT 24 Aug 01 04:54:43 PM PDT 24 27291120 ps
T510 /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3917896257 Aug 01 04:54:19 PM PDT 24 Aug 01 04:54:20 PM PDT 24 34225444 ps
T511 /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.3369568530 Aug 01 04:54:43 PM PDT 24 Aug 01 04:54:44 PM PDT 24 12354334 ps
T512 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2727018821 Aug 01 04:54:51 PM PDT 24 Aug 01 04:54:52 PM PDT 24 14211249 ps
T513 /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1348023000 Aug 01 04:54:19 PM PDT 24 Aug 01 04:54:20 PM PDT 24 14401825 ps
T514 /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.213953400 Aug 01 04:54:44 PM PDT 24 Aug 01 04:54:45 PM PDT 24 100906062 ps
T515 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.596984804 Aug 01 04:54:44 PM PDT 24 Aug 01 04:54:45 PM PDT 24 32165669 ps
T516 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.3143270927 Aug 01 04:54:53 PM PDT 24 Aug 01 04:54:54 PM PDT 24 47899365 ps
T517 /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.235689981 Aug 01 04:54:28 PM PDT 24 Aug 01 04:54:30 PM PDT 24 30402230 ps
T518 /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.1085735868 Aug 01 04:54:09 PM PDT 24 Aug 01 04:54:10 PM PDT 24 245766406 ps
T519 /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.3898082817 Aug 01 04:54:18 PM PDT 24 Aug 01 04:54:19 PM PDT 24 36156047 ps
T520 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.209089299 Aug 01 04:54:54 PM PDT 24 Aug 01 04:54:55 PM PDT 24 16002256 ps
T521 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.2585178677 Aug 01 04:54:42 PM PDT 24 Aug 01 04:54:42 PM PDT 24 29128569 ps
T522 /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.3871508984 Aug 01 04:54:21 PM PDT 24 Aug 01 04:54:21 PM PDT 24 32896253 ps
T523 /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3984118974 Aug 01 04:54:43 PM PDT 24 Aug 01 04:54:45 PM PDT 24 360185429 ps
T524 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.1948193299 Aug 01 04:54:46 PM PDT 24 Aug 01 04:54:48 PM PDT 24 111631082 ps
T525 /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.4038081882 Aug 01 04:54:20 PM PDT 24 Aug 01 04:54:22 PM PDT 24 479684143 ps
T526 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.456708740 Aug 01 04:54:06 PM PDT 24 Aug 01 04:54:06 PM PDT 24 47989324 ps
T527 /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.4253114304 Aug 01 04:54:55 PM PDT 24 Aug 01 04:54:55 PM PDT 24 39572911 ps
T528 /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.877709785 Aug 01 04:54:08 PM PDT 24 Aug 01 04:54:08 PM PDT 24 30742477 ps
T529 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3581661630 Aug 01 04:54:40 PM PDT 24 Aug 01 04:54:41 PM PDT 24 11383701 ps
T530 /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.830708418 Aug 01 04:54:19 PM PDT 24 Aug 01 04:54:21 PM PDT 24 67304377 ps
T531 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2101429815 Aug 01 04:54:21 PM PDT 24 Aug 01 04:54:22 PM PDT 24 74280707 ps
T532 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.2007920976 Aug 01 04:54:53 PM PDT 24 Aug 01 04:54:54 PM PDT 24 13269592 ps
T533 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.3304763776 Aug 01 04:54:07 PM PDT 24 Aug 01 04:54:10 PM PDT 24 400562426 ps
T534 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.2845255827 Aug 01 04:54:22 PM PDT 24 Aug 01 04:54:24 PM PDT 24 76179424 ps
T535 /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.838378625 Aug 01 04:54:19 PM PDT 24 Aug 01 04:54:20 PM PDT 24 244418540 ps
T536 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.284343444 Aug 01 04:54:21 PM PDT 24 Aug 01 04:54:22 PM PDT 24 187701500 ps
T537 /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.277388621 Aug 01 04:54:41 PM PDT 24 Aug 01 04:54:42 PM PDT 24 24694039 ps
T538 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.2707580217 Aug 01 04:54:08 PM PDT 24 Aug 01 04:54:09 PM PDT 24 16478156 ps
T539 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.3803897178 Aug 01 04:54:28 PM PDT 24 Aug 01 04:54:29 PM PDT 24 70761187 ps
T85 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2254442748 Aug 01 04:54:19 PM PDT 24 Aug 01 04:54:21 PM PDT 24 88585801 ps
T540 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.1035268958 Aug 01 04:54:39 PM PDT 24 Aug 01 04:54:40 PM PDT 24 19358165 ps
T541 /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1204977653 Aug 01 04:54:29 PM PDT 24 Aug 01 04:54:30 PM PDT 24 468224522 ps
T542 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.1751174130 Aug 01 04:54:53 PM PDT 24 Aug 01 04:54:54 PM PDT 24 34305529 ps
T543 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1425572850 Aug 01 04:54:41 PM PDT 24 Aug 01 04:54:42 PM PDT 24 52578530 ps
T544 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1879342719 Aug 01 04:54:53 PM PDT 24 Aug 01 04:54:54 PM PDT 24 15602540 ps
T545 /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.439240634 Aug 01 04:54:43 PM PDT 24 Aug 01 04:54:44 PM PDT 24 41726136 ps
T546 /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.1551893046 Aug 01 04:54:07 PM PDT 24 Aug 01 04:54:08 PM PDT 24 27038825 ps
T547 /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.1048959444 Aug 01 04:54:39 PM PDT 24 Aug 01 04:54:40 PM PDT 24 18462979 ps
T548 /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.2210852455 Aug 01 04:54:40 PM PDT 24 Aug 01 04:54:41 PM PDT 24 25022185 ps
T549 /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.882220191 Aug 01 04:54:53 PM PDT 24 Aug 01 04:54:54 PM PDT 24 86600609 ps
T73 /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3703113728 Aug 01 04:54:21 PM PDT 24 Aug 01 04:54:21 PM PDT 24 32021973 ps
T550 /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3557133385 Aug 01 04:54:07 PM PDT 24 Aug 01 04:54:09 PM PDT 24 37290066 ps
T551 /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.621707398 Aug 01 04:54:20 PM PDT 24 Aug 01 04:54:21 PM PDT 24 16944129 ps
T552 /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.3947850599 Aug 01 04:54:52 PM PDT 24 Aug 01 04:54:53 PM PDT 24 13482022 ps
T553 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.2478199177 Aug 01 04:54:29 PM PDT 24 Aug 01 04:54:30 PM PDT 24 449324817 ps
T554 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.1508135223 Aug 01 04:54:29 PM PDT 24 Aug 01 04:54:31 PM PDT 24 242709763 ps
T555 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.4009207052 Aug 01 04:54:43 PM PDT 24 Aug 01 04:54:44 PM PDT 24 41566141 ps
T556 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.708479407 Aug 01 04:54:07 PM PDT 24 Aug 01 04:54:08 PM PDT 24 21927262 ps
T557 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.550608820 Aug 01 04:54:39 PM PDT 24 Aug 01 04:54:40 PM PDT 24 16389191 ps
T558 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.617779071 Aug 01 04:54:42 PM PDT 24 Aug 01 04:54:43 PM PDT 24 97740935 ps
T559 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1619631060 Aug 01 04:54:18 PM PDT 24 Aug 01 04:54:19 PM PDT 24 42329982 ps
T560 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.824914612 Aug 01 04:54:31 PM PDT 24 Aug 01 04:54:31 PM PDT 24 62688875 ps
T561 /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.1395015887 Aug 01 04:54:06 PM PDT 24 Aug 01 04:54:09 PM PDT 24 53387951 ps
T562 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.192790882 Aug 01 04:54:30 PM PDT 24 Aug 01 04:54:31 PM PDT 24 44619117 ps
T563 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.45603290 Aug 01 04:54:30 PM PDT 24 Aug 01 04:54:32 PM PDT 24 154173468 ps
T86 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.816326883 Aug 01 04:54:29 PM PDT 24 Aug 01 04:54:31 PM PDT 24 72354659 ps
T564 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1629355573 Aug 01 04:54:29 PM PDT 24 Aug 01 04:54:31 PM PDT 24 98475721 ps
T565 /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.3464262157 Aug 01 04:54:17 PM PDT 24 Aug 01 04:54:19 PM PDT 24 105549463 ps
T566 /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.3860598835 Aug 01 04:54:06 PM PDT 24 Aug 01 04:54:08 PM PDT 24 605121309 ps
T567 /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.706511586 Aug 01 04:54:39 PM PDT 24 Aug 01 04:54:41 PM PDT 24 180096340 ps
T568 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.2817176175 Aug 01 04:54:05 PM PDT 24 Aug 01 04:54:06 PM PDT 24 84268268 ps
T569 /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.819216792 Aug 01 04:54:43 PM PDT 24 Aug 01 04:54:44 PM PDT 24 15150405 ps
T570 /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.392817430 Aug 01 04:54:29 PM PDT 24 Aug 01 04:54:30 PM PDT 24 22087104 ps
T74 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.962802821 Aug 01 04:54:07 PM PDT 24 Aug 01 04:54:08 PM PDT 24 72677548 ps
T571 /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.1607936560 Aug 01 04:54:52 PM PDT 24 Aug 01 04:54:53 PM PDT 24 35633100 ps
T572 /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.670123261 Aug 01 04:54:43 PM PDT 24 Aug 01 04:54:44 PM PDT 24 19179363 ps
T573 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2463224607 Aug 01 04:54:08 PM PDT 24 Aug 01 04:54:10 PM PDT 24 128301712 ps
T574 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.3263689146 Aug 01 04:54:18 PM PDT 24 Aug 01 04:54:19 PM PDT 24 15167439 ps
T575 /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.2915089001 Aug 01 04:54:53 PM PDT 24 Aug 01 04:54:54 PM PDT 24 35136302 ps
T576 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.43668793 Aug 01 04:54:29 PM PDT 24 Aug 01 04:54:30 PM PDT 24 14673515 ps
T577 /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.1297872388 Aug 01 04:54:23 PM PDT 24 Aug 01 04:54:24 PM PDT 24 161067232 ps
T578 /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.1842421018 Aug 01 04:54:06 PM PDT 24 Aug 01 04:54:10 PM PDT 24 1248212038 ps
T579 /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.4083342867 Aug 01 04:54:39 PM PDT 24 Aug 01 04:54:40 PM PDT 24 43113676 ps

Test location /workspace/coverage/default/32.rv_timer_random.2973212291
Short name T2
Test name
Test status
Simulation time 386190628906 ps
CPU time 1181.5 seconds
Started Aug 01 04:19:21 PM PDT 24
Finished Aug 01 04:39:03 PM PDT 24
Peak memory 191416 kb
Host smart-57c439da-f1a2-4ddf-b7be-919218362f7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973212291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.2973212291
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all_with_rand_reset.324567027
Short name T11
Test name
Test status
Simulation time 124043761957 ps
CPU time 969.89 seconds
Started Aug 01 04:21:03 PM PDT 24
Finished Aug 01 04:37:13 PM PDT 24
Peak memory 208908 kb
Host smart-e16abe48-adcd-44a1-87a9-88f18186d977
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324567027 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all_with_rand_reset.324567027
Directory /workspace/26.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.636653996
Short name T28
Test name
Test status
Simulation time 624028525 ps
CPU time 1.31 seconds
Started Aug 01 04:54:18 PM PDT 24
Finished Aug 01 04:54:20 PM PDT 24
Peak memory 195408 kb
Host smart-050b6ad7-fc90-42cc-b707-51801dbec404
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636653996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_int
g_err.636653996
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.4238757459
Short name T200
Test name
Test status
Simulation time 550981218146 ps
CPU time 1279.35 seconds
Started Aug 01 04:20:55 PM PDT 24
Finished Aug 01 04:42:15 PM PDT 24
Peak memory 191072 kb
Host smart-82fa09e5-3efc-44f6-b0e6-b415a85f7378
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238757459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.4238757459
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.3181247680
Short name T57
Test name
Test status
Simulation time 1369238762131 ps
CPU time 1494.54 seconds
Started Aug 01 04:23:04 PM PDT 24
Finished Aug 01 04:47:59 PM PDT 24
Peak memory 191396 kb
Host smart-8e3f28a3-a78e-446c-be2f-50c66e8d8ee4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181247680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.3181247680
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.3919040086
Short name T98
Test name
Test status
Simulation time 1737520718183 ps
CPU time 2574.95 seconds
Started Aug 01 04:22:53 PM PDT 24
Finished Aug 01 05:05:48 PM PDT 24
Peak memory 191148 kb
Host smart-1328e6ae-30e4-4fd2-ba19-4c36b50c52f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919040086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.3919040086
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.350872917
Short name T208
Test name
Test status
Simulation time 3156283915413 ps
CPU time 1949.76 seconds
Started Aug 01 04:20:55 PM PDT 24
Finished Aug 01 04:53:25 PM PDT 24
Peak memory 196340 kb
Host smart-c3c49e70-2d90-41f6-9304-ce23659f4d15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350872917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all.
350872917
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.38497517
Short name T97
Test name
Test status
Simulation time 385175289975 ps
CPU time 1440.01 seconds
Started Aug 01 04:20:03 PM PDT 24
Finished Aug 01 04:44:03 PM PDT 24
Peak memory 191420 kb
Host smart-497bbfef-801d-47ba-ba1f-3d88ecd9e181
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38497517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all.38497517
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.4046713148
Short name T140
Test name
Test status
Simulation time 570902722574 ps
CPU time 1410.86 seconds
Started Aug 01 04:18:23 PM PDT 24
Finished Aug 01 04:41:54 PM PDT 24
Peak memory 191184 kb
Host smart-79cdc536-89bd-4d28-8d95-4e7aaa3d6b9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046713148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.4046713148
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.2512390135
Short name T260
Test name
Test status
Simulation time 1345732677311 ps
CPU time 1612.08 seconds
Started Aug 01 04:23:43 PM PDT 24
Finished Aug 01 04:50:36 PM PDT 24
Peak memory 195396 kb
Host smart-ae9fcc9d-98a4-4343-8344-56a1064ee3fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512390135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.2512390135
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.208781297
Short name T8
Test name
Test status
Simulation time 740803586674 ps
CPU time 440.06 seconds
Started Aug 01 04:22:24 PM PDT 24
Finished Aug 01 04:29:44 PM PDT 24
Peak memory 195488 kb
Host smart-663da649-2c16-4553-8dfb-7d04fd21522a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208781297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all.
208781297
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.3878016466
Short name T166
Test name
Test status
Simulation time 847476870180 ps
CPU time 1939.19 seconds
Started Aug 01 04:22:25 PM PDT 24
Finished Aug 01 04:54:45 PM PDT 24
Peak memory 190164 kb
Host smart-ae7a99fb-317d-45f8-a0c7-89f4993e7355
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878016466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
3878016466
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/94.rv_timer_random.4039435443
Short name T95
Test name
Test status
Simulation time 349781279753 ps
CPU time 168.49 seconds
Started Aug 01 04:24:00 PM PDT 24
Finished Aug 01 04:26:49 PM PDT 24
Peak memory 191144 kb
Host smart-91af5bf0-3b72-4700-a9cd-43e9baff94fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039435443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.4039435443
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.320165622
Short name T14
Test name
Test status
Simulation time 132476998 ps
CPU time 0.76 seconds
Started Aug 01 04:17:46 PM PDT 24
Finished Aug 01 04:17:47 PM PDT 24
Peak memory 213940 kb
Host smart-0ce1443d-6a19-4793-ab8d-cb42a14c6164
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320165622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.320165622
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.4271408299
Short name T203
Test name
Test status
Simulation time 429440437884 ps
CPU time 664.37 seconds
Started Aug 01 04:19:02 PM PDT 24
Finished Aug 01 04:30:06 PM PDT 24
Peak memory 191576 kb
Host smart-ea1493ca-a187-4b1f-8978-8a127eb55269
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271408299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.4271408299
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.3665552755
Short name T186
Test name
Test status
Simulation time 3895037783233 ps
CPU time 1871.44 seconds
Started Aug 01 04:24:15 PM PDT 24
Finished Aug 01 04:55:27 PM PDT 24
Peak memory 190188 kb
Host smart-ee5860bb-26c5-4d60-b8df-679c8ff1d34e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665552755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.3665552755
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.1326154291
Short name T162
Test name
Test status
Simulation time 495119095438 ps
CPU time 2767.34 seconds
Started Aug 01 04:19:38 PM PDT 24
Finished Aug 01 05:05:46 PM PDT 24
Peak memory 191452 kb
Host smart-4c569bd8-517c-4d9c-bb76-5b32cdf77ada
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326154291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.1326154291
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/125.rv_timer_random.2386380282
Short name T157
Test name
Test status
Simulation time 618946895533 ps
CPU time 1092.6 seconds
Started Aug 01 04:23:27 PM PDT 24
Finished Aug 01 04:41:39 PM PDT 24
Peak memory 191388 kb
Host smart-85872041-fc94-4824-b663-342258d87e7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386380282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.2386380282
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.3569112669
Short name T273
Test name
Test status
Simulation time 1193606920268 ps
CPU time 2931.35 seconds
Started Aug 01 04:22:37 PM PDT 24
Finished Aug 01 05:11:29 PM PDT 24
Peak memory 190952 kb
Host smart-6b26bc0a-5c93-4e80-8b40-2b30abf8697f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569112669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.3569112669
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.1512699672
Short name T102
Test name
Test status
Simulation time 1551627298805 ps
CPU time 2097.38 seconds
Started Aug 01 04:22:47 PM PDT 24
Finished Aug 01 04:57:45 PM PDT 24
Peak memory 189724 kb
Host smart-a30baa6d-87c6-4f68-8aa1-19aec3957bd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512699672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
1512699672
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/76.rv_timer_random.2204728240
Short name T90
Test name
Test status
Simulation time 148983558651 ps
CPU time 242.75 seconds
Started Aug 01 04:23:27 PM PDT 24
Finished Aug 01 04:27:30 PM PDT 24
Peak memory 189436 kb
Host smart-42d12e80-3f60-48c7-9ecb-266c74ed3b72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204728240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.2204728240
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.3250906440
Short name T205
Test name
Test status
Simulation time 1031560392642 ps
CPU time 1071.43 seconds
Started Aug 01 04:23:03 PM PDT 24
Finished Aug 01 04:40:55 PM PDT 24
Peak memory 191144 kb
Host smart-1d74298f-e410-4bc9-a777-40e8ece30c64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250906440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.3250906440
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.2235314085
Short name T235
Test name
Test status
Simulation time 2124816409844 ps
CPU time 1075.72 seconds
Started Aug 01 04:17:45 PM PDT 24
Finished Aug 01 04:35:41 PM PDT 24
Peak memory 183352 kb
Host smart-1546610f-42b9-443c-a520-50082de7e4cb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235314085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.2235314085
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.176536762
Short name T221
Test name
Test status
Simulation time 1387829377818 ps
CPU time 1241.71 seconds
Started Aug 01 04:23:08 PM PDT 24
Finished Aug 01 04:43:50 PM PDT 24
Peak memory 195460 kb
Host smart-2a519716-e675-4dfa-8f38-fbd204a99d7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176536762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all.
176536762
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.3771812798
Short name T284
Test name
Test status
Simulation time 1105513244105 ps
CPU time 741.1 seconds
Started Aug 01 04:19:35 PM PDT 24
Finished Aug 01 04:31:57 PM PDT 24
Peak memory 191516 kb
Host smart-539d4f57-84bb-4ca6-b486-7351e85b2448
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771812798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.3771812798
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.2634981169
Short name T202
Test name
Test status
Simulation time 561925616043 ps
CPU time 487.26 seconds
Started Aug 01 04:23:03 PM PDT 24
Finished Aug 01 04:31:11 PM PDT 24
Peak memory 182944 kb
Host smart-5aa864c7-2ef4-4b1f-af80-81fc17b1b36f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634981169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.2634981169
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/84.rv_timer_random.554617354
Short name T150
Test name
Test status
Simulation time 767959134931 ps
CPU time 503.32 seconds
Started Aug 01 04:22:10 PM PDT 24
Finished Aug 01 04:30:33 PM PDT 24
Peak memory 191608 kb
Host smart-4c81b150-dc12-45b9-b3bc-b3dda3ed6d38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554617354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.554617354
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.584460822
Short name T110
Test name
Test status
Simulation time 492291561459 ps
CPU time 400.71 seconds
Started Aug 01 04:23:23 PM PDT 24
Finished Aug 01 04:30:04 PM PDT 24
Peak memory 191400 kb
Host smart-1b2b1933-0452-4b95-a38b-7e3abd2abd57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584460822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.584460822
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.1751964119
Short name T336
Test name
Test status
Simulation time 274097621333 ps
CPU time 554.72 seconds
Started Aug 01 04:23:24 PM PDT 24
Finished Aug 01 04:32:39 PM PDT 24
Peak memory 191468 kb
Host smart-f9e897ef-a218-429d-ae2b-e4aeb838696b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751964119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.1751964119
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random.790623775
Short name T161
Test name
Test status
Simulation time 112532134675 ps
CPU time 1570.1 seconds
Started Aug 01 04:22:51 PM PDT 24
Finished Aug 01 04:49:02 PM PDT 24
Peak memory 191176 kb
Host smart-2297e3e9-2c53-48ab-ad89-00843bed4cc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790623775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.790623775
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.2434683167
Short name T283
Test name
Test status
Simulation time 86213999062 ps
CPU time 451.19 seconds
Started Aug 01 04:23:40 PM PDT 24
Finished Aug 01 04:31:12 PM PDT 24
Peak memory 191388 kb
Host smart-0f841cd3-7d64-4f87-b699-6e8526b8ffea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434683167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.2434683167
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random.446229435
Short name T111
Test name
Test status
Simulation time 255245919169 ps
CPU time 559.48 seconds
Started Aug 01 04:22:43 PM PDT 24
Finished Aug 01 04:32:03 PM PDT 24
Peak memory 191592 kb
Host smart-0b7a0014-be7e-4cf9-925c-605611f78314
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446229435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.446229435
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.1091131412
Short name T68
Test name
Test status
Simulation time 20538150 ps
CPU time 0.78 seconds
Started Aug 01 04:54:07 PM PDT 24
Finished Aug 01 04:54:08 PM PDT 24
Peak memory 182736 kb
Host smart-a17aa473-d1e2-4b45-b82e-2729acbfc10b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091131412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.1091131412
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/default/118.rv_timer_random.1589867760
Short name T176
Test name
Test status
Simulation time 188044801125 ps
CPU time 446.92 seconds
Started Aug 01 04:23:13 PM PDT 24
Finished Aug 01 04:30:40 PM PDT 24
Peak memory 191436 kb
Host smart-bab863cb-4a4c-4d56-8d40-98683a12f7ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589867760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.1589867760
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/130.rv_timer_random.488122739
Short name T10
Test name
Test status
Simulation time 104935570553 ps
CPU time 164.41 seconds
Started Aug 01 04:23:23 PM PDT 24
Finished Aug 01 04:26:08 PM PDT 24
Peak memory 191464 kb
Host smart-64f49009-2ff2-4b89-9ce0-8a521b32dde1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488122739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.488122739
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random.3847695197
Short name T229
Test name
Test status
Simulation time 390391222440 ps
CPU time 189.37 seconds
Started Aug 01 04:23:18 PM PDT 24
Finished Aug 01 04:26:27 PM PDT 24
Peak memory 191168 kb
Host smart-ab7470d7-878a-43b2-9212-3b194bfd2c91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847695197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.3847695197
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random.1195257666
Short name T244
Test name
Test status
Simulation time 181878067067 ps
CPU time 476.9 seconds
Started Aug 01 04:22:29 PM PDT 24
Finished Aug 01 04:30:26 PM PDT 24
Peak memory 193200 kb
Host smart-92c57c0b-6c56-46e6-b4b4-9ae54348beea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195257666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.1195257666
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random.2540206656
Short name T224
Test name
Test status
Simulation time 314198928466 ps
CPU time 526.52 seconds
Started Aug 01 04:18:18 PM PDT 24
Finished Aug 01 04:27:04 PM PDT 24
Peak memory 191848 kb
Host smart-0517019c-e557-4894-b902-fcded997a26e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540206656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.2540206656
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.3607223808
Short name T269
Test name
Test status
Simulation time 192305792879 ps
CPU time 723.15 seconds
Started Aug 01 04:23:20 PM PDT 24
Finished Aug 01 04:35:24 PM PDT 24
Peak memory 191148 kb
Host smart-57ab9bfa-9b35-45e7-96a0-463f24e07943
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607223808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.3607223808
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random.3585446057
Short name T3
Test name
Test status
Simulation time 375054572383 ps
CPU time 261.8 seconds
Started Aug 01 04:22:39 PM PDT 24
Finished Aug 01 04:27:01 PM PDT 24
Peak memory 191012 kb
Host smart-02484332-a45f-45b6-b25a-f012b508edba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585446057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.3585446057
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.4124490089
Short name T223
Test name
Test status
Simulation time 451393812603 ps
CPU time 762.4 seconds
Started Aug 01 04:23:23 PM PDT 24
Finished Aug 01 04:36:06 PM PDT 24
Peak memory 191452 kb
Host smart-e11af68d-5556-4f17-9c7c-e6bd49c0c1aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124490089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.4124490089
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/150.rv_timer_random.1329506208
Short name T251
Test name
Test status
Simulation time 380503026935 ps
CPU time 390.16 seconds
Started Aug 01 04:23:27 PM PDT 24
Finished Aug 01 04:29:57 PM PDT 24
Peak memory 191388 kb
Host smart-ee7447e7-24bc-4c9d-83b6-8a81078c85ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329506208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.1329506208
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.3360541245
Short name T172
Test name
Test status
Simulation time 186093761059 ps
CPU time 268.13 seconds
Started Aug 01 04:23:39 PM PDT 24
Finished Aug 01 04:28:07 PM PDT 24
Peak memory 191404 kb
Host smart-ecc4354d-e6bc-4719-b934-64a4b84c5d77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360541245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.3360541245
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.3165136101
Short name T320
Test name
Test status
Simulation time 520762925126 ps
CPU time 1256.16 seconds
Started Aug 01 04:22:29 PM PDT 24
Finished Aug 01 04:43:26 PM PDT 24
Peak memory 191216 kb
Host smart-400627e3-e8b8-4215-ae44-684926921fb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165136101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.3165136101
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_random.1751595927
Short name T218
Test name
Test status
Simulation time 109822981017 ps
CPU time 441.38 seconds
Started Aug 01 04:22:39 PM PDT 24
Finished Aug 01 04:30:00 PM PDT 24
Peak memory 182944 kb
Host smart-33d91254-038e-43e3-99e9-db2c6d944178
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751595927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.1751595927
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random.4114243867
Short name T22
Test name
Test status
Simulation time 105029573713 ps
CPU time 883.23 seconds
Started Aug 01 04:22:25 PM PDT 24
Finished Aug 01 04:37:09 PM PDT 24
Peak memory 190676 kb
Host smart-b8cac8f9-ee38-48aa-92af-6cd9bcfdfd20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114243867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.4114243867
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.1903551031
Short name T354
Test name
Test status
Simulation time 1950050386682 ps
CPU time 1363.04 seconds
Started Aug 01 04:22:42 PM PDT 24
Finished Aug 01 04:45:26 PM PDT 24
Peak memory 190600 kb
Host smart-e117f3fd-805e-479a-8c79-8e7d825557f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903551031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.1903551031
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/103.rv_timer_random.2803604680
Short name T290
Test name
Test status
Simulation time 122529483206 ps
CPU time 92.27 seconds
Started Aug 01 04:23:12 PM PDT 24
Finished Aug 01 04:24:44 PM PDT 24
Peak memory 191408 kb
Host smart-be9198e4-ca6b-42b8-9b96-03418e3c8740
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803604680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.2803604680
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.3125732979
Short name T274
Test name
Test status
Simulation time 299672304944 ps
CPU time 504.99 seconds
Started Aug 01 04:22:30 PM PDT 24
Finished Aug 01 04:30:55 PM PDT 24
Peak memory 182952 kb
Host smart-a5f2e03d-a4af-4d54-9246-0f1a1dd09048
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125732979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.3125732979
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/145.rv_timer_random.441277838
Short name T170
Test name
Test status
Simulation time 87481619236 ps
CPU time 226.39 seconds
Started Aug 01 04:23:25 PM PDT 24
Finished Aug 01 04:27:11 PM PDT 24
Peak memory 194332 kb
Host smart-b5a90a8b-399c-47e0-b604-fa3c73b659ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441277838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.441277838
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.2781222938
Short name T93
Test name
Test status
Simulation time 25378059977 ps
CPU time 42.73 seconds
Started Aug 01 04:23:36 PM PDT 24
Finished Aug 01 04:24:19 PM PDT 24
Peak memory 191848 kb
Host smart-93961051-9fe4-4579-934b-866fd2ce7dfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781222938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.2781222938
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.1624830745
Short name T174
Test name
Test status
Simulation time 621256157297 ps
CPU time 693.58 seconds
Started Aug 01 04:23:40 PM PDT 24
Finished Aug 01 04:35:14 PM PDT 24
Peak memory 191352 kb
Host smart-5b213160-b6c0-4896-a618-bd5a5a0a4607
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624830745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.1624830745
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.301716759
Short name T328
Test name
Test status
Simulation time 7876091312 ps
CPU time 7.71 seconds
Started Aug 01 04:23:18 PM PDT 24
Finished Aug 01 04:23:26 PM PDT 24
Peak memory 182936 kb
Host smart-f4f001e8-69f3-409f-b8e4-813eb6b56b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301716759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.301716759
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.3446623545
Short name T78
Test name
Test status
Simulation time 49234610 ps
CPU time 0.67 seconds
Started Aug 01 04:54:07 PM PDT 24
Finished Aug 01 04:54:08 PM PDT 24
Peak memory 192360 kb
Host smart-819c2347-d3e3-4a27-8191-b738aa526886
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446623545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.3446623545
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.3592039490
Short name T197
Test name
Test status
Simulation time 508842159060 ps
CPU time 779.72 seconds
Started Aug 01 04:23:07 PM PDT 24
Finished Aug 01 04:36:07 PM PDT 24
Peak memory 190160 kb
Host smart-4f376b5a-3d1b-40ce-8811-31ccf8f81281
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592039490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
3592039490
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/105.rv_timer_random.1928630848
Short name T94
Test name
Test status
Simulation time 301767145178 ps
CPU time 136.16 seconds
Started Aug 01 04:23:12 PM PDT 24
Finished Aug 01 04:25:29 PM PDT 24
Peak memory 193628 kb
Host smart-dba49526-bb19-4c38-8df1-09d6d7435381
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928630848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.1928630848
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.3584150203
Short name T145
Test name
Test status
Simulation time 305944016154 ps
CPU time 140.35 seconds
Started Aug 01 04:23:12 PM PDT 24
Finished Aug 01 04:25:33 PM PDT 24
Peak memory 191428 kb
Host smart-04fe6587-9eb1-4612-89f0-9e0e7fc1286f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584150203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.3584150203
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.124882544
Short name T238
Test name
Test status
Simulation time 513850367815 ps
CPU time 364.25 seconds
Started Aug 01 04:23:10 PM PDT 24
Finished Aug 01 04:29:14 PM PDT 24
Peak memory 191408 kb
Host smart-2bcdd9ed-81f2-445c-99bf-751c2713721e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124882544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.124882544
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.1793056569
Short name T263
Test name
Test status
Simulation time 482351090470 ps
CPU time 246.79 seconds
Started Aug 01 04:23:24 PM PDT 24
Finished Aug 01 04:27:31 PM PDT 24
Peak memory 191416 kb
Host smart-b3502503-2507-44b3-99a9-e925208949a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793056569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.1793056569
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.3701734802
Short name T321
Test name
Test status
Simulation time 457985533750 ps
CPU time 239.54 seconds
Started Aug 01 04:23:25 PM PDT 24
Finished Aug 01 04:27:24 PM PDT 24
Peak memory 193484 kb
Host smart-02a04f07-6f3c-4336-81fd-b1c3c59223b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701734802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.3701734802
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.770218604
Short name T195
Test name
Test status
Simulation time 369547997433 ps
CPU time 1316.88 seconds
Started Aug 01 04:23:26 PM PDT 24
Finished Aug 01 04:45:23 PM PDT 24
Peak memory 191388 kb
Host smart-4e478ee2-bc2c-4f86-94a4-2e83225fb3c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770218604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.770218604
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.178020927
Short name T132
Test name
Test status
Simulation time 65503355776 ps
CPU time 75.89 seconds
Started Aug 01 04:19:24 PM PDT 24
Finished Aug 01 04:20:40 PM PDT 24
Peak memory 183248 kb
Host smart-d01a2a5c-3d31-4f2a-a657-a81761140208
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178020927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.rv_timer_cfg_update_on_fly.178020927
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.2070502489
Short name T100
Test name
Test status
Simulation time 3837315032978 ps
CPU time 1252.25 seconds
Started Aug 01 04:22:48 PM PDT 24
Finished Aug 01 04:43:41 PM PDT 24
Peak memory 183184 kb
Host smart-ec587c7e-3753-4e37-838d-bbf150cc2dcd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070502489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.2070502489
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/186.rv_timer_random.1731119974
Short name T143
Test name
Test status
Simulation time 650155023913 ps
CPU time 2472.35 seconds
Started Aug 01 04:23:40 PM PDT 24
Finished Aug 01 05:04:53 PM PDT 24
Peak memory 191372 kb
Host smart-1be95e3e-9214-40d8-ac4a-ea143023f0b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731119974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.1731119974
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.2275676964
Short name T131
Test name
Test status
Simulation time 191601182109 ps
CPU time 88.88 seconds
Started Aug 01 04:23:39 PM PDT 24
Finished Aug 01 04:25:08 PM PDT 24
Peak memory 191052 kb
Host smart-cc95cd86-cf7f-4a71-ab36-a6d80471d4b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275676964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.2275676964
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.2685126249
Short name T101
Test name
Test status
Simulation time 146473975577 ps
CPU time 257.77 seconds
Started Aug 01 04:23:39 PM PDT 24
Finished Aug 01 04:27:58 PM PDT 24
Peak memory 191436 kb
Host smart-75516210-0b3f-42b0-8e11-dbc06adac0da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685126249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.2685126249
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random.2404959664
Short name T314
Test name
Test status
Simulation time 476834501845 ps
CPU time 301.33 seconds
Started Aug 01 04:20:46 PM PDT 24
Finished Aug 01 04:25:48 PM PDT 24
Peak memory 189176 kb
Host smart-83a81b3b-ffa4-40c2-9818-1bd7f231b343
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404959664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.2404959664
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.3095179828
Short name T446
Test name
Test status
Simulation time 439998995246 ps
CPU time 517.56 seconds
Started Aug 01 04:22:52 PM PDT 24
Finished Aug 01 04:31:30 PM PDT 24
Peak memory 191148 kb
Host smart-ca8ce4c4-d98a-46dc-a6ed-a9efe99c24c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095179828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.3095179828
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/50.rv_timer_random.3565241652
Short name T227
Test name
Test status
Simulation time 149879038100 ps
CPU time 113.18 seconds
Started Aug 01 04:23:02 PM PDT 24
Finished Aug 01 04:24:56 PM PDT 24
Peak memory 194696 kb
Host smart-334a5b70-5d22-4321-9c03-4effcd830bf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565241652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.3565241652
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.1759032695
Short name T122
Test name
Test status
Simulation time 153461547400 ps
CPU time 1939.96 seconds
Started Aug 01 04:23:23 PM PDT 24
Finished Aug 01 04:55:44 PM PDT 24
Peak memory 191400 kb
Host smart-f5f8cddd-92fd-45df-8978-f65ea9e7663c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759032695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.1759032695
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/80.rv_timer_random.4274275605
Short name T254
Test name
Test status
Simulation time 793019764965 ps
CPU time 686 seconds
Started Aug 01 04:22:06 PM PDT 24
Finished Aug 01 04:33:32 PM PDT 24
Peak memory 191576 kb
Host smart-843a85cb-99f7-4e68-80e0-84ed793a013e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274275605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.4274275605
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1685952002
Short name T84
Test name
Test status
Simulation time 103989503 ps
CPU time 1.36 seconds
Started Aug 01 04:54:07 PM PDT 24
Finished Aug 01 04:54:09 PM PDT 24
Peak memory 195044 kb
Host smart-192431e6-4f36-4cd5-8b46-22e1a1d8e511
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685952002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.1685952002
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/11.rv_timer_random.2804985938
Short name T242
Test name
Test status
Simulation time 163328281191 ps
CPU time 200.98 seconds
Started Aug 01 04:22:59 PM PDT 24
Finished Aug 01 04:26:20 PM PDT 24
Peak memory 183244 kb
Host smart-8a1b0804-61a2-4192-851a-bde4ed01d3c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804985938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.2804985938
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.431129965
Short name T294
Test name
Test status
Simulation time 78029358013 ps
CPU time 146.48 seconds
Started Aug 01 04:23:11 PM PDT 24
Finished Aug 01 04:25:37 PM PDT 24
Peak memory 191588 kb
Host smart-ab7e90d4-e382-4b0b-907b-767229b69e21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431129965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.431129965
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.104129005
Short name T167
Test name
Test status
Simulation time 54219209237 ps
CPU time 173.53 seconds
Started Aug 01 04:23:29 PM PDT 24
Finished Aug 01 04:26:22 PM PDT 24
Peak memory 191428 kb
Host smart-261c0bf8-0752-4fe8-880f-b7205a2027bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104129005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.104129005
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random.2865037971
Short name T104
Test name
Test status
Simulation time 561817175588 ps
CPU time 806.4 seconds
Started Aug 01 04:22:37 PM PDT 24
Finished Aug 01 04:36:04 PM PDT 24
Peak memory 190336 kb
Host smart-5071c98d-7166-4bf3-8820-37cbc75297c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865037971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.2865037971
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.1408601153
Short name T106
Test name
Test status
Simulation time 338416213797 ps
CPU time 341.82 seconds
Started Aug 01 04:23:29 PM PDT 24
Finished Aug 01 04:29:11 PM PDT 24
Peak memory 194820 kb
Host smart-3e4f6617-d52a-42a2-8735-893dab404523
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408601153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.1408601153
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/140.rv_timer_random.4163166718
Short name T237
Test name
Test status
Simulation time 123117570477 ps
CPU time 223.55 seconds
Started Aug 01 04:23:22 PM PDT 24
Finished Aug 01 04:27:06 PM PDT 24
Peak memory 191444 kb
Host smart-a1a15269-c6d3-4947-ab0f-dd9da3aa9f9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163166718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.4163166718
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.4140591873
Short name T88
Test name
Test status
Simulation time 180243488316 ps
CPU time 298.96 seconds
Started Aug 01 04:23:27 PM PDT 24
Finished Aug 01 04:28:26 PM PDT 24
Peak memory 191380 kb
Host smart-424be018-5aef-416b-a9e3-edd7ba8950eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140591873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.4140591873
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/160.rv_timer_random.3991615607
Short name T247
Test name
Test status
Simulation time 129645659066 ps
CPU time 394.13 seconds
Started Aug 01 04:23:29 PM PDT 24
Finished Aug 01 04:30:04 PM PDT 24
Peak memory 194428 kb
Host smart-3a1eafd7-e3c2-4239-bb06-5ccf1649c8e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991615607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.3991615607
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.2482275513
Short name T287
Test name
Test status
Simulation time 285708596802 ps
CPU time 348.15 seconds
Started Aug 01 04:23:33 PM PDT 24
Finished Aug 01 04:29:21 PM PDT 24
Peak memory 191080 kb
Host smart-e356a5a2-b084-408d-91b8-5947fe04733e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482275513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.2482275513
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.1057774832
Short name T169
Test name
Test status
Simulation time 831334354900 ps
CPU time 1339.8 seconds
Started Aug 01 04:23:36 PM PDT 24
Finished Aug 01 04:45:56 PM PDT 24
Peak memory 191468 kb
Host smart-5f954a8e-f20d-41d4-9471-2be8800fbe11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057774832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.1057774832
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.2829867361
Short name T279
Test name
Test status
Simulation time 45702589708 ps
CPU time 430.59 seconds
Started Aug 01 04:23:35 PM PDT 24
Finished Aug 01 04:30:45 PM PDT 24
Peak memory 183208 kb
Host smart-f2b412d1-efea-474f-b8eb-baa597fd5897
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829867361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.2829867361
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/170.rv_timer_random.773826237
Short name T196
Test name
Test status
Simulation time 613721690160 ps
CPU time 815.81 seconds
Started Aug 01 04:23:40 PM PDT 24
Finished Aug 01 04:37:16 PM PDT 24
Peak memory 191428 kb
Host smart-2a9d235f-6acf-4dd7-b097-826be73b2f2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773826237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.773826237
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.957220125
Short name T26
Test name
Test status
Simulation time 770019959437 ps
CPU time 510.6 seconds
Started Aug 01 04:23:37 PM PDT 24
Finished Aug 01 04:32:08 PM PDT 24
Peak memory 191452 kb
Host smart-d5b2bcb8-9d75-4f4d-b005-dfab0bfde60f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957220125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.957220125
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.282582298
Short name T188
Test name
Test status
Simulation time 23709576707 ps
CPU time 38.3 seconds
Started Aug 01 04:23:36 PM PDT 24
Finished Aug 01 04:24:15 PM PDT 24
Peak memory 183224 kb
Host smart-6fd55dda-4975-41b5-86ec-cc3f4a768877
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282582298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.282582298
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.1042150600
Short name T173
Test name
Test status
Simulation time 373172144931 ps
CPU time 572.43 seconds
Started Aug 01 04:22:54 PM PDT 24
Finished Aug 01 04:32:27 PM PDT 24
Peak memory 182936 kb
Host smart-47973ae4-cd5e-4fa6-a990-a4ada760c746
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042150600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.1042150600
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/194.rv_timer_random.3064149141
Short name T209
Test name
Test status
Simulation time 111463995746 ps
CPU time 533.98 seconds
Started Aug 01 04:23:40 PM PDT 24
Finished Aug 01 04:32:35 PM PDT 24
Peak memory 191416 kb
Host smart-0ff98fcb-351e-4746-9b5d-b1a30828936f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064149141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.3064149141
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.82595946
Short name T153
Test name
Test status
Simulation time 63817491302 ps
CPU time 32.11 seconds
Started Aug 01 04:23:57 PM PDT 24
Finished Aug 01 04:24:29 PM PDT 24
Peak memory 195276 kb
Host smart-f3f7818d-ec03-4295-8770-e1936d1bca51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82595946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.82595946
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.1201371052
Short name T347
Test name
Test status
Simulation time 146193460745 ps
CPU time 232.04 seconds
Started Aug 01 04:18:15 PM PDT 24
Finished Aug 01 04:22:07 PM PDT 24
Peak memory 183220 kb
Host smart-7aeca034-0520-45ad-ac12-fb53e828f181
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201371052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.1201371052
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.381629453
Short name T199
Test name
Test status
Simulation time 245916816203 ps
CPU time 261.84 seconds
Started Aug 01 04:18:33 PM PDT 24
Finished Aug 01 04:22:55 PM PDT 24
Peak memory 191848 kb
Host smart-963ef8f9-0a79-49be-9939-6463cbaaec6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381629453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all.
381629453
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.2678909345
Short name T302
Test name
Test status
Simulation time 731204809542 ps
CPU time 162.37 seconds
Started Aug 01 04:22:40 PM PDT 24
Finished Aug 01 04:25:23 PM PDT 24
Peak memory 182408 kb
Host smart-84bd73f3-9462-4db4-b5ed-06490c5a98bf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678909345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.2678909345
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.312441263
Short name T226
Test name
Test status
Simulation time 83098480794 ps
CPU time 167.94 seconds
Started Aug 01 04:20:46 PM PDT 24
Finished Aug 01 04:23:35 PM PDT 24
Peak memory 180364 kb
Host smart-0f907bc5-1c43-4252-9f4b-a9d53c79ac1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312441263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.312441263
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_random.1156648115
Short name T99
Test name
Test status
Simulation time 588785246987 ps
CPU time 274.36 seconds
Started Aug 01 04:22:38 PM PDT 24
Finished Aug 01 04:27:13 PM PDT 24
Peak memory 191116 kb
Host smart-46a80cd3-1083-4630-b93d-238c6048292e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156648115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.1156648115
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.2603419348
Short name T159
Test name
Test status
Simulation time 81297835169 ps
CPU time 138.7 seconds
Started Aug 01 04:18:53 PM PDT 24
Finished Aug 01 04:21:12 PM PDT 24
Peak memory 183228 kb
Host smart-38976f90-1d3e-483a-bea7-a114dd71f420
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603419348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.2603419348
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_random.2234545444
Short name T189
Test name
Test status
Simulation time 111112475600 ps
CPU time 186.15 seconds
Started Aug 01 04:22:53 PM PDT 24
Finished Aug 01 04:25:59 PM PDT 24
Peak memory 190504 kb
Host smart-b204a240-785d-48b6-8e6b-0df230514c89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234545444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.2234545444
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random.1148034977
Short name T270
Test name
Test status
Simulation time 101999943527 ps
CPU time 165.71 seconds
Started Aug 01 04:21:42 PM PDT 24
Finished Aug 01 04:24:28 PM PDT 24
Peak memory 191580 kb
Host smart-eff4cc27-4117-425f-9bd5-3e4a5f1443bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148034977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.1148034977
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random.1813162923
Short name T299
Test name
Test status
Simulation time 238666690748 ps
CPU time 169.36 seconds
Started Aug 01 04:23:19 PM PDT 24
Finished Aug 01 04:26:09 PM PDT 24
Peak memory 189804 kb
Host smart-6f3380a3-4387-43a8-8d03-dceddb898357
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813162923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.1813162923
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random.2927475419
Short name T148
Test name
Test status
Simulation time 31108151584 ps
CPU time 55.79 seconds
Started Aug 01 04:22:42 PM PDT 24
Finished Aug 01 04:23:39 PM PDT 24
Peak memory 182412 kb
Host smart-2a19e57c-9b6d-4b6a-aa96-8b30058fe135
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927475419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.2927475419
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.3069323405
Short name T268
Test name
Test status
Simulation time 82501232150 ps
CPU time 123.65 seconds
Started Aug 01 04:22:42 PM PDT 24
Finished Aug 01 04:24:46 PM PDT 24
Peak memory 182368 kb
Host smart-5ba054c4-b53b-4843-89f2-574eecab7dda
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069323405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.3069323405
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_random.1849935323
Short name T311
Test name
Test status
Simulation time 240627080935 ps
CPU time 145.92 seconds
Started Aug 01 04:23:36 PM PDT 24
Finished Aug 01 04:26:02 PM PDT 24
Peak memory 191104 kb
Host smart-feed781b-1e8c-4df4-9779-1931fd4c74d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849935323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.1849935323
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.2499692569
Short name T241
Test name
Test status
Simulation time 538743593443 ps
CPU time 302.86 seconds
Started Aug 01 04:23:26 PM PDT 24
Finished Aug 01 04:28:29 PM PDT 24
Peak memory 183248 kb
Host smart-5d67d854-ce3d-40b4-8baf-6dd0a7f6e8fa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499692569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.2499692569
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/70.rv_timer_random.1357817906
Short name T96
Test name
Test status
Simulation time 567731907598 ps
CPU time 517.43 seconds
Started Aug 01 04:21:55 PM PDT 24
Finished Aug 01 04:30:32 PM PDT 24
Peak memory 191452 kb
Host smart-602187a2-8063-4591-9487-8370256f7f20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357817906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.1357817906
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.2500185042
Short name T47
Test name
Test status
Simulation time 334945858967 ps
CPU time 402.91 seconds
Started Aug 01 04:24:01 PM PDT 24
Finished Aug 01 04:30:44 PM PDT 24
Peak memory 191144 kb
Host smart-0780b8aa-25a4-44db-b147-a335646ad090
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500185042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.2500185042
Directory /workspace/99.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.2242917702
Short name T83
Test name
Test status
Simulation time 63766008 ps
CPU time 2.39 seconds
Started Aug 01 04:54:06 PM PDT 24
Finished Aug 01 04:54:08 PM PDT 24
Peak memory 193608 kb
Host smart-77646cb3-7d78-4bd1-8da4-90ec2b8f729a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242917702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.2242917702
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.2587998321
Short name T481
Test name
Test status
Simulation time 38881379 ps
CPU time 0.55 seconds
Started Aug 01 04:54:06 PM PDT 24
Finished Aug 01 04:54:07 PM PDT 24
Peak memory 182716 kb
Host smart-6739ca38-9d72-4752-b874-0fd9d185ec99
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587998321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.2587998321
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.629214836
Short name T478
Test name
Test status
Simulation time 60054433 ps
CPU time 0.79 seconds
Started Aug 01 04:54:06 PM PDT 24
Finished Aug 01 04:54:07 PM PDT 24
Peak memory 196716 kb
Host smart-f16ff048-01db-4766-bdc4-adbd592dddc3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629214836 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.629214836
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.2305698606
Short name T506
Test name
Test status
Simulation time 21547681 ps
CPU time 0.57 seconds
Started Aug 01 04:54:08 PM PDT 24
Finished Aug 01 04:54:09 PM PDT 24
Peak memory 182744 kb
Host smart-6cca3d60-7cf8-45d6-9319-e6402ccbbb90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305698606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.2305698606
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.708479407
Short name T556
Test name
Test status
Simulation time 21927262 ps
CPU time 0.55 seconds
Started Aug 01 04:54:07 PM PDT 24
Finished Aug 01 04:54:08 PM PDT 24
Peak memory 182088 kb
Host smart-bcffd1c4-b097-4d03-9c5e-ac0270fe1d2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708479407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.708479407
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2463224607
Short name T573
Test name
Test status
Simulation time 128301712 ps
CPU time 1.86 seconds
Started Aug 01 04:54:08 PM PDT 24
Finished Aug 01 04:54:10 PM PDT 24
Peak memory 197488 kb
Host smart-6eaf2418-9f4b-4858-9fbd-ceea3aa47c17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463224607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.2463224607
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.962802821
Short name T74
Test name
Test status
Simulation time 72677548 ps
CPU time 0.66 seconds
Started Aug 01 04:54:07 PM PDT 24
Finished Aug 01 04:54:08 PM PDT 24
Peak memory 192140 kb
Host smart-57b62d12-06e7-43b2-9960-0bc445bc64cb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962802821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alias
ing.962802821
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.1842421018
Short name T578
Test name
Test status
Simulation time 1248212038 ps
CPU time 3.45 seconds
Started Aug 01 04:54:06 PM PDT 24
Finished Aug 01 04:54:10 PM PDT 24
Peak memory 192392 kb
Host smart-0f5ea2db-a0a1-4b0a-8cfe-b6a6a6d48861
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842421018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.1842421018
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.2707580217
Short name T538
Test name
Test status
Simulation time 16478156 ps
CPU time 0.6 seconds
Started Aug 01 04:54:08 PM PDT 24
Finished Aug 01 04:54:09 PM PDT 24
Peak memory 182792 kb
Host smart-c386daca-a067-451e-b0c6-7b739ce09647
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707580217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.2707580217
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.2817176175
Short name T568
Test name
Test status
Simulation time 84268268 ps
CPU time 0.94 seconds
Started Aug 01 04:54:05 PM PDT 24
Finished Aug 01 04:54:06 PM PDT 24
Peak memory 196428 kb
Host smart-ea6fae47-f311-4146-bde7-53ccc7f305aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817176175 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.2817176175
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.348972645
Short name T472
Test name
Test status
Simulation time 32783555 ps
CPU time 0.56 seconds
Started Aug 01 04:54:07 PM PDT 24
Finished Aug 01 04:54:07 PM PDT 24
Peak memory 182524 kb
Host smart-44db4fb5-3511-49ed-8bab-3b46d4e1549d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348972645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.348972645
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.877709785
Short name T528
Test name
Test status
Simulation time 30742477 ps
CPU time 0.56 seconds
Started Aug 01 04:54:08 PM PDT 24
Finished Aug 01 04:54:08 PM PDT 24
Peak memory 182528 kb
Host smart-a8f3c461-a991-43d6-8822-5a2bcc6dbe12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877709785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.877709785
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.4202331837
Short name T62
Test name
Test status
Simulation time 48642598 ps
CPU time 0.66 seconds
Started Aug 01 04:54:07 PM PDT 24
Finished Aug 01 04:54:08 PM PDT 24
Peak memory 191704 kb
Host smart-8f33d85e-eda8-49a5-83a1-bdd6e9025d00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202331837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.4202331837
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.1395015887
Short name T561
Test name
Test status
Simulation time 53387951 ps
CPU time 2.78 seconds
Started Aug 01 04:54:06 PM PDT 24
Finished Aug 01 04:54:09 PM PDT 24
Peak memory 197504 kb
Host smart-9b0085e1-20f8-4cd0-bd60-12b1d51d249e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395015887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.1395015887
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3225772896
Short name T494
Test name
Test status
Simulation time 50537903 ps
CPU time 0.77 seconds
Started Aug 01 04:54:08 PM PDT 24
Finished Aug 01 04:54:09 PM PDT 24
Peak memory 183120 kb
Host smart-3f1c5a91-5717-481b-be04-540054a480f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225772896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.3225772896
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.2368973411
Short name T493
Test name
Test status
Simulation time 78940955 ps
CPU time 0.84 seconds
Started Aug 01 04:54:29 PM PDT 24
Finished Aug 01 04:54:30 PM PDT 24
Peak memory 196980 kb
Host smart-40e4d57e-b909-4c0b-b8f2-d95871cf3369
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368973411 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.2368973411
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.2586808721
Short name T477
Test name
Test status
Simulation time 13054682 ps
CPU time 0.58 seconds
Started Aug 01 04:54:30 PM PDT 24
Finished Aug 01 04:54:30 PM PDT 24
Peak memory 182880 kb
Host smart-f088e845-072f-4691-8293-dfd5340c6c6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586808721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.2586808721
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1671821081
Short name T457
Test name
Test status
Simulation time 13707310 ps
CPU time 0.59 seconds
Started Aug 01 04:54:28 PM PDT 24
Finished Aug 01 04:54:29 PM PDT 24
Peak memory 182244 kb
Host smart-75efc47f-251a-4094-8784-8401542acce9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671821081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.1671821081
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.824914612
Short name T560
Test name
Test status
Simulation time 62688875 ps
CPU time 0.69 seconds
Started Aug 01 04:54:31 PM PDT 24
Finished Aug 01 04:54:31 PM PDT 24
Peak memory 193152 kb
Host smart-19a70a7e-0307-4506-a834-62dc3edece50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824914612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_ti
mer_same_csr_outstanding.824914612
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1629355573
Short name T564
Test name
Test status
Simulation time 98475721 ps
CPU time 2.47 seconds
Started Aug 01 04:54:29 PM PDT 24
Finished Aug 01 04:54:31 PM PDT 24
Peak memory 197528 kb
Host smart-3134047c-7015-4e0c-b36d-4753af218fe6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629355573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.1629355573
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1204977653
Short name T541
Test name
Test status
Simulation time 468224522 ps
CPU time 1.1 seconds
Started Aug 01 04:54:29 PM PDT 24
Finished Aug 01 04:54:30 PM PDT 24
Peak memory 183528 kb
Host smart-45268449-944c-4c23-a642-cab3c9b8e441
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204977653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.1204977653
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.3386574136
Short name T467
Test name
Test status
Simulation time 67693778 ps
CPU time 0.96 seconds
Started Aug 01 04:54:30 PM PDT 24
Finished Aug 01 04:54:32 PM PDT 24
Peak memory 196956 kb
Host smart-c1332b07-37b3-4f90-a2fc-ff75ec579bbf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386574136 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.3386574136
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.244915893
Short name T59
Test name
Test status
Simulation time 24872559 ps
CPU time 0.55 seconds
Started Aug 01 04:54:32 PM PDT 24
Finished Aug 01 04:54:33 PM PDT 24
Peak memory 182464 kb
Host smart-b8a139d0-59f0-4122-af0f-4180ae993021
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244915893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.244915893
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.392817430
Short name T570
Test name
Test status
Simulation time 22087104 ps
CPU time 0.53 seconds
Started Aug 01 04:54:29 PM PDT 24
Finished Aug 01 04:54:30 PM PDT 24
Peak memory 182400 kb
Host smart-d0567657-4620-477f-ad1e-45e326596dbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392817430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.392817430
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3521747814
Short name T495
Test name
Test status
Simulation time 67992036 ps
CPU time 0.68 seconds
Started Aug 01 04:54:29 PM PDT 24
Finished Aug 01 04:54:30 PM PDT 24
Peak memory 192276 kb
Host smart-6cc2e957-f953-48ed-8906-f95517f51196
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521747814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.3521747814
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.3209999565
Short name T492
Test name
Test status
Simulation time 359599251 ps
CPU time 2.25 seconds
Started Aug 01 04:54:29 PM PDT 24
Finished Aug 01 04:54:32 PM PDT 24
Peak memory 197520 kb
Host smart-9fe95f22-c416-48ce-b204-9dc2bcb22b14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209999565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.3209999565
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.2050896197
Short name T30
Test name
Test status
Simulation time 434717324 ps
CPU time 1.3 seconds
Started Aug 01 04:54:30 PM PDT 24
Finished Aug 01 04:54:31 PM PDT 24
Peak memory 195228 kb
Host smart-032a032a-3986-4201-8815-4d9c9656c422
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050896197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.2050896197
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.45603290
Short name T563
Test name
Test status
Simulation time 154173468 ps
CPU time 0.91 seconds
Started Aug 01 04:54:30 PM PDT 24
Finished Aug 01 04:54:32 PM PDT 24
Peak memory 196216 kb
Host smart-03b39d50-74cb-4be8-a875-df28109f7d5a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45603290 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.45603290
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2332212340
Short name T66
Test name
Test status
Simulation time 17313415 ps
CPU time 0.59 seconds
Started Aug 01 04:54:30 PM PDT 24
Finished Aug 01 04:54:31 PM PDT 24
Peak memory 182744 kb
Host smart-381ec083-7fc2-460b-a117-e2ccb639a8af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332212340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.2332212340
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.471875886
Short name T455
Test name
Test status
Simulation time 43074779 ps
CPU time 0.55 seconds
Started Aug 01 04:54:28 PM PDT 24
Finished Aug 01 04:54:29 PM PDT 24
Peak memory 182548 kb
Host smart-e9dc4cd8-53ec-41a6-a33a-707590aa287e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471875886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.471875886
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.4217402284
Short name T80
Test name
Test status
Simulation time 181893852 ps
CPU time 0.61 seconds
Started Aug 01 04:54:30 PM PDT 24
Finished Aug 01 04:54:31 PM PDT 24
Peak memory 191484 kb
Host smart-7814657d-452d-4a4d-9a78-ff0d93d065ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217402284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.4217402284
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.235689981
Short name T517
Test name
Test status
Simulation time 30402230 ps
CPU time 1.5 seconds
Started Aug 01 04:54:28 PM PDT 24
Finished Aug 01 04:54:30 PM PDT 24
Peak memory 197492 kb
Host smart-a78e9dca-bb74-4385-ad8e-a4a19f6d1ee7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235689981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.235689981
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.816326883
Short name T86
Test name
Test status
Simulation time 72354659 ps
CPU time 1.07 seconds
Started Aug 01 04:54:29 PM PDT 24
Finished Aug 01 04:54:31 PM PDT 24
Peak memory 183396 kb
Host smart-3c44c982-d3f0-40a4-8c7b-58cb2e4c89bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816326883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_in
tg_err.816326883
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.496357758
Short name T470
Test name
Test status
Simulation time 337636051 ps
CPU time 0.74 seconds
Started Aug 01 04:54:31 PM PDT 24
Finished Aug 01 04:54:32 PM PDT 24
Peak memory 194904 kb
Host smart-0b8b0523-7958-40fa-baaf-5e71f719e9f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496357758 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.496357758
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.192790882
Short name T562
Test name
Test status
Simulation time 44619117 ps
CPU time 0.55 seconds
Started Aug 01 04:54:30 PM PDT 24
Finished Aug 01 04:54:31 PM PDT 24
Peak memory 182920 kb
Host smart-5b53bd96-bec9-43e6-bc94-0075a067966b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192790882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.192790882
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.2858106406
Short name T484
Test name
Test status
Simulation time 15530473 ps
CPU time 0.56 seconds
Started Aug 01 04:54:29 PM PDT 24
Finished Aug 01 04:54:29 PM PDT 24
Peak memory 182604 kb
Host smart-a897d8a4-2d2e-468a-a8b2-f8b2c90086b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858106406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.2858106406
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.43668793
Short name T576
Test name
Test status
Simulation time 14673515 ps
CPU time 0.71 seconds
Started Aug 01 04:54:29 PM PDT 24
Finished Aug 01 04:54:30 PM PDT 24
Peak memory 192068 kb
Host smart-0e7ef5ea-cf05-4b02-8fc8-e7a4ff79050e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43668793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_tim
er_same_csr_outstanding.43668793
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.1508135223
Short name T554
Test name
Test status
Simulation time 242709763 ps
CPU time 1.78 seconds
Started Aug 01 04:54:29 PM PDT 24
Finished Aug 01 04:54:31 PM PDT 24
Peak memory 197504 kb
Host smart-50640b05-308e-408c-8b82-bfefe1c01221
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508135223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.1508135223
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.2216444120
Short name T29
Test name
Test status
Simulation time 92185385 ps
CPU time 1.07 seconds
Started Aug 01 04:54:29 PM PDT 24
Finished Aug 01 04:54:30 PM PDT 24
Peak memory 195364 kb
Host smart-8da2da5a-3a73-4d62-abed-df15db02aa5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216444120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.2216444120
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.4150578482
Short name T471
Test name
Test status
Simulation time 31412997 ps
CPU time 0.83 seconds
Started Aug 01 04:54:28 PM PDT 24
Finished Aug 01 04:54:29 PM PDT 24
Peak memory 196648 kb
Host smart-be88b0c8-ba7d-4bac-b04c-2b63c6ff0612
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150578482 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.4150578482
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3823054923
Short name T61
Test name
Test status
Simulation time 13260004 ps
CPU time 0.55 seconds
Started Aug 01 04:54:29 PM PDT 24
Finished Aug 01 04:54:30 PM PDT 24
Peak memory 182468 kb
Host smart-acedea6b-557a-48cd-b4dc-2c9dc959c099
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823054923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.3823054923
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.2357706142
Short name T500
Test name
Test status
Simulation time 14792419 ps
CPU time 0.55 seconds
Started Aug 01 04:54:30 PM PDT 24
Finished Aug 01 04:54:31 PM PDT 24
Peak memory 182652 kb
Host smart-71152bbc-64c2-4dad-9793-6f6a6f50b245
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357706142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.2357706142
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.2927512971
Short name T33
Test name
Test status
Simulation time 20475601 ps
CPU time 0.77 seconds
Started Aug 01 04:54:29 PM PDT 24
Finished Aug 01 04:54:30 PM PDT 24
Peak memory 191740 kb
Host smart-b029ab99-0084-4db6-8e90-602fb4af93d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927512971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.2927512971
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2563595432
Short name T454
Test name
Test status
Simulation time 112809761 ps
CPU time 2.83 seconds
Started Aug 01 04:54:29 PM PDT 24
Finished Aug 01 04:54:32 PM PDT 24
Peak memory 197512 kb
Host smart-ecdd0d3a-24df-4060-8404-37027ab81029
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563595432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.2563595432
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.3448491793
Short name T485
Test name
Test status
Simulation time 153477109 ps
CPU time 0.82 seconds
Started Aug 01 04:54:27 PM PDT 24
Finished Aug 01 04:54:28 PM PDT 24
Peak memory 183036 kb
Host smart-f578beb9-9e1a-4916-8371-9adf98e45742
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448491793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.3448491793
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1807820319
Short name T496
Test name
Test status
Simulation time 85682070 ps
CPU time 0.77 seconds
Started Aug 01 04:54:42 PM PDT 24
Finished Aug 01 04:54:43 PM PDT 24
Peak memory 195124 kb
Host smart-52842000-edc5-4213-a97a-04545b0214d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807820319 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.1807820319
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.2229258859
Short name T52
Test name
Test status
Simulation time 19543077 ps
CPU time 0.54 seconds
Started Aug 01 04:54:29 PM PDT 24
Finished Aug 01 04:54:30 PM PDT 24
Peak memory 182592 kb
Host smart-82ec9366-1726-4d52-a2b4-62dd7ce4ae80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229258859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.2229258859
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.3803897178
Short name T539
Test name
Test status
Simulation time 70761187 ps
CPU time 0.58 seconds
Started Aug 01 04:54:28 PM PDT 24
Finished Aug 01 04:54:29 PM PDT 24
Peak memory 182656 kb
Host smart-8e11f5c2-2263-48bf-baca-09fd750f5660
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803897178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.3803897178
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.2780847184
Short name T81
Test name
Test status
Simulation time 21584976 ps
CPU time 0.82 seconds
Started Aug 01 04:54:31 PM PDT 24
Finished Aug 01 04:54:32 PM PDT 24
Peak memory 191012 kb
Host smart-567e557e-1daa-434f-b04f-dd43495bab6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780847184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.2780847184
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1653139442
Short name T483
Test name
Test status
Simulation time 216262423 ps
CPU time 2.66 seconds
Started Aug 01 04:54:29 PM PDT 24
Finished Aug 01 04:54:32 PM PDT 24
Peak memory 197496 kb
Host smart-8f85d993-fe14-4951-8756-4cf3d8505751
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653139442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.1653139442
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.2478199177
Short name T553
Test name
Test status
Simulation time 449324817 ps
CPU time 1.39 seconds
Started Aug 01 04:54:29 PM PDT 24
Finished Aug 01 04:54:30 PM PDT 24
Peak memory 183224 kb
Host smart-da3dc56c-386f-43a4-8ec8-2af5e368a44c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478199177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.2478199177
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.4055172969
Short name T466
Test name
Test status
Simulation time 121372850 ps
CPU time 0.91 seconds
Started Aug 01 04:54:39 PM PDT 24
Finished Aug 01 04:54:40 PM PDT 24
Peak memory 197412 kb
Host smart-cf992705-5e11-4ab5-b072-78e655d5fef6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055172969 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.4055172969
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.2622798309
Short name T509
Test name
Test status
Simulation time 31326251 ps
CPU time 0.55 seconds
Started Aug 01 04:54:43 PM PDT 24
Finished Aug 01 04:54:44 PM PDT 24
Peak memory 182772 kb
Host smart-81648fb9-c91c-4398-bda8-c932d84e1cc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622798309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.2622798309
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.3369568530
Short name T511
Test name
Test status
Simulation time 12354334 ps
CPU time 0.56 seconds
Started Aug 01 04:54:43 PM PDT 24
Finished Aug 01 04:54:44 PM PDT 24
Peak memory 182596 kb
Host smart-cc3e9497-96ad-4c86-a167-5318ac77c26e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369568530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.3369568530
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.350558142
Short name T79
Test name
Test status
Simulation time 31873285 ps
CPU time 0.6 seconds
Started Aug 01 04:54:42 PM PDT 24
Finished Aug 01 04:54:42 PM PDT 24
Peak memory 191568 kb
Host smart-c2d90c86-fc1b-4914-ac9a-37f3e9294a44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350558142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_ti
mer_same_csr_outstanding.350558142
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.4083342867
Short name T579
Test name
Test status
Simulation time 43113676 ps
CPU time 1.14 seconds
Started Aug 01 04:54:39 PM PDT 24
Finished Aug 01 04:54:40 PM PDT 24
Peak memory 197532 kb
Host smart-90d822dd-3033-4d82-990e-305a8fb33eab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083342867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.4083342867
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.439240634
Short name T545
Test name
Test status
Simulation time 41726136 ps
CPU time 0.8 seconds
Started Aug 01 04:54:43 PM PDT 24
Finished Aug 01 04:54:44 PM PDT 24
Peak memory 193320 kb
Host smart-1a16ada7-3de8-4cfb-abf4-f12ef23f832e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439240634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_in
tg_err.439240634
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.448592292
Short name T479
Test name
Test status
Simulation time 21677513 ps
CPU time 0.72 seconds
Started Aug 01 04:54:41 PM PDT 24
Finished Aug 01 04:54:42 PM PDT 24
Peak memory 194704 kb
Host smart-793a2294-27e0-47fa-8fd7-0923f1ab5592
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448592292 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.448592292
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.2585178677
Short name T521
Test name
Test status
Simulation time 29128569 ps
CPU time 0.53 seconds
Started Aug 01 04:54:42 PM PDT 24
Finished Aug 01 04:54:42 PM PDT 24
Peak memory 182432 kb
Host smart-265bb37a-2860-465e-b48c-e0f6c56a119f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585178677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.2585178677
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3581661630
Short name T529
Test name
Test status
Simulation time 11383701 ps
CPU time 0.56 seconds
Started Aug 01 04:54:40 PM PDT 24
Finished Aug 01 04:54:41 PM PDT 24
Peak memory 182068 kb
Host smart-0b8c05dd-12f9-4095-9830-8f647085ae0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581661630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.3581661630
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.213953400
Short name T514
Test name
Test status
Simulation time 100906062 ps
CPU time 0.63 seconds
Started Aug 01 04:54:44 PM PDT 24
Finished Aug 01 04:54:45 PM PDT 24
Peak memory 192088 kb
Host smart-0cabeed5-d693-4824-9e04-91e76314d0b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213953400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_ti
mer_same_csr_outstanding.213953400
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.706511586
Short name T567
Test name
Test status
Simulation time 180096340 ps
CPU time 2.18 seconds
Started Aug 01 04:54:39 PM PDT 24
Finished Aug 01 04:54:41 PM PDT 24
Peak memory 197512 kb
Host smart-feb3c176-a292-4d96-8265-3f9cc7a8a3fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706511586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.706511586
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.689677337
Short name T476
Test name
Test status
Simulation time 233313115 ps
CPU time 0.8 seconds
Started Aug 01 04:54:39 PM PDT 24
Finished Aug 01 04:54:40 PM PDT 24
Peak memory 183048 kb
Host smart-f6524cd7-28c5-4c19-865e-61baef011be4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689677337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_in
tg_err.689677337
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.596984804
Short name T515
Test name
Test status
Simulation time 32165669 ps
CPU time 0.86 seconds
Started Aug 01 04:54:44 PM PDT 24
Finished Aug 01 04:54:45 PM PDT 24
Peak memory 196808 kb
Host smart-4f4b9675-5027-491e-8c59-75fd6cdf6a04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596984804 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.596984804
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.1864670452
Short name T65
Test name
Test status
Simulation time 30757548 ps
CPU time 0.57 seconds
Started Aug 01 04:54:40 PM PDT 24
Finished Aug 01 04:54:41 PM PDT 24
Peak memory 181824 kb
Host smart-7dc5b8a2-5379-4e34-af82-94d3a183a1ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864670452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.1864670452
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.2210852455
Short name T548
Test name
Test status
Simulation time 25022185 ps
CPU time 0.52 seconds
Started Aug 01 04:54:40 PM PDT 24
Finished Aug 01 04:54:41 PM PDT 24
Peak memory 181328 kb
Host smart-64aa671a-5477-49fa-a6b8-cbf278199137
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210852455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.2210852455
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3584865426
Short name T50
Test name
Test status
Simulation time 62127663 ps
CPU time 0.62 seconds
Started Aug 01 04:54:42 PM PDT 24
Finished Aug 01 04:54:42 PM PDT 24
Peak memory 192020 kb
Host smart-e3e09f89-416c-4419-86fa-c2a34f671f04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584865426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.3584865426
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.1948193299
Short name T524
Test name
Test status
Simulation time 111631082 ps
CPU time 1.99 seconds
Started Aug 01 04:54:46 PM PDT 24
Finished Aug 01 04:54:48 PM PDT 24
Peak memory 197496 kb
Host smart-e5b74932-abec-4d77-8f27-d965a733e89d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948193299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.1948193299
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.617779071
Short name T558
Test name
Test status
Simulation time 97740935 ps
CPU time 0.87 seconds
Started Aug 01 04:54:42 PM PDT 24
Finished Aug 01 04:54:43 PM PDT 24
Peak memory 193900 kb
Host smart-b3cd34f2-e3a5-4350-bb67-1fc534a924ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617779071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_in
tg_err.617779071
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.1680809370
Short name T505
Test name
Test status
Simulation time 112076308 ps
CPU time 1.09 seconds
Started Aug 01 04:54:43 PM PDT 24
Finished Aug 01 04:54:45 PM PDT 24
Peak memory 197408 kb
Host smart-f00bd8fe-b7ed-45d9-a793-f243de61f8a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680809370 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.1680809370
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.103050255
Short name T72
Test name
Test status
Simulation time 27291120 ps
CPU time 0.57 seconds
Started Aug 01 04:54:43 PM PDT 24
Finished Aug 01 04:54:43 PM PDT 24
Peak memory 182700 kb
Host smart-22fafef0-0097-4167-b9e3-eb4e2edbf001
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103050255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.103050255
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.550608820
Short name T557
Test name
Test status
Simulation time 16389191 ps
CPU time 0.56 seconds
Started Aug 01 04:54:39 PM PDT 24
Finished Aug 01 04:54:40 PM PDT 24
Peak memory 182552 kb
Host smart-8fa7e589-198e-459f-a162-83d4a71ba2b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550608820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.550608820
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2002797620
Short name T76
Test name
Test status
Simulation time 40373770 ps
CPU time 0.6 seconds
Started Aug 01 04:54:40 PM PDT 24
Finished Aug 01 04:54:41 PM PDT 24
Peak memory 192024 kb
Host smart-39e06431-379b-42e8-a7d9-d3272b31dd82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002797620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.2002797620
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3984118974
Short name T523
Test name
Test status
Simulation time 360185429 ps
CPU time 2.02 seconds
Started Aug 01 04:54:43 PM PDT 24
Finished Aug 01 04:54:45 PM PDT 24
Peak memory 197360 kb
Host smart-6ffa3f7d-a5e7-4670-b9a2-4d19d2a1e637
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984118974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.3984118974
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1425572850
Short name T543
Test name
Test status
Simulation time 52578530 ps
CPU time 0.84 seconds
Started Aug 01 04:54:41 PM PDT 24
Finished Aug 01 04:54:42 PM PDT 24
Peak memory 193720 kb
Host smart-8c00dbe6-30a9-4b64-9bfb-249f428b5217
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425572850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.1425572850
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.2785852712
Short name T501
Test name
Test status
Simulation time 33402588 ps
CPU time 0.82 seconds
Started Aug 01 04:54:09 PM PDT 24
Finished Aug 01 04:54:10 PM PDT 24
Peak memory 192684 kb
Host smart-a67e5e42-e076-4bc3-8190-62ff20e16f37
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785852712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.2785852712
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.2789826022
Short name T468
Test name
Test status
Simulation time 285233707 ps
CPU time 2.77 seconds
Started Aug 01 04:54:07 PM PDT 24
Finished Aug 01 04:54:10 PM PDT 24
Peak memory 191196 kb
Host smart-75823fd8-f34e-4f17-84f0-e5b083e95823
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789826022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.2789826022
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.2851714090
Short name T490
Test name
Test status
Simulation time 50821194 ps
CPU time 0.59 seconds
Started Aug 01 04:54:07 PM PDT 24
Finished Aug 01 04:54:08 PM PDT 24
Peak memory 182844 kb
Host smart-e861a609-0ef0-4466-bcae-593f43385706
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851714090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.2851714090
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.4179610515
Short name T31
Test name
Test status
Simulation time 52052611 ps
CPU time 0.65 seconds
Started Aug 01 04:54:07 PM PDT 24
Finished Aug 01 04:54:07 PM PDT 24
Peak memory 193160 kb
Host smart-ca76a8dc-1298-4179-afa3-ceab3039b00b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179610515 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.4179610515
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.456708740
Short name T526
Test name
Test status
Simulation time 47989324 ps
CPU time 0.61 seconds
Started Aug 01 04:54:06 PM PDT 24
Finished Aug 01 04:54:06 PM PDT 24
Peak memory 182704 kb
Host smart-c9177c68-441a-401c-be0f-67081b295ea7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456708740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.456708740
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.1862320928
Short name T502
Test name
Test status
Simulation time 53644443 ps
CPU time 0.53 seconds
Started Aug 01 04:54:10 PM PDT 24
Finished Aug 01 04:54:11 PM PDT 24
Peak memory 182592 kb
Host smart-b56c184d-f94b-4d5f-ad65-7587915972b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862320928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.1862320928
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.1551893046
Short name T546
Test name
Test status
Simulation time 27038825 ps
CPU time 0.7 seconds
Started Aug 01 04:54:07 PM PDT 24
Finished Aug 01 04:54:08 PM PDT 24
Peak memory 192312 kb
Host smart-df1a40b6-68b0-48a6-8faf-ca8a95375691
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551893046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.1551893046
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.3304763776
Short name T533
Test name
Test status
Simulation time 400562426 ps
CPU time 2.04 seconds
Started Aug 01 04:54:07 PM PDT 24
Finished Aug 01 04:54:10 PM PDT 24
Peak memory 197588 kb
Host smart-4f121ddb-5b87-4572-a5f7-ac8f33011f19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304763776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.3304763776
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.1085735868
Short name T518
Test name
Test status
Simulation time 245766406 ps
CPU time 0.81 seconds
Started Aug 01 04:54:09 PM PDT 24
Finished Aug 01 04:54:10 PM PDT 24
Peak memory 193596 kb
Host smart-cd7f9303-92d8-4d1f-9bcf-dfd8223b719a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085735868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.1085735868
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.3894205887
Short name T460
Test name
Test status
Simulation time 16756134 ps
CPU time 0.55 seconds
Started Aug 01 04:54:42 PM PDT 24
Finished Aug 01 04:54:43 PM PDT 24
Peak memory 182072 kb
Host smart-f80a901a-6a83-467a-a00f-caf002c7572c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894205887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.3894205887
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.3722441359
Short name T480
Test name
Test status
Simulation time 120511141 ps
CPU time 0.53 seconds
Started Aug 01 04:54:44 PM PDT 24
Finished Aug 01 04:54:44 PM PDT 24
Peak memory 182080 kb
Host smart-fe7f81ce-d85b-420e-a536-888da793e69b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722441359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.3722441359
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.277388621
Short name T537
Test name
Test status
Simulation time 24694039 ps
CPU time 0.54 seconds
Started Aug 01 04:54:41 PM PDT 24
Finished Aug 01 04:54:42 PM PDT 24
Peak memory 182356 kb
Host smart-8017e6d3-4a63-43a2-a2be-015fe87dcc51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277388621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.277388621
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.1048959444
Short name T547
Test name
Test status
Simulation time 18462979 ps
CPU time 0.57 seconds
Started Aug 01 04:54:39 PM PDT 24
Finished Aug 01 04:54:40 PM PDT 24
Peak memory 182964 kb
Host smart-80b0da4c-a462-410f-8626-5ae84003b754
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048959444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.1048959444
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.819216792
Short name T569
Test name
Test status
Simulation time 15150405 ps
CPU time 0.57 seconds
Started Aug 01 04:54:43 PM PDT 24
Finished Aug 01 04:54:44 PM PDT 24
Peak memory 182540 kb
Host smart-1e25b181-139e-41b2-8bd6-68cd2af2300b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819216792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.819216792
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.2461573742
Short name T489
Test name
Test status
Simulation time 43654519 ps
CPU time 0.55 seconds
Started Aug 01 04:54:41 PM PDT 24
Finished Aug 01 04:54:42 PM PDT 24
Peak memory 182724 kb
Host smart-779002e2-1cc3-41b6-8232-49ae786d1c11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461573742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.2461573742
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.670123261
Short name T572
Test name
Test status
Simulation time 19179363 ps
CPU time 0.63 seconds
Started Aug 01 04:54:43 PM PDT 24
Finished Aug 01 04:54:44 PM PDT 24
Peak memory 182504 kb
Host smart-a7e90827-9a71-4281-a07d-ff35c5fc84b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670123261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.670123261
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.3683325455
Short name T475
Test name
Test status
Simulation time 11030471 ps
CPU time 0.57 seconds
Started Aug 01 04:54:40 PM PDT 24
Finished Aug 01 04:54:40 PM PDT 24
Peak memory 182684 kb
Host smart-cd55d732-57f5-4aea-abee-c41f693e914d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683325455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.3683325455
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.4009207052
Short name T555
Test name
Test status
Simulation time 41566141 ps
CPU time 0.54 seconds
Started Aug 01 04:54:43 PM PDT 24
Finished Aug 01 04:54:44 PM PDT 24
Peak memory 182088 kb
Host smart-260658b9-5a37-45fa-80cf-4b5f79a891f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009207052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.4009207052
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.1035268958
Short name T540
Test name
Test status
Simulation time 19358165 ps
CPU time 0.53 seconds
Started Aug 01 04:54:39 PM PDT 24
Finished Aug 01 04:54:40 PM PDT 24
Peak memory 182540 kb
Host smart-456a981f-7a24-40aa-828f-8b00b7ec470c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035268958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.1035268958
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3636700874
Short name T67
Test name
Test status
Simulation time 31611422 ps
CPU time 0.62 seconds
Started Aug 01 04:54:19 PM PDT 24
Finished Aug 01 04:54:20 PM PDT 24
Peak memory 182832 kb
Host smart-d3f9e37d-2e91-410c-8ece-ea85838a3c99
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636700874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.3636700874
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.830708418
Short name T530
Test name
Test status
Simulation time 67304377 ps
CPU time 2.34 seconds
Started Aug 01 04:54:19 PM PDT 24
Finished Aug 01 04:54:21 PM PDT 24
Peak memory 192548 kb
Host smart-499ee7bb-8ff0-4a2b-998d-e2d44b71aa85
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830708418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_b
ash.830708418
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3703113728
Short name T73
Test name
Test status
Simulation time 32021973 ps
CPU time 0.55 seconds
Started Aug 01 04:54:21 PM PDT 24
Finished Aug 01 04:54:21 PM PDT 24
Peak memory 182344 kb
Host smart-405b8c0f-d8f6-448a-bc67-2d9f28164c95
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703113728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.3703113728
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.284343444
Short name T536
Test name
Test status
Simulation time 187701500 ps
CPU time 0.65 seconds
Started Aug 01 04:54:21 PM PDT 24
Finished Aug 01 04:54:22 PM PDT 24
Peak memory 193904 kb
Host smart-cea22e73-85c0-45e8-b3dd-b10ec81b7480
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284343444 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.284343444
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.999391880
Short name T487
Test name
Test status
Simulation time 39716407 ps
CPU time 0.57 seconds
Started Aug 01 04:54:18 PM PDT 24
Finished Aug 01 04:54:19 PM PDT 24
Peak memory 182712 kb
Host smart-5cfd380e-5563-416c-bcdd-ae924965a878
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999391880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.999391880
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.445217548
Short name T473
Test name
Test status
Simulation time 79181179 ps
CPU time 0.59 seconds
Started Aug 01 04:54:08 PM PDT 24
Finished Aug 01 04:54:09 PM PDT 24
Peak memory 182640 kb
Host smart-bc1003a3-ed62-4be3-a164-156a254ef908
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445217548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.445217548
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.3898082817
Short name T519
Test name
Test status
Simulation time 36156047 ps
CPU time 0.6 seconds
Started Aug 01 04:54:18 PM PDT 24
Finished Aug 01 04:54:19 PM PDT 24
Peak memory 192284 kb
Host smart-5077afd3-ecfc-49d4-ba00-3119b792b675
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898082817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.3898082817
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3557133385
Short name T550
Test name
Test status
Simulation time 37290066 ps
CPU time 1.1 seconds
Started Aug 01 04:54:07 PM PDT 24
Finished Aug 01 04:54:09 PM PDT 24
Peak memory 197312 kb
Host smart-bb07ddfe-2899-47ff-84a3-08559ee2407a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557133385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.3557133385
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.3860598835
Short name T566
Test name
Test status
Simulation time 605121309 ps
CPU time 1.43 seconds
Started Aug 01 04:54:06 PM PDT 24
Finished Aug 01 04:54:08 PM PDT 24
Peak memory 195464 kb
Host smart-4ed3f8bb-477f-463c-829c-7dca29d094ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860598835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.3860598835
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.3617627885
Short name T453
Test name
Test status
Simulation time 20045912 ps
CPU time 0.53 seconds
Started Aug 01 04:54:40 PM PDT 24
Finished Aug 01 04:54:41 PM PDT 24
Peak memory 181128 kb
Host smart-61a36b20-16a0-4ddf-8190-caffca86f04b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617627885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.3617627885
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.3947850599
Short name T552
Test name
Test status
Simulation time 13482022 ps
CPU time 0.53 seconds
Started Aug 01 04:54:52 PM PDT 24
Finished Aug 01 04:54:53 PM PDT 24
Peak memory 182092 kb
Host smart-30caf969-93fc-495b-a7f7-9d6882d7fe72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947850599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.3947850599
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.1751174130
Short name T542
Test name
Test status
Simulation time 34305529 ps
CPU time 0.56 seconds
Started Aug 01 04:54:53 PM PDT 24
Finished Aug 01 04:54:54 PM PDT 24
Peak memory 182576 kb
Host smart-a54dbcbd-ec34-4f8b-87eb-c325f91712ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751174130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.1751174130
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1456097592
Short name T459
Test name
Test status
Simulation time 19005746 ps
CPU time 0.57 seconds
Started Aug 01 04:54:52 PM PDT 24
Finished Aug 01 04:54:53 PM PDT 24
Peak memory 182604 kb
Host smart-56490a49-719e-4824-ba7b-1d10c5c78d1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456097592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.1456097592
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.3143270927
Short name T516
Test name
Test status
Simulation time 47899365 ps
CPU time 0.56 seconds
Started Aug 01 04:54:53 PM PDT 24
Finished Aug 01 04:54:54 PM PDT 24
Peak memory 182620 kb
Host smart-8d9bfc46-7e98-4e9e-8a11-57560095ad67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143270927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.3143270927
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2727018821
Short name T512
Test name
Test status
Simulation time 14211249 ps
CPU time 0.58 seconds
Started Aug 01 04:54:51 PM PDT 24
Finished Aug 01 04:54:52 PM PDT 24
Peak memory 182120 kb
Host smart-8c5593f7-b971-45a3-ac33-f88f7f282084
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727018821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.2727018821
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.2915089001
Short name T575
Test name
Test status
Simulation time 35136302 ps
CPU time 0.55 seconds
Started Aug 01 04:54:53 PM PDT 24
Finished Aug 01 04:54:54 PM PDT 24
Peak memory 182292 kb
Host smart-a34b3b69-a240-4555-95c9-43dfc8f20215
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915089001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.2915089001
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.1607936560
Short name T571
Test name
Test status
Simulation time 35633100 ps
CPU time 0.57 seconds
Started Aug 01 04:54:52 PM PDT 24
Finished Aug 01 04:54:53 PM PDT 24
Peak memory 182672 kb
Host smart-76151321-e339-4691-be5d-49ab7a7c5479
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607936560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.1607936560
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.1003282
Short name T462
Test name
Test status
Simulation time 179262754 ps
CPU time 0.55 seconds
Started Aug 01 04:54:59 PM PDT 24
Finished Aug 01 04:55:00 PM PDT 24
Peak memory 182552 kb
Host smart-acf7ab69-d393-47a3-a07e-480500cb76ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.1003282
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.2987226439
Short name T461
Test name
Test status
Simulation time 13898630 ps
CPU time 0.55 seconds
Started Aug 01 04:54:53 PM PDT 24
Finished Aug 01 04:54:54 PM PDT 24
Peak memory 182624 kb
Host smart-475e29b1-e217-40ff-a9b7-6d2a9da7d24c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987226439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.2987226439
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.2921127345
Short name T69
Test name
Test status
Simulation time 20885901 ps
CPU time 0.61 seconds
Started Aug 01 04:54:18 PM PDT 24
Finished Aug 01 04:54:18 PM PDT 24
Peak memory 182700 kb
Host smart-905e3d6b-0288-4045-b3ee-e2f86ed3496b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921127345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.2921127345
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.4241144147
Short name T64
Test name
Test status
Simulation time 278872322 ps
CPU time 2.53 seconds
Started Aug 01 04:54:21 PM PDT 24
Finished Aug 01 04:54:24 PM PDT 24
Peak memory 191200 kb
Host smart-4a2e2470-259c-4f04-9cb1-8f1a8604e8ab
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241144147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.4241144147
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.3644334942
Short name T474
Test name
Test status
Simulation time 21703320 ps
CPU time 0.57 seconds
Started Aug 01 04:54:19 PM PDT 24
Finished Aug 01 04:54:20 PM PDT 24
Peak memory 182780 kb
Host smart-3341ecfc-a8bb-4473-8a3a-ed7fad272f66
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644334942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.3644334942
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3687271393
Short name T51
Test name
Test status
Simulation time 30900115 ps
CPU time 0.8 seconds
Started Aug 01 04:54:19 PM PDT 24
Finished Aug 01 04:54:20 PM PDT 24
Peak memory 195976 kb
Host smart-f07f6310-24fa-46d6-a26f-31076438ff4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687271393 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.3687271393
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.3344706426
Short name T488
Test name
Test status
Simulation time 32907609 ps
CPU time 0.6 seconds
Started Aug 01 04:54:17 PM PDT 24
Finished Aug 01 04:54:17 PM PDT 24
Peak memory 182816 kb
Host smart-40fc9508-63ee-4aca-9756-b1f4d41a9fd3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344706426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.3344706426
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.3871508984
Short name T522
Test name
Test status
Simulation time 32896253 ps
CPU time 0.56 seconds
Started Aug 01 04:54:21 PM PDT 24
Finished Aug 01 04:54:21 PM PDT 24
Peak memory 182660 kb
Host smart-812f2a5f-4b4f-4fb3-9ba6-7fc29d541b3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871508984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.3871508984
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.2990979160
Short name T75
Test name
Test status
Simulation time 18996796 ps
CPU time 0.61 seconds
Started Aug 01 04:54:19 PM PDT 24
Finished Aug 01 04:54:20 PM PDT 24
Peak memory 191984 kb
Host smart-cc72ccad-c480-4fc6-953b-e5ce8facaac0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990979160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.2990979160
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1619631060
Short name T559
Test name
Test status
Simulation time 42329982 ps
CPU time 0.92 seconds
Started Aug 01 04:54:18 PM PDT 24
Finished Aug 01 04:54:19 PM PDT 24
Peak memory 196836 kb
Host smart-bf45dbc3-fa6d-4e79-aa2a-c7f1c0d57a53
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619631060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.1619631060
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2254442748
Short name T85
Test name
Test status
Simulation time 88585801 ps
CPU time 1.04 seconds
Started Aug 01 04:54:19 PM PDT 24
Finished Aug 01 04:54:21 PM PDT 24
Peak memory 195104 kb
Host smart-94e928f7-2130-4efb-a3ca-3564e21bf0b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254442748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.2254442748
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.808060813
Short name T469
Test name
Test status
Simulation time 13848988 ps
CPU time 0.54 seconds
Started Aug 01 04:54:55 PM PDT 24
Finished Aug 01 04:54:56 PM PDT 24
Peak memory 182056 kb
Host smart-b2eff82d-8bd7-4abc-b01f-a25cafca2452
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808060813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.808060813
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.882220191
Short name T549
Test name
Test status
Simulation time 86600609 ps
CPU time 0.53 seconds
Started Aug 01 04:54:53 PM PDT 24
Finished Aug 01 04:54:54 PM PDT 24
Peak memory 182080 kb
Host smart-63db96fa-de1c-4c00-b962-dc8e4a71c46a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882220191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.882220191
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.4253114304
Short name T527
Test name
Test status
Simulation time 39572911 ps
CPU time 0.53 seconds
Started Aug 01 04:54:55 PM PDT 24
Finished Aug 01 04:54:55 PM PDT 24
Peak memory 182228 kb
Host smart-4bc9722e-f234-4678-b11f-6ecec32509f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253114304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.4253114304
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.1305086557
Short name T497
Test name
Test status
Simulation time 59175286 ps
CPU time 0.56 seconds
Started Aug 01 04:54:53 PM PDT 24
Finished Aug 01 04:54:53 PM PDT 24
Peak memory 182660 kb
Host smart-1b262fdc-20a8-46ab-accb-fc8888e58cef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305086557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.1305086557
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.2634316471
Short name T458
Test name
Test status
Simulation time 21433196 ps
CPU time 0.54 seconds
Started Aug 01 04:54:57 PM PDT 24
Finished Aug 01 04:54:57 PM PDT 24
Peak memory 182584 kb
Host smart-a1870e6f-6842-4a92-b112-ab980a3b406d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634316471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.2634316471
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1879342719
Short name T544
Test name
Test status
Simulation time 15602540 ps
CPU time 0.55 seconds
Started Aug 01 04:54:53 PM PDT 24
Finished Aug 01 04:54:54 PM PDT 24
Peak memory 182552 kb
Host smart-f465f063-192d-4300-bffd-db452b6eab58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879342719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.1879342719
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.2007920976
Short name T532
Test name
Test status
Simulation time 13269592 ps
CPU time 0.54 seconds
Started Aug 01 04:54:53 PM PDT 24
Finished Aug 01 04:54:54 PM PDT 24
Peak memory 182076 kb
Host smart-28581bff-13d8-4e0b-83b5-f32a4e5fa6dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007920976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.2007920976
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.3987269160
Short name T482
Test name
Test status
Simulation time 13372869 ps
CPU time 0.55 seconds
Started Aug 01 04:54:54 PM PDT 24
Finished Aug 01 04:54:54 PM PDT 24
Peak memory 182040 kb
Host smart-7baa946e-c539-4169-a44f-876573946b62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987269160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.3987269160
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.209089299
Short name T520
Test name
Test status
Simulation time 16002256 ps
CPU time 0.56 seconds
Started Aug 01 04:54:54 PM PDT 24
Finished Aug 01 04:54:55 PM PDT 24
Peak memory 182572 kb
Host smart-83febfba-b2a5-4351-90f0-629f03073857
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209089299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.209089299
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.2059745273
Short name T498
Test name
Test status
Simulation time 17073131 ps
CPU time 0.58 seconds
Started Aug 01 04:54:55 PM PDT 24
Finished Aug 01 04:54:55 PM PDT 24
Peak memory 182628 kb
Host smart-1420a564-21b5-4dbc-b9ff-257ba8fb8dcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059745273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.2059745273
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.253684502
Short name T456
Test name
Test status
Simulation time 34957714 ps
CPU time 0.89 seconds
Started Aug 01 04:54:18 PM PDT 24
Finished Aug 01 04:54:19 PM PDT 24
Peak memory 196744 kb
Host smart-89d3dd95-99d8-47a2-ab14-6672d422d38a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253684502 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.253684502
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.2600547277
Short name T63
Test name
Test status
Simulation time 12909073 ps
CPU time 0.58 seconds
Started Aug 01 04:54:21 PM PDT 24
Finished Aug 01 04:54:21 PM PDT 24
Peak memory 182768 kb
Host smart-4840c731-3336-476a-a5e5-ba19f3adfd80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600547277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.2600547277
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.621707398
Short name T551
Test name
Test status
Simulation time 16944129 ps
CPU time 0.55 seconds
Started Aug 01 04:54:20 PM PDT 24
Finished Aug 01 04:54:21 PM PDT 24
Peak memory 182704 kb
Host smart-3c131b54-2541-4f1d-a188-6c2df6a864d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621707398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.621707398
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1348023000
Short name T513
Test name
Test status
Simulation time 14401825 ps
CPU time 0.62 seconds
Started Aug 01 04:54:19 PM PDT 24
Finished Aug 01 04:54:20 PM PDT 24
Peak memory 192300 kb
Host smart-eab02c96-2f89-4548-9b7b-86ea4b420521
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348023000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.1348023000
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.2124525303
Short name T465
Test name
Test status
Simulation time 134118573 ps
CPU time 2.27 seconds
Started Aug 01 04:54:22 PM PDT 24
Finished Aug 01 04:54:24 PM PDT 24
Peak memory 197516 kb
Host smart-43280f29-6215-4cbf-ab21-910bc5929c36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124525303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.2124525303
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.2845255827
Short name T534
Test name
Test status
Simulation time 76179424 ps
CPU time 1.07 seconds
Started Aug 01 04:54:22 PM PDT 24
Finished Aug 01 04:54:24 PM PDT 24
Peak memory 195080 kb
Host smart-d0d124ec-e6b0-4311-bae3-3e6e3f02a665
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845255827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.2845255827
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.2760650030
Short name T486
Test name
Test status
Simulation time 24878674 ps
CPU time 1.06 seconds
Started Aug 01 04:54:19 PM PDT 24
Finished Aug 01 04:54:20 PM PDT 24
Peak memory 197604 kb
Host smart-93b8200c-bd65-408f-abee-c794cc7ca424
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760650030 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.2760650030
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1572167285
Short name T71
Test name
Test status
Simulation time 24813939 ps
CPU time 0.59 seconds
Started Aug 01 04:54:18 PM PDT 24
Finished Aug 01 04:54:19 PM PDT 24
Peak memory 182784 kb
Host smart-400952d9-6051-41cc-b1ac-48a93ca50ab2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572167285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.1572167285
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.3263689146
Short name T574
Test name
Test status
Simulation time 15167439 ps
CPU time 0.52 seconds
Started Aug 01 04:54:18 PM PDT 24
Finished Aug 01 04:54:19 PM PDT 24
Peak memory 182100 kb
Host smart-bd12dcb1-50f8-4a0a-aee2-ff348eaf8429
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263689146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.3263689146
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.2847296622
Short name T77
Test name
Test status
Simulation time 29607727 ps
CPU time 0.71 seconds
Started Aug 01 04:54:18 PM PDT 24
Finished Aug 01 04:54:19 PM PDT 24
Peak memory 193348 kb
Host smart-927eccdd-435f-4404-91dc-1ee50713d0ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847296622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.2847296622
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.4038081882
Short name T525
Test name
Test status
Simulation time 479684143 ps
CPU time 1.92 seconds
Started Aug 01 04:54:20 PM PDT 24
Finished Aug 01 04:54:22 PM PDT 24
Peak memory 197496 kb
Host smart-97e9ba48-bcf3-4d6a-87a7-8a5040e8fe2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038081882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.4038081882
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.838378625
Short name T535
Test name
Test status
Simulation time 244418540 ps
CPU time 1.28 seconds
Started Aug 01 04:54:19 PM PDT 24
Finished Aug 01 04:54:20 PM PDT 24
Peak memory 183600 kb
Host smart-80ce71ee-ee71-4209-81bb-f6a71b42cdbd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838378625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_int
g_err.838378625
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2101429815
Short name T531
Test name
Test status
Simulation time 74280707 ps
CPU time 0.65 seconds
Started Aug 01 04:54:21 PM PDT 24
Finished Aug 01 04:54:22 PM PDT 24
Peak memory 194700 kb
Host smart-b54dc18f-584d-45c4-8ad5-9d7b20842970
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101429815 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.2101429815
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.3526959093
Short name T70
Test name
Test status
Simulation time 12153629 ps
CPU time 0.58 seconds
Started Aug 01 04:54:20 PM PDT 24
Finished Aug 01 04:54:21 PM PDT 24
Peak memory 182744 kb
Host smart-44e7d78c-4eb8-4ff8-b9ee-28f385c29f73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526959093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.3526959093
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.3602187472
Short name T463
Test name
Test status
Simulation time 44304524 ps
CPU time 0.53 seconds
Started Aug 01 04:54:19 PM PDT 24
Finished Aug 01 04:54:20 PM PDT 24
Peak memory 182620 kb
Host smart-19ab3032-edd8-4ea4-8b89-400b3ec66477
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602187472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.3602187472
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3917896257
Short name T510
Test name
Test status
Simulation time 34225444 ps
CPU time 0.75 seconds
Started Aug 01 04:54:19 PM PDT 24
Finished Aug 01 04:54:20 PM PDT 24
Peak memory 193544 kb
Host smart-83d96e3e-cfa0-49d7-a2f8-531606d7252e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917896257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.3917896257
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.85912070
Short name T503
Test name
Test status
Simulation time 191271592 ps
CPU time 2.43 seconds
Started Aug 01 04:54:21 PM PDT 24
Finished Aug 01 04:54:24 PM PDT 24
Peak memory 197496 kb
Host smart-9e898a20-2631-4fba-806c-bdae8a84d713
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85912070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.85912070
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3571682625
Short name T32
Test name
Test status
Simulation time 65738392 ps
CPU time 0.9 seconds
Started Aug 01 04:54:20 PM PDT 24
Finished Aug 01 04:54:21 PM PDT 24
Peak memory 197404 kb
Host smart-5ad4974b-2d53-4c58-bc9e-d7414e58a5fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571682625 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.3571682625
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.83253636
Short name T82
Test name
Test status
Simulation time 30124945 ps
CPU time 0.53 seconds
Started Aug 01 04:54:20 PM PDT 24
Finished Aug 01 04:54:21 PM PDT 24
Peak memory 182420 kb
Host smart-d2b9e78b-9a90-4c23-9b7f-bc2ad29df21e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83253636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.83253636
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.2538447574
Short name T464
Test name
Test status
Simulation time 14438007 ps
CPU time 0.58 seconds
Started Aug 01 04:54:21 PM PDT 24
Finished Aug 01 04:54:21 PM PDT 24
Peak memory 182588 kb
Host smart-635e06f8-e276-463a-a8ea-fd5b1fa62c20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538447574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.2538447574
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.4030822928
Short name T508
Test name
Test status
Simulation time 97056966 ps
CPU time 0.83 seconds
Started Aug 01 04:54:20 PM PDT 24
Finished Aug 01 04:54:21 PM PDT 24
Peak memory 194100 kb
Host smart-ddf907f4-f43f-474b-a99d-2324c1f38935
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030822928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.4030822928
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.4221270490
Short name T499
Test name
Test status
Simulation time 303803010 ps
CPU time 2.4 seconds
Started Aug 01 04:54:21 PM PDT 24
Finished Aug 01 04:54:23 PM PDT 24
Peak memory 197404 kb
Host smart-9658b3f1-7007-4a14-b371-c350e36b605f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221270490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.4221270490
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.1297872388
Short name T577
Test name
Test status
Simulation time 161067232 ps
CPU time 0.84 seconds
Started Aug 01 04:54:23 PM PDT 24
Finished Aug 01 04:54:24 PM PDT 24
Peak memory 193556 kb
Host smart-1aef07de-0ae1-476c-ace0-7d3812b4ee76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297872388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.1297872388
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.186786775
Short name T491
Test name
Test status
Simulation time 68666957 ps
CPU time 0.89 seconds
Started Aug 01 04:54:28 PM PDT 24
Finished Aug 01 04:54:29 PM PDT 24
Peak memory 197420 kb
Host smart-537f4a62-ef2a-4c88-adde-35f52ad74fc2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186786775 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.186786775
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.1762911784
Short name T60
Test name
Test status
Simulation time 46577062 ps
CPU time 0.55 seconds
Started Aug 01 04:54:19 PM PDT 24
Finished Aug 01 04:54:19 PM PDT 24
Peak memory 182768 kb
Host smart-a1c1318f-ae1b-4134-b33a-4b2a564e2c49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762911784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.1762911784
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.4175647408
Short name T452
Test name
Test status
Simulation time 65243503 ps
CPU time 0.53 seconds
Started Aug 01 04:54:20 PM PDT 24
Finished Aug 01 04:54:20 PM PDT 24
Peak memory 182776 kb
Host smart-e9b62072-bc87-4c5e-956e-6e6fa2ac935c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175647408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.4175647408
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1354301854
Short name T507
Test name
Test status
Simulation time 58634711 ps
CPU time 0.8 seconds
Started Aug 01 04:54:22 PM PDT 24
Finished Aug 01 04:54:23 PM PDT 24
Peak memory 193504 kb
Host smart-a3aace8c-58db-4207-b6f8-995cd0c6104b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354301854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.1354301854
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.3464262157
Short name T565
Test name
Test status
Simulation time 105549463 ps
CPU time 1.35 seconds
Started Aug 01 04:54:17 PM PDT 24
Finished Aug 01 04:54:19 PM PDT 24
Peak memory 197024 kb
Host smart-59ba4b33-8dec-46ec-94da-343d0639c51e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464262157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.3464262157
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3414235113
Short name T504
Test name
Test status
Simulation time 563287911 ps
CPU time 0.78 seconds
Started Aug 01 04:54:18 PM PDT 24
Finished Aug 01 04:54:19 PM PDT 24
Peak memory 193796 kb
Host smart-186d9098-9129-4702-b655-dc2063ce58a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414235113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.3414235113
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.3141065500
Short name T372
Test name
Test status
Simulation time 222305534136 ps
CPU time 146.48 seconds
Started Aug 01 04:22:39 PM PDT 24
Finished Aug 01 04:25:06 PM PDT 24
Peak memory 181944 kb
Host smart-2484e6f0-1745-45fb-a9bc-a19e127cdff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141065500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.3141065500
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.3164741772
Short name T264
Test name
Test status
Simulation time 27404908328 ps
CPU time 39.45 seconds
Started Aug 01 04:22:50 PM PDT 24
Finished Aug 01 04:23:29 PM PDT 24
Peak memory 191096 kb
Host smart-d79b55d8-b33f-437d-b0ec-f0c96768e10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164741772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.3164741772
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.2747490773
Short name T55
Test name
Test status
Simulation time 1666498048088 ps
CPU time 789.72 seconds
Started Aug 01 04:22:39 PM PDT 24
Finished Aug 01 04:35:49 PM PDT 24
Peak memory 195748 kb
Host smart-b7ce0a6f-df71-46f8-b97f-57469b4b6ab9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747490773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
2747490773
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.2789471282
Short name T27
Test name
Test status
Simulation time 57138199195 ps
CPU time 92.61 seconds
Started Aug 01 04:17:49 PM PDT 24
Finished Aug 01 04:19:21 PM PDT 24
Peak memory 183284 kb
Host smart-9fb05644-c518-471d-8992-0c84d4f2ffb9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789471282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.2789471282
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_random.3128598241
Short name T390
Test name
Test status
Simulation time 278347246877 ps
CPU time 907.32 seconds
Started Aug 01 04:17:48 PM PDT 24
Finished Aug 01 04:32:55 PM PDT 24
Peak memory 191476 kb
Host smart-2b8b2fc6-0380-44df-af33-4ae03c94b4be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128598241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.3128598241
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.1379703787
Short name T371
Test name
Test status
Simulation time 11916977462 ps
CPU time 16.63 seconds
Started Aug 01 04:23:19 PM PDT 24
Finished Aug 01 04:23:36 PM PDT 24
Peak memory 182892 kb
Host smart-9e298d0e-80be-4239-bfef-2523bab3fade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379703787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.1379703787
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.1953434706
Short name T17
Test name
Test status
Simulation time 173386780 ps
CPU time 0.91 seconds
Started Aug 01 04:23:10 PM PDT 24
Finished Aug 01 04:23:12 PM PDT 24
Peak memory 214592 kb
Host smart-0caff031-037a-40c6-9d78-675e7e43f44e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953434706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.1953434706
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.3469220743
Short name T317
Test name
Test status
Simulation time 1691716937488 ps
CPU time 785.41 seconds
Started Aug 01 04:22:43 PM PDT 24
Finished Aug 01 04:35:48 PM PDT 24
Peak memory 182892 kb
Host smart-014dda72-d0ce-4db6-b923-a191862e918c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469220743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.3469220743
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.3324268875
Short name T411
Test name
Test status
Simulation time 247710696940 ps
CPU time 86.16 seconds
Started Aug 01 04:22:25 PM PDT 24
Finished Aug 01 04:23:52 PM PDT 24
Peak memory 182180 kb
Host smart-a2d0163a-ae44-440f-a192-29a2d2d92efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324268875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.3324268875
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.544813676
Short name T381
Test name
Test status
Simulation time 23781852 ps
CPU time 0.6 seconds
Started Aug 01 04:18:37 PM PDT 24
Finished Aug 01 04:18:37 PM PDT 24
Peak memory 183076 kb
Host smart-3f48dc3b-fdc9-4641-93a0-3691a3299dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544813676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.544813676
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/100.rv_timer_random.907596969
Short name T146
Test name
Test status
Simulation time 479460179742 ps
CPU time 286.79 seconds
Started Aug 01 04:23:04 PM PDT 24
Finished Aug 01 04:27:51 PM PDT 24
Peak memory 191608 kb
Host smart-84025e90-3036-4e1b-9d1d-a0b98ba85897
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907596969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.907596969
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.4133729445
Short name T325
Test name
Test status
Simulation time 250113240472 ps
CPU time 254.32 seconds
Started Aug 01 04:23:02 PM PDT 24
Finished Aug 01 04:27:17 PM PDT 24
Peak memory 191452 kb
Host smart-62c120f1-e67f-47aa-8f83-1f0a45104cfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133729445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.4133729445
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.2497334052
Short name T207
Test name
Test status
Simulation time 227765028268 ps
CPU time 3283.55 seconds
Started Aug 01 04:24:15 PM PDT 24
Finished Aug 01 05:18:59 PM PDT 24
Peak memory 190512 kb
Host smart-67697382-087f-4717-a932-64527335fe38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497334052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.2497334052
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.1451770682
Short name T23
Test name
Test status
Simulation time 90244854123 ps
CPU time 1686.21 seconds
Started Aug 01 04:23:13 PM PDT 24
Finished Aug 01 04:51:19 PM PDT 24
Peak memory 183180 kb
Host smart-1aa74300-808d-4366-9de2-0dc2cbf22685
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451770682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.1451770682
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.2220591562
Short name T127
Test name
Test status
Simulation time 1528342878566 ps
CPU time 671.84 seconds
Started Aug 01 04:23:12 PM PDT 24
Finished Aug 01 04:34:24 PM PDT 24
Peak memory 191416 kb
Host smart-50845c9d-4c6e-4a01-84f9-5b009f177b5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220591562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.2220591562
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.2547661026
Short name T324
Test name
Test status
Simulation time 126150594617 ps
CPU time 79.1 seconds
Started Aug 01 04:23:12 PM PDT 24
Finished Aug 01 04:24:32 PM PDT 24
Peak memory 183384 kb
Host smart-0a99488b-6beb-4f25-924c-b543070b58d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547661026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.2547661026
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.2852792885
Short name T187
Test name
Test status
Simulation time 90901920103 ps
CPU time 137.96 seconds
Started Aug 01 04:23:12 PM PDT 24
Finished Aug 01 04:25:30 PM PDT 24
Peak memory 191408 kb
Host smart-5eaec921-6161-4680-bd61-26d90c77799d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852792885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.2852792885
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.3843394780
Short name T404
Test name
Test status
Simulation time 39412232006 ps
CPU time 38.99 seconds
Started Aug 01 04:23:10 PM PDT 24
Finished Aug 01 04:23:49 PM PDT 24
Peak memory 183312 kb
Host smart-0edc7f6f-f73e-4a19-8d2b-37ecf5e71ac3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843394780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.3843394780
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.187023747
Short name T278
Test name
Test status
Simulation time 1382767763314 ps
CPU time 647.28 seconds
Started Aug 01 04:22:59 PM PDT 24
Finished Aug 01 04:33:46 PM PDT 24
Peak memory 183244 kb
Host smart-2ad1b92a-b748-46e2-85ca-5c4489f19ead
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187023747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.rv_timer_cfg_update_on_fly.187023747
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.4001863699
Short name T436
Test name
Test status
Simulation time 61661876860 ps
CPU time 83.3 seconds
Started Aug 01 04:23:04 PM PDT 24
Finished Aug 01 04:24:28 PM PDT 24
Peak memory 183228 kb
Host smart-5a0cb26f-0064-4a39-82ab-306722ea52ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001863699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.4001863699
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.3541272300
Short name T5
Test name
Test status
Simulation time 68916501486 ps
CPU time 103.26 seconds
Started Aug 01 04:22:58 PM PDT 24
Finished Aug 01 04:24:41 PM PDT 24
Peak memory 182976 kb
Host smart-ccd0b0f1-7463-4121-bd02-86bc9fbc0370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541272300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.3541272300
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.3393131557
Short name T406
Test name
Test status
Simulation time 629713039778 ps
CPU time 100.87 seconds
Started Aug 01 04:22:49 PM PDT 24
Finished Aug 01 04:24:30 PM PDT 24
Peak memory 182924 kb
Host smart-49a0d9a6-a34a-438b-ab1e-58cd329a24bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393131557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.3393131557
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/110.rv_timer_random.273877664
Short name T355
Test name
Test status
Simulation time 463535582630 ps
CPU time 73.09 seconds
Started Aug 01 04:24:29 PM PDT 24
Finished Aug 01 04:25:43 PM PDT 24
Peak memory 183268 kb
Host smart-ced9862b-8676-44e7-9e72-b895128df37a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273877664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.273877664
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.426845911
Short name T147
Test name
Test status
Simulation time 104538827908 ps
CPU time 403.54 seconds
Started Aug 01 04:23:12 PM PDT 24
Finished Aug 01 04:29:56 PM PDT 24
Peak memory 191436 kb
Host smart-fe98c406-6dd3-4782-a9e7-4686a08a0af8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426845911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.426845911
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.2825694775
Short name T346
Test name
Test status
Simulation time 184432647281 ps
CPU time 458.86 seconds
Started Aug 01 04:23:12 PM PDT 24
Finished Aug 01 04:30:51 PM PDT 24
Peak memory 191416 kb
Host smart-8b8c96b2-7f63-442b-a2e6-a60e1236f070
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825694775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.2825694775
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.3465891023
Short name T213
Test name
Test status
Simulation time 258215817091 ps
CPU time 412.08 seconds
Started Aug 01 04:24:29 PM PDT 24
Finished Aug 01 04:31:21 PM PDT 24
Peak memory 191476 kb
Host smart-ba4b7a67-f0ba-4ff1-8f1e-f8c197f33b19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465891023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.3465891023
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.2623056375
Short name T144
Test name
Test status
Simulation time 366721704152 ps
CPU time 152.81 seconds
Started Aug 01 04:23:10 PM PDT 24
Finished Aug 01 04:25:43 PM PDT 24
Peak memory 191388 kb
Host smart-f0e217ec-fca3-493b-a3c1-bc4250346ad3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623056375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.2623056375
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.1895155565
Short name T20
Test name
Test status
Simulation time 459729166555 ps
CPU time 619.52 seconds
Started Aug 01 04:23:02 PM PDT 24
Finished Aug 01 04:33:21 PM PDT 24
Peak memory 183244 kb
Host smart-cf8127c5-f72e-49d7-8ed7-dff1c0c3fee1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895155565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.1895155565
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.3603233495
Short name T426
Test name
Test status
Simulation time 6892095122 ps
CPU time 5.83 seconds
Started Aug 01 04:22:50 PM PDT 24
Finished Aug 01 04:22:56 PM PDT 24
Peak memory 182960 kb
Host smart-b1773d62-3c10-4a9d-922b-0f911c09c8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603233495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.3603233495
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.1008037214
Short name T282
Test name
Test status
Simulation time 254348234920 ps
CPU time 145.99 seconds
Started Aug 01 04:22:58 PM PDT 24
Finished Aug 01 04:25:24 PM PDT 24
Peak memory 191160 kb
Host smart-a352d0a6-88b2-40bf-ada1-92cfa3f7d5be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008037214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.1008037214
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.3948680090
Short name T363
Test name
Test status
Simulation time 3340005748 ps
CPU time 3.67 seconds
Started Aug 01 04:22:50 PM PDT 24
Finished Aug 01 04:22:54 PM PDT 24
Peak memory 182960 kb
Host smart-09d2b69b-5cf7-40cc-832b-b027c1b929be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948680090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.3948680090
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.3933981362
Short name T58
Test name
Test status
Simulation time 1795133086074 ps
CPU time 955.76 seconds
Started Aug 01 04:22:48 PM PDT 24
Finished Aug 01 04:38:44 PM PDT 24
Peak memory 190216 kb
Host smart-507c0a09-6953-4806-8808-2c6ed06da898
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933981362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.3933981362
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/120.rv_timer_random.3493458704
Short name T105
Test name
Test status
Simulation time 10094209514 ps
CPU time 17.63 seconds
Started Aug 01 04:23:28 PM PDT 24
Finished Aug 01 04:23:46 PM PDT 24
Peak memory 183236 kb
Host smart-da5c13ce-ede1-4361-9b69-1b59311e6d85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493458704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.3493458704
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.17645036
Short name T118
Test name
Test status
Simulation time 206136507857 ps
CPU time 163.45 seconds
Started Aug 01 04:23:25 PM PDT 24
Finished Aug 01 04:26:09 PM PDT 24
Peak memory 191480 kb
Host smart-8a3f37e0-1ced-441a-a37f-09742ce4dc21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17645036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.17645036
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.2088944741
Short name T240
Test name
Test status
Simulation time 72492067507 ps
CPU time 86.06 seconds
Started Aug 01 04:23:24 PM PDT 24
Finished Aug 01 04:24:50 PM PDT 24
Peak memory 191848 kb
Host smart-cfc574aa-7e52-4e9d-bf09-aa30af68e6fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088944741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.2088944741
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.679058130
Short name T305
Test name
Test status
Simulation time 209202583625 ps
CPU time 122.97 seconds
Started Aug 01 04:23:25 PM PDT 24
Finished Aug 01 04:25:28 PM PDT 24
Peak memory 183244 kb
Host smart-9bbcf9df-7606-45f5-b169-300bd17b6011
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679058130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.679058130
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.3218954251
Short name T345
Test name
Test status
Simulation time 573893490783 ps
CPU time 416.99 seconds
Started Aug 01 04:23:24 PM PDT 24
Finished Aug 01 04:30:22 PM PDT 24
Peak memory 183208 kb
Host smart-7e05b589-e5d0-4cec-83b7-5110e2080105
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218954251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.3218954251
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.1581554725
Short name T236
Test name
Test status
Simulation time 74721356158 ps
CPU time 24.33 seconds
Started Aug 01 04:23:25 PM PDT 24
Finished Aug 01 04:23:49 PM PDT 24
Peak memory 183408 kb
Host smart-9bfb5db2-6306-46ab-863f-1f930ad9f2c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581554725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.1581554725
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.1419467147
Short name T136
Test name
Test status
Simulation time 42464412985 ps
CPU time 60.73 seconds
Started Aug 01 04:23:25 PM PDT 24
Finished Aug 01 04:24:25 PM PDT 24
Peak memory 191380 kb
Host smart-9618bf20-2cfe-4ef7-905f-ad837b753145
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419467147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.1419467147
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.4178675976
Short name T391
Test name
Test status
Simulation time 102658742641 ps
CPU time 101.4 seconds
Started Aug 01 04:23:24 PM PDT 24
Finished Aug 01 04:25:05 PM PDT 24
Peak memory 183160 kb
Host smart-5184f3cc-100f-4003-bcae-bcb51027ef87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178675976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.4178675976
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.4167844957
Short name T427
Test name
Test status
Simulation time 28176269596 ps
CPU time 14.41 seconds
Started Aug 01 04:22:37 PM PDT 24
Finished Aug 01 04:22:52 PM PDT 24
Peak memory 182048 kb
Host smart-f8a70a16-4e91-4c37-a36a-a9b8a0b43248
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167844957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.4167844957
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.1215203575
Short name T441
Test name
Test status
Simulation time 261359886646 ps
CPU time 74.74 seconds
Started Aug 01 04:24:16 PM PDT 24
Finished Aug 01 04:25:31 PM PDT 24
Peak memory 182840 kb
Host smart-451ea8a8-d698-43b5-9d8e-5f9c188f04ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215203575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.1215203575
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.2599256282
Short name T266
Test name
Test status
Simulation time 75156482976 ps
CPU time 63.47 seconds
Started Aug 01 04:22:37 PM PDT 24
Finished Aug 01 04:23:40 PM PDT 24
Peak memory 191392 kb
Host smart-202087a6-9dbb-4ef8-9c1e-99250905a3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599256282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.2599256282
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/132.rv_timer_random.1452728337
Short name T451
Test name
Test status
Simulation time 17363961194 ps
CPU time 27.24 seconds
Started Aug 01 04:23:25 PM PDT 24
Finished Aug 01 04:23:53 PM PDT 24
Peak memory 183244 kb
Host smart-c54c2b3e-4c8f-4fb9-b724-dbbafde77f1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452728337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.1452728337
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.790109479
Short name T125
Test name
Test status
Simulation time 870651594257 ps
CPU time 324.35 seconds
Started Aug 01 04:23:25 PM PDT 24
Finished Aug 01 04:28:49 PM PDT 24
Peak memory 191852 kb
Host smart-a27eae5b-b4ac-4392-8cf1-c5b62370fd29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790109479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.790109479
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.104419198
Short name T429
Test name
Test status
Simulation time 48613365635 ps
CPU time 59.56 seconds
Started Aug 01 04:23:28 PM PDT 24
Finished Aug 01 04:24:28 PM PDT 24
Peak memory 183248 kb
Host smart-f6e74f5d-e588-42f3-a25a-4942bd006e55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104419198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.104419198
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.4113981407
Short name T250
Test name
Test status
Simulation time 839296019651 ps
CPU time 477.9 seconds
Started Aug 01 04:23:23 PM PDT 24
Finished Aug 01 04:31:21 PM PDT 24
Peak memory 191584 kb
Host smart-5bd270a8-a725-4938-ace0-dab0cc40a441
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113981407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.4113981407
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.133123872
Short name T312
Test name
Test status
Simulation time 543174899867 ps
CPU time 491.77 seconds
Started Aug 01 04:23:24 PM PDT 24
Finished Aug 01 04:31:36 PM PDT 24
Peak memory 191596 kb
Host smart-5755bf36-de42-4532-b08b-2d4582b0dad4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133123872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.133123872
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.2907641855
Short name T392
Test name
Test status
Simulation time 26313915984 ps
CPU time 9.68 seconds
Started Aug 01 04:22:23 PM PDT 24
Finished Aug 01 04:22:33 PM PDT 24
Peak memory 182232 kb
Host smart-2af03542-cc06-4257-88e3-c477c08623ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907641855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.2907641855
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.4143300388
Short name T231
Test name
Test status
Simulation time 176944155936 ps
CPU time 238.88 seconds
Started Aug 01 04:22:23 PM PDT 24
Finished Aug 01 04:26:23 PM PDT 24
Peak memory 190392 kb
Host smart-c9c9049d-64cc-47d0-b616-5df67b8f1f36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143300388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.4143300388
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.2844232500
Short name T109
Test name
Test status
Simulation time 32284077132 ps
CPU time 12.3 seconds
Started Aug 01 04:23:02 PM PDT 24
Finished Aug 01 04:23:14 PM PDT 24
Peak memory 183024 kb
Host smart-f1f0e3a5-e4d7-447d-adfd-c1ad2e6e59c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844232500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.2844232500
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.2264539828
Short name T413
Test name
Test status
Simulation time 38671483 ps
CPU time 0.63 seconds
Started Aug 01 04:23:25 PM PDT 24
Finished Aug 01 04:23:26 PM PDT 24
Peak memory 182944 kb
Host smart-0d5aee3b-ce3f-402d-beca-e6936999872b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264539828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.2264539828
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/141.rv_timer_random.2363015762
Short name T255
Test name
Test status
Simulation time 49993323255 ps
CPU time 243.5 seconds
Started Aug 01 04:23:30 PM PDT 24
Finished Aug 01 04:27:33 PM PDT 24
Peak memory 194720 kb
Host smart-a7df36a0-e83a-4c87-bcba-51c6730cf87c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363015762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.2363015762
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.1905527752
Short name T332
Test name
Test status
Simulation time 419343333022 ps
CPU time 209.35 seconds
Started Aug 01 04:23:24 PM PDT 24
Finished Aug 01 04:26:54 PM PDT 24
Peak memory 191436 kb
Host smart-e564f5c5-5b07-419f-be9d-c175e2b3f20b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905527752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.1905527752
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.3070361527
Short name T135
Test name
Test status
Simulation time 188662761821 ps
CPU time 1217.1 seconds
Started Aug 01 04:23:25 PM PDT 24
Finished Aug 01 04:43:43 PM PDT 24
Peak memory 191380 kb
Host smart-f8d28761-5a72-4549-9ec8-9204afaea330
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070361527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.3070361527
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.2410988834
Short name T327
Test name
Test status
Simulation time 60907915115 ps
CPU time 277.66 seconds
Started Aug 01 04:23:24 PM PDT 24
Finished Aug 01 04:28:02 PM PDT 24
Peak memory 191460 kb
Host smart-2c4013cc-f398-4d65-a92e-5c01a864f68b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410988834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.2410988834
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.1787058886
Short name T9
Test name
Test status
Simulation time 87557496760 ps
CPU time 385.29 seconds
Started Aug 01 04:23:26 PM PDT 24
Finished Aug 01 04:29:52 PM PDT 24
Peak memory 191432 kb
Host smart-204f1e6a-adea-4623-9f3e-a0908bc2c918
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787058886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.1787058886
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.1654865959
Short name T271
Test name
Test status
Simulation time 63253578884 ps
CPU time 292.59 seconds
Started Aug 01 04:23:27 PM PDT 24
Finished Aug 01 04:28:20 PM PDT 24
Peak memory 191428 kb
Host smart-3c1a862c-59dd-48a4-9b9a-ccefda1bf937
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654865959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.1654865959
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.3326027580
Short name T112
Test name
Test status
Simulation time 2409870248817 ps
CPU time 671.13 seconds
Started Aug 01 04:23:27 PM PDT 24
Finished Aug 01 04:34:39 PM PDT 24
Peak memory 183228 kb
Host smart-1b6e2a50-43c3-4541-aa59-b4b1490e009a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326027580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.3326027580
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.1438368443
Short name T417
Test name
Test status
Simulation time 737090029511 ps
CPU time 296.99 seconds
Started Aug 01 04:20:36 PM PDT 24
Finished Aug 01 04:25:33 PM PDT 24
Peak memory 183380 kb
Host smart-aa0ded73-9565-4bc5-a49e-a6176b47e9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438368443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.1438368443
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.41627130
Short name T215
Test name
Test status
Simulation time 55072600086 ps
CPU time 347.34 seconds
Started Aug 01 04:23:03 PM PDT 24
Finished Aug 01 04:28:50 PM PDT 24
Peak memory 191088 kb
Host smart-e0c8e6fe-f0da-4732-bef0-d3ac1c977862
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41627130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.41627130
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.2513363619
Short name T343
Test name
Test status
Simulation time 1953373231 ps
CPU time 3.68 seconds
Started Aug 01 04:22:59 PM PDT 24
Finished Aug 01 04:23:03 PM PDT 24
Peak memory 182752 kb
Host smart-a541ffdc-82a3-4b94-b2a5-65f06e6d3663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513363619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.2513363619
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.2095690946
Short name T53
Test name
Test status
Simulation time 716456669777 ps
CPU time 467.09 seconds
Started Aug 01 04:22:26 PM PDT 24
Finished Aug 01 04:30:13 PM PDT 24
Peak memory 191124 kb
Host smart-fd94fccc-e340-4acc-b0a7-c1053b694fa1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095690946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.2095690946
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/151.rv_timer_random.3317507906
Short name T219
Test name
Test status
Simulation time 263553942676 ps
CPU time 280.56 seconds
Started Aug 01 04:23:29 PM PDT 24
Finished Aug 01 04:28:10 PM PDT 24
Peak memory 191428 kb
Host smart-b3fc4f5e-da35-4554-837b-94ae286997a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317507906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.3317507906
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.3732380369
Short name T183
Test name
Test status
Simulation time 263398777401 ps
CPU time 133.45 seconds
Started Aug 01 04:23:25 PM PDT 24
Finished Aug 01 04:25:38 PM PDT 24
Peak memory 191364 kb
Host smart-b485967e-0311-4fd3-93b0-6ea7348b412d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732380369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.3732380369
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.3461916033
Short name T331
Test name
Test status
Simulation time 67988661184 ps
CPU time 108.1 seconds
Started Aug 01 04:23:29 PM PDT 24
Finished Aug 01 04:25:17 PM PDT 24
Peak memory 191428 kb
Host smart-4401e83b-98bf-4c63-872a-7ca8cfeaea67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461916033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.3461916033
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.912842065
Short name T281
Test name
Test status
Simulation time 109781167724 ps
CPU time 163.21 seconds
Started Aug 01 04:23:26 PM PDT 24
Finished Aug 01 04:26:10 PM PDT 24
Peak memory 191452 kb
Host smart-90922fa3-d42b-4736-9f11-62118dc58e65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912842065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.912842065
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.2720324815
Short name T397
Test name
Test status
Simulation time 43384132061 ps
CPU time 21.06 seconds
Started Aug 01 04:23:25 PM PDT 24
Finished Aug 01 04:23:46 PM PDT 24
Peak memory 183200 kb
Host smart-1f3134b6-08ca-436e-b539-5ce285684df0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720324815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.2720324815
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.735900496
Short name T217
Test name
Test status
Simulation time 948208603330 ps
CPU time 454.7 seconds
Started Aug 01 04:23:25 PM PDT 24
Finished Aug 01 04:31:00 PM PDT 24
Peak memory 191380 kb
Host smart-55214a02-5709-4d67-b226-d3cdb7c21796
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735900496 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.735900496
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.2391262978
Short name T377
Test name
Test status
Simulation time 43699293510 ps
CPU time 69.68 seconds
Started Aug 01 04:23:24 PM PDT 24
Finished Aug 01 04:24:34 PM PDT 24
Peak memory 183268 kb
Host smart-332b6c5a-5cf7-44cc-a247-4967c25a7f08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391262978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.2391262978
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.4015936383
Short name T262
Test name
Test status
Simulation time 244154236975 ps
CPU time 119.76 seconds
Started Aug 01 04:23:23 PM PDT 24
Finished Aug 01 04:25:23 PM PDT 24
Peak memory 191588 kb
Host smart-29b36fc3-823a-4be0-a71c-34a7b0af0d38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015936383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.4015936383
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.1303012842
Short name T434
Test name
Test status
Simulation time 123257549399 ps
CPU time 108.27 seconds
Started Aug 01 04:23:25 PM PDT 24
Finished Aug 01 04:25:14 PM PDT 24
Peak memory 191408 kb
Host smart-46ae9505-0b97-40bb-a012-48d1cfe199c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303012842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.1303012842
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.2642306078
Short name T375
Test name
Test status
Simulation time 170438848605 ps
CPU time 67.39 seconds
Started Aug 01 04:22:58 PM PDT 24
Finished Aug 01 04:24:05 PM PDT 24
Peak memory 182992 kb
Host smart-f74386a7-09f8-493d-b287-4a59587e14ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642306078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.2642306078
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.1527797299
Short name T285
Test name
Test status
Simulation time 638327488555 ps
CPU time 286.77 seconds
Started Aug 01 04:22:49 PM PDT 24
Finished Aug 01 04:27:36 PM PDT 24
Peak memory 191172 kb
Host smart-a3c4e9db-9fe6-48fa-ae75-2830ecdbe5ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527797299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.1527797299
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.981194252
Short name T361
Test name
Test status
Simulation time 189030694 ps
CPU time 0.86 seconds
Started Aug 01 04:22:29 PM PDT 24
Finished Aug 01 04:22:30 PM PDT 24
Peak memory 191304 kb
Host smart-9826bd1e-7903-4746-94d4-a6ff2ea3e4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981194252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.981194252
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all_with_rand_reset.386848266
Short name T38
Test name
Test status
Simulation time 111729393245 ps
CPU time 197.23 seconds
Started Aug 01 04:22:53 PM PDT 24
Finished Aug 01 04:26:11 PM PDT 24
Peak memory 196908 kb
Host smart-a9fb2945-37c3-473e-93e5-b6b08a51c8c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386848266 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all_with_rand_reset.386848266
Directory /workspace/16.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/163.rv_timer_random.3045139948
Short name T175
Test name
Test status
Simulation time 673746648507 ps
CPU time 398.61 seconds
Started Aug 01 04:23:37 PM PDT 24
Finished Aug 01 04:30:16 PM PDT 24
Peak memory 191416 kb
Host smart-d2b66ae4-7555-40d2-9d73-3fe5372df857
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045139948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.3045139948
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.472963983
Short name T234
Test name
Test status
Simulation time 53231083087 ps
CPU time 42.89 seconds
Started Aug 01 04:23:37 PM PDT 24
Finished Aug 01 04:24:20 PM PDT 24
Peak memory 183228 kb
Host smart-06e53c7f-2b3d-4d84-957a-f420206a83e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472963983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.472963983
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.3161188620
Short name T25
Test name
Test status
Simulation time 189555545165 ps
CPU time 77.81 seconds
Started Aug 01 04:23:39 PM PDT 24
Finished Aug 01 04:24:58 PM PDT 24
Peak memory 183244 kb
Host smart-0ddfbdc0-ba8b-490e-a10e-a20488363cb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161188620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.3161188620
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.3306851992
Short name T425
Test name
Test status
Simulation time 291419234862 ps
CPU time 240.47 seconds
Started Aug 01 04:23:38 PM PDT 24
Finished Aug 01 04:27:38 PM PDT 24
Peak memory 191448 kb
Host smart-077e49e1-da13-4fc2-b170-22b89ab67387
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306851992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.3306851992
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.2060902877
Short name T322
Test name
Test status
Simulation time 57048778892 ps
CPU time 95.42 seconds
Started Aug 01 04:23:37 PM PDT 24
Finished Aug 01 04:25:13 PM PDT 24
Peak memory 195004 kb
Host smart-64e0df70-fa28-4f06-a7de-0ae3719bf820
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060902877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.2060902877
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.1587319985
Short name T46
Test name
Test status
Simulation time 601947829966 ps
CPU time 252.91 seconds
Started Aug 01 04:22:57 PM PDT 24
Finished Aug 01 04:27:10 PM PDT 24
Peak memory 182960 kb
Host smart-53b7183a-7078-47d2-9495-374d7128cdb6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587319985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.1587319985
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.1489255068
Short name T440
Test name
Test status
Simulation time 198857651062 ps
CPU time 286.31 seconds
Started Aug 01 04:22:43 PM PDT 24
Finished Aug 01 04:27:29 PM PDT 24
Peak memory 183220 kb
Host smart-153ec433-5256-4e44-9b6c-10081ced034c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489255068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.1489255068
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.3477426921
Short name T193
Test name
Test status
Simulation time 8643584918 ps
CPU time 5.26 seconds
Started Aug 01 04:22:29 PM PDT 24
Finished Aug 01 04:22:35 PM PDT 24
Peak memory 182336 kb
Host smart-211e20b0-04c0-49b7-a3ee-47c056645486
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477426921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.3477426921
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.843161494
Short name T335
Test name
Test status
Simulation time 73387963396 ps
CPU time 942.42 seconds
Started Aug 01 04:22:56 PM PDT 24
Finished Aug 01 04:38:39 PM PDT 24
Peak memory 182900 kb
Host smart-ef45592f-804c-4e4c-9285-61cfe3642680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843161494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.843161494
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.3972086684
Short name T370
Test name
Test status
Simulation time 242960203133 ps
CPU time 168.15 seconds
Started Aug 01 04:22:25 PM PDT 24
Finished Aug 01 04:25:14 PM PDT 24
Peak memory 182236 kb
Host smart-473f49be-c28d-42f4-8eec-b5d781e93c5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972086684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.3972086684
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/172.rv_timer_random.604755931
Short name T306
Test name
Test status
Simulation time 60815085785 ps
CPU time 297.09 seconds
Started Aug 01 04:23:37 PM PDT 24
Finished Aug 01 04:28:35 PM PDT 24
Peak memory 191452 kb
Host smart-f7d8c257-3944-4db8-b782-05f6d4e7e50b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604755931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.604755931
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.3851676203
Short name T119
Test name
Test status
Simulation time 15349249588 ps
CPU time 11.81 seconds
Started Aug 01 04:23:38 PM PDT 24
Finished Aug 01 04:23:49 PM PDT 24
Peak memory 183196 kb
Host smart-3c1aad57-dc03-4597-8daf-9e5f44366c88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851676203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.3851676203
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.2393005351
Short name T310
Test name
Test status
Simulation time 615284568860 ps
CPU time 210.06 seconds
Started Aug 01 04:23:37 PM PDT 24
Finished Aug 01 04:27:07 PM PDT 24
Peak memory 191464 kb
Host smart-a3989ca9-dd4b-4d29-bbc5-50c6aa7659b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393005351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.2393005351
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.3948888456
Short name T297
Test name
Test status
Simulation time 882418755518 ps
CPU time 194.33 seconds
Started Aug 01 04:23:35 PM PDT 24
Finished Aug 01 04:26:50 PM PDT 24
Peak memory 191448 kb
Host smart-2aa25473-8862-40a3-883d-2879a9d170ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948888456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.3948888456
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.3822159132
Short name T433
Test name
Test status
Simulation time 120403969462 ps
CPU time 196.33 seconds
Started Aug 01 04:18:37 PM PDT 24
Finished Aug 01 04:21:54 PM PDT 24
Peak memory 183324 kb
Host smart-05c5faa5-ced3-4f6d-a2fa-1ac6ba4ad4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822159132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.3822159132
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.3050264958
Short name T340
Test name
Test status
Simulation time 58488477810 ps
CPU time 236.82 seconds
Started Aug 01 04:23:04 PM PDT 24
Finished Aug 01 04:27:01 PM PDT 24
Peak memory 191452 kb
Host smart-79c3c334-cd7f-41c1-8220-590a2d0eb420
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050264958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.3050264958
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.1298536112
Short name T191
Test name
Test status
Simulation time 46612705820 ps
CPU time 68.73 seconds
Started Aug 01 04:23:13 PM PDT 24
Finished Aug 01 04:24:22 PM PDT 24
Peak memory 191096 kb
Host smart-da015090-7076-4712-b9e0-b9d10339f5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298536112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.1298536112
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/180.rv_timer_random.1937702318
Short name T414
Test name
Test status
Simulation time 204574479006 ps
CPU time 79.46 seconds
Started Aug 01 04:23:38 PM PDT 24
Finished Aug 01 04:24:57 PM PDT 24
Peak memory 183180 kb
Host smart-c76f888c-42b3-4f8e-8e5b-a1e0fc4b4f88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937702318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.1937702318
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.215621447
Short name T21
Test name
Test status
Simulation time 708178334530 ps
CPU time 698.17 seconds
Started Aug 01 04:23:39 PM PDT 24
Finished Aug 01 04:35:18 PM PDT 24
Peak memory 191412 kb
Host smart-1086d212-21b6-4556-a7ae-65baed1b194e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215621447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.215621447
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.3150849803
Short name T256
Test name
Test status
Simulation time 348322865618 ps
CPU time 92.35 seconds
Started Aug 01 04:23:39 PM PDT 24
Finished Aug 01 04:25:12 PM PDT 24
Peak memory 191364 kb
Host smart-28eaf722-eb01-40fb-ad3f-217d26f51c08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150849803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.3150849803
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.74090025
Short name T182
Test name
Test status
Simulation time 90500181352 ps
CPU time 182.04 seconds
Started Aug 01 04:23:40 PM PDT 24
Finished Aug 01 04:26:43 PM PDT 24
Peak memory 195064 kb
Host smart-c21abf24-b606-4500-9c15-01148f4513ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74090025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.74090025
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.467701442
Short name T293
Test name
Test status
Simulation time 321830722645 ps
CPU time 273.99 seconds
Started Aug 01 04:23:40 PM PDT 24
Finished Aug 01 04:28:15 PM PDT 24
Peak memory 191428 kb
Host smart-28718826-049c-4f8a-a306-5c4a30bca375
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467701442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.467701442
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.396497650
Short name T4
Test name
Test status
Simulation time 271789134188 ps
CPU time 297.37 seconds
Started Aug 01 04:23:38 PM PDT 24
Finished Aug 01 04:28:36 PM PDT 24
Peak memory 191436 kb
Host smart-703e18a3-e523-47c8-ab93-a89096157ff3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396497650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.396497650
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.1300385427
Short name T206
Test name
Test status
Simulation time 152017974580 ps
CPU time 454.86 seconds
Started Aug 01 04:23:35 PM PDT 24
Finished Aug 01 04:31:10 PM PDT 24
Peak memory 193980 kb
Host smart-da32584e-1c74-4f6c-abf3-73ccfab49934
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300385427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.1300385427
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.3215440492
Short name T398
Test name
Test status
Simulation time 443440830833 ps
CPU time 96.54 seconds
Started Aug 01 04:22:56 PM PDT 24
Finished Aug 01 04:24:32 PM PDT 24
Peak memory 183180 kb
Host smart-30f52578-8b33-4a01-b976-3c8ca3e7c306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215440492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.3215440492
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.4052412288
Short name T114
Test name
Test status
Simulation time 23821619480 ps
CPU time 39.55 seconds
Started Aug 01 04:22:40 PM PDT 24
Finished Aug 01 04:23:19 PM PDT 24
Peak memory 181744 kb
Host smart-e89ae944-97e8-497b-9a65-75369ee9e744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052412288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.4052412288
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all_with_rand_reset.574637304
Short name T34
Test name
Test status
Simulation time 494649700411 ps
CPU time 254.23 seconds
Started Aug 01 04:22:40 PM PDT 24
Finished Aug 01 04:26:54 PM PDT 24
Peak memory 207100 kb
Host smart-0b52c668-59db-45b8-855a-1a5fa3a9bd45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574637304 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all_with_rand_reset.574637304
Directory /workspace/19.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.1665403071
Short name T133
Test name
Test status
Simulation time 48897145037 ps
CPU time 41.94 seconds
Started Aug 01 04:23:37 PM PDT 24
Finished Aug 01 04:24:19 PM PDT 24
Peak memory 183204 kb
Host smart-e1329f03-b942-4496-a393-1a32df560fdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665403071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.1665403071
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.3401340151
Short name T134
Test name
Test status
Simulation time 317800789925 ps
CPU time 465.92 seconds
Started Aug 01 04:23:39 PM PDT 24
Finished Aug 01 04:31:25 PM PDT 24
Peak memory 190944 kb
Host smart-68aa2067-172b-4fba-bab9-8aa0d946aa32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401340151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.3401340151
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.3848164027
Short name T19
Test name
Test status
Simulation time 163709177135 ps
CPU time 587.79 seconds
Started Aug 01 04:23:37 PM PDT 24
Finished Aug 01 04:33:25 PM PDT 24
Peak memory 191452 kb
Host smart-d8e7fb99-41c5-4986-9094-81853d56d029
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848164027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.3848164027
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.1079943941
Short name T190
Test name
Test status
Simulation time 81238492897 ps
CPU time 124.1 seconds
Started Aug 01 04:23:35 PM PDT 24
Finished Aug 01 04:25:40 PM PDT 24
Peak memory 191404 kb
Host smart-ceaa95c7-32bf-4b87-aff6-b265ebb87aa6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079943941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.1079943941
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.4216508764
Short name T344
Test name
Test status
Simulation time 234892686822 ps
CPU time 339.3 seconds
Started Aug 01 04:23:40 PM PDT 24
Finished Aug 01 04:29:20 PM PDT 24
Peak memory 191340 kb
Host smart-700f00b9-ce1a-498a-928a-75ef8aa2417f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216508764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.4216508764
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.3098285399
Short name T160
Test name
Test status
Simulation time 33047028351 ps
CPU time 51.57 seconds
Started Aug 01 04:23:41 PM PDT 24
Finished Aug 01 04:24:33 PM PDT 24
Peak memory 191420 kb
Host smart-07b221cb-96ea-4c09-adf5-68d0a1cedde3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098285399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.3098285399
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.2722568745
Short name T194
Test name
Test status
Simulation time 79757540625 ps
CPU time 187.47 seconds
Started Aug 01 04:23:41 PM PDT 24
Finished Aug 01 04:26:49 PM PDT 24
Peak memory 191416 kb
Host smart-98eb1491-0331-46c4-b61a-3d66015a06d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722568745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.2722568745
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.986943696
Short name T415
Test name
Test status
Simulation time 64398120043 ps
CPU time 101.15 seconds
Started Aug 01 04:23:40 PM PDT 24
Finished Aug 01 04:25:22 PM PDT 24
Peak memory 195128 kb
Host smart-39718c61-1568-4539-b4e9-374ecd3edf28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986943696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.986943696
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.1326540943
Short name T123
Test name
Test status
Simulation time 405786150438 ps
CPU time 210.46 seconds
Started Aug 01 04:22:52 PM PDT 24
Finished Aug 01 04:26:22 PM PDT 24
Peak memory 182972 kb
Host smart-8f64e2dc-c771-46c8-81bd-e5b950674a70
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326540943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.1326540943
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.3586258710
Short name T388
Test name
Test status
Simulation time 110316108894 ps
CPU time 164.78 seconds
Started Aug 01 04:22:51 PM PDT 24
Finished Aug 01 04:25:36 PM PDT 24
Peak memory 182912 kb
Host smart-b811cbd6-544a-4b5d-b68c-c874780d32db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586258710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.3586258710
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.961671701
Short name T15
Test name
Test status
Simulation time 146019239 ps
CPU time 0.84 seconds
Started Aug 01 04:22:50 PM PDT 24
Finished Aug 01 04:22:51 PM PDT 24
Peak memory 213428 kb
Host smart-8891deab-a3e1-4121-8752-fa02755a38a3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961671701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.961671701
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.3275238803
Short name T120
Test name
Test status
Simulation time 75911302776 ps
CPU time 26.87 seconds
Started Aug 01 04:23:21 PM PDT 24
Finished Aug 01 04:23:48 PM PDT 24
Peak memory 192896 kb
Host smart-1a16c5da-c34f-44f0-b671-f68b339e5b25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275238803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
3275238803
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.2111561523
Short name T438
Test name
Test status
Simulation time 133356642468 ps
CPU time 211.27 seconds
Started Aug 01 04:18:35 PM PDT 24
Finished Aug 01 04:22:06 PM PDT 24
Peak memory 183180 kb
Host smart-d0455e0f-6f99-4597-b229-441bc74292f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111561523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.2111561523
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.576101633
Short name T369
Test name
Test status
Simulation time 2335613027 ps
CPU time 4.58 seconds
Started Aug 01 04:18:22 PM PDT 24
Finished Aug 01 04:18:26 PM PDT 24
Peak memory 182980 kb
Host smart-33bb3c1d-5818-455a-bb0e-b36fc9a7a92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576101633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.576101633
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all_with_rand_reset.4104213930
Short name T40
Test name
Test status
Simulation time 70283151354 ps
CPU time 472.97 seconds
Started Aug 01 04:18:20 PM PDT 24
Finished Aug 01 04:26:13 PM PDT 24
Peak memory 206168 kb
Host smart-2fb5951a-92ab-4d4a-bcc9-ce760dfed41a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104213930 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all_with_rand_reset.4104213930
Directory /workspace/20.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.1189866753
Short name T334
Test name
Test status
Simulation time 4542294681298 ps
CPU time 1128.49 seconds
Started Aug 01 04:23:02 PM PDT 24
Finished Aug 01 04:41:51 PM PDT 24
Peak memory 183244 kb
Host smart-05e8b33c-5ff4-4c8a-af2b-780565df3dfa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189866753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.1189866753
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.4075630883
Short name T412
Test name
Test status
Simulation time 37876117036 ps
CPU time 59.21 seconds
Started Aug 01 04:18:21 PM PDT 24
Finished Aug 01 04:19:20 PM PDT 24
Peak memory 183416 kb
Host smart-30d3f23f-7c41-4956-aeef-0381bb1fd7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075630883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.4075630883
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.630685077
Short name T113
Test name
Test status
Simulation time 50135104879 ps
CPU time 76.8 seconds
Started Aug 01 04:18:19 PM PDT 24
Finished Aug 01 04:19:36 PM PDT 24
Peak memory 191460 kb
Host smart-398aea7d-ac9d-4f8f-9c82-000dcce3e547
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630685077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.630685077
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.3449761431
Short name T313
Test name
Test status
Simulation time 79538493702 ps
CPU time 30.73 seconds
Started Aug 01 04:22:49 PM PDT 24
Finished Aug 01 04:23:20 PM PDT 24
Peak memory 182956 kb
Host smart-59455d1d-c3d5-4bb4-9ca8-14891b08e162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449761431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.3449761431
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.1983007254
Short name T54
Test name
Test status
Simulation time 30859940740 ps
CPU time 56.28 seconds
Started Aug 01 04:18:20 PM PDT 24
Finished Aug 01 04:19:16 PM PDT 24
Peak memory 191568 kb
Host smart-025ba0e0-3db2-4ec9-a203-4bcb35798919
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983007254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.1983007254
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.2471907518
Short name T137
Test name
Test status
Simulation time 330289979763 ps
CPU time 287.26 seconds
Started Aug 01 04:23:05 PM PDT 24
Finished Aug 01 04:27:52 PM PDT 24
Peak memory 183240 kb
Host smart-8a61c019-d177-4868-bb81-95c702411eab
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471907518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.2471907518
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.553039511
Short name T379
Test name
Test status
Simulation time 66563925770 ps
CPU time 50.64 seconds
Started Aug 01 04:23:09 PM PDT 24
Finished Aug 01 04:24:00 PM PDT 24
Peak memory 183268 kb
Host smart-49630210-1751-423e-ba10-b4966d745928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553039511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.553039511
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.2156087937
Short name T276
Test name
Test status
Simulation time 27613999858 ps
CPU time 52.62 seconds
Started Aug 01 04:19:22 PM PDT 24
Finished Aug 01 04:20:15 PM PDT 24
Peak memory 182580 kb
Host smart-8b005eb1-359d-4cfc-bfce-0590da9e008f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156087937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.2156087937
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.1573678779
Short name T428
Test name
Test status
Simulation time 29667786983 ps
CPU time 44.67 seconds
Started Aug 01 04:22:37 PM PDT 24
Finished Aug 01 04:23:22 PM PDT 24
Peak memory 190932 kb
Host smart-4579ad4e-01d0-49f6-9dbd-04da65f0513d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573678779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.1573678779
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all_with_rand_reset.1173549188
Short name T12
Test name
Test status
Simulation time 156906662626 ps
CPU time 446.25 seconds
Started Aug 01 04:19:26 PM PDT 24
Finished Aug 01 04:26:52 PM PDT 24
Peak memory 206196 kb
Host smart-b9961d66-247d-45c1-a1f8-1b7e5f3705b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173549188 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all_with_rand_reset.1173549188
Directory /workspace/22.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.3721749070
Short name T291
Test name
Test status
Simulation time 22576754464 ps
CPU time 12.05 seconds
Started Aug 01 04:18:50 PM PDT 24
Finished Aug 01 04:19:02 PM PDT 24
Peak memory 183392 kb
Host smart-41b3b856-f34c-4b1f-a768-bd97b68fe4d6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721749070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.3721749070
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.377421132
Short name T383
Test name
Test status
Simulation time 231027165745 ps
CPU time 151.59 seconds
Started Aug 01 04:20:54 PM PDT 24
Finished Aug 01 04:23:26 PM PDT 24
Peak memory 182876 kb
Host smart-964e2473-1788-40e5-9ca7-19e09c7ea8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377421132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.377421132
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.3888306923
Short name T349
Test name
Test status
Simulation time 290680219677 ps
CPU time 74.02 seconds
Started Aug 01 04:23:34 PM PDT 24
Finished Aug 01 04:24:49 PM PDT 24
Peak memory 191448 kb
Host smart-d44461ba-3e08-4574-b5fe-6da93650f47c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888306923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.3888306923
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.2525291095
Short name T409
Test name
Test status
Simulation time 61346989964 ps
CPU time 30.23 seconds
Started Aug 01 04:23:03 PM PDT 24
Finished Aug 01 04:23:34 PM PDT 24
Peak memory 182352 kb
Host smart-54ed11f0-6bea-41d8-9963-bcd658ab6061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525291095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.2525291095
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.3243395146
Short name T384
Test name
Test status
Simulation time 742732946914 ps
CPU time 415.87 seconds
Started Aug 01 04:23:17 PM PDT 24
Finished Aug 01 04:30:13 PM PDT 24
Peak memory 182936 kb
Host smart-11116ec4-092c-424c-a415-ef8e3d23f7cf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243395146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.3243395146
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.3472938049
Short name T396
Test name
Test status
Simulation time 51203017648 ps
CPU time 71.76 seconds
Started Aug 01 04:21:44 PM PDT 24
Finished Aug 01 04:22:55 PM PDT 24
Peak memory 183388 kb
Host smart-5cfdebc8-045e-451b-b3b2-bd4ab92a5293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472938049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.3472938049
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.1410173784
Short name T257
Test name
Test status
Simulation time 129204194509 ps
CPU time 377.01 seconds
Started Aug 01 04:22:44 PM PDT 24
Finished Aug 01 04:29:01 PM PDT 24
Peak memory 191448 kb
Host smart-ad5e4ad1-e4c4-4c21-ba32-d7f94fb5cdc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410173784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.1410173784
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.351439088
Short name T405
Test name
Test status
Simulation time 19625653 ps
CPU time 0.55 seconds
Started Aug 01 04:22:29 PM PDT 24
Finished Aug 01 04:22:30 PM PDT 24
Peak memory 181700 kb
Host smart-bfbde3c3-179e-46a4-88a4-e9529ffe28cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351439088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.351439088
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.2481852813
Short name T163
Test name
Test status
Simulation time 385290753164 ps
CPU time 1042.51 seconds
Started Aug 01 04:22:49 PM PDT 24
Finished Aug 01 04:40:12 PM PDT 24
Peak memory 191168 kb
Host smart-793ad34e-7be2-4949-888e-27a123c8666c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481852813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.2481852813
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.626098887
Short name T24
Test name
Test status
Simulation time 344239846291 ps
CPU time 75.92 seconds
Started Aug 01 04:20:46 PM PDT 24
Finished Aug 01 04:22:03 PM PDT 24
Peak memory 180352 kb
Host smart-d1246bdc-767f-4510-9abc-01832bc86b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626098887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.626098887
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.3868041409
Short name T211
Test name
Test status
Simulation time 372176949487 ps
CPU time 173.49 seconds
Started Aug 01 04:20:46 PM PDT 24
Finished Aug 01 04:23:40 PM PDT 24
Peak memory 188584 kb
Host smart-67f8d1ad-32e9-4ecb-ad2f-813d63614e9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868041409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.3868041409
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.1498552155
Short name T444
Test name
Test status
Simulation time 37227701 ps
CPU time 0.6 seconds
Started Aug 01 04:21:24 PM PDT 24
Finished Aug 01 04:21:25 PM PDT 24
Peak memory 183168 kb
Host smart-0e9e0f4d-4e72-4807-8b82-cddebaf189d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498552155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.1498552155
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.1750432067
Short name T214
Test name
Test status
Simulation time 1126070329443 ps
CPU time 221.74 seconds
Started Aug 01 04:22:35 PM PDT 24
Finished Aug 01 04:26:17 PM PDT 24
Peak memory 183000 kb
Host smart-ab6040bf-f677-475d-ade2-94a405a067e4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750432067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.1750432067
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.3483897597
Short name T395
Test name
Test status
Simulation time 81449664725 ps
CPU time 109.27 seconds
Started Aug 01 04:22:50 PM PDT 24
Finished Aug 01 04:24:39 PM PDT 24
Peak memory 182980 kb
Host smart-f40d1a1d-0d5c-479d-8e20-518bb25f5f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483897597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.3483897597
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.979591101
Short name T152
Test name
Test status
Simulation time 57036858944 ps
CPU time 172.23 seconds
Started Aug 01 04:18:36 PM PDT 24
Finished Aug 01 04:21:28 PM PDT 24
Peak memory 195112 kb
Host smart-0ac33449-4dc0-4349-b812-24826df4564d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979591101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.979591101
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.1228917950
Short name T439
Test name
Test status
Simulation time 159779792080 ps
CPU time 74.39 seconds
Started Aug 01 04:18:44 PM PDT 24
Finished Aug 01 04:19:59 PM PDT 24
Peak memory 191524 kb
Host smart-15db31ae-7976-4a06-908a-fb4dc164affb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228917950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.1228917950
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.1867474054
Short name T295
Test name
Test status
Simulation time 29938584593 ps
CPU time 13.59 seconds
Started Aug 01 04:18:49 PM PDT 24
Finished Aug 01 04:19:03 PM PDT 24
Peak memory 183380 kb
Host smart-f2188fce-1e3a-45d4-bba0-aa5bf1bc8081
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867474054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.1867474054
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.1520275879
Short name T385
Test name
Test status
Simulation time 694617071340 ps
CPU time 235.89 seconds
Started Aug 01 04:22:49 PM PDT 24
Finished Aug 01 04:26:45 PM PDT 24
Peak memory 182980 kb
Host smart-71b444d0-2774-4e81-821c-e1add1cb6093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520275879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.1520275879
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.3230381610
Short name T408
Test name
Test status
Simulation time 264836985 ps
CPU time 0.93 seconds
Started Aug 01 04:19:14 PM PDT 24
Finished Aug 01 04:19:15 PM PDT 24
Peak memory 183152 kb
Host smart-b36d4349-3749-438c-bd6f-f85744d058ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230381610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.3230381610
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.3299218573
Short name T192
Test name
Test status
Simulation time 259317868056 ps
CPU time 950.3 seconds
Started Aug 01 04:19:14 PM PDT 24
Finished Aug 01 04:35:04 PM PDT 24
Peak memory 191580 kb
Host smart-e83291a4-605b-4df1-b9f1-73775fbe94fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299218573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.3299218573
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.2144329357
Short name T272
Test name
Test status
Simulation time 111727608232 ps
CPU time 164.63 seconds
Started Aug 01 04:22:34 PM PDT 24
Finished Aug 01 04:25:19 PM PDT 24
Peak memory 183000 kb
Host smart-357170f8-ac51-4cc6-b665-b9b365405b00
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144329357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.2144329357
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.3818096628
Short name T362
Test name
Test status
Simulation time 95293524209 ps
CPU time 124.76 seconds
Started Aug 01 04:18:49 PM PDT 24
Finished Aug 01 04:20:54 PM PDT 24
Peak memory 183392 kb
Host smart-301a88ba-9541-4cf0-97af-13f0377d7879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818096628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.3818096628
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.3800578834
Short name T222
Test name
Test status
Simulation time 160646610655 ps
CPU time 553.08 seconds
Started Aug 01 04:22:29 PM PDT 24
Finished Aug 01 04:31:43 PM PDT 24
Peak memory 190516 kb
Host smart-9480cc77-ae52-414e-bdaf-f13274c48174
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800578834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.3800578834
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.1269678269
Short name T352
Test name
Test status
Simulation time 46393044094 ps
CPU time 112.68 seconds
Started Aug 01 04:22:37 PM PDT 24
Finished Aug 01 04:24:31 PM PDT 24
Peak memory 190764 kb
Host smart-2cfaaba5-3ef5-4a3d-aac0-5d5ec29663d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269678269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.1269678269
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.3208114801
Short name T378
Test name
Test status
Simulation time 136069714821 ps
CPU time 195.91 seconds
Started Aug 01 04:18:45 PM PDT 24
Finished Aug 01 04:22:01 PM PDT 24
Peak memory 191552 kb
Host smart-6ad8ac56-432a-4276-8f57-d17960d90ca7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208114801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.3208114801
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all_with_rand_reset.3078184880
Short name T177
Test name
Test status
Simulation time 399550112235 ps
CPU time 836.76 seconds
Started Aug 01 04:22:29 PM PDT 24
Finished Aug 01 04:36:26 PM PDT 24
Peak memory 211876 kb
Host smart-555f8c1c-dca0-4eeb-b85f-ebd7de97ed80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078184880 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all_with_rand_reset.3078184880
Directory /workspace/28.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.1754764010
Short name T368
Test name
Test status
Simulation time 96485098046 ps
CPU time 150.26 seconds
Started Aug 01 04:22:33 PM PDT 24
Finished Aug 01 04:25:04 PM PDT 24
Peak memory 182960 kb
Host smart-f5a3ccb8-11c9-460f-a86d-1c07ae4201e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754764010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.1754764010
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.2771700315
Short name T124
Test name
Test status
Simulation time 378808244308 ps
CPU time 73.42 seconds
Started Aug 01 04:22:27 PM PDT 24
Finished Aug 01 04:23:41 PM PDT 24
Peak memory 190688 kb
Host smart-caa0f6ed-421e-44ea-8870-b422b7a5c74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771700315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.2771700315
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.1991019084
Short name T181
Test name
Test status
Simulation time 2041773264904 ps
CPU time 1053.6 seconds
Started Aug 01 04:19:50 PM PDT 24
Finished Aug 01 04:37:24 PM PDT 24
Peak memory 183396 kb
Host smart-a4b7f1c9-d7d7-4ef1-a0af-be406075edf5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991019084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.1991019084
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.1713131328
Short name T380
Test name
Test status
Simulation time 328141042273 ps
CPU time 244.29 seconds
Started Aug 01 04:22:40 PM PDT 24
Finished Aug 01 04:26:44 PM PDT 24
Peak memory 182624 kb
Host smart-62059c34-5777-49cd-801d-0182f44e4725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713131328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.1713131328
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.1005883436
Short name T154
Test name
Test status
Simulation time 141129061498 ps
CPU time 251.49 seconds
Started Aug 01 04:23:25 PM PDT 24
Finished Aug 01 04:27:36 PM PDT 24
Peak memory 194700 kb
Host smart-795a2045-dcb3-4ebb-9aaa-fa05608a3bcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005883436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.1005883436
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.3834935068
Short name T366
Test name
Test status
Simulation time 82654153 ps
CPU time 0.69 seconds
Started Aug 01 04:23:13 PM PDT 24
Finished Aug 01 04:23:14 PM PDT 24
Peak memory 182508 kb
Host smart-88de9ed0-cddb-4e1d-88a1-7118e1f15dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834935068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.3834935068
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.2698267208
Short name T16
Test name
Test status
Simulation time 59618168 ps
CPU time 0.81 seconds
Started Aug 01 04:19:26 PM PDT 24
Finished Aug 01 04:19:27 PM PDT 24
Peak memory 214504 kb
Host smart-77c5c15a-59c7-4d8b-9660-60f67678828d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698267208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.2698267208
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.2618099604
Short name T129
Test name
Test status
Simulation time 253526705779 ps
CPU time 479.52 seconds
Started Aug 01 04:22:58 PM PDT 24
Finished Aug 01 04:30:58 PM PDT 24
Peak memory 191180 kb
Host smart-84c8f12d-a2c2-45da-bc84-8cb9e34749c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618099604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
2618099604
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all_with_rand_reset.2046344552
Short name T13
Test name
Test status
Simulation time 248801902001 ps
CPU time 1361.2 seconds
Started Aug 01 04:22:51 PM PDT 24
Finished Aug 01 04:45:33 PM PDT 24
Peak memory 222476 kb
Host smart-aa6c3a1b-a828-44c1-9a5a-e285ca5c25c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046344552 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all_with_rand_reset.2046344552
Directory /workspace/3.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.2550829515
Short name T341
Test name
Test status
Simulation time 284104944956 ps
CPU time 200.01 seconds
Started Aug 01 04:19:09 PM PDT 24
Finished Aug 01 04:22:29 PM PDT 24
Peak memory 183268 kb
Host smart-cc2f73f5-b3f2-4f71-b478-3afbe2c3c945
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550829515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.2550829515
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.3383421840
Short name T401
Test name
Test status
Simulation time 170605625687 ps
CPU time 197.62 seconds
Started Aug 01 04:22:28 PM PDT 24
Finished Aug 01 04:25:46 PM PDT 24
Peak memory 182924 kb
Host smart-003d8143-23eb-4fe1-a630-b71fc3015c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383421840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.3383421840
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.364733506
Short name T115
Test name
Test status
Simulation time 206207322036 ps
CPU time 222.72 seconds
Started Aug 01 04:19:09 PM PDT 24
Finished Aug 01 04:22:52 PM PDT 24
Peak memory 191468 kb
Host smart-1f5b474d-413e-46c2-8199-2eb475cf3f90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364733506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.364733506
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.4150453059
Short name T259
Test name
Test status
Simulation time 238769669462 ps
CPU time 1859.3 seconds
Started Aug 01 04:19:06 PM PDT 24
Finished Aug 01 04:50:06 PM PDT 24
Peak memory 191860 kb
Host smart-b2547691-b4f0-4291-b3e1-581187c07c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150453059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.4150453059
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.1348026473
Short name T220
Test name
Test status
Simulation time 1100287329591 ps
CPU time 2095.08 seconds
Started Aug 01 04:22:29 PM PDT 24
Finished Aug 01 04:57:24 PM PDT 24
Peak memory 189856 kb
Host smart-d8fdf359-5b0b-4e48-8bb3-a3ba0eb3f0ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348026473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.1348026473
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.1038656719
Short name T44
Test name
Test status
Simulation time 1873137741251 ps
CPU time 864.45 seconds
Started Aug 01 04:19:07 PM PDT 24
Finished Aug 01 04:33:32 PM PDT 24
Peak memory 183436 kb
Host smart-ad7e3a1c-36e5-4bf8-9167-8e2e0bac5b56
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038656719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.1038656719
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.1465474611
Short name T261
Test name
Test status
Simulation time 215307524544 ps
CPU time 151 seconds
Started Aug 01 04:22:43 PM PDT 24
Finished Aug 01 04:25:15 PM PDT 24
Peak memory 191456 kb
Host smart-b57c7560-ab2b-40b6-b0c0-a5a133a81d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465474611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.1465474611
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all_with_rand_reset.889938118
Short name T36
Test name
Test status
Simulation time 136779133693 ps
CPU time 1387.88 seconds
Started Aug 01 04:23:01 PM PDT 24
Finished Aug 01 04:46:10 PM PDT 24
Peak memory 222212 kb
Host smart-9266c53a-d2af-40d6-bf92-f870e2701a7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889938118 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all_with_rand_reset.889938118
Directory /workspace/31.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.2420570655
Short name T164
Test name
Test status
Simulation time 271535596824 ps
CPU time 126.75 seconds
Started Aug 01 04:19:26 PM PDT 24
Finished Aug 01 04:21:33 PM PDT 24
Peak memory 183376 kb
Host smart-fae8aea5-48c2-4710-9990-10863109e59d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420570655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.2420570655
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.1351461067
Short name T245
Test name
Test status
Simulation time 15940008733 ps
CPU time 534.76 seconds
Started Aug 01 04:23:13 PM PDT 24
Finished Aug 01 04:32:08 PM PDT 24
Peak memory 183032 kb
Host smart-5763dc4c-8904-4070-b18d-92f3bd14552e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351461067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.1351461067
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.1295547824
Short name T103
Test name
Test status
Simulation time 746109112861 ps
CPU time 1847.38 seconds
Started Aug 01 04:20:55 PM PDT 24
Finished Aug 01 04:51:42 PM PDT 24
Peak memory 191076 kb
Host smart-ecd27905-fe7a-4384-ae20-a786e49f374e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295547824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.1295547824
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.696368661
Short name T228
Test name
Test status
Simulation time 160674122576 ps
CPU time 138.12 seconds
Started Aug 01 04:20:54 PM PDT 24
Finished Aug 01 04:23:12 PM PDT 24
Peak memory 182896 kb
Host smart-5d5f1bdf-d5aa-4999-b76e-04d22aabc545
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696368661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.rv_timer_cfg_update_on_fly.696368661
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.2788068518
Short name T42
Test name
Test status
Simulation time 183257071257 ps
CPU time 78.35 seconds
Started Aug 01 04:23:13 PM PDT 24
Finished Aug 01 04:24:32 PM PDT 24
Peak memory 183020 kb
Host smart-af337537-0b9f-4fc1-9ba8-057d53d7ad4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788068518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.2788068518
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.3080643052
Short name T448
Test name
Test status
Simulation time 183300809328 ps
CPU time 77.01 seconds
Started Aug 01 04:20:46 PM PDT 24
Finished Aug 01 04:22:04 PM PDT 24
Peak memory 180396 kb
Host smart-52991d50-ef2f-4b1b-8803-e05ad6e13c76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080643052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.3080643052
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.2654573326
Short name T184
Test name
Test status
Simulation time 92853098264 ps
CPU time 1589.63 seconds
Started Aug 01 04:19:37 PM PDT 24
Finished Aug 01 04:46:07 PM PDT 24
Peak memory 183396 kb
Host smart-0d439e3d-13e1-44ab-9514-eafab761ea50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654573326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.2654573326
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.2715096286
Short name T333
Test name
Test status
Simulation time 1683025412420 ps
CPU time 449.73 seconds
Started Aug 01 04:22:33 PM PDT 24
Finished Aug 01 04:30:03 PM PDT 24
Peak memory 183008 kb
Host smart-f56e69da-4487-4aea-b03b-f8c1c07a54a8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715096286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.2715096286
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.3823923330
Short name T358
Test name
Test status
Simulation time 75704883584 ps
CPU time 105.87 seconds
Started Aug 01 04:23:33 PM PDT 24
Finished Aug 01 04:25:19 PM PDT 24
Peak memory 182996 kb
Host smart-77d85dc9-b2ff-4a39-bd73-d6bec55ef869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823923330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.3823923330
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.2108442539
Short name T431
Test name
Test status
Simulation time 223487595 ps
CPU time 0.85 seconds
Started Aug 01 04:22:32 PM PDT 24
Finished Aug 01 04:22:33 PM PDT 24
Peak memory 182684 kb
Host smart-86fe4706-1df8-4f75-a37a-7d755a15b326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108442539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.2108442539
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.3510678980
Short name T230
Test name
Test status
Simulation time 483595487846 ps
CPU time 202.79 seconds
Started Aug 01 04:22:24 PM PDT 24
Finished Aug 01 04:25:47 PM PDT 24
Peak memory 191108 kb
Host smart-1ec33580-428d-43cf-8f2c-8085c1604368
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510678980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.3510678980
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all_with_rand_reset.351282954
Short name T35
Test name
Test status
Simulation time 71188253330 ps
CPU time 288.2 seconds
Started Aug 01 04:22:59 PM PDT 24
Finished Aug 01 04:27:48 PM PDT 24
Peak memory 205916 kb
Host smart-bcfb5f51-b03c-42ac-bc3f-c0baee1e1219
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351282954 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all_with_rand_reset.351282954
Directory /workspace/34.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.1328730649
Short name T316
Test name
Test status
Simulation time 392889408125 ps
CPU time 449.62 seconds
Started Aug 01 04:23:08 PM PDT 24
Finished Aug 01 04:30:38 PM PDT 24
Peak memory 183236 kb
Host smart-32401b19-87cf-48fc-b65f-ba6a9d3d5bbf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328730649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.1328730649
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.3401079598
Short name T386
Test name
Test status
Simulation time 304037935856 ps
CPU time 120.64 seconds
Started Aug 01 04:21:43 PM PDT 24
Finished Aug 01 04:23:44 PM PDT 24
Peak memory 183264 kb
Host smart-1d0ac3b1-77f8-40a2-ae21-7f639ebdac1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401079598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.3401079598
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.931308342
Short name T216
Test name
Test status
Simulation time 2400895665929 ps
CPU time 1994.4 seconds
Started Aug 01 04:21:21 PM PDT 24
Finished Aug 01 04:54:35 PM PDT 24
Peak memory 191460 kb
Host smart-f9caa514-5dfa-4a40-bb1b-be10f701d4c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931308342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.931308342
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.2861509981
Short name T435
Test name
Test status
Simulation time 265332626 ps
CPU time 0.63 seconds
Started Aug 01 04:23:08 PM PDT 24
Finished Aug 01 04:23:09 PM PDT 24
Peak memory 182984 kb
Host smart-21042b01-9354-47d5-b6d6-dcf974bea807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861509981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.2861509981
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all_with_rand_reset.64101064
Short name T39
Test name
Test status
Simulation time 280527526436 ps
CPU time 700.88 seconds
Started Aug 01 04:23:02 PM PDT 24
Finished Aug 01 04:34:43 PM PDT 24
Peak memory 211316 kb
Host smart-a5576d9e-feac-4c58-bb21-09d2196bba29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64101064 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all_with_rand_reset.64101064
Directory /workspace/35.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.2714362111
Short name T117
Test name
Test status
Simulation time 3932813896832 ps
CPU time 2285.61 seconds
Started Aug 01 04:21:36 PM PDT 24
Finished Aug 01 04:59:42 PM PDT 24
Peak memory 183240 kb
Host smart-aa2766d2-c7a9-457e-b37b-a30229248264
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714362111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.2714362111
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.16517342
Short name T402
Test name
Test status
Simulation time 180520842059 ps
CPU time 263.63 seconds
Started Aug 01 04:22:38 PM PDT 24
Finished Aug 01 04:27:02 PM PDT 24
Peak memory 182796 kb
Host smart-3b509d55-7919-45b9-b82a-f0208aa8be1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16517342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.16517342
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.370768254
Short name T149
Test name
Test status
Simulation time 30158413711 ps
CPU time 40.52 seconds
Started Aug 01 04:19:55 PM PDT 24
Finished Aug 01 04:20:36 PM PDT 24
Peak memory 191416 kb
Host smart-e14fbe83-c05c-4cb0-890e-62d88d906fd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370768254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.370768254
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.3476757352
Short name T296
Test name
Test status
Simulation time 659407889655 ps
CPU time 196.06 seconds
Started Aug 01 04:19:50 PM PDT 24
Finished Aug 01 04:23:06 PM PDT 24
Peak memory 191480 kb
Host smart-afc5d3e6-6ccf-4cf2-adae-d71de9417073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476757352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.3476757352
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.3273261568
Short name T416
Test name
Test status
Simulation time 293608369841 ps
CPU time 240.78 seconds
Started Aug 01 04:21:16 PM PDT 24
Finished Aug 01 04:25:17 PM PDT 24
Peak memory 194256 kb
Host smart-2e81319e-f0a6-4334-a646-02b1c027d973
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273261568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.3273261568
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.3554234370
Short name T449
Test name
Test status
Simulation time 148440039993 ps
CPU time 237.55 seconds
Started Aug 01 04:23:27 PM PDT 24
Finished Aug 01 04:27:25 PM PDT 24
Peak memory 182964 kb
Host smart-b2166019-b31d-4727-850f-bb00ab24cd7a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554234370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.3554234370
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.2162482915
Short name T376
Test name
Test status
Simulation time 182286270406 ps
CPU time 277.52 seconds
Started Aug 01 04:22:57 PM PDT 24
Finished Aug 01 04:27:35 PM PDT 24
Peak memory 182924 kb
Host smart-881f98ae-fd1a-4517-8c6b-84252e402009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162482915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.2162482915
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.4103962472
Short name T56
Test name
Test status
Simulation time 248468693313 ps
CPU time 197.8 seconds
Started Aug 01 04:21:46 PM PDT 24
Finished Aug 01 04:25:04 PM PDT 24
Peak memory 195236 kb
Host smart-45de2c37-399d-4764-8d32-18a2b7274edf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103962472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.4103962472
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.3458676855
Short name T232
Test name
Test status
Simulation time 270461623619 ps
CPU time 387.9 seconds
Started Aug 01 04:23:19 PM PDT 24
Finished Aug 01 04:29:47 PM PDT 24
Peak memory 180404 kb
Host smart-6b5e2655-89a1-46f7-97b9-c6b1596e456e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458676855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.3458676855
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.2988442608
Short name T359
Test name
Test status
Simulation time 76016293993 ps
CPU time 97 seconds
Started Aug 01 04:23:19 PM PDT 24
Finished Aug 01 04:24:56 PM PDT 24
Peak memory 180116 kb
Host smart-63889d3c-a2df-4b08-a6f5-c747767fb601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988442608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.2988442608
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.1772927990
Short name T329
Test name
Test status
Simulation time 188294729341 ps
CPU time 96.02 seconds
Started Aug 01 04:23:04 PM PDT 24
Finished Aug 01 04:24:40 PM PDT 24
Peak memory 183280 kb
Host smart-7d25948d-da30-416f-97ab-dd7a19998512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772927990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.1772927990
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.3859289823
Short name T277
Test name
Test status
Simulation time 1863779132 ps
CPU time 1.41 seconds
Started Aug 01 04:21:17 PM PDT 24
Finished Aug 01 04:21:18 PM PDT 24
Peak memory 183004 kb
Host smart-23edafa9-0218-4fc5-9228-006637fc0be6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859289823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.3859289823
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.3956952511
Short name T373
Test name
Test status
Simulation time 159363181329 ps
CPU time 70 seconds
Started Aug 01 04:22:29 PM PDT 24
Finished Aug 01 04:23:39 PM PDT 24
Peak memory 182868 kb
Host smart-2a0ab964-7c2f-405f-a4fb-dd09f45c4b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956952511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.3956952511
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.2256774067
Short name T130
Test name
Test status
Simulation time 213985122720 ps
CPU time 194.1 seconds
Started Aug 01 04:22:29 PM PDT 24
Finished Aug 01 04:25:43 PM PDT 24
Peak memory 191068 kb
Host smart-9f77c5ea-af00-4e59-8e92-27bcaa6daf3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256774067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.2256774067
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.626718779
Short name T326
Test name
Test status
Simulation time 72608699720 ps
CPU time 55.87 seconds
Started Aug 01 04:23:19 PM PDT 24
Finished Aug 01 04:24:15 PM PDT 24
Peak memory 180444 kb
Host smart-eb226437-81e1-41da-ba6f-f685dd70b3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626718779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.626718779
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.602802413
Short name T142
Test name
Test status
Simulation time 1591235581176 ps
CPU time 412.13 seconds
Started Aug 01 04:20:02 PM PDT 24
Finished Aug 01 04:26:54 PM PDT 24
Peak memory 191592 kb
Host smart-a2f0075d-ccd0-413d-9899-bd3227330830
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602802413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all.
602802413
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.2870591760
Short name T233
Test name
Test status
Simulation time 8692570528 ps
CPU time 13.08 seconds
Started Aug 01 04:24:29 PM PDT 24
Finished Aug 01 04:24:43 PM PDT 24
Peak memory 183252 kb
Host smart-8a02df21-b806-4ac3-85d0-d7ad4337cb65
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870591760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.2870591760
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.4128028757
Short name T422
Test name
Test status
Simulation time 202449083518 ps
CPU time 284.27 seconds
Started Aug 01 04:22:40 PM PDT 24
Finished Aug 01 04:27:24 PM PDT 24
Peak memory 181732 kb
Host smart-4bd99747-b507-4683-82d6-4e12a0abf2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128028757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.4128028757
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.2916576502
Short name T288
Test name
Test status
Simulation time 80091820267 ps
CPU time 432 seconds
Started Aug 01 04:22:42 PM PDT 24
Finished Aug 01 04:29:55 PM PDT 24
Peak memory 194176 kb
Host smart-408c232e-fcb0-453d-b126-7d7b68f44e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916576502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.2916576502
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.4105534760
Short name T18
Test name
Test status
Simulation time 148114168 ps
CPU time 0.91 seconds
Started Aug 01 04:24:15 PM PDT 24
Finished Aug 01 04:24:16 PM PDT 24
Peak memory 213456 kb
Host smart-f01a0bee-11be-4a85-a4d6-23c6ba17ff40
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105534760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.4105534760
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.369796049
Short name T365
Test name
Test status
Simulation time 59385433 ps
CPU time 0.54 seconds
Started Aug 01 04:23:24 PM PDT 24
Finished Aug 01 04:23:25 PM PDT 24
Peak memory 182716 kb
Host smart-e6919d25-6795-4e1a-a206-b7f630963f7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369796049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.369796049
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.1179796589
Short name T45
Test name
Test status
Simulation time 122349258182 ps
CPU time 176.65 seconds
Started Aug 01 04:23:04 PM PDT 24
Finished Aug 01 04:26:01 PM PDT 24
Peak memory 183144 kb
Host smart-e35e2bc5-7467-4f6b-9a7d-72b950f03697
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179796589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.1179796589
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.3893924199
Short name T357
Test name
Test status
Simulation time 557291571360 ps
CPU time 223.07 seconds
Started Aug 01 04:22:28 PM PDT 24
Finished Aug 01 04:26:12 PM PDT 24
Peak memory 182036 kb
Host smart-1cb261a3-5151-4ac2-9ea7-01142e8f9c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893924199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.3893924199
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.1010979010
Short name T225
Test name
Test status
Simulation time 110201341436 ps
CPU time 77.53 seconds
Started Aug 01 04:20:21 PM PDT 24
Finished Aug 01 04:21:39 PM PDT 24
Peak memory 191420 kb
Host smart-fe7c6c13-093c-4301-8ae9-494dd1f167bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010979010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.1010979010
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.770277243
Short name T298
Test name
Test status
Simulation time 1774085144182 ps
CPU time 794.19 seconds
Started Aug 01 04:22:42 PM PDT 24
Finished Aug 01 04:35:57 PM PDT 24
Peak memory 191288 kb
Host smart-a37b5dfe-0271-49d5-8458-dd0a4bea99b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770277243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all.
770277243
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.4275502536
Short name T179
Test name
Test status
Simulation time 201551496953 ps
CPU time 79.18 seconds
Started Aug 01 04:22:32 PM PDT 24
Finished Aug 01 04:23:51 PM PDT 24
Peak memory 183204 kb
Host smart-416833f8-c971-44d0-b4bd-154a8db780ec
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275502536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.4275502536
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.587107745
Short name T403
Test name
Test status
Simulation time 30171010940 ps
CPU time 41.84 seconds
Started Aug 01 04:22:42 PM PDT 24
Finished Aug 01 04:23:24 PM PDT 24
Peak memory 183108 kb
Host smart-0b693ac6-9e95-417c-b051-f735a5c26f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587107745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.587107745
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.1188094896
Short name T151
Test name
Test status
Simulation time 349147309758 ps
CPU time 188.71 seconds
Started Aug 01 04:22:42 PM PDT 24
Finished Aug 01 04:25:51 PM PDT 24
Peak memory 191308 kb
Host smart-c107eb55-7f07-4f98-88d3-ab2b1c1982f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188094896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.1188094896
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.426223306
Short name T323
Test name
Test status
Simulation time 84321202860 ps
CPU time 63.65 seconds
Started Aug 01 04:22:23 PM PDT 24
Finished Aug 01 04:23:27 PM PDT 24
Peak memory 190436 kb
Host smart-d9bfd477-4035-4769-8a68-2227875eff6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426223306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.426223306
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.2163065634
Short name T121
Test name
Test status
Simulation time 2011290583448 ps
CPU time 340.8 seconds
Started Aug 01 04:22:31 PM PDT 24
Finished Aug 01 04:28:12 PM PDT 24
Peak memory 190620 kb
Host smart-3816876d-64b2-4823-9912-16b536304387
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163065634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.2163065634
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.3408577391
Short name T423
Test name
Test status
Simulation time 66523526559 ps
CPU time 117.88 seconds
Started Aug 01 04:20:24 PM PDT 24
Finished Aug 01 04:22:22 PM PDT 24
Peak memory 183312 kb
Host smart-c7888fe2-7ff3-46c2-8c82-5845bcd5789c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408577391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.3408577391
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.1724001278
Short name T418
Test name
Test status
Simulation time 298372889344 ps
CPU time 101.26 seconds
Started Aug 01 04:22:32 PM PDT 24
Finished Aug 01 04:24:14 PM PDT 24
Peak memory 183184 kb
Host smart-beeed814-e26b-4f56-aa0f-c14ff85fdfa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724001278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.1724001278
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.651436178
Short name T92
Test name
Test status
Simulation time 134150315871 ps
CPU time 189.12 seconds
Started Aug 01 04:22:40 PM PDT 24
Finished Aug 01 04:25:50 PM PDT 24
Peak memory 191216 kb
Host smart-4195d460-f62f-4256-a883-c55c10398bc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651436178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.651436178
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.2019097438
Short name T407
Test name
Test status
Simulation time 60709809 ps
CPU time 0.55 seconds
Started Aug 01 04:20:30 PM PDT 24
Finished Aug 01 04:20:31 PM PDT 24
Peak memory 183128 kb
Host smart-385a8bf7-8b70-4098-bd33-a3707565b0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019097438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.2019097438
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.2537660352
Short name T430
Test name
Test status
Simulation time 25455012 ps
CPU time 0.6 seconds
Started Aug 01 04:20:37 PM PDT 24
Finished Aug 01 04:20:38 PM PDT 24
Peak memory 182988 kb
Host smart-3e3eb418-3dea-4962-91ad-c065c96fd28e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537660352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.2537660352
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.3178224778
Short name T303
Test name
Test status
Simulation time 875318776895 ps
CPU time 675.21 seconds
Started Aug 01 04:22:53 PM PDT 24
Finished Aug 01 04:34:08 PM PDT 24
Peak memory 182968 kb
Host smart-5c0a2f1b-a163-4182-a143-693a2ac56371
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178224778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.3178224778
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.613607190
Short name T389
Test name
Test status
Simulation time 460629584560 ps
CPU time 205.73 seconds
Started Aug 01 04:20:45 PM PDT 24
Finished Aug 01 04:24:10 PM PDT 24
Peak memory 183320 kb
Host smart-d59a23ca-39ab-4165-bdf5-41d93ced5b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613607190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.613607190
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.3520766371
Short name T275
Test name
Test status
Simulation time 163084962762 ps
CPU time 467.93 seconds
Started Aug 01 04:22:43 PM PDT 24
Finished Aug 01 04:30:31 PM PDT 24
Peak memory 193420 kb
Host smart-da9bcb84-8632-497e-b311-13855682c99b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520766371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.3520766371
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.470128198
Short name T265
Test name
Test status
Simulation time 70885604667 ps
CPU time 34.75 seconds
Started Aug 01 04:22:43 PM PDT 24
Finished Aug 01 04:23:18 PM PDT 24
Peak memory 191048 kb
Host smart-1896b419-0676-4c70-abb8-ff4b40f1423a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470128198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.470128198
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.2725457590
Short name T37
Test name
Test status
Simulation time 98005759802 ps
CPU time 707.2 seconds
Started Aug 01 04:23:10 PM PDT 24
Finished Aug 01 04:34:58 PM PDT 24
Peak memory 198996 kb
Host smart-551108b0-4d6d-4f80-9b0d-e567cdea174a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725457590 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.2725457590
Directory /workspace/43.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.1679055035
Short name T6
Test name
Test status
Simulation time 75111425104 ps
CPU time 95.51 seconds
Started Aug 01 04:22:43 PM PDT 24
Finished Aug 01 04:24:19 PM PDT 24
Peak memory 182952 kb
Host smart-298cc0bc-4610-4c84-a4bf-0c83a86b9db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679055035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.1679055035
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.1747287585
Short name T421
Test name
Test status
Simulation time 77382308689 ps
CPU time 31.36 seconds
Started Aug 01 04:23:10 PM PDT 24
Finished Aug 01 04:23:42 PM PDT 24
Peak memory 182176 kb
Host smart-885869dc-04db-4d15-82ab-84b8e991ce50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747287585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.1747287585
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.321277860
Short name T243
Test name
Test status
Simulation time 146594464980 ps
CPU time 140.82 seconds
Started Aug 01 04:21:47 PM PDT 24
Finished Aug 01 04:24:08 PM PDT 24
Peak memory 194256 kb
Host smart-25b1f75f-7bc2-4ef6-a692-175fc06076d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321277860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.321277860
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.1211125419
Short name T300
Test name
Test status
Simulation time 201996583368 ps
CPU time 112.19 seconds
Started Aug 01 04:20:44 PM PDT 24
Finished Aug 01 04:22:37 PM PDT 24
Peak memory 183220 kb
Host smart-82a4621f-f5a0-454f-8960-68c6a10b107d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211125419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.1211125419
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.2923709792
Short name T410
Test name
Test status
Simulation time 433973704638 ps
CPU time 188.32 seconds
Started Aug 01 04:23:43 PM PDT 24
Finished Aug 01 04:26:52 PM PDT 24
Peak memory 182116 kb
Host smart-28eff411-283a-4b0c-ac54-33304f2b3671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923709792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.2923709792
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.3452809643
Short name T246
Test name
Test status
Simulation time 22847689512 ps
CPU time 375.5 seconds
Started Aug 01 04:20:45 PM PDT 24
Finished Aug 01 04:27:01 PM PDT 24
Peak memory 191480 kb
Host smart-6396eb4f-d517-4c0a-93be-631f3a965766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452809643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.3452809643
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.3925136125
Short name T437
Test name
Test status
Simulation time 104492159 ps
CPU time 0.57 seconds
Started Aug 01 04:21:14 PM PDT 24
Finished Aug 01 04:21:14 PM PDT 24
Peak memory 183400 kb
Host smart-5a0f0f4a-cb53-4635-b3fa-8a6a7da5aca4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925136125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.3925136125
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.1537093875
Short name T138
Test name
Test status
Simulation time 83036651371 ps
CPU time 1174.03 seconds
Started Aug 01 04:20:49 PM PDT 24
Finished Aug 01 04:40:23 PM PDT 24
Peak memory 213592 kb
Host smart-552884d4-9d01-44b4-ab62-022146f4421d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537093875 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all_with_rand_reset.1537093875
Directory /workspace/45.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.4288876318
Short name T399
Test name
Test status
Simulation time 10669084448 ps
CPU time 8.59 seconds
Started Aug 01 04:20:55 PM PDT 24
Finished Aug 01 04:21:04 PM PDT 24
Peak memory 183384 kb
Host smart-50472ac8-385e-4fc5-8535-b75e34771760
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288876318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.4288876318
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.724769480
Short name T364
Test name
Test status
Simulation time 569997077408 ps
CPU time 219.94 seconds
Started Aug 01 04:23:36 PM PDT 24
Finished Aug 01 04:27:16 PM PDT 24
Peak memory 182912 kb
Host smart-0cb0429e-0b08-44f7-9c24-55176236be26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724769480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.724769480
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.2458385385
Short name T342
Test name
Test status
Simulation time 120153755696 ps
CPU time 60.68 seconds
Started Aug 01 04:20:56 PM PDT 24
Finished Aug 01 04:21:57 PM PDT 24
Peak memory 183396 kb
Host smart-62032776-c6ee-4dac-b6ce-03c23e0a23cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458385385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.2458385385
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.2145632407
Short name T419
Test name
Test status
Simulation time 31610750441 ps
CPU time 14.71 seconds
Started Aug 01 04:21:02 PM PDT 24
Finished Aug 01 04:21:16 PM PDT 24
Peak memory 191468 kb
Host smart-64d2aa4d-eb4c-4c2e-b02c-82a97edc610d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145632407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.2145632407
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.3282427082
Short name T107
Test name
Test status
Simulation time 212558038305 ps
CPU time 402.78 seconds
Started Aug 01 04:23:24 PM PDT 24
Finished Aug 01 04:30:07 PM PDT 24
Peak memory 195928 kb
Host smart-c2d2934e-9e47-45b5-b931-918bf5816e1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282427082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.3282427082
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.523415179
Short name T337
Test name
Test status
Simulation time 666891789978 ps
CPU time 315.42 seconds
Started Aug 01 04:22:52 PM PDT 24
Finished Aug 01 04:28:07 PM PDT 24
Peak memory 182944 kb
Host smart-2baca3c0-509f-4e47-89b8-a7a3bef59a23
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523415179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.rv_timer_cfg_update_on_fly.523415179
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.898311566
Short name T394
Test name
Test status
Simulation time 75695982562 ps
CPU time 28.09 seconds
Started Aug 01 04:22:54 PM PDT 24
Finished Aug 01 04:23:22 PM PDT 24
Peak memory 182968 kb
Host smart-82c057d9-9610-4fc1-afdc-2cb5e374be00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898311566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.898311566
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.3792489658
Short name T49
Test name
Test status
Simulation time 111384517443 ps
CPU time 166.22 seconds
Started Aug 01 04:23:24 PM PDT 24
Finished Aug 01 04:26:10 PM PDT 24
Peak memory 194708 kb
Host smart-bb507f24-4c97-4747-8c3a-ae953973ce3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792489658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.3792489658
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.2796137928
Short name T258
Test name
Test status
Simulation time 3028117977 ps
CPU time 1.6 seconds
Started Aug 01 04:21:05 PM PDT 24
Finished Aug 01 04:21:06 PM PDT 24
Peak memory 183084 kb
Host smart-f623bcd5-e885-44d8-ae07-091e5fb05353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796137928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.2796137928
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.838962285
Short name T158
Test name
Test status
Simulation time 225065645793 ps
CPU time 190.43 seconds
Started Aug 01 04:22:29 PM PDT 24
Finished Aug 01 04:25:40 PM PDT 24
Peak memory 182196 kb
Host smart-0ae54fd0-5d6f-4149-a680-87ae02e8b69f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838962285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.rv_timer_cfg_update_on_fly.838962285
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.1278029283
Short name T367
Test name
Test status
Simulation time 254718454322 ps
CPU time 214.44 seconds
Started Aug 01 04:22:51 PM PDT 24
Finished Aug 01 04:26:26 PM PDT 24
Peak memory 182952 kb
Host smart-a135360e-09a3-4d45-9a33-a3e20279d9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278029283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.1278029283
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.826824992
Short name T139
Test name
Test status
Simulation time 38958656007 ps
CPU time 38.11 seconds
Started Aug 01 04:22:52 PM PDT 24
Finished Aug 01 04:23:30 PM PDT 24
Peak memory 182948 kb
Host smart-d011894f-3e03-45c4-a9ac-0259b96ef200
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826824992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.826824992
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.1280894396
Short name T280
Test name
Test status
Simulation time 69133819248 ps
CPU time 27.42 seconds
Started Aug 01 04:22:26 PM PDT 24
Finished Aug 01 04:22:53 PM PDT 24
Peak memory 182904 kb
Host smart-82cf32ca-b3a2-46ff-8574-e98743bcdb84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280894396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.1280894396
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.3498090739
Short name T387
Test name
Test status
Simulation time 482651748435 ps
CPU time 161.27 seconds
Started Aug 01 04:22:37 PM PDT 24
Finished Aug 01 04:25:19 PM PDT 24
Peak memory 182876 kb
Host smart-ff9309ae-8aee-4d81-8518-ef4ea0e3817c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498090739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.3498090739
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.116275101
Short name T185
Test name
Test status
Simulation time 1996758124312 ps
CPU time 1043.16 seconds
Started Aug 01 04:22:41 PM PDT 24
Finished Aug 01 04:40:04 PM PDT 24
Peak memory 191196 kb
Host smart-f7641d66-bfcf-4b49-b0ad-a21ef8405d54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116275101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.116275101
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.1448821581
Short name T41
Test name
Test status
Simulation time 5691410788 ps
CPU time 12.28 seconds
Started Aug 01 04:22:50 PM PDT 24
Finished Aug 01 04:23:02 PM PDT 24
Peak memory 194808 kb
Host smart-a054df7f-ae02-43fe-a2ec-2a3c1b1fae81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448821581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.1448821581
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.1697525866
Short name T239
Test name
Test status
Simulation time 3168761500450 ps
CPU time 1225.83 seconds
Started Aug 01 04:22:47 PM PDT 24
Finished Aug 01 04:43:14 PM PDT 24
Peak memory 181532 kb
Host smart-94636135-0645-4708-923e-8d847df11022
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697525866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.1697525866
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.1155196672
Short name T360
Test name
Test status
Simulation time 400252434718 ps
CPU time 139.88 seconds
Started Aug 01 04:22:34 PM PDT 24
Finished Aug 01 04:24:55 PM PDT 24
Peak memory 183192 kb
Host smart-b8a0de55-9c84-4bc0-9a60-b7eb9add3ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155196672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.1155196672
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.1955589689
Short name T442
Test name
Test status
Simulation time 46856943294 ps
CPU time 78.4 seconds
Started Aug 01 04:18:42 PM PDT 24
Finished Aug 01 04:20:00 PM PDT 24
Peak memory 183208 kb
Host smart-5f4a8fa9-f730-4d0e-9c5e-e786dc92adba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955589689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.1955589689
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/51.rv_timer_random.899930554
Short name T178
Test name
Test status
Simulation time 138015740500 ps
CPU time 110.41 seconds
Started Aug 01 04:22:42 PM PDT 24
Finished Aug 01 04:24:33 PM PDT 24
Peak memory 190948 kb
Host smart-d00ba06b-ff43-44ad-93e4-0fb1ff62c127
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899930554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.899930554
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.3130472151
Short name T128
Test name
Test status
Simulation time 1384992646964 ps
CPU time 433.03 seconds
Started Aug 01 04:21:32 PM PDT 24
Finished Aug 01 04:28:45 PM PDT 24
Peak memory 191608 kb
Host smart-8062ed36-51db-41e2-ab63-17650220c00c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130472151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.3130472151
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.912388373
Short name T252
Test name
Test status
Simulation time 310436971830 ps
CPU time 218.21 seconds
Started Aug 01 04:21:37 PM PDT 24
Finished Aug 01 04:25:15 PM PDT 24
Peak memory 191640 kb
Host smart-478f4839-18c8-4f31-95a8-b4edc8c30efc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912388373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.912388373
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.1127981433
Short name T204
Test name
Test status
Simulation time 40295497256 ps
CPU time 66.99 seconds
Started Aug 01 04:21:32 PM PDT 24
Finished Aug 01 04:22:39 PM PDT 24
Peak memory 191584 kb
Host smart-d8dcdc0e-b9af-454f-aefa-89c4962713b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127981433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.1127981433
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.3838115241
Short name T141
Test name
Test status
Simulation time 66457783399 ps
CPU time 371.33 seconds
Started Aug 01 04:21:30 PM PDT 24
Finished Aug 01 04:27:42 PM PDT 24
Peak memory 191608 kb
Host smart-cdfe4fd4-e4b9-4155-8c9c-c81c93120d12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838115241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.3838115241
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.3414142617
Short name T180
Test name
Test status
Simulation time 380538342645 ps
CPU time 671.06 seconds
Started Aug 01 04:21:53 PM PDT 24
Finished Aug 01 04:33:04 PM PDT 24
Peak memory 191596 kb
Host smart-9498706d-2fe7-4f32-a588-ea548ad46410
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414142617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.3414142617
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.1940436694
Short name T89
Test name
Test status
Simulation time 244491714562 ps
CPU time 191.79 seconds
Started Aug 01 04:23:35 PM PDT 24
Finished Aug 01 04:26:47 PM PDT 24
Peak memory 191112 kb
Host smart-a0678609-ef46-4e71-9e83-41bb007372a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940436694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.1940436694
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.725149297
Short name T348
Test name
Test status
Simulation time 108068003706 ps
CPU time 566.29 seconds
Started Aug 01 04:21:44 PM PDT 24
Finished Aug 01 04:31:11 PM PDT 24
Peak memory 191580 kb
Host smart-f3e98d84-a759-4a03-80f8-2f7ee6f11038
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725149297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.725149297
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.4257001397
Short name T432
Test name
Test status
Simulation time 315884023367 ps
CPU time 263.76 seconds
Started Aug 01 04:21:50 PM PDT 24
Finished Aug 01 04:26:13 PM PDT 24
Peak memory 190780 kb
Host smart-99a51ff0-70e3-4d91-99f8-3bbf50b5b349
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257001397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.4257001397
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.1963516584
Short name T155
Test name
Test status
Simulation time 982637513029 ps
CPU time 827.57 seconds
Started Aug 01 04:18:30 PM PDT 24
Finished Aug 01 04:32:17 PM PDT 24
Peak memory 183436 kb
Host smart-3566e581-37e1-4521-8c53-1b343333772f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963516584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.1963516584
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.1720720035
Short name T445
Test name
Test status
Simulation time 111651228891 ps
CPU time 125.82 seconds
Started Aug 01 04:22:37 PM PDT 24
Finished Aug 01 04:24:43 PM PDT 24
Peak memory 183252 kb
Host smart-f785c69b-c022-425a-8a7e-3a9fbae3cea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720720035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.1720720035
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.2632556260
Short name T393
Test name
Test status
Simulation time 369040570849 ps
CPU time 125.95 seconds
Started Aug 01 04:22:21 PM PDT 24
Finished Aug 01 04:24:28 PM PDT 24
Peak memory 182116 kb
Host smart-edc4a14d-d00b-489f-80b0-d2ee91c73ccf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632556260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.2632556260
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.3542721720
Short name T382
Test name
Test status
Simulation time 51400728 ps
CPU time 0.57 seconds
Started Aug 01 04:22:30 PM PDT 24
Finished Aug 01 04:22:31 PM PDT 24
Peak memory 182668 kb
Host smart-497d0e2f-d59e-4f9a-b511-3a38b44a4f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542721720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.3542721720
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.1392559801
Short name T443
Test name
Test status
Simulation time 214640523284 ps
CPU time 73.81 seconds
Started Aug 01 04:22:48 PM PDT 24
Finished Aug 01 04:24:02 PM PDT 24
Peak memory 182980 kb
Host smart-f52e0a64-866d-4da9-95b9-57830cc5c56a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392559801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
1392559801
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all_with_rand_reset.2918340276
Short name T420
Test name
Test status
Simulation time 25163411263 ps
CPU time 247.3 seconds
Started Aug 01 04:22:21 PM PDT 24
Finished Aug 01 04:26:29 PM PDT 24
Peak memory 196756 kb
Host smart-b3190022-e98d-493f-a2a7-866939a241e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918340276 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all_with_rand_reset.2918340276
Directory /workspace/6.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.2885002988
Short name T91
Test name
Test status
Simulation time 314422855329 ps
CPU time 421.49 seconds
Started Aug 01 04:21:44 PM PDT 24
Finished Aug 01 04:28:46 PM PDT 24
Peak memory 191636 kb
Host smart-16f10390-182d-49db-982c-322610fde7e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885002988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.2885002988
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.3216345471
Short name T424
Test name
Test status
Simulation time 414243203223 ps
CPU time 480.07 seconds
Started Aug 01 04:21:43 PM PDT 24
Finished Aug 01 04:29:43 PM PDT 24
Peak memory 191452 kb
Host smart-a9dcf6b9-b872-4762-b391-ecc063290f4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216345471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.3216345471
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.4170477700
Short name T339
Test name
Test status
Simulation time 64767311779 ps
CPU time 103.73 seconds
Started Aug 01 04:21:44 PM PDT 24
Finished Aug 01 04:23:28 PM PDT 24
Peak memory 191600 kb
Host smart-4d752170-fb76-4c5e-8e03-286a52ea9f6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170477700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.4170477700
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.825908646
Short name T309
Test name
Test status
Simulation time 328880585502 ps
CPU time 192.45 seconds
Started Aug 01 04:21:58 PM PDT 24
Finished Aug 01 04:25:11 PM PDT 24
Peak memory 194632 kb
Host smart-8ac969b8-cd49-43b1-b089-c18011219dba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825908646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.825908646
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.1413329741
Short name T248
Test name
Test status
Simulation time 122154714743 ps
CPU time 22.66 seconds
Started Aug 01 04:21:58 PM PDT 24
Finished Aug 01 04:22:21 PM PDT 24
Peak memory 183216 kb
Host smart-01392b97-4c09-44c6-8569-05730f2e1d3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413329741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.1413329741
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.264585861
Short name T267
Test name
Test status
Simulation time 172093645980 ps
CPU time 98.89 seconds
Started Aug 01 04:23:24 PM PDT 24
Finished Aug 01 04:25:03 PM PDT 24
Peak memory 191400 kb
Host smart-297fe66d-9efd-4f92-9463-5e4e713dbcea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264585861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.264585861
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.413122366
Short name T292
Test name
Test status
Simulation time 60927891842 ps
CPU time 62.71 seconds
Started Aug 01 04:23:20 PM PDT 24
Finished Aug 01 04:24:22 PM PDT 24
Peak memory 191140 kb
Host smart-87f6fd76-6775-49d3-979b-e2373e2f2664
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413122366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.413122366
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.2718071324
Short name T447
Test name
Test status
Simulation time 117216412631 ps
CPU time 175.13 seconds
Started Aug 01 04:23:35 PM PDT 24
Finished Aug 01 04:26:30 PM PDT 24
Peak memory 191112 kb
Host smart-2d8e77e1-e654-41e0-9fe9-2d2b122b8035
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718071324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.2718071324
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random.2360784212
Short name T307
Test name
Test status
Simulation time 55354851422 ps
CPU time 102.14 seconds
Started Aug 01 04:22:25 PM PDT 24
Finished Aug 01 04:24:08 PM PDT 24
Peak memory 190092 kb
Host smart-44ecf450-9b48-44da-92bd-2b74a25e2b46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360784212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.2360784212
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.2775374937
Short name T374
Test name
Test status
Simulation time 218958751 ps
CPU time 0.84 seconds
Started Aug 01 04:22:52 PM PDT 24
Finished Aug 01 04:22:54 PM PDT 24
Peak memory 182180 kb
Host smart-55e26c2a-d07a-4afb-b713-adcb12bdd304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775374937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.2775374937
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/71.rv_timer_random.393537098
Short name T289
Test name
Test status
Simulation time 334854397753 ps
CPU time 986.48 seconds
Started Aug 01 04:21:57 PM PDT 24
Finished Aug 01 04:38:24 PM PDT 24
Peak memory 191640 kb
Host smart-2f98bfaa-f465-4517-9b0c-e51e83509e43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393537098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.393537098
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.1312811279
Short name T350
Test name
Test status
Simulation time 132702535880 ps
CPU time 242.36 seconds
Started Aug 01 04:21:55 PM PDT 24
Finished Aug 01 04:25:58 PM PDT 24
Peak memory 191840 kb
Host smart-b5342d19-1c62-4b56-adb0-6f54453db4f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312811279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.1312811279
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.3789102642
Short name T156
Test name
Test status
Simulation time 241071799578 ps
CPU time 152.78 seconds
Started Aug 01 04:23:23 PM PDT 24
Finished Aug 01 04:25:56 PM PDT 24
Peak memory 191392 kb
Host smart-9d040e56-e9ce-4afd-b70b-69a5db2465ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789102642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.3789102642
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.2877093175
Short name T304
Test name
Test status
Simulation time 6602355392 ps
CPU time 10.26 seconds
Started Aug 01 04:23:10 PM PDT 24
Finished Aug 01 04:23:21 PM PDT 24
Peak memory 190444 kb
Host smart-d660cdc8-f938-436f-971b-c92accd748ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877093175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.2877093175
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.143259115
Short name T286
Test name
Test status
Simulation time 117262155582 ps
CPU time 94.02 seconds
Started Aug 01 04:21:57 PM PDT 24
Finished Aug 01 04:23:31 PM PDT 24
Peak memory 191648 kb
Host smart-bcf6fc5c-4b71-4bb1-ac07-db1cf2ca9eee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143259115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.143259115
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.3630390013
Short name T1
Test name
Test status
Simulation time 61625110448 ps
CPU time 45.69 seconds
Started Aug 01 04:21:56 PM PDT 24
Finished Aug 01 04:22:42 PM PDT 24
Peak memory 183648 kb
Host smart-7d53e5d8-ac3c-4425-b40c-e6dbc6ae50f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630390013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.3630390013
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.3213984584
Short name T318
Test name
Test status
Simulation time 241948687613 ps
CPU time 128.08 seconds
Started Aug 01 04:22:27 PM PDT 24
Finished Aug 01 04:24:35 PM PDT 24
Peak memory 191464 kb
Host smart-db6c6146-6f6f-4395-b3f2-c2f383a7a097
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213984584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.3213984584
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.3587303469
Short name T319
Test name
Test status
Simulation time 317994108801 ps
CPU time 1576.62 seconds
Started Aug 01 04:22:15 PM PDT 24
Finished Aug 01 04:48:31 PM PDT 24
Peak memory 191588 kb
Host smart-1fdcd1d6-6c47-438d-bad1-1e9523e6cc84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587303469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.3587303469
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.1480112570
Short name T210
Test name
Test status
Simulation time 120125959393 ps
CPU time 195.48 seconds
Started Aug 01 04:23:33 PM PDT 24
Finished Aug 01 04:26:48 PM PDT 24
Peak memory 182972 kb
Host smart-1cbe3d8b-8b50-457a-b9dd-7cd03c694e06
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480112570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.1480112570
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.39501294
Short name T400
Test name
Test status
Simulation time 60202606413 ps
CPU time 97.45 seconds
Started Aug 01 04:18:20 PM PDT 24
Finished Aug 01 04:19:57 PM PDT 24
Peak memory 182936 kb
Host smart-2b1879d3-ca45-4e94-8e40-a88942ce4db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39501294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.39501294
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.3460414762
Short name T201
Test name
Test status
Simulation time 5148053705 ps
CPU time 8.33 seconds
Started Aug 01 04:23:24 PM PDT 24
Finished Aug 01 04:23:34 PM PDT 24
Peak memory 181832 kb
Host smart-8cf8f901-f150-419a-a87f-ca416f1f94d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460414762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.3460414762
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.1956804194
Short name T126
Test name
Test status
Simulation time 11606357662 ps
CPU time 10.92 seconds
Started Aug 01 04:20:05 PM PDT 24
Finished Aug 01 04:20:16 PM PDT 24
Peak memory 191596 kb
Host smart-efc77a0d-13cf-4dc0-b1a6-6b69c11354f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956804194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.1956804194
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.146962635
Short name T48
Test name
Test status
Simulation time 1141935858295 ps
CPU time 1258.08 seconds
Started Aug 01 04:22:57 PM PDT 24
Finished Aug 01 04:43:56 PM PDT 24
Peak memory 191204 kb
Host smart-2852ffbf-65e5-46e8-a265-698ee3112252
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146962635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.146962635
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/81.rv_timer_random.2583856601
Short name T301
Test name
Test status
Simulation time 73913795215 ps
CPU time 640.4 seconds
Started Aug 01 04:22:29 PM PDT 24
Finished Aug 01 04:33:10 PM PDT 24
Peak memory 183264 kb
Host smart-e1106d6b-032b-437e-9586-3777065556a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583856601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.2583856601
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.2070569218
Short name T330
Test name
Test status
Simulation time 33860156641 ps
CPU time 27.05 seconds
Started Aug 01 04:22:10 PM PDT 24
Finished Aug 01 04:22:37 PM PDT 24
Peak memory 191580 kb
Host smart-88936d9d-fa54-4165-a97f-3e8215e03bd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070569218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.2070569218
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.1219932628
Short name T249
Test name
Test status
Simulation time 375613636983 ps
CPU time 188.68 seconds
Started Aug 01 04:22:07 PM PDT 24
Finished Aug 01 04:25:16 PM PDT 24
Peak memory 193840 kb
Host smart-22f34128-722e-4f1d-953c-e4f53dedd187
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219932628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.1219932628
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.2130298071
Short name T43
Test name
Test status
Simulation time 65722110837 ps
CPU time 765.03 seconds
Started Aug 01 04:23:27 PM PDT 24
Finished Aug 01 04:36:12 PM PDT 24
Peak memory 189360 kb
Host smart-4099d134-5099-4c9e-a2de-d4eecb525eb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130298071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.2130298071
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.2348946659
Short name T168
Test name
Test status
Simulation time 161500315814 ps
CPU time 614.63 seconds
Started Aug 01 04:23:27 PM PDT 24
Finished Aug 01 04:33:42 PM PDT 24
Peak memory 189652 kb
Host smart-2d82fd0a-15c4-438a-af6c-5dd1f559c079
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348946659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.2348946659
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.686929176
Short name T353
Test name
Test status
Simulation time 124013028532 ps
CPU time 1036.99 seconds
Started Aug 01 04:23:27 PM PDT 24
Finished Aug 01 04:40:44 PM PDT 24
Peak memory 181136 kb
Host smart-c809424a-d700-4da2-8ef0-1fef04dc0cb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686929176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.686929176
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.104493983
Short name T253
Test name
Test status
Simulation time 103267750767 ps
CPU time 347.52 seconds
Started Aug 01 04:22:24 PM PDT 24
Finished Aug 01 04:28:12 PM PDT 24
Peak memory 195136 kb
Host smart-925afa55-f038-4d8f-9d58-ecf9adc0618a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104493983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.104493983
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.208943562
Short name T87
Test name
Test status
Simulation time 295752286599 ps
CPU time 542.88 seconds
Started Aug 01 04:22:35 PM PDT 24
Finished Aug 01 04:31:38 PM PDT 24
Peak memory 191516 kb
Host smart-498ad65b-347c-4e10-ba8d-9f22a503999e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208943562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.208943562
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.1735382368
Short name T315
Test name
Test status
Simulation time 647028294095 ps
CPU time 598.37 seconds
Started Aug 01 04:22:41 PM PDT 24
Finished Aug 01 04:32:40 PM PDT 24
Peak memory 182920 kb
Host smart-fa5e142a-6e45-4671-9fdb-ae6fcb60c29f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735382368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.1735382368
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.1284485316
Short name T356
Test name
Test status
Simulation time 130943312645 ps
CPU time 155.49 seconds
Started Aug 01 04:22:35 PM PDT 24
Finished Aug 01 04:25:10 PM PDT 24
Peak memory 183024 kb
Host smart-f8e61c55-b90a-4515-8514-c9f462d52c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284485316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.1284485316
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.1170741926
Short name T116
Test name
Test status
Simulation time 124881543347 ps
CPU time 129.48 seconds
Started Aug 01 04:22:43 PM PDT 24
Finished Aug 01 04:24:53 PM PDT 24
Peak memory 191420 kb
Host smart-ad2308ba-68bb-4f09-96c8-911008b3a21b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170741926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.1170741926
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.646234961
Short name T450
Test name
Test status
Simulation time 84833532903 ps
CPU time 462.84 seconds
Started Aug 01 04:23:17 PM PDT 24
Finished Aug 01 04:31:00 PM PDT 24
Peak memory 191496 kb
Host smart-a8827fd4-ab92-49d1-81c2-9ef31130b1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646234961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.646234961
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.3211196744
Short name T7
Test name
Test status
Simulation time 65304358 ps
CPU time 0.54 seconds
Started Aug 01 04:22:25 PM PDT 24
Finished Aug 01 04:22:26 PM PDT 24
Peak memory 182608 kb
Host smart-257aed0d-069b-41bb-b0f9-26d9a5b25551
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211196744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
3211196744
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/90.rv_timer_random.1487049475
Short name T198
Test name
Test status
Simulation time 164660592230 ps
CPU time 158.55 seconds
Started Aug 01 04:23:36 PM PDT 24
Finished Aug 01 04:26:15 PM PDT 24
Peak memory 190380 kb
Host smart-bd4652fa-aef3-4aab-be62-8a91c6e09ca7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487049475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.1487049475
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.4279212539
Short name T351
Test name
Test status
Simulation time 308540961659 ps
CPU time 326.53 seconds
Started Aug 01 04:23:35 PM PDT 24
Finished Aug 01 04:29:02 PM PDT 24
Peak memory 182912 kb
Host smart-43d93215-8fb6-416e-af1c-ce2d5005c134
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279212539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.4279212539
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.3393150975
Short name T171
Test name
Test status
Simulation time 183346915176 ps
CPU time 128.52 seconds
Started Aug 01 04:23:36 PM PDT 24
Finished Aug 01 04:25:45 PM PDT 24
Peak memory 192576 kb
Host smart-72f2d6f0-c1a1-453c-b560-a4165782e952
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393150975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.3393150975
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.4171733079
Short name T212
Test name
Test status
Simulation time 133509930487 ps
CPU time 285.03 seconds
Started Aug 01 04:22:45 PM PDT 24
Finished Aug 01 04:27:30 PM PDT 24
Peak memory 191464 kb
Host smart-1e1770c1-19e2-4e93-9f08-91bc253b755f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171733079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.4171733079
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.4047692424
Short name T108
Test name
Test status
Simulation time 237986580227 ps
CPU time 114.48 seconds
Started Aug 01 04:22:45 PM PDT 24
Finished Aug 01 04:24:40 PM PDT 24
Peak memory 191328 kb
Host smart-fd5cc3aa-2df8-4de4-81a0-4ad86c7f7447
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047692424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.4047692424
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.3642897642
Short name T338
Test name
Test status
Simulation time 170097891120 ps
CPU time 237.96 seconds
Started Aug 01 04:23:52 PM PDT 24
Finished Aug 01 04:27:51 PM PDT 24
Peak memory 190572 kb
Host smart-b5652f3c-2733-4a49-b4f4-f106bc60f587
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642897642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.3642897642
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.648871548
Short name T165
Test name
Test status
Simulation time 627669995607 ps
CPU time 606.66 seconds
Started Aug 01 04:22:46 PM PDT 24
Finished Aug 01 04:32:52 PM PDT 24
Peak memory 194916 kb
Host smart-43ee55af-ff5a-4bfc-9891-8c8fd26db685
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648871548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.648871548
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.1130333596
Short name T308
Test name
Test status
Simulation time 188081826552 ps
CPU time 68.77 seconds
Started Aug 01 04:22:46 PM PDT 24
Finished Aug 01 04:23:54 PM PDT 24
Peak memory 183256 kb
Host smart-77c1fcdf-295f-4dc9-b7b9-b20156f57b00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130333596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.1130333596
Directory /workspace/98.rv_timer_random/latest
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