Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.64 99.36 98.73 100.00 100.00 100.00 99.77


Total test records in report: 580
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T509 /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.4067965813 Aug 02 04:39:07 PM PDT 24 Aug 02 04:39:07 PM PDT 24 77627284 ps
T510 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3459748160 Aug 02 04:40:19 PM PDT 24 Aug 02 04:40:21 PM PDT 24 29354388 ps
T511 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.173929155 Aug 02 04:39:14 PM PDT 24 Aug 02 04:39:15 PM PDT 24 23174999 ps
T512 /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.3650853047 Aug 02 04:39:06 PM PDT 24 Aug 02 04:39:07 PM PDT 24 335205115 ps
T513 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.1558873451 Aug 02 04:38:59 PM PDT 24 Aug 02 04:39:01 PM PDT 24 1128243768 ps
T514 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3950958944 Aug 02 04:39:05 PM PDT 24 Aug 02 04:39:06 PM PDT 24 175895148 ps
T515 /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2887137633 Aug 02 04:39:25 PM PDT 24 Aug 02 04:39:26 PM PDT 24 14190171 ps
T516 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.3883781987 Aug 02 04:39:10 PM PDT 24 Aug 02 04:39:10 PM PDT 24 95234656 ps
T517 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.1718519362 Aug 02 04:39:32 PM PDT 24 Aug 02 04:39:33 PM PDT 24 14624003 ps
T101 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.2143415191 Aug 02 04:39:12 PM PDT 24 Aug 02 04:39:13 PM PDT 24 37885775 ps
T102 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.1476551391 Aug 02 04:39:02 PM PDT 24 Aug 02 04:39:03 PM PDT 24 59267233 ps
T518 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2935076678 Aug 02 04:39:01 PM PDT 24 Aug 02 04:39:02 PM PDT 24 30511634 ps
T519 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.580837179 Aug 02 04:39:03 PM PDT 24 Aug 02 04:39:05 PM PDT 24 30582961 ps
T520 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.4178993204 Aug 02 04:39:27 PM PDT 24 Aug 02 04:39:33 PM PDT 24 40533642 ps
T521 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.3971216495 Aug 02 04:39:12 PM PDT 24 Aug 02 04:39:13 PM PDT 24 60288830 ps
T522 /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.798353000 Aug 02 04:39:45 PM PDT 24 Aug 02 04:39:46 PM PDT 24 133977964 ps
T523 /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.2370946404 Aug 02 04:39:07 PM PDT 24 Aug 02 04:39:09 PM PDT 24 466907432 ps
T524 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.3511023249 Aug 02 04:39:11 PM PDT 24 Aug 02 04:39:12 PM PDT 24 191781269 ps
T525 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.3782524285 Aug 02 04:39:04 PM PDT 24 Aug 02 04:39:05 PM PDT 24 21336434 ps
T526 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.3613659839 Aug 02 04:39:31 PM PDT 24 Aug 02 04:39:32 PM PDT 24 207445992 ps
T527 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1656643327 Aug 02 04:39:43 PM PDT 24 Aug 02 04:39:44 PM PDT 24 145647074 ps
T528 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.4107219937 Aug 02 04:39:48 PM PDT 24 Aug 02 04:39:48 PM PDT 24 16358678 ps
T103 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3333287252 Aug 02 04:39:15 PM PDT 24 Aug 02 04:39:16 PM PDT 24 17477714 ps
T529 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.2881124931 Aug 02 04:39:11 PM PDT 24 Aug 02 04:39:14 PM PDT 24 165338258 ps
T530 /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.1501441375 Aug 02 04:39:29 PM PDT 24 Aug 02 04:39:30 PM PDT 24 36786320 ps
T531 /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.3370662936 Aug 02 04:39:05 PM PDT 24 Aug 02 04:39:06 PM PDT 24 40242357 ps
T532 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.1409882746 Aug 02 04:39:12 PM PDT 24 Aug 02 04:39:13 PM PDT 24 56718838 ps
T533 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.1267061652 Aug 02 04:39:01 PM PDT 24 Aug 02 04:39:03 PM PDT 24 105790870 ps
T534 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.4090998571 Aug 02 04:39:35 PM PDT 24 Aug 02 04:39:36 PM PDT 24 29639239 ps
T535 /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.2663071750 Aug 02 04:39:48 PM PDT 24 Aug 02 04:39:48 PM PDT 24 10260990 ps
T536 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.22119288 Aug 02 04:39:28 PM PDT 24 Aug 02 04:39:29 PM PDT 24 14935022 ps
T537 /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.2223575999 Aug 02 04:39:04 PM PDT 24 Aug 02 04:39:04 PM PDT 24 27262019 ps
T538 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.1943681340 Aug 02 04:39:23 PM PDT 24 Aug 02 04:39:24 PM PDT 24 21612080 ps
T539 /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.1030612986 Aug 02 04:40:34 PM PDT 24 Aug 02 04:40:34 PM PDT 24 67373828 ps
T540 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.2095946834 Aug 02 04:39:28 PM PDT 24 Aug 02 04:39:28 PM PDT 24 12596374 ps
T541 /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.3302734839 Aug 02 04:39:32 PM PDT 24 Aug 02 04:39:32 PM PDT 24 15637487 ps
T542 /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.2451243987 Aug 02 04:39:18 PM PDT 24 Aug 02 04:39:19 PM PDT 24 19990367 ps
T543 /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.431990550 Aug 02 04:39:22 PM PDT 24 Aug 02 04:39:23 PM PDT 24 98000446 ps
T104 /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.1662355019 Aug 02 04:39:14 PM PDT 24 Aug 02 04:39:15 PM PDT 24 36909655 ps
T544 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.722722743 Aug 02 04:39:27 PM PDT 24 Aug 02 04:39:28 PM PDT 24 93056703 ps
T545 /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.4271811919 Aug 02 04:39:37 PM PDT 24 Aug 02 04:39:37 PM PDT 24 15375962 ps
T546 /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.406054768 Aug 02 04:38:50 PM PDT 24 Aug 02 04:38:50 PM PDT 24 165891132 ps
T547 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.2645932357 Aug 02 04:39:46 PM PDT 24 Aug 02 04:39:48 PM PDT 24 44278849 ps
T548 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.3611379985 Aug 02 04:39:02 PM PDT 24 Aug 02 04:39:02 PM PDT 24 57236930 ps
T549 /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.1106807243 Aug 02 04:39:02 PM PDT 24 Aug 02 04:39:03 PM PDT 24 15620729 ps
T550 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.4160729169 Aug 02 04:40:36 PM PDT 24 Aug 02 04:40:37 PM PDT 24 173672182 ps
T105 /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.1496013122 Aug 02 04:38:54 PM PDT 24 Aug 02 04:38:55 PM PDT 24 25278342 ps
T108 /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.1983490599 Aug 02 04:39:14 PM PDT 24 Aug 02 04:39:15 PM PDT 24 27278690 ps
T551 /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.3426629474 Aug 02 04:39:12 PM PDT 24 Aug 02 04:39:13 PM PDT 24 86192255 ps
T552 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.2395378711 Aug 02 04:39:19 PM PDT 24 Aug 02 04:39:20 PM PDT 24 14069574 ps
T553 /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.246944612 Aug 02 04:39:20 PM PDT 24 Aug 02 04:39:22 PM PDT 24 110229773 ps
T554 /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.4281767235 Aug 02 04:39:00 PM PDT 24 Aug 02 04:39:01 PM PDT 24 75916695 ps
T555 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.1767310030 Aug 02 04:39:13 PM PDT 24 Aug 02 04:39:15 PM PDT 24 86257844 ps
T556 /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.3020872317 Aug 02 04:39:07 PM PDT 24 Aug 02 04:39:08 PM PDT 24 34622689 ps
T557 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.3897395779 Aug 02 04:39:02 PM PDT 24 Aug 02 04:39:05 PM PDT 24 83488120 ps
T106 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.4120663909 Aug 02 04:38:53 PM PDT 24 Aug 02 04:38:54 PM PDT 24 39010056 ps
T558 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.3976658324 Aug 02 04:39:01 PM PDT 24 Aug 02 04:39:02 PM PDT 24 14139768 ps
T559 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.301306152 Aug 02 04:39:29 PM PDT 24 Aug 02 04:39:30 PM PDT 24 55914049 ps
T560 /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.2633239663 Aug 02 04:39:02 PM PDT 24 Aug 02 04:39:03 PM PDT 24 16204217 ps
T107 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.2582902540 Aug 02 04:38:59 PM PDT 24 Aug 02 04:38:59 PM PDT 24 17780651 ps
T561 /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.3696136813 Aug 02 04:39:04 PM PDT 24 Aug 02 04:39:07 PM PDT 24 609553075 ps
T562 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.4091273134 Aug 02 04:40:38 PM PDT 24 Aug 02 04:40:39 PM PDT 24 24686441 ps
T563 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.4220206012 Aug 02 04:39:14 PM PDT 24 Aug 02 04:39:15 PM PDT 24 15991275 ps
T564 /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.395054106 Aug 02 04:39:08 PM PDT 24 Aug 02 04:39:09 PM PDT 24 61421471 ps
T565 /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.2160562580 Aug 02 04:38:58 PM PDT 24 Aug 02 04:38:59 PM PDT 24 65830718 ps
T566 /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.2100431437 Aug 02 04:39:14 PM PDT 24 Aug 02 04:39:16 PM PDT 24 62601968 ps
T567 /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.4264050128 Aug 02 04:38:52 PM PDT 24 Aug 02 04:38:53 PM PDT 24 51176078 ps
T568 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.780276066 Aug 02 04:38:56 PM PDT 24 Aug 02 04:38:57 PM PDT 24 354092602 ps
T569 /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.2106602667 Aug 02 04:39:44 PM PDT 24 Aug 02 04:39:44 PM PDT 24 44686086 ps
T570 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2489535602 Aug 02 04:39:50 PM PDT 24 Aug 02 04:39:51 PM PDT 24 11637113 ps
T571 /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3341401126 Aug 02 04:39:12 PM PDT 24 Aug 02 04:39:14 PM PDT 24 654262682 ps
T572 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.1789256056 Aug 02 04:39:04 PM PDT 24 Aug 02 04:39:05 PM PDT 24 306918634 ps
T573 /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.269815361 Aug 02 04:39:13 PM PDT 24 Aug 02 04:39:14 PM PDT 24 27186268 ps
T574 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2119807093 Aug 02 04:39:48 PM PDT 24 Aug 02 04:39:49 PM PDT 24 398601519 ps
T575 /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.2961664083 Aug 02 04:39:21 PM PDT 24 Aug 02 04:39:22 PM PDT 24 14921927 ps
T576 /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.1051690097 Aug 02 04:39:14 PM PDT 24 Aug 02 04:39:15 PM PDT 24 31652998 ps
T577 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.2910381159 Aug 02 04:39:10 PM PDT 24 Aug 02 04:39:11 PM PDT 24 143931385 ps
T578 /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.582417172 Aug 02 04:38:56 PM PDT 24 Aug 02 04:38:57 PM PDT 24 27994472 ps
T579 /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.2888943343 Aug 02 04:39:28 PM PDT 24 Aug 02 04:39:29 PM PDT 24 32500946 ps
T580 /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.122706768 Aug 02 04:39:29 PM PDT 24 Aug 02 04:39:30 PM PDT 24 211311392 ps

Test location /workspace/coverage/default/40.rv_timer_stress_all.726083102
Short name T6
Test name
Test status
Simulation time 2380144778989 ps
CPU time 4159.07 seconds
Started Aug 02 04:39:58 PM PDT 24
Finished Aug 02 05:49:18 PM PDT 24
Peak memory 191384 kb
Host smart-c9b671c2-4416-4604-b412-4c9b47af7191
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726083102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all.
726083102
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all_with_rand_reset.2194140456
Short name T15
Test name
Test status
Simulation time 89347979624 ps
CPU time 919.9 seconds
Started Aug 02 04:39:30 PM PDT 24
Finished Aug 02 04:54:50 PM PDT 24
Peak memory 213744 kb
Host smart-f38c466c-e74d-4d54-a793-99f2c8271195
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194140456 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all_with_rand_reset.2194140456
Directory /workspace/9.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.289225377
Short name T46
Test name
Test status
Simulation time 215254311640 ps
CPU time 408.5 seconds
Started Aug 02 04:39:51 PM PDT 24
Finished Aug 02 04:46:40 PM PDT 24
Peak memory 196108 kb
Host smart-f7fa9a5a-1914-470b-b0bd-aeede210dd45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289225377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all.
289225377
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.2277887527
Short name T31
Test name
Test status
Simulation time 304769552 ps
CPU time 0.85 seconds
Started Aug 02 04:39:29 PM PDT 24
Finished Aug 02 04:39:30 PM PDT 24
Peak memory 193844 kb
Host smart-50df9b52-9c38-49ba-8b63-8a371be19630
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277887527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.2277887527
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.721932647
Short name T153
Test name
Test status
Simulation time 1821651038591 ps
CPU time 2590.76 seconds
Started Aug 02 04:39:48 PM PDT 24
Finished Aug 02 05:23:00 PM PDT 24
Peak memory 197560 kb
Host smart-239b0d09-b6b0-46c0-b93d-dfbb40ee97e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721932647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.721932647
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.3887255680
Short name T152
Test name
Test status
Simulation time 1145348526274 ps
CPU time 1832.96 seconds
Started Aug 02 04:39:35 PM PDT 24
Finished Aug 02 05:10:09 PM PDT 24
Peak memory 191556 kb
Host smart-77d830d4-384c-4ee9-8317-eba431afbb22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887255680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.3887255680
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.4177480210
Short name T227
Test name
Test status
Simulation time 600097131226 ps
CPU time 1182.72 seconds
Started Aug 02 04:39:50 PM PDT 24
Finished Aug 02 04:59:33 PM PDT 24
Peak memory 196060 kb
Host smart-2d541272-977f-4070-a572-aeba88c3a2a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177480210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.4177480210
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.1922830071
Short name T74
Test name
Test status
Simulation time 4134415148716 ps
CPU time 1448.14 seconds
Started Aug 02 04:40:07 PM PDT 24
Finished Aug 02 05:04:15 PM PDT 24
Peak memory 191508 kb
Host smart-d75f0f02-d503-457c-9c03-5ef6f96ec3e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922830071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.1922830071
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.2709402785
Short name T131
Test name
Test status
Simulation time 2612845707933 ps
CPU time 3690.3 seconds
Started Aug 02 04:39:31 PM PDT 24
Finished Aug 02 05:41:02 PM PDT 24
Peak memory 191476 kb
Host smart-24b0fd52-e3d2-40b3-9b22-a51d55a75b43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709402785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.2709402785
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.1659022819
Short name T164
Test name
Test status
Simulation time 363021041952 ps
CPU time 1026.05 seconds
Started Aug 02 04:40:15 PM PDT 24
Finished Aug 02 04:57:21 PM PDT 24
Peak memory 191520 kb
Host smart-97f89a40-3651-4767-8afe-57d74e4ad98e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659022819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.1659022819
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.2944030742
Short name T69
Test name
Test status
Simulation time 823916608110 ps
CPU time 1455.69 seconds
Started Aug 02 04:40:02 PM PDT 24
Finished Aug 02 05:04:18 PM PDT 24
Peak memory 191456 kb
Host smart-28716b99-2aa4-4251-a138-104c6d93ee2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944030742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.2944030742
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.193948046
Short name T217
Test name
Test status
Simulation time 299693858680 ps
CPU time 2261.22 seconds
Started Aug 02 04:40:11 PM PDT 24
Finished Aug 02 05:17:53 PM PDT 24
Peak memory 195500 kb
Host smart-cb439c24-5b14-4595-89c2-d81169ac98b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193948046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all.
193948046
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/128.rv_timer_random.172386281
Short name T50
Test name
Test status
Simulation time 201373297175 ps
CPU time 352.55 seconds
Started Aug 02 04:40:24 PM PDT 24
Finished Aug 02 04:46:17 PM PDT 24
Peak memory 191624 kb
Host smart-2845b021-c795-4925-862e-92d0f1831e96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172386281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.172386281
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.3030009273
Short name T19
Test name
Test status
Simulation time 287811874 ps
CPU time 0.88 seconds
Started Aug 02 04:39:27 PM PDT 24
Finished Aug 02 04:39:28 PM PDT 24
Peak memory 213828 kb
Host smart-ea801c74-0e0e-4b95-8fe1-ba6ad1e02dda
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030009273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.3030009273
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.66576236
Short name T200
Test name
Test status
Simulation time 1200891746452 ps
CPU time 810.44 seconds
Started Aug 02 04:39:34 PM PDT 24
Finished Aug 02 04:53:04 PM PDT 24
Peak memory 191180 kb
Host smart-0feaad1e-13e5-4647-8154-55133c68e85b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66576236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.66576236
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.2421712659
Short name T71
Test name
Test status
Simulation time 414344214929 ps
CPU time 1357.97 seconds
Started Aug 02 04:39:42 PM PDT 24
Finished Aug 02 05:02:20 PM PDT 24
Peak memory 193872 kb
Host smart-03b2f972-2073-4387-8381-cd167f386e1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421712659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
2421712659
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.1458321704
Short name T11
Test name
Test status
Simulation time 413161345511 ps
CPU time 485.8 seconds
Started Aug 02 04:40:02 PM PDT 24
Finished Aug 02 04:48:08 PM PDT 24
Peak memory 183220 kb
Host smart-a605c7a7-aa82-4018-a237-830163179716
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458321704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.1458321704
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.2237224988
Short name T75
Test name
Test status
Simulation time 1453004989927 ps
CPU time 1198.84 seconds
Started Aug 02 04:39:49 PM PDT 24
Finished Aug 02 04:59:48 PM PDT 24
Peak memory 193940 kb
Host smart-f6724166-fb7c-4739-a7f2-7218059de38b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237224988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.2237224988
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/156.rv_timer_random.2270700046
Short name T134
Test name
Test status
Simulation time 506342658882 ps
CPU time 333.22 seconds
Started Aug 02 04:40:21 PM PDT 24
Finished Aug 02 04:45:54 PM PDT 24
Peak memory 191564 kb
Host smart-4385f0c6-c438-4537-8aca-646d39364329
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270700046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.2270700046
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.4158170652
Short name T121
Test name
Test status
Simulation time 1205407688827 ps
CPU time 206.86 seconds
Started Aug 02 04:40:41 PM PDT 24
Finished Aug 02 04:44:08 PM PDT 24
Peak memory 191524 kb
Host smart-e972699f-513f-4b4b-aa04-52b4c38a2198
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158170652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.4158170652
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.4120663909
Short name T106
Test name
Test status
Simulation time 39010056 ps
CPU time 0.84 seconds
Started Aug 02 04:38:53 PM PDT 24
Finished Aug 02 04:38:54 PM PDT 24
Peak memory 192704 kb
Host smart-54ecb5ec-bf45-42cc-ae3d-c60bb8850854
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120663909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.4120663909
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/default/100.rv_timer_random.613458539
Short name T172
Test name
Test status
Simulation time 117528861348 ps
CPU time 539.75 seconds
Started Aug 02 04:40:20 PM PDT 24
Finished Aug 02 04:49:20 PM PDT 24
Peak memory 191328 kb
Host smart-0bd83465-7188-41df-a3ca-f786019e2a70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613458539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.613458539
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.2412353242
Short name T183
Test name
Test status
Simulation time 1824385969731 ps
CPU time 892.65 seconds
Started Aug 02 04:39:42 PM PDT 24
Finished Aug 02 04:54:35 PM PDT 24
Peak memory 191524 kb
Host smart-82cc7e1b-56bf-44b0-afc1-74acab4f1a6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412353242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.2412353242
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_random.3035521664
Short name T8
Test name
Test status
Simulation time 192229642029 ps
CPU time 309.69 seconds
Started Aug 02 04:39:50 PM PDT 24
Finished Aug 02 04:44:59 PM PDT 24
Peak memory 191492 kb
Host smart-7bdb6935-825d-4539-8432-b2546148539b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035521664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.3035521664
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.3551622427
Short name T176
Test name
Test status
Simulation time 720829264366 ps
CPU time 546.04 seconds
Started Aug 02 04:40:24 PM PDT 24
Finished Aug 02 04:49:30 PM PDT 24
Peak memory 191528 kb
Host smart-12f9dad9-5dc7-4d06-a385-a2fc47995a86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551622427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.3551622427
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/150.rv_timer_random.1001304672
Short name T148
Test name
Test status
Simulation time 172727911319 ps
CPU time 734.18 seconds
Started Aug 02 04:40:29 PM PDT 24
Finished Aug 02 04:52:44 PM PDT 24
Peak memory 191512 kb
Host smart-89af874d-71be-4311-a090-7916eec81f0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001304672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.1001304672
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.1294350262
Short name T165
Test name
Test status
Simulation time 1185115972443 ps
CPU time 1602.97 seconds
Started Aug 02 04:39:48 PM PDT 24
Finished Aug 02 05:06:31 PM PDT 24
Peak memory 191452 kb
Host smart-1f441aa9-7b45-4e5a-a3b0-c90f2e6d0e0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294350262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.1294350262
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.381693101
Short name T77
Test name
Test status
Simulation time 6540779651827 ps
CPU time 1730.63 seconds
Started Aug 02 04:39:48 PM PDT 24
Finished Aug 02 05:08:39 PM PDT 24
Peak memory 191548 kb
Host smart-79063fe7-693a-4be2-a8a0-0cbe4a858998
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381693101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.
381693101
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.1397482110
Short name T234
Test name
Test status
Simulation time 346195340566 ps
CPU time 909.44 seconds
Started Aug 02 04:40:04 PM PDT 24
Finished Aug 02 04:55:14 PM PDT 24
Peak memory 191520 kb
Host smart-3ac7ab55-4b63-4184-8e3b-ef76156fa5d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397482110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.1397482110
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/109.rv_timer_random.3107735483
Short name T173
Test name
Test status
Simulation time 114636448910 ps
CPU time 137.99 seconds
Started Aug 02 04:40:29 PM PDT 24
Finished Aug 02 04:42:47 PM PDT 24
Peak memory 191532 kb
Host smart-4bfb1dae-82d4-4071-971a-90df9e7e3202
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107735483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.3107735483
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random.3096443392
Short name T189
Test name
Test status
Simulation time 1571678843363 ps
CPU time 320.95 seconds
Started Aug 02 04:39:56 PM PDT 24
Finished Aug 02 04:45:17 PM PDT 24
Peak memory 191412 kb
Host smart-e8f7aac5-b677-4cb7-a9fc-e313910c1dfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096443392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.3096443392
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random.3337087798
Short name T338
Test name
Test status
Simulation time 427620006258 ps
CPU time 342.68 seconds
Started Aug 02 04:40:12 PM PDT 24
Finished Aug 02 04:45:55 PM PDT 24
Peak memory 191548 kb
Host smart-402e20da-5f32-41cc-8611-df27fb94a4a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337087798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.3337087798
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.877877232
Short name T269
Test name
Test status
Simulation time 198001628265 ps
CPU time 595.38 seconds
Started Aug 02 04:40:22 PM PDT 24
Finished Aug 02 04:50:18 PM PDT 24
Peak memory 195216 kb
Host smart-f234334b-23f2-425c-8a15-088ecb5ac60a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877877232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.877877232
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.3258603596
Short name T202
Test name
Test status
Simulation time 106941772381 ps
CPU time 161.27 seconds
Started Aug 02 04:40:50 PM PDT 24
Finished Aug 02 04:43:32 PM PDT 24
Peak memory 191416 kb
Host smart-cbdb00d5-910c-4e95-a2cf-04c00bb6478f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258603596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.3258603596
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.307691592
Short name T126
Test name
Test status
Simulation time 158937132339 ps
CPU time 240.41 seconds
Started Aug 02 04:40:37 PM PDT 24
Finished Aug 02 04:44:37 PM PDT 24
Peak memory 193736 kb
Host smart-3396c2d8-9c16-4366-a011-9f27683d602a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307691592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.307691592
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random.3000031023
Short name T233
Test name
Test status
Simulation time 448954560286 ps
CPU time 225.68 seconds
Started Aug 02 04:39:32 PM PDT 24
Finished Aug 02 04:43:18 PM PDT 24
Peak memory 191484 kb
Host smart-eb612882-d822-46f1-bd18-72d11930794a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000031023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.3000031023
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.2887079725
Short name T218
Test name
Test status
Simulation time 1574258301606 ps
CPU time 817.03 seconds
Started Aug 02 04:40:14 PM PDT 24
Finished Aug 02 04:53:51 PM PDT 24
Peak memory 191552 kb
Host smart-afdedf4b-a5ce-448f-b4de-c62f5695d873
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887079725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.2887079725
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.783508413
Short name T209
Test name
Test status
Simulation time 146814408146 ps
CPU time 202.88 seconds
Started Aug 02 04:40:19 PM PDT 24
Finished Aug 02 04:43:42 PM PDT 24
Peak memory 191484 kb
Host smart-7a851941-2776-4d31-97c4-f43ca367c493
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783508413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.783508413
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.153501895
Short name T169
Test name
Test status
Simulation time 148113742500 ps
CPU time 478.34 seconds
Started Aug 02 04:40:35 PM PDT 24
Finished Aug 02 04:48:33 PM PDT 24
Peak memory 191520 kb
Host smart-1ff31232-bcb3-475a-81f5-23993abc30b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153501895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.153501895
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.1725937320
Short name T231
Test name
Test status
Simulation time 141313363461 ps
CPU time 215.94 seconds
Started Aug 02 04:40:18 PM PDT 24
Finished Aug 02 04:43:55 PM PDT 24
Peak memory 193836 kb
Host smart-acc31982-7962-4bbd-9bbd-a37311f4313f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725937320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.1725937320
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.2199065777
Short name T190
Test name
Test status
Simulation time 441117262531 ps
CPU time 828.98 seconds
Started Aug 02 04:40:15 PM PDT 24
Finished Aug 02 04:54:04 PM PDT 24
Peak memory 191488 kb
Host smart-297d14f9-c08a-478d-991e-077af466ad9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199065777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.2199065777
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.4137925274
Short name T225
Test name
Test status
Simulation time 262596488693 ps
CPU time 159.02 seconds
Started Aug 02 04:40:17 PM PDT 24
Finished Aug 02 04:42:56 PM PDT 24
Peak memory 191568 kb
Host smart-520b5ff0-3512-4edc-83cc-7d2bf8920ba6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137925274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.4137925274
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.1506772073
Short name T185
Test name
Test status
Simulation time 237535296688 ps
CPU time 382.15 seconds
Started Aug 02 04:39:37 PM PDT 24
Finished Aug 02 04:46:00 PM PDT 24
Peak memory 183316 kb
Host smart-933f3c2a-77e7-4fa9-88bc-6bf6cc21a59b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506772073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.1506772073
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_random.4084778125
Short name T280
Test name
Test status
Simulation time 374863259586 ps
CPU time 256.29 seconds
Started Aug 02 04:39:35 PM PDT 24
Finished Aug 02 04:43:51 PM PDT 24
Peak memory 191508 kb
Host smart-1f294e9b-b3d3-49d8-b393-7dc2ea67a2bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084778125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.4084778125
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/170.rv_timer_random.1044309224
Short name T261
Test name
Test status
Simulation time 303268297001 ps
CPU time 245.14 seconds
Started Aug 02 04:40:42 PM PDT 24
Finished Aug 02 04:44:48 PM PDT 24
Peak memory 191496 kb
Host smart-7ca4fa57-27ad-491f-b22c-f86133359b0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044309224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.1044309224
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random.2449244412
Short name T286
Test name
Test status
Simulation time 113585064206 ps
CPU time 343.21 seconds
Started Aug 02 04:39:48 PM PDT 24
Finished Aug 02 04:45:31 PM PDT 24
Peak memory 191508 kb
Host smart-7f3e8da7-6918-4de9-bf0e-d8ffcdb180f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449244412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.2449244412
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.837803924
Short name T72
Test name
Test status
Simulation time 526881134699 ps
CPU time 600.78 seconds
Started Aug 02 04:39:36 PM PDT 24
Finished Aug 02 04:49:37 PM PDT 24
Peak memory 191496 kb
Host smart-4d41862f-8df9-46da-bfaa-f8032896bf2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837803924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.837803924
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.112671614
Short name T214
Test name
Test status
Simulation time 512489648501 ps
CPU time 245.66 seconds
Started Aug 02 04:40:01 PM PDT 24
Finished Aug 02 04:44:07 PM PDT 24
Peak memory 195972 kb
Host smart-d87445b7-8443-4bef-8197-6cae8e93cb5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112671614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all.
112671614
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/65.rv_timer_random.520862794
Short name T278
Test name
Test status
Simulation time 195220713257 ps
CPU time 2117.21 seconds
Started Aug 02 04:40:11 PM PDT 24
Finished Aug 02 05:15:29 PM PDT 24
Peak memory 191576 kb
Host smart-8d98638d-15fb-4a19-b0fa-d4833b41615a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520862794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.520862794
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.634471725
Short name T118
Test name
Test status
Simulation time 122006334 ps
CPU time 1.53 seconds
Started Aug 02 04:38:56 PM PDT 24
Finished Aug 02 04:38:58 PM PDT 24
Peak memory 195284 kb
Host smart-c2685579-dae4-4287-bfa6-9c4bcf9612a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634471725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_int
g_err.634471725
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/106.rv_timer_random.4206251177
Short name T171
Test name
Test status
Simulation time 70975485344 ps
CPU time 128.23 seconds
Started Aug 02 04:40:18 PM PDT 24
Finished Aug 02 04:42:26 PM PDT 24
Peak memory 191500 kb
Host smart-247b2724-fa0c-4169-b7d0-a3f325f0af9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206251177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.4206251177
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/110.rv_timer_random.2136243427
Short name T175
Test name
Test status
Simulation time 475283924389 ps
CPU time 249.22 seconds
Started Aug 02 04:40:23 PM PDT 24
Finished Aug 02 04:44:33 PM PDT 24
Peak memory 191504 kb
Host smart-41d88ac7-1d51-4ab8-8c33-2b948e92120c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136243427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.2136243427
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.2447727050
Short name T287
Test name
Test status
Simulation time 138071656405 ps
CPU time 286.38 seconds
Started Aug 02 04:40:36 PM PDT 24
Finished Aug 02 04:45:23 PM PDT 24
Peak memory 191496 kb
Host smart-6b82790f-6e1a-4d4f-96e1-1ed06a59051e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447727050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.2447727050
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.3227028028
Short name T323
Test name
Test status
Simulation time 96840779668 ps
CPU time 155.66 seconds
Started Aug 02 04:40:25 PM PDT 24
Finished Aug 02 04:43:01 PM PDT 24
Peak memory 191536 kb
Host smart-8ba1a738-9e4d-4078-9ede-c1612da4a9c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227028028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.3227028028
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.2817896732
Short name T129
Test name
Test status
Simulation time 163634636163 ps
CPU time 534.34 seconds
Started Aug 02 04:40:39 PM PDT 24
Finished Aug 02 04:49:33 PM PDT 24
Peak memory 191504 kb
Host smart-f8d88559-0b1b-4645-94eb-d1462f836e15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817896732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.2817896732
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.2927976042
Short name T353
Test name
Test status
Simulation time 331352272553 ps
CPU time 326.11 seconds
Started Aug 02 04:40:28 PM PDT 24
Finished Aug 02 04:45:54 PM PDT 24
Peak memory 191536 kb
Host smart-ff9698eb-476d-4b9b-8cf3-91a9b4bb99ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927976042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.2927976042
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.1571665720
Short name T356
Test name
Test status
Simulation time 181489840415 ps
CPU time 474.05 seconds
Started Aug 02 04:40:30 PM PDT 24
Finished Aug 02 04:48:24 PM PDT 24
Peak memory 191516 kb
Host smart-7a4a707f-99ca-46e7-a020-31ba9a00b99f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571665720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.1571665720
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.2109966978
Short name T177
Test name
Test status
Simulation time 108229938615 ps
CPU time 89.73 seconds
Started Aug 02 04:39:47 PM PDT 24
Finished Aug 02 04:41:17 PM PDT 24
Peak memory 183252 kb
Host smart-15a55994-3fd6-4cf3-91de-0d82e5744e79
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109966978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.2109966978
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.978618239
Short name T109
Test name
Test status
Simulation time 15808995 ps
CPU time 0.63 seconds
Started Aug 02 04:39:05 PM PDT 24
Finished Aug 02 04:39:05 PM PDT 24
Peak memory 192056 kb
Host smart-ea319e76-b731-47aa-a4de-72defe7e1847
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978618239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_tim
er_same_csr_outstanding.978618239
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/104.rv_timer_random.1804554065
Short name T83
Test name
Test status
Simulation time 336661926699 ps
CPU time 145.28 seconds
Started Aug 02 04:40:22 PM PDT 24
Finished Aug 02 04:42:47 PM PDT 24
Peak memory 191500 kb
Host smart-b585f1b2-3bdc-424a-855b-64a0436f9ebe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804554065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.1804554065
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.2608659097
Short name T60
Test name
Test status
Simulation time 3615862477337 ps
CPU time 1180.5 seconds
Started Aug 02 04:39:35 PM PDT 24
Finished Aug 02 04:59:16 PM PDT 24
Peak memory 183336 kb
Host smart-40823e23-3231-45d7-8587-f29cddeda4ab
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608659097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.2608659097
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/147.rv_timer_random.2812374632
Short name T310
Test name
Test status
Simulation time 1152195606608 ps
CPU time 388.51 seconds
Started Aug 02 04:40:35 PM PDT 24
Finished Aug 02 04:47:04 PM PDT 24
Peak memory 191476 kb
Host smart-85dd429c-dc32-4cac-971a-a5a2efbf2664
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812374632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.2812374632
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.1716030216
Short name T204
Test name
Test status
Simulation time 150037953445 ps
CPU time 124.79 seconds
Started Aug 02 04:40:31 PM PDT 24
Finished Aug 02 04:42:36 PM PDT 24
Peak memory 191600 kb
Host smart-2e749bd1-5d69-4bae-81b0-e12f3d1805e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716030216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.1716030216
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.1701092003
Short name T156
Test name
Test status
Simulation time 338005830258 ps
CPU time 121.51 seconds
Started Aug 02 04:39:47 PM PDT 24
Finished Aug 02 04:41:49 PM PDT 24
Peak memory 183304 kb
Host smart-fe6ebb0c-e275-47b2-ae04-4d457de9307b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701092003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.1701092003
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/177.rv_timer_random.1449009346
Short name T23
Test name
Test status
Simulation time 714898096145 ps
CPU time 557.16 seconds
Started Aug 02 04:40:31 PM PDT 24
Finished Aug 02 04:49:49 PM PDT 24
Peak memory 192496 kb
Host smart-e77f040a-a4e3-4a9f-bc01-8d5319dd584b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449009346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.1449009346
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.2259817767
Short name T192
Test name
Test status
Simulation time 373100955554 ps
CPU time 622.87 seconds
Started Aug 02 04:39:55 PM PDT 24
Finished Aug 02 04:50:18 PM PDT 24
Peak memory 183208 kb
Host smart-82cb89b4-c2ba-4b3d-8030-965b3633ec55
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259817767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.2259817767
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.361197152
Short name T294
Test name
Test status
Simulation time 24066727994 ps
CPU time 22.78 seconds
Started Aug 02 04:39:42 PM PDT 24
Finished Aug 02 04:40:05 PM PDT 24
Peak memory 183244 kb
Host smart-4534838c-ec99-40fc-b9d2-e77c2f2092da
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361197152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.rv_timer_cfg_update_on_fly.361197152
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_random.1891427254
Short name T181
Test name
Test status
Simulation time 108746501747 ps
CPU time 321.6 seconds
Started Aug 02 04:39:50 PM PDT 24
Finished Aug 02 04:45:12 PM PDT 24
Peak memory 191468 kb
Host smart-2611cad7-8f06-45b1-9927-862e5ff610dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891427254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.1891427254
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random.2110094271
Short name T355
Test name
Test status
Simulation time 342195893057 ps
CPU time 114.14 seconds
Started Aug 02 04:39:33 PM PDT 24
Finished Aug 02 04:41:28 PM PDT 24
Peak memory 191496 kb
Host smart-6b27af2b-3f91-4281-a901-26c62d23c6a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110094271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.2110094271
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.2762092435
Short name T30
Test name
Test status
Simulation time 41995781330 ps
CPU time 71.55 seconds
Started Aug 02 04:39:52 PM PDT 24
Finished Aug 02 04:41:04 PM PDT 24
Peak memory 183332 kb
Host smart-27306c94-617e-48a2-8251-922edcf50fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762092435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.2762092435
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_random.2332693949
Short name T295
Test name
Test status
Simulation time 882856285168 ps
CPU time 1032.36 seconds
Started Aug 02 04:39:58 PM PDT 24
Finished Aug 02 04:57:11 PM PDT 24
Peak memory 191524 kb
Host smart-d78b6100-d08f-4d2c-8381-cfff31945c18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332693949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.2332693949
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random.1202792264
Short name T221
Test name
Test status
Simulation time 43777128293 ps
CPU time 517.77 seconds
Started Aug 02 04:40:00 PM PDT 24
Finished Aug 02 04:48:38 PM PDT 24
Peak memory 191204 kb
Host smart-b5c4f4b5-af84-482c-b53e-47c9f5161242
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202792264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.1202792264
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.3818381490
Short name T161
Test name
Test status
Simulation time 73511438200 ps
CPU time 148.9 seconds
Started Aug 02 04:40:07 PM PDT 24
Finished Aug 02 04:42:36 PM PDT 24
Peak memory 191556 kb
Host smart-f3cdcbbe-c36d-4147-ab99-a63ab8245bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818381490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.3818381490
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.1917799677
Short name T244
Test name
Test status
Simulation time 646859236530 ps
CPU time 378.12 seconds
Started Aug 02 04:39:33 PM PDT 24
Finished Aug 02 04:45:52 PM PDT 24
Peak memory 183232 kb
Host smart-85866ae8-58ad-4320-8724-a134a1ec0f87
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917799677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.1917799677
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/90.rv_timer_random.1468981043
Short name T120
Test name
Test status
Simulation time 329261205472 ps
CPU time 746.87 seconds
Started Aug 02 04:40:31 PM PDT 24
Finished Aug 02 04:52:58 PM PDT 24
Peak memory 191620 kb
Host smart-f064fc5a-2055-449a-bb12-b1537a33b467
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468981043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.1468981043
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.1306462185
Short name T242
Test name
Test status
Simulation time 495567711571 ps
CPU time 1636.74 seconds
Started Aug 02 04:40:26 PM PDT 24
Finished Aug 02 05:07:43 PM PDT 24
Peak memory 191508 kb
Host smart-cc842a67-f549-4a91-abb6-d4238d01fdf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306462185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.1306462185
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.3007663642
Short name T158
Test name
Test status
Simulation time 745697790117 ps
CPU time 420.02 seconds
Started Aug 02 04:39:44 PM PDT 24
Finished Aug 02 04:46:44 PM PDT 24
Peak memory 183312 kb
Host smart-66551c2d-1e6b-419b-87e3-54b2cbf75852
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007663642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.3007663642
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/101.rv_timer_random.2281782896
Short name T319
Test name
Test status
Simulation time 36596624591 ps
CPU time 59.47 seconds
Started Aug 02 04:40:29 PM PDT 24
Finished Aug 02 04:41:29 PM PDT 24
Peak memory 191500 kb
Host smart-92e4e4c6-aac0-47b3-be0d-f1f0d0eba479
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281782896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.2281782896
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.4267746812
Short name T147
Test name
Test status
Simulation time 864368354584 ps
CPU time 115.9 seconds
Started Aug 02 04:40:25 PM PDT 24
Finished Aug 02 04:42:21 PM PDT 24
Peak memory 191496 kb
Host smart-20bc7c69-e389-4efe-87f5-34b8e9b54291
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267746812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.4267746812
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.297597152
Short name T163
Test name
Test status
Simulation time 244502914658 ps
CPU time 109.98 seconds
Started Aug 02 04:40:32 PM PDT 24
Finished Aug 02 04:42:22 PM PDT 24
Peak memory 191512 kb
Host smart-13145b5e-37e6-4ac0-8d3e-d8023cf0fa77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297597152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.297597152
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.2404673667
Short name T184
Test name
Test status
Simulation time 2165867209673 ps
CPU time 921.95 seconds
Started Aug 02 04:40:20 PM PDT 24
Finished Aug 02 04:55:42 PM PDT 24
Peak memory 191512 kb
Host smart-89de765d-433a-4414-be45-bff37fee83a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404673667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.2404673667
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.1760786084
Short name T201
Test name
Test status
Simulation time 207642246761 ps
CPU time 116.83 seconds
Started Aug 02 04:40:14 PM PDT 24
Finished Aug 02 04:42:11 PM PDT 24
Peak memory 191564 kb
Host smart-b657a96c-c30d-4b0e-9864-5e16f5004aad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760786084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.1760786084
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.3989768252
Short name T351
Test name
Test status
Simulation time 92649357458 ps
CPU time 278.62 seconds
Started Aug 02 04:39:34 PM PDT 24
Finished Aug 02 04:44:13 PM PDT 24
Peak memory 191536 kb
Host smart-556d4b5a-0cbc-4253-83c2-45e533dbc97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989768252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.3989768252
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.3770330754
Short name T73
Test name
Test status
Simulation time 402184595749 ps
CPU time 959.44 seconds
Started Aug 02 04:39:47 PM PDT 24
Finished Aug 02 04:55:46 PM PDT 24
Peak memory 196208 kb
Host smart-38b35f18-8c32-4d52-9719-0d0d0c277054
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770330754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.3770330754
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/131.rv_timer_random.2729512111
Short name T258
Test name
Test status
Simulation time 71208356012 ps
CPU time 471.42 seconds
Started Aug 02 04:40:50 PM PDT 24
Finished Aug 02 04:48:42 PM PDT 24
Peak memory 191416 kb
Host smart-1fd4ded5-70fc-4f7e-b1bb-d4f8127607f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729512111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.2729512111
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.2277405074
Short name T137
Test name
Test status
Simulation time 488040955167 ps
CPU time 266.65 seconds
Started Aug 02 04:40:27 PM PDT 24
Finished Aug 02 04:44:54 PM PDT 24
Peak memory 191476 kb
Host smart-5703d749-2667-4b45-8d2b-3c4f53eada9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277405074 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.2277405074
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random.3023343431
Short name T321
Test name
Test status
Simulation time 702907547274 ps
CPU time 581.92 seconds
Started Aug 02 04:39:37 PM PDT 24
Finished Aug 02 04:49:19 PM PDT 24
Peak memory 191548 kb
Host smart-15254955-4179-4708-9e17-cc324c0ae859
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023343431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.3023343431
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.2650377683
Short name T304
Test name
Test status
Simulation time 39096879243 ps
CPU time 83.32 seconds
Started Aug 02 04:40:28 PM PDT 24
Finished Aug 02 04:41:51 PM PDT 24
Peak memory 183276 kb
Host smart-95026108-be2b-4d43-9662-4915fa1e49ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650377683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.2650377683
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/160.rv_timer_random.893446948
Short name T212
Test name
Test status
Simulation time 74895777679 ps
CPU time 110.01 seconds
Started Aug 02 04:40:27 PM PDT 24
Finished Aug 02 04:42:17 PM PDT 24
Peak memory 191448 kb
Host smart-1ee6eb7f-01e1-4d67-8301-cf75d9994d2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893446948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.893446948
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.3580750802
Short name T178
Test name
Test status
Simulation time 13117368553 ps
CPU time 94.9 seconds
Started Aug 02 04:40:37 PM PDT 24
Finished Aug 02 04:42:12 PM PDT 24
Peak memory 183260 kb
Host smart-d1ba3c13-aaf1-49f0-a064-f12bf61c8cfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580750802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.3580750802
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.479799655
Short name T216
Test name
Test status
Simulation time 42739626175 ps
CPU time 624.86 seconds
Started Aug 02 04:40:28 PM PDT 24
Finished Aug 02 04:50:53 PM PDT 24
Peak memory 191572 kb
Host smart-67a6dee5-4973-465c-b8a3-c567992aa688
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479799655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.479799655
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.3180071230
Short name T7
Test name
Test status
Simulation time 347142280604 ps
CPU time 415.02 seconds
Started Aug 02 04:40:28 PM PDT 24
Finished Aug 02 04:47:24 PM PDT 24
Peak memory 194736 kb
Host smart-7777847c-bf26-4bb2-84c3-5a48b3b4f4a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180071230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.3180071230
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random.3005481294
Short name T236
Test name
Test status
Simulation time 53369401056 ps
CPU time 45.53 seconds
Started Aug 02 04:39:51 PM PDT 24
Finished Aug 02 04:40:37 PM PDT 24
Peak memory 191476 kb
Host smart-ffd52190-9894-4123-8438-65e3cac0dc82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005481294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.3005481294
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.1120959916
Short name T308
Test name
Test status
Simulation time 628359898300 ps
CPU time 782.97 seconds
Started Aug 02 04:40:30 PM PDT 24
Finished Aug 02 04:53:33 PM PDT 24
Peak memory 191508 kb
Host smart-8602fb50-798f-411f-9804-6702c97cc54a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120959916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.1120959916
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.1721528309
Short name T245
Test name
Test status
Simulation time 1771901355085 ps
CPU time 897.22 seconds
Started Aug 02 04:39:56 PM PDT 24
Finished Aug 02 04:54:54 PM PDT 24
Peak memory 195988 kb
Host smart-49723310-fb3f-4075-b37a-b9f6cee49af5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721528309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.1721528309
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_random.175738815
Short name T141
Test name
Test status
Simulation time 626933215008 ps
CPU time 680.24 seconds
Started Aug 02 04:40:02 PM PDT 24
Finished Aug 02 04:51:23 PM PDT 24
Peak memory 191504 kb
Host smart-7ff44e24-24ee-47fb-a048-7653c542b9ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175738815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.175738815
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.241920320
Short name T342
Test name
Test status
Simulation time 301857009771 ps
CPU time 127.81 seconds
Started Aug 02 04:39:58 PM PDT 24
Finished Aug 02 04:42:05 PM PDT 24
Peak memory 183384 kb
Host smart-b6fd9460-2533-4e73-a2ac-58024622942c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241920320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.rv_timer_cfg_update_on_fly.241920320
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.776742113
Short name T90
Test name
Test status
Simulation time 194488109414 ps
CPU time 302.97 seconds
Started Aug 02 04:39:53 PM PDT 24
Finished Aug 02 04:44:56 PM PDT 24
Peak memory 183304 kb
Host smart-7f9c6821-491b-4134-9a51-20b0f1b430d3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776742113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.rv_timer_cfg_update_on_fly.776742113
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.386158578
Short name T64
Test name
Test status
Simulation time 6318025016769 ps
CPU time 2306.21 seconds
Started Aug 02 04:39:46 PM PDT 24
Finished Aug 02 05:18:13 PM PDT 24
Peak memory 191672 kb
Host smart-1283ff7f-9331-4630-a9a2-8d549a813f83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386158578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all.
386158578
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.3673339213
Short name T65
Test name
Test status
Simulation time 175865931343 ps
CPU time 439.69 seconds
Started Aug 02 04:40:15 PM PDT 24
Finished Aug 02 04:47:35 PM PDT 24
Peak memory 183308 kb
Host smart-39af7fd1-9ad8-42da-b6f4-67b665267bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673339213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.3673339213
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.1467026159
Short name T292
Test name
Test status
Simulation time 66173861236 ps
CPU time 234.3 seconds
Started Aug 02 04:40:07 PM PDT 24
Finished Aug 02 04:44:01 PM PDT 24
Peak memory 191508 kb
Host smart-3588df1c-7d87-452f-a39c-a2bfbe700c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467026159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.1467026159
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_random.406266484
Short name T268
Test name
Test status
Simulation time 81716621286 ps
CPU time 287.94 seconds
Started Aug 02 04:40:00 PM PDT 24
Finished Aug 02 04:44:48 PM PDT 24
Peak memory 191504 kb
Host smart-895405cc-dba3-4bca-99b7-9ff8adfe23ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406266484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.406266484
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.1924581900
Short name T316
Test name
Test status
Simulation time 1241075028228 ps
CPU time 378.55 seconds
Started Aug 02 04:39:45 PM PDT 24
Finished Aug 02 04:46:04 PM PDT 24
Peak memory 183304 kb
Host smart-6ba9ceb4-54b6-4a65-857c-3e2ae9d30866
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924581900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.1924581900
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.1017090681
Short name T138
Test name
Test status
Simulation time 1729468888433 ps
CPU time 712.56 seconds
Started Aug 02 04:40:17 PM PDT 24
Finished Aug 02 04:52:09 PM PDT 24
Peak memory 183296 kb
Host smart-5b77f340-1617-4fec-a254-b5bdae78602a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017090681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.1017090681
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.2428734612
Short name T313
Test name
Test status
Simulation time 128458924052 ps
CPU time 306.59 seconds
Started Aug 02 04:40:21 PM PDT 24
Finished Aug 02 04:45:28 PM PDT 24
Peak memory 195192 kb
Host smart-2dd235e1-81b6-4ca9-a246-bc2ed000300a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428734612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.2428734612
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_random.872382522
Short name T123
Test name
Test status
Simulation time 344971253250 ps
CPU time 239.52 seconds
Started Aug 02 04:40:17 PM PDT 24
Finished Aug 02 04:44:17 PM PDT 24
Peak memory 191524 kb
Host smart-e825e215-6575-45d5-a795-8dc70609ae8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872382522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.872382522
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.1075662670
Short name T266
Test name
Test status
Simulation time 434330325175 ps
CPU time 597.34 seconds
Started Aug 02 04:40:08 PM PDT 24
Finished Aug 02 04:50:05 PM PDT 24
Peak memory 183280 kb
Host smart-e8169667-3b9b-4695-8832-1b92358c3d45
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075662670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.1075662670
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_random.1609563589
Short name T78
Test name
Test status
Simulation time 93721038555 ps
CPU time 328.08 seconds
Started Aug 02 04:40:17 PM PDT 24
Finished Aug 02 04:45:45 PM PDT 24
Peak memory 191540 kb
Host smart-d1fe622e-1218-4b02-bea2-0db24155f888
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609563589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.1609563589
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.2203112180
Short name T53
Test name
Test status
Simulation time 106779129 ps
CPU time 0.71 seconds
Started Aug 02 04:38:56 PM PDT 24
Finished Aug 02 04:38:57 PM PDT 24
Peak memory 191976 kb
Host smart-b8e187b6-2d76-4157-8266-6ebbfc1fc9b9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203112180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.2203112180
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.862086241
Short name T55
Test name
Test status
Simulation time 275525422 ps
CPU time 2.6 seconds
Started Aug 02 04:38:56 PM PDT 24
Finished Aug 02 04:38:59 PM PDT 24
Peak memory 192128 kb
Host smart-8d93cb34-cffa-49ea-ab11-35810471b89e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862086241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_b
ash.862086241
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.4264050128
Short name T567
Test name
Test status
Simulation time 51176078 ps
CPU time 0.56 seconds
Started Aug 02 04:38:52 PM PDT 24
Finished Aug 02 04:38:53 PM PDT 24
Peak memory 182708 kb
Host smart-1c6423aa-865f-4d04-ba8c-5883215f0484
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264050128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.4264050128
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.2160562580
Short name T565
Test name
Test status
Simulation time 65830718 ps
CPU time 0.84 seconds
Started Aug 02 04:38:58 PM PDT 24
Finished Aug 02 04:38:59 PM PDT 24
Peak memory 197136 kb
Host smart-efa813fa-964f-4927-8928-ebf42de6e1c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160562580 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.2160562580
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.1833217652
Short name T460
Test name
Test status
Simulation time 80346908 ps
CPU time 0.61 seconds
Started Aug 02 04:38:56 PM PDT 24
Finished Aug 02 04:38:57 PM PDT 24
Peak memory 182772 kb
Host smart-967f0c83-3db3-4b16-b366-cb30bb5d6cb1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833217652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.1833217652
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.4167535477
Short name T491
Test name
Test status
Simulation time 18748105 ps
CPU time 0.53 seconds
Started Aug 02 04:38:59 PM PDT 24
Finished Aug 02 04:38:59 PM PDT 24
Peak memory 182488 kb
Host smart-98e36164-de9f-4709-9eb2-bb9dab6daa4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167535477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.4167535477
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.582417172
Short name T578
Test name
Test status
Simulation time 27994472 ps
CPU time 0.73 seconds
Started Aug 02 04:38:56 PM PDT 24
Finished Aug 02 04:38:57 PM PDT 24
Peak memory 192348 kb
Host smart-46cd2104-13e7-431f-b920-467ee018c0bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582417172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_tim
er_same_csr_outstanding.582417172
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.1558873451
Short name T513
Test name
Test status
Simulation time 1128243768 ps
CPU time 2.02 seconds
Started Aug 02 04:38:59 PM PDT 24
Finished Aug 02 04:39:01 PM PDT 24
Peak memory 197432 kb
Host smart-14d24b13-e954-4123-8d97-051b4eab8ac6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558873451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.1558873451
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.780276066
Short name T568
Test name
Test status
Simulation time 354092602 ps
CPU time 1.12 seconds
Started Aug 02 04:38:56 PM PDT 24
Finished Aug 02 04:38:57 PM PDT 24
Peak memory 195116 kb
Host smart-6cc14d42-845d-4bf8-8c1e-9aa6b9ffa546
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780276066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_int
g_err.780276066
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.4240665140
Short name T502
Test name
Test status
Simulation time 564436367 ps
CPU time 3.38 seconds
Started Aug 02 04:38:52 PM PDT 24
Finished Aug 02 04:38:56 PM PDT 24
Peak memory 192900 kb
Host smart-70244442-5dcf-436f-9e0c-c68140cef80b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240665140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.4240665140
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.2582902540
Short name T107
Test name
Test status
Simulation time 17780651 ps
CPU time 0.58 seconds
Started Aug 02 04:38:59 PM PDT 24
Finished Aug 02 04:38:59 PM PDT 24
Peak memory 182676 kb
Host smart-8f49cbd6-8f3d-4790-a19a-d5135a8dba31
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582902540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.2582902540
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.3782524285
Short name T525
Test name
Test status
Simulation time 21336434 ps
CPU time 1.04 seconds
Started Aug 02 04:39:04 PM PDT 24
Finished Aug 02 04:39:05 PM PDT 24
Peak memory 197364 kb
Host smart-18640c2c-bf34-482a-a855-3c63b2b3dabf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782524285 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.3782524285
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.1496013122
Short name T105
Test name
Test status
Simulation time 25278342 ps
CPU time 0.59 seconds
Started Aug 02 04:38:54 PM PDT 24
Finished Aug 02 04:38:55 PM PDT 24
Peak memory 182728 kb
Host smart-09acd218-212d-4c9e-8f08-ad5d6cc52a68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496013122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.1496013122
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.406054768
Short name T546
Test name
Test status
Simulation time 165891132 ps
CPU time 0.52 seconds
Started Aug 02 04:38:50 PM PDT 24
Finished Aug 02 04:38:50 PM PDT 24
Peak memory 181348 kb
Host smart-7cb889a5-577a-44c6-bbe7-a472dd9675ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406054768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.406054768
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.4281767235
Short name T554
Test name
Test status
Simulation time 75916695 ps
CPU time 1.41 seconds
Started Aug 02 04:39:00 PM PDT 24
Finished Aug 02 04:39:01 PM PDT 24
Peak memory 197476 kb
Host smart-cb4d548e-f228-4228-9bd9-24b88b958aa3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281767235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.4281767235
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.3971216495
Short name T521
Test name
Test status
Simulation time 60288830 ps
CPU time 1.36 seconds
Started Aug 02 04:39:12 PM PDT 24
Finished Aug 02 04:39:13 PM PDT 24
Peak memory 197512 kb
Host smart-f6a0caae-eec5-4913-a848-3c5e83d74f1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971216495 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.3971216495
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.3330603751
Short name T504
Test name
Test status
Simulation time 13749524 ps
CPU time 0.58 seconds
Started Aug 02 04:39:10 PM PDT 24
Finished Aug 02 04:39:10 PM PDT 24
Peak memory 182720 kb
Host smart-ac7f70fc-5d1a-4156-b829-053f62515f23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330603751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.3330603751
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.3265254907
Short name T496
Test name
Test status
Simulation time 41075718 ps
CPU time 0.56 seconds
Started Aug 02 04:39:21 PM PDT 24
Finished Aug 02 04:39:21 PM PDT 24
Peak memory 182560 kb
Host smart-b55b8d2c-3753-49d5-a450-78a94f988115
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265254907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.3265254907
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.1409882746
Short name T532
Test name
Test status
Simulation time 56718838 ps
CPU time 0.75 seconds
Started Aug 02 04:39:12 PM PDT 24
Finished Aug 02 04:39:13 PM PDT 24
Peak memory 191740 kb
Host smart-5dd9f694-70a0-4b81-94d6-bafd382f32db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409882746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.1409882746
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1755698270
Short name T469
Test name
Test status
Simulation time 217318213 ps
CPU time 2.65 seconds
Started Aug 02 04:39:27 PM PDT 24
Finished Aug 02 04:39:29 PM PDT 24
Peak memory 197444 kb
Host smart-c7c28b81-4463-4167-b79d-b3ee1436726e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755698270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.1755698270
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.2246286033
Short name T458
Test name
Test status
Simulation time 77128112 ps
CPU time 0.97 seconds
Started Aug 02 04:39:12 PM PDT 24
Finished Aug 02 04:39:13 PM PDT 24
Peak memory 197092 kb
Host smart-bd6e1b15-02c7-4d09-bbde-502414b66da6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246286033 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.2246286033
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.1298264556
Short name T507
Test name
Test status
Simulation time 25212516 ps
CPU time 0.58 seconds
Started Aug 02 04:39:27 PM PDT 24
Finished Aug 02 04:39:27 PM PDT 24
Peak memory 182720 kb
Host smart-4fb0d012-48bc-4369-a228-13bf07631b02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298264556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.1298264556
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.3020872317
Short name T556
Test name
Test status
Simulation time 34622689 ps
CPU time 0.5 seconds
Started Aug 02 04:39:07 PM PDT 24
Finished Aug 02 04:39:08 PM PDT 24
Peak memory 182076 kb
Host smart-64c28ca2-4bbf-43c7-b60a-522d58ba5520
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020872317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.3020872317
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.2242618979
Short name T112
Test name
Test status
Simulation time 15430226 ps
CPU time 0.66 seconds
Started Aug 02 04:39:31 PM PDT 24
Finished Aug 02 04:39:32 PM PDT 24
Peak memory 192164 kb
Host smart-d8c5e9d1-fe3a-42c0-b3dd-9f3594fefd00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242618979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.2242618979
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.1767310030
Short name T555
Test name
Test status
Simulation time 86257844 ps
CPU time 1.81 seconds
Started Aug 02 04:39:13 PM PDT 24
Finished Aug 02 04:39:15 PM PDT 24
Peak memory 197652 kb
Host smart-708fb0e2-3f22-47a7-8ad6-3a92fbb94210
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767310030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.1767310030
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3341401126
Short name T571
Test name
Test status
Simulation time 654262682 ps
CPU time 1.37 seconds
Started Aug 02 04:39:12 PM PDT 24
Finished Aug 02 04:39:14 PM PDT 24
Peak memory 183444 kb
Host smart-a2116b35-a232-4954-acc8-3d3613643483
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341401126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.3341401126
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.1943681340
Short name T538
Test name
Test status
Simulation time 21612080 ps
CPU time 0.66 seconds
Started Aug 02 04:39:23 PM PDT 24
Finished Aug 02 04:39:24 PM PDT 24
Peak memory 194048 kb
Host smart-ec700884-a953-479e-bb7f-9c0caa4c5341
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943681340 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.1943681340
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.4220206012
Short name T563
Test name
Test status
Simulation time 15991275 ps
CPU time 0.6 seconds
Started Aug 02 04:39:14 PM PDT 24
Finished Aug 02 04:39:15 PM PDT 24
Peak memory 182652 kb
Host smart-51c29bbe-39f9-473b-9ab1-b81743c8f52b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220206012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.4220206012
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.4204124245
Short name T457
Test name
Test status
Simulation time 22287618 ps
CPU time 0.56 seconds
Started Aug 02 04:39:23 PM PDT 24
Finished Aug 02 04:39:24 PM PDT 24
Peak memory 182568 kb
Host smart-c4ed6cfd-53a8-4ab1-81ee-4a5ebd195155
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204124245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.4204124245
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.173929155
Short name T511
Test name
Test status
Simulation time 23174999 ps
CPU time 0.6 seconds
Started Aug 02 04:39:14 PM PDT 24
Finished Aug 02 04:39:15 PM PDT 24
Peak memory 192092 kb
Host smart-fa9a0295-89ed-4fc1-baae-98e545fe4f34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173929155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_ti
mer_same_csr_outstanding.173929155
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.1980908735
Short name T57
Test name
Test status
Simulation time 267658837 ps
CPU time 1.28 seconds
Started Aug 02 04:39:15 PM PDT 24
Finished Aug 02 04:39:16 PM PDT 24
Peak memory 195376 kb
Host smart-430bf2f4-1c09-4ac0-a950-79cc46fdc139
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980908735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.1980908735
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.3511023249
Short name T524
Test name
Test status
Simulation time 191781269 ps
CPU time 1.37 seconds
Started Aug 02 04:39:11 PM PDT 24
Finished Aug 02 04:39:12 PM PDT 24
Peak memory 195328 kb
Host smart-2cb9115b-bad5-4840-bfeb-8c9918827959
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511023249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.3511023249
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.272624667
Short name T476
Test name
Test status
Simulation time 19942748 ps
CPU time 0.86 seconds
Started Aug 02 04:39:09 PM PDT 24
Finished Aug 02 04:39:10 PM PDT 24
Peak memory 197224 kb
Host smart-a8e02e7b-5b04-492a-99d6-f2ee7bd33375
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272624667 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.272624667
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.22119288
Short name T536
Test name
Test status
Simulation time 14935022 ps
CPU time 0.54 seconds
Started Aug 02 04:39:28 PM PDT 24
Finished Aug 02 04:39:29 PM PDT 24
Peak memory 182756 kb
Host smart-fda9885a-2051-46fd-9988-5d3bd6d745de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22119288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.22119288
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.2728498984
Short name T485
Test name
Test status
Simulation time 49230248 ps
CPU time 0.54 seconds
Started Aug 02 04:39:21 PM PDT 24
Finished Aug 02 04:39:22 PM PDT 24
Peak memory 182720 kb
Host smart-1e9fd4e2-8383-4206-bfe4-cefc0a508430
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728498984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.2728498984
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.2910381159
Short name T577
Test name
Test status
Simulation time 143931385 ps
CPU time 0.78 seconds
Started Aug 02 04:39:10 PM PDT 24
Finished Aug 02 04:39:11 PM PDT 24
Peak memory 191732 kb
Host smart-bae16bb8-5163-477f-ac26-e7608c10411e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910381159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.2910381159
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.934514871
Short name T456
Test name
Test status
Simulation time 51226032 ps
CPU time 2.4 seconds
Started Aug 02 04:39:13 PM PDT 24
Finished Aug 02 04:39:15 PM PDT 24
Peak memory 197532 kb
Host smart-2f987d5f-de64-4359-a0be-c66de0790cbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934514871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.934514871
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.2919969871
Short name T494
Test name
Test status
Simulation time 135475057 ps
CPU time 0.82 seconds
Started Aug 02 04:39:32 PM PDT 24
Finished Aug 02 04:39:33 PM PDT 24
Peak memory 183296 kb
Host smart-965aab9e-5544-4cf0-ba12-b922e52ffb50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919969871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.2919969871
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.2382170901
Short name T58
Test name
Test status
Simulation time 118684881 ps
CPU time 0.85 seconds
Started Aug 02 04:39:10 PM PDT 24
Finished Aug 02 04:39:11 PM PDT 24
Peak memory 196752 kb
Host smart-79ba2108-f68b-4bef-878a-1df9935c51fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382170901 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.2382170901
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.4271811919
Short name T545
Test name
Test status
Simulation time 15375962 ps
CPU time 0.59 seconds
Started Aug 02 04:39:37 PM PDT 24
Finished Aug 02 04:39:37 PM PDT 24
Peak memory 182820 kb
Host smart-26a004d0-9e1f-4878-b6be-b2102fab8a80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271811919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.4271811919
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.269815361
Short name T573
Test name
Test status
Simulation time 27186268 ps
CPU time 0.57 seconds
Started Aug 02 04:39:13 PM PDT 24
Finished Aug 02 04:39:14 PM PDT 24
Peak memory 182516 kb
Host smart-f0a8215a-0beb-42a6-b723-b6f3e9c42acb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269815361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.269815361
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.2458403264
Short name T110
Test name
Test status
Simulation time 97515590 ps
CPU time 0.62 seconds
Started Aug 02 04:39:12 PM PDT 24
Finished Aug 02 04:39:13 PM PDT 24
Peak memory 191568 kb
Host smart-64e9ab72-35c3-4adc-aebf-d56bfb1380ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458403264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.2458403264
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2174328607
Short name T505
Test name
Test status
Simulation time 68443369 ps
CPU time 0.98 seconds
Started Aug 02 04:39:28 PM PDT 24
Finished Aug 02 04:39:29 PM PDT 24
Peak memory 197096 kb
Host smart-7a77442b-9f5c-48b0-82cd-01bbd4260f68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174328607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.2174328607
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.101508520
Short name T117
Test name
Test status
Simulation time 325902299 ps
CPU time 1.1 seconds
Started Aug 02 04:39:10 PM PDT 24
Finished Aug 02 04:39:11 PM PDT 24
Peak memory 195120 kb
Host smart-a7434d96-80b6-45b4-9f9a-d9c4cf62324f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101508520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_in
tg_err.101508520
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.3450353198
Short name T477
Test name
Test status
Simulation time 19417572 ps
CPU time 0.7 seconds
Started Aug 02 04:39:33 PM PDT 24
Finished Aug 02 04:39:34 PM PDT 24
Peak memory 194676 kb
Host smart-4ba1065b-5e83-4777-af81-0da5ab07707a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450353198 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.3450353198
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.4159538279
Short name T95
Test name
Test status
Simulation time 45087400 ps
CPU time 0.6 seconds
Started Aug 02 04:39:10 PM PDT 24
Finished Aug 02 04:39:11 PM PDT 24
Peak memory 182796 kb
Host smart-3a36a827-c472-4de0-a718-e3ffa06ae45f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159538279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.4159538279
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.1718519362
Short name T517
Test name
Test status
Simulation time 14624003 ps
CPU time 0.58 seconds
Started Aug 02 04:39:32 PM PDT 24
Finished Aug 02 04:39:33 PM PDT 24
Peak memory 182584 kb
Host smart-04e99687-c0c2-4a0f-a3ac-e6f92a9bfd52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718519362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.1718519362
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.1493731519
Short name T111
Test name
Test status
Simulation time 108015135 ps
CPU time 0.71 seconds
Started Aug 02 04:39:11 PM PDT 24
Finished Aug 02 04:39:11 PM PDT 24
Peak memory 191748 kb
Host smart-645d5b45-8aaf-48d4-b81b-354cf820bea7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493731519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.1493731519
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.2881124931
Short name T529
Test name
Test status
Simulation time 165338258 ps
CPU time 2.77 seconds
Started Aug 02 04:39:11 PM PDT 24
Finished Aug 02 04:39:14 PM PDT 24
Peak memory 197568 kb
Host smart-69854876-43c2-4cc5-bdab-dbb488c57e02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881124931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.2881124931
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3150660554
Short name T116
Test name
Test status
Simulation time 616017710 ps
CPU time 1.33 seconds
Started Aug 02 04:39:14 PM PDT 24
Finished Aug 02 04:39:15 PM PDT 24
Peak memory 194460 kb
Host smart-6ae80201-c2ef-4b1e-a58c-8a88163917ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150660554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.3150660554
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.3238894267
Short name T56
Test name
Test status
Simulation time 51311621 ps
CPU time 0.71 seconds
Started Aug 02 04:40:33 PM PDT 24
Finished Aug 02 04:40:34 PM PDT 24
Peak memory 195080 kb
Host smart-28b6507a-8728-449d-b41a-cff6482b8fed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238894267 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.3238894267
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.1902516383
Short name T97
Test name
Test status
Simulation time 17148949 ps
CPU time 0.55 seconds
Started Aug 02 04:39:30 PM PDT 24
Finished Aug 02 04:39:30 PM PDT 24
Peak memory 182768 kb
Host smart-985bd481-36de-4f44-aa2e-ab7ad17306be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902516383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.1902516383
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.4272242930
Short name T478
Test name
Test status
Simulation time 30491893 ps
CPU time 0.57 seconds
Started Aug 02 04:39:10 PM PDT 24
Finished Aug 02 04:39:11 PM PDT 24
Peak memory 182564 kb
Host smart-d291da0e-8ea7-4832-bfa0-0e7aff0b52e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272242930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.4272242930
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1286381899
Short name T34
Test name
Test status
Simulation time 52733166 ps
CPU time 0.71 seconds
Started Aug 02 04:39:13 PM PDT 24
Finished Aug 02 04:39:14 PM PDT 24
Peak memory 191740 kb
Host smart-9a82626d-c10e-4462-ba47-78e610d6e36d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286381899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.1286381899
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.1919929544
Short name T499
Test name
Test status
Simulation time 125380930 ps
CPU time 2.29 seconds
Started Aug 02 04:39:09 PM PDT 24
Finished Aug 02 04:39:11 PM PDT 24
Peak memory 197500 kb
Host smart-97dd9cf7-8870-4480-9abb-83097ef674e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919929544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.1919929544
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.122706768
Short name T580
Test name
Test status
Simulation time 211311392 ps
CPU time 1.34 seconds
Started Aug 02 04:39:29 PM PDT 24
Finished Aug 02 04:39:30 PM PDT 24
Peak memory 195592 kb
Host smart-5b242e29-97b7-4117-a647-69a6194a588f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122706768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_in
tg_err.122706768
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3459748160
Short name T510
Test name
Test status
Simulation time 29354388 ps
CPU time 0.82 seconds
Started Aug 02 04:40:19 PM PDT 24
Finished Aug 02 04:40:21 PM PDT 24
Peak memory 195284 kb
Host smart-3c69a02c-07e4-425c-aaec-a0f5b3c8971a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459748160 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.3459748160
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.4160729169
Short name T550
Test name
Test status
Simulation time 173672182 ps
CPU time 0.6 seconds
Started Aug 02 04:40:36 PM PDT 24
Finished Aug 02 04:40:37 PM PDT 24
Peak memory 182708 kb
Host smart-b07c73f0-ffae-44dd-9f3e-f5e230b43ddf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160729169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.4160729169
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.4091273134
Short name T562
Test name
Test status
Simulation time 24686441 ps
CPU time 0.56 seconds
Started Aug 02 04:40:38 PM PDT 24
Finished Aug 02 04:40:39 PM PDT 24
Peak memory 182520 kb
Host smart-9da5d9dc-5f8d-4f2d-8dc6-7eaaae58d1ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091273134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.4091273134
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.1030612986
Short name T539
Test name
Test status
Simulation time 67373828 ps
CPU time 0.7 seconds
Started Aug 02 04:40:34 PM PDT 24
Finished Aug 02 04:40:34 PM PDT 24
Peak memory 191660 kb
Host smart-dc8dfdb6-7f70-4f0b-a77c-3f9a4c013c98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030612986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.1030612986
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.1824281217
Short name T467
Test name
Test status
Simulation time 53494505 ps
CPU time 1.42 seconds
Started Aug 02 04:39:14 PM PDT 24
Finished Aug 02 04:39:15 PM PDT 24
Peak memory 196252 kb
Host smart-233314a2-4db9-484c-a11d-21f24c799900
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824281217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.1824281217
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.980324869
Short name T33
Test name
Test status
Simulation time 362432757 ps
CPU time 1.49 seconds
Started Aug 02 04:39:14 PM PDT 24
Finished Aug 02 04:39:15 PM PDT 24
Peak memory 183236 kb
Host smart-f5031e00-2bde-4c52-85d0-5c073427f3cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980324869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_in
tg_err.980324869
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3665218014
Short name T462
Test name
Test status
Simulation time 36231336 ps
CPU time 0.7 seconds
Started Aug 02 04:39:47 PM PDT 24
Finished Aug 02 04:39:47 PM PDT 24
Peak memory 194976 kb
Host smart-2438c949-7fad-4d08-9c2a-bfe44b542788
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665218014 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.3665218014
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.431990550
Short name T543
Test name
Test status
Simulation time 98000446 ps
CPU time 0.57 seconds
Started Aug 02 04:39:22 PM PDT 24
Finished Aug 02 04:39:23 PM PDT 24
Peak memory 182716 kb
Host smart-f2e22dcc-8a99-4766-a494-e12c5bac6d6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431990550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.431990550
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.2961664083
Short name T575
Test name
Test status
Simulation time 14921927 ps
CPU time 0.58 seconds
Started Aug 02 04:39:21 PM PDT 24
Finished Aug 02 04:39:22 PM PDT 24
Peak memory 182468 kb
Host smart-e6f91eed-e6a1-4207-a6f6-40e114c9700e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961664083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.2961664083
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1138025315
Short name T99
Test name
Test status
Simulation time 163901128 ps
CPU time 0.86 seconds
Started Aug 02 04:39:23 PM PDT 24
Finished Aug 02 04:39:24 PM PDT 24
Peak memory 191696 kb
Host smart-5fae5940-d5ac-4a62-8a98-1642462078ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138025315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.1138025315
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.2965582544
Short name T493
Test name
Test status
Simulation time 29046206 ps
CPU time 1.19 seconds
Started Aug 02 04:40:38 PM PDT 24
Finished Aug 02 04:40:39 PM PDT 24
Peak memory 197440 kb
Host smart-a50764a6-5d10-4bd4-884c-55396656f109
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965582544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.2965582544
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1656643327
Short name T527
Test name
Test status
Simulation time 145647074 ps
CPU time 0.81 seconds
Started Aug 02 04:39:43 PM PDT 24
Finished Aug 02 04:39:44 PM PDT 24
Peak memory 193244 kb
Host smart-21c19e94-4149-4782-ac4a-0a26c3c9b2fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656643327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.1656643327
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.2645932357
Short name T547
Test name
Test status
Simulation time 44278849 ps
CPU time 1 seconds
Started Aug 02 04:39:46 PM PDT 24
Finished Aug 02 04:39:48 PM PDT 24
Peak memory 197272 kb
Host smart-ccaa36f6-54c1-47d5-9f05-c3de568fb26d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645932357 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.2645932357
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.2789467550
Short name T96
Test name
Test status
Simulation time 51341487 ps
CPU time 0.58 seconds
Started Aug 02 04:39:39 PM PDT 24
Finished Aug 02 04:39:39 PM PDT 24
Peak memory 182964 kb
Host smart-9c88178b-8994-45ca-a511-4fc92053c552
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789467550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.2789467550
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.3613659839
Short name T526
Test name
Test status
Simulation time 207445992 ps
CPU time 0.54 seconds
Started Aug 02 04:39:31 PM PDT 24
Finished Aug 02 04:39:32 PM PDT 24
Peak memory 182280 kb
Host smart-febc0ed0-5c7c-4ce1-9a19-584b719a097b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613659839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.3613659839
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.798353000
Short name T522
Test name
Test status
Simulation time 133977964 ps
CPU time 0.85 seconds
Started Aug 02 04:39:45 PM PDT 24
Finished Aug 02 04:39:46 PM PDT 24
Peak memory 193552 kb
Host smart-7c5e0d7a-502d-4aeb-95ca-f7cfa6d99be6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798353000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_ti
mer_same_csr_outstanding.798353000
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.246944612
Short name T553
Test name
Test status
Simulation time 110229773 ps
CPU time 1.3 seconds
Started Aug 02 04:39:20 PM PDT 24
Finished Aug 02 04:39:22 PM PDT 24
Peak memory 197020 kb
Host smart-febc6910-78b8-40be-8e59-b05319f4785f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246944612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.246944612
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2119807093
Short name T574
Test name
Test status
Simulation time 398601519 ps
CPU time 1.32 seconds
Started Aug 02 04:39:48 PM PDT 24
Finished Aug 02 04:39:49 PM PDT 24
Peak memory 195500 kb
Host smart-ce27515f-423d-48f6-a1f1-4eaa365daa4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119807093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.2119807093
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.1210495506
Short name T100
Test name
Test status
Simulation time 39942397 ps
CPU time 0.65 seconds
Started Aug 02 04:39:03 PM PDT 24
Finished Aug 02 04:39:04 PM PDT 24
Peak memory 182736 kb
Host smart-d3f4065d-69f2-4ecb-a2ba-2c7f4bc64ed0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210495506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.1210495506
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.3897395779
Short name T557
Test name
Test status
Simulation time 83488120 ps
CPU time 2.33 seconds
Started Aug 02 04:39:02 PM PDT 24
Finished Aug 02 04:39:05 PM PDT 24
Peak memory 193552 kb
Host smart-bed23f10-b417-4c9d-b9f3-774d4ba41d51
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897395779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.3897395779
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.1983490599
Short name T108
Test name
Test status
Simulation time 27278690 ps
CPU time 0.58 seconds
Started Aug 02 04:39:14 PM PDT 24
Finished Aug 02 04:39:15 PM PDT 24
Peak memory 182792 kb
Host smart-53c55a3d-205c-4130-9cea-72bbc6e01fde
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983490599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.1983490599
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.2038000522
Short name T490
Test name
Test status
Simulation time 52618433 ps
CPU time 0.67 seconds
Started Aug 02 04:39:04 PM PDT 24
Finished Aug 02 04:39:04 PM PDT 24
Peak memory 194712 kb
Host smart-1f3cc065-c20b-4716-9e83-fa19d4b9cbef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038000522 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.2038000522
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.3976658324
Short name T558
Test name
Test status
Simulation time 14139768 ps
CPU time 0.54 seconds
Started Aug 02 04:39:01 PM PDT 24
Finished Aug 02 04:39:02 PM PDT 24
Peak memory 182644 kb
Host smart-6a84cf6d-226a-4d32-83ff-58c7cee7b2be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976658324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.3976658324
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.4051325636
Short name T466
Test name
Test status
Simulation time 24820932 ps
CPU time 0.55 seconds
Started Aug 02 04:39:21 PM PDT 24
Finished Aug 02 04:39:22 PM PDT 24
Peak memory 182544 kb
Host smart-e097ad66-83eb-4e7f-9d37-77261646b2a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051325636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.4051325636
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.3732473702
Short name T508
Test name
Test status
Simulation time 64749646 ps
CPU time 0.63 seconds
Started Aug 02 04:39:21 PM PDT 24
Finished Aug 02 04:39:21 PM PDT 24
Peak memory 191704 kb
Host smart-1fcfd768-1aed-4e43-af0e-4131d06bc95a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732473702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.3732473702
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.4021670013
Short name T453
Test name
Test status
Simulation time 482318510 ps
CPU time 1.88 seconds
Started Aug 02 04:39:14 PM PDT 24
Finished Aug 02 04:39:16 PM PDT 24
Peak memory 197552 kb
Host smart-b4936572-39c1-45ac-bdc7-f3655c512768
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021670013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.4021670013
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.3650853047
Short name T512
Test name
Test status
Simulation time 335205115 ps
CPU time 0.83 seconds
Started Aug 02 04:39:06 PM PDT 24
Finished Aug 02 04:39:07 PM PDT 24
Peak memory 193608 kb
Host smart-2e87ba3a-dee1-4204-abd9-c325f6adb28e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650853047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.3650853047
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.4107219937
Short name T528
Test name
Test status
Simulation time 16358678 ps
CPU time 0.54 seconds
Started Aug 02 04:39:48 PM PDT 24
Finished Aug 02 04:39:48 PM PDT 24
Peak memory 182552 kb
Host smart-b1ad8bec-a46c-475d-8844-c80e0fe1569e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107219937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.4107219937
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1316182959
Short name T495
Test name
Test status
Simulation time 84932813 ps
CPU time 0.59 seconds
Started Aug 02 04:39:28 PM PDT 24
Finished Aug 02 04:39:29 PM PDT 24
Peak memory 182056 kb
Host smart-5727fd1f-44e1-4dc6-b531-864b05161aa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316182959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.1316182959
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.2730689255
Short name T454
Test name
Test status
Simulation time 13464336 ps
CPU time 0.53 seconds
Started Aug 02 04:39:33 PM PDT 24
Finished Aug 02 04:39:34 PM PDT 24
Peak memory 182548 kb
Host smart-0560c45a-8194-466b-bc6b-7d418893f10a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730689255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.2730689255
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.2317672487
Short name T472
Test name
Test status
Simulation time 21542675 ps
CPU time 0.56 seconds
Started Aug 02 04:39:38 PM PDT 24
Finished Aug 02 04:39:39 PM PDT 24
Peak memory 182528 kb
Host smart-20d07d53-f0de-4aba-8ad1-a961f66db96f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317672487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.2317672487
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2887137633
Short name T515
Test name
Test status
Simulation time 14190171 ps
CPU time 0.57 seconds
Started Aug 02 04:39:25 PM PDT 24
Finished Aug 02 04:39:26 PM PDT 24
Peak memory 182596 kb
Host smart-54268fbc-0b28-4950-96af-1ac3daaac23c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887137633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.2887137633
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.3302734839
Short name T541
Test name
Test status
Simulation time 15637487 ps
CPU time 0.54 seconds
Started Aug 02 04:39:32 PM PDT 24
Finished Aug 02 04:39:32 PM PDT 24
Peak memory 182604 kb
Host smart-d8dd02b3-6925-467a-bd7f-fbe8616c583f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302734839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.3302734839
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.2608583818
Short name T492
Test name
Test status
Simulation time 38949314 ps
CPU time 0.53 seconds
Started Aug 02 04:39:33 PM PDT 24
Finished Aug 02 04:39:34 PM PDT 24
Peak memory 182064 kb
Host smart-52446193-d419-4883-903a-538aa32e7315
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608583818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.2608583818
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.722722743
Short name T544
Test name
Test status
Simulation time 93056703 ps
CPU time 0.52 seconds
Started Aug 02 04:39:27 PM PDT 24
Finished Aug 02 04:39:28 PM PDT 24
Peak memory 182012 kb
Host smart-4bbf0ec3-cd9c-4ff3-9bb1-9f897e59773e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722722743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.722722743
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2489535602
Short name T570
Test name
Test status
Simulation time 11637113 ps
CPU time 0.61 seconds
Started Aug 02 04:39:50 PM PDT 24
Finished Aug 02 04:39:51 PM PDT 24
Peak memory 182648 kb
Host smart-73520e3b-ab97-441e-a896-fc0a8bb64433
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489535602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.2489535602
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.2646156309
Short name T470
Test name
Test status
Simulation time 136349325 ps
CPU time 0.54 seconds
Started Aug 02 04:39:28 PM PDT 24
Finished Aug 02 04:39:29 PM PDT 24
Peak memory 182256 kb
Host smart-9293b5da-dd6a-4698-a2eb-344479015807
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646156309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.2646156309
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3333287252
Short name T103
Test name
Test status
Simulation time 17477714 ps
CPU time 0.71 seconds
Started Aug 02 04:39:15 PM PDT 24
Finished Aug 02 04:39:16 PM PDT 24
Peak memory 182724 kb
Host smart-3c3391d8-e444-49d7-b92e-52cd82c41b9e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333287252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.3333287252
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.3696136813
Short name T561
Test name
Test status
Simulation time 609553075 ps
CPU time 2.45 seconds
Started Aug 02 04:39:04 PM PDT 24
Finished Aug 02 04:39:07 PM PDT 24
Peak memory 191096 kb
Host smart-e56d8ba6-5823-4749-9cd4-6691ea465a73
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696136813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.3696136813
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.4067965813
Short name T509
Test name
Test status
Simulation time 77627284 ps
CPU time 0.58 seconds
Started Aug 02 04:39:07 PM PDT 24
Finished Aug 02 04:39:07 PM PDT 24
Peak memory 182696 kb
Host smart-0ecf22ea-7f5a-4bf6-a358-f41f8d3d858b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067965813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.4067965813
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.359682112
Short name T484
Test name
Test status
Simulation time 59698043 ps
CPU time 0.92 seconds
Started Aug 02 04:39:16 PM PDT 24
Finished Aug 02 04:39:17 PM PDT 24
Peak memory 197220 kb
Host smart-62c7b948-559d-4cf8-b333-71ed67e1db56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359682112 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.359682112
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.1476551391
Short name T102
Test name
Test status
Simulation time 59267233 ps
CPU time 0.61 seconds
Started Aug 02 04:39:02 PM PDT 24
Finished Aug 02 04:39:03 PM PDT 24
Peak memory 182660 kb
Host smart-83243233-d469-4af6-be75-e7c1af08fe6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476551391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.1476551391
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.2223575999
Short name T537
Test name
Test status
Simulation time 27262019 ps
CPU time 0.55 seconds
Started Aug 02 04:39:04 PM PDT 24
Finished Aug 02 04:39:04 PM PDT 24
Peak memory 182564 kb
Host smart-cb9263ab-f565-43a4-b8c8-de35f3754368
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223575999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.2223575999
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.3706855581
Short name T35
Test name
Test status
Simulation time 97711427 ps
CPU time 0.79 seconds
Started Aug 02 04:39:16 PM PDT 24
Finished Aug 02 04:39:17 PM PDT 24
Peak memory 193624 kb
Host smart-a4fd62e1-9cb0-4bce-92fc-61d12465cfd1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706855581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.3706855581
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.1182158996
Short name T455
Test name
Test status
Simulation time 44889027 ps
CPU time 2.06 seconds
Started Aug 02 04:39:24 PM PDT 24
Finished Aug 02 04:39:26 PM PDT 24
Peak memory 197448 kb
Host smart-ae447f47-cbcf-4474-8694-f5f4c4cbc6e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182158996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.1182158996
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.2406683023
Short name T119
Test name
Test status
Simulation time 175554070 ps
CPU time 1.37 seconds
Started Aug 02 04:39:01 PM PDT 24
Finished Aug 02 04:39:03 PM PDT 24
Peak memory 195388 kb
Host smart-2d88201f-a3c1-47a7-b997-7f209b0ce7d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406683023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.2406683023
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.502704951
Short name T468
Test name
Test status
Simulation time 23959326 ps
CPU time 0.55 seconds
Started Aug 02 04:39:27 PM PDT 24
Finished Aug 02 04:39:28 PM PDT 24
Peak memory 182536 kb
Host smart-76c5ef8c-02fc-4202-adf1-2202adb7a49b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502704951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.502704951
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.3316509616
Short name T481
Test name
Test status
Simulation time 55166839 ps
CPU time 0.55 seconds
Started Aug 02 04:39:26 PM PDT 24
Finished Aug 02 04:39:26 PM PDT 24
Peak memory 182044 kb
Host smart-ab8e8607-9248-4297-af11-3d5e0483f6a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316509616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.3316509616
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.787622658
Short name T479
Test name
Test status
Simulation time 16479573 ps
CPU time 0.52 seconds
Started Aug 02 04:39:28 PM PDT 24
Finished Aug 02 04:39:29 PM PDT 24
Peak memory 182600 kb
Host smart-43ad514f-10ff-460b-9476-f7cb9abe3c97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787622658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.787622658
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.2095946834
Short name T540
Test name
Test status
Simulation time 12596374 ps
CPU time 0.56 seconds
Started Aug 02 04:39:28 PM PDT 24
Finished Aug 02 04:39:28 PM PDT 24
Peak memory 182588 kb
Host smart-c8256c01-a89d-4a50-81d5-6bcc3238ac58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095946834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.2095946834
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.2050149633
Short name T483
Test name
Test status
Simulation time 34970214 ps
CPU time 0.54 seconds
Started Aug 02 04:39:30 PM PDT 24
Finished Aug 02 04:39:31 PM PDT 24
Peak memory 182060 kb
Host smart-812cfa96-2160-4978-978b-c0736768153a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050149633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.2050149633
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.4197108136
Short name T465
Test name
Test status
Simulation time 44476542 ps
CPU time 0.58 seconds
Started Aug 02 04:39:35 PM PDT 24
Finished Aug 02 04:39:36 PM PDT 24
Peak memory 182568 kb
Host smart-8854518c-5e57-4b6d-a66f-64a88e772d5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197108136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.4197108136
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.557973764
Short name T473
Test name
Test status
Simulation time 12525459 ps
CPU time 0.57 seconds
Started Aug 02 04:39:30 PM PDT 24
Finished Aug 02 04:39:31 PM PDT 24
Peak memory 182296 kb
Host smart-f8ee37df-02c0-4b06-a4b5-e1127bd155a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557973764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.557973764
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.2660695768
Short name T452
Test name
Test status
Simulation time 27380146 ps
CPU time 0.55 seconds
Started Aug 02 04:39:23 PM PDT 24
Finished Aug 02 04:39:24 PM PDT 24
Peak memory 182628 kb
Host smart-c8153b00-4f49-4ef1-af04-fc9d109e1871
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660695768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.2660695768
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.2106602667
Short name T569
Test name
Test status
Simulation time 44686086 ps
CPU time 0.56 seconds
Started Aug 02 04:39:44 PM PDT 24
Finished Aug 02 04:39:44 PM PDT 24
Peak memory 182044 kb
Host smart-dd7cc7ae-27ce-45d7-b713-4614b90d00c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106602667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.2106602667
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.1501441375
Short name T530
Test name
Test status
Simulation time 36786320 ps
CPU time 0.52 seconds
Started Aug 02 04:39:29 PM PDT 24
Finished Aug 02 04:39:30 PM PDT 24
Peak memory 182108 kb
Host smart-20b3c133-a2c5-4d04-8508-f398748f3beb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501441375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.1501441375
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.3883781987
Short name T516
Test name
Test status
Simulation time 95234656 ps
CPU time 0.73 seconds
Started Aug 02 04:39:10 PM PDT 24
Finished Aug 02 04:39:10 PM PDT 24
Peak memory 192716 kb
Host smart-3c154624-aa55-4c40-8ba8-c487f742dde2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883781987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.3883781987
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.2100431437
Short name T566
Test name
Test status
Simulation time 62601968 ps
CPU time 2.24 seconds
Started Aug 02 04:39:14 PM PDT 24
Finished Aug 02 04:39:16 PM PDT 24
Peak memory 191308 kb
Host smart-e63dc1ed-f2ad-4032-944f-2268affcae93
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100431437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.2100431437
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.3611379985
Short name T548
Test name
Test status
Simulation time 57236930 ps
CPU time 0.56 seconds
Started Aug 02 04:39:02 PM PDT 24
Finished Aug 02 04:39:02 PM PDT 24
Peak memory 182756 kb
Host smart-52a074f8-5cc9-4589-98de-9447e01e607e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611379985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.3611379985
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.1740922609
Short name T461
Test name
Test status
Simulation time 45545987 ps
CPU time 0.83 seconds
Started Aug 02 04:39:13 PM PDT 24
Finished Aug 02 04:39:14 PM PDT 24
Peak memory 196080 kb
Host smart-7adbab3e-baf1-49c6-89e5-91e597726fa1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740922609 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.1740922609
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.3822280625
Short name T487
Test name
Test status
Simulation time 139687827 ps
CPU time 0.59 seconds
Started Aug 02 04:39:01 PM PDT 24
Finished Aug 02 04:39:02 PM PDT 24
Peak memory 182756 kb
Host smart-6aecfc1d-2e54-411b-8c3f-f9f9f2dd034f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822280625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.3822280625
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.395054106
Short name T564
Test name
Test status
Simulation time 61421471 ps
CPU time 0.61 seconds
Started Aug 02 04:39:08 PM PDT 24
Finished Aug 02 04:39:09 PM PDT 24
Peak memory 182512 kb
Host smart-1de00d9e-cdbb-49b6-9447-fa62e94c25b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395054106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.395054106
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.3370662936
Short name T531
Test name
Test status
Simulation time 40242357 ps
CPU time 0.64 seconds
Started Aug 02 04:39:05 PM PDT 24
Finished Aug 02 04:39:06 PM PDT 24
Peak memory 191736 kb
Host smart-5388f803-a1d2-479c-ba4f-2ea9eed4d2f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370662936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.3370662936
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2995635485
Short name T54
Test name
Test status
Simulation time 746886062 ps
CPU time 3.19 seconds
Started Aug 02 04:39:06 PM PDT 24
Finished Aug 02 04:39:09 PM PDT 24
Peak memory 197488 kb
Host smart-d0b8bef8-36e0-4bd1-a402-392bffb2482a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995635485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.2995635485
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.1789256056
Short name T572
Test name
Test status
Simulation time 306918634 ps
CPU time 1.15 seconds
Started Aug 02 04:39:04 PM PDT 24
Finished Aug 02 04:39:05 PM PDT 24
Peak memory 195244 kb
Host smart-df85b010-0486-454e-af61-1a1cfe68d09e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789256056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.1789256056
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.1700548555
Short name T471
Test name
Test status
Simulation time 31082536 ps
CPU time 0.53 seconds
Started Aug 02 04:39:21 PM PDT 24
Finished Aug 02 04:39:21 PM PDT 24
Peak memory 182264 kb
Host smart-294ccdcd-5ac0-4f3a-9b8a-fc173a575693
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700548555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.1700548555
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.2888943343
Short name T579
Test name
Test status
Simulation time 32500946 ps
CPU time 0.54 seconds
Started Aug 02 04:39:28 PM PDT 24
Finished Aug 02 04:39:29 PM PDT 24
Peak memory 182024 kb
Host smart-32f94bf0-e25f-4f04-b202-1368533bca71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888943343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.2888943343
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.2663071750
Short name T535
Test name
Test status
Simulation time 10260990 ps
CPU time 0.53 seconds
Started Aug 02 04:39:48 PM PDT 24
Finished Aug 02 04:39:48 PM PDT 24
Peak memory 182032 kb
Host smart-4369b146-2dab-48a8-bb4e-f247306999fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663071750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.2663071750
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.2487497449
Short name T498
Test name
Test status
Simulation time 42672450 ps
CPU time 0.55 seconds
Started Aug 02 04:39:38 PM PDT 24
Finished Aug 02 04:39:39 PM PDT 24
Peak memory 182512 kb
Host smart-d6c44930-36b0-4be2-8b8b-1f565faf5059
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487497449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.2487497449
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.428823411
Short name T480
Test name
Test status
Simulation time 19686652 ps
CPU time 0.58 seconds
Started Aug 02 04:39:20 PM PDT 24
Finished Aug 02 04:39:20 PM PDT 24
Peak memory 182536 kb
Host smart-7d66fea2-8b41-46d2-96ca-68815a95d65b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428823411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.428823411
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.4178993204
Short name T520
Test name
Test status
Simulation time 40533642 ps
CPU time 0.54 seconds
Started Aug 02 04:39:27 PM PDT 24
Finished Aug 02 04:39:33 PM PDT 24
Peak memory 182640 kb
Host smart-bf94b3d6-fae9-4123-943d-a30ec0965cff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178993204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.4178993204
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.4090998571
Short name T534
Test name
Test status
Simulation time 29639239 ps
CPU time 0.58 seconds
Started Aug 02 04:39:35 PM PDT 24
Finished Aug 02 04:39:36 PM PDT 24
Peak memory 182576 kb
Host smart-958a41ca-5725-41b2-bc1a-4d10f2fb1038
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090998571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.4090998571
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.164959754
Short name T503
Test name
Test status
Simulation time 28213383 ps
CPU time 0.58 seconds
Started Aug 02 04:39:28 PM PDT 24
Finished Aug 02 04:39:29 PM PDT 24
Peak memory 182576 kb
Host smart-f7545f98-4f31-41aa-ac1b-da691a947bef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164959754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.164959754
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.752166191
Short name T506
Test name
Test status
Simulation time 55877079 ps
CPU time 0.61 seconds
Started Aug 02 04:39:46 PM PDT 24
Finished Aug 02 04:39:47 PM PDT 24
Peak memory 182576 kb
Host smart-9f7e0fb8-4d11-47ab-91f1-f924a0372d8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752166191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.752166191
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.2388064892
Short name T464
Test name
Test status
Simulation time 11425281 ps
CPU time 0.58 seconds
Started Aug 02 04:39:26 PM PDT 24
Finished Aug 02 04:39:26 PM PDT 24
Peak memory 182556 kb
Host smart-1ac22b3a-166c-47c4-9d27-e0a915f3aa94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388064892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.2388064892
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2935076678
Short name T518
Test name
Test status
Simulation time 30511634 ps
CPU time 0.82 seconds
Started Aug 02 04:39:01 PM PDT 24
Finished Aug 02 04:39:02 PM PDT 24
Peak memory 196456 kb
Host smart-cc0e0101-ff23-45b2-848f-0a72845c0491
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935076678 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.2935076678
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.1662355019
Short name T104
Test name
Test status
Simulation time 36909655 ps
CPU time 0.62 seconds
Started Aug 02 04:39:14 PM PDT 24
Finished Aug 02 04:39:15 PM PDT 24
Peak memory 182816 kb
Host smart-fca29375-ae08-4428-8d02-02233a083b08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662355019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.1662355019
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1676117083
Short name T459
Test name
Test status
Simulation time 22310965 ps
CPU time 0.57 seconds
Started Aug 02 04:39:03 PM PDT 24
Finished Aug 02 04:39:04 PM PDT 24
Peak memory 182012 kb
Host smart-81525d05-a1aa-4c6a-ac8b-a7dc75f7b637
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676117083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.1676117083
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2969677489
Short name T36
Test name
Test status
Simulation time 34433989 ps
CPU time 0.83 seconds
Started Aug 02 04:39:16 PM PDT 24
Finished Aug 02 04:39:17 PM PDT 24
Peak memory 191720 kb
Host smart-bfaa6d41-e408-4cec-9bc7-f4bdb075ca6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969677489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.2969677489
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.2413687532
Short name T475
Test name
Test status
Simulation time 27121142 ps
CPU time 1.34 seconds
Started Aug 02 04:39:13 PM PDT 24
Finished Aug 02 04:39:14 PM PDT 24
Peak memory 197512 kb
Host smart-06b7d472-978d-46d2-80a1-63ac79544a8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413687532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.2413687532
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.909296643
Short name T115
Test name
Test status
Simulation time 418247746 ps
CPU time 1.3 seconds
Started Aug 02 04:39:12 PM PDT 24
Finished Aug 02 04:39:14 PM PDT 24
Peak memory 195228 kb
Host smart-333e26d1-90b4-4b04-b78f-9d87e33d43bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909296643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_int
g_err.909296643
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3892104436
Short name T463
Test name
Test status
Simulation time 123772401 ps
CPU time 0.89 seconds
Started Aug 02 04:39:03 PM PDT 24
Finished Aug 02 04:39:05 PM PDT 24
Peak memory 196444 kb
Host smart-9b929535-8894-4a49-99bc-eed84c4491d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892104436 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.3892104436
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1474183157
Short name T488
Test name
Test status
Simulation time 43182870 ps
CPU time 0.58 seconds
Started Aug 02 04:39:12 PM PDT 24
Finished Aug 02 04:39:12 PM PDT 24
Peak memory 182780 kb
Host smart-d57fb6b3-bd50-4051-bf26-448260b0a815
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474183157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.1474183157
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.301306152
Short name T559
Test name
Test status
Simulation time 55914049 ps
CPU time 0.53 seconds
Started Aug 02 04:39:29 PM PDT 24
Finished Aug 02 04:39:30 PM PDT 24
Peak memory 182044 kb
Host smart-013f5ea5-69e0-4c6c-af71-04daa6322f7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301306152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.301306152
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.3228238069
Short name T113
Test name
Test status
Simulation time 62423902 ps
CPU time 0.69 seconds
Started Aug 02 04:39:04 PM PDT 24
Finished Aug 02 04:39:05 PM PDT 24
Peak memory 193048 kb
Host smart-6a610b65-d26f-48de-80a1-422a3ef9da88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228238069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.3228238069
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.680409802
Short name T501
Test name
Test status
Simulation time 193557505 ps
CPU time 1.98 seconds
Started Aug 02 04:39:01 PM PDT 24
Finished Aug 02 04:39:03 PM PDT 24
Peak memory 197460 kb
Host smart-d184209f-8338-48af-80f1-ef117a517bdf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680409802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.680409802
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.2866492072
Short name T32
Test name
Test status
Simulation time 227582441 ps
CPU time 1.35 seconds
Started Aug 02 04:39:02 PM PDT 24
Finished Aug 02 04:39:04 PM PDT 24
Peak memory 195308 kb
Host smart-109d118a-14d7-4de2-bcbd-af380542ff4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866492072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.2866492072
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.580837179
Short name T519
Test name
Test status
Simulation time 30582961 ps
CPU time 1.03 seconds
Started Aug 02 04:39:03 PM PDT 24
Finished Aug 02 04:39:05 PM PDT 24
Peak memory 197460 kb
Host smart-c4261ce9-8e74-46dd-820e-173fd8ebe40b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580837179 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.580837179
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.1344964629
Short name T98
Test name
Test status
Simulation time 31695345 ps
CPU time 0.57 seconds
Started Aug 02 04:39:08 PM PDT 24
Finished Aug 02 04:39:08 PM PDT 24
Peak memory 182664 kb
Host smart-e6cab88c-ef66-463c-a7b4-df2265fcb56d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344964629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.1344964629
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.2633239663
Short name T560
Test name
Test status
Simulation time 16204217 ps
CPU time 0.55 seconds
Started Aug 02 04:39:02 PM PDT 24
Finished Aug 02 04:39:03 PM PDT 24
Peak memory 182208 kb
Host smart-63bb4c7b-0d78-4690-a693-fb62cf3fd83a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633239663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.2633239663
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.1051690097
Short name T576
Test name
Test status
Simulation time 31652998 ps
CPU time 0.72 seconds
Started Aug 02 04:39:14 PM PDT 24
Finished Aug 02 04:39:15 PM PDT 24
Peak memory 192244 kb
Host smart-fdef2291-9edf-473f-bb48-6374333e89e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051690097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.1051690097
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.1063211455
Short name T497
Test name
Test status
Simulation time 176677295 ps
CPU time 3.19 seconds
Started Aug 02 04:39:03 PM PDT 24
Finished Aug 02 04:39:06 PM PDT 24
Peak memory 197468 kb
Host smart-6e461b34-0cd4-4a73-8e9b-1dc20c3a6ca9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063211455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.1063211455
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.3426629474
Short name T551
Test name
Test status
Simulation time 86192255 ps
CPU time 0.85 seconds
Started Aug 02 04:39:12 PM PDT 24
Finished Aug 02 04:39:13 PM PDT 24
Peak memory 182888 kb
Host smart-7c45e045-0aa9-48d2-b1a3-ebf82d8eede5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426629474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.3426629474
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.2056895556
Short name T474
Test name
Test status
Simulation time 55659238 ps
CPU time 0.71 seconds
Started Aug 02 04:39:24 PM PDT 24
Finished Aug 02 04:39:24 PM PDT 24
Peak memory 194720 kb
Host smart-7986af80-65ee-42e5-aa09-1bc313d670e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056895556 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.2056895556
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.606522869
Short name T489
Test name
Test status
Simulation time 21143661 ps
CPU time 0.55 seconds
Started Aug 02 04:39:04 PM PDT 24
Finished Aug 02 04:39:04 PM PDT 24
Peak memory 182676 kb
Host smart-d6bc1c8b-cabb-49a7-b112-f69b378fc350
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606522869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.606522869
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.4283744578
Short name T486
Test name
Test status
Simulation time 31304946 ps
CPU time 0.58 seconds
Started Aug 02 04:39:03 PM PDT 24
Finished Aug 02 04:39:04 PM PDT 24
Peak memory 182604 kb
Host smart-5f381c48-931a-4d5c-b081-4632f5023161
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283744578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.4283744578
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.2395378711
Short name T552
Test name
Test status
Simulation time 14069574 ps
CPU time 0.67 seconds
Started Aug 02 04:39:19 PM PDT 24
Finished Aug 02 04:39:20 PM PDT 24
Peak memory 192244 kb
Host smart-28d3c834-c543-4ad9-9a44-70eee30ac47a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395378711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.2395378711
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3950958944
Short name T514
Test name
Test status
Simulation time 175895148 ps
CPU time 1.03 seconds
Started Aug 02 04:39:05 PM PDT 24
Finished Aug 02 04:39:06 PM PDT 24
Peak memory 196120 kb
Host smart-818d1684-78f7-470a-96f1-99b1bed6e2ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950958944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.3950958944
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.1865732446
Short name T500
Test name
Test status
Simulation time 173743944 ps
CPU time 0.88 seconds
Started Aug 02 04:39:05 PM PDT 24
Finished Aug 02 04:39:06 PM PDT 24
Peak memory 193532 kb
Host smart-eb646e8a-1773-4c11-9bfd-95d39d3cd3dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865732446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.1865732446
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.1961552938
Short name T482
Test name
Test status
Simulation time 82560454 ps
CPU time 0.69 seconds
Started Aug 02 04:39:10 PM PDT 24
Finished Aug 02 04:39:11 PM PDT 24
Peak memory 194992 kb
Host smart-c7276940-8ebd-4b14-8f76-d5406192c374
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961552938 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.1961552938
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.2143415191
Short name T101
Test name
Test status
Simulation time 37885775 ps
CPU time 0.54 seconds
Started Aug 02 04:39:12 PM PDT 24
Finished Aug 02 04:39:13 PM PDT 24
Peak memory 182752 kb
Host smart-10607c62-dea2-43c9-99de-652a9948e3c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143415191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.2143415191
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.1106807243
Short name T549
Test name
Test status
Simulation time 15620729 ps
CPU time 0.59 seconds
Started Aug 02 04:39:02 PM PDT 24
Finished Aug 02 04:39:03 PM PDT 24
Peak memory 182224 kb
Host smart-5f0ff25e-0002-409f-aad4-43df0b0814ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106807243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.1106807243
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.2451243987
Short name T542
Test name
Test status
Simulation time 19990367 ps
CPU time 0.81 seconds
Started Aug 02 04:39:18 PM PDT 24
Finished Aug 02 04:39:19 PM PDT 24
Peak memory 193540 kb
Host smart-0774fec6-9e2c-4369-b17e-2da369f180a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451243987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.2451243987
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.2370946404
Short name T523
Test name
Test status
Simulation time 466907432 ps
CPU time 2.25 seconds
Started Aug 02 04:39:07 PM PDT 24
Finished Aug 02 04:39:09 PM PDT 24
Peak memory 197480 kb
Host smart-3234e817-abad-429c-a8a3-78738fb0b4c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370946404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.2370946404
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.1267061652
Short name T533
Test name
Test status
Simulation time 105790870 ps
CPU time 1.34 seconds
Started Aug 02 04:39:01 PM PDT 24
Finished Aug 02 04:39:03 PM PDT 24
Peak memory 195428 kb
Host smart-552100b8-6c14-4e81-b700-899a88f63acd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267061652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.1267061652
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.2056911001
Short name T270
Test name
Test status
Simulation time 28620846668 ps
CPU time 19.77 seconds
Started Aug 02 04:39:40 PM PDT 24
Finished Aug 02 04:40:00 PM PDT 24
Peak memory 183280 kb
Host smart-b689b646-0d80-44df-83dd-d1cd40083c3c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056911001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.2056911001
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.3204211937
Short name T441
Test name
Test status
Simulation time 89961083003 ps
CPU time 131.3 seconds
Started Aug 02 04:39:29 PM PDT 24
Finished Aug 02 04:41:41 PM PDT 24
Peak memory 183348 kb
Host smart-1bc721aa-f3cc-45e2-9307-2a886bd94708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204211937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.3204211937
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.3844295598
Short name T223
Test name
Test status
Simulation time 562576887801 ps
CPU time 373.04 seconds
Started Aug 02 04:39:36 PM PDT 24
Finished Aug 02 04:45:49 PM PDT 24
Peak memory 191464 kb
Host smart-6d0510bd-30c3-4ccc-af92-498baa486c80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844295598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.3844295598
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.1226704652
Short name T22
Test name
Test status
Simulation time 76386344435 ps
CPU time 56.3 seconds
Started Aug 02 04:39:36 PM PDT 24
Finished Aug 02 04:40:32 PM PDT 24
Peak memory 195192 kb
Host smart-9fc0e0d6-7c76-4321-a4a7-eda1dbef76d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226704652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.1226704652
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.3453247690
Short name T433
Test name
Test status
Simulation time 21769147 ps
CPU time 0.58 seconds
Started Aug 02 04:39:28 PM PDT 24
Finished Aug 02 04:39:29 PM PDT 24
Peak memory 183004 kb
Host smart-2ab30d0b-af04-42e1-a717-885fd1d7b070
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453247690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
3453247690
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.2382897897
Short name T401
Test name
Test status
Simulation time 20789193666 ps
CPU time 19.35 seconds
Started Aug 02 04:39:25 PM PDT 24
Finished Aug 02 04:39:44 PM PDT 24
Peak memory 183308 kb
Host smart-2cf27c2f-2685-43df-bc37-941c5f103a3c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382897897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.2382897897
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.2675559142
Short name T393
Test name
Test status
Simulation time 145948458147 ps
CPU time 201.29 seconds
Started Aug 02 04:39:34 PM PDT 24
Finished Aug 02 04:42:56 PM PDT 24
Peak memory 183280 kb
Host smart-a92e74f2-3b88-4ca6-8079-7edb3f8fefb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675559142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.2675559142
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.2027115010
Short name T151
Test name
Test status
Simulation time 93511466585 ps
CPU time 123 seconds
Started Aug 02 04:39:23 PM PDT 24
Finished Aug 02 04:41:26 PM PDT 24
Peak memory 191516 kb
Host smart-0d480fe4-91f9-496b-a396-b4aa1f0a5d3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027115010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.2027115010
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.585876100
Short name T380
Test name
Test status
Simulation time 393714033 ps
CPU time 0.73 seconds
Started Aug 02 04:39:45 PM PDT 24
Finished Aug 02 04:39:45 PM PDT 24
Peak memory 191664 kb
Host smart-ec0459f4-0ca3-4d58-91c9-7ab8754026a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585876100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.585876100
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.1066297025
Short name T20
Test name
Test status
Simulation time 70693912 ps
CPU time 0.85 seconds
Started Aug 02 04:39:27 PM PDT 24
Finished Aug 02 04:39:28 PM PDT 24
Peak memory 213848 kb
Host smart-2be59bb3-1cca-4b27-bd33-7e521c1c3116
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066297025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.1066297025
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.2721387501
Short name T68
Test name
Test status
Simulation time 353838334604 ps
CPU time 286.76 seconds
Started Aug 02 04:39:31 PM PDT 24
Finished Aug 02 04:44:18 PM PDT 24
Peak memory 194144 kb
Host smart-61277442-15ef-4e3e-918a-2a4915c85344
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721387501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
2721387501
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all_with_rand_reset.3444389717
Short name T16
Test name
Test status
Simulation time 183015569921 ps
CPU time 446.2 seconds
Started Aug 02 04:39:31 PM PDT 24
Finished Aug 02 04:46:57 PM PDT 24
Peak memory 206180 kb
Host smart-934645d5-63fe-4773-b192-f1691c970a61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444389717 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all_with_rand_reset.3444389717
Directory /workspace/1.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.3518380259
Short name T370
Test name
Test status
Simulation time 93863142917 ps
CPU time 136.17 seconds
Started Aug 02 04:39:30 PM PDT 24
Finished Aug 02 04:41:46 PM PDT 24
Peak memory 183456 kb
Host smart-d6f1c089-8b87-4b44-9988-d49ec03242e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518380259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.3518380259
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.414847369
Short name T426
Test name
Test status
Simulation time 118097420633 ps
CPU time 35.7 seconds
Started Aug 02 04:39:36 PM PDT 24
Finished Aug 02 04:40:12 PM PDT 24
Peak memory 183280 kb
Host smart-18917d59-2131-4148-aea0-d87f6d4d80a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414847369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.414847369
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.3554293151
Short name T12
Test name
Test status
Simulation time 1861880568 ps
CPU time 1.09 seconds
Started Aug 02 04:39:42 PM PDT 24
Finished Aug 02 04:39:43 PM PDT 24
Peak memory 183036 kb
Host smart-1673c9ee-c02f-40a6-bb4f-7dd000b3911f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554293151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.3554293151
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/102.rv_timer_random.2177884369
Short name T206
Test name
Test status
Simulation time 208349099424 ps
CPU time 196.46 seconds
Started Aug 02 04:40:16 PM PDT 24
Finished Aug 02 04:43:32 PM PDT 24
Peak memory 191508 kb
Host smart-d577fe3a-0a5c-405e-8be2-ec6cf8242cc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177884369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.2177884369
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.635267154
Short name T293
Test name
Test status
Simulation time 62523638522 ps
CPU time 186.49 seconds
Started Aug 02 04:40:21 PM PDT 24
Finished Aug 02 04:43:28 PM PDT 24
Peak memory 191520 kb
Host smart-cd99a627-5cf3-4ef4-883a-c769070f6a42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635267154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.635267154
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.1846900900
Short name T263
Test name
Test status
Simulation time 56061458626 ps
CPU time 1606.06 seconds
Started Aug 02 04:40:33 PM PDT 24
Finished Aug 02 05:07:19 PM PDT 24
Peak memory 191512 kb
Host smart-61f781c0-afad-4570-9a48-7080966d201d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846900900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.1846900900
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.1381972155
Short name T408
Test name
Test status
Simulation time 237746257905 ps
CPU time 349.19 seconds
Started Aug 02 04:39:32 PM PDT 24
Finished Aug 02 04:45:22 PM PDT 24
Peak memory 183288 kb
Host smart-8d906e29-5daa-4ce4-bad6-ffcfb7f66e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381972155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.1381972155
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.3785139023
Short name T274
Test name
Test status
Simulation time 384304228423 ps
CPU time 192.29 seconds
Started Aug 02 04:39:48 PM PDT 24
Finished Aug 02 04:43:00 PM PDT 24
Peak memory 191452 kb
Host smart-ad53d4f3-860d-4af0-b7e4-595b423f3fb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785139023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.3785139023
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.47921441
Short name T3
Test name
Test status
Simulation time 174927461649 ps
CPU time 72.07 seconds
Started Aug 02 04:39:36 PM PDT 24
Finished Aug 02 04:40:49 PM PDT 24
Peak memory 183320 kb
Host smart-7477e422-50f5-402d-a3ec-508476456455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47921441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.47921441
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/112.rv_timer_random.2844575972
Short name T215
Test name
Test status
Simulation time 492897430959 ps
CPU time 2672.18 seconds
Started Aug 02 04:40:16 PM PDT 24
Finished Aug 02 05:24:48 PM PDT 24
Peak memory 191660 kb
Host smart-6b0e4d3b-fa07-46d9-a8b6-ca9bd59376ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844575972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.2844575972
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.2017053682
Short name T267
Test name
Test status
Simulation time 20303726106 ps
CPU time 33.37 seconds
Started Aug 02 04:40:15 PM PDT 24
Finished Aug 02 04:40:49 PM PDT 24
Peak memory 183308 kb
Host smart-cde5f63d-afa7-4b44-be25-6ca2a56362d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017053682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.2017053682
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.2859551316
Short name T122
Test name
Test status
Simulation time 155798591920 ps
CPU time 250.18 seconds
Started Aug 02 04:40:26 PM PDT 24
Finished Aug 02 04:44:37 PM PDT 24
Peak memory 191476 kb
Host smart-b06e0355-2521-4e95-b9ad-923f2ee45766
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859551316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.2859551316
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.3658537897
Short name T414
Test name
Test status
Simulation time 795974812418 ps
CPU time 113.9 seconds
Started Aug 02 04:39:35 PM PDT 24
Finished Aug 02 04:41:30 PM PDT 24
Peak memory 183340 kb
Host smart-0229ca77-1f25-4cc2-a0e7-a5e0ae6b286e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658537897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.3658537897
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.994846152
Short name T389
Test name
Test status
Simulation time 83663293318 ps
CPU time 168.71 seconds
Started Aug 02 04:39:37 PM PDT 24
Finished Aug 02 04:42:26 PM PDT 24
Peak memory 183320 kb
Host smart-ced4ecfa-c7dd-4dce-9b2c-40cf6acf8ea7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994846152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.994846152
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.880082706
Short name T419
Test name
Test status
Simulation time 165666508 ps
CPU time 0.79 seconds
Started Aug 02 04:39:35 PM PDT 24
Finished Aug 02 04:39:36 PM PDT 24
Peak memory 183100 kb
Host smart-d1ced74e-9e94-48f3-a159-5665a7948b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880082706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.880082706
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/120.rv_timer_random.2655858434
Short name T330
Test name
Test status
Simulation time 114318260317 ps
CPU time 165.6 seconds
Started Aug 02 04:40:33 PM PDT 24
Finished Aug 02 04:43:19 PM PDT 24
Peak memory 191624 kb
Host smart-075a9bed-ac08-419c-b28f-549f957b23ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655858434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.2655858434
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.729666253
Short name T297
Test name
Test status
Simulation time 134969117996 ps
CPU time 250.02 seconds
Started Aug 02 04:40:22 PM PDT 24
Finished Aug 02 04:44:32 PM PDT 24
Peak memory 183424 kb
Host smart-b432e1d3-263e-4120-a1df-7b75ee94f0fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729666253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.729666253
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.3081626422
Short name T290
Test name
Test status
Simulation time 495907920790 ps
CPU time 653.69 seconds
Started Aug 02 04:40:37 PM PDT 24
Finished Aug 02 04:51:31 PM PDT 24
Peak memory 191528 kb
Host smart-e14c7d07-0e06-46a0-b489-7ad93583cfeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081626422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.3081626422
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.2077356048
Short name T144
Test name
Test status
Simulation time 2293627631105 ps
CPU time 537.87 seconds
Started Aug 02 04:40:28 PM PDT 24
Finished Aug 02 04:49:26 PM PDT 24
Peak memory 191612 kb
Host smart-7a5dcb3d-625c-4fdf-b5fa-88b186df8dbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077356048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.2077356048
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.1520111202
Short name T407
Test name
Test status
Simulation time 438653558416 ps
CPU time 348.88 seconds
Started Aug 02 04:40:16 PM PDT 24
Finished Aug 02 04:46:05 PM PDT 24
Peak memory 191484 kb
Host smart-d35b4590-77dd-4595-b21f-d4048ce958f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520111202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.1520111202
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.1908875328
Short name T213
Test name
Test status
Simulation time 527918615663 ps
CPU time 424.66 seconds
Started Aug 02 04:40:32 PM PDT 24
Finished Aug 02 04:47:37 PM PDT 24
Peak memory 191520 kb
Host smart-014516f1-9037-4353-bfd0-133b9d8b5171
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908875328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.1908875328
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.3944061300
Short name T359
Test name
Test status
Simulation time 29120424747 ps
CPU time 76.54 seconds
Started Aug 02 04:40:11 PM PDT 24
Finished Aug 02 04:41:27 PM PDT 24
Peak memory 183312 kb
Host smart-948b670e-185d-4447-836b-be58ab6dcbd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944061300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.3944061300
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.1862346918
Short name T257
Test name
Test status
Simulation time 1519194629535 ps
CPU time 824.9 seconds
Started Aug 02 04:39:35 PM PDT 24
Finished Aug 02 04:53:20 PM PDT 24
Peak memory 183332 kb
Host smart-419777d1-920e-4336-a37e-d42229019215
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862346918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.1862346918
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.54488448
Short name T88
Test name
Test status
Simulation time 412902636145 ps
CPU time 143.28 seconds
Started Aug 02 04:39:47 PM PDT 24
Finished Aug 02 04:42:11 PM PDT 24
Peak memory 183256 kb
Host smart-a7139e11-f144-4d85-87ff-2bac432cbbee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54488448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.54488448
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.599971187
Short name T13
Test name
Test status
Simulation time 20624859762 ps
CPU time 30.61 seconds
Started Aug 02 04:39:44 PM PDT 24
Finished Aug 02 04:40:14 PM PDT 24
Peak memory 183252 kb
Host smart-0d5b86c6-6fe3-4cdd-8a63-ac01afe40ab5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599971187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.599971187
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all_with_rand_reset.3322849344
Short name T417
Test name
Test status
Simulation time 96394635310 ps
CPU time 333.86 seconds
Started Aug 02 04:39:50 PM PDT 24
Finished Aug 02 04:45:25 PM PDT 24
Peak memory 206164 kb
Host smart-f28abb51-204e-42c3-820b-f43af381782c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322849344 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all_with_rand_reset.3322849344
Directory /workspace/13.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/132.rv_timer_random.1105734119
Short name T160
Test name
Test status
Simulation time 187953933086 ps
CPU time 646.59 seconds
Started Aug 02 04:40:18 PM PDT 24
Finished Aug 02 04:51:05 PM PDT 24
Peak memory 191464 kb
Host smart-b147031b-925a-4dc6-9e47-4505df1e3006
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105734119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.1105734119
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.3212251656
Short name T251
Test name
Test status
Simulation time 189265568333 ps
CPU time 82.37 seconds
Started Aug 02 04:40:25 PM PDT 24
Finished Aug 02 04:41:48 PM PDT 24
Peak memory 191476 kb
Host smart-e3b36ee9-9c2b-45f3-8bad-74e966ae714d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212251656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.3212251656
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.1897818052
Short name T288
Test name
Test status
Simulation time 25555024627 ps
CPU time 52.59 seconds
Started Aug 02 04:40:21 PM PDT 24
Finished Aug 02 04:41:14 PM PDT 24
Peak memory 183292 kb
Host smart-70d5453d-2e4d-452f-8819-f01585f35240
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897818052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.1897818052
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.115163860
Short name T241
Test name
Test status
Simulation time 146438680473 ps
CPU time 205.04 seconds
Started Aug 02 04:40:31 PM PDT 24
Finished Aug 02 04:43:56 PM PDT 24
Peak memory 191520 kb
Host smart-4138e629-e4cb-45db-8af0-8bbf7bbd8de0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115163860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.115163860
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.2829618788
Short name T437
Test name
Test status
Simulation time 18768035205 ps
CPU time 29.58 seconds
Started Aug 02 04:40:37 PM PDT 24
Finished Aug 02 04:41:07 PM PDT 24
Peak memory 183272 kb
Host smart-db923ecd-c20b-4f6c-8ce6-a024769913f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829618788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.2829618788
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.2191324348
Short name T361
Test name
Test status
Simulation time 428454905766 ps
CPU time 353.31 seconds
Started Aug 02 04:40:21 PM PDT 24
Finished Aug 02 04:46:14 PM PDT 24
Peak memory 191560 kb
Host smart-8562b8c9-b9dc-4ab5-a88a-2ef11834220c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191324348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.2191324348
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.858509303
Short name T358
Test name
Test status
Simulation time 109514736759 ps
CPU time 92.74 seconds
Started Aug 02 04:40:24 PM PDT 24
Finished Aug 02 04:41:57 PM PDT 24
Peak memory 183308 kb
Host smart-ab753414-c82f-47e4-8867-a8890b2261dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858509303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.858509303
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.3779664992
Short name T372
Test name
Test status
Simulation time 53532968730 ps
CPU time 76.4 seconds
Started Aug 02 04:39:47 PM PDT 24
Finished Aug 02 04:41:04 PM PDT 24
Peak memory 183332 kb
Host smart-d9d85738-7486-420b-8b06-5518350193f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779664992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.3779664992
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.1185237598
Short name T306
Test name
Test status
Simulation time 230952480966 ps
CPU time 83.24 seconds
Started Aug 02 04:39:38 PM PDT 24
Finished Aug 02 04:41:02 PM PDT 24
Peak memory 191548 kb
Host smart-e79daec7-ff6c-4a09-b211-4d95fc2185f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185237598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.1185237598
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.1988187285
Short name T47
Test name
Test status
Simulation time 570393403 ps
CPU time 1.27 seconds
Started Aug 02 04:39:50 PM PDT 24
Finished Aug 02 04:39:52 PM PDT 24
Peak memory 193700 kb
Host smart-da8f242a-bbad-4713-a6c3-3d3b85e7c2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988187285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.1988187285
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.2334202260
Short name T289
Test name
Test status
Simulation time 192901703549 ps
CPU time 162.16 seconds
Started Aug 02 04:40:01 PM PDT 24
Finished Aug 02 04:42:44 PM PDT 24
Peak memory 195132 kb
Host smart-b756df94-17f5-4b1f-9471-31df052f1546
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334202260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.2334202260
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/140.rv_timer_random.3181833290
Short name T186
Test name
Test status
Simulation time 30246197184 ps
CPU time 49 seconds
Started Aug 02 04:40:21 PM PDT 24
Finished Aug 02 04:41:10 PM PDT 24
Peak memory 183348 kb
Host smart-f876c464-b5d7-4eb2-8cdf-b363fe5fc0eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181833290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.3181833290
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.3463791591
Short name T339
Test name
Test status
Simulation time 140529645893 ps
CPU time 165.7 seconds
Started Aug 02 04:40:27 PM PDT 24
Finished Aug 02 04:43:13 PM PDT 24
Peak memory 191508 kb
Host smart-eb99afb4-6e89-4f54-92d0-cfb2e0c01db3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463791591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.3463791591
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.1865512018
Short name T232
Test name
Test status
Simulation time 216972129294 ps
CPU time 1999.25 seconds
Started Aug 02 04:40:28 PM PDT 24
Finished Aug 02 05:13:47 PM PDT 24
Peak memory 191468 kb
Host smart-e3372657-5169-4537-9ada-39b8f55f8f49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865512018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.1865512018
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.958495521
Short name T62
Test name
Test status
Simulation time 514205897062 ps
CPU time 206.39 seconds
Started Aug 02 04:40:21 PM PDT 24
Finished Aug 02 04:43:48 PM PDT 24
Peak memory 191652 kb
Host smart-3cac05c0-3d3d-459f-a8a8-302ab7ead86f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958495521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.958495521
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.1765581100
Short name T331
Test name
Test status
Simulation time 67042392727 ps
CPU time 385.8 seconds
Started Aug 02 04:40:50 PM PDT 24
Finished Aug 02 04:47:16 PM PDT 24
Peak memory 191424 kb
Host smart-34928141-4f91-4220-b0c1-b91fa9ed6f7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765581100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.1765581100
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.2948702349
Short name T135
Test name
Test status
Simulation time 137194785961 ps
CPU time 196.55 seconds
Started Aug 02 04:40:35 PM PDT 24
Finished Aug 02 04:43:52 PM PDT 24
Peak memory 183268 kb
Host smart-36070c1b-8290-4028-bf74-400ab1d9cb3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948702349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.2948702349
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.2199379249
Short name T273
Test name
Test status
Simulation time 106214461593 ps
CPU time 178.16 seconds
Started Aug 02 04:40:26 PM PDT 24
Finished Aug 02 04:43:24 PM PDT 24
Peak memory 191516 kb
Host smart-621503c7-e141-400b-8934-e70e7cfe5cfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199379249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.2199379249
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.1070608299
Short name T133
Test name
Test status
Simulation time 456723620309 ps
CPU time 2426.98 seconds
Started Aug 02 04:40:22 PM PDT 24
Finished Aug 02 05:20:50 PM PDT 24
Peak memory 191488 kb
Host smart-95afebd6-b797-4a3a-a7a9-805bcb4c3da3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070608299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.1070608299
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.936477118
Short name T149
Test name
Test status
Simulation time 235067673853 ps
CPU time 372.26 seconds
Started Aug 02 04:39:37 PM PDT 24
Finished Aug 02 04:45:50 PM PDT 24
Peak memory 183308 kb
Host smart-f7dc39d7-72ae-4784-80f5-af076946c38e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936477118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.rv_timer_cfg_update_on_fly.936477118
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.3953483926
Short name T424
Test name
Test status
Simulation time 21953666271 ps
CPU time 32.92 seconds
Started Aug 02 04:39:36 PM PDT 24
Finished Aug 02 04:40:09 PM PDT 24
Peak memory 183140 kb
Host smart-9e781fb8-f093-4b66-a4b0-0a6f10d43259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953483926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.3953483926
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.2154941225
Short name T371
Test name
Test status
Simulation time 100951767 ps
CPU time 0.59 seconds
Started Aug 02 04:39:35 PM PDT 24
Finished Aug 02 04:39:36 PM PDT 24
Peak memory 183076 kb
Host smart-39429720-d7f8-422b-8723-bc68ae705137
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154941225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.2154941225
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/151.rv_timer_random.1294941860
Short name T208
Test name
Test status
Simulation time 46903974528 ps
CPU time 597.48 seconds
Started Aug 02 04:40:31 PM PDT 24
Finished Aug 02 04:50:28 PM PDT 24
Peak memory 191528 kb
Host smart-462807b0-5d2d-4c23-8b7a-d0d8a68a7f20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294941860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.1294941860
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.832824660
Short name T276
Test name
Test status
Simulation time 153197335567 ps
CPU time 143.64 seconds
Started Aug 02 04:40:28 PM PDT 24
Finished Aug 02 04:42:51 PM PDT 24
Peak memory 191456 kb
Host smart-da1fbba6-4f20-4936-8864-f9f4fded55d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832824660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.832824660
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.270151143
Short name T222
Test name
Test status
Simulation time 158004998088 ps
CPU time 1244.58 seconds
Started Aug 02 04:40:27 PM PDT 24
Finished Aug 02 05:01:11 PM PDT 24
Peak memory 191648 kb
Host smart-e9df1e12-cdad-47b6-832b-bfaf088ae4f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270151143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.270151143
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.2920793427
Short name T335
Test name
Test status
Simulation time 297688085753 ps
CPU time 2296.84 seconds
Started Aug 02 04:40:20 PM PDT 24
Finished Aug 02 05:18:38 PM PDT 24
Peak memory 191536 kb
Host smart-705d091e-e738-4ce4-927a-73570f199f34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920793427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.2920793427
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.3206633009
Short name T168
Test name
Test status
Simulation time 652857962519 ps
CPU time 1848.69 seconds
Started Aug 02 04:40:32 PM PDT 24
Finished Aug 02 05:11:21 PM PDT 24
Peak memory 191548 kb
Host smart-190cd39e-1de7-4e42-a675-c0fc385dbaf1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206633009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.3206633009
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.3834146571
Short name T230
Test name
Test status
Simulation time 1157244244484 ps
CPU time 419.03 seconds
Started Aug 02 04:39:47 PM PDT 24
Finished Aug 02 04:46:47 PM PDT 24
Peak memory 183300 kb
Host smart-ee10056a-f79c-4156-a52c-013c79abf7bf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834146571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.3834146571
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.2854482939
Short name T398
Test name
Test status
Simulation time 3484734064 ps
CPU time 5.29 seconds
Started Aug 02 04:39:47 PM PDT 24
Finished Aug 02 04:39:53 PM PDT 24
Peak memory 183140 kb
Host smart-c6102376-6a20-427b-a8eb-5b2c480361e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854482939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.2854482939
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.4045536510
Short name T363
Test name
Test status
Simulation time 298540540 ps
CPU time 1.19 seconds
Started Aug 02 04:39:35 PM PDT 24
Finished Aug 02 04:39:36 PM PDT 24
Peak memory 183296 kb
Host smart-11ab2d95-48b2-4a3f-b973-4e2ac6ae3130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045536510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.4045536510
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all_with_rand_reset.3768505181
Short name T94
Test name
Test status
Simulation time 72894783609 ps
CPU time 705.28 seconds
Started Aug 02 04:39:49 PM PDT 24
Finished Aug 02 04:51:35 PM PDT 24
Peak memory 199416 kb
Host smart-abb5897d-bd03-4fef-904a-679520660090
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768505181 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all_with_rand_reset.3768505181
Directory /workspace/16.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/161.rv_timer_random.2874099250
Short name T219
Test name
Test status
Simulation time 144190366808 ps
CPU time 116.18 seconds
Started Aug 02 04:40:21 PM PDT 24
Finished Aug 02 04:42:17 PM PDT 24
Peak memory 191556 kb
Host smart-d98a3360-79eb-44c8-b8ab-dc4105b3e109
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874099250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.2874099250
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.2812301047
Short name T299
Test name
Test status
Simulation time 56834211561 ps
CPU time 22.24 seconds
Started Aug 02 04:40:23 PM PDT 24
Finished Aug 02 04:40:46 PM PDT 24
Peak memory 183188 kb
Host smart-17b30268-aa4b-437b-b6a4-568bcd87ee8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812301047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.2812301047
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.3161537487
Short name T334
Test name
Test status
Simulation time 140029452334 ps
CPU time 256.42 seconds
Started Aug 02 04:40:28 PM PDT 24
Finished Aug 02 04:44:45 PM PDT 24
Peak memory 191492 kb
Host smart-efb6c1e1-cbee-4b10-83f6-9a0f9f83f310
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161537487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.3161537487
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.3113857447
Short name T271
Test name
Test status
Simulation time 68112110379 ps
CPU time 138.3 seconds
Started Aug 02 04:40:26 PM PDT 24
Finished Aug 02 04:42:45 PM PDT 24
Peak memory 191012 kb
Host smart-c1362e1f-ad31-4343-bd37-353716360251
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113857447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.3113857447
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.1346995016
Short name T272
Test name
Test status
Simulation time 92562914295 ps
CPU time 132.97 seconds
Started Aug 02 04:40:38 PM PDT 24
Finished Aug 02 04:42:51 PM PDT 24
Peak memory 191472 kb
Host smart-658986f4-57fd-4c8a-9654-a233b20327fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346995016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.1346995016
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.1940379949
Short name T343
Test name
Test status
Simulation time 49731324561 ps
CPU time 137.22 seconds
Started Aug 02 04:40:28 PM PDT 24
Finished Aug 02 04:42:45 PM PDT 24
Peak memory 183336 kb
Host smart-32909177-ee78-4e46-a831-15fbd784ea70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940379949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.1940379949
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.3146501016
Short name T285
Test name
Test status
Simulation time 218063193510 ps
CPU time 467.4 seconds
Started Aug 02 04:40:30 PM PDT 24
Finished Aug 02 04:48:17 PM PDT 24
Peak memory 191464 kb
Host smart-becd4e02-645e-4577-83bd-79d531b8fd48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146501016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.3146501016
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.3062082477
Short name T87
Test name
Test status
Simulation time 16615299557 ps
CPU time 24.68 seconds
Started Aug 02 04:39:54 PM PDT 24
Finished Aug 02 04:40:19 PM PDT 24
Peak memory 183308 kb
Host smart-39c4ff94-2150-4c30-a293-76876509c567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062082477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.3062082477
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.3114657492
Short name T427
Test name
Test status
Simulation time 171220160538 ps
CPU time 66.76 seconds
Started Aug 02 04:39:50 PM PDT 24
Finished Aug 02 04:40:57 PM PDT 24
Peak memory 183348 kb
Host smart-3a99270e-bbee-4794-9e7a-35bdd0e1c43f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114657492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.3114657492
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.4060527588
Short name T260
Test name
Test status
Simulation time 48373957450 ps
CPU time 84.28 seconds
Started Aug 02 04:39:47 PM PDT 24
Finished Aug 02 04:41:12 PM PDT 24
Peak memory 191524 kb
Host smart-1a286f6e-d130-48a3-9a69-2f9a7a089b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060527588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.4060527588
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.459072518
Short name T385
Test name
Test status
Simulation time 139312358 ps
CPU time 0.58 seconds
Started Aug 02 04:39:41 PM PDT 24
Finished Aug 02 04:39:42 PM PDT 24
Peak memory 183016 kb
Host smart-42198baf-33e1-4c64-94bf-4d40d6d58c75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459072518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all.
459072518
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/172.rv_timer_random.3448318994
Short name T127
Test name
Test status
Simulation time 83521379852 ps
CPU time 138.94 seconds
Started Aug 02 04:40:40 PM PDT 24
Finished Aug 02 04:42:59 PM PDT 24
Peak memory 191592 kb
Host smart-9e07f273-9b7f-4060-849f-2b0abe9784e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448318994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.3448318994
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.2704354807
Short name T198
Test name
Test status
Simulation time 49357599526 ps
CPU time 84.21 seconds
Started Aug 02 04:40:32 PM PDT 24
Finished Aug 02 04:41:56 PM PDT 24
Peak memory 183308 kb
Host smart-5bbd7bf5-13b7-4f68-b603-8d6518428d8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704354807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.2704354807
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.3554586176
Short name T411
Test name
Test status
Simulation time 54331842943 ps
CPU time 73.01 seconds
Started Aug 02 04:40:28 PM PDT 24
Finished Aug 02 04:41:42 PM PDT 24
Peak memory 183296 kb
Host smart-ad89f3d3-812e-409e-848b-fdf7b3d5222d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554586176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.3554586176
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.2414324569
Short name T413
Test name
Test status
Simulation time 19997057021 ps
CPU time 13.73 seconds
Started Aug 02 04:40:38 PM PDT 24
Finished Aug 02 04:40:52 PM PDT 24
Peak memory 183392 kb
Host smart-9444520f-823a-49b6-98de-3bdb4205c56e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414324569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.2414324569
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.677768071
Short name T49
Test name
Test status
Simulation time 1608248691359 ps
CPU time 666.87 seconds
Started Aug 02 04:39:48 PM PDT 24
Finished Aug 02 04:51:00 PM PDT 24
Peak memory 183200 kb
Host smart-c067aaaf-1a63-46d5-b462-f2359b787bf3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677768071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.rv_timer_cfg_update_on_fly.677768071
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.1029974913
Short name T395
Test name
Test status
Simulation time 239602071758 ps
CPU time 168.54 seconds
Started Aug 02 04:39:41 PM PDT 24
Finished Aug 02 04:42:29 PM PDT 24
Peak memory 183196 kb
Host smart-97363561-268e-44d7-a728-901d435db377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029974913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.1029974913
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.222008746
Short name T390
Test name
Test status
Simulation time 95387932577 ps
CPU time 42.05 seconds
Started Aug 02 04:39:46 PM PDT 24
Finished Aug 02 04:40:28 PM PDT 24
Peak memory 191508 kb
Host smart-32e227e0-385e-4f82-b861-53f38c66cf22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222008746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.222008746
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.623794769
Short name T305
Test name
Test status
Simulation time 120096534021 ps
CPU time 165.7 seconds
Started Aug 02 04:39:54 PM PDT 24
Finished Aug 02 04:42:40 PM PDT 24
Peak memory 194976 kb
Host smart-b562b073-e926-406e-a6bc-f1bca8856fc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623794769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all.
623794769
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/180.rv_timer_random.2002299572
Short name T337
Test name
Test status
Simulation time 62954671187 ps
CPU time 184.11 seconds
Started Aug 02 04:40:38 PM PDT 24
Finished Aug 02 04:43:42 PM PDT 24
Peak memory 191512 kb
Host smart-723bfcc3-6bd5-40a1-a98d-6a644b1ab2f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002299572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.2002299572
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.1261986104
Short name T228
Test name
Test status
Simulation time 1087568362865 ps
CPU time 1641.85 seconds
Started Aug 02 04:40:29 PM PDT 24
Finished Aug 02 05:07:51 PM PDT 24
Peak memory 191556 kb
Host smart-a89ed65d-cafc-4913-84f3-756e5187f660
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261986104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.1261986104
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.3165815185
Short name T203
Test name
Test status
Simulation time 247892248637 ps
CPU time 580 seconds
Started Aug 02 04:40:40 PM PDT 24
Finished Aug 02 04:50:20 PM PDT 24
Peak memory 191548 kb
Host smart-d8e90b03-40bb-42ee-bea3-93e7629891b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165815185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.3165815185
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.1749923482
Short name T329
Test name
Test status
Simulation time 44794577358 ps
CPU time 32.04 seconds
Started Aug 02 04:40:37 PM PDT 24
Finished Aug 02 04:41:09 PM PDT 24
Peak memory 183324 kb
Host smart-e6c26c07-10c8-490f-a118-47e47f06ae80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749923482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.1749923482
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.3981332417
Short name T252
Test name
Test status
Simulation time 47410874092 ps
CPU time 290.8 seconds
Started Aug 02 04:40:44 PM PDT 24
Finished Aug 02 04:45:35 PM PDT 24
Peak memory 192060 kb
Host smart-d68092c9-723f-4c68-89ee-02ba8cd5c2c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981332417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.3981332417
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.802649630
Short name T362
Test name
Test status
Simulation time 15343537055 ps
CPU time 14.71 seconds
Started Aug 02 04:40:36 PM PDT 24
Finished Aug 02 04:40:51 PM PDT 24
Peak memory 183276 kb
Host smart-aa59ffa3-9565-4865-992c-fc9560ad7ebf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802649630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.802649630
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.4114769896
Short name T423
Test name
Test status
Simulation time 83054461083 ps
CPU time 149.29 seconds
Started Aug 02 04:40:30 PM PDT 24
Finished Aug 02 04:43:00 PM PDT 24
Peak memory 183256 kb
Host smart-f2e41f76-cfe5-4fa9-84f2-0ad17e506fe1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114769896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.4114769896
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.1002900166
Short name T422
Test name
Test status
Simulation time 49821655898 ps
CPU time 45.85 seconds
Started Aug 02 04:40:30 PM PDT 24
Finished Aug 02 04:41:16 PM PDT 24
Peak memory 191504 kb
Host smart-cb750f00-2f61-40cf-af91-d92b7c76bdd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002900166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.1002900166
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.3383473906
Short name T166
Test name
Test status
Simulation time 175440558065 ps
CPU time 192.32 seconds
Started Aug 02 04:40:37 PM PDT 24
Finished Aug 02 04:43:50 PM PDT 24
Peak memory 191488 kb
Host smart-df03e014-6594-49c0-8186-e7e8f8758dc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383473906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.3383473906
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.3509679364
Short name T420
Test name
Test status
Simulation time 341996752367 ps
CPU time 178.01 seconds
Started Aug 02 04:39:48 PM PDT 24
Finished Aug 02 04:42:46 PM PDT 24
Peak memory 183304 kb
Host smart-ffd63de3-4895-4389-9de7-97ee7b04878a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509679364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.3509679364
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.2773410035
Short name T284
Test name
Test status
Simulation time 36079618092 ps
CPU time 25.09 seconds
Started Aug 02 04:39:53 PM PDT 24
Finished Aug 02 04:40:18 PM PDT 24
Peak memory 183324 kb
Host smart-2b106001-f042-42e4-8372-73ba0ad7a5a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773410035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.2773410035
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.742781898
Short name T436
Test name
Test status
Simulation time 156388249 ps
CPU time 0.67 seconds
Started Aug 02 04:40:17 PM PDT 24
Finished Aug 02 04:40:18 PM PDT 24
Peak memory 183064 kb
Host smart-9db1e2ea-70bc-4aee-95f7-c8cdfc22496f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742781898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.742781898
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.3857120311
Short name T199
Test name
Test status
Simulation time 573171903805 ps
CPU time 349.5 seconds
Started Aug 02 04:39:46 PM PDT 24
Finished Aug 02 04:45:36 PM PDT 24
Peak memory 191524 kb
Host smart-7633ecd1-f273-413d-9f44-4d8bf38891c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857120311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.3857120311
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all_with_rand_reset.3676103373
Short name T114
Test name
Test status
Simulation time 128822706297 ps
CPU time 472.73 seconds
Started Aug 02 04:39:48 PM PDT 24
Finished Aug 02 04:47:41 PM PDT 24
Peak memory 207244 kb
Host smart-b9eb7d81-6e2d-4c83-a9bc-385abae431c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676103373 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all_with_rand_reset.3676103373
Directory /workspace/19.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.2007502465
Short name T226
Test name
Test status
Simulation time 193485335261 ps
CPU time 77.26 seconds
Started Aug 02 04:40:46 PM PDT 24
Finished Aug 02 04:42:03 PM PDT 24
Peak memory 194884 kb
Host smart-0a6fe6ae-c52d-472d-b3f7-f210405acfbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007502465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.2007502465
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.3740860792
Short name T347
Test name
Test status
Simulation time 72268337643 ps
CPU time 142.2 seconds
Started Aug 02 04:40:44 PM PDT 24
Finished Aug 02 04:43:06 PM PDT 24
Peak memory 191520 kb
Host smart-7d574761-1841-4faa-8dc6-a5ba81429167
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740860792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.3740860792
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.256603222
Short name T298
Test name
Test status
Simulation time 269256498904 ps
CPU time 384.75 seconds
Started Aug 02 04:40:37 PM PDT 24
Finished Aug 02 04:47:02 PM PDT 24
Peak memory 183300 kb
Host smart-cdacbdca-a02a-42d8-9dc9-2b7e17effb5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256603222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.256603222
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.680191491
Short name T434
Test name
Test status
Simulation time 15573375220 ps
CPU time 542.84 seconds
Started Aug 02 04:40:37 PM PDT 24
Finished Aug 02 04:49:40 PM PDT 24
Peak memory 183296 kb
Host smart-af2cea0f-f39c-4f44-823b-da27443f27a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680191491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.680191491
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.1813798798
Short name T188
Test name
Test status
Simulation time 195398472 ps
CPU time 0.86 seconds
Started Aug 02 04:40:39 PM PDT 24
Finished Aug 02 04:40:40 PM PDT 24
Peak memory 183032 kb
Host smart-815131d0-18f9-4d77-9b4c-e97e735bafad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813798798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.1813798798
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.3981134163
Short name T195
Test name
Test status
Simulation time 48866646788 ps
CPU time 75.12 seconds
Started Aug 02 04:40:45 PM PDT 24
Finished Aug 02 04:42:01 PM PDT 24
Peak memory 191512 kb
Host smart-01f19fe6-4f00-4917-9efc-33290cad5b9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981134163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.3981134163
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.1589041276
Short name T79
Test name
Test status
Simulation time 13782880643 ps
CPU time 81.07 seconds
Started Aug 02 04:40:40 PM PDT 24
Finished Aug 02 04:42:01 PM PDT 24
Peak memory 191468 kb
Host smart-499aee41-9ec5-47ce-a6fe-3e95409f9ba4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589041276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.1589041276
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.4041008723
Short name T159
Test name
Test status
Simulation time 449293332346 ps
CPU time 277.42 seconds
Started Aug 02 04:40:36 PM PDT 24
Finished Aug 02 04:45:13 PM PDT 24
Peak memory 191500 kb
Host smart-86e37b1e-122b-4762-b295-1d268f2501ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041008723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.4041008723
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.1556601812
Short name T402
Test name
Test status
Simulation time 122963685695 ps
CPU time 70.46 seconds
Started Aug 02 04:39:57 PM PDT 24
Finished Aug 02 04:41:07 PM PDT 24
Peak memory 183248 kb
Host smart-d7d84a10-1557-4a2d-a94c-bcbc5628718d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556601812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.1556601812
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.1617092293
Short name T81
Test name
Test status
Simulation time 106442094343 ps
CPU time 158.28 seconds
Started Aug 02 04:39:30 PM PDT 24
Finished Aug 02 04:42:08 PM PDT 24
Peak memory 183428 kb
Host smart-d4d38971-1cb3-4709-b1ce-033c39ec0bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617092293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.1617092293
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.2074612441
Short name T238
Test name
Test status
Simulation time 296678605311 ps
CPU time 164.81 seconds
Started Aug 02 04:39:31 PM PDT 24
Finished Aug 02 04:42:16 PM PDT 24
Peak memory 191484 kb
Host smart-8adda265-23f2-4ac5-81e9-71fa503d9860
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074612441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.2074612441
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.1813123770
Short name T311
Test name
Test status
Simulation time 191328630593 ps
CPU time 233.02 seconds
Started Aug 02 04:39:32 PM PDT 24
Finished Aug 02 04:43:25 PM PDT 24
Peak memory 191496 kb
Host smart-c2aaf242-7199-4cbb-bad6-567473082037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813123770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.1813123770
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.215593422
Short name T17
Test name
Test status
Simulation time 1309534852 ps
CPU time 1.15 seconds
Started Aug 02 04:39:35 PM PDT 24
Finished Aug 02 04:39:36 PM PDT 24
Peak memory 213924 kb
Host smart-56590f79-dfea-49d4-8be1-ea35ee425bb9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215593422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.215593422
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.2623647234
Short name T170
Test name
Test status
Simulation time 3671859336889 ps
CPU time 880.69 seconds
Started Aug 02 04:39:46 PM PDT 24
Finished Aug 02 04:54:27 PM PDT 24
Peak memory 191456 kb
Host smart-ce0f939f-b68f-4278-99fd-613e2d78e7ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623647234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
2623647234
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all_with_rand_reset.1070437400
Short name T428
Test name
Test status
Simulation time 336851653077 ps
CPU time 896.79 seconds
Started Aug 02 04:39:47 PM PDT 24
Finished Aug 02 04:54:44 PM PDT 24
Peak memory 212796 kb
Host smart-338fb62f-ddfb-4837-8a51-5eea5cf87217
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070437400 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all_with_rand_reset.1070437400
Directory /workspace/2.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.3245525331
Short name T205
Test name
Test status
Simulation time 576231775924 ps
CPU time 297.21 seconds
Started Aug 02 04:39:51 PM PDT 24
Finished Aug 02 04:44:49 PM PDT 24
Peak memory 183384 kb
Host smart-3ac6ec28-df54-43a4-a153-3b89ef2c3884
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245525331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.3245525331
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.1423078055
Short name T365
Test name
Test status
Simulation time 451776978284 ps
CPU time 179.38 seconds
Started Aug 02 04:40:03 PM PDT 24
Finished Aug 02 04:43:02 PM PDT 24
Peak memory 183284 kb
Host smart-a5764c2b-2c8d-4002-9546-63592adbc3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423078055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.1423078055
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.3056358136
Short name T59
Test name
Test status
Simulation time 38174678405 ps
CPU time 93.76 seconds
Started Aug 02 04:39:49 PM PDT 24
Finished Aug 02 04:41:23 PM PDT 24
Peak memory 191564 kb
Host smart-dc33565b-2969-4903-b27b-df00b97a4f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056358136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.3056358136
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.643305331
Short name T377
Test name
Test status
Simulation time 695097157560 ps
CPU time 211.27 seconds
Started Aug 02 04:39:49 PM PDT 24
Finished Aug 02 04:43:21 PM PDT 24
Peak memory 183356 kb
Host smart-e3abc917-3452-451c-8ac4-02dff5e45b6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643305331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all.
643305331
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.885082232
Short name T93
Test name
Test status
Simulation time 146891291695 ps
CPU time 75.98 seconds
Started Aug 02 04:39:52 PM PDT 24
Finished Aug 02 04:41:08 PM PDT 24
Peak memory 183300 kb
Host smart-6b126677-22fa-44a0-9684-96df1619e8e4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885082232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.rv_timer_cfg_update_on_fly.885082232
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.4182719685
Short name T369
Test name
Test status
Simulation time 141853476071 ps
CPU time 230.62 seconds
Started Aug 02 04:39:49 PM PDT 24
Finished Aug 02 04:43:40 PM PDT 24
Peak memory 183364 kb
Host smart-2183f1b2-a35a-4d08-965a-6837aa0d3b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182719685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.4182719685
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.1412328746
Short name T157
Test name
Test status
Simulation time 169088018531 ps
CPU time 119.16 seconds
Started Aug 02 04:39:47 PM PDT 24
Finished Aug 02 04:41:46 PM PDT 24
Peak memory 191536 kb
Host smart-e6737ab8-b5be-4db3-ac5b-c8c88d75f5c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412328746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.1412328746
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.728630263
Short name T27
Test name
Test status
Simulation time 89157257583 ps
CPU time 74.85 seconds
Started Aug 02 04:39:42 PM PDT 24
Finished Aug 02 04:40:57 PM PDT 24
Peak memory 183308 kb
Host smart-ccb047e1-7691-44ab-b555-7a6593289910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728630263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.728630263
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.387667838
Short name T382
Test name
Test status
Simulation time 80172420929 ps
CPU time 111.22 seconds
Started Aug 02 04:39:49 PM PDT 24
Finished Aug 02 04:41:40 PM PDT 24
Peak memory 183312 kb
Host smart-134aa0b1-b427-4470-9e0a-62f2d590872b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387667838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.387667838
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.3494960508
Short name T139
Test name
Test status
Simulation time 28556927523 ps
CPU time 390.63 seconds
Started Aug 02 04:39:56 PM PDT 24
Finished Aug 02 04:46:27 PM PDT 24
Peak memory 191476 kb
Host smart-22bce1f5-bef4-4549-936a-ce68263098d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494960508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.3494960508
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.4062119231
Short name T341
Test name
Test status
Simulation time 7703731324 ps
CPU time 32.5 seconds
Started Aug 02 04:40:06 PM PDT 24
Finished Aug 02 04:40:38 PM PDT 24
Peak memory 183356 kb
Host smart-0a6b2be6-fd3b-4403-969d-482d5cad9a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062119231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.4062119231
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.3047006540
Short name T439
Test name
Test status
Simulation time 389709409629 ps
CPU time 134.62 seconds
Started Aug 02 04:39:44 PM PDT 24
Finished Aug 02 04:41:59 PM PDT 24
Peak memory 183332 kb
Host smart-99de6a58-dccd-4592-9f9f-09ec9848a23b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047006540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.3047006540
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.3742870993
Short name T247
Test name
Test status
Simulation time 897053038203 ps
CPU time 320.66 seconds
Started Aug 02 04:39:43 PM PDT 24
Finished Aug 02 04:45:03 PM PDT 24
Peak memory 183312 kb
Host smart-5ef0ee97-58dc-45ef-8ecd-167fea70cd13
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742870993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.3742870993
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.4114681607
Short name T435
Test name
Test status
Simulation time 68210954547 ps
CPU time 44.74 seconds
Started Aug 02 04:39:46 PM PDT 24
Finished Aug 02 04:40:31 PM PDT 24
Peak memory 183288 kb
Host smart-bcdc8a3a-1031-42ec-80ac-beaded9f30f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114681607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.4114681607
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.2253063887
Short name T224
Test name
Test status
Simulation time 681953153236 ps
CPU time 713.38 seconds
Started Aug 02 04:39:47 PM PDT 24
Finished Aug 02 04:51:41 PM PDT 24
Peak memory 191516 kb
Host smart-d87ec686-8e95-42a2-a3dc-b61cc7fffc32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253063887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.2253063887
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.1685289908
Short name T404
Test name
Test status
Simulation time 737744546 ps
CPU time 1.16 seconds
Started Aug 02 04:39:54 PM PDT 24
Finished Aug 02 04:39:56 PM PDT 24
Peak memory 183088 kb
Host smart-809d0eba-c95e-4297-8be3-9ea985e8566c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685289908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.1685289908
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.1781402655
Short name T5
Test name
Test status
Simulation time 1002411933361 ps
CPU time 271.78 seconds
Started Aug 02 04:39:54 PM PDT 24
Finished Aug 02 04:44:26 PM PDT 24
Peak memory 183260 kb
Host smart-90567f48-7001-4329-b6b2-b4596e6f3d35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781402655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.1781402655
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.65622560
Short name T416
Test name
Test status
Simulation time 592132680540 ps
CPU time 305.9 seconds
Started Aug 02 04:39:46 PM PDT 24
Finished Aug 02 04:44:53 PM PDT 24
Peak memory 183292 kb
Host smart-9bbb3e39-73e8-43d5-bf79-60452b38ba46
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65622560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.rv_timer_cfg_update_on_fly.65622560
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.2262285193
Short name T432
Test name
Test status
Simulation time 197767721133 ps
CPU time 250.59 seconds
Started Aug 02 04:39:46 PM PDT 24
Finished Aug 02 04:43:57 PM PDT 24
Peak memory 183300 kb
Host smart-6bdb7b80-0d06-4b8a-9530-4e5591312e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262285193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.2262285193
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.1397839896
Short name T259
Test name
Test status
Simulation time 89592813728 ps
CPU time 369.01 seconds
Started Aug 02 04:40:07 PM PDT 24
Finished Aug 02 04:46:16 PM PDT 24
Peak memory 191516 kb
Host smart-082fda9e-878e-4321-89b7-22773cb0eeb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397839896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.1397839896
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.3632106781
Short name T28
Test name
Test status
Simulation time 19129512552 ps
CPU time 27.09 seconds
Started Aug 02 04:39:50 PM PDT 24
Finished Aug 02 04:40:18 PM PDT 24
Peak memory 191488 kb
Host smart-9c8dd2e4-10c4-41d3-9118-d23064129549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632106781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.3632106781
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.2381757737
Short name T89
Test name
Test status
Simulation time 378579647042 ps
CPU time 371.94 seconds
Started Aug 02 04:39:48 PM PDT 24
Finished Aug 02 04:46:00 PM PDT 24
Peak memory 183296 kb
Host smart-7580ba4e-90be-49f0-a3fc-9f0e7a2db52f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381757737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.2381757737
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.2941993348
Short name T399
Test name
Test status
Simulation time 341731638740 ps
CPU time 136.19 seconds
Started Aug 02 04:39:49 PM PDT 24
Finished Aug 02 04:42:05 PM PDT 24
Peak memory 183316 kb
Host smart-eb24512d-afd1-4408-b198-2fec70ea8cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941993348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.2941993348
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.309304875
Short name T360
Test name
Test status
Simulation time 53150133854 ps
CPU time 92.37 seconds
Started Aug 02 04:39:51 PM PDT 24
Finished Aug 02 04:41:23 PM PDT 24
Peak memory 191496 kb
Host smart-9e98eae0-e66e-4695-ba0b-d6d0ca7899ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309304875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.309304875
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.457422361
Short name T451
Test name
Test status
Simulation time 279179904876 ps
CPU time 355.2 seconds
Started Aug 02 04:40:20 PM PDT 24
Finished Aug 02 04:46:15 PM PDT 24
Peak memory 195900 kb
Host smart-30395925-2182-4333-a5f1-a0c8a0c25319
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457422361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all.
457422361
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.3479216017
Short name T391
Test name
Test status
Simulation time 249656444329 ps
CPU time 110.04 seconds
Started Aug 02 04:39:50 PM PDT 24
Finished Aug 02 04:41:41 PM PDT 24
Peak memory 183204 kb
Host smart-5a32a6bc-1bce-4b3c-9283-cdf8e41ee6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479216017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.3479216017
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.4088334366
Short name T300
Test name
Test status
Simulation time 107056328119 ps
CPU time 42.27 seconds
Started Aug 02 04:39:50 PM PDT 24
Finished Aug 02 04:40:33 PM PDT 24
Peak memory 183248 kb
Host smart-29cfac8c-e0f3-4180-be2c-21340e624e62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088334366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.4088334366
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.2258390513
Short name T2
Test name
Test status
Simulation time 21120625899 ps
CPU time 18.32 seconds
Started Aug 02 04:39:50 PM PDT 24
Finished Aug 02 04:40:09 PM PDT 24
Peak memory 183308 kb
Host smart-67ebd0f9-23e6-4299-97bb-90202956f250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258390513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.2258390513
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all_with_rand_reset.704869010
Short name T43
Test name
Test status
Simulation time 34986672284 ps
CPU time 108.14 seconds
Started Aug 02 04:39:49 PM PDT 24
Finished Aug 02 04:41:37 PM PDT 24
Peak memory 198072 kb
Host smart-67769b1e-de8b-496b-9c0b-ee542aab1819
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704869010 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all_with_rand_reset.704869010
Directory /workspace/26.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.3925117923
Short name T446
Test name
Test status
Simulation time 678635883845 ps
CPU time 335.28 seconds
Started Aug 02 04:39:50 PM PDT 24
Finished Aug 02 04:45:25 PM PDT 24
Peak memory 183288 kb
Host smart-a15f24ad-5347-4c79-86f5-b0dd667db1d2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925117923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.3925117923
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.1273218720
Short name T444
Test name
Test status
Simulation time 522065512170 ps
CPU time 197.56 seconds
Started Aug 02 04:39:45 PM PDT 24
Finished Aug 02 04:43:03 PM PDT 24
Peak memory 183300 kb
Host smart-23526e2b-d9c6-41cb-98e6-b6dd63f50f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273218720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.1273218720
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.2273398680
Short name T191
Test name
Test status
Simulation time 135421995707 ps
CPU time 1195.16 seconds
Started Aug 02 04:39:50 PM PDT 24
Finished Aug 02 04:59:46 PM PDT 24
Peak memory 183300 kb
Host smart-baa142eb-54d8-4ca8-9ae1-391bb4a74fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273398680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.2273398680
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.2049870976
Short name T443
Test name
Test status
Simulation time 720899413592 ps
CPU time 168.11 seconds
Started Aug 02 04:39:55 PM PDT 24
Finished Aug 02 04:42:44 PM PDT 24
Peak memory 183348 kb
Host smart-9755b5ae-3991-49f5-978a-858df94d0e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049870976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.2049870976
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.521710359
Short name T277
Test name
Test status
Simulation time 58583622216 ps
CPU time 116.32 seconds
Started Aug 02 04:39:51 PM PDT 24
Finished Aug 02 04:41:48 PM PDT 24
Peak memory 192620 kb
Host smart-2e88c8ec-0f35-4bb0-b561-bc1a7dc59ab3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521710359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.521710359
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.2169967619
Short name T410
Test name
Test status
Simulation time 18857935 ps
CPU time 0.57 seconds
Started Aug 02 04:39:51 PM PDT 24
Finished Aug 02 04:39:52 PM PDT 24
Peak memory 183112 kb
Host smart-81bbd4a7-d4cc-44e2-8ce4-23cff26ff244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169967619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.2169967619
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.2096250608
Short name T282
Test name
Test status
Simulation time 920121881513 ps
CPU time 1006.88 seconds
Started Aug 02 04:39:49 PM PDT 24
Finished Aug 02 04:56:36 PM PDT 24
Peak memory 183292 kb
Host smart-309b44b5-6aca-4498-a6bc-82f6f9664ef1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096250608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.2096250608
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.878715077
Short name T84
Test name
Test status
Simulation time 120864316434 ps
CPU time 184.57 seconds
Started Aug 02 04:40:07 PM PDT 24
Finished Aug 02 04:43:12 PM PDT 24
Peak memory 183312 kb
Host smart-f9db16aa-de08-4f9f-8e80-9939d869f7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878715077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.878715077
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.2437288331
Short name T438
Test name
Test status
Simulation time 182564527894 ps
CPU time 602.67 seconds
Started Aug 02 04:40:02 PM PDT 24
Finished Aug 02 04:50:05 PM PDT 24
Peak memory 191568 kb
Host smart-c0e7f4df-3614-4588-ae77-454b199dc7a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437288331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.2437288331
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.397917566
Short name T146
Test name
Test status
Simulation time 96621780382 ps
CPU time 80.3 seconds
Started Aug 02 04:39:47 PM PDT 24
Finished Aug 02 04:41:08 PM PDT 24
Peak memory 191536 kb
Host smart-9fd42a82-c832-48be-9b8a-e66af8954134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397917566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.397917566
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.4163556963
Short name T82
Test name
Test status
Simulation time 168631736561 ps
CPU time 287.86 seconds
Started Aug 02 04:39:33 PM PDT 24
Finished Aug 02 04:44:21 PM PDT 24
Peak memory 183280 kb
Host smart-cada25e8-14db-4f0b-ab1e-bd28c8a033ee
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163556963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.4163556963
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.1645788165
Short name T373
Test name
Test status
Simulation time 100441952405 ps
CPU time 158.86 seconds
Started Aug 02 04:39:30 PM PDT 24
Finished Aug 02 04:42:09 PM PDT 24
Peak memory 183264 kb
Host smart-f33bbc1e-0ec4-4b5c-9d9c-71b574633f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645788165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.1645788165
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.2115094630
Short name T128
Test name
Test status
Simulation time 331305627547 ps
CPU time 315.33 seconds
Started Aug 02 04:39:30 PM PDT 24
Finished Aug 02 04:44:45 PM PDT 24
Peak memory 191392 kb
Host smart-b1146e23-c416-4950-9922-502985dd888d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115094630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.2115094630
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.300783091
Short name T18
Test name
Test status
Simulation time 220727344 ps
CPU time 0.78 seconds
Started Aug 02 04:39:36 PM PDT 24
Finished Aug 02 04:39:37 PM PDT 24
Peak memory 213832 kb
Host smart-924f9d6c-9a17-4590-b48f-8ff502d33cec
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300783091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.300783091
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.3337427534
Short name T345
Test name
Test status
Simulation time 194391111303 ps
CPU time 165.55 seconds
Started Aug 02 04:39:50 PM PDT 24
Finished Aug 02 04:42:35 PM PDT 24
Peak memory 183304 kb
Host smart-ffc1659e-0703-4375-9341-d309aa584296
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337427534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.3337427534
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.4102915370
Short name T388
Test name
Test status
Simulation time 663106427852 ps
CPU time 263.92 seconds
Started Aug 02 04:39:54 PM PDT 24
Finished Aug 02 04:44:18 PM PDT 24
Peak memory 183300 kb
Host smart-e9502da1-1ad9-4660-82ca-68271f7baefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102915370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.4102915370
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.2245511353
Short name T196
Test name
Test status
Simulation time 422974535374 ps
CPU time 510.73 seconds
Started Aug 02 04:40:08 PM PDT 24
Finished Aug 02 04:48:39 PM PDT 24
Peak memory 191504 kb
Host smart-b5e0bcce-5089-4451-970b-f6855db24f4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245511353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.2245511353
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.2251782825
Short name T314
Test name
Test status
Simulation time 47870297525 ps
CPU time 107.99 seconds
Started Aug 02 04:39:47 PM PDT 24
Finished Aug 02 04:41:35 PM PDT 24
Peak memory 191552 kb
Host smart-743e05cd-cb4f-4945-ab7c-58877c1eff54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251782825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.2251782825
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.234420287
Short name T235
Test name
Test status
Simulation time 487244795618 ps
CPU time 219.99 seconds
Started Aug 02 04:39:50 PM PDT 24
Finished Aug 02 04:43:31 PM PDT 24
Peak memory 195948 kb
Host smart-2fb1fcbc-c3ea-45ef-b96c-7e3055f885c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234420287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all.
234420287
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all_with_rand_reset.2326743159
Short name T40
Test name
Test status
Simulation time 43812308023 ps
CPU time 157.52 seconds
Started Aug 02 04:39:45 PM PDT 24
Finished Aug 02 04:42:23 PM PDT 24
Peak memory 206280 kb
Host smart-2dd5eaeb-e508-4a4d-b1af-21a05dc607e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326743159 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all_with_rand_reset.2326743159
Directory /workspace/30.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.893350140
Short name T315
Test name
Test status
Simulation time 439007258508 ps
CPU time 366.81 seconds
Started Aug 02 04:39:43 PM PDT 24
Finished Aug 02 04:45:50 PM PDT 24
Peak memory 183284 kb
Host smart-1fb99a00-477d-48e2-ad56-d36af2363b87
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893350140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.rv_timer_cfg_update_on_fly.893350140
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.781397878
Short name T364
Test name
Test status
Simulation time 210752099599 ps
CPU time 326.54 seconds
Started Aug 02 04:40:01 PM PDT 24
Finished Aug 02 04:45:28 PM PDT 24
Peak memory 183260 kb
Host smart-15f9e125-f68d-4603-bec8-6769a9e77c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781397878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.781397878
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.2163611873
Short name T318
Test name
Test status
Simulation time 202428994873 ps
CPU time 109.02 seconds
Started Aug 02 04:40:11 PM PDT 24
Finished Aug 02 04:42:00 PM PDT 24
Peak memory 191504 kb
Host smart-909d5ce5-d6ff-42fc-9639-719f5f62a8ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163611873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.2163611873
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.2937766382
Short name T255
Test name
Test status
Simulation time 77986372565 ps
CPU time 741.11 seconds
Started Aug 02 04:39:53 PM PDT 24
Finished Aug 02 04:52:14 PM PDT 24
Peak memory 183340 kb
Host smart-74261546-4a83-4345-86d9-b2e991883001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937766382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.2937766382
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all_with_rand_reset.1812227728
Short name T37
Test name
Test status
Simulation time 24424255686 ps
CPU time 210.13 seconds
Started Aug 02 04:39:59 PM PDT 24
Finished Aug 02 04:43:29 PM PDT 24
Peak memory 206272 kb
Host smart-22722031-1cd7-4824-8371-330d17acb905
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812227728 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all_with_rand_reset.1812227728
Directory /workspace/31.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.1984680816
Short name T85
Test name
Test status
Simulation time 744389038452 ps
CPU time 398.51 seconds
Started Aug 02 04:39:48 PM PDT 24
Finished Aug 02 04:46:26 PM PDT 24
Peak memory 183296 kb
Host smart-822c96f3-df1f-445c-a89f-35c4587ae14e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984680816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.1984680816
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.2958822513
Short name T429
Test name
Test status
Simulation time 107811077522 ps
CPU time 46.49 seconds
Started Aug 02 04:39:48 PM PDT 24
Finished Aug 02 04:40:35 PM PDT 24
Peak memory 183240 kb
Host smart-505945c0-38eb-42db-abd6-c0a418f3327c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958822513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.2958822513
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.3546041570
Short name T352
Test name
Test status
Simulation time 62458184178 ps
CPU time 55.5 seconds
Started Aug 02 04:39:48 PM PDT 24
Finished Aug 02 04:40:44 PM PDT 24
Peak memory 183304 kb
Host smart-1a6e82af-4917-4b43-b5bb-a15ab3e5e585
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546041570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.3546041570
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.3412696061
Short name T449
Test name
Test status
Simulation time 35758791152 ps
CPU time 61.68 seconds
Started Aug 02 04:39:54 PM PDT 24
Finished Aug 02 04:40:56 PM PDT 24
Peak memory 191508 kb
Host smart-70664a88-d6d1-4c10-bc9f-3530e7e2086b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412696061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.3412696061
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.1102237692
Short name T307
Test name
Test status
Simulation time 982011046 ps
CPU time 1.41 seconds
Started Aug 02 04:39:48 PM PDT 24
Finished Aug 02 04:39:50 PM PDT 24
Peak memory 183048 kb
Host smart-abe0c82f-3c9b-4418-bef5-8ea010f2cce6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102237692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.1102237692
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.1682897635
Short name T409
Test name
Test status
Simulation time 939597956107 ps
CPU time 193.13 seconds
Started Aug 02 04:39:54 PM PDT 24
Finished Aug 02 04:43:07 PM PDT 24
Peak memory 183276 kb
Host smart-e24c2cf3-779f-4666-ac1f-9ad216510c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682897635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.1682897635
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all_with_rand_reset.574777623
Short name T42
Test name
Test status
Simulation time 17289076126 ps
CPU time 133.97 seconds
Started Aug 02 04:40:07 PM PDT 24
Finished Aug 02 04:42:21 PM PDT 24
Peak memory 198020 kb
Host smart-93fad0f6-d67d-4e73-a8c3-5cca9a693624
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574777623 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all_with_rand_reset.574777623
Directory /workspace/33.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.3888753997
Short name T349
Test name
Test status
Simulation time 697426472664 ps
CPU time 299.6 seconds
Started Aug 02 04:39:58 PM PDT 24
Finished Aug 02 04:44:58 PM PDT 24
Peak memory 183280 kb
Host smart-982cac7e-d7ce-4aa8-8f53-118fa0fea270
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888753997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.3888753997
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.1814227834
Short name T366
Test name
Test status
Simulation time 467630436823 ps
CPU time 96.64 seconds
Started Aug 02 04:39:58 PM PDT 24
Finished Aug 02 04:41:35 PM PDT 24
Peak memory 183332 kb
Host smart-fb092514-6de2-4bf1-8ef2-0492b28bfcea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814227834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.1814227834
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.2400910570
Short name T243
Test name
Test status
Simulation time 148641156739 ps
CPU time 331.14 seconds
Started Aug 02 04:40:06 PM PDT 24
Finished Aug 02 04:45:37 PM PDT 24
Peak memory 191452 kb
Host smart-6f26900a-b149-4d25-a9f3-001f2344e81f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400910570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.2400910570
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.991641508
Short name T281
Test name
Test status
Simulation time 273014570615 ps
CPU time 260.75 seconds
Started Aug 02 04:40:00 PM PDT 24
Finished Aug 02 04:44:21 PM PDT 24
Peak memory 183316 kb
Host smart-94b589b2-276f-4582-a82a-5d2fb45f0506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991641508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.991641508
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.1290156509
Short name T354
Test name
Test status
Simulation time 2471395415956 ps
CPU time 807.5 seconds
Started Aug 02 04:40:05 PM PDT 24
Finished Aug 02 04:53:32 PM PDT 24
Peak memory 183244 kb
Host smart-a7c6eadf-4ef1-4f39-8323-2548f4d2a3d6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290156509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.1290156509
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.2267791059
Short name T397
Test name
Test status
Simulation time 137700651367 ps
CPU time 194.59 seconds
Started Aug 02 04:39:58 PM PDT 24
Finished Aug 02 04:43:13 PM PDT 24
Peak memory 183384 kb
Host smart-bfca6e76-e046-4ce0-9cd6-2994084bdef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267791059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.2267791059
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.192121562
Short name T154
Test name
Test status
Simulation time 33041263087 ps
CPU time 183.44 seconds
Started Aug 02 04:39:50 PM PDT 24
Finished Aug 02 04:42:53 PM PDT 24
Peak memory 191492 kb
Host smart-7d674bf9-206b-407c-8ae8-5260574526b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192121562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.192121562
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all_with_rand_reset.626703288
Short name T38
Test name
Test status
Simulation time 40388248896 ps
CPU time 388.14 seconds
Started Aug 02 04:40:02 PM PDT 24
Finished Aug 02 04:46:30 PM PDT 24
Peak memory 206220 kb
Host smart-62185759-de75-4122-a2f2-01d104bdb247
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626703288 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all_with_rand_reset.626703288
Directory /workspace/35.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.3045184745
Short name T254
Test name
Test status
Simulation time 223562006711 ps
CPU time 105.95 seconds
Started Aug 02 04:40:03 PM PDT 24
Finished Aug 02 04:41:50 PM PDT 24
Peak memory 183284 kb
Host smart-5f1a4386-a57e-4c3a-9042-a30ee51dadeb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045184745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.3045184745
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.1533021561
Short name T405
Test name
Test status
Simulation time 45454176857 ps
CPU time 62.48 seconds
Started Aug 02 04:39:53 PM PDT 24
Finished Aug 02 04:40:56 PM PDT 24
Peak memory 183340 kb
Host smart-6fffbb7f-def3-40db-a3af-10205fc4c897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533021561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.1533021561
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.3798503245
Short name T392
Test name
Test status
Simulation time 61249832574 ps
CPU time 31.46 seconds
Started Aug 02 04:39:49 PM PDT 24
Finished Aug 02 04:40:21 PM PDT 24
Peak memory 183316 kb
Host smart-dfa279f5-2ab3-49e3-9978-9b17285901ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798503245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.3798503245
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.526538033
Short name T132
Test name
Test status
Simulation time 214610245232 ps
CPU time 86.46 seconds
Started Aug 02 04:40:01 PM PDT 24
Finished Aug 02 04:41:28 PM PDT 24
Peak memory 191564 kb
Host smart-85875d37-94c8-415a-9457-9967886f4efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526538033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.526538033
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.3670710116
Short name T70
Test name
Test status
Simulation time 394357720461 ps
CPU time 1113.08 seconds
Started Aug 02 04:39:53 PM PDT 24
Finished Aug 02 04:58:26 PM PDT 24
Peak memory 191572 kb
Host smart-0dae796a-95e6-4c60-b471-b5846b466a98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670710116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.3670710116
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.271124113
Short name T324
Test name
Test status
Simulation time 7504094934 ps
CPU time 13.16 seconds
Started Aug 02 04:40:08 PM PDT 24
Finished Aug 02 04:40:21 PM PDT 24
Peak memory 183276 kb
Host smart-33db6547-e54b-4233-95e4-e6f0e8e99961
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271124113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.rv_timer_cfg_update_on_fly.271124113
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.3666814025
Short name T368
Test name
Test status
Simulation time 388359468009 ps
CPU time 143.26 seconds
Started Aug 02 04:39:49 PM PDT 24
Finished Aug 02 04:42:13 PM PDT 24
Peak memory 183320 kb
Host smart-36166b8f-c4f8-44be-b184-7d91df7d6152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666814025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.3666814025
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.1309259402
Short name T383
Test name
Test status
Simulation time 712563316966 ps
CPU time 179.34 seconds
Started Aug 02 04:39:51 PM PDT 24
Finished Aug 02 04:42:51 PM PDT 24
Peak memory 183312 kb
Host smart-e144d3ba-7cb1-4366-8c2e-8a91ff4d7012
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309259402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.1309259402
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.285410544
Short name T63
Test name
Test status
Simulation time 32898285849 ps
CPU time 19.99 seconds
Started Aug 02 04:40:03 PM PDT 24
Finished Aug 02 04:40:24 PM PDT 24
Peak memory 183352 kb
Host smart-4d0c853d-0898-4a53-ba8e-af2763a6fd7f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285410544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.rv_timer_cfg_update_on_fly.285410544
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.3986140395
Short name T412
Test name
Test status
Simulation time 138527257275 ps
CPU time 171.15 seconds
Started Aug 02 04:40:09 PM PDT 24
Finished Aug 02 04:43:00 PM PDT 24
Peak memory 183296 kb
Host smart-aa6cfe10-764c-4cc3-9c6d-190652e1c51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986140395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.3986140395
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.1661971566
Short name T346
Test name
Test status
Simulation time 113270800185 ps
CPU time 135.67 seconds
Started Aug 02 04:40:05 PM PDT 24
Finished Aug 02 04:42:20 PM PDT 24
Peak memory 183292 kb
Host smart-ef02c582-45ea-4d49-aba7-57965cbcf222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661971566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.1661971566
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.2630472662
Short name T309
Test name
Test status
Simulation time 43220843192 ps
CPU time 57.77 seconds
Started Aug 02 04:40:02 PM PDT 24
Finished Aug 02 04:41:00 PM PDT 24
Peak memory 192368 kb
Host smart-b1dd3184-16fb-4492-a855-1ceff50ab5bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630472662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.2630472662
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all_with_rand_reset.3208355066
Short name T41
Test name
Test status
Simulation time 71394057824 ps
CPU time 194.24 seconds
Started Aug 02 04:40:04 PM PDT 24
Finished Aug 02 04:43:19 PM PDT 24
Peak memory 206248 kb
Host smart-5cb3b94e-2550-4a00-9f53-c1c0a16cae6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208355066 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all_with_rand_reset.3208355066
Directory /workspace/38.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.2042859006
Short name T283
Test name
Test status
Simulation time 913773787615 ps
CPU time 437.32 seconds
Started Aug 02 04:40:09 PM PDT 24
Finished Aug 02 04:47:26 PM PDT 24
Peak memory 183296 kb
Host smart-f2730e9d-82b1-4c31-8cd9-cec131d2da0b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042859006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.2042859006
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.2371917602
Short name T425
Test name
Test status
Simulation time 674124849681 ps
CPU time 86.66 seconds
Started Aug 02 04:40:11 PM PDT 24
Finished Aug 02 04:41:38 PM PDT 24
Peak memory 183244 kb
Host smart-7825d025-432f-4389-a729-4dd5b3b432cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371917602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.2371917602
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.2622902871
Short name T275
Test name
Test status
Simulation time 215305888888 ps
CPU time 1000.34 seconds
Started Aug 02 04:40:07 PM PDT 24
Finished Aug 02 04:56:48 PM PDT 24
Peak memory 191552 kb
Host smart-fb44afd5-a93f-4e22-a1fa-48f14ae3868d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622902871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.2622902871
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.2565931985
Short name T92
Test name
Test status
Simulation time 99301828089 ps
CPU time 280.42 seconds
Started Aug 02 04:39:49 PM PDT 24
Finished Aug 02 04:44:30 PM PDT 24
Peak memory 195828 kb
Host smart-0c226784-58dd-4b61-9075-11e7a908b18e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565931985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.2565931985
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.1060211990
Short name T376
Test name
Test status
Simulation time 120390535420 ps
CPU time 152.61 seconds
Started Aug 02 04:39:33 PM PDT 24
Finished Aug 02 04:42:05 PM PDT 24
Peak memory 183280 kb
Host smart-77cc10f2-2b79-4a63-a236-89b4ea2d032f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060211990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.1060211990
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.957891030
Short name T320
Test name
Test status
Simulation time 88183494783 ps
CPU time 69.03 seconds
Started Aug 02 04:39:32 PM PDT 24
Finished Aug 02 04:40:41 PM PDT 24
Peak memory 183292 kb
Host smart-5a640738-c67a-4b39-92d2-a05c688c6753
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957891030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.957891030
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.1867662482
Short name T10
Test name
Test status
Simulation time 31699852233 ps
CPU time 18.25 seconds
Started Aug 02 04:39:46 PM PDT 24
Finished Aug 02 04:40:05 PM PDT 24
Peak memory 183272 kb
Host smart-73d5023e-d276-4394-9db6-1ea04bcf7ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867662482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.1867662482
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.10315714
Short name T21
Test name
Test status
Simulation time 202344394 ps
CPU time 0.92 seconds
Started Aug 02 04:39:43 PM PDT 24
Finished Aug 02 04:39:44 PM PDT 24
Peak memory 214956 kb
Host smart-0903ebae-81b9-41a4-8d3d-0ddee1ff8cdc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10315714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.10315714
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all_with_rand_reset.3701259803
Short name T14
Test name
Test status
Simulation time 36067474325 ps
CPU time 150.59 seconds
Started Aug 02 04:39:46 PM PDT 24
Finished Aug 02 04:42:17 PM PDT 24
Peak memory 197992 kb
Host smart-b7bc9e4e-d7ea-4b4f-a921-f7285a904194
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701259803 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all_with_rand_reset.3701259803
Directory /workspace/4.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.2329515322
Short name T253
Test name
Test status
Simulation time 547936572940 ps
CPU time 301.84 seconds
Started Aug 02 04:40:07 PM PDT 24
Finished Aug 02 04:45:09 PM PDT 24
Peak memory 183428 kb
Host smart-67606466-4c2b-4dfa-8d38-8c77fdf5bbe4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329515322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.2329515322
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.2108202516
Short name T48
Test name
Test status
Simulation time 131879906046 ps
CPU time 98.09 seconds
Started Aug 02 04:39:50 PM PDT 24
Finished Aug 02 04:41:28 PM PDT 24
Peak memory 183292 kb
Host smart-014a53e3-0402-42ec-8801-8c595d010921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108202516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.2108202516
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.3390679867
Short name T76
Test name
Test status
Simulation time 39825498112 ps
CPU time 33.82 seconds
Started Aug 02 04:39:52 PM PDT 24
Finished Aug 02 04:40:26 PM PDT 24
Peak memory 183252 kb
Host smart-b412b2d3-e2ee-4c5c-8b62-ece575d5c101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390679867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.3390679867
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.305458468
Short name T303
Test name
Test status
Simulation time 509836018757 ps
CPU time 451.44 seconds
Started Aug 02 04:39:58 PM PDT 24
Finished Aug 02 04:47:29 PM PDT 24
Peak memory 183272 kb
Host smart-5c68fc37-96d6-410d-af13-8d63aad51e7c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305458468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.rv_timer_cfg_update_on_fly.305458468
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.4226404612
Short name T418
Test name
Test status
Simulation time 95690194563 ps
CPU time 136.09 seconds
Started Aug 02 04:39:50 PM PDT 24
Finished Aug 02 04:42:06 PM PDT 24
Peak memory 183348 kb
Host smart-e848dc2f-b9ec-4e3a-9d67-146e8f01fbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226404612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.4226404612
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.3646488811
Short name T207
Test name
Test status
Simulation time 608327133576 ps
CPU time 190.56 seconds
Started Aug 02 04:40:06 PM PDT 24
Finished Aug 02 04:43:16 PM PDT 24
Peak memory 191508 kb
Host smart-e8b8def5-5886-4240-afe1-e427063e42f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646488811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.3646488811
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.3927842534
Short name T357
Test name
Test status
Simulation time 625728066203 ps
CPU time 315.7 seconds
Started Aug 02 04:40:00 PM PDT 24
Finished Aug 02 04:45:15 PM PDT 24
Peak memory 195916 kb
Host smart-67bcd68a-e4a4-4db3-b7ad-65cb41b98385
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927842534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.3927842534
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.729050392
Short name T378
Test name
Test status
Simulation time 10494826591 ps
CPU time 16.28 seconds
Started Aug 02 04:40:09 PM PDT 24
Finished Aug 02 04:40:26 PM PDT 24
Peak memory 183256 kb
Host smart-65e5b8df-d65e-4a51-8dcb-55293f57b1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729050392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.729050392
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.502432907
Short name T340
Test name
Test status
Simulation time 165813836160 ps
CPU time 294.87 seconds
Started Aug 02 04:40:08 PM PDT 24
Finished Aug 02 04:45:03 PM PDT 24
Peak memory 183296 kb
Host smart-e70988a1-9a35-4401-89a2-de5a9435852e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502432907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.502432907
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.3206262821
Short name T384
Test name
Test status
Simulation time 20826675879 ps
CPU time 17.28 seconds
Started Aug 02 04:40:06 PM PDT 24
Finished Aug 02 04:40:23 PM PDT 24
Peak memory 183296 kb
Host smart-cf5a76a6-f3a9-4b75-8ecb-6da52f4bfb00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206262821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.3206262821
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.3946860614
Short name T45
Test name
Test status
Simulation time 287453429381 ps
CPU time 789.04 seconds
Started Aug 02 04:40:09 PM PDT 24
Finished Aug 02 04:53:19 PM PDT 24
Peak memory 191472 kb
Host smart-806948c0-aca9-4b95-b52d-b8644833a7c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946860614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.3946860614
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.189037677
Short name T140
Test name
Test status
Simulation time 679751275049 ps
CPU time 364.39 seconds
Started Aug 02 04:40:09 PM PDT 24
Finished Aug 02 04:46:14 PM PDT 24
Peak memory 183360 kb
Host smart-dc7d44c9-edd1-4142-90c0-b40703ccebaa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189037677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.rv_timer_cfg_update_on_fly.189037677
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.3320760580
Short name T421
Test name
Test status
Simulation time 166691120745 ps
CPU time 230.05 seconds
Started Aug 02 04:40:09 PM PDT 24
Finished Aug 02 04:43:59 PM PDT 24
Peak memory 183188 kb
Host smart-7da300eb-99c2-48fa-aaba-9f0aa57fd7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320760580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.3320760580
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.1874448438
Short name T312
Test name
Test status
Simulation time 71769323891 ps
CPU time 117.42 seconds
Started Aug 02 04:40:02 PM PDT 24
Finished Aug 02 04:41:59 PM PDT 24
Peak memory 191568 kb
Host smart-0f620b1a-7210-49c4-abf4-e43b596af6ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874448438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.1874448438
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.2372195248
Short name T387
Test name
Test status
Simulation time 575672574 ps
CPU time 0.81 seconds
Started Aug 02 04:40:19 PM PDT 24
Finished Aug 02 04:40:20 PM PDT 24
Peak memory 191688 kb
Host smart-73fab051-6cc0-4d8e-9337-0280dec128f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372195248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.2372195248
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.82421453
Short name T197
Test name
Test status
Simulation time 61057259358 ps
CPU time 94.57 seconds
Started Aug 02 04:40:18 PM PDT 24
Finished Aug 02 04:41:53 PM PDT 24
Peak memory 183304 kb
Host smart-7a18da05-b5de-4e74-8e3a-c8da46a48638
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82421453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.rv_timer_cfg_update_on_fly.82421453
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.3464333096
Short name T328
Test name
Test status
Simulation time 120405847513 ps
CPU time 149.27 seconds
Started Aug 02 04:40:11 PM PDT 24
Finished Aug 02 04:42:41 PM PDT 24
Peak memory 183288 kb
Host smart-1e47e738-523f-4410-bb7c-55079daceb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464333096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.3464333096
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.4064283864
Short name T86
Test name
Test status
Simulation time 104208035 ps
CPU time 0.56 seconds
Started Aug 02 04:40:18 PM PDT 24
Finished Aug 02 04:40:18 PM PDT 24
Peak memory 183044 kb
Host smart-ce107e8b-0e66-4793-9e48-2b7646b7f37f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064283864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.4064283864
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.1307332241
Short name T327
Test name
Test status
Simulation time 32649335521 ps
CPU time 7.91 seconds
Started Aug 02 04:40:15 PM PDT 24
Finished Aug 02 04:40:23 PM PDT 24
Peak memory 183268 kb
Host smart-9f92c1cc-b549-4f93-8a60-945bf8b5ff7c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307332241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.1307332241
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.1506487713
Short name T367
Test name
Test status
Simulation time 37186703907 ps
CPU time 52.85 seconds
Started Aug 02 04:40:13 PM PDT 24
Finished Aug 02 04:41:06 PM PDT 24
Peak memory 183232 kb
Host smart-7b3ad8f2-1dc1-4935-bdae-b161a2bb1f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506487713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.1506487713
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.507593630
Short name T24
Test name
Test status
Simulation time 40647705277 ps
CPU time 337.07 seconds
Started Aug 02 04:40:13 PM PDT 24
Finished Aug 02 04:45:50 PM PDT 24
Peak memory 183292 kb
Host smart-812ad928-a057-4821-98cc-a964c70f1d7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507593630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.507593630
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.110768341
Short name T322
Test name
Test status
Simulation time 78726765006 ps
CPU time 118.44 seconds
Started Aug 02 04:40:19 PM PDT 24
Finished Aug 02 04:42:18 PM PDT 24
Peak memory 183264 kb
Host smart-d4a068b8-adcb-4905-a7ce-003f2cd424f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110768341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.110768341
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.1740521134
Short name T39
Test name
Test status
Simulation time 169312715678 ps
CPU time 174.96 seconds
Started Aug 02 04:40:14 PM PDT 24
Finished Aug 02 04:43:09 PM PDT 24
Peak memory 206196 kb
Host smart-9d4e5414-e8e7-489b-9be4-d361ec5878e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740521134 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all_with_rand_reset.1740521134
Directory /workspace/45.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.3757907191
Short name T249
Test name
Test status
Simulation time 239045170135 ps
CPU time 397.19 seconds
Started Aug 02 04:40:15 PM PDT 24
Finished Aug 02 04:46:57 PM PDT 24
Peak memory 183252 kb
Host smart-b8f04749-88d8-4ed5-9f92-f6b14bdaaa43
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757907191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.3757907191
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.3154727273
Short name T381
Test name
Test status
Simulation time 48559471380 ps
CPU time 63.8 seconds
Started Aug 02 04:40:12 PM PDT 24
Finished Aug 02 04:41:16 PM PDT 24
Peak memory 183304 kb
Host smart-3843bb82-7bdc-4880-a934-9e72add95f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154727273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.3154727273
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.3963922408
Short name T180
Test name
Test status
Simulation time 108626454060 ps
CPU time 89.49 seconds
Started Aug 02 04:40:05 PM PDT 24
Finished Aug 02 04:41:35 PM PDT 24
Peak memory 191516 kb
Host smart-fcd6c66d-be50-4203-a179-4bdfa12a9f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963922408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.3963922408
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.3242196288
Short name T25
Test name
Test status
Simulation time 131004640983 ps
CPU time 82.1 seconds
Started Aug 02 04:40:15 PM PDT 24
Finished Aug 02 04:41:37 PM PDT 24
Peak memory 183372 kb
Host smart-d41841c2-1657-4f2a-9921-33533380ba5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242196288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.3242196288
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.4131179931
Short name T344
Test name
Test status
Simulation time 128298444238 ps
CPU time 288.69 seconds
Started Aug 02 04:40:23 PM PDT 24
Finished Aug 02 04:45:12 PM PDT 24
Peak memory 183368 kb
Host smart-aabe2f0c-3486-48ec-aac4-394182805db4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131179931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.4131179931
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.1987812190
Short name T302
Test name
Test status
Simulation time 28824161019 ps
CPU time 44.45 seconds
Started Aug 02 04:40:08 PM PDT 24
Finished Aug 02 04:40:52 PM PDT 24
Peak memory 191524 kb
Host smart-c87699d7-c3d6-4801-b3f4-e1398a184ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987812190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.1987812190
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.3423306134
Short name T445
Test name
Test status
Simulation time 81658919 ps
CPU time 0.57 seconds
Started Aug 02 04:40:07 PM PDT 24
Finished Aug 02 04:40:08 PM PDT 24
Peak memory 183012 kb
Host smart-0cb01282-6d7b-47a9-ad90-45c78d7807c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423306134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.3423306134
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.2597949286
Short name T406
Test name
Test status
Simulation time 22798974744 ps
CPU time 11.21 seconds
Started Aug 02 04:40:15 PM PDT 24
Finished Aug 02 04:40:27 PM PDT 24
Peak memory 183312 kb
Host smart-cb2e464e-892b-47c6-a1de-6a6ad78e225e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597949286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.2597949286
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.3423467557
Short name T150
Test name
Test status
Simulation time 155722353727 ps
CPU time 65.87 seconds
Started Aug 02 04:40:12 PM PDT 24
Finished Aug 02 04:41:18 PM PDT 24
Peak memory 183356 kb
Host smart-6b6f6bc0-36c2-4324-9426-5f170d94073f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423467557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.3423467557
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.1037998784
Short name T350
Test name
Test status
Simulation time 923617560674 ps
CPU time 1110.97 seconds
Started Aug 02 04:40:06 PM PDT 24
Finished Aug 02 04:58:38 PM PDT 24
Peak memory 191504 kb
Host smart-711db920-89f4-45a0-8042-73e7b43dd9d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037998784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.1037998784
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.3315831375
Short name T66
Test name
Test status
Simulation time 103034469469 ps
CPU time 50.16 seconds
Started Aug 02 04:40:08 PM PDT 24
Finished Aug 02 04:40:59 PM PDT 24
Peak memory 183248 kb
Host smart-6e7d098b-776e-471c-a739-6e98bd5c5484
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315831375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.3315831375
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.362899785
Short name T379
Test name
Test status
Simulation time 70393552988 ps
CPU time 29.27 seconds
Started Aug 02 04:40:11 PM PDT 24
Finished Aug 02 04:40:41 PM PDT 24
Peak memory 183348 kb
Host smart-3cef78b7-2190-432b-9710-1871b34e3cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362899785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.362899785
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.3439072392
Short name T279
Test name
Test status
Simulation time 42820795053 ps
CPU time 308.83 seconds
Started Aug 02 04:40:08 PM PDT 24
Finished Aug 02 04:45:17 PM PDT 24
Peak memory 191452 kb
Host smart-b61eb834-6c6e-41a7-98ea-1abaf5fb4573
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439072392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.3439072392
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.314263067
Short name T430
Test name
Test status
Simulation time 1664915347 ps
CPU time 1.28 seconds
Started Aug 02 04:40:15 PM PDT 24
Finished Aug 02 04:40:16 PM PDT 24
Peak memory 183020 kb
Host smart-7cba0616-9db3-4db8-9594-33d8130969ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314263067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.314263067
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.1252370969
Short name T440
Test name
Test status
Simulation time 50805377233 ps
CPU time 71.95 seconds
Started Aug 02 04:39:36 PM PDT 24
Finished Aug 02 04:40:48 PM PDT 24
Peak memory 183268 kb
Host smart-f5ea159f-226a-4f76-b749-58165c87416e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252370969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.1252370969
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.3881468580
Short name T400
Test name
Test status
Simulation time 213650890 ps
CPU time 0.75 seconds
Started Aug 02 04:39:32 PM PDT 24
Finished Aug 02 04:39:33 PM PDT 24
Peak memory 183044 kb
Host smart-83a739b8-c063-4f83-a38f-519cb60cb1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881468580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.3881468580
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.1859791528
Short name T403
Test name
Test status
Simulation time 419546069768 ps
CPU time 109.25 seconds
Started Aug 02 04:39:50 PM PDT 24
Finished Aug 02 04:41:39 PM PDT 24
Peak memory 183284 kb
Host smart-e1399111-3986-4602-9f71-319115c98d17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859791528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
1859791528
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/50.rv_timer_random.3966258850
Short name T326
Test name
Test status
Simulation time 143233319955 ps
CPU time 371.02 seconds
Started Aug 02 04:40:13 PM PDT 24
Finished Aug 02 04:46:24 PM PDT 24
Peak memory 191404 kb
Host smart-fec09243-7a32-4007-b045-d883c883e04e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966258850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.3966258850
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.2617125273
Short name T124
Test name
Test status
Simulation time 410148807741 ps
CPU time 2156.8 seconds
Started Aug 02 04:40:02 PM PDT 24
Finished Aug 02 05:15:59 PM PDT 24
Peak memory 191492 kb
Host smart-387ea687-e22b-4fa2-b8a2-df358a0227df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617125273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.2617125273
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.265623044
Short name T291
Test name
Test status
Simulation time 227446095515 ps
CPU time 436.37 seconds
Started Aug 02 04:40:27 PM PDT 24
Finished Aug 02 04:47:43 PM PDT 24
Peak memory 191596 kb
Host smart-542bafbd-deb7-433b-9c01-6e8c65195899
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265623044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.265623044
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.838748762
Short name T332
Test name
Test status
Simulation time 308705048634 ps
CPU time 79.33 seconds
Started Aug 02 04:40:09 PM PDT 24
Finished Aug 02 04:41:28 PM PDT 24
Peak memory 183324 kb
Host smart-66659278-4928-4393-8505-08a43f358347
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838748762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.838748762
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.2930777926
Short name T130
Test name
Test status
Simulation time 86089794246 ps
CPU time 180.66 seconds
Started Aug 02 04:40:12 PM PDT 24
Finished Aug 02 04:43:12 PM PDT 24
Peak memory 191464 kb
Host smart-ebde3afc-8e08-4df6-9df8-fd8558b4a72a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930777926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.2930777926
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.1196404414
Short name T61
Test name
Test status
Simulation time 176747799793 ps
CPU time 151.87 seconds
Started Aug 02 04:40:12 PM PDT 24
Finished Aug 02 04:42:44 PM PDT 24
Peak memory 191520 kb
Host smart-82c2d6dd-6591-4b24-add7-b669440d0ecc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196404414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.1196404414
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.3142897413
Short name T450
Test name
Test status
Simulation time 378200803868 ps
CPU time 239.05 seconds
Started Aug 02 04:40:12 PM PDT 24
Finished Aug 02 04:44:11 PM PDT 24
Peak memory 191496 kb
Host smart-00f2169a-32c1-4894-9891-7a552dc7c0bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142897413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.3142897413
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.3863246158
Short name T336
Test name
Test status
Simulation time 453907464833 ps
CPU time 243.87 seconds
Started Aug 02 04:40:15 PM PDT 24
Finished Aug 02 04:44:19 PM PDT 24
Peak memory 191496 kb
Host smart-8e057311-c121-4fe1-98e1-edbeb2ea7335
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863246158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.3863246158
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.3593151921
Short name T179
Test name
Test status
Simulation time 82573936317 ps
CPU time 167.72 seconds
Started Aug 02 04:40:13 PM PDT 24
Finished Aug 02 04:43:01 PM PDT 24
Peak memory 191488 kb
Host smart-0b481f04-b3b1-43fd-a188-f14f3b710ed4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593151921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.3593151921
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.2246716959
Short name T220
Test name
Test status
Simulation time 88131716114 ps
CPU time 47.17 seconds
Started Aug 02 04:40:08 PM PDT 24
Finished Aug 02 04:40:55 PM PDT 24
Peak memory 183320 kb
Host smart-0d9d2729-50c3-4043-b497-872a257b8d99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246716959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.2246716959
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.2043994436
Short name T333
Test name
Test status
Simulation time 71207003487 ps
CPU time 38.27 seconds
Started Aug 02 04:39:43 PM PDT 24
Finished Aug 02 04:40:22 PM PDT 24
Peak memory 183304 kb
Host smart-340897ea-348e-4a02-8b63-66a4395f1681
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043994436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.2043994436
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.2300241302
Short name T386
Test name
Test status
Simulation time 84814876914 ps
CPU time 64.9 seconds
Started Aug 02 04:39:50 PM PDT 24
Finished Aug 02 04:40:55 PM PDT 24
Peak memory 183312 kb
Host smart-04dd63b2-d969-4b79-bc52-78e9f939f6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300241302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.2300241302
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.3582441823
Short name T145
Test name
Test status
Simulation time 551176811429 ps
CPU time 987.47 seconds
Started Aug 02 04:40:04 PM PDT 24
Finished Aug 02 04:56:31 PM PDT 24
Peak memory 191456 kb
Host smart-1d378d23-aad0-492c-ab62-77c5f116f361
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582441823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.3582441823
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.1493104229
Short name T51
Test name
Test status
Simulation time 36041571832 ps
CPU time 53 seconds
Started Aug 02 04:39:42 PM PDT 24
Finished Aug 02 04:40:35 PM PDT 24
Peak memory 191528 kb
Host smart-6c01546a-3e58-4e83-93a2-03e1482f36c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493104229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.1493104229
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.881253895
Short name T26
Test name
Test status
Simulation time 2715854078265 ps
CPU time 1029.03 seconds
Started Aug 02 04:39:36 PM PDT 24
Finished Aug 02 04:56:46 PM PDT 24
Peak memory 191520 kb
Host smart-bf70d841-a763-4919-8189-0babfdad01f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881253895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.881253895
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/60.rv_timer_random.2135252548
Short name T136
Test name
Test status
Simulation time 428635221801 ps
CPU time 1305.41 seconds
Started Aug 02 04:40:15 PM PDT 24
Finished Aug 02 05:02:01 PM PDT 24
Peak memory 191496 kb
Host smart-9705c902-4769-45aa-9c94-bc943d4d05ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135252548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.2135252548
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.1042602245
Short name T44
Test name
Test status
Simulation time 88405704975 ps
CPU time 161.47 seconds
Started Aug 02 04:40:15 PM PDT 24
Finished Aug 02 04:42:56 PM PDT 24
Peak memory 191504 kb
Host smart-bc43e99d-d736-49a3-999e-a4f0edb184e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042602245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.1042602245
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.1351688220
Short name T240
Test name
Test status
Simulation time 57851632557 ps
CPU time 148.36 seconds
Started Aug 02 04:40:10 PM PDT 24
Finished Aug 02 04:42:38 PM PDT 24
Peak memory 191488 kb
Host smart-d5266c34-7c3a-43ea-b86e-8b80b7d32179
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351688220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.1351688220
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.3852631267
Short name T182
Test name
Test status
Simulation time 182750124918 ps
CPU time 289.96 seconds
Started Aug 02 04:40:05 PM PDT 24
Finished Aug 02 04:44:55 PM PDT 24
Peak memory 191524 kb
Host smart-0c5a0d48-e9c3-468c-912d-5e69bb165603
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852631267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.3852631267
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.2637000834
Short name T52
Test name
Test status
Simulation time 65343036461 ps
CPU time 489 seconds
Started Aug 02 04:40:20 PM PDT 24
Finished Aug 02 04:48:30 PM PDT 24
Peak memory 191316 kb
Host smart-d776e979-b431-46af-b85a-7b5ae4f55341
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637000834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.2637000834
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.1483694325
Short name T301
Test name
Test status
Simulation time 679869868417 ps
CPU time 271.79 seconds
Started Aug 02 04:40:15 PM PDT 24
Finished Aug 02 04:44:47 PM PDT 24
Peak memory 191496 kb
Host smart-23133675-182f-48e2-8e8c-6a75fe12e3a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483694325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.1483694325
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.4026570076
Short name T265
Test name
Test status
Simulation time 35533579142 ps
CPU time 174.83 seconds
Started Aug 02 04:40:17 PM PDT 24
Finished Aug 02 04:43:12 PM PDT 24
Peak memory 183304 kb
Host smart-b1fad3c7-7a3d-486b-bd74-e6c822736cad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026570076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.4026570076
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.2454949423
Short name T155
Test name
Test status
Simulation time 51036169703 ps
CPU time 176.89 seconds
Started Aug 02 04:40:12 PM PDT 24
Finished Aug 02 04:43:09 PM PDT 24
Peak memory 191496 kb
Host smart-6a2a4c5c-7c95-4f18-9660-93bc47ec8bd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454949423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.2454949423
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.2979174867
Short name T194
Test name
Test status
Simulation time 49699329535 ps
CPU time 80.56 seconds
Started Aug 02 04:39:35 PM PDT 24
Finished Aug 02 04:40:56 PM PDT 24
Peak memory 183288 kb
Host smart-2f81f755-846b-46e7-878f-449d25229688
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979174867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.2979174867
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.3406576160
Short name T375
Test name
Test status
Simulation time 532415638196 ps
CPU time 126.03 seconds
Started Aug 02 04:39:48 PM PDT 24
Finished Aug 02 04:41:54 PM PDT 24
Peak memory 183320 kb
Host smart-0ac4bf07-5b36-4ace-9092-a6e69e4acaf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406576160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.3406576160
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.3037836283
Short name T29
Test name
Test status
Simulation time 110732483770 ps
CPU time 104.81 seconds
Started Aug 02 04:39:48 PM PDT 24
Finished Aug 02 04:41:33 PM PDT 24
Peak memory 183316 kb
Host smart-1033ca94-a521-4efd-b3c9-cf234859763f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037836283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.3037836283
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.2167737738
Short name T394
Test name
Test status
Simulation time 1415610315 ps
CPU time 1.42 seconds
Started Aug 02 04:39:40 PM PDT 24
Finished Aug 02 04:39:41 PM PDT 24
Peak memory 191440 kb
Host smart-6890b641-f12e-47ee-b0a2-efe8334ebecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167737738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.2167737738
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.1510247959
Short name T448
Test name
Test status
Simulation time 29775229811 ps
CPU time 335.35 seconds
Started Aug 02 04:39:50 PM PDT 24
Finished Aug 02 04:45:26 PM PDT 24
Peak memory 198032 kb
Host smart-69871e12-7134-43a7-ab1c-902365c28ecf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510247959 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all_with_rand_reset.1510247959
Directory /workspace/7.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.453013251
Short name T211
Test name
Test status
Simulation time 162717496580 ps
CPU time 152.37 seconds
Started Aug 02 04:40:07 PM PDT 24
Finished Aug 02 04:42:40 PM PDT 24
Peak memory 191512 kb
Host smart-48dfdb78-df03-44f3-8874-b372e4d19320
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453013251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.453013251
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.2721362388
Short name T80
Test name
Test status
Simulation time 101329563060 ps
CPU time 296.82 seconds
Started Aug 02 04:40:13 PM PDT 24
Finished Aug 02 04:45:10 PM PDT 24
Peak memory 183304 kb
Host smart-00426fa0-1466-49af-aedd-49f210f1eaac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721362388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.2721362388
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.2724746398
Short name T1
Test name
Test status
Simulation time 159908351082 ps
CPU time 527.44 seconds
Started Aug 02 04:40:18 PM PDT 24
Finished Aug 02 04:49:06 PM PDT 24
Peak memory 191444 kb
Host smart-8b8f0d38-d956-4207-a5f2-5c683ccb0252
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724746398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.2724746398
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.1657452000
Short name T256
Test name
Test status
Simulation time 772427871203 ps
CPU time 885.49 seconds
Started Aug 02 04:40:25 PM PDT 24
Finished Aug 02 04:55:11 PM PDT 24
Peak memory 191452 kb
Host smart-82e216f3-f59a-4414-bb22-bcc369488878
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657452000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.1657452000
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.2950893026
Short name T415
Test name
Test status
Simulation time 34434326905 ps
CPU time 56.02 seconds
Started Aug 02 04:40:25 PM PDT 24
Finished Aug 02 04:41:21 PM PDT 24
Peak memory 191640 kb
Host smart-4e15d6e8-22c8-4fd3-ab7c-72dbcd2d578b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950893026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.2950893026
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.1813439734
Short name T262
Test name
Test status
Simulation time 649731659601 ps
CPU time 281.76 seconds
Started Aug 02 04:40:35 PM PDT 24
Finished Aug 02 04:45:16 PM PDT 24
Peak memory 191392 kb
Host smart-a603840c-f4b2-4f3f-af67-ff97ea9e9949
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813439734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.1813439734
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.949773166
Short name T187
Test name
Test status
Simulation time 158727683589 ps
CPU time 660.4 seconds
Started Aug 02 04:40:17 PM PDT 24
Finished Aug 02 04:51:17 PM PDT 24
Peak memory 191516 kb
Host smart-b22aa509-c779-4897-8135-b7d0418d4029
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949773166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.949773166
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.2872902629
Short name T143
Test name
Test status
Simulation time 52064520729 ps
CPU time 92.44 seconds
Started Aug 02 04:40:27 PM PDT 24
Finished Aug 02 04:41:59 PM PDT 24
Peak memory 183440 kb
Host smart-f7b79019-b4b2-434c-8492-8810e414e544
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872902629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.2872902629
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.1539306934
Short name T348
Test name
Test status
Simulation time 39508781383 ps
CPU time 931.61 seconds
Started Aug 02 04:40:15 PM PDT 24
Finished Aug 02 04:55:47 PM PDT 24
Peak memory 191524 kb
Host smart-1703a139-5945-4ff6-afc9-6a2770ba3b69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539306934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.1539306934
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.261640500
Short name T296
Test name
Test status
Simulation time 163447051394 ps
CPU time 211.71 seconds
Started Aug 02 04:40:16 PM PDT 24
Finished Aug 02 04:43:48 PM PDT 24
Peak memory 191576 kb
Host smart-eff7d593-73ff-4836-a807-f44c297403f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261640500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.261640500
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.2111917856
Short name T9
Test name
Test status
Simulation time 347591270509 ps
CPU time 580.68 seconds
Started Aug 02 04:39:35 PM PDT 24
Finished Aug 02 04:49:16 PM PDT 24
Peak memory 183392 kb
Host smart-3aad487b-b061-43f0-b4ae-407f73a6b223
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111917856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.2111917856
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_random.2474559264
Short name T193
Test name
Test status
Simulation time 182947658980 ps
CPU time 774.22 seconds
Started Aug 02 04:39:33 PM PDT 24
Finished Aug 02 04:52:27 PM PDT 24
Peak memory 191484 kb
Host smart-c98f4fc6-8afe-46fc-824d-69c196801c93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474559264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.2474559264
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.4286015575
Short name T174
Test name
Test status
Simulation time 42162374368 ps
CPU time 87.22 seconds
Started Aug 02 04:39:38 PM PDT 24
Finished Aug 02 04:41:05 PM PDT 24
Peak memory 191524 kb
Host smart-a5c27b89-e5d4-46cc-b1a0-508c64f90c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286015575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.4286015575
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all_with_rand_reset.4001030307
Short name T442
Test name
Test status
Simulation time 94341084661 ps
CPU time 377.32 seconds
Started Aug 02 04:39:36 PM PDT 24
Finished Aug 02 04:45:53 PM PDT 24
Peak memory 198004 kb
Host smart-651edee8-4352-4cf0-9be4-0a1b23b14c30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001030307 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all_with_rand_reset.4001030307
Directory /workspace/8.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.3713416245
Short name T167
Test name
Test status
Simulation time 104438075998 ps
CPU time 150.95 seconds
Started Aug 02 04:40:15 PM PDT 24
Finished Aug 02 04:42:46 PM PDT 24
Peak memory 195060 kb
Host smart-3217b5a3-c480-4d2a-9d7a-c98d844809be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713416245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.3713416245
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.2815649902
Short name T325
Test name
Test status
Simulation time 15274210936 ps
CPU time 146.31 seconds
Started Aug 02 04:40:17 PM PDT 24
Finished Aug 02 04:42:44 PM PDT 24
Peak memory 183348 kb
Host smart-814a88ee-5935-467b-b077-08588043fa8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815649902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.2815649902
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.2506298802
Short name T248
Test name
Test status
Simulation time 504575156822 ps
CPU time 242.9 seconds
Started Aug 02 04:40:23 PM PDT 24
Finished Aug 02 04:44:26 PM PDT 24
Peak memory 193940 kb
Host smart-7b209032-82f1-4d10-9f6f-d1c8408a1b86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506298802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.2506298802
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.139141249
Short name T317
Test name
Test status
Simulation time 46927280416 ps
CPU time 69.32 seconds
Started Aug 02 04:40:16 PM PDT 24
Finished Aug 02 04:41:25 PM PDT 24
Peak memory 183308 kb
Host smart-020f0469-aad7-47e3-ac67-7b5081f278c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139141249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.139141249
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.4140049109
Short name T162
Test name
Test status
Simulation time 56704244335 ps
CPU time 184.14 seconds
Started Aug 02 04:40:50 PM PDT 24
Finished Aug 02 04:43:54 PM PDT 24
Peak memory 191424 kb
Host smart-50150f69-3b6f-4c5e-8d93-43ccf73e1137
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140049109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.4140049109
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.2037431104
Short name T237
Test name
Test status
Simulation time 226861411787 ps
CPU time 693.08 seconds
Started Aug 02 04:40:23 PM PDT 24
Finished Aug 02 04:51:56 PM PDT 24
Peak memory 191520 kb
Host smart-7f40d29f-6b1f-4ca0-872d-ef85a6663cc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037431104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.2037431104
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.4177050895
Short name T67
Test name
Test status
Simulation time 359934170139 ps
CPU time 377.93 seconds
Started Aug 02 04:40:11 PM PDT 24
Finished Aug 02 04:46:30 PM PDT 24
Peak memory 191520 kb
Host smart-19a0c68b-82b0-463a-970e-30860f0c6990
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177050895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.4177050895
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.4046888854
Short name T239
Test name
Test status
Simulation time 442499662260 ps
CPU time 704.18 seconds
Started Aug 02 04:40:30 PM PDT 24
Finished Aug 02 04:52:14 PM PDT 24
Peak memory 191512 kb
Host smart-62714f55-2524-4105-a657-468f8a0d433b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046888854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.4046888854
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.3221021001
Short name T229
Test name
Test status
Simulation time 834799348562 ps
CPU time 1043.04 seconds
Started Aug 02 04:40:28 PM PDT 24
Finished Aug 02 04:57:51 PM PDT 24
Peak memory 191648 kb
Host smart-7466575b-bf70-41f8-ad88-77fe3de6e8ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221021001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.3221021001
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.4262705935
Short name T431
Test name
Test status
Simulation time 12664610705 ps
CPU time 22.01 seconds
Started Aug 02 04:39:36 PM PDT 24
Finished Aug 02 04:39:58 PM PDT 24
Peak memory 183292 kb
Host smart-381117ad-0905-4331-b120-1ef05bf21d9d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262705935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.4262705935
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.894089660
Short name T374
Test name
Test status
Simulation time 246865957805 ps
CPU time 101.82 seconds
Started Aug 02 04:39:34 PM PDT 24
Finished Aug 02 04:41:16 PM PDT 24
Peak memory 182988 kb
Host smart-183af9f7-de94-42c0-92ed-35f564b6d9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894089660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.894089660
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.2593435815
Short name T246
Test name
Test status
Simulation time 107328220859 ps
CPU time 113.84 seconds
Started Aug 02 04:39:35 PM PDT 24
Finished Aug 02 04:41:29 PM PDT 24
Peak memory 191576 kb
Host smart-d26eb664-5871-41ee-8e95-42ad42b2fe67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593435815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.2593435815
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.2792500257
Short name T396
Test name
Test status
Simulation time 487222883 ps
CPU time 1.02 seconds
Started Aug 02 04:39:37 PM PDT 24
Finished Aug 02 04:39:39 PM PDT 24
Peak memory 183080 kb
Host smart-439c2819-0303-40ed-adbe-419b025a8d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792500257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.2792500257
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.2581097655
Short name T447
Test name
Test status
Simulation time 360747148252 ps
CPU time 670.2 seconds
Started Aug 02 04:39:35 PM PDT 24
Finished Aug 02 04:50:45 PM PDT 24
Peak memory 195180 kb
Host smart-b436cd40-f284-43f7-a1d4-a88429657778
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581097655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
2581097655
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/91.rv_timer_random.2990780525
Short name T91
Test name
Test status
Simulation time 7333709985 ps
CPU time 11.7 seconds
Started Aug 02 04:40:29 PM PDT 24
Finished Aug 02 04:40:41 PM PDT 24
Peak memory 183288 kb
Host smart-c7558359-efc1-4e16-8188-5a5035d93ae8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990780525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.2990780525
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.3007781548
Short name T210
Test name
Test status
Simulation time 5799297076 ps
CPU time 9.42 seconds
Started Aug 02 04:40:17 PM PDT 24
Finished Aug 02 04:40:27 PM PDT 24
Peak memory 183244 kb
Host smart-376d6fc2-8d33-4045-a7ce-d648b1d22b33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007781548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.3007781548
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.4164513722
Short name T250
Test name
Test status
Simulation time 375136869895 ps
CPU time 174.25 seconds
Started Aug 02 04:40:21 PM PDT 24
Finished Aug 02 04:43:15 PM PDT 24
Peak memory 194284 kb
Host smart-a6fbbb01-a897-4f09-a02c-25dd7008cc2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164513722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.4164513722
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.3489532731
Short name T142
Test name
Test status
Simulation time 146362415584 ps
CPU time 329.04 seconds
Started Aug 02 04:40:20 PM PDT 24
Finished Aug 02 04:45:49 PM PDT 24
Peak memory 191504 kb
Host smart-d588e662-3f2d-4fe5-ad85-17028d4338c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489532731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.3489532731
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.4010363350
Short name T264
Test name
Test status
Simulation time 342970114951 ps
CPU time 145.4 seconds
Started Aug 02 04:40:19 PM PDT 24
Finished Aug 02 04:42:45 PM PDT 24
Peak memory 191548 kb
Host smart-1d4c266a-c146-4803-9510-a113af4c544d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010363350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.4010363350
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.4051700865
Short name T4
Test name
Test status
Simulation time 34796026783 ps
CPU time 146.57 seconds
Started Aug 02 04:40:26 PM PDT 24
Finished Aug 02 04:42:53 PM PDT 24
Peak memory 191512 kb
Host smart-18b97e59-3fda-4086-be5e-bee2c68f2e1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051700865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.4051700865
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.1482723835
Short name T125
Test name
Test status
Simulation time 51145637870 ps
CPU time 74.97 seconds
Started Aug 02 04:40:24 PM PDT 24
Finished Aug 02 04:41:40 PM PDT 24
Peak memory 191452 kb
Host smart-33b6e30a-93ec-4a25-84c4-a234fb1d0e4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482723835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.1482723835
Directory /workspace/99.rv_timer_random/latest
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