Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.55 99.36 98.73 100.00 100.00 100.00 99.21


Total test records in report: 585
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T111 /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.870724190 Aug 03 04:23:19 PM PDT 24 Aug 03 04:23:21 PM PDT 24 995895423 ps
T508 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3810165376 Aug 03 04:24:08 PM PDT 24 Aug 03 04:24:10 PM PDT 24 293935796 ps
T105 /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1190532091 Aug 03 04:22:02 PM PDT 24 Aug 03 04:22:03 PM PDT 24 14519788 ps
T509 /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.597934945 Aug 03 04:22:29 PM PDT 24 Aug 03 04:22:30 PM PDT 24 279727131 ps
T510 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.3783610535 Aug 03 04:22:03 PM PDT 24 Aug 03 04:22:05 PM PDT 24 124510261 ps
T95 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.3213347690 Aug 03 04:23:26 PM PDT 24 Aug 03 04:23:27 PM PDT 24 18443416 ps
T511 /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.380938481 Aug 03 04:23:40 PM PDT 24 Aug 03 04:23:40 PM PDT 24 18378766 ps
T512 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.1940009109 Aug 03 04:22:16 PM PDT 24 Aug 03 04:22:18 PM PDT 24 217252666 ps
T513 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.734723747 Aug 03 04:21:53 PM PDT 24 Aug 03 04:21:55 PM PDT 24 312515477 ps
T514 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.276538591 Aug 03 04:23:25 PM PDT 24 Aug 03 04:23:27 PM PDT 24 926910053 ps
T515 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1602403910 Aug 03 04:22:07 PM PDT 24 Aug 03 04:22:09 PM PDT 24 88411284 ps
T516 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2482179407 Aug 03 04:23:23 PM PDT 24 Aug 03 04:23:25 PM PDT 24 1859546701 ps
T517 /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.1849185726 Aug 03 04:23:13 PM PDT 24 Aug 03 04:23:14 PM PDT 24 150996684 ps
T518 /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.311168555 Aug 03 04:23:30 PM PDT 24 Aug 03 04:23:31 PM PDT 24 69795087 ps
T519 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.641627242 Aug 03 04:23:33 PM PDT 24 Aug 03 04:23:34 PM PDT 24 64744926 ps
T520 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.949820523 Aug 03 04:23:17 PM PDT 24 Aug 03 04:23:18 PM PDT 24 108329811 ps
T521 /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.1707424649 Aug 03 04:23:39 PM PDT 24 Aug 03 04:23:40 PM PDT 24 96427999 ps
T522 /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.1716978695 Aug 03 04:22:23 PM PDT 24 Aug 03 04:22:23 PM PDT 24 17353242 ps
T523 /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.1598455467 Aug 03 04:23:29 PM PDT 24 Aug 03 04:23:30 PM PDT 24 50086410 ps
T524 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.4293293620 Aug 03 04:23:12 PM PDT 24 Aug 03 04:23:13 PM PDT 24 47410459 ps
T525 /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.1456414077 Aug 03 04:23:25 PM PDT 24 Aug 03 04:23:27 PM PDT 24 202695984 ps
T526 /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.4082639526 Aug 03 04:23:33 PM PDT 24 Aug 03 04:23:34 PM PDT 24 90043220 ps
T96 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.2792784079 Aug 03 04:23:32 PM PDT 24 Aug 03 04:23:33 PM PDT 24 15282576 ps
T527 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.1538671420 Aug 03 04:23:13 PM PDT 24 Aug 03 04:23:14 PM PDT 24 27442492 ps
T528 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.2040302178 Aug 03 04:22:15 PM PDT 24 Aug 03 04:22:16 PM PDT 24 53049956 ps
T97 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.67119866 Aug 03 04:23:21 PM PDT 24 Aug 03 04:23:21 PM PDT 24 13918719 ps
T529 /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.4000912643 Aug 03 04:22:22 PM PDT 24 Aug 03 04:22:22 PM PDT 24 58873980 ps
T530 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.4105385990 Aug 03 04:21:55 PM PDT 24 Aug 03 04:21:56 PM PDT 24 51851150 ps
T531 /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.3292205642 Aug 03 04:22:41 PM PDT 24 Aug 03 04:22:41 PM PDT 24 99259663 ps
T532 /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.985696452 Aug 03 04:22:15 PM PDT 24 Aug 03 04:22:16 PM PDT 24 39821213 ps
T533 /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.3941951616 Aug 03 04:23:39 PM PDT 24 Aug 03 04:23:40 PM PDT 24 52182981 ps
T534 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1946049058 Aug 03 04:23:13 PM PDT 24 Aug 03 04:23:14 PM PDT 24 93264931 ps
T535 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3828262709 Aug 03 04:23:33 PM PDT 24 Aug 03 04:23:33 PM PDT 24 60337262 ps
T536 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.3060748352 Aug 03 04:23:44 PM PDT 24 Aug 03 04:23:45 PM PDT 24 50026448 ps
T537 /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.831982434 Aug 03 04:23:28 PM PDT 24 Aug 03 04:23:29 PM PDT 24 41582999 ps
T538 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.827798295 Aug 03 04:22:18 PM PDT 24 Aug 03 04:22:19 PM PDT 24 32060860 ps
T539 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1793576299 Aug 03 04:22:37 PM PDT 24 Aug 03 04:22:37 PM PDT 24 50576483 ps
T540 /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1247662044 Aug 03 04:24:29 PM PDT 24 Aug 03 04:24:34 PM PDT 24 12126497 ps
T541 /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.764399328 Aug 03 04:23:54 PM PDT 24 Aug 03 04:23:55 PM PDT 24 13015503 ps
T542 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.3529605044 Aug 03 04:21:50 PM PDT 24 Aug 03 04:21:51 PM PDT 24 12035652 ps
T543 /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.3708803413 Aug 03 04:21:51 PM PDT 24 Aug 03 04:21:54 PM PDT 24 1412532451 ps
T544 /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.3673477561 Aug 03 04:23:31 PM PDT 24 Aug 03 04:23:32 PM PDT 24 13897107 ps
T545 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.681727753 Aug 03 04:23:08 PM PDT 24 Aug 03 04:23:13 PM PDT 24 377257047 ps
T98 /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.416580353 Aug 03 04:22:42 PM PDT 24 Aug 03 04:22:43 PM PDT 24 112666850 ps
T546 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.1313719044 Aug 03 04:22:33 PM PDT 24 Aug 03 04:22:34 PM PDT 24 31778272 ps
T547 /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.1018741991 Aug 03 04:23:29 PM PDT 24 Aug 03 04:23:32 PM PDT 24 151901391 ps
T548 /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.3018557427 Aug 03 04:22:15 PM PDT 24 Aug 03 04:22:16 PM PDT 24 48636411 ps
T549 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.2537541779 Aug 03 04:22:01 PM PDT 24 Aug 03 04:22:02 PM PDT 24 14986487 ps
T550 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.2407649648 Aug 03 04:22:38 PM PDT 24 Aug 03 04:22:38 PM PDT 24 29547255 ps
T551 /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.1835078584 Aug 03 04:23:53 PM PDT 24 Aug 03 04:23:54 PM PDT 24 31839227 ps
T552 /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2107163129 Aug 03 04:23:09 PM PDT 24 Aug 03 04:23:11 PM PDT 24 141662369 ps
T553 /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.3344724381 Aug 03 04:23:34 PM PDT 24 Aug 03 04:23:35 PM PDT 24 45384395 ps
T554 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.4009807478 Aug 03 04:22:15 PM PDT 24 Aug 03 04:22:17 PM PDT 24 356239404 ps
T555 /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.3557811545 Aug 03 04:22:31 PM PDT 24 Aug 03 04:22:32 PM PDT 24 43090929 ps
T556 /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.2117910974 Aug 03 04:23:35 PM PDT 24 Aug 03 04:23:37 PM PDT 24 74950595 ps
T557 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.1986006652 Aug 03 04:23:35 PM PDT 24 Aug 03 04:23:35 PM PDT 24 13036620 ps
T558 /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2695344265 Aug 03 04:22:32 PM PDT 24 Aug 03 04:22:33 PM PDT 24 237947220 ps
T559 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.193658125 Aug 03 04:21:50 PM PDT 24 Aug 03 04:21:50 PM PDT 24 56887641 ps
T560 /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3584510509 Aug 03 04:23:13 PM PDT 24 Aug 03 04:23:14 PM PDT 24 29818770 ps
T561 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.4109857141 Aug 03 04:22:29 PM PDT 24 Aug 03 04:22:31 PM PDT 24 38927056 ps
T562 /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.1637242424 Aug 03 04:22:32 PM PDT 24 Aug 03 04:22:33 PM PDT 24 34224845 ps
T563 /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.907705634 Aug 03 04:23:18 PM PDT 24 Aug 03 04:23:19 PM PDT 24 60469997 ps
T564 /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.656877750 Aug 03 04:23:33 PM PDT 24 Aug 03 04:23:34 PM PDT 24 24654327 ps
T565 /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.1553188579 Aug 03 04:21:50 PM PDT 24 Aug 03 04:21:51 PM PDT 24 91115528 ps
T566 /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.1544379457 Aug 03 04:23:34 PM PDT 24 Aug 03 04:23:35 PM PDT 24 23182546 ps
T567 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.593183368 Aug 03 04:22:31 PM PDT 24 Aug 03 04:22:31 PM PDT 24 30975724 ps
T568 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.1878408213 Aug 03 04:22:35 PM PDT 24 Aug 03 04:22:36 PM PDT 24 13566206 ps
T569 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.329904173 Aug 03 04:23:44 PM PDT 24 Aug 03 04:23:45 PM PDT 24 14001793 ps
T570 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1609116216 Aug 03 04:23:12 PM PDT 24 Aug 03 04:23:13 PM PDT 24 16220301 ps
T99 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.2390369643 Aug 03 04:23:25 PM PDT 24 Aug 03 04:23:26 PM PDT 24 33715717 ps
T571 /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.1322514873 Aug 03 04:23:39 PM PDT 24 Aug 03 04:23:40 PM PDT 24 17150885 ps
T572 /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.3777400796 Aug 03 04:23:32 PM PDT 24 Aug 03 04:23:33 PM PDT 24 60286261 ps
T573 /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.49051296 Aug 03 04:23:26 PM PDT 24 Aug 03 04:23:26 PM PDT 24 155152796 ps
T574 /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.990640882 Aug 03 04:22:04 PM PDT 24 Aug 03 04:22:05 PM PDT 24 415355605 ps
T575 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.3401537389 Aug 03 04:22:15 PM PDT 24 Aug 03 04:22:18 PM PDT 24 873992772 ps
T576 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3747214768 Aug 03 04:22:21 PM PDT 24 Aug 03 04:22:22 PM PDT 24 51194060 ps
T577 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.2679122572 Aug 03 04:22:20 PM PDT 24 Aug 03 04:22:22 PM PDT 24 213224980 ps
T578 /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.1644053912 Aug 03 04:23:21 PM PDT 24 Aug 03 04:23:21 PM PDT 24 54916551 ps
T579 /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.3078232331 Aug 03 04:23:34 PM PDT 24 Aug 03 04:23:34 PM PDT 24 40712877 ps
T580 /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.439789118 Aug 03 04:22:59 PM PDT 24 Aug 03 04:23:00 PM PDT 24 28117405 ps
T581 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.4278971655 Aug 03 04:23:24 PM PDT 24 Aug 03 04:23:25 PM PDT 24 82613402 ps
T582 /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.2977487954 Aug 03 04:22:25 PM PDT 24 Aug 03 04:22:26 PM PDT 24 81913743 ps
T583 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1763919270 Aug 03 04:23:09 PM PDT 24 Aug 03 04:23:10 PM PDT 24 26155016 ps
T584 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.1177560765 Aug 03 04:23:25 PM PDT 24 Aug 03 04:23:26 PM PDT 24 144231908 ps
T585 /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.3853713842 Aug 03 04:21:49 PM PDT 24 Aug 03 04:21:51 PM PDT 24 198823348 ps

Test location /workspace/coverage/default/93.rv_timer_random.3032350695
Short name T6
Test name
Test status
Simulation time 736632470382 ps
CPU time 1225.28 seconds
Started Aug 03 04:25:44 PM PDT 24
Finished Aug 03 04:46:09 PM PDT 24
Peak memory 191476 kb
Host smart-6070a3de-7111-4b26-909e-be6153b804a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032350695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.3032350695
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all_with_rand_reset.4161121942
Short name T13
Test name
Test status
Simulation time 43141123199 ps
CPU time 477.88 seconds
Started Aug 03 04:25:18 PM PDT 24
Finished Aug 03 04:33:16 PM PDT 24
Peak memory 206220 kb
Host smart-e6165afe-bc43-425a-bb26-c8fb0c27f76c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161121942 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all_with_rand_reset.4161121942
Directory /workspace/32.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.3708523334
Short name T11
Test name
Test status
Simulation time 3167174807140 ps
CPU time 1143.5 seconds
Started Aug 03 04:25:14 PM PDT 24
Finished Aug 03 04:44:17 PM PDT 24
Peak memory 191488 kb
Host smart-ac4fd2e7-942c-46d9-8ee3-638b98eb7408
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708523334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
3708523334
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.1918133282
Short name T206
Test name
Test status
Simulation time 3738513121620 ps
CPU time 1839.85 seconds
Started Aug 03 04:25:50 PM PDT 24
Finished Aug 03 04:56:31 PM PDT 24
Peak memory 191460 kb
Host smart-8463b47d-3cfa-42d8-a562-0576807d1eb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918133282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.1918133282
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.2770625254
Short name T22
Test name
Test status
Simulation time 114389261 ps
CPU time 1.08 seconds
Started Aug 03 04:22:15 PM PDT 24
Finished Aug 03 04:22:16 PM PDT 24
Peak memory 183476 kb
Host smart-4c720100-aa0d-4cc8-ae5d-9511c5389a00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770625254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.2770625254
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.1040812791
Short name T194
Test name
Test status
Simulation time 3344837903427 ps
CPU time 2382.37 seconds
Started Aug 03 04:25:01 PM PDT 24
Finished Aug 03 05:04:43 PM PDT 24
Peak memory 191512 kb
Host smart-ed37ed9e-e0de-4fc5-9a20-c0944b19afda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040812791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
1040812791
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.544803240
Short name T64
Test name
Test status
Simulation time 1758550815429 ps
CPU time 1449.23 seconds
Started Aug 03 04:25:27 PM PDT 24
Finished Aug 03 04:49:37 PM PDT 24
Peak memory 195972 kb
Host smart-cf06ec4b-6982-4869-985d-dfb9812e8b20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544803240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all.
544803240
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.4050063285
Short name T113
Test name
Test status
Simulation time 2403947261685 ps
CPU time 2571.96 seconds
Started Aug 03 04:26:24 PM PDT 24
Finished Aug 03 05:09:16 PM PDT 24
Peak memory 191112 kb
Host smart-45844907-26be-4ca3-bd00-adf5fc565151
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050063285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.4050063285
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.18289209
Short name T47
Test name
Test status
Simulation time 48083047 ps
CPU time 0.57 seconds
Started Aug 03 04:23:09 PM PDT 24
Finished Aug 03 04:23:10 PM PDT 24
Peak memory 181268 kb
Host smart-c872fdeb-8dcc-475c-a927-3e9e7a32416a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18289209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_res
et.18289209
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.1673861975
Short name T114
Test name
Test status
Simulation time 292162718202 ps
CPU time 1675.26 seconds
Started Aug 03 04:25:19 PM PDT 24
Finished Aug 03 04:53:15 PM PDT 24
Peak memory 191464 kb
Host smart-fa78278e-5594-4d49-af15-f50814ab7849
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673861975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.1673861975
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.3195546137
Short name T345
Test name
Test status
Simulation time 608536120249 ps
CPU time 1408.22 seconds
Started Aug 03 04:25:23 PM PDT 24
Finished Aug 03 04:48:52 PM PDT 24
Peak memory 191488 kb
Host smart-dc1fdd45-0cd2-4f40-98bb-97deb6ed46a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195546137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.3195546137
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.3499531475
Short name T251
Test name
Test status
Simulation time 2212139649803 ps
CPU time 1311.17 seconds
Started Aug 03 04:25:12 PM PDT 24
Finished Aug 03 04:47:03 PM PDT 24
Peak memory 196496 kb
Host smart-e92025c4-8e9b-411c-8cbd-96c407f8ddce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499531475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
3499531475
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.364359581
Short name T216
Test name
Test status
Simulation time 507794279140 ps
CPU time 1150.67 seconds
Started Aug 03 04:25:18 PM PDT 24
Finished Aug 03 04:44:29 PM PDT 24
Peak memory 191452 kb
Host smart-7157d219-97ea-47d0-b4a3-2b2c12bcdb21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364359581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all.
364359581
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.671141686
Short name T18
Test name
Test status
Simulation time 93817448 ps
CPU time 0.94 seconds
Started Aug 03 04:25:05 PM PDT 24
Finished Aug 03 04:25:06 PM PDT 24
Peak memory 214920 kb
Host smart-a69eb3c6-b648-42b6-a55e-5271279764d9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671141686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.671141686
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/186.rv_timer_random.3297488477
Short name T212
Test name
Test status
Simulation time 359483154844 ps
CPU time 369.38 seconds
Started Aug 03 04:25:42 PM PDT 24
Finished Aug 03 04:31:52 PM PDT 24
Peak memory 191404 kb
Host smart-105aa4cf-b60b-4c6d-9dad-585d240afdaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297488477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.3297488477
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.2312666474
Short name T156
Test name
Test status
Simulation time 378008679955 ps
CPU time 975.26 seconds
Started Aug 03 04:25:11 PM PDT 24
Finished Aug 03 04:41:26 PM PDT 24
Peak memory 191464 kb
Host smart-f5af1cfa-b03e-490b-a13f-f6a2e33d439c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312666474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.2312666474
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.2505629060
Short name T62
Test name
Test status
Simulation time 686058135393 ps
CPU time 1001.57 seconds
Started Aug 03 04:25:17 PM PDT 24
Finished Aug 03 04:42:04 PM PDT 24
Peak memory 190884 kb
Host smart-8015db44-a90f-4333-8ebb-c3bafb5ecb86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505629060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
2505629060
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.2727921370
Short name T177
Test name
Test status
Simulation time 860964270748 ps
CPU time 1518.58 seconds
Started Aug 03 04:25:34 PM PDT 24
Finished Aug 03 04:50:53 PM PDT 24
Peak memory 191508 kb
Host smart-8756f772-866f-4dfd-98d2-352ad563d22b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727921370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.2727921370
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/187.rv_timer_random.3885187933
Short name T340
Test name
Test status
Simulation time 366059254416 ps
CPU time 364.96 seconds
Started Aug 03 04:25:56 PM PDT 24
Finished Aug 03 04:32:01 PM PDT 24
Peak memory 191532 kb
Host smart-eb3f9b89-f28e-408f-a3dd-a18c8b814c2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885187933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.3885187933
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.3831169081
Short name T259
Test name
Test status
Simulation time 1560718697744 ps
CPU time 2412.34 seconds
Started Aug 03 04:25:19 PM PDT 24
Finished Aug 03 05:05:32 PM PDT 24
Peak memory 196988 kb
Host smart-f58378f4-a01f-46a5-82f1-7636ea5058b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831169081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.3831169081
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/14.rv_timer_random.3721997192
Short name T163
Test name
Test status
Simulation time 651812382314 ps
CPU time 526.07 seconds
Started Aug 03 04:25:13 PM PDT 24
Finished Aug 03 04:33:59 PM PDT 24
Peak memory 191528 kb
Host smart-8c404ede-edb0-4a87-8009-fcc139919865
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721997192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.3721997192
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.243263168
Short name T4
Test name
Test status
Simulation time 597956207194 ps
CPU time 778.88 seconds
Started Aug 03 04:25:32 PM PDT 24
Finished Aug 03 04:38:31 PM PDT 24
Peak memory 191172 kb
Host smart-0a1f16e4-00eb-42c2-a5d8-c77771904ed0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243263168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.243263168
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.2639217642
Short name T188
Test name
Test status
Simulation time 727894212331 ps
CPU time 711.4 seconds
Started Aug 03 04:25:44 PM PDT 24
Finished Aug 03 04:37:36 PM PDT 24
Peak memory 191460 kb
Host smart-fed82798-a903-4166-88db-95d7706244e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639217642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.2639217642
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.371921801
Short name T353
Test name
Test status
Simulation time 377197961543 ps
CPU time 785.08 seconds
Started Aug 03 04:25:16 PM PDT 24
Finished Aug 03 04:38:21 PM PDT 24
Peak memory 194444 kb
Host smart-cd56615b-0aeb-4757-98a2-aacc2cc4e620
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371921801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.371921801
Directory /workspace/99.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.633815312
Short name T221
Test name
Test status
Simulation time 487351022369 ps
CPU time 582.49 seconds
Started Aug 03 04:25:25 PM PDT 24
Finished Aug 03 04:35:08 PM PDT 24
Peak memory 191460 kb
Host smart-d5872cc6-a5d9-4edd-a8dd-0243d741b241
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633815312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.633815312
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.3822074039
Short name T169
Test name
Test status
Simulation time 736157164057 ps
CPU time 698.48 seconds
Started Aug 03 04:25:45 PM PDT 24
Finished Aug 03 04:37:29 PM PDT 24
Peak memory 191536 kb
Host smart-4b4acc76-e1f3-460b-80cc-499a50e90a7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822074039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.3822074039
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.2917395840
Short name T198
Test name
Test status
Simulation time 1284262354879 ps
CPU time 1620.09 seconds
Started Aug 03 04:25:17 PM PDT 24
Finished Aug 03 04:52:17 PM PDT 24
Peak memory 191452 kb
Host smart-100af836-28e8-4b7b-9773-79e42d723443
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917395840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.2917395840
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/107.rv_timer_random.2730427245
Short name T160
Test name
Test status
Simulation time 118950972152 ps
CPU time 168.74 seconds
Started Aug 03 04:25:27 PM PDT 24
Finished Aug 03 04:28:15 PM PDT 24
Peak memory 194128 kb
Host smart-83e3053f-80b3-4b17-98f7-e1bed231121d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730427245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.2730427245
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/150.rv_timer_random.3830384726
Short name T294
Test name
Test status
Simulation time 447176960984 ps
CPU time 230.27 seconds
Started Aug 03 04:25:45 PM PDT 24
Finished Aug 03 04:29:35 PM PDT 24
Peak memory 191472 kb
Host smart-81674774-a3ed-4e5c-881a-9a74ebab8b07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830384726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.3830384726
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random.1000845362
Short name T3
Test name
Test status
Simulation time 3014558799225 ps
CPU time 1877.81 seconds
Started Aug 03 04:25:12 PM PDT 24
Finished Aug 03 04:56:30 PM PDT 24
Peak memory 191492 kb
Host smart-74b27e7a-30bd-4df6-bf00-e66342652069
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000845362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.1000845362
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random.930673905
Short name T128
Test name
Test status
Simulation time 180544290677 ps
CPU time 327.29 seconds
Started Aug 03 04:25:16 PM PDT 24
Finished Aug 03 04:30:43 PM PDT 24
Peak memory 193868 kb
Host smart-8960bb9c-0d42-4998-81be-cbd326b7ae31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930673905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.930673905
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.3755102613
Short name T67
Test name
Test status
Simulation time 242671388221 ps
CPU time 354.5 seconds
Started Aug 03 04:25:03 PM PDT 24
Finished Aug 03 04:30:58 PM PDT 24
Peak memory 191452 kb
Host smart-0e8ad40c-4c84-4cb3-ad9d-52f0dde74657
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755102613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
3755102613
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.430935365
Short name T79
Test name
Test status
Simulation time 16724210 ps
CPU time 0.84 seconds
Started Aug 03 04:23:24 PM PDT 24
Finished Aug 03 04:23:26 PM PDT 24
Peak memory 180496 kb
Host smart-78c389cc-ba06-4c23-8fd5-c7e3129e3c47
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430935365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alias
ing.430935365
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.69860521
Short name T175
Test name
Test status
Simulation time 3789547302372 ps
CPU time 1279.56 seconds
Started Aug 03 04:25:09 PM PDT 24
Finished Aug 03 04:46:29 PM PDT 24
Peak memory 183380 kb
Host smart-5fbb7927-3799-42f0-9608-91de1a636034
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69860521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.rv_timer_cfg_update_on_fly.69860521
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/156.rv_timer_random.686890516
Short name T121
Test name
Test status
Simulation time 658204739161 ps
CPU time 543.79 seconds
Started Aug 03 04:25:31 PM PDT 24
Finished Aug 03 04:34:35 PM PDT 24
Peak memory 191172 kb
Host smart-99a89841-663b-4755-9ef0-d35dca700130
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686890516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.686890516
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.3823136198
Short name T205
Test name
Test status
Simulation time 319038275831 ps
CPU time 263.85 seconds
Started Aug 03 04:25:11 PM PDT 24
Finished Aug 03 04:29:35 PM PDT 24
Peak memory 182980 kb
Host smart-4342169e-5059-45de-8af8-e1fa26cad414
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823136198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.3823136198
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.1095528142
Short name T149
Test name
Test status
Simulation time 485730883754 ps
CPU time 1128.31 seconds
Started Aug 03 04:25:32 PM PDT 24
Finished Aug 03 04:44:20 PM PDT 24
Peak memory 195912 kb
Host smart-4b459950-2115-4b32-8731-e493076eff4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095528142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.1095528142
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/86.rv_timer_random.3800553725
Short name T204
Test name
Test status
Simulation time 43486939506 ps
CPU time 75.36 seconds
Started Aug 03 04:25:51 PM PDT 24
Finished Aug 03 04:27:06 PM PDT 24
Peak memory 195148 kb
Host smart-09d1c732-6485-48f2-b416-1611c2bd082f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800553725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.3800553725
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.206664394
Short name T152
Test name
Test status
Simulation time 863460036887 ps
CPU time 481.38 seconds
Started Aug 03 04:25:51 PM PDT 24
Finished Aug 03 04:33:53 PM PDT 24
Peak memory 191480 kb
Host smart-ab99f4b0-bb84-422d-9bb0-e67d723554a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206664394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.206664394
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.567844006
Short name T120
Test name
Test status
Simulation time 228287605809 ps
CPU time 528.39 seconds
Started Aug 03 04:25:51 PM PDT 24
Finished Aug 03 04:34:39 PM PDT 24
Peak memory 191500 kb
Host smart-6a4777fb-b72d-487c-9280-e291ea03b0e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567844006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.567844006
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.1359058678
Short name T122
Test name
Test status
Simulation time 297073259990 ps
CPU time 237.81 seconds
Started Aug 03 04:25:24 PM PDT 24
Finished Aug 03 04:29:22 PM PDT 24
Peak memory 191464 kb
Host smart-99002a30-020c-4e46-8d05-780496417d5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359058678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.1359058678
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.3618167556
Short name T325
Test name
Test status
Simulation time 112163343103 ps
CPU time 217.79 seconds
Started Aug 03 04:25:39 PM PDT 24
Finished Aug 03 04:29:17 PM PDT 24
Peak memory 191516 kb
Host smart-d5ad562b-c4ab-4170-91e5-c815f31d82ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618167556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.3618167556
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.3441372039
Short name T20
Test name
Test status
Simulation time 296920498943 ps
CPU time 2167.69 seconds
Started Aug 03 04:25:40 PM PDT 24
Finished Aug 03 05:01:48 PM PDT 24
Peak memory 193580 kb
Host smart-01aa08c5-6529-42be-a19f-51ba5543b042
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441372039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.3441372039
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.966216409
Short name T145
Test name
Test status
Simulation time 698081432572 ps
CPU time 866.27 seconds
Started Aug 03 04:25:51 PM PDT 24
Finished Aug 03 04:40:17 PM PDT 24
Peak memory 195028 kb
Host smart-1a47bd9d-0965-42fd-ae91-82b1c98ff2ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966216409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.966216409
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.1198559124
Short name T153
Test name
Test status
Simulation time 774563568967 ps
CPU time 408.02 seconds
Started Aug 03 04:25:04 PM PDT 24
Finished Aug 03 04:31:52 PM PDT 24
Peak memory 191496 kb
Host smart-2a85462b-ddd7-4dd5-af70-c7e47fef72da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198559124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
1198559124
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/105.rv_timer_random.2864972118
Short name T249
Test name
Test status
Simulation time 406531161831 ps
CPU time 653.25 seconds
Started Aug 03 04:25:29 PM PDT 24
Finished Aug 03 04:36:22 PM PDT 24
Peak memory 191492 kb
Host smart-9a29c0c6-c387-42b4-b21a-2dd3dba39406
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864972118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.2864972118
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.2937192118
Short name T201
Test name
Test status
Simulation time 797137256618 ps
CPU time 520.15 seconds
Started Aug 03 04:25:21 PM PDT 24
Finished Aug 03 04:34:01 PM PDT 24
Peak memory 191500 kb
Host smart-c03133a5-4fb5-4d9e-90df-43ff5c4ae8e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937192118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.2937192118
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.2754638976
Short name T199
Test name
Test status
Simulation time 95572717019 ps
CPU time 262.17 seconds
Started Aug 03 04:25:45 PM PDT 24
Finished Aug 03 04:30:07 PM PDT 24
Peak memory 191444 kb
Host smart-f4382d65-9cb4-4092-9dd8-b884ea33c663
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754638976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.2754638976
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.3304901142
Short name T158
Test name
Test status
Simulation time 416745052989 ps
CPU time 299.4 seconds
Started Aug 03 04:25:28 PM PDT 24
Finished Aug 03 04:30:28 PM PDT 24
Peak memory 191496 kb
Host smart-ef6ec584-dbb7-4100-9519-99e6cd6103d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304901142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.3304901142
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/160.rv_timer_random.1095444880
Short name T131
Test name
Test status
Simulation time 360558653569 ps
CPU time 627.2 seconds
Started Aug 03 04:25:53 PM PDT 24
Finished Aug 03 04:36:20 PM PDT 24
Peak memory 191544 kb
Host smart-8cbf764c-9184-4e24-8e93-24ad2de418d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095444880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.1095444880
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.1634939380
Short name T224
Test name
Test status
Simulation time 378150668304 ps
CPU time 295.1 seconds
Started Aug 03 04:25:58 PM PDT 24
Finished Aug 03 04:30:53 PM PDT 24
Peak memory 192900 kb
Host smart-5df6ebb4-bc0d-40d5-b7eb-7bd7ea1992b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634939380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.1634939380
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.2137944343
Short name T136
Test name
Test status
Simulation time 193420604721 ps
CPU time 367.98 seconds
Started Aug 03 04:25:44 PM PDT 24
Finished Aug 03 04:31:52 PM PDT 24
Peak memory 191520 kb
Host smart-c5ebecf2-20ad-41d6-9af0-919b125b1a62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137944343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.2137944343
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.16680209
Short name T144
Test name
Test status
Simulation time 209360272251 ps
CPU time 363.37 seconds
Started Aug 03 04:25:16 PM PDT 24
Finished Aug 03 04:31:19 PM PDT 24
Peak memory 183376 kb
Host smart-4842c108-4fa1-405b-9ca6-35d91dd979aa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16680209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.rv_timer_cfg_update_on_fly.16680209
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/195.rv_timer_random.1606248523
Short name T21
Test name
Test status
Simulation time 154099652378 ps
CPU time 2727.18 seconds
Started Aug 03 04:25:42 PM PDT 24
Finished Aug 03 05:11:09 PM PDT 24
Peak memory 191552 kb
Host smart-0c5a63d0-7666-4061-b207-8e633e73ca94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606248523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.1606248523
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.4152575219
Short name T265
Test name
Test status
Simulation time 222625935734 ps
CPU time 594.17 seconds
Started Aug 03 04:25:19 PM PDT 24
Finished Aug 03 04:35:13 PM PDT 24
Peak memory 196180 kb
Host smart-ed24e104-e03d-4bbd-8176-fc8e2e24efc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152575219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.4152575219
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.843809867
Short name T268
Test name
Test status
Simulation time 39014673630 ps
CPU time 61.82 seconds
Started Aug 03 04:25:53 PM PDT 24
Finished Aug 03 04:26:56 PM PDT 24
Peak memory 191488 kb
Host smart-50b468c6-54d1-4ede-93e1-588e5f5aff61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843809867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.843809867
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_random.2959581968
Short name T202
Test name
Test status
Simulation time 1138086940089 ps
CPU time 268.21 seconds
Started Aug 03 04:26:15 PM PDT 24
Finished Aug 03 04:30:44 PM PDT 24
Peak memory 189232 kb
Host smart-d3863cb3-b22c-4cb9-894d-c5907b8c2ece
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959581968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.2959581968
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.1974432646
Short name T222
Test name
Test status
Simulation time 429522573502 ps
CPU time 511.04 seconds
Started Aug 03 04:25:35 PM PDT 24
Finished Aug 03 04:34:06 PM PDT 24
Peak memory 191488 kb
Host smart-c7a8d81d-1cac-41f2-aa01-6ecdf18710b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974432646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.1974432646
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.4248485594
Short name T102
Test name
Test status
Simulation time 18461536 ps
CPU time 0.69 seconds
Started Aug 03 04:23:40 PM PDT 24
Finished Aug 03 04:23:40 PM PDT 24
Peak memory 193244 kb
Host smart-eab610c9-e549-45d8-be32-5d2cbacea380
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248485594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.4248485594
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.870724190
Short name T111
Test name
Test status
Simulation time 995895423 ps
CPU time 1.35 seconds
Started Aug 03 04:23:19 PM PDT 24
Finished Aug 03 04:23:21 PM PDT 24
Peak memory 195316 kb
Host smart-b257f274-6785-4266-93f2-2958b03b27b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870724190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_in
tg_err.870724190
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.3768177739
Short name T117
Test name
Test status
Simulation time 27296866275 ps
CPU time 145.8 seconds
Started Aug 03 04:24:45 PM PDT 24
Finished Aug 03 04:27:11 PM PDT 24
Peak memory 191440 kb
Host smart-3414a7ef-d486-46b9-b3bb-9b8efd431b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768177739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.3768177739
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/103.rv_timer_random.4057309391
Short name T276
Test name
Test status
Simulation time 65538878800 ps
CPU time 95.55 seconds
Started Aug 03 04:25:51 PM PDT 24
Finished Aug 03 04:27:27 PM PDT 24
Peak memory 191508 kb
Host smart-9efa2150-2b9e-466f-8632-522b159b04ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057309391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.4057309391
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.617376875
Short name T226
Test name
Test status
Simulation time 652828313589 ps
CPU time 635.06 seconds
Started Aug 03 04:25:22 PM PDT 24
Finished Aug 03 04:35:57 PM PDT 24
Peak memory 191168 kb
Host smart-9dd98e3f-67ca-4c4c-9a57-c0f16fbc9d2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617376875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.617376875
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.4215065597
Short name T262
Test name
Test status
Simulation time 50907095058 ps
CPU time 167.75 seconds
Started Aug 03 04:25:27 PM PDT 24
Finished Aug 03 04:28:15 PM PDT 24
Peak memory 191508 kb
Host smart-c31faf49-c81e-40fb-a683-b03e314cb8c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215065597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.4215065597
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random.466574907
Short name T178
Test name
Test status
Simulation time 96229270901 ps
CPU time 202.33 seconds
Started Aug 03 04:25:07 PM PDT 24
Finished Aug 03 04:28:30 PM PDT 24
Peak memory 191420 kb
Host smart-406d8ff4-fdd9-468d-a3ac-8161ff3964b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466574907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.466574907
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/170.rv_timer_random.4217317566
Short name T135
Test name
Test status
Simulation time 117805729668 ps
CPU time 518.92 seconds
Started Aug 03 04:25:58 PM PDT 24
Finished Aug 03 04:34:37 PM PDT 24
Peak memory 191524 kb
Host smart-02e21259-e412-4059-9967-c8c5488ecefe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217317566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.4217317566
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.1179573131
Short name T151
Test name
Test status
Simulation time 107328419485 ps
CPU time 471.52 seconds
Started Aug 03 04:25:49 PM PDT 24
Finished Aug 03 04:33:41 PM PDT 24
Peak memory 191480 kb
Host smart-78e044b0-7b86-4bb1-8b65-df4a128014c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179573131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.1179573131
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.3187114289
Short name T174
Test name
Test status
Simulation time 148986361116 ps
CPU time 74.5 seconds
Started Aug 03 04:25:56 PM PDT 24
Finished Aug 03 04:27:11 PM PDT 24
Peak memory 191520 kb
Host smart-7436a75c-0cb1-4ca6-8a8c-f1be9cea5efc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187114289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.3187114289
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all_with_rand_reset.4283397592
Short name T15
Test name
Test status
Simulation time 34288718234 ps
CPU time 366.77 seconds
Started Aug 03 04:26:02 PM PDT 24
Finished Aug 03 04:32:09 PM PDT 24
Peak memory 206264 kb
Host smart-5172d81e-6128-450d-9eee-4bc27344650f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283397592 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all_with_rand_reset.4283397592
Directory /workspace/28.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.3377516028
Short name T167
Test name
Test status
Simulation time 19090199399 ps
CPU time 28.31 seconds
Started Aug 03 04:25:43 PM PDT 24
Finished Aug 03 04:26:11 PM PDT 24
Peak memory 183264 kb
Host smart-c31db591-0588-4448-8a6a-edffdefac862
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377516028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.3377516028
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.2540867899
Short name T186
Test name
Test status
Simulation time 256600357368 ps
CPU time 1886.43 seconds
Started Aug 03 04:26:03 PM PDT 24
Finished Aug 03 04:57:30 PM PDT 24
Peak memory 191500 kb
Host smart-16dc1dec-75a6-4403-b66a-221793a402e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540867899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.2540867899
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_random.2197270079
Short name T233
Test name
Test status
Simulation time 168620720510 ps
CPU time 1321.72 seconds
Started Aug 03 04:25:43 PM PDT 24
Finished Aug 03 04:47:45 PM PDT 24
Peak memory 191468 kb
Host smart-17385efd-939a-4e99-b065-3e2b348aaa2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197270079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.2197270079
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random.2193802775
Short name T133
Test name
Test status
Simulation time 68931853616 ps
CPU time 96.26 seconds
Started Aug 03 04:26:15 PM PDT 24
Finished Aug 03 04:27:52 PM PDT 24
Peak memory 189676 kb
Host smart-461ec430-9e4a-4183-a116-300c1fb0ca19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193802775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.2193802775
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.4023701230
Short name T208
Test name
Test status
Simulation time 39529664987 ps
CPU time 79.83 seconds
Started Aug 03 04:25:38 PM PDT 24
Finished Aug 03 04:26:58 PM PDT 24
Peak memory 191472 kb
Host smart-d48b1f65-49ad-4c77-8ee1-e3d68681220a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023701230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.4023701230
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_random.3090159586
Short name T238
Test name
Test status
Simulation time 670914396148 ps
CPU time 1116.31 seconds
Started Aug 03 04:25:32 PM PDT 24
Finished Aug 03 04:44:09 PM PDT 24
Peak memory 191496 kb
Host smart-fe19cc05-b954-4646-98fc-f624417e57b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090159586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.3090159586
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3239289797
Short name T106
Test name
Test status
Simulation time 149821387 ps
CPU time 0.76 seconds
Started Aug 03 04:23:39 PM PDT 24
Finished Aug 03 04:23:40 PM PDT 24
Peak memory 183164 kb
Host smart-532d3bc7-e04e-4fe2-b2be-2d41941289df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239289797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.3239289797
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.1239219060
Short name T123
Test name
Test status
Simulation time 6900464752 ps
CPU time 6.12 seconds
Started Aug 03 04:25:09 PM PDT 24
Finished Aug 03 04:25:15 PM PDT 24
Peak memory 183304 kb
Host smart-3c8156bd-b757-49db-a8f8-09e6e5789d0e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239219060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.1239219060
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.3003034802
Short name T168
Test name
Test status
Simulation time 656933021875 ps
CPU time 515.19 seconds
Started Aug 03 04:24:47 PM PDT 24
Finished Aug 03 04:33:22 PM PDT 24
Peak memory 191456 kb
Host smart-223d139e-8375-478e-b0be-39837ae1924c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003034802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
3003034802
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.3979390590
Short name T305
Test name
Test status
Simulation time 296651984242 ps
CPU time 86.49 seconds
Started Aug 03 04:25:14 PM PDT 24
Finished Aug 03 04:26:41 PM PDT 24
Peak memory 183320 kb
Host smart-87b602ba-8f28-4b43-a6e8-92a0f7473d6d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979390590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.3979390590
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/104.rv_timer_random.1538587473
Short name T197
Test name
Test status
Simulation time 159971436559 ps
CPU time 281.07 seconds
Started Aug 03 04:25:48 PM PDT 24
Finished Aug 03 04:30:29 PM PDT 24
Peak memory 191572 kb
Host smart-fd10c0c0-575f-4f0c-8c03-d99613ffb3b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538587473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.1538587473
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.2941845169
Short name T229
Test name
Test status
Simulation time 13511380670 ps
CPU time 13.68 seconds
Started Aug 03 04:25:38 PM PDT 24
Finished Aug 03 04:25:52 PM PDT 24
Peak memory 183244 kb
Host smart-72cfda45-5fec-477c-84a6-30a78788899a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941845169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.2941845169
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.2690822421
Short name T311
Test name
Test status
Simulation time 265275054609 ps
CPU time 516.82 seconds
Started Aug 03 04:25:50 PM PDT 24
Finished Aug 03 04:34:27 PM PDT 24
Peak memory 191500 kb
Host smart-b650539f-a943-4023-8f26-c40e6a3e66b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690822421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.2690822421
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.1893420104
Short name T254
Test name
Test status
Simulation time 1630186846737 ps
CPU time 932.99 seconds
Started Aug 03 04:25:01 PM PDT 24
Finished Aug 03 04:40:34 PM PDT 24
Peak memory 183332 kb
Host smart-fb2f57de-7074-4fcb-9b88-9b4abd99a510
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893420104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.1893420104
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.3497529272
Short name T172
Test name
Test status
Simulation time 100391183314 ps
CPU time 233.11 seconds
Started Aug 03 04:25:14 PM PDT 24
Finished Aug 03 04:29:07 PM PDT 24
Peak memory 194700 kb
Host smart-e1bdedaa-776f-4b2e-94a9-ad5681798f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497529272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.3497529272
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/124.rv_timer_random.1018371354
Short name T9
Test name
Test status
Simulation time 124595904974 ps
CPU time 97.44 seconds
Started Aug 03 04:25:48 PM PDT 24
Finished Aug 03 04:27:26 PM PDT 24
Peak memory 183356 kb
Host smart-0af87c5f-8701-4dff-9995-71e4c6a2467a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018371354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.1018371354
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.1161353556
Short name T274
Test name
Test status
Simulation time 89968724760 ps
CPU time 90.31 seconds
Started Aug 03 04:25:40 PM PDT 24
Finished Aug 03 04:27:11 PM PDT 24
Peak memory 194792 kb
Host smart-6b225e81-f548-4c7a-a33f-a5216f246769
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161353556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.1161353556
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random.3510031194
Short name T271
Test name
Test status
Simulation time 425652222832 ps
CPU time 183.51 seconds
Started Aug 03 04:25:11 PM PDT 24
Finished Aug 03 04:28:14 PM PDT 24
Peak memory 191456 kb
Host smart-1fcdba33-5a3d-408f-9d61-015fdcc36984
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510031194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.3510031194
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.2026900113
Short name T223
Test name
Test status
Simulation time 197222223043 ps
CPU time 245.11 seconds
Started Aug 03 04:25:54 PM PDT 24
Finished Aug 03 04:30:00 PM PDT 24
Peak memory 191624 kb
Host smart-7eb9b667-6af4-4fb3-9d98-eaba62e023c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026900113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.2026900113
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/140.rv_timer_random.2871193689
Short name T331
Test name
Test status
Simulation time 718517067049 ps
CPU time 314.76 seconds
Started Aug 03 04:25:26 PM PDT 24
Finished Aug 03 04:30:41 PM PDT 24
Peak memory 191540 kb
Host smart-fea29ba3-ae65-46ba-978c-42fec1913384
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871193689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.2871193689
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.3422383428
Short name T322
Test name
Test status
Simulation time 759093176854 ps
CPU time 805.17 seconds
Started Aug 03 04:25:50 PM PDT 24
Finished Aug 03 04:39:15 PM PDT 24
Peak memory 191476 kb
Host smart-3c5ed1a7-f4ed-4a65-b14b-45ffe619d0ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422383428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.3422383428
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.1738157798
Short name T196
Test name
Test status
Simulation time 218904574 ps
CPU time 1.35 seconds
Started Aug 03 04:25:38 PM PDT 24
Finished Aug 03 04:25:39 PM PDT 24
Peak memory 183240 kb
Host smart-8af84776-9ab0-4527-a1c9-a38c4f9cd586
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738157798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.1738157798
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.918449041
Short name T170
Test name
Test status
Simulation time 645270693359 ps
CPU time 1226.67 seconds
Started Aug 03 04:25:02 PM PDT 24
Finished Aug 03 04:45:29 PM PDT 24
Peak memory 191412 kb
Host smart-6174350b-e1c4-490e-9112-1ad8e06459f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918449041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all.
918449041
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/171.rv_timer_random.2182609674
Short name T132
Test name
Test status
Simulation time 304784058411 ps
CPU time 120.83 seconds
Started Aug 03 04:25:48 PM PDT 24
Finished Aug 03 04:27:49 PM PDT 24
Peak memory 191616 kb
Host smart-e318e012-dc56-4c22-b330-27ce54795105
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182609674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.2182609674
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.361298512
Short name T302
Test name
Test status
Simulation time 199013499618 ps
CPU time 505.27 seconds
Started Aug 03 04:25:43 PM PDT 24
Finished Aug 03 04:34:09 PM PDT 24
Peak memory 191532 kb
Host smart-55cdc5b2-612f-4376-9899-7a33d0757358
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361298512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.361298512
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.138698004
Short name T337
Test name
Test status
Simulation time 208543924248 ps
CPU time 95.83 seconds
Started Aug 03 04:25:10 PM PDT 24
Finished Aug 03 04:26:46 PM PDT 24
Peak memory 191488 kb
Host smart-6f2d5c73-0deb-4ace-9d62-342ef87e8ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138698004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.138698004
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.3055028907
Short name T183
Test name
Test status
Simulation time 120446149745 ps
CPU time 214.07 seconds
Started Aug 03 04:25:13 PM PDT 24
Finished Aug 03 04:28:47 PM PDT 24
Peak memory 183292 kb
Host smart-c046ad17-3b25-46b7-abfe-c24f290e2797
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055028907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.3055028907
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_random.2189702051
Short name T124
Test name
Test status
Simulation time 192596404320 ps
CPU time 371.69 seconds
Started Aug 03 04:25:31 PM PDT 24
Finished Aug 03 04:31:43 PM PDT 24
Peak memory 191172 kb
Host smart-690c324a-0073-43b1-b501-1a7f9d8ddcc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189702051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.2189702051
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/50.rv_timer_random.3737031613
Short name T273
Test name
Test status
Simulation time 86225449239 ps
CPU time 228.09 seconds
Started Aug 03 04:25:20 PM PDT 24
Finished Aug 03 04:29:08 PM PDT 24
Peak memory 191504 kb
Host smart-72469167-ad5b-4161-ae3f-bc41b6fc08b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737031613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.3737031613
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.4179119213
Short name T329
Test name
Test status
Simulation time 358140518992 ps
CPU time 321.23 seconds
Started Aug 03 04:25:21 PM PDT 24
Finished Aug 03 04:30:52 PM PDT 24
Peak memory 191512 kb
Host smart-78cd26cb-88f6-41ce-8d85-89940d83e5b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179119213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.4179119213
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.681727753
Short name T545
Test name
Test status
Simulation time 377257047 ps
CPU time 3.86 seconds
Started Aug 03 04:23:08 PM PDT 24
Finished Aug 03 04:23:13 PM PDT 24
Peak memory 189568 kb
Host smart-7b7d2af7-5889-47e7-8920-f92afcca65b3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681727753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_b
ash.681727753
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.3557811545
Short name T555
Test name
Test status
Simulation time 43090929 ps
CPU time 0.89 seconds
Started Aug 03 04:22:31 PM PDT 24
Finished Aug 03 04:22:32 PM PDT 24
Peak memory 197316 kb
Host smart-0c774d5d-76b9-4e8a-9ede-1d57b011ffe1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557811545 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.3557811545
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.1718056888
Short name T92
Test name
Test status
Simulation time 58203503 ps
CPU time 0.63 seconds
Started Aug 03 04:22:01 PM PDT 24
Finished Aug 03 04:22:02 PM PDT 24
Peak memory 182680 kb
Host smart-5e7ba22d-56ca-4142-8ecc-8a109c82525e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718056888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.1718056888
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.1909943510
Short name T489
Test name
Test status
Simulation time 38863891 ps
CPU time 0.52 seconds
Started Aug 03 04:23:09 PM PDT 24
Finished Aug 03 04:23:10 PM PDT 24
Peak memory 181676 kb
Host smart-f0753588-5c08-4fbf-86bb-d3986b1bd98e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909943510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.1909943510
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.1272476551
Short name T482
Test name
Test status
Simulation time 345585913 ps
CPU time 1.78 seconds
Started Aug 03 04:24:00 PM PDT 24
Finished Aug 03 04:24:02 PM PDT 24
Peak memory 197076 kb
Host smart-b77f3810-0bae-47d9-aa95-2f2a3ce6d6df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272476551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.1272476551
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.734723747
Short name T513
Test name
Test status
Simulation time 312515477 ps
CPU time 1.12 seconds
Started Aug 03 04:21:53 PM PDT 24
Finished Aug 03 04:21:55 PM PDT 24
Peak memory 194924 kb
Host smart-2a1a09f9-ac70-4e06-a372-5a1bac60897d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734723747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_int
g_err.734723747
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.2390369643
Short name T99
Test name
Test status
Simulation time 33715717 ps
CPU time 0.77 seconds
Started Aug 03 04:23:25 PM PDT 24
Finished Aug 03 04:23:26 PM PDT 24
Peak memory 190596 kb
Host smart-711242cf-0bf1-47e3-9972-25a5525f27d6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390369643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.2390369643
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2107163129
Short name T552
Test name
Test status
Simulation time 141662369 ps
CPU time 1.42 seconds
Started Aug 03 04:23:09 PM PDT 24
Finished Aug 03 04:23:11 PM PDT 24
Peak memory 189400 kb
Host smart-72d60d39-6868-46c9-8faa-44a4520cafa5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107163129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.2107163129
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.4105385990
Short name T530
Test name
Test status
Simulation time 51851150 ps
CPU time 0.54 seconds
Started Aug 03 04:21:55 PM PDT 24
Finished Aug 03 04:21:56 PM PDT 24
Peak memory 182736 kb
Host smart-66ee822d-18df-4109-8386-b29574ad44cb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105385990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.4105385990
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.1177560765
Short name T584
Test name
Test status
Simulation time 144231908 ps
CPU time 0.89 seconds
Started Aug 03 04:23:25 PM PDT 24
Finished Aug 03 04:23:26 PM PDT 24
Peak memory 197300 kb
Host smart-53635909-2d84-4a49-8aed-51472794565b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177560765 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.1177560765
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.416580353
Short name T98
Test name
Test status
Simulation time 112666850 ps
CPU time 0.56 seconds
Started Aug 03 04:22:42 PM PDT 24
Finished Aug 03 04:22:43 PM PDT 24
Peak memory 182376 kb
Host smart-dab9a501-177d-42b2-8139-59cb49c8654f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416580353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.416580353
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.49051296
Short name T573
Test name
Test status
Simulation time 155152796 ps
CPU time 0.53 seconds
Started Aug 03 04:23:26 PM PDT 24
Finished Aug 03 04:23:26 PM PDT 24
Peak memory 181960 kb
Host smart-d00465aa-5f95-4709-9a7a-8243e9389eca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49051296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.49051296
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.439789118
Short name T580
Test name
Test status
Simulation time 28117405 ps
CPU time 0.61 seconds
Started Aug 03 04:22:59 PM PDT 24
Finished Aug 03 04:23:00 PM PDT 24
Peak memory 191908 kb
Host smart-f850c9e3-b5c4-4189-8ee4-82b927105866
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439789118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_tim
er_same_csr_outstanding.439789118
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.1428643942
Short name T486
Test name
Test status
Simulation time 103275349 ps
CPU time 1.15 seconds
Started Aug 03 04:23:26 PM PDT 24
Finished Aug 03 04:23:27 PM PDT 24
Peak memory 197192 kb
Host smart-525d14e0-a462-4b74-bec6-e0fd97981849
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428643942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.1428643942
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.2225785290
Short name T60
Test name
Test status
Simulation time 50213420 ps
CPU time 0.85 seconds
Started Aug 03 04:23:24 PM PDT 24
Finished Aug 03 04:23:26 PM PDT 24
Peak memory 191824 kb
Host smart-fc6713b8-17a2-4ad4-8a4c-10f3a83c97fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225785290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.2225785290
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.1312880388
Short name T475
Test name
Test status
Simulation time 21582033 ps
CPU time 0.71 seconds
Started Aug 03 04:22:56 PM PDT 24
Finished Aug 03 04:22:56 PM PDT 24
Peak memory 194828 kb
Host smart-281a4eac-0166-44da-9038-527e306f9bcb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312880388 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.1312880388
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.1678873984
Short name T76
Test name
Test status
Simulation time 21060178 ps
CPU time 0.64 seconds
Started Aug 03 04:23:16 PM PDT 24
Finished Aug 03 04:23:17 PM PDT 24
Peak memory 182656 kb
Host smart-7c8d3ab2-42bd-44e6-9581-35220649a69e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678873984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.1678873984
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.854056239
Short name T468
Test name
Test status
Simulation time 76314413 ps
CPU time 0.57 seconds
Started Aug 03 04:23:29 PM PDT 24
Finished Aug 03 04:23:30 PM PDT 24
Peak memory 182516 kb
Host smart-0a57a739-3a0b-4ba1-8af0-132a80831b3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854056239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.854056239
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.1986006652
Short name T557
Test name
Test status
Simulation time 13036620 ps
CPU time 0.58 seconds
Started Aug 03 04:23:35 PM PDT 24
Finished Aug 03 04:23:35 PM PDT 24
Peak memory 191308 kb
Host smart-d7b05632-41ed-40f4-af62-636774aa9d16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986006652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.1986006652
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.107854957
Short name T463
Test name
Test status
Simulation time 49513963 ps
CPU time 2.11 seconds
Started Aug 03 04:23:28 PM PDT 24
Finished Aug 03 04:23:31 PM PDT 24
Peak memory 197344 kb
Host smart-bb9c5954-dd6d-4f5c-817c-59dfb259ddc0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107854957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.107854957
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.2952283918
Short name T466
Test name
Test status
Simulation time 122791626 ps
CPU time 0.87 seconds
Started Aug 03 04:23:28 PM PDT 24
Finished Aug 03 04:23:30 PM PDT 24
Peak memory 197000 kb
Host smart-4d390e76-d606-452c-81b2-4a62d4b4fae8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952283918 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.2952283918
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.2036724449
Short name T25
Test name
Test status
Simulation time 13980865 ps
CPU time 0.58 seconds
Started Aug 03 04:23:18 PM PDT 24
Finished Aug 03 04:23:19 PM PDT 24
Peak memory 180240 kb
Host smart-ba8f14ed-1b8f-46a4-a943-96c4d38fc429
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036724449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.2036724449
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.1598455467
Short name T523
Test name
Test status
Simulation time 50086410 ps
CPU time 0.54 seconds
Started Aug 03 04:23:29 PM PDT 24
Finished Aug 03 04:23:30 PM PDT 24
Peak memory 182520 kb
Host smart-94004529-6723-4560-bb94-1ec0e19a5197
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598455467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.1598455467
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.1849185726
Short name T517
Test name
Test status
Simulation time 150996684 ps
CPU time 0.74 seconds
Started Aug 03 04:23:13 PM PDT 24
Finished Aug 03 04:23:14 PM PDT 24
Peak memory 191364 kb
Host smart-2a145075-57ec-4f0e-879f-c79631d4dba4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849185726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.1849185726
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.2679122572
Short name T577
Test name
Test status
Simulation time 213224980 ps
CPU time 1.84 seconds
Started Aug 03 04:22:20 PM PDT 24
Finished Aug 03 04:22:22 PM PDT 24
Peak memory 197464 kb
Host smart-560847e8-712f-4994-9209-9d8bec30a780
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679122572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.2679122572
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3828262709
Short name T535
Test name
Test status
Simulation time 60337262 ps
CPU time 0.79 seconds
Started Aug 03 04:23:33 PM PDT 24
Finished Aug 03 04:23:33 PM PDT 24
Peak memory 196148 kb
Host smart-99d9d2c1-2958-40bb-894f-0dab7ab615b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828262709 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.3828262709
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1609116216
Short name T570
Test name
Test status
Simulation time 16220301 ps
CPU time 0.59 seconds
Started Aug 03 04:23:12 PM PDT 24
Finished Aug 03 04:23:13 PM PDT 24
Peak memory 180932 kb
Host smart-d7132269-710e-45e7-8013-eebd938e9b88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609116216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.1609116216
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.1538671420
Short name T527
Test name
Test status
Simulation time 27442492 ps
CPU time 0.56 seconds
Started Aug 03 04:23:13 PM PDT 24
Finished Aug 03 04:23:14 PM PDT 24
Peak memory 181224 kb
Host smart-c9a29269-cbbf-4f74-9bf5-97d0072c44e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538671420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.1538671420
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1946049058
Short name T534
Test name
Test status
Simulation time 93264931 ps
CPU time 0.77 seconds
Started Aug 03 04:23:13 PM PDT 24
Finished Aug 03 04:23:14 PM PDT 24
Peak memory 192336 kb
Host smart-dae4382f-946b-4e4f-9518-4786ee4e2516
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946049058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.1946049058
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.2117910974
Short name T556
Test name
Test status
Simulation time 74950595 ps
CPU time 1.72 seconds
Started Aug 03 04:23:35 PM PDT 24
Finished Aug 03 04:23:37 PM PDT 24
Peak memory 197448 kb
Host smart-f6990afe-d2ab-4714-8c69-dd7c8c2acb92
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117910974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.2117910974
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.3783610535
Short name T510
Test name
Test status
Simulation time 124510261 ps
CPU time 1.35 seconds
Started Aug 03 04:22:03 PM PDT 24
Finished Aug 03 04:22:05 PM PDT 24
Peak memory 195460 kb
Host smart-47d3ca5d-5977-4097-9b20-4e0a08a94777
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783610535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.3783610535
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.771305953
Short name T49
Test name
Test status
Simulation time 58825257 ps
CPU time 0.74 seconds
Started Aug 03 04:22:03 PM PDT 24
Finished Aug 03 04:22:04 PM PDT 24
Peak memory 195708 kb
Host smart-294e55db-a8bb-4c02-92fd-61f36b4c842a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771305953 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.771305953
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.1269728496
Short name T78
Test name
Test status
Simulation time 14015917 ps
CPU time 0.58 seconds
Started Aug 03 04:23:29 PM PDT 24
Finished Aug 03 04:23:30 PM PDT 24
Peak memory 182688 kb
Host smart-6a12502e-9070-4250-8536-6d957cbcbc2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269728496 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.1269728496
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.1068334502
Short name T503
Test name
Test status
Simulation time 37499412 ps
CPU time 0.55 seconds
Started Aug 03 04:22:08 PM PDT 24
Finished Aug 03 04:22:09 PM PDT 24
Peak memory 182600 kb
Host smart-7184fcc0-e3ac-4e46-8986-c10dcaeca246
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068334502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.1068334502
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.2040302178
Short name T528
Test name
Test status
Simulation time 53049956 ps
CPU time 0.73 seconds
Started Aug 03 04:22:15 PM PDT 24
Finished Aug 03 04:22:16 PM PDT 24
Peak memory 193316 kb
Host smart-48b24c3e-450d-4ae3-9be8-893cc0cf79b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040302178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.2040302178
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.4009807478
Short name T554
Test name
Test status
Simulation time 356239404 ps
CPU time 2 seconds
Started Aug 03 04:22:15 PM PDT 24
Finished Aug 03 04:22:17 PM PDT 24
Peak memory 197260 kb
Host smart-72362526-4f37-4392-80b1-9f3f6348cd6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009807478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.4009807478
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.990640882
Short name T574
Test name
Test status
Simulation time 415355605 ps
CPU time 1.36 seconds
Started Aug 03 04:22:04 PM PDT 24
Finished Aug 03 04:22:05 PM PDT 24
Peak memory 195572 kb
Host smart-2dfec6d5-7359-44d1-a761-448f71410bd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990640882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_in
tg_err.990640882
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.656877750
Short name T564
Test name
Test status
Simulation time 24654327 ps
CPU time 0.58 seconds
Started Aug 03 04:23:33 PM PDT 24
Finished Aug 03 04:23:34 PM PDT 24
Peak memory 192964 kb
Host smart-6699a346-ea78-4039-b73b-4676dd8e0cbf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656877750 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.656877750
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.2422056050
Short name T491
Test name
Test status
Simulation time 37647678 ps
CPU time 0.57 seconds
Started Aug 03 04:23:29 PM PDT 24
Finished Aug 03 04:23:30 PM PDT 24
Peak memory 182688 kb
Host smart-29b5de7f-e21d-48c0-9c49-9289b7c85ed2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422056050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.2422056050
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.3642000415
Short name T494
Test name
Test status
Simulation time 156907156 ps
CPU time 0.55 seconds
Started Aug 03 04:22:53 PM PDT 24
Finished Aug 03 04:22:54 PM PDT 24
Peak memory 182532 kb
Host smart-ab952c6f-b089-4451-968e-7c0e7c531cec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642000415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.3642000415
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.1544379457
Short name T566
Test name
Test status
Simulation time 23182546 ps
CPU time 0.8 seconds
Started Aug 03 04:23:34 PM PDT 24
Finished Aug 03 04:23:35 PM PDT 24
Peak memory 194044 kb
Host smart-bc06440f-3072-448a-84bb-2d6a6e7135c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544379457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.1544379457
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.1018741991
Short name T547
Test name
Test status
Simulation time 151901391 ps
CPU time 2.28 seconds
Started Aug 03 04:23:29 PM PDT 24
Finished Aug 03 04:23:32 PM PDT 24
Peak memory 197384 kb
Host smart-1b0b98bb-b98f-4106-91e5-fcfc2210cd25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018741991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.1018741991
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.3452577755
Short name T479
Test name
Test status
Simulation time 432326654 ps
CPU time 1.34 seconds
Started Aug 03 04:23:05 PM PDT 24
Finished Aug 03 04:23:06 PM PDT 24
Peak memory 195288 kb
Host smart-f8ca5db7-3b1c-4d9a-a2ee-4e89562e1bef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452577755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.3452577755
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.311168555
Short name T518
Test name
Test status
Simulation time 69795087 ps
CPU time 0.67 seconds
Started Aug 03 04:23:30 PM PDT 24
Finished Aug 03 04:23:31 PM PDT 24
Peak memory 192536 kb
Host smart-66ac4b28-6095-472d-b0be-97dcff11a01c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311168555 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.311168555
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.3673477561
Short name T544
Test name
Test status
Simulation time 13897107 ps
CPU time 0.53 seconds
Started Aug 03 04:23:31 PM PDT 24
Finished Aug 03 04:23:32 PM PDT 24
Peak memory 182692 kb
Host smart-27c01777-f3e8-45e4-bff9-facd2e1e90e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673477561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.3673477561
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.1495111569
Short name T499
Test name
Test status
Simulation time 62326109 ps
CPU time 0.54 seconds
Started Aug 03 04:23:29 PM PDT 24
Finished Aug 03 04:23:30 PM PDT 24
Peak memory 182452 kb
Host smart-9972b04f-f837-4bfe-961e-3023a5031bc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495111569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.1495111569
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.4293293620
Short name T524
Test name
Test status
Simulation time 47410459 ps
CPU time 0.68 seconds
Started Aug 03 04:23:12 PM PDT 24
Finished Aug 03 04:23:13 PM PDT 24
Peak memory 190460 kb
Host smart-44261de0-e6fe-4dd5-9580-29d0ec7b1c79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293293620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.4293293620
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1602403910
Short name T515
Test name
Test status
Simulation time 88411284 ps
CPU time 1.57 seconds
Started Aug 03 04:22:07 PM PDT 24
Finished Aug 03 04:22:09 PM PDT 24
Peak memory 197484 kb
Host smart-e585bfad-2816-453a-a94b-ab39dce0994f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602403910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.1602403910
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3958438975
Short name T24
Test name
Test status
Simulation time 152412007 ps
CPU time 1.04 seconds
Started Aug 03 04:23:12 PM PDT 24
Finished Aug 03 04:23:14 PM PDT 24
Peak memory 181344 kb
Host smart-a6da6235-a4eb-46a6-bdb2-17fad74dc57a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958438975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.3958438975
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.3292205642
Short name T531
Test name
Test status
Simulation time 99259663 ps
CPU time 0.8 seconds
Started Aug 03 04:22:41 PM PDT 24
Finished Aug 03 04:22:41 PM PDT 24
Peak memory 195664 kb
Host smart-470cbf19-0f3f-4484-85b1-533217ad58d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292205642 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.3292205642
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.2451455618
Short name T81
Test name
Test status
Simulation time 17197564 ps
CPU time 0.61 seconds
Started Aug 03 04:22:26 PM PDT 24
Finished Aug 03 04:22:27 PM PDT 24
Peak memory 182700 kb
Host smart-5989d783-2cca-4292-b8d9-70b15250bf0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451455618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.2451455618
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.1855738467
Short name T460
Test name
Test status
Simulation time 16134573 ps
CPU time 0.59 seconds
Started Aug 03 04:23:30 PM PDT 24
Finished Aug 03 04:23:31 PM PDT 24
Peak memory 181192 kb
Host smart-ddc474c6-f466-442d-9460-73af6b0351bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855738467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.1855738467
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2427029937
Short name T77
Test name
Test status
Simulation time 107213052 ps
CPU time 0.75 seconds
Started Aug 03 04:23:39 PM PDT 24
Finished Aug 03 04:23:40 PM PDT 24
Peak memory 191660 kb
Host smart-e8fc320a-cdf1-4bf6-9988-286d188b3dad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427029937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.2427029937
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.4052853061
Short name T467
Test name
Test status
Simulation time 52033600 ps
CPU time 1.21 seconds
Started Aug 03 04:23:29 PM PDT 24
Finished Aug 03 04:23:31 PM PDT 24
Peak memory 195872 kb
Host smart-27ab8d29-4e2f-4400-a206-40b49ae83623
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052853061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.4052853061
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.3947810363
Short name T109
Test name
Test status
Simulation time 39186388 ps
CPU time 0.79 seconds
Started Aug 03 04:23:30 PM PDT 24
Finished Aug 03 04:23:31 PM PDT 24
Peak memory 181400 kb
Host smart-c2378b86-b739-4114-bffc-3b20ca29546c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947810363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.3947810363
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.2524475985
Short name T474
Test name
Test status
Simulation time 18798599 ps
CPU time 0.68 seconds
Started Aug 03 04:23:23 PM PDT 24
Finished Aug 03 04:23:24 PM PDT 24
Peak memory 192176 kb
Host smart-d5a27136-4f73-4cd7-9497-cabcd424b417
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524475985 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.2524475985
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.4218537547
Short name T94
Test name
Test status
Simulation time 21377142 ps
CPU time 0.56 seconds
Started Aug 03 04:23:39 PM PDT 24
Finished Aug 03 04:23:40 PM PDT 24
Peak memory 182692 kb
Host smart-b6ac8648-fc4f-4385-a016-d0d653ff7c94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218537547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.4218537547
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1793576299
Short name T539
Test name
Test status
Simulation time 50576483 ps
CPU time 0.55 seconds
Started Aug 03 04:22:37 PM PDT 24
Finished Aug 03 04:22:37 PM PDT 24
Peak memory 182532 kb
Host smart-43ee8fb3-5745-465b-b9a3-d61d0f532dac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793576299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.1793576299
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2695344265
Short name T558
Test name
Test status
Simulation time 237947220 ps
CPU time 0.8 seconds
Started Aug 03 04:22:32 PM PDT 24
Finished Aug 03 04:22:33 PM PDT 24
Peak memory 191640 kb
Host smart-194f9537-0c72-46a5-a295-897cdbbcecc8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695344265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.2695344265
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.3121021594
Short name T490
Test name
Test status
Simulation time 153963650 ps
CPU time 2.54 seconds
Started Aug 03 04:22:29 PM PDT 24
Finished Aug 03 04:22:32 PM PDT 24
Peak memory 197400 kb
Host smart-d8d1c880-b364-494a-917c-a6a9ceb349c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121021594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.3121021594
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.579463374
Short name T485
Test name
Test status
Simulation time 64086940 ps
CPU time 0.84 seconds
Started Aug 03 04:23:23 PM PDT 24
Finished Aug 03 04:23:24 PM PDT 24
Peak memory 194692 kb
Host smart-634f32e1-5d1f-41a3-85ff-ad35de087e0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579463374 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.579463374
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.1322514873
Short name T571
Test name
Test status
Simulation time 17150885 ps
CPU time 0.55 seconds
Started Aug 03 04:23:39 PM PDT 24
Finished Aug 03 04:23:40 PM PDT 24
Peak memory 182692 kb
Host smart-ab4fcd3c-72ac-4b4c-98c6-bc8d42e4182b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322514873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.1322514873
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.380938481
Short name T511
Test name
Test status
Simulation time 18378766 ps
CPU time 0.57 seconds
Started Aug 03 04:23:40 PM PDT 24
Finished Aug 03 04:23:40 PM PDT 24
Peak memory 182548 kb
Host smart-b0309070-df97-4f59-a9b3-d256ba55a24a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380938481 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.380938481
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.132232142
Short name T100
Test name
Test status
Simulation time 14979227 ps
CPU time 0.67 seconds
Started Aug 03 04:23:23 PM PDT 24
Finished Aug 03 04:23:24 PM PDT 24
Peak memory 191136 kb
Host smart-ff2d08cb-3241-4e54-b015-d16e8200652b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132232142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_ti
mer_same_csr_outstanding.132232142
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3747214768
Short name T576
Test name
Test status
Simulation time 51194060 ps
CPU time 1.2 seconds
Started Aug 03 04:22:21 PM PDT 24
Finished Aug 03 04:22:22 PM PDT 24
Peak memory 197424 kb
Host smart-eac30100-fbf3-432a-b24c-fdf2aeaedfd8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747214768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.3747214768
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.3651696527
Short name T108
Test name
Test status
Simulation time 124347697 ps
CPU time 1.33 seconds
Started Aug 03 04:23:39 PM PDT 24
Finished Aug 03 04:23:40 PM PDT 24
Peak memory 183180 kb
Host smart-c62995e7-dfea-40d8-94ef-65bfb894d93f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651696527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.3651696527
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.4109857141
Short name T561
Test name
Test status
Simulation time 38927056 ps
CPU time 1.36 seconds
Started Aug 03 04:22:29 PM PDT 24
Finished Aug 03 04:22:31 PM PDT 24
Peak memory 197468 kb
Host smart-5d88910a-8222-4e4b-a06c-8f2a522ba7ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109857141 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.4109857141
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.985696452
Short name T532
Test name
Test status
Simulation time 39821213 ps
CPU time 0.56 seconds
Started Aug 03 04:22:15 PM PDT 24
Finished Aug 03 04:22:16 PM PDT 24
Peak memory 182748 kb
Host smart-916918f2-0f7d-4e75-9b03-179ff4a4ccf5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985696452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.985696452
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.2407649648
Short name T550
Test name
Test status
Simulation time 29547255 ps
CPU time 0.59 seconds
Started Aug 03 04:22:38 PM PDT 24
Finished Aug 03 04:22:38 PM PDT 24
Peak memory 182536 kb
Host smart-238bda6b-b82b-4a37-a8c2-29cca0be6012
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407649648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.2407649648
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.597934945
Short name T509
Test name
Test status
Simulation time 279727131 ps
CPU time 0.77 seconds
Started Aug 03 04:22:29 PM PDT 24
Finished Aug 03 04:22:30 PM PDT 24
Peak memory 193988 kb
Host smart-8c543dc6-4fcc-4ee0-a73e-90e0035f49d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597934945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_ti
mer_same_csr_outstanding.597934945
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.2977487954
Short name T582
Test name
Test status
Simulation time 81913743 ps
CPU time 1 seconds
Started Aug 03 04:22:25 PM PDT 24
Finished Aug 03 04:22:26 PM PDT 24
Peak memory 197312 kb
Host smart-66bbf9f9-cdf7-4c1b-9f18-322de2f74302
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977487954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.2977487954
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2482179407
Short name T516
Test name
Test status
Simulation time 1859546701 ps
CPU time 1.39 seconds
Started Aug 03 04:23:23 PM PDT 24
Finished Aug 03 04:23:25 PM PDT 24
Peak memory 193208 kb
Host smart-3c1956b0-38cf-47da-ab95-40ec724a7dd0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482179407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.2482179407
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.3062977757
Short name T50
Test name
Test status
Simulation time 19789548 ps
CPU time 0.61 seconds
Started Aug 03 04:24:33 PM PDT 24
Finished Aug 03 04:24:34 PM PDT 24
Peak memory 191904 kb
Host smart-c7e4c2db-b090-4bed-b903-2fefaca9271a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062977757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.3062977757
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.3401537389
Short name T575
Test name
Test status
Simulation time 873992772 ps
CPU time 2.39 seconds
Started Aug 03 04:22:15 PM PDT 24
Finished Aug 03 04:22:18 PM PDT 24
Peak memory 192132 kb
Host smart-287b2a75-3168-41d6-852d-773821a52b5c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401537389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.3401537389
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.1022571121
Short name T26
Test name
Test status
Simulation time 24736216 ps
CPU time 0.62 seconds
Started Aug 03 04:23:24 PM PDT 24
Finished Aug 03 04:23:25 PM PDT 24
Peak memory 181272 kb
Host smart-4ff36333-0512-431b-b451-e06a83a5a860
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022571121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.1022571121
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.193658125
Short name T559
Test name
Test status
Simulation time 56887641 ps
CPU time 0.64 seconds
Started Aug 03 04:21:50 PM PDT 24
Finished Aug 03 04:21:50 PM PDT 24
Peak memory 193692 kb
Host smart-56626a47-9b2f-4f5d-afb0-cd0af79824b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193658125 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.193658125
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.3158485299
Short name T488
Test name
Test status
Simulation time 22935777 ps
CPU time 0.57 seconds
Started Aug 03 04:23:09 PM PDT 24
Finished Aug 03 04:23:10 PM PDT 24
Peak memory 181344 kb
Host smart-a27cf0a7-1cf5-4381-8508-2d616b8664c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158485299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.3158485299
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.1690952100
Short name T459
Test name
Test status
Simulation time 35025744 ps
CPU time 0.52 seconds
Started Aug 03 04:23:39 PM PDT 24
Finished Aug 03 04:23:40 PM PDT 24
Peak memory 182420 kb
Host smart-fcd405ff-a829-4de7-bf46-8b95199a0aec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690952100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.1690952100
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.2094901238
Short name T101
Test name
Test status
Simulation time 15683235 ps
CPU time 0.59 seconds
Started Aug 03 04:23:40 PM PDT 24
Finished Aug 03 04:23:40 PM PDT 24
Peak memory 191896 kb
Host smart-854201f6-4f5b-4c1d-8a42-e5e93769e703
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094901238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.2094901238
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.1580751637
Short name T465
Test name
Test status
Simulation time 170341098 ps
CPU time 1.96 seconds
Started Aug 03 04:23:25 PM PDT 24
Finished Aug 03 04:23:27 PM PDT 24
Peak memory 197308 kb
Host smart-daa33440-3610-4aed-b468-cf77b504b322
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580751637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.1580751637
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2304659673
Short name T110
Test name
Test status
Simulation time 1101603627 ps
CPU time 1.28 seconds
Started Aug 03 04:23:19 PM PDT 24
Finished Aug 03 04:23:20 PM PDT 24
Peak memory 195308 kb
Host smart-32d8f1e3-1160-4da5-97b8-2802e7d20260
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304659673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.2304659673
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.1416089106
Short name T506
Test name
Test status
Simulation time 27958923 ps
CPU time 0.59 seconds
Started Aug 03 04:22:33 PM PDT 24
Finished Aug 03 04:22:34 PM PDT 24
Peak memory 182564 kb
Host smart-9e561061-2d48-41ba-a5b0-3959512a3c56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416089106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.1416089106
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1889654677
Short name T464
Test name
Test status
Simulation time 17344860 ps
CPU time 0.56 seconds
Started Aug 03 04:22:34 PM PDT 24
Finished Aug 03 04:22:35 PM PDT 24
Peak memory 182492 kb
Host smart-1425cd41-32d2-4c92-bb30-15bfa21fadb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889654677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.1889654677
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.3018557427
Short name T548
Test name
Test status
Simulation time 48636411 ps
CPU time 0.59 seconds
Started Aug 03 04:22:15 PM PDT 24
Finished Aug 03 04:22:16 PM PDT 24
Peak memory 181912 kb
Host smart-6c97805a-4152-484d-8a61-3f235fda3ebc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018557427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.3018557427
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.3078232331
Short name T579
Test name
Test status
Simulation time 40712877 ps
CPU time 0.53 seconds
Started Aug 03 04:23:34 PM PDT 24
Finished Aug 03 04:23:34 PM PDT 24
Peak memory 181700 kb
Host smart-e1bdd5ef-db33-4a07-bf26-27d59001831e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078232331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.3078232331
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.1877036963
Short name T497
Test name
Test status
Simulation time 49334895 ps
CPU time 0.55 seconds
Started Aug 03 04:22:20 PM PDT 24
Finished Aug 03 04:22:20 PM PDT 24
Peak memory 182156 kb
Host smart-1478cebb-8a40-4bb6-9de1-33af006948ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877036963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.1877036963
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.3344724381
Short name T553
Test name
Test status
Simulation time 45384395 ps
CPU time 0.54 seconds
Started Aug 03 04:23:34 PM PDT 24
Finished Aug 03 04:23:35 PM PDT 24
Peak memory 182216 kb
Host smart-2953adba-49a3-4e5b-9b65-a0930598f28a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344724381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.3344724381
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.358912437
Short name T484
Test name
Test status
Simulation time 28367188 ps
CPU time 0.55 seconds
Started Aug 03 04:23:49 PM PDT 24
Finished Aug 03 04:23:50 PM PDT 24
Peak memory 182496 kb
Host smart-7d3f9b8a-c981-4f50-94b5-0116915cf1de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358912437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.358912437
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.1939042940
Short name T498
Test name
Test status
Simulation time 42304858 ps
CPU time 0.58 seconds
Started Aug 03 04:22:28 PM PDT 24
Finished Aug 03 04:22:29 PM PDT 24
Peak memory 182536 kb
Host smart-fdd1e84d-2653-4b0c-bc8a-24f69b45b650
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939042940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.1939042940
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2778010376
Short name T469
Test name
Test status
Simulation time 10949024 ps
CPU time 0.55 seconds
Started Aug 03 04:22:33 PM PDT 24
Finished Aug 03 04:22:33 PM PDT 24
Peak memory 182436 kb
Host smart-14342dfd-d8f8-4ac5-ac6c-3ce4da0ae3ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778010376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.2778010376
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.329904173
Short name T569
Test name
Test status
Simulation time 14001793 ps
CPU time 0.54 seconds
Started Aug 03 04:23:44 PM PDT 24
Finished Aug 03 04:23:45 PM PDT 24
Peak memory 181988 kb
Host smart-08136207-15d9-403e-9036-73b80de34218
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329904173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.329904173
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3892201513
Short name T93
Test name
Test status
Simulation time 27690463 ps
CPU time 0.7 seconds
Started Aug 03 04:22:00 PM PDT 24
Finished Aug 03 04:22:01 PM PDT 24
Peak memory 191940 kb
Host smart-3786b0b0-df89-4130-a9e8-04cab89ab8ec
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892201513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.3892201513
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.3708803413
Short name T543
Test name
Test status
Simulation time 1412532451 ps
CPU time 2.5 seconds
Started Aug 03 04:21:51 PM PDT 24
Finished Aug 03 04:21:54 PM PDT 24
Peak memory 191116 kb
Host smart-f1411384-2ba5-4146-9833-094775c10603
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708803413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.3708803413
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.4000912643
Short name T529
Test name
Test status
Simulation time 58873980 ps
CPU time 0.56 seconds
Started Aug 03 04:22:22 PM PDT 24
Finished Aug 03 04:22:22 PM PDT 24
Peak memory 191952 kb
Host smart-9977b526-908b-41bb-b654-a1793b675370
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000912643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.4000912643
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.4278971655
Short name T581
Test name
Test status
Simulation time 82613402 ps
CPU time 0.7 seconds
Started Aug 03 04:23:24 PM PDT 24
Finished Aug 03 04:23:25 PM PDT 24
Peak memory 192220 kb
Host smart-5c8e204c-abb6-42b0-ae8e-d2cece55fa40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278971655 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.4278971655
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.211486118
Short name T502
Test name
Test status
Simulation time 143302876 ps
CPU time 0.6 seconds
Started Aug 03 04:23:09 PM PDT 24
Finished Aug 03 04:23:10 PM PDT 24
Peak memory 181432 kb
Host smart-a2ff099b-4fda-4aad-a893-53a4369b2a70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211486118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.211486118
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.157360508
Short name T471
Test name
Test status
Simulation time 46036446 ps
CPU time 0.52 seconds
Started Aug 03 04:22:15 PM PDT 24
Finished Aug 03 04:22:16 PM PDT 24
Peak memory 182196 kb
Host smart-322a2a3c-445c-4cbb-8262-d71fbc467afd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157360508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.157360508
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.3959075308
Short name T104
Test name
Test status
Simulation time 117565724 ps
CPU time 0.78 seconds
Started Aug 03 04:23:25 PM PDT 24
Finished Aug 03 04:23:26 PM PDT 24
Peak memory 193304 kb
Host smart-56ba09ce-6ef7-4671-87bc-08b7d8958ef6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959075308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.3959075308
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.1456414077
Short name T525
Test name
Test status
Simulation time 202695984 ps
CPU time 1.17 seconds
Started Aug 03 04:23:25 PM PDT 24
Finished Aug 03 04:23:27 PM PDT 24
Peak memory 197116 kb
Host smart-4f2a41b1-7f18-4678-8c3b-e6fc32d608a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456414077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.1456414077
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.1707424649
Short name T521
Test name
Test status
Simulation time 96427999 ps
CPU time 1.03 seconds
Started Aug 03 04:23:39 PM PDT 24
Finished Aug 03 04:23:40 PM PDT 24
Peak memory 194140 kb
Host smart-a7989141-794c-4c01-a380-091985476886
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707424649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.1707424649
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.1716978695
Short name T522
Test name
Test status
Simulation time 17353242 ps
CPU time 0.58 seconds
Started Aug 03 04:22:23 PM PDT 24
Finished Aug 03 04:22:23 PM PDT 24
Peak memory 182516 kb
Host smart-0bd0b149-90dd-426f-827d-fa106e433a33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716978695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.1716978695
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.4082639526
Short name T526
Test name
Test status
Simulation time 90043220 ps
CPU time 0.65 seconds
Started Aug 03 04:23:33 PM PDT 24
Finished Aug 03 04:23:34 PM PDT 24
Peak memory 181704 kb
Host smart-83e4e0da-e7bf-4081-89ea-4d86784bfc61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082639526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.4082639526
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.639595227
Short name T470
Test name
Test status
Simulation time 13444911 ps
CPU time 0.54 seconds
Started Aug 03 04:23:09 PM PDT 24
Finished Aug 03 04:23:09 PM PDT 24
Peak memory 182000 kb
Host smart-540da518-7228-4835-a436-e9c12125ef9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639595227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.639595227
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1476839263
Short name T487
Test name
Test status
Simulation time 20995604 ps
CPU time 0.56 seconds
Started Aug 03 04:22:23 PM PDT 24
Finished Aug 03 04:22:23 PM PDT 24
Peak memory 181964 kb
Host smart-3f584cc2-e4b6-471c-ae94-97289bea8ff3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476839263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.1476839263
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.1878408213
Short name T568
Test name
Test status
Simulation time 13566206 ps
CPU time 0.56 seconds
Started Aug 03 04:22:35 PM PDT 24
Finished Aug 03 04:22:36 PM PDT 24
Peak memory 182604 kb
Host smart-440c805f-f68c-4ab3-89e9-194948bbff99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878408213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.1878408213
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.1313719044
Short name T546
Test name
Test status
Simulation time 31778272 ps
CPU time 0.54 seconds
Started Aug 03 04:22:33 PM PDT 24
Finished Aug 03 04:22:34 PM PDT 24
Peak memory 181612 kb
Host smart-591c9fdd-e1b4-4ada-9dbe-77ab009132aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313719044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.1313719044
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.1835078584
Short name T551
Test name
Test status
Simulation time 31839227 ps
CPU time 0.53 seconds
Started Aug 03 04:23:53 PM PDT 24
Finished Aug 03 04:23:54 PM PDT 24
Peak memory 182508 kb
Host smart-b95d00c3-ad5e-446c-909b-9ad2cb0a5539
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835078584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.1835078584
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.764399328
Short name T541
Test name
Test status
Simulation time 13015503 ps
CPU time 0.54 seconds
Started Aug 03 04:23:54 PM PDT 24
Finished Aug 03 04:23:55 PM PDT 24
Peak memory 182588 kb
Host smart-3766b913-bb0c-4036-a1cb-05a27fda90b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764399328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.764399328
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.1849758155
Short name T478
Test name
Test status
Simulation time 75332337 ps
CPU time 0.56 seconds
Started Aug 03 04:23:04 PM PDT 24
Finished Aug 03 04:23:04 PM PDT 24
Peak memory 182604 kb
Host smart-3ddaf351-c04c-4b17-a123-f851fcc08120
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849758155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.1849758155
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.1637242424
Short name T562
Test name
Test status
Simulation time 34224845 ps
CPU time 0.55 seconds
Started Aug 03 04:22:32 PM PDT 24
Finished Aug 03 04:22:33 PM PDT 24
Peak memory 182472 kb
Host smart-fb926f36-85b5-434a-8320-4d6bbd7e6c08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637242424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.1637242424
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1763919270
Short name T583
Test name
Test status
Simulation time 26155016 ps
CPU time 0.78 seconds
Started Aug 03 04:23:09 PM PDT 24
Finished Aug 03 04:23:10 PM PDT 24
Peak memory 181368 kb
Host smart-7446b8a0-0acd-4d87-a804-97cda3a21a33
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763919270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.1763919270
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.3853713842
Short name T585
Test name
Test status
Simulation time 198823348 ps
CPU time 2.43 seconds
Started Aug 03 04:21:49 PM PDT 24
Finished Aug 03 04:21:51 PM PDT 24
Peak memory 191028 kb
Host smart-e63c150b-3f40-4799-971d-d780e158e286
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853713842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.3853713842
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.3213347690
Short name T95
Test name
Test status
Simulation time 18443416 ps
CPU time 0.57 seconds
Started Aug 03 04:23:26 PM PDT 24
Finished Aug 03 04:23:27 PM PDT 24
Peak memory 182668 kb
Host smart-7ae8b04e-cfa9-47d4-82a1-7372fafb69e3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213347690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.3213347690
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3680580626
Short name T477
Test name
Test status
Simulation time 31860823 ps
CPU time 0.65 seconds
Started Aug 03 04:23:18 PM PDT 24
Finished Aug 03 04:23:19 PM PDT 24
Peak memory 191080 kb
Host smart-51151ecd-01d8-4f6b-807e-5de42821e263
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680580626 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.3680580626
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.3529605044
Short name T542
Test name
Test status
Simulation time 12035652 ps
CPU time 0.55 seconds
Started Aug 03 04:21:50 PM PDT 24
Finished Aug 03 04:21:51 PM PDT 24
Peak memory 182404 kb
Host smart-cf230969-a227-40f7-baeb-876fd2868608
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529605044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.3529605044
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.3941951616
Short name T533
Test name
Test status
Simulation time 52182981 ps
CPU time 0.52 seconds
Started Aug 03 04:23:39 PM PDT 24
Finished Aug 03 04:23:40 PM PDT 24
Peak memory 182408 kb
Host smart-742e618e-db6f-4136-99c0-29f8254942b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941951616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.3941951616
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.1553188579
Short name T565
Test name
Test status
Simulation time 91115528 ps
CPU time 0.65 seconds
Started Aug 03 04:21:50 PM PDT 24
Finished Aug 03 04:21:51 PM PDT 24
Peak memory 191672 kb
Host smart-d88dd36e-95da-4c74-98f3-e8fcfcaaedb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553188579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.1553188579
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.276538591
Short name T514
Test name
Test status
Simulation time 926910053 ps
CPU time 1.21 seconds
Started Aug 03 04:23:25 PM PDT 24
Finished Aug 03 04:23:27 PM PDT 24
Peak memory 197384 kb
Host smart-a77eba03-54bb-4893-9549-6d5ac339e011
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276538591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.276538591
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.370211426
Short name T495
Test name
Test status
Simulation time 90336126 ps
CPU time 1.04 seconds
Started Aug 03 04:21:58 PM PDT 24
Finished Aug 03 04:21:59 PM PDT 24
Peak memory 194940 kb
Host smart-8100fd27-d265-42fa-92a9-f6cfbc1ea628
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370211426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_int
g_err.370211426
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.1166396565
Short name T473
Test name
Test status
Simulation time 13186248 ps
CPU time 0.54 seconds
Started Aug 03 04:23:58 PM PDT 24
Finished Aug 03 04:23:59 PM PDT 24
Peak memory 182572 kb
Host smart-42dfd63e-78a0-4981-b029-18611b0eae64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166396565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.1166396565
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.1394512748
Short name T492
Test name
Test status
Simulation time 83837796 ps
CPU time 0.56 seconds
Started Aug 03 04:22:24 PM PDT 24
Finished Aug 03 04:22:24 PM PDT 24
Peak memory 182496 kb
Host smart-c44454d5-9a2c-4aeb-980f-4774c04d8de8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394512748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.1394512748
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1745998640
Short name T476
Test name
Test status
Simulation time 14716782 ps
CPU time 0.58 seconds
Started Aug 03 04:22:23 PM PDT 24
Finished Aug 03 04:22:23 PM PDT 24
Peak memory 181944 kb
Host smart-8b548ad5-f130-47fd-8594-59847b63e2e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745998640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.1745998640
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.1042884871
Short name T505
Test name
Test status
Simulation time 21503961 ps
CPU time 0.54 seconds
Started Aug 03 04:23:52 PM PDT 24
Finished Aug 03 04:23:52 PM PDT 24
Peak memory 182212 kb
Host smart-e21ec326-a56e-4211-a5f6-cdd6ff127479
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042884871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.1042884871
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.827798295
Short name T538
Test name
Test status
Simulation time 32060860 ps
CPU time 0.59 seconds
Started Aug 03 04:22:18 PM PDT 24
Finished Aug 03 04:22:19 PM PDT 24
Peak memory 182516 kb
Host smart-8d54685c-14b7-43a6-a671-fbabac127080
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827798295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.827798295
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1744708495
Short name T501
Test name
Test status
Simulation time 32918415 ps
CPU time 0.55 seconds
Started Aug 03 04:22:32 PM PDT 24
Finished Aug 03 04:22:32 PM PDT 24
Peak memory 182512 kb
Host smart-cd41b2d7-37df-41a6-b11a-65eb28839c00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744708495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.1744708495
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.1761635295
Short name T461
Test name
Test status
Simulation time 27321294 ps
CPU time 0.56 seconds
Started Aug 03 04:22:35 PM PDT 24
Finished Aug 03 04:22:36 PM PDT 24
Peak memory 182524 kb
Host smart-e69a49e5-7b3a-44b2-82a9-49090ef83cd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761635295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.1761635295
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.641627242
Short name T519
Test name
Test status
Simulation time 64744926 ps
CPU time 0.62 seconds
Started Aug 03 04:23:33 PM PDT 24
Finished Aug 03 04:23:34 PM PDT 24
Peak memory 181732 kb
Host smart-ecb8c93d-35e4-4fb3-89ec-d8285477398e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641627242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.641627242
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.593183368
Short name T567
Test name
Test status
Simulation time 30975724 ps
CPU time 0.53 seconds
Started Aug 03 04:22:31 PM PDT 24
Finished Aug 03 04:22:31 PM PDT 24
Peak memory 182528 kb
Host smart-f4bdbac4-e3eb-47bd-b3d3-243013722124
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593183368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.593183368
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.3060748352
Short name T536
Test name
Test status
Simulation time 50026448 ps
CPU time 0.55 seconds
Started Aug 03 04:23:44 PM PDT 24
Finished Aug 03 04:23:45 PM PDT 24
Peak memory 182524 kb
Host smart-091a4c37-0000-4249-be1a-9bd643da2b2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060748352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.3060748352
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.337990135
Short name T68
Test name
Test status
Simulation time 39311561 ps
CPU time 0.7 seconds
Started Aug 03 04:23:19 PM PDT 24
Finished Aug 03 04:23:20 PM PDT 24
Peak memory 194696 kb
Host smart-c4ad8f72-c958-4d3f-8dfa-ee15e74c11b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337990135 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.337990135
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.1644053912
Short name T578
Test name
Test status
Simulation time 54916551 ps
CPU time 0.54 seconds
Started Aug 03 04:23:21 PM PDT 24
Finished Aug 03 04:23:21 PM PDT 24
Peak memory 182388 kb
Host smart-b2947562-a1a3-46bc-9ad8-92dc4cde926b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644053912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.1644053912
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1392680510
Short name T480
Test name
Test status
Simulation time 11405993 ps
CPU time 0.54 seconds
Started Aug 03 04:23:32 PM PDT 24
Finished Aug 03 04:23:33 PM PDT 24
Peak memory 182144 kb
Host smart-43879b55-5f63-44f7-bde8-9d4714ce2faa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392680510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.1392680510
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1190532091
Short name T105
Test name
Test status
Simulation time 14519788 ps
CPU time 0.67 seconds
Started Aug 03 04:22:02 PM PDT 24
Finished Aug 03 04:22:03 PM PDT 24
Peak memory 191936 kb
Host smart-f728085a-ef13-4d8d-bcf2-d2b58bc7f328
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190532091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.1190532091
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.1823738931
Short name T496
Test name
Test status
Simulation time 28451125 ps
CPU time 1.43 seconds
Started Aug 03 04:21:56 PM PDT 24
Finished Aug 03 04:21:58 PM PDT 24
Peak memory 197436 kb
Host smart-27be4967-4114-4e96-9763-44c02b5f8ddc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823738931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.1823738931
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1329365790
Short name T107
Test name
Test status
Simulation time 256214882 ps
CPU time 1.25 seconds
Started Aug 03 04:23:58 PM PDT 24
Finished Aug 03 04:24:05 PM PDT 24
Peak memory 194468 kb
Host smart-caa0032c-fb84-404e-b371-1285ad4c75b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329365790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.1329365790
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3584510509
Short name T560
Test name
Test status
Simulation time 29818770 ps
CPU time 0.65 seconds
Started Aug 03 04:23:13 PM PDT 24
Finished Aug 03 04:23:14 PM PDT 24
Peak memory 194192 kb
Host smart-138b087a-736b-4aff-9797-27da15f62ab3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584510509 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.3584510509
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.67119866
Short name T97
Test name
Test status
Simulation time 13918719 ps
CPU time 0.51 seconds
Started Aug 03 04:23:21 PM PDT 24
Finished Aug 03 04:23:21 PM PDT 24
Peak memory 182152 kb
Host smart-551da9c8-f02a-4a61-8703-cb3cf1abbbf6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67119866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.67119866
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.3508294952
Short name T462
Test name
Test status
Simulation time 29370202 ps
CPU time 0.54 seconds
Started Aug 03 04:23:19 PM PDT 24
Finished Aug 03 04:23:20 PM PDT 24
Peak memory 182368 kb
Host smart-8397fb87-4a33-4656-a592-f6a7e390c326
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508294952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.3508294952
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.907705634
Short name T563
Test name
Test status
Simulation time 60469997 ps
CPU time 0.6 seconds
Started Aug 03 04:23:18 PM PDT 24
Finished Aug 03 04:23:19 PM PDT 24
Peak memory 189400 kb
Host smart-02be873f-efbf-4174-adb8-9283daa130dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907705634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_tim
er_same_csr_outstanding.907705634
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.3226740744
Short name T472
Test name
Test status
Simulation time 198959004 ps
CPU time 2.6 seconds
Started Aug 03 04:21:58 PM PDT 24
Finished Aug 03 04:22:01 PM PDT 24
Peak memory 197300 kb
Host smart-2bd19f7b-e994-42cf-94f4-00f38e42359f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226740744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.3226740744
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.3777400796
Short name T572
Test name
Test status
Simulation time 60286261 ps
CPU time 0.8 seconds
Started Aug 03 04:23:32 PM PDT 24
Finished Aug 03 04:23:33 PM PDT 24
Peak memory 183196 kb
Host smart-fa631bd9-ae3e-40c0-bb27-ba64613c582f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777400796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.3777400796
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.949820523
Short name T520
Test name
Test status
Simulation time 108329811 ps
CPU time 0.66 seconds
Started Aug 03 04:23:17 PM PDT 24
Finished Aug 03 04:23:18 PM PDT 24
Peak memory 194848 kb
Host smart-12a42d46-656c-4826-a26b-6abdadce3276
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949820523 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.949820523
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.941676976
Short name T91
Test name
Test status
Simulation time 15091648 ps
CPU time 0.6 seconds
Started Aug 03 04:23:33 PM PDT 24
Finished Aug 03 04:23:33 PM PDT 24
Peak memory 182656 kb
Host smart-bd6f89e6-ec42-48ed-88f2-d91b6c39788b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941676976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.941676976
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.3263956034
Short name T493
Test name
Test status
Simulation time 10928895 ps
CPU time 0.55 seconds
Started Aug 03 04:21:55 PM PDT 24
Finished Aug 03 04:21:56 PM PDT 24
Peak memory 182220 kb
Host smart-fd92ce20-1264-4607-b542-998651551237
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263956034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.3263956034
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3121944226
Short name T80
Test name
Test status
Simulation time 94719259 ps
CPU time 0.73 seconds
Started Aug 03 04:23:32 PM PDT 24
Finished Aug 03 04:23:33 PM PDT 24
Peak memory 193112 kb
Host smart-28d5dced-4145-4f01-b90f-14dcae16d1e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121944226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.3121944226
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.3717324370
Short name T481
Test name
Test status
Simulation time 161476311 ps
CPU time 1.7 seconds
Started Aug 03 04:24:17 PM PDT 24
Finished Aug 03 04:24:19 PM PDT 24
Peak memory 197336 kb
Host smart-7e3d6e62-42da-42f4-8f59-270e8ef0f234
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717324370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.3717324370
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.3886138912
Short name T23
Test name
Test status
Simulation time 67329014 ps
CPU time 1.01 seconds
Started Aug 03 04:24:24 PM PDT 24
Finished Aug 03 04:24:25 PM PDT 24
Peak memory 194952 kb
Host smart-34ad48a9-e3bd-44a8-9b9b-fccd44539f8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886138912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.3886138912
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.1940009109
Short name T512
Test name
Test status
Simulation time 217252666 ps
CPU time 1.24 seconds
Started Aug 03 04:22:16 PM PDT 24
Finished Aug 03 04:22:18 PM PDT 24
Peak memory 197568 kb
Host smart-784b38c1-9902-40c7-b745-7dfc7bc0cdd9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940009109 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.1940009109
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.2537541779
Short name T549
Test name
Test status
Simulation time 14986487 ps
CPU time 0.64 seconds
Started Aug 03 04:22:01 PM PDT 24
Finished Aug 03 04:22:02 PM PDT 24
Peak memory 182696 kb
Host smart-50adbb6c-34ff-4832-a54b-ce6dd8de390b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537541779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.2537541779
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.831982434
Short name T537
Test name
Test status
Simulation time 41582999 ps
CPU time 0.54 seconds
Started Aug 03 04:23:28 PM PDT 24
Finished Aug 03 04:23:29 PM PDT 24
Peak memory 182412 kb
Host smart-6ac230c5-d1f1-4af3-a0e3-81cd5d32b0ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831982434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.831982434
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.418908966
Short name T103
Test name
Test status
Simulation time 148820929 ps
CPU time 0.61 seconds
Started Aug 03 04:23:20 PM PDT 24
Finished Aug 03 04:23:20 PM PDT 24
Peak memory 191584 kb
Host smart-2c036337-0f53-4e87-89e8-8604f4753750
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418908966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_tim
er_same_csr_outstanding.418908966
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.179318798
Short name T507
Test name
Test status
Simulation time 242641825 ps
CPU time 1.44 seconds
Started Aug 03 04:22:15 PM PDT 24
Finished Aug 03 04:22:17 PM PDT 24
Peak memory 197204 kb
Host smart-37e38b54-231a-4656-942a-533faefa7d3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179318798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.179318798
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.1459334656
Short name T500
Test name
Test status
Simulation time 260452243 ps
CPU time 1 seconds
Started Aug 03 04:24:15 PM PDT 24
Finished Aug 03 04:24:16 PM PDT 24
Peak memory 183424 kb
Host smart-8f8cc10b-15e6-4e67-b12c-4f9eb9d9e9f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459334656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.1459334656
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.2772564040
Short name T48
Test name
Test status
Simulation time 166796363 ps
CPU time 0.96 seconds
Started Aug 03 04:21:58 PM PDT 24
Finished Aug 03 04:22:00 PM PDT 24
Peak memory 197240 kb
Host smart-3e436441-aa8f-4993-90f0-70e5bfffa0f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772564040 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.2772564040
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.2792784079
Short name T96
Test name
Test status
Simulation time 15282576 ps
CPU time 0.6 seconds
Started Aug 03 04:23:32 PM PDT 24
Finished Aug 03 04:23:33 PM PDT 24
Peak memory 191876 kb
Host smart-bfee43f8-9ecb-41bc-a637-7063ffbf7738
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792784079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.2792784079
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.2083048137
Short name T504
Test name
Test status
Simulation time 64701715 ps
CPU time 0.6 seconds
Started Aug 03 04:23:13 PM PDT 24
Finished Aug 03 04:23:14 PM PDT 24
Peak memory 181152 kb
Host smart-20e286a9-5fb1-4a88-88aa-4f81c6b356b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083048137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.2083048137
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1247662044
Short name T540
Test name
Test status
Simulation time 12126497 ps
CPU time 0.57 seconds
Started Aug 03 04:24:29 PM PDT 24
Finished Aug 03 04:24:34 PM PDT 24
Peak memory 191276 kb
Host smart-ad81f349-5896-4bfa-aed5-60e9a792f53b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247662044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.1247662044
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.937644420
Short name T483
Test name
Test status
Simulation time 226464367 ps
CPU time 1.17 seconds
Started Aug 03 04:23:32 PM PDT 24
Finished Aug 03 04:23:33 PM PDT 24
Peak memory 197440 kb
Host smart-191c4d66-b510-440e-aa23-8bc148cec29c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937644420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.937644420
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3810165376
Short name T508
Test name
Test status
Simulation time 293935796 ps
CPU time 1.01 seconds
Started Aug 03 04:24:08 PM PDT 24
Finished Aug 03 04:24:10 PM PDT 24
Peak memory 194744 kb
Host smart-f73c3f0f-57d2-40f5-8eb0-9ebf38a9b5a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810165376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.3810165376
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.733349456
Short name T379
Test name
Test status
Simulation time 176087213217 ps
CPU time 67.37 seconds
Started Aug 03 04:24:58 PM PDT 24
Finished Aug 03 04:26:05 PM PDT 24
Peak memory 183316 kb
Host smart-8cd69435-8013-4a91-85c1-580f6164dd9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733349456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.733349456
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.123058741
Short name T437
Test name
Test status
Simulation time 51893237110 ps
CPU time 263.2 seconds
Started Aug 03 04:24:50 PM PDT 24
Finished Aug 03 04:29:13 PM PDT 24
Peak memory 183260 kb
Host smart-29767947-08b1-48ce-894e-8dc2951b52f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123058741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.123058741
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.3302858419
Short name T356
Test name
Test status
Simulation time 174794364107 ps
CPU time 60.74 seconds
Started Aug 03 04:25:00 PM PDT 24
Finished Aug 03 04:26:01 PM PDT 24
Peak memory 183132 kb
Host smart-8916ccdc-d595-4d27-8a94-366bab643f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302858419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.3302858419
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.2434200938
Short name T310
Test name
Test status
Simulation time 403120594461 ps
CPU time 203.14 seconds
Started Aug 03 04:24:54 PM PDT 24
Finished Aug 03 04:28:17 PM PDT 24
Peak memory 183248 kb
Host smart-8f74fd3d-e09c-415d-8680-9b3d676ca38d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434200938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.2434200938
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.1172223225
Short name T72
Test name
Test status
Simulation time 362053560627 ps
CPU time 252.95 seconds
Started Aug 03 04:24:50 PM PDT 24
Finished Aug 03 04:29:03 PM PDT 24
Peak memory 183276 kb
Host smart-ab3a1c5b-6856-43e9-bb52-8128fb71c0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172223225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.1172223225
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.314949186
Short name T86
Test name
Test status
Simulation time 331108853561 ps
CPU time 191.3 seconds
Started Aug 03 04:25:00 PM PDT 24
Finished Aug 03 04:28:11 PM PDT 24
Peak memory 192640 kb
Host smart-11edcceb-7887-4ec4-ad1d-fd373866a936
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314949186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.314949186
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.3583121808
Short name T17
Test name
Test status
Simulation time 33730432 ps
CPU time 0.73 seconds
Started Aug 03 04:25:10 PM PDT 24
Finished Aug 03 04:25:11 PM PDT 24
Peak memory 213880 kb
Host smart-94ffa07c-bd54-408e-85d9-10ca7a0f91a5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583121808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.3583121808
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all_with_rand_reset.2166200145
Short name T361
Test name
Test status
Simulation time 57103228644 ps
CPU time 322.9 seconds
Started Aug 03 04:24:58 PM PDT 24
Finished Aug 03 04:30:21 PM PDT 24
Peak memory 206152 kb
Host smart-8dc802ac-ff43-4463-9a5d-c7f7d381b5bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166200145 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all_with_rand_reset.2166200145
Directory /workspace/1.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.3048352031
Short name T87
Test name
Test status
Simulation time 414615300742 ps
CPU time 180.28 seconds
Started Aug 03 04:25:08 PM PDT 24
Finished Aug 03 04:28:09 PM PDT 24
Peak memory 183380 kb
Host smart-2b75976b-081a-4951-b270-0435a7f00f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048352031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.3048352031
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.609272983
Short name T272
Test name
Test status
Simulation time 812156071191 ps
CPU time 780.22 seconds
Started Aug 03 04:25:22 PM PDT 24
Finished Aug 03 04:38:23 PM PDT 24
Peak memory 191488 kb
Host smart-c8c8d52d-2143-4194-b21a-8ad65ddb2f7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609272983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.609272983
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.1711377692
Short name T432
Test name
Test status
Simulation time 375978712893 ps
CPU time 194.7 seconds
Started Aug 03 04:25:02 PM PDT 24
Finished Aug 03 04:28:18 PM PDT 24
Peak memory 190628 kb
Host smart-591ac77a-3b04-44df-bc49-c30a56910a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711377692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.1711377692
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.3478477815
Short name T349
Test name
Test status
Simulation time 65896073185 ps
CPU time 887.99 seconds
Started Aug 03 04:25:42 PM PDT 24
Finished Aug 03 04:40:30 PM PDT 24
Peak memory 191184 kb
Host smart-f4aa6fad-ea26-41c7-b944-888a1b494a7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478477815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.3478477815
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/100.rv_timer_random.207499698
Short name T318
Test name
Test status
Simulation time 13210082876 ps
CPU time 13.13 seconds
Started Aug 03 04:25:31 PM PDT 24
Finished Aug 03 04:25:44 PM PDT 24
Peak memory 183248 kb
Host smart-d08887eb-36d4-4bba-b1fb-561a8bff3d91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207499698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.207499698
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.1200522554
Short name T40
Test name
Test status
Simulation time 58398354421 ps
CPU time 120.58 seconds
Started Aug 03 04:25:54 PM PDT 24
Finished Aug 03 04:27:55 PM PDT 24
Peak memory 191420 kb
Host smart-9bfa7688-4db5-4b1a-a968-ac2beff7449f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200522554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.1200522554
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.865120321
Short name T73
Test name
Test status
Simulation time 82432963126 ps
CPU time 178.36 seconds
Started Aug 03 04:25:29 PM PDT 24
Finished Aug 03 04:28:28 PM PDT 24
Peak memory 191488 kb
Host smart-c2081bda-446d-4453-b9bf-5ced16dbced5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865120321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.865120321
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.3519344272
Short name T157
Test name
Test status
Simulation time 134283371417 ps
CPU time 258.87 seconds
Started Aug 03 04:25:35 PM PDT 24
Finished Aug 03 04:29:54 PM PDT 24
Peak memory 191536 kb
Host smart-d3780270-676b-4aa7-b7c2-f5a3b4d41934
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519344272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.3519344272
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.2074121417
Short name T403
Test name
Test status
Simulation time 46858925555 ps
CPU time 239.35 seconds
Started Aug 03 04:25:47 PM PDT 24
Finished Aug 03 04:29:47 PM PDT 24
Peak memory 183416 kb
Host smart-8373517c-e374-46ce-8e9b-9aa8dc8fa3a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074121417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.2074121417
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.1936243068
Short name T410
Test name
Test status
Simulation time 728891091249 ps
CPU time 249.12 seconds
Started Aug 03 04:24:49 PM PDT 24
Finished Aug 03 04:28:58 PM PDT 24
Peak memory 183200 kb
Host smart-7ee025de-aba9-4380-9129-732feea51256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936243068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.1936243068
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.4206844469
Short name T112
Test name
Test status
Simulation time 175536789657 ps
CPU time 167.07 seconds
Started Aug 03 04:25:00 PM PDT 24
Finished Aug 03 04:27:47 PM PDT 24
Peak memory 191456 kb
Host smart-449bcfbc-18b6-4697-a966-75e44c1c048c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206844469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.4206844469
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.3389269687
Short name T192
Test name
Test status
Simulation time 35262485741 ps
CPU time 200.19 seconds
Started Aug 03 04:25:07 PM PDT 24
Finished Aug 03 04:28:28 PM PDT 24
Peak memory 183228 kb
Host smart-5bdea31b-173b-4f71-b269-85430c2c4567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389269687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.3389269687
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.753258284
Short name T162
Test name
Test status
Simulation time 395484085100 ps
CPU time 2493.12 seconds
Started Aug 03 04:25:10 PM PDT 24
Finished Aug 03 05:06:44 PM PDT 24
Peak memory 191448 kb
Host smart-d91bc4bb-103f-4588-a15f-59f30a1c3cba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753258284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all.
753258284
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/110.rv_timer_random.3084606166
Short name T339
Test name
Test status
Simulation time 249281797231 ps
CPU time 118.6 seconds
Started Aug 03 04:25:35 PM PDT 24
Finished Aug 03 04:27:39 PM PDT 24
Peak memory 194960 kb
Host smart-3103e00c-3ff8-4c9e-a658-c2d90d441987
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084606166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.3084606166
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.712510898
Short name T334
Test name
Test status
Simulation time 15612242730 ps
CPU time 7.15 seconds
Started Aug 03 04:25:16 PM PDT 24
Finished Aug 03 04:25:24 PM PDT 24
Peak memory 183308 kb
Host smart-15303010-a213-4ce3-9977-22172fb8c080
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712510898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.712510898
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.3988795635
Short name T235
Test name
Test status
Simulation time 533665768820 ps
CPU time 547.44 seconds
Started Aug 03 04:25:47 PM PDT 24
Finished Aug 03 04:34:55 PM PDT 24
Peak memory 191500 kb
Host smart-c2d9a8e6-ed05-4992-87eb-8520ad07020c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988795635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.3988795635
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.817724614
Short name T285
Test name
Test status
Simulation time 47274279138 ps
CPU time 91.83 seconds
Started Aug 03 04:25:33 PM PDT 24
Finished Aug 03 04:27:05 PM PDT 24
Peak memory 191492 kb
Host smart-2addb526-ea02-44d4-984f-bdf8daa9027a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817724614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.817724614
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.4032121810
Short name T429
Test name
Test status
Simulation time 84166312398 ps
CPU time 124.25 seconds
Started Aug 03 04:25:49 PM PDT 24
Finished Aug 03 04:27:53 PM PDT 24
Peak memory 191444 kb
Host smart-484b41f6-a4af-4730-ab79-3f5da3ba5b49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032121810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.4032121810
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.1149525897
Short name T420
Test name
Test status
Simulation time 181952623670 ps
CPU time 140.14 seconds
Started Aug 03 04:25:10 PM PDT 24
Finished Aug 03 04:27:30 PM PDT 24
Peak memory 182992 kb
Host smart-a009ab57-d636-4b36-9a08-c77b380144fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149525897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.1149525897
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.674572862
Short name T232
Test name
Test status
Simulation time 429323328814 ps
CPU time 1880.02 seconds
Started Aug 03 04:25:28 PM PDT 24
Finished Aug 03 04:56:49 PM PDT 24
Peak memory 195496 kb
Host smart-189d1704-14e8-4e1b-b562-3a3e37791aec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674572862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all.
674572862
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all_with_rand_reset.3984475509
Short name T31
Test name
Test status
Simulation time 66498626584 ps
CPU time 679.67 seconds
Started Aug 03 04:25:24 PM PDT 24
Finished Aug 03 04:36:44 PM PDT 24
Peak memory 209832 kb
Host smart-962caacb-44d8-4660-952e-d26aa1967b81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984475509 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all_with_rand_reset.3984475509
Directory /workspace/12.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.rv_timer_random.1338000887
Short name T283
Test name
Test status
Simulation time 30875593603 ps
CPU time 45.35 seconds
Started Aug 03 04:25:44 PM PDT 24
Finished Aug 03 04:26:29 PM PDT 24
Peak memory 191492 kb
Host smart-b54fec3f-b981-4714-b38a-71eeed8b3c85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338000887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.1338000887
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.2272906958
Short name T286
Test name
Test status
Simulation time 99712251033 ps
CPU time 147.17 seconds
Started Aug 03 04:25:52 PM PDT 24
Finished Aug 03 04:28:20 PM PDT 24
Peak memory 194936 kb
Host smart-bb3d6de0-7bde-4fef-a67e-c1f414782fcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272906958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.2272906958
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.3264408257
Short name T227
Test name
Test status
Simulation time 465642786593 ps
CPU time 209.65 seconds
Started Aug 03 04:25:38 PM PDT 24
Finished Aug 03 04:29:08 PM PDT 24
Peak memory 191520 kb
Host smart-a2e57f0e-f7ce-402d-8bd9-c042a14f64ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264408257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.3264408257
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.1863340028
Short name T352
Test name
Test status
Simulation time 94090531141 ps
CPU time 376.82 seconds
Started Aug 03 04:26:01 PM PDT 24
Finished Aug 03 04:32:18 PM PDT 24
Peak memory 191508 kb
Host smart-1f939e14-9a2f-47b6-b178-ff53cd93da63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863340028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.1863340028
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.2968514993
Short name T421
Test name
Test status
Simulation time 124396580902 ps
CPU time 207.75 seconds
Started Aug 03 04:25:48 PM PDT 24
Finished Aug 03 04:29:17 PM PDT 24
Peak memory 183596 kb
Host smart-e3c0f550-7f8c-4ed2-ac8e-38ec5712eb77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968514993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.2968514993
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.1586480952
Short name T269
Test name
Test status
Simulation time 205541261047 ps
CPU time 523.07 seconds
Started Aug 03 04:25:40 PM PDT 24
Finished Aug 03 04:34:24 PM PDT 24
Peak memory 191464 kb
Host smart-b10c5d8e-434e-4234-be71-b09d115aa3a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586480952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.1586480952
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.1740030452
Short name T320
Test name
Test status
Simulation time 536907136905 ps
CPU time 295.61 seconds
Started Aug 03 04:25:44 PM PDT 24
Finished Aug 03 04:30:40 PM PDT 24
Peak memory 191496 kb
Host smart-b0eba00f-40b9-49ea-b9a4-495da078ddad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740030452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.1740030452
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.2389375604
Short name T430
Test name
Test status
Simulation time 173911789177 ps
CPU time 270.65 seconds
Started Aug 03 04:25:12 PM PDT 24
Finished Aug 03 04:29:43 PM PDT 24
Peak memory 183324 kb
Host smart-18c16187-bb19-4bdc-b27b-518bb83911d6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389375604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.2389375604
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.820651641
Short name T444
Test name
Test status
Simulation time 115118640935 ps
CPU time 160.04 seconds
Started Aug 03 04:25:31 PM PDT 24
Finished Aug 03 04:28:11 PM PDT 24
Peak memory 183340 kb
Host smart-42eda318-9a38-4534-9ca3-6b2a67d0e778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820651641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.820651641
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.2336169410
Short name T412
Test name
Test status
Simulation time 769060412 ps
CPU time 0.6 seconds
Started Aug 03 04:25:10 PM PDT 24
Finished Aug 03 04:25:11 PM PDT 24
Peak memory 183016 kb
Host smart-2344f6d6-c339-4aca-acb5-646d9de06e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336169410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.2336169410
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.3597722273
Short name T248
Test name
Test status
Simulation time 430673613083 ps
CPU time 584.59 seconds
Started Aug 03 04:25:16 PM PDT 24
Finished Aug 03 04:35:01 PM PDT 24
Peak memory 191524 kb
Host smart-5d61f328-0a79-45ca-8d6b-5ecd8436158b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597722273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.3597722273
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/130.rv_timer_random.850300951
Short name T234
Test name
Test status
Simulation time 204799844043 ps
CPU time 2162.78 seconds
Started Aug 03 04:25:38 PM PDT 24
Finished Aug 03 05:01:41 PM PDT 24
Peak memory 191464 kb
Host smart-c6abc185-55a9-4679-9fcc-ca69c6038317
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850300951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.850300951
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.2313978527
Short name T295
Test name
Test status
Simulation time 422116926345 ps
CPU time 261.83 seconds
Started Aug 03 04:25:23 PM PDT 24
Finished Aug 03 04:29:45 PM PDT 24
Peak memory 191172 kb
Host smart-7135b823-a3f6-45df-adee-e4353394c12b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313978527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.2313978527
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.104659331
Short name T338
Test name
Test status
Simulation time 722918354075 ps
CPU time 285.09 seconds
Started Aug 03 04:25:43 PM PDT 24
Finished Aug 03 04:30:28 PM PDT 24
Peak memory 191532 kb
Host smart-20e73e74-cb6b-48fa-80b1-429c90ed7905
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104659331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.104659331
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.2634440665
Short name T195
Test name
Test status
Simulation time 53748553743 ps
CPU time 244.78 seconds
Started Aug 03 04:25:53 PM PDT 24
Finished Aug 03 04:29:58 PM PDT 24
Peak memory 191472 kb
Host smart-b70e53fa-2829-4ef9-a204-7bc600192bbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634440665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.2634440665
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.1544193830
Short name T446
Test name
Test status
Simulation time 285812139398 ps
CPU time 536.74 seconds
Started Aug 03 04:25:42 PM PDT 24
Finished Aug 03 04:34:39 PM PDT 24
Peak memory 191492 kb
Host smart-460e20fd-eb65-455d-b708-c84628e2f823
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544193830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.1544193830
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.246601062
Short name T70
Test name
Test status
Simulation time 75120260191 ps
CPU time 109.28 seconds
Started Aug 03 04:25:47 PM PDT 24
Finished Aug 03 04:27:37 PM PDT 24
Peak memory 195020 kb
Host smart-429c4531-7316-408b-9ac5-7294206eca3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246601062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.246601062
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.3268602111
Short name T443
Test name
Test status
Simulation time 356869666980 ps
CPU time 202.09 seconds
Started Aug 03 04:25:44 PM PDT 24
Finished Aug 03 04:29:07 PM PDT 24
Peak memory 191512 kb
Host smart-93351f13-2920-490b-831a-d1aed3a00080
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268602111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.3268602111
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.3416144385
Short name T7
Test name
Test status
Simulation time 172717028443 ps
CPU time 99.8 seconds
Started Aug 03 04:25:47 PM PDT 24
Finished Aug 03 04:27:27 PM PDT 24
Peak memory 191536 kb
Host smart-c7c2a220-ece2-4b95-876b-6dac55f1a9ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416144385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.3416144385
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.2938703793
Short name T307
Test name
Test status
Simulation time 2804492319148 ps
CPU time 754.81 seconds
Started Aug 03 04:25:12 PM PDT 24
Finished Aug 03 04:37:47 PM PDT 24
Peak memory 183268 kb
Host smart-ef2d2a14-2e2d-486c-8352-b36d104a51e6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938703793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.2938703793
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.2294807463
Short name T393
Test name
Test status
Simulation time 63461494948 ps
CPU time 88.6 seconds
Started Aug 03 04:25:10 PM PDT 24
Finished Aug 03 04:26:39 PM PDT 24
Peak memory 183256 kb
Host smart-53d5acab-c98d-47af-ab04-4a39e0d7a624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294807463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.2294807463
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.3976982595
Short name T56
Test name
Test status
Simulation time 610088646434 ps
CPU time 447.82 seconds
Started Aug 03 04:24:58 PM PDT 24
Finished Aug 03 04:32:26 PM PDT 24
Peak memory 191504 kb
Host smart-195c9c92-dba5-464c-bc0e-2f522f3fee97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976982595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.3976982595
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.2927323906
Short name T61
Test name
Test status
Simulation time 264826709961 ps
CPU time 461.43 seconds
Started Aug 03 04:25:12 PM PDT 24
Finished Aug 03 04:32:53 PM PDT 24
Peak memory 195964 kb
Host smart-6121331c-1ea9-412d-aef6-654cb21fefab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927323906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.2927323906
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/141.rv_timer_random.2044616037
Short name T2
Test name
Test status
Simulation time 107423457018 ps
CPU time 581.84 seconds
Started Aug 03 04:25:40 PM PDT 24
Finished Aug 03 04:35:22 PM PDT 24
Peak memory 191456 kb
Host smart-4cf38797-2b64-4ba3-b5d1-2e83dd8afdbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044616037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.2044616037
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.227477465
Short name T240
Test name
Test status
Simulation time 191874004920 ps
CPU time 160.09 seconds
Started Aug 03 04:25:48 PM PDT 24
Finished Aug 03 04:28:29 PM PDT 24
Peak memory 191476 kb
Host smart-e97efe0a-c87b-42c9-bf2c-f0a4f514e9bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227477465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.227477465
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.2878462732
Short name T155
Test name
Test status
Simulation time 113834099434 ps
CPU time 1803.96 seconds
Started Aug 03 04:25:52 PM PDT 24
Finished Aug 03 04:55:56 PM PDT 24
Peak memory 195020 kb
Host smart-78800a22-e23e-498b-8de9-48ffedf0f999
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878462732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.2878462732
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.2762265157
Short name T125
Test name
Test status
Simulation time 116486683638 ps
CPU time 182.37 seconds
Started Aug 03 04:25:31 PM PDT 24
Finished Aug 03 04:28:34 PM PDT 24
Peak memory 191396 kb
Host smart-e362abbf-cd7c-4f7d-921d-456ad84973e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762265157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.2762265157
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.47013852
Short name T148
Test name
Test status
Simulation time 92690504327 ps
CPU time 312.63 seconds
Started Aug 03 04:25:55 PM PDT 24
Finished Aug 03 04:31:08 PM PDT 24
Peak memory 191540 kb
Host smart-e3eb7dc4-e4be-494a-9311-796a274bfbcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47013852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.47013852
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.159325950
Short name T363
Test name
Test status
Simulation time 11680324874 ps
CPU time 7.02 seconds
Started Aug 03 04:25:28 PM PDT 24
Finished Aug 03 04:25:35 PM PDT 24
Peak memory 183140 kb
Host smart-39af3b3b-5432-4cd9-baee-de053e350b59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159325950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.159325950
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.3687499035
Short name T225
Test name
Test status
Simulation time 70820472389 ps
CPU time 120.02 seconds
Started Aug 03 04:25:36 PM PDT 24
Finished Aug 03 04:27:37 PM PDT 24
Peak memory 191488 kb
Host smart-896d5edd-09f0-4d75-9b1b-6208b2773fd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687499035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.3687499035
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.1403617578
Short name T321
Test name
Test status
Simulation time 572266129037 ps
CPU time 279.96 seconds
Started Aug 03 04:25:17 PM PDT 24
Finished Aug 03 04:29:57 PM PDT 24
Peak memory 183420 kb
Host smart-97baca06-b0b1-424c-8f6f-b9a942950e75
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403617578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.1403617578
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.1735602298
Short name T433
Test name
Test status
Simulation time 98931298494 ps
CPU time 40.33 seconds
Started Aug 03 04:25:22 PM PDT 24
Finished Aug 03 04:26:02 PM PDT 24
Peak memory 183288 kb
Host smart-434589ef-77a7-44e0-9461-80aa1dbb16e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735602298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.1735602298
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.2339411665
Short name T179
Test name
Test status
Simulation time 63782967002 ps
CPU time 105.33 seconds
Started Aug 03 04:25:39 PM PDT 24
Finished Aug 03 04:27:25 PM PDT 24
Peak memory 191480 kb
Host smart-7d7cea34-8768-4b31-880d-e0b85714b0b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339411665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.2339411665
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.161496416
Short name T373
Test name
Test status
Simulation time 80160629 ps
CPU time 0.69 seconds
Started Aug 03 04:25:11 PM PDT 24
Finished Aug 03 04:25:12 PM PDT 24
Peak memory 183356 kb
Host smart-5a9903ee-0385-4fc5-88bf-44f801cfec8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161496416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.161496416
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/151.rv_timer_random.4178682248
Short name T185
Test name
Test status
Simulation time 65488969982 ps
CPU time 102.42 seconds
Started Aug 03 04:25:39 PM PDT 24
Finished Aug 03 04:27:22 PM PDT 24
Peak memory 191492 kb
Host smart-780f2a03-ce33-4f0b-9797-34ae6f05f528
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178682248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.4178682248
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.3535010127
Short name T247
Test name
Test status
Simulation time 109466010233 ps
CPU time 60.17 seconds
Started Aug 03 04:25:36 PM PDT 24
Finished Aug 03 04:26:37 PM PDT 24
Peak memory 191496 kb
Host smart-65b2e21a-6ba9-4230-8014-5f7af0a1e37f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535010127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.3535010127
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.4217560127
Short name T287
Test name
Test status
Simulation time 172495518162 ps
CPU time 598.24 seconds
Started Aug 03 04:25:45 PM PDT 24
Finished Aug 03 04:35:43 PM PDT 24
Peak memory 191492 kb
Host smart-996680d4-c439-41a7-83d2-56fc6cbd7981
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217560127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.4217560127
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.3276193246
Short name T275
Test name
Test status
Simulation time 77230414037 ps
CPU time 54.49 seconds
Started Aug 03 04:25:51 PM PDT 24
Finished Aug 03 04:26:45 PM PDT 24
Peak memory 183284 kb
Host smart-07643850-3a9a-4d21-aa0d-4810f878b80b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276193246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.3276193246
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.2253454429
Short name T447
Test name
Test status
Simulation time 31390740875 ps
CPU time 50.21 seconds
Started Aug 03 04:25:56 PM PDT 24
Finished Aug 03 04:26:47 PM PDT 24
Peak memory 191520 kb
Host smart-838dda86-d023-4452-90de-fcdc96865a1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253454429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.2253454429
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.502576098
Short name T190
Test name
Test status
Simulation time 221064213071 ps
CPU time 259.23 seconds
Started Aug 03 04:25:11 PM PDT 24
Finished Aug 03 04:29:30 PM PDT 24
Peak memory 183236 kb
Host smart-12d558d9-9b6b-43ac-abf7-2b2bcc8fd7ea
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502576098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.rv_timer_cfg_update_on_fly.502576098
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.3757040008
Short name T35
Test name
Test status
Simulation time 311421097339 ps
CPU time 229.95 seconds
Started Aug 03 04:25:13 PM PDT 24
Finished Aug 03 04:29:08 PM PDT 24
Peak memory 182996 kb
Host smart-7b66f83a-ae68-46b0-b211-23e87cc3197d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757040008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.3757040008
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.608401225
Short name T253
Test name
Test status
Simulation time 122840024173 ps
CPU time 239.15 seconds
Started Aug 03 04:25:27 PM PDT 24
Finished Aug 03 04:29:26 PM PDT 24
Peak memory 191488 kb
Host smart-e41b280b-8dc7-4f97-8f4e-e2512679b260
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608401225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.608401225
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.1952712553
Short name T193
Test name
Test status
Simulation time 67894374166 ps
CPU time 107.93 seconds
Started Aug 03 04:25:09 PM PDT 24
Finished Aug 03 04:26:57 PM PDT 24
Peak memory 183272 kb
Host smart-102ac77c-d205-411f-b7db-8532480e6a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952712553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.1952712553
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/161.rv_timer_random.529656805
Short name T315
Test name
Test status
Simulation time 19231930786 ps
CPU time 32.21 seconds
Started Aug 03 04:25:46 PM PDT 24
Finished Aug 03 04:26:18 PM PDT 24
Peak memory 183276 kb
Host smart-72918b31-98e1-416c-b65c-078be0f2eb3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529656805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.529656805
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.192373617
Short name T243
Test name
Test status
Simulation time 532170874169 ps
CPU time 348.7 seconds
Started Aug 03 04:25:39 PM PDT 24
Finished Aug 03 04:31:28 PM PDT 24
Peak memory 191580 kb
Host smart-9a49d4b8-258f-48a1-bd30-ea4967516e0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192373617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.192373617
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.3039146537
Short name T350
Test name
Test status
Simulation time 904482410946 ps
CPU time 244.28 seconds
Started Aug 03 04:25:48 PM PDT 24
Finished Aug 03 04:29:52 PM PDT 24
Peak memory 191552 kb
Host smart-266dadbc-8dae-41f4-8709-e96aad1a47eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039146537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.3039146537
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.2327927015
Short name T138
Test name
Test status
Simulation time 106950667689 ps
CPU time 169.54 seconds
Started Aug 03 04:25:48 PM PDT 24
Finished Aug 03 04:28:38 PM PDT 24
Peak memory 195004 kb
Host smart-d4b2adf0-cde5-4cca-b22c-a5a68df6a84b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327927015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.2327927015
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.118261450
Short name T258
Test name
Test status
Simulation time 479593021067 ps
CPU time 352.59 seconds
Started Aug 03 04:25:49 PM PDT 24
Finished Aug 03 04:31:42 PM PDT 24
Peak memory 191536 kb
Host smart-748880ea-3919-45fb-9a9e-d490773a14cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118261450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.118261450
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.758894237
Short name T246
Test name
Test status
Simulation time 767305214033 ps
CPU time 715.69 seconds
Started Aug 03 04:25:51 PM PDT 24
Finished Aug 03 04:37:47 PM PDT 24
Peak memory 191460 kb
Host smart-7989df96-7087-46e0-bba7-60aa3d8668bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758894237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.758894237
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.3536188634
Short name T406
Test name
Test status
Simulation time 134598536231 ps
CPU time 46.85 seconds
Started Aug 03 04:25:04 PM PDT 24
Finished Aug 03 04:25:51 PM PDT 24
Peak memory 183348 kb
Host smart-213aaf58-761a-41b5-bc94-b6783e54e3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536188634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.3536188634
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.1964216996
Short name T399
Test name
Test status
Simulation time 61337044695 ps
CPU time 67.15 seconds
Started Aug 03 04:25:15 PM PDT 24
Finished Aug 03 04:26:23 PM PDT 24
Peak memory 191524 kb
Host smart-b67f4ce3-87b2-4518-8827-17436ea76e99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964216996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.1964216996
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.3546979855
Short name T448
Test name
Test status
Simulation time 14206813561 ps
CPU time 22.24 seconds
Started Aug 03 04:25:19 PM PDT 24
Finished Aug 03 04:25:42 PM PDT 24
Peak memory 183228 kb
Host smart-205120f0-77b3-476c-aed5-083610abae88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546979855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.3546979855
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/172.rv_timer_random.3363676321
Short name T445
Test name
Test status
Simulation time 109828807133 ps
CPU time 76.94 seconds
Started Aug 03 04:25:58 PM PDT 24
Finished Aug 03 04:27:15 PM PDT 24
Peak memory 191468 kb
Host smart-43efd22c-2579-4898-a0a8-167fcc2d5ebe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363676321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.3363676321
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.3537681971
Short name T164
Test name
Test status
Simulation time 816947347899 ps
CPU time 654.99 seconds
Started Aug 03 04:25:48 PM PDT 24
Finished Aug 03 04:36:44 PM PDT 24
Peak memory 191496 kb
Host smart-f0e63de1-acc3-40ab-ba1e-a59c86271969
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537681971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.3537681971
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.251368786
Short name T134
Test name
Test status
Simulation time 429535353910 ps
CPU time 351.36 seconds
Started Aug 03 04:25:52 PM PDT 24
Finished Aug 03 04:31:44 PM PDT 24
Peak memory 191476 kb
Host smart-e43c72bb-1949-491e-a68b-cf64c3e19b05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251368786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.251368786
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.2251263725
Short name T58
Test name
Test status
Simulation time 165736194994 ps
CPU time 824.31 seconds
Started Aug 03 04:25:52 PM PDT 24
Finished Aug 03 04:39:37 PM PDT 24
Peak memory 191484 kb
Host smart-284003ac-dfcb-40e2-a9d0-d6d0090ef8a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251263725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.2251263725
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.621828651
Short name T143
Test name
Test status
Simulation time 130541914745 ps
CPU time 128.89 seconds
Started Aug 03 04:25:44 PM PDT 24
Finished Aug 03 04:27:54 PM PDT 24
Peak memory 191484 kb
Host smart-87f6ec35-c059-4cd7-be49-5d657a3f95cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621828651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.621828651
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.1834803522
Short name T141
Test name
Test status
Simulation time 68657293565 ps
CPU time 44.62 seconds
Started Aug 03 04:25:47 PM PDT 24
Finished Aug 03 04:26:32 PM PDT 24
Peak memory 191500 kb
Host smart-c250237d-872b-42a1-a2c9-d522b037be23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834803522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.1834803522
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.908156251
Short name T304
Test name
Test status
Simulation time 546783565358 ps
CPU time 293.23 seconds
Started Aug 03 04:25:00 PM PDT 24
Finished Aug 03 04:29:53 PM PDT 24
Peak memory 183284 kb
Host smart-124fb826-5b68-4e01-96a3-81393e485948
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908156251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.rv_timer_cfg_update_on_fly.908156251
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.2845438683
Short name T371
Test name
Test status
Simulation time 762742797948 ps
CPU time 89.12 seconds
Started Aug 03 04:25:13 PM PDT 24
Finished Aug 03 04:26:43 PM PDT 24
Peak memory 183300 kb
Host smart-782eccee-9762-488d-98d6-d1bfa106f42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845438683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.2845438683
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.390022756
Short name T289
Test name
Test status
Simulation time 406812538853 ps
CPU time 99.56 seconds
Started Aug 03 04:25:08 PM PDT 24
Finished Aug 03 04:26:48 PM PDT 24
Peak memory 191552 kb
Host smart-cbb49c97-48fc-43f3-ad60-dfa69f1231ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390022756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.390022756
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.1052923722
Short name T52
Test name
Test status
Simulation time 85969956902 ps
CPU time 125.81 seconds
Started Aug 03 04:25:10 PM PDT 24
Finished Aug 03 04:27:16 PM PDT 24
Peak memory 183336 kb
Host smart-48c75f18-bcc5-4db6-ba8d-fa00da6526bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052923722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.1052923722
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.511043635
Short name T456
Test name
Test status
Simulation time 154258390768 ps
CPU time 1340.26 seconds
Started Aug 03 04:25:32 PM PDT 24
Finished Aug 03 04:47:52 PM PDT 24
Peak memory 214076 kb
Host smart-d0efe471-bd6e-425d-b22e-820f5c3e2aba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511043635 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all_with_rand_reset.511043635
Directory /workspace/18.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.rv_timer_random.3524931101
Short name T297
Test name
Test status
Simulation time 36168718785 ps
CPU time 55.02 seconds
Started Aug 03 04:25:51 PM PDT 24
Finished Aug 03 04:26:46 PM PDT 24
Peak memory 183352 kb
Host smart-d855130d-e194-4958-b77a-cff4d4cb18e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524931101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.3524931101
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.2980205621
Short name T181
Test name
Test status
Simulation time 637508816926 ps
CPU time 405.45 seconds
Started Aug 03 04:25:50 PM PDT 24
Finished Aug 03 04:32:36 PM PDT 24
Peak memory 191468 kb
Host smart-42d17be8-d2b6-4007-9524-f08dc1c96840
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980205621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.2980205621
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.1253807185
Short name T300
Test name
Test status
Simulation time 858939824204 ps
CPU time 652.62 seconds
Started Aug 03 04:25:44 PM PDT 24
Finished Aug 03 04:36:37 PM PDT 24
Peak memory 191404 kb
Host smart-efd20179-fef6-4221-8760-992a369021fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253807185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.1253807185
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.986210636
Short name T319
Test name
Test status
Simulation time 50796830427 ps
CPU time 308.88 seconds
Started Aug 03 04:25:52 PM PDT 24
Finished Aug 03 04:31:01 PM PDT 24
Peak memory 191480 kb
Host smart-aba488d9-337a-4c87-a464-837dd5cca401
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986210636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.986210636
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.1274945382
Short name T377
Test name
Test status
Simulation time 589291114917 ps
CPU time 228.47 seconds
Started Aug 03 04:25:01 PM PDT 24
Finished Aug 03 04:28:50 PM PDT 24
Peak memory 183264 kb
Host smart-0c27e054-a714-46d1-97a9-1f3286c950bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274945382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.1274945382
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.82717146
Short name T299
Test name
Test status
Simulation time 3900553222 ps
CPU time 140.24 seconds
Started Aug 03 04:25:16 PM PDT 24
Finished Aug 03 04:27:36 PM PDT 24
Peak memory 182976 kb
Host smart-ab6495fd-3912-41a4-b0dc-6977bb91eb63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82717146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.82717146
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.290253955
Short name T327
Test name
Test status
Simulation time 56771894924 ps
CPU time 90.73 seconds
Started Aug 03 04:25:05 PM PDT 24
Finished Aug 03 04:26:36 PM PDT 24
Peak memory 191528 kb
Host smart-e311c581-54be-4ebd-9428-f51984708c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290253955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.290253955
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.1994745996
Short name T298
Test name
Test status
Simulation time 637721161888 ps
CPU time 865.79 seconds
Started Aug 03 04:25:15 PM PDT 24
Finished Aug 03 04:39:41 PM PDT 24
Peak memory 191552 kb
Host smart-057f3a97-2705-4d1c-947d-a1111ed0bc40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994745996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.1994745996
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/190.rv_timer_random.1345065605
Short name T203
Test name
Test status
Simulation time 83996026254 ps
CPU time 442.75 seconds
Started Aug 03 04:25:49 PM PDT 24
Finished Aug 03 04:33:12 PM PDT 24
Peak memory 191404 kb
Host smart-682e51ad-4ec3-4334-8df8-8635f8656941
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345065605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.1345065605
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.1057399609
Short name T293
Test name
Test status
Simulation time 7535586477 ps
CPU time 11.28 seconds
Started Aug 03 04:25:55 PM PDT 24
Finished Aug 03 04:26:07 PM PDT 24
Peak memory 183300 kb
Host smart-1337014a-33f1-4284-a8e0-d4051c370eee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057399609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.1057399609
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.128353607
Short name T360
Test name
Test status
Simulation time 95372090917 ps
CPU time 608.05 seconds
Started Aug 03 04:25:47 PM PDT 24
Finished Aug 03 04:35:55 PM PDT 24
Peak memory 191192 kb
Host smart-9755ea9f-f6ab-4917-9025-564ed397de00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128353607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.128353607
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.3543050242
Short name T250
Test name
Test status
Simulation time 164191171532 ps
CPU time 549.99 seconds
Started Aug 03 04:25:47 PM PDT 24
Finished Aug 03 04:34:57 PM PDT 24
Peak memory 191396 kb
Host smart-dce8a1be-674f-4b30-a3d7-e0a4352e7060
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543050242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.3543050242
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.4039628661
Short name T263
Test name
Test status
Simulation time 76882383526 ps
CPU time 247.3 seconds
Started Aug 03 04:25:46 PM PDT 24
Finished Aug 03 04:29:54 PM PDT 24
Peak memory 191500 kb
Host smart-93ac017a-dd01-486b-90d0-33fbfd1a61a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039628661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.4039628661
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.4241729846
Short name T159
Test name
Test status
Simulation time 106053556645 ps
CPU time 249.69 seconds
Started Aug 03 04:25:47 PM PDT 24
Finished Aug 03 04:29:56 PM PDT 24
Peak memory 191436 kb
Host smart-26b64d3d-3715-406e-a838-87c25337c346
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241729846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.4241729846
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.2053540032
Short name T200
Test name
Test status
Simulation time 67144613453 ps
CPU time 101.27 seconds
Started Aug 03 04:26:02 PM PDT 24
Finished Aug 03 04:27:44 PM PDT 24
Peak memory 194776 kb
Host smart-ffec2cdb-d338-4c78-a723-c8ad67535901
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053540032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.2053540032
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.3588187181
Short name T242
Test name
Test status
Simulation time 147647681707 ps
CPU time 603.61 seconds
Started Aug 03 04:25:54 PM PDT 24
Finished Aug 03 04:35:57 PM PDT 24
Peak memory 191456 kb
Host smart-6e5a4a1a-351b-460e-a9bb-133526365e78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588187181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.3588187181
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.847262651
Short name T303
Test name
Test status
Simulation time 50197595560 ps
CPU time 45 seconds
Started Aug 03 04:25:02 PM PDT 24
Finished Aug 03 04:25:48 PM PDT 24
Peak memory 183268 kb
Host smart-d936aa6c-5525-4300-bf4a-d8b291dbf6c2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847262651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.rv_timer_cfg_update_on_fly.847262651
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.1610336814
Short name T376
Test name
Test status
Simulation time 368478657544 ps
CPU time 152.97 seconds
Started Aug 03 04:25:16 PM PDT 24
Finished Aug 03 04:27:49 PM PDT 24
Peak memory 183400 kb
Host smart-5c70ce85-0b57-4743-b591-6a9a1eddf7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610336814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.1610336814
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.3521231472
Short name T346
Test name
Test status
Simulation time 92090064800 ps
CPU time 165.5 seconds
Started Aug 03 04:24:45 PM PDT 24
Finished Aug 03 04:27:31 PM PDT 24
Peak memory 191448 kb
Host smart-2af249e6-055a-4136-9fb3-b30284df9969
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521231472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.3521231472
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.372271732
Short name T370
Test name
Test status
Simulation time 4086622008 ps
CPU time 42.02 seconds
Started Aug 03 04:24:58 PM PDT 24
Finished Aug 03 04:25:40 PM PDT 24
Peak memory 191468 kb
Host smart-5af4ff84-0f25-4a5d-a9a0-290465dc9615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372271732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.372271732
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.3775700864
Short name T5
Test name
Test status
Simulation time 141562029 ps
CPU time 0.73 seconds
Started Aug 03 04:24:56 PM PDT 24
Finished Aug 03 04:24:56 PM PDT 24
Peak memory 213888 kb
Host smart-177724c1-1253-4446-9ce8-96db623654af
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775700864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.3775700864
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.3113654262
Short name T394
Test name
Test status
Simulation time 4941268988598 ps
CPU time 657.97 seconds
Started Aug 03 04:25:03 PM PDT 24
Finished Aug 03 04:36:02 PM PDT 24
Peak memory 191344 kb
Host smart-a670efac-3f1a-48a0-9bf3-40fed20c0d56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113654262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
3113654262
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all_with_rand_reset.629901593
Short name T44
Test name
Test status
Simulation time 7851687710 ps
CPU time 58.23 seconds
Started Aug 03 04:25:09 PM PDT 24
Finished Aug 03 04:26:08 PM PDT 24
Peak memory 198020 kb
Host smart-2c2f4b2c-427f-4d9e-ac25-e27a9f3134d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629901593 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all_with_rand_reset.629901593
Directory /workspace/2.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.2196944624
Short name T51
Test name
Test status
Simulation time 209754848688 ps
CPU time 336.58 seconds
Started Aug 03 04:25:24 PM PDT 24
Finished Aug 03 04:31:01 PM PDT 24
Peak memory 182940 kb
Host smart-ece4ad21-9e37-4ecb-8bfc-1b4fffcc932e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196944624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.2196944624
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.4076959604
Short name T391
Test name
Test status
Simulation time 32267214380 ps
CPU time 48.75 seconds
Started Aug 03 04:25:18 PM PDT 24
Finished Aug 03 04:26:07 PM PDT 24
Peak memory 183260 kb
Host smart-60dc8ff9-ffd8-4eef-a8f3-a7c5eda0a6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076959604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.4076959604
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.151124155
Short name T129
Test name
Test status
Simulation time 226345053387 ps
CPU time 1931.78 seconds
Started Aug 03 04:25:00 PM PDT 24
Finished Aug 03 04:57:12 PM PDT 24
Peak memory 191484 kb
Host smart-ea6d53b6-3b00-4b27-aecb-b238f3cef5f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151124155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.151124155
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.2265879170
Short name T380
Test name
Test status
Simulation time 181707583 ps
CPU time 0.64 seconds
Started Aug 03 04:25:23 PM PDT 24
Finished Aug 03 04:25:23 PM PDT 24
Peak memory 183104 kb
Host smart-ece9a9fa-23f7-4797-8426-029b6693d295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265879170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.2265879170
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.2023432886
Short name T176
Test name
Test status
Simulation time 857341014304 ps
CPU time 416.8 seconds
Started Aug 03 04:25:49 PM PDT 24
Finished Aug 03 04:32:46 PM PDT 24
Peak memory 183276 kb
Host smart-b3a38591-b9e7-4857-a6f3-4ad9da91ee33
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023432886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.2023432886
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.3768324912
Short name T90
Test name
Test status
Simulation time 415238595228 ps
CPU time 297.69 seconds
Started Aug 03 04:25:29 PM PDT 24
Finished Aug 03 04:30:27 PM PDT 24
Peak memory 183332 kb
Host smart-7b19d4df-99d5-40fc-9559-fb17e0d643bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768324912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.3768324912
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.1847786349
Short name T431
Test name
Test status
Simulation time 131748578134 ps
CPU time 84.99 seconds
Started Aug 03 04:25:13 PM PDT 24
Finished Aug 03 04:26:38 PM PDT 24
Peak memory 183236 kb
Host smart-7582807a-2123-4e15-b081-bce4c54e5e58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847786349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.1847786349
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.1610861216
Short name T384
Test name
Test status
Simulation time 462150856 ps
CPU time 1.63 seconds
Started Aug 03 04:25:09 PM PDT 24
Finished Aug 03 04:25:11 PM PDT 24
Peak memory 191444 kb
Host smart-a51ab3f8-e752-4057-ada2-e5d72d2a76d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610861216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.1610861216
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.4009516250
Short name T291
Test name
Test status
Simulation time 607541176016 ps
CPU time 258.01 seconds
Started Aug 03 04:25:46 PM PDT 24
Finished Aug 03 04:30:05 PM PDT 24
Peak memory 191548 kb
Host smart-2e1957c7-efe1-4c83-b846-7b20fa5648be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009516250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.4009516250
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.1796376143
Short name T118
Test name
Test status
Simulation time 33850331435 ps
CPU time 52.74 seconds
Started Aug 03 04:25:21 PM PDT 24
Finished Aug 03 04:26:14 PM PDT 24
Peak memory 183308 kb
Host smart-1ad77892-dd65-4f9a-9612-718ffd16c2f8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796376143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.1796376143
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_random.1073673441
Short name T1
Test name
Test status
Simulation time 91626345784 ps
CPU time 276.96 seconds
Started Aug 03 04:25:20 PM PDT 24
Finished Aug 03 04:29:57 PM PDT 24
Peak memory 195132 kb
Host smart-3410acae-bc0b-411a-8148-498f4bd39b78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073673441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.1073673441
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.220707167
Short name T395
Test name
Test status
Simulation time 1162055369 ps
CPU time 0.65 seconds
Started Aug 03 04:25:29 PM PDT 24
Finished Aug 03 04:25:30 PM PDT 24
Peak memory 182988 kb
Host smart-a6f72985-bd7a-44a3-ba53-abc911865175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220707167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.220707167
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.1564881927
Short name T404
Test name
Test status
Simulation time 20155955311 ps
CPU time 34.96 seconds
Started Aug 03 04:25:13 PM PDT 24
Finished Aug 03 04:25:49 PM PDT 24
Peak memory 182400 kb
Host smart-fbff1677-615b-4bf9-8045-fd7eb9573d09
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564881927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.1564881927
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.3189249072
Short name T385
Test name
Test status
Simulation time 231420793661 ps
CPU time 47.21 seconds
Started Aug 03 04:25:14 PM PDT 24
Finished Aug 03 04:26:06 PM PDT 24
Peak memory 182952 kb
Host smart-626af603-68d6-4099-a141-0b1a967ae402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189249072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.3189249072
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.1278781409
Short name T425
Test name
Test status
Simulation time 204906051358 ps
CPU time 259.59 seconds
Started Aug 03 04:25:14 PM PDT 24
Finished Aug 03 04:29:34 PM PDT 24
Peak memory 191464 kb
Host smart-225e892a-71c4-4364-a28d-bf212d47ed29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278781409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.1278781409
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.2071516940
Short name T369
Test name
Test status
Simulation time 653423140 ps
CPU time 1.4 seconds
Started Aug 03 04:25:14 PM PDT 24
Finished Aug 03 04:25:15 PM PDT 24
Peak memory 191384 kb
Host smart-4895087e-a919-420a-a39d-1377534ba0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071516940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.2071516940
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.2054470539
Short name T390
Test name
Test status
Simulation time 93307234 ps
CPU time 0.58 seconds
Started Aug 03 04:25:17 PM PDT 24
Finished Aug 03 04:25:17 PM PDT 24
Peak memory 182500 kb
Host smart-9f6392ec-4e23-4c45-a4b5-393d9bdcb509
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054470539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.2054470539
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.1470792238
Short name T296
Test name
Test status
Simulation time 163989094356 ps
CPU time 238.14 seconds
Started Aug 03 04:25:23 PM PDT 24
Finished Aug 03 04:29:22 PM PDT 24
Peak memory 183268 kb
Host smart-e1ac2140-8504-4e09-99c1-eef3d3020062
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470792238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.1470792238
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.76635941
Short name T375
Test name
Test status
Simulation time 407677652703 ps
CPU time 159.55 seconds
Started Aug 03 04:25:28 PM PDT 24
Finished Aug 03 04:28:08 PM PDT 24
Peak memory 183312 kb
Host smart-27cd58ea-e6c2-4a70-9748-7a60716892a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76635941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.76635941
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.4121838920
Short name T75
Test name
Test status
Simulation time 403051319654 ps
CPU time 212.46 seconds
Started Aug 03 04:25:19 PM PDT 24
Finished Aug 03 04:28:52 PM PDT 24
Peak memory 191172 kb
Host smart-6b669006-10af-4d75-b0ce-203f110da73d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121838920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.4121838920
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.3062166181
Short name T332
Test name
Test status
Simulation time 497930101226 ps
CPU time 109.82 seconds
Started Aug 03 04:25:14 PM PDT 24
Finished Aug 03 04:27:04 PM PDT 24
Peak memory 194344 kb
Host smart-7550c3e5-c62d-4bf3-b509-59ea1cbb54c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062166181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.3062166181
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.3517931962
Short name T414
Test name
Test status
Simulation time 168132116779 ps
CPU time 120.16 seconds
Started Aug 03 04:25:38 PM PDT 24
Finished Aug 03 04:27:38 PM PDT 24
Peak memory 194184 kb
Host smart-1fb78e0d-5387-4c18-a07e-03da0d6838f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517931962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.3517931962
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.1746820625
Short name T362
Test name
Test status
Simulation time 51458090098 ps
CPU time 24.6 seconds
Started Aug 03 04:25:44 PM PDT 24
Finished Aug 03 04:26:09 PM PDT 24
Peak memory 183260 kb
Host smart-d02ac336-763f-47fc-9a23-aa9a7372b00c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746820625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.1746820625
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.3725923461
Short name T413
Test name
Test status
Simulation time 66208620767 ps
CPU time 50.33 seconds
Started Aug 03 04:25:33 PM PDT 24
Finished Aug 03 04:26:29 PM PDT 24
Peak memory 183240 kb
Host smart-71079210-2db7-429c-ac27-90c022c13183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725923461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.3725923461
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.2393012356
Short name T218
Test name
Test status
Simulation time 235852672441 ps
CPU time 195.51 seconds
Started Aug 03 04:26:23 PM PDT 24
Finished Aug 03 04:29:39 PM PDT 24
Peak memory 193400 kb
Host smart-881c9aab-3332-4409-8641-3907f6c90897
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393012356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.2393012356
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.3850140670
Short name T165
Test name
Test status
Simulation time 177927294876 ps
CPU time 460.7 seconds
Started Aug 03 04:25:17 PM PDT 24
Finished Aug 03 04:33:02 PM PDT 24
Peak memory 194760 kb
Host smart-0bb3a429-86ea-4766-84a3-1c86c2a0cd75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850140670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.3850140670
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all_with_rand_reset.3394302776
Short name T32
Test name
Test status
Simulation time 47211368071 ps
CPU time 166.17 seconds
Started Aug 03 04:25:23 PM PDT 24
Finished Aug 03 04:28:10 PM PDT 24
Peak memory 206196 kb
Host smart-16662754-c3b0-4865-9eee-48492dca2fec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394302776 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all_with_rand_reset.3394302776
Directory /workspace/25.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.262352297
Short name T267
Test name
Test status
Simulation time 235095735894 ps
CPU time 371.54 seconds
Started Aug 03 04:25:41 PM PDT 24
Finished Aug 03 04:31:53 PM PDT 24
Peak memory 182976 kb
Host smart-5c318fcf-4da5-4ab8-ba34-716618ec6c7f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262352297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.rv_timer_cfg_update_on_fly.262352297
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.3992099409
Short name T88
Test name
Test status
Simulation time 21716080879 ps
CPU time 28.33 seconds
Started Aug 03 04:25:20 PM PDT 24
Finished Aug 03 04:25:48 PM PDT 24
Peak memory 183348 kb
Host smart-fe486266-99d9-4386-853f-b2a659b7a7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992099409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.3992099409
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.3863632254
Short name T191
Test name
Test status
Simulation time 54938087796 ps
CPU time 595.62 seconds
Started Aug 03 04:25:15 PM PDT 24
Finished Aug 03 04:35:10 PM PDT 24
Peak memory 191484 kb
Host smart-4f58b384-d049-44c6-84e0-e14d77b93d93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863632254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.3863632254
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.1491557189
Short name T89
Test name
Test status
Simulation time 107316412482 ps
CPU time 56.38 seconds
Started Aug 03 04:25:20 PM PDT 24
Finished Aug 03 04:26:16 PM PDT 24
Peak memory 191176 kb
Host smart-dfa45405-bb3e-4c3d-ba1b-af98cb4278f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491557189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.1491557189
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.2167394431
Short name T314
Test name
Test status
Simulation time 49406681283 ps
CPU time 74.8 seconds
Started Aug 03 04:25:13 PM PDT 24
Finished Aug 03 04:26:28 PM PDT 24
Peak memory 182972 kb
Host smart-823039a1-3361-4cd4-b4c9-4a4f38cdb568
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167394431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.2167394431
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.1081057386
Short name T180
Test name
Test status
Simulation time 903338118768 ps
CPU time 187.24 seconds
Started Aug 03 04:25:29 PM PDT 24
Finished Aug 03 04:28:37 PM PDT 24
Peak memory 183264 kb
Host smart-aaed4610-fbf7-46b4-86be-66161bb7f312
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081057386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.1081057386
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.3407471228
Short name T435
Test name
Test status
Simulation time 94789443323 ps
CPU time 68.19 seconds
Started Aug 03 04:25:39 PM PDT 24
Finished Aug 03 04:26:47 PM PDT 24
Peak memory 183324 kb
Host smart-94035e2b-7269-4140-9e42-131c5d1f828e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407471228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.3407471228
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.2006740091
Short name T423
Test name
Test status
Simulation time 49552769930 ps
CPU time 624.36 seconds
Started Aug 03 04:25:13 PM PDT 24
Finished Aug 03 04:35:38 PM PDT 24
Peak memory 191600 kb
Host smart-549433f0-2999-4c18-9023-b9fe35ded36f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006740091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.2006740091
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.697501974
Short name T140
Test name
Test status
Simulation time 39605192692 ps
CPU time 18.11 seconds
Started Aug 03 04:25:15 PM PDT 24
Finished Aug 03 04:25:34 PM PDT 24
Peak memory 195032 kb
Host smart-fbef8177-3f76-47ef-a5e1-a4c73a4f1128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697501974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.697501974
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.1158195694
Short name T220
Test name
Test status
Simulation time 359616049861 ps
CPU time 505.94 seconds
Started Aug 03 04:25:11 PM PDT 24
Finished Aug 03 04:33:37 PM PDT 24
Peak memory 195956 kb
Host smart-700ce792-41a0-465c-9dde-ca665d826f2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158195694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.1158195694
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.4245972820
Short name T366
Test name
Test status
Simulation time 5414848227337 ps
CPU time 2131.67 seconds
Started Aug 03 04:25:19 PM PDT 24
Finished Aug 03 05:00:51 PM PDT 24
Peak memory 183300 kb
Host smart-3d58eda6-660b-47f3-b36f-42a96d4dc4c6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245972820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.4245972820
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.1634390724
Short name T418
Test name
Test status
Simulation time 160112491897 ps
CPU time 70.92 seconds
Started Aug 03 04:25:30 PM PDT 24
Finished Aug 03 04:26:41 PM PDT 24
Peak memory 183272 kb
Host smart-cc6c7b5b-35bc-4cfd-ad21-9a22865891ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634390724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.1634390724
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.2535871847
Short name T264
Test name
Test status
Simulation time 138292333172 ps
CPU time 533.48 seconds
Started Aug 03 04:25:44 PM PDT 24
Finished Aug 03 04:34:38 PM PDT 24
Peak memory 192804 kb
Host smart-87416d8d-6f80-4f3c-bf66-3567dbdfcb26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535871847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.2535871847
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.1692212157
Short name T442
Test name
Test status
Simulation time 45389266004 ps
CPU time 1192.07 seconds
Started Aug 03 04:25:19 PM PDT 24
Finished Aug 03 04:45:12 PM PDT 24
Peak memory 191176 kb
Host smart-ce32c2d8-9141-4468-8093-36bbfb092593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692212157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.1692212157
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.2577892805
Short name T292
Test name
Test status
Simulation time 201347582634 ps
CPU time 354.38 seconds
Started Aug 03 04:25:33 PM PDT 24
Finished Aug 03 04:31:27 PM PDT 24
Peak memory 183264 kb
Host smart-af12ce2c-5b9c-45d6-934a-3d4c131e70c7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577892805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.2577892805
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.4155300031
Short name T41
Test name
Test status
Simulation time 83589109661 ps
CPU time 120.48 seconds
Started Aug 03 04:25:14 PM PDT 24
Finished Aug 03 04:27:15 PM PDT 24
Peak memory 183292 kb
Host smart-420f8a18-dab0-46ff-8f6f-14afd1a0ad0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155300031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.4155300031
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.2511861423
Short name T127
Test name
Test status
Simulation time 110966626217 ps
CPU time 164.23 seconds
Started Aug 03 04:25:28 PM PDT 24
Finished Aug 03 04:28:12 PM PDT 24
Peak memory 191464 kb
Host smart-d4e7d5c3-85d9-453e-84be-1d5bb5f4f792
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511861423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.2511861423
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all_with_rand_reset.3209899990
Short name T14
Test name
Test status
Simulation time 56160366338 ps
CPU time 307.11 seconds
Started Aug 03 04:25:48 PM PDT 24
Finished Aug 03 04:30:56 PM PDT 24
Peak memory 206204 kb
Host smart-416819f3-36ef-423a-a4b8-29eb90f13a0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209899990 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all_with_rand_reset.3209899990
Directory /workspace/29.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.2585601316
Short name T355
Test name
Test status
Simulation time 244246240189 ps
CPU time 196.45 seconds
Started Aug 03 04:25:14 PM PDT 24
Finished Aug 03 04:28:30 PM PDT 24
Peak memory 183292 kb
Host smart-1aba9a3d-7a23-43c1-9c24-3bf183c4ff81
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585601316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.2585601316
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.2588408763
Short name T381
Test name
Test status
Simulation time 73390054615 ps
CPU time 52.82 seconds
Started Aug 03 04:25:03 PM PDT 24
Finished Aug 03 04:25:56 PM PDT 24
Peak memory 183256 kb
Host smart-da77ce1b-6a9a-416a-b153-c5b80536e13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588408763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.2588408763
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.1694468085
Short name T150
Test name
Test status
Simulation time 30025506585 ps
CPU time 48.29 seconds
Started Aug 03 04:25:05 PM PDT 24
Finished Aug 03 04:25:53 PM PDT 24
Peak memory 183104 kb
Host smart-11defe83-881c-43f7-b99d-753645cc7b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694468085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.1694468085
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.1433181851
Short name T16
Test name
Test status
Simulation time 380162851 ps
CPU time 0.82 seconds
Started Aug 03 04:25:07 PM PDT 24
Finished Aug 03 04:25:08 PM PDT 24
Peak memory 213828 kb
Host smart-909a33cf-24b4-42bd-84fc-e592a2156adb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433181851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.1433181851
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.145934798
Short name T142
Test name
Test status
Simulation time 88044137461 ps
CPU time 25.75 seconds
Started Aug 03 04:25:25 PM PDT 24
Finished Aug 03 04:25:51 PM PDT 24
Peak memory 183300 kb
Host smart-b471b393-4589-48e0-8c7a-8984bce38b5b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145934798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.rv_timer_cfg_update_on_fly.145934798
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.363605478
Short name T439
Test name
Test status
Simulation time 327950225701 ps
CPU time 211.76 seconds
Started Aug 03 04:25:26 PM PDT 24
Finished Aug 03 04:28:58 PM PDT 24
Peak memory 183364 kb
Host smart-ea279077-92d9-4ef0-a95c-526c6806b8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363605478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.363605478
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.3426262359
Short name T434
Test name
Test status
Simulation time 1175771981866 ps
CPU time 1166.06 seconds
Started Aug 03 04:25:33 PM PDT 24
Finished Aug 03 04:44:59 PM PDT 24
Peak memory 191492 kb
Host smart-d0af8e97-3a03-4884-b58f-1f6d6de1e007
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426262359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.3426262359
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.650096352
Short name T119
Test name
Test status
Simulation time 1687996127774 ps
CPU time 610.29 seconds
Started Aug 03 04:26:55 PM PDT 24
Finished Aug 03 04:37:06 PM PDT 24
Peak memory 191172 kb
Host smart-d455cb60-deec-4e2e-a2d8-7be5eac1889f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650096352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all.
650096352
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all_with_rand_reset.3321132366
Short name T45
Test name
Test status
Simulation time 81548269622 ps
CPU time 535.77 seconds
Started Aug 03 04:26:23 PM PDT 24
Finished Aug 03 04:35:19 PM PDT 24
Peak memory 205844 kb
Host smart-4b59e0f9-402b-4502-9c3a-97dbccfa6fac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321132366 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all_with_rand_reset.3321132366
Directory /workspace/30.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.2052822331
Short name T42
Test name
Test status
Simulation time 1184550663947 ps
CPU time 836.28 seconds
Started Aug 03 04:25:29 PM PDT 24
Finished Aug 03 04:39:25 PM PDT 24
Peak memory 183244 kb
Host smart-c2a69a15-1b65-4b52-a0da-f0662ba48312
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052822331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.2052822331
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.3999297789
Short name T383
Test name
Test status
Simulation time 326095471884 ps
CPU time 115.16 seconds
Started Aug 03 04:25:40 PM PDT 24
Finished Aug 03 04:27:35 PM PDT 24
Peak memory 183404 kb
Host smart-ea78711e-df6d-4cdb-99c2-3ec36a3824cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999297789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.3999297789
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.846574352
Short name T317
Test name
Test status
Simulation time 159471249560 ps
CPU time 83.14 seconds
Started Aug 03 04:25:38 PM PDT 24
Finished Aug 03 04:27:01 PM PDT 24
Peak memory 183332 kb
Host smart-6cb39d08-6fd3-4b87-a7c6-e14c5e8f1106
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846574352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.846574352
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.1928482954
Short name T323
Test name
Test status
Simulation time 27902543570 ps
CPU time 11.03 seconds
Started Aug 03 04:25:14 PM PDT 24
Finished Aug 03 04:25:25 PM PDT 24
Peak memory 182384 kb
Host smart-7f1d1ff5-0ce0-47ba-869f-faa372ceaa2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928482954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.1928482954
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.2778875006
Short name T83
Test name
Test status
Simulation time 790223535423 ps
CPU time 936.2 seconds
Started Aug 03 04:25:23 PM PDT 24
Finished Aug 03 04:41:00 PM PDT 24
Peak memory 191496 kb
Host smart-d36d1072-0cc8-4c3a-957a-db97d1565d04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778875006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.2778875006
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.961104740
Short name T211
Test name
Test status
Simulation time 13442931312 ps
CPU time 11.96 seconds
Started Aug 03 04:25:26 PM PDT 24
Finished Aug 03 04:25:38 PM PDT 24
Peak memory 183288 kb
Host smart-d4bbcfd9-9ff7-4db8-a5c0-5bbac68c46a3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961104740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.rv_timer_cfg_update_on_fly.961104740
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.3499994925
Short name T438
Test name
Test status
Simulation time 205004349737 ps
CPU time 29.08 seconds
Started Aug 03 04:26:03 PM PDT 24
Finished Aug 03 04:26:32 PM PDT 24
Peak memory 183268 kb
Host smart-aff384ec-48bd-41fd-9426-3d2d8efb612a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499994925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.3499994925
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.1847163008
Short name T290
Test name
Test status
Simulation time 26426089317 ps
CPU time 42.82 seconds
Started Aug 03 04:25:36 PM PDT 24
Finished Aug 03 04:26:19 PM PDT 24
Peak memory 182992 kb
Host smart-b1e32e88-8698-4934-b5e5-95c979e64ce3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847163008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.1847163008
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.997663126
Short name T230
Test name
Test status
Simulation time 240564352117 ps
CPU time 760.56 seconds
Started Aug 03 04:25:27 PM PDT 24
Finished Aug 03 04:38:08 PM PDT 24
Peak memory 191496 kb
Host smart-4112ef0b-67a1-4096-a076-2ef752446a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997663126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.997663126
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.1789218276
Short name T74
Test name
Test status
Simulation time 143341149828 ps
CPU time 43.09 seconds
Started Aug 03 04:25:16 PM PDT 24
Finished Aug 03 04:25:59 PM PDT 24
Peak memory 183292 kb
Host smart-b1011809-a4b4-45c5-a779-e5626bcd6294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789218276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.1789218276
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.1706756546
Short name T85
Test name
Test status
Simulation time 719796899562 ps
CPU time 241.36 seconds
Started Aug 03 04:25:50 PM PDT 24
Finished Aug 03 04:29:51 PM PDT 24
Peak memory 191496 kb
Host smart-fa5ed6a5-6468-46fe-b265-7680854804a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706756546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.1706756546
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.3021714750
Short name T449
Test name
Test status
Simulation time 26960364972 ps
CPU time 22.98 seconds
Started Aug 03 04:25:48 PM PDT 24
Finished Aug 03 04:26:12 PM PDT 24
Peak memory 183296 kb
Host smart-9e2d3b89-24b2-47e6-9093-87cf332f9f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021714750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.3021714750
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.1999520741
Short name T388
Test name
Test status
Simulation time 21219868 ps
CPU time 0.54 seconds
Started Aug 03 04:25:46 PM PDT 24
Finished Aug 03 04:25:47 PM PDT 24
Peak memory 183168 kb
Host smart-1f01d2d9-7035-4102-a180-833fac0a50da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999520741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.1999520741
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all_with_rand_reset.2421615939
Short name T28
Test name
Test status
Simulation time 44274447133 ps
CPU time 325.43 seconds
Started Aug 03 04:25:17 PM PDT 24
Finished Aug 03 04:30:43 PM PDT 24
Peak memory 197924 kb
Host smart-31163bce-aa29-4026-abc1-5dcaa4412fa6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421615939 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all_with_rand_reset.2421615939
Directory /workspace/33.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.1923503698
Short name T457
Test name
Test status
Simulation time 30775485955 ps
CPU time 7.96 seconds
Started Aug 03 04:25:15 PM PDT 24
Finished Aug 03 04:25:23 PM PDT 24
Peak memory 183288 kb
Host smart-6beee3c3-31df-4edc-b628-28f4a29db829
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923503698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.1923503698
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.3841857007
Short name T396
Test name
Test status
Simulation time 854227532 ps
CPU time 0.68 seconds
Started Aug 03 04:25:27 PM PDT 24
Finished Aug 03 04:25:27 PM PDT 24
Peak memory 182860 kb
Host smart-505f5fbd-afbb-419f-9918-7b7c4e6e6bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841857007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.3841857007
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.24466777
Short name T147
Test name
Test status
Simulation time 124272765073 ps
CPU time 386.09 seconds
Started Aug 03 04:25:57 PM PDT 24
Finished Aug 03 04:32:23 PM PDT 24
Peak memory 191488 kb
Host smart-a66a686a-e5cf-4d46-bb8b-c4e5953c1aee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24466777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.24466777
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.2397647960
Short name T37
Test name
Test status
Simulation time 172534351189 ps
CPU time 235.58 seconds
Started Aug 03 04:25:21 PM PDT 24
Finished Aug 03 04:29:17 PM PDT 24
Peak memory 195628 kb
Host smart-80cc3050-1a2f-448f-9b04-ff6c03bb7d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397647960 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.2397647960
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all_with_rand_reset.3191095195
Short name T441
Test name
Test status
Simulation time 77544592357 ps
CPU time 175.4 seconds
Started Aug 03 04:25:23 PM PDT 24
Finished Aug 03 04:28:19 PM PDT 24
Peak memory 197684 kb
Host smart-59cc2396-5991-4d5f-ba84-45a35137be70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191095195 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all_with_rand_reset.3191095195
Directory /workspace/34.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.1151387768
Short name T171
Test name
Test status
Simulation time 56573085423 ps
CPU time 97.4 seconds
Started Aug 03 04:26:00 PM PDT 24
Finished Aug 03 04:27:38 PM PDT 24
Peak memory 183296 kb
Host smart-b731c7b1-3bf4-446e-84b3-682e34e5da08
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151387768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.1151387768
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.4045108380
Short name T409
Test name
Test status
Simulation time 138336173162 ps
CPU time 88.03 seconds
Started Aug 03 04:26:24 PM PDT 24
Finished Aug 03 04:27:52 PM PDT 24
Peak memory 182928 kb
Host smart-40ea09cc-a3c8-482d-b624-a5aa318a6dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045108380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.4045108380
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.827373029
Short name T330
Test name
Test status
Simulation time 77974509487 ps
CPU time 119.39 seconds
Started Aug 03 04:25:26 PM PDT 24
Finished Aug 03 04:27:26 PM PDT 24
Peak memory 191484 kb
Host smart-5c080124-a343-4279-bb93-0b21734e50e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827373029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.827373029
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.1964584906
Short name T451
Test name
Test status
Simulation time 39129843500 ps
CPU time 16.34 seconds
Started Aug 03 04:25:30 PM PDT 24
Finished Aug 03 04:25:46 PM PDT 24
Peak memory 191536 kb
Host smart-3dfab639-3d0c-4f98-bae2-0c39d8865fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964584906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.1964584906
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.4235909191
Short name T27
Test name
Test status
Simulation time 3366691243102 ps
CPU time 496.78 seconds
Started Aug 03 04:26:47 PM PDT 24
Finished Aug 03 04:35:04 PM PDT 24
Peak memory 190592 kb
Host smart-5bfefb9b-29c9-433c-8c30-4b18b8f336e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235909191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.4235909191
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all_with_rand_reset.2184694896
Short name T33
Test name
Test status
Simulation time 132756718506 ps
CPU time 1080.32 seconds
Started Aug 03 04:25:48 PM PDT 24
Finished Aug 03 04:43:48 PM PDT 24
Peak memory 205904 kb
Host smart-9f69adc2-eb3c-4879-a187-fe40328552da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184694896 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all_with_rand_reset.2184694896
Directory /workspace/35.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.4274967266
Short name T219
Test name
Test status
Simulation time 163522702640 ps
CPU time 231.48 seconds
Started Aug 03 04:26:01 PM PDT 24
Finished Aug 03 04:29:53 PM PDT 24
Peak memory 183252 kb
Host smart-d318fdfe-f0ff-4d77-a8a9-aa5ddff3216e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274967266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.4274967266
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.1462998918
Short name T416
Test name
Test status
Simulation time 24921716487 ps
CPU time 33.14 seconds
Started Aug 03 04:25:12 PM PDT 24
Finished Aug 03 04:25:45 PM PDT 24
Peak memory 183244 kb
Host smart-a949784d-94b2-4a5d-ade2-0b11b833e3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462998918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.1462998918
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.934922303
Short name T440
Test name
Test status
Simulation time 1606625897327 ps
CPU time 1004.7 seconds
Started Aug 03 04:25:46 PM PDT 24
Finished Aug 03 04:42:31 PM PDT 24
Peak memory 191636 kb
Host smart-8fe97a48-ed5d-4c02-8c1f-b8824b8be89e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934922303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.934922303
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.1273845563
Short name T335
Test name
Test status
Simulation time 407511552389 ps
CPU time 135.12 seconds
Started Aug 03 04:25:23 PM PDT 24
Finished Aug 03 04:27:38 PM PDT 24
Peak memory 183260 kb
Host smart-7fcad18b-6fa0-483c-bdee-ea23a51b5349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273845563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.1273845563
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.3306775127
Short name T252
Test name
Test status
Simulation time 600501002384 ps
CPU time 401.82 seconds
Started Aug 03 04:25:25 PM PDT 24
Finished Aug 03 04:32:07 PM PDT 24
Peak memory 191504 kb
Host smart-4ab1d599-b67a-4c55-8f41-06036ffcc7e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306775127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.3306775127
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.1360358565
Short name T342
Test name
Test status
Simulation time 343648023487 ps
CPU time 488.37 seconds
Started Aug 03 04:25:38 PM PDT 24
Finished Aug 03 04:33:46 PM PDT 24
Peak memory 183328 kb
Host smart-863ed43f-f160-4585-a6a9-7a7d092a4604
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360358565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.1360358565
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.1506592827
Short name T452
Test name
Test status
Simulation time 437160932112 ps
CPU time 120.51 seconds
Started Aug 03 04:25:49 PM PDT 24
Finished Aug 03 04:27:50 PM PDT 24
Peak memory 183328 kb
Host smart-ba515f90-a322-4d80-b906-6f1780336474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506592827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.1506592827
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.2675523746
Short name T326
Test name
Test status
Simulation time 2863289652 ps
CPU time 5.61 seconds
Started Aug 03 04:26:23 PM PDT 24
Finished Aug 03 04:26:29 PM PDT 24
Peak memory 182940 kb
Host smart-5a5530d2-cd8e-47dd-8c39-860187a53d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675523746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.2675523746
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.2053019340
Short name T166
Test name
Test status
Simulation time 453506197917 ps
CPU time 237.99 seconds
Started Aug 03 04:25:11 PM PDT 24
Finished Aug 03 04:29:09 PM PDT 24
Peak memory 191468 kb
Host smart-949881ab-0afd-4d2a-b244-bdea9ebf249c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053019340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.2053019340
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.3949919993
Short name T55
Test name
Test status
Simulation time 100675982522 ps
CPU time 159.82 seconds
Started Aug 03 04:25:52 PM PDT 24
Finished Aug 03 04:28:32 PM PDT 24
Peak memory 183348 kb
Host smart-a333735d-2d87-40bd-8948-9c8844bd0591
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949919993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.3949919993
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.1015292544
Short name T453
Test name
Test status
Simulation time 184219585915 ps
CPU time 126.01 seconds
Started Aug 03 04:25:19 PM PDT 24
Finished Aug 03 04:27:25 PM PDT 24
Peak memory 183436 kb
Host smart-9b922e3c-0256-4669-9ec7-46daa8e0838f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015292544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.1015292544
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.1421293556
Short name T324
Test name
Test status
Simulation time 86782428085 ps
CPU time 131.16 seconds
Started Aug 03 04:25:34 PM PDT 24
Finished Aug 03 04:27:46 PM PDT 24
Peak memory 191460 kb
Host smart-c991942c-7c97-4919-a0be-3787aaafdba3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421293556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.1421293556
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.4046428166
Short name T411
Test name
Test status
Simulation time 327943045 ps
CPU time 0.89 seconds
Started Aug 03 04:25:34 PM PDT 24
Finished Aug 03 04:25:35 PM PDT 24
Peak memory 183000 kb
Host smart-5b8a3a53-17aa-4747-8922-f413743e7cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046428166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.4046428166
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.3969143665
Short name T173
Test name
Test status
Simulation time 1482761639031 ps
CPU time 613.9 seconds
Started Aug 03 04:25:42 PM PDT 24
Finished Aug 03 04:35:56 PM PDT 24
Peak memory 196096 kb
Host smart-776856f3-8e6d-46c9-9a0e-44274f112d2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969143665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.3969143665
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all_with_rand_reset.1456386821
Short name T30
Test name
Test status
Simulation time 41594139474 ps
CPU time 391.18 seconds
Started Aug 03 04:25:16 PM PDT 24
Finished Aug 03 04:31:48 PM PDT 24
Peak memory 206156 kb
Host smart-c7a54b29-0af7-4960-8089-cec686c1590c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456386821 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all_with_rand_reset.1456386821
Directory /workspace/38.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.3186162072
Short name T239
Test name
Test status
Simulation time 39880911967 ps
CPU time 21.1 seconds
Started Aug 03 04:25:12 PM PDT 24
Finished Aug 03 04:25:33 PM PDT 24
Peak memory 183332 kb
Host smart-62863e44-6ad9-4423-ad95-38ff3d320ef4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186162072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.3186162072
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.1860385176
Short name T417
Test name
Test status
Simulation time 342062057538 ps
CPU time 133.18 seconds
Started Aug 03 04:25:38 PM PDT 24
Finished Aug 03 04:27:51 PM PDT 24
Peak memory 183300 kb
Host smart-a9b7ac73-52fe-4469-91f5-ae6f835b9685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860385176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.1860385176
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.1847622652
Short name T357
Test name
Test status
Simulation time 131133137832 ps
CPU time 476.55 seconds
Started Aug 03 04:25:38 PM PDT 24
Finished Aug 03 04:33:35 PM PDT 24
Peak memory 191504 kb
Host smart-d999e78b-d9ae-429b-86a2-0538efd5cc4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847622652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.1847622652
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.1597356805
Short name T358
Test name
Test status
Simulation time 34073971200 ps
CPU time 20.5 seconds
Started Aug 03 04:25:59 PM PDT 24
Finished Aug 03 04:26:19 PM PDT 24
Peak memory 191472 kb
Host smart-e7f0d27f-86d1-4ccc-a646-898eccbae91f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597356805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.1597356805
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all_with_rand_reset.3825585679
Short name T46
Test name
Test status
Simulation time 91854950995 ps
CPU time 629.28 seconds
Started Aug 03 04:26:23 PM PDT 24
Finished Aug 03 04:36:53 PM PDT 24
Peak memory 205848 kb
Host smart-4ac43339-816e-48a3-ac07-61cd60a7b6fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825585679 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all_with_rand_reset.3825585679
Directory /workspace/39.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.3285048231
Short name T10
Test name
Test status
Simulation time 597297325756 ps
CPU time 322.94 seconds
Started Aug 03 04:24:45 PM PDT 24
Finished Aug 03 04:30:08 PM PDT 24
Peak memory 183304 kb
Host smart-9b45eeb5-a748-427c-853e-c098df775f89
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285048231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.3285048231
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.3487162189
Short name T400
Test name
Test status
Simulation time 390193349537 ps
CPU time 145.3 seconds
Started Aug 03 04:24:53 PM PDT 24
Finished Aug 03 04:27:18 PM PDT 24
Peak memory 183316 kb
Host smart-b3b02ce1-c8db-4e7e-acf2-6e0b0640b355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487162189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.3487162189
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.2954987526
Short name T343
Test name
Test status
Simulation time 18016838508 ps
CPU time 30.87 seconds
Started Aug 03 04:25:03 PM PDT 24
Finished Aug 03 04:25:34 PM PDT 24
Peak memory 183340 kb
Host smart-14219e31-8aff-47b3-aebd-24b080d83c22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954987526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.2954987526
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.2932663613
Short name T146
Test name
Test status
Simulation time 30432109868 ps
CPU time 37.07 seconds
Started Aug 03 04:25:10 PM PDT 24
Finished Aug 03 04:25:47 PM PDT 24
Peak memory 183000 kb
Host smart-1a05f476-16c8-42ba-9ac9-3df9ac7bca07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932663613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.2932663613
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.4165504787
Short name T19
Test name
Test status
Simulation time 94339140 ps
CPU time 0.96 seconds
Started Aug 03 04:25:13 PM PDT 24
Finished Aug 03 04:25:15 PM PDT 24
Peak memory 215080 kb
Host smart-fe25bb5a-2a11-4150-b422-1e8abc7f7543
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165504787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.4165504787
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.1126028341
Short name T65
Test name
Test status
Simulation time 364283708201 ps
CPU time 284.85 seconds
Started Aug 03 04:25:27 PM PDT 24
Finished Aug 03 04:30:12 PM PDT 24
Peak memory 191188 kb
Host smart-53d7c9eb-7a66-46dc-8554-7c7e1e0911a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126028341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
1126028341
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.2444741488
Short name T115
Test name
Test status
Simulation time 448566142118 ps
CPU time 214.74 seconds
Started Aug 03 04:25:43 PM PDT 24
Finished Aug 03 04:29:18 PM PDT 24
Peak memory 183348 kb
Host smart-0a418041-c625-428c-b662-5371903328f2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444741488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.2444741488
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.673700118
Short name T424
Test name
Test status
Simulation time 62471968858 ps
CPU time 97.84 seconds
Started Aug 03 04:26:15 PM PDT 24
Finished Aug 03 04:27:54 PM PDT 24
Peak memory 181416 kb
Host smart-b6df11eb-6513-4e11-b67a-8d92fc5407cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673700118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.673700118
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.2459302731
Short name T116
Test name
Test status
Simulation time 143565785326 ps
CPU time 93.81 seconds
Started Aug 03 04:25:26 PM PDT 24
Finished Aug 03 04:27:00 PM PDT 24
Peak memory 194696 kb
Host smart-db0b2b5d-5be9-445b-be5a-3b106c2bb9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459302731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.2459302731
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.1216108624
Short name T66
Test name
Test status
Simulation time 436583519801 ps
CPU time 582.15 seconds
Started Aug 03 04:25:39 PM PDT 24
Finished Aug 03 04:35:21 PM PDT 24
Peak memory 191492 kb
Host smart-08064f98-79c2-4b9e-b62c-aef56c83a50a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216108624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.1216108624
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.2730923780
Short name T428
Test name
Test status
Simulation time 164137153387 ps
CPU time 223.65 seconds
Started Aug 03 04:26:15 PM PDT 24
Finished Aug 03 04:30:00 PM PDT 24
Peak memory 181240 kb
Host smart-859984ee-dbaf-4155-96a3-9469aacbbd94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730923780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.2730923780
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.1929578945
Short name T419
Test name
Test status
Simulation time 317671129 ps
CPU time 0.68 seconds
Started Aug 03 04:26:24 PM PDT 24
Finished Aug 03 04:26:25 PM PDT 24
Peak memory 182672 kb
Host smart-fa550721-7f82-49c2-b3d0-374a1216f0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929578945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.1929578945
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.2615060519
Short name T436
Test name
Test status
Simulation time 1076943364471 ps
CPU time 478.59 seconds
Started Aug 03 04:25:17 PM PDT 24
Finished Aug 03 04:33:15 PM PDT 24
Peak memory 191452 kb
Host smart-4e3cc379-8188-4c9b-a641-b0a5907aa6d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615060519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.2615060519
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.1669234594
Short name T402
Test name
Test status
Simulation time 5587903565 ps
CPU time 5.89 seconds
Started Aug 03 04:25:38 PM PDT 24
Finished Aug 03 04:25:44 PM PDT 24
Peak memory 183216 kb
Host smart-f4d46662-ac7a-4c2e-bb1a-e6fbe500cf8b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669234594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.1669234594
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.2359302246
Short name T82
Test name
Test status
Simulation time 106099211426 ps
CPU time 134.73 seconds
Started Aug 03 04:25:22 PM PDT 24
Finished Aug 03 04:27:37 PM PDT 24
Peak memory 183276 kb
Host smart-eee2934c-78d7-4420-8528-777996e9ee24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359302246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.2359302246
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.2980812825
Short name T53
Test name
Test status
Simulation time 402121017408 ps
CPU time 125.98 seconds
Started Aug 03 04:25:37 PM PDT 24
Finished Aug 03 04:27:43 PM PDT 24
Peak memory 191492 kb
Host smart-fab228ba-1cd1-481d-8881-e17a7fcb6df8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980812825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.2980812825
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.2657512031
Short name T12
Test name
Test status
Simulation time 263232418458 ps
CPU time 245.94 seconds
Started Aug 03 04:25:44 PM PDT 24
Finished Aug 03 04:29:51 PM PDT 24
Peak memory 191556 kb
Host smart-70e7f38a-fb74-4e04-8eb9-b9a4750d772f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657512031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.2657512031
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.2933537939
Short name T57
Test name
Test status
Simulation time 1917144126069 ps
CPU time 848.63 seconds
Started Aug 03 04:25:24 PM PDT 24
Finished Aug 03 04:39:33 PM PDT 24
Peak memory 191468 kb
Host smart-9b69341b-572d-4ec0-87ec-4d668e67e975
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933537939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.2933537939
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.321643170
Short name T408
Test name
Test status
Simulation time 358671450509 ps
CPU time 568.5 seconds
Started Aug 03 04:25:20 PM PDT 24
Finished Aug 03 04:34:49 PM PDT 24
Peak memory 183248 kb
Host smart-dcdd3f2e-79af-499b-807f-c2d82107c5d7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321643170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.rv_timer_cfg_update_on_fly.321643170
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.3167514793
Short name T389
Test name
Test status
Simulation time 216277711312 ps
CPU time 292.52 seconds
Started Aug 03 04:25:28 PM PDT 24
Finished Aug 03 04:30:20 PM PDT 24
Peak memory 183300 kb
Host smart-1e75240a-9b54-4f56-bf94-7a1291903237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167514793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.3167514793
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.158541959
Short name T450
Test name
Test status
Simulation time 670608452 ps
CPU time 0.89 seconds
Started Aug 03 04:25:28 PM PDT 24
Finished Aug 03 04:25:29 PM PDT 24
Peak memory 192452 kb
Host smart-cd7c50bc-163d-47d3-b92f-3a9bd61eb083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158541959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.158541959
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.3714046586
Short name T309
Test name
Test status
Simulation time 148162718630 ps
CPU time 575.07 seconds
Started Aug 03 04:25:38 PM PDT 24
Finished Aug 03 04:35:13 PM PDT 24
Peak memory 191576 kb
Host smart-ce6aa57b-2be1-41cd-8024-7349605008b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714046586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.3714046586
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.2393465577
Short name T29
Test name
Test status
Simulation time 31061737180 ps
CPU time 161.75 seconds
Started Aug 03 04:25:30 PM PDT 24
Finished Aug 03 04:28:12 PM PDT 24
Peak memory 206240 kb
Host smart-3f657d50-5d29-4a2a-a2f9-5d1a00c3c80d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393465577 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.2393465577
Directory /workspace/43.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.3223235079
Short name T236
Test name
Test status
Simulation time 2845490815961 ps
CPU time 849.53 seconds
Started Aug 03 04:25:17 PM PDT 24
Finished Aug 03 04:39:27 PM PDT 24
Peak memory 183236 kb
Host smart-7cf37dd4-ef78-422a-9374-93021fc6bc00
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223235079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.3223235079
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.4216484950
Short name T39
Test name
Test status
Simulation time 382700766124 ps
CPU time 317.08 seconds
Started Aug 03 04:25:39 PM PDT 24
Finished Aug 03 04:30:56 PM PDT 24
Peak memory 183256 kb
Host smart-3e5c1a78-c260-481c-81b1-de4bbb9f77d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216484950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.4216484950
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.1967959066
Short name T341
Test name
Test status
Simulation time 20449387135 ps
CPU time 143.18 seconds
Started Aug 03 04:25:31 PM PDT 24
Finished Aug 03 04:27:54 PM PDT 24
Peak memory 183108 kb
Host smart-ff192dd8-2c2c-4abe-ac1c-085a896c6221
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967959066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.1967959066
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.2149280556
Short name T36
Test name
Test status
Simulation time 26097925153 ps
CPU time 46.48 seconds
Started Aug 03 04:25:44 PM PDT 24
Finished Aug 03 04:26:31 PM PDT 24
Peak memory 183316 kb
Host smart-1137e21d-2bd4-4547-8df4-a5d96fe45b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149280556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.2149280556
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.2983885589
Short name T43
Test name
Test status
Simulation time 21673154683 ps
CPU time 158.02 seconds
Started Aug 03 04:25:10 PM PDT 24
Finished Aug 03 04:27:48 PM PDT 24
Peak memory 198036 kb
Host smart-cb5315bc-6d55-45e8-9ef9-f0211feb1592
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983885589 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.2983885589
Directory /workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.2367623503
Short name T69
Test name
Test status
Simulation time 38160611468 ps
CPU time 28.67 seconds
Started Aug 03 04:25:15 PM PDT 24
Finished Aug 03 04:25:43 PM PDT 24
Peak memory 183288 kb
Host smart-368af763-f135-4995-bb5e-5a1c12811c0f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367623503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.2367623503
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.4159687226
Short name T378
Test name
Test status
Simulation time 614164841013 ps
CPU time 246.57 seconds
Started Aug 03 04:25:24 PM PDT 24
Finished Aug 03 04:29:31 PM PDT 24
Peak memory 183252 kb
Host smart-78e2d960-f58a-4d9d-9125-d4c522f63968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159687226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.4159687226
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.2061788398
Short name T328
Test name
Test status
Simulation time 189698497513 ps
CPU time 724.73 seconds
Started Aug 03 04:25:41 PM PDT 24
Finished Aug 03 04:37:46 PM PDT 24
Peak memory 191492 kb
Host smart-4a8f2b78-adf5-4ca5-9b0b-afd53719a89f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061788398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.2061788398
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.3814353800
Short name T347
Test name
Test status
Simulation time 211365658738 ps
CPU time 83.56 seconds
Started Aug 03 04:25:15 PM PDT 24
Finished Aug 03 04:26:38 PM PDT 24
Peak memory 191564 kb
Host smart-669c888b-fc26-4a7c-a1c0-6e45cabf9f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814353800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.3814353800
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.1270578912
Short name T34
Test name
Test status
Simulation time 18471341143 ps
CPU time 192.89 seconds
Started Aug 03 04:25:36 PM PDT 24
Finished Aug 03 04:28:49 PM PDT 24
Peak memory 198056 kb
Host smart-2f514a5c-c6a5-425e-8cc6-0e6601756463
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270578912 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all_with_rand_reset.1270578912
Directory /workspace/45.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.1129826731
Short name T182
Test name
Test status
Simulation time 150786193350 ps
CPU time 85.83 seconds
Started Aug 03 04:25:52 PM PDT 24
Finished Aug 03 04:27:18 PM PDT 24
Peak memory 183264 kb
Host smart-096c6668-cd4f-4756-abaf-5d5b5c6ff579
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129826731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.1129826731
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.1685328622
Short name T59
Test name
Test status
Simulation time 65118049777 ps
CPU time 80.18 seconds
Started Aug 03 04:25:23 PM PDT 24
Finished Aug 03 04:26:44 PM PDT 24
Peak memory 183260 kb
Host smart-2e7b3e1f-b1b0-40a0-af71-3c3571cce782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685328622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.1685328622
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.630721688
Short name T126
Test name
Test status
Simulation time 374334183701 ps
CPU time 129.04 seconds
Started Aug 03 04:25:47 PM PDT 24
Finished Aug 03 04:27:56 PM PDT 24
Peak memory 191520 kb
Host smart-915d424d-13e7-4b2d-978f-9143b61e65ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630721688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.630721688
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.1317782964
Short name T405
Test name
Test status
Simulation time 4984614666067 ps
CPU time 563.99 seconds
Started Aug 03 04:25:51 PM PDT 24
Finished Aug 03 04:35:15 PM PDT 24
Peak memory 191448 kb
Host smart-14d6bb22-44dc-49c4-b9cc-9604c3ecc7ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317782964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.1317782964
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all_with_rand_reset.695973713
Short name T260
Test name
Test status
Simulation time 245408541907 ps
CPU time 460.25 seconds
Started Aug 03 04:25:18 PM PDT 24
Finished Aug 03 04:32:58 PM PDT 24
Peak memory 206176 kb
Host smart-b57fbbb7-76bc-4570-98fa-a42bff4cbfe4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695973713 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all_with_rand_reset.695973713
Directory /workspace/46.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.1112075835
Short name T301
Test name
Test status
Simulation time 51534412704 ps
CPU time 34.24 seconds
Started Aug 03 04:25:24 PM PDT 24
Finished Aug 03 04:25:58 PM PDT 24
Peak memory 183272 kb
Host smart-d08dd906-7da9-40e4-b158-72387c6c2e46
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112075835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.1112075835
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.3828198698
Short name T386
Test name
Test status
Simulation time 28600351071 ps
CPU time 40.11 seconds
Started Aug 03 04:25:23 PM PDT 24
Finished Aug 03 04:26:04 PM PDT 24
Peak memory 182956 kb
Host smart-6b0faa1f-a8e4-480c-b0b8-998b0f1a5acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828198698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.3828198698
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.2432577653
Short name T368
Test name
Test status
Simulation time 20600149366 ps
CPU time 10.05 seconds
Started Aug 03 04:25:24 PM PDT 24
Finished Aug 03 04:25:34 PM PDT 24
Peak memory 183304 kb
Host smart-8f19adba-deb2-4c6b-ac24-72d5cb73ad0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432577653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.2432577653
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.22052983
Short name T308
Test name
Test status
Simulation time 20280937895 ps
CPU time 27.6 seconds
Started Aug 03 04:26:00 PM PDT 24
Finished Aug 03 04:26:28 PM PDT 24
Peak memory 191488 kb
Host smart-8ab0f7b0-6db3-4ee7-b10f-636557d13494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22052983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.22052983
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.2821285536
Short name T282
Test name
Test status
Simulation time 112749974484 ps
CPU time 165.58 seconds
Started Aug 03 04:25:15 PM PDT 24
Finished Aug 03 04:28:00 PM PDT 24
Peak memory 191448 kb
Host smart-42431f15-4975-43c2-b007-77a16971b34b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821285536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.2821285536
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.2439446351
Short name T256
Test name
Test status
Simulation time 2179669779816 ps
CPU time 725.27 seconds
Started Aug 03 04:25:23 PM PDT 24
Finished Aug 03 04:37:29 PM PDT 24
Peak memory 183276 kb
Host smart-236ebf77-7520-483b-b3d1-0bbbeeb1a1ae
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439446351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.2439446351
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.569425439
Short name T397
Test name
Test status
Simulation time 611668505856 ps
CPU time 232.48 seconds
Started Aug 03 04:25:38 PM PDT 24
Finished Aug 03 04:29:30 PM PDT 24
Peak memory 182996 kb
Host smart-8dc10d25-0d4b-41e0-ae17-ca87f40d7ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569425439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.569425439
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.2420610936
Short name T382
Test name
Test status
Simulation time 497219368 ps
CPU time 1.21 seconds
Started Aug 03 04:25:37 PM PDT 24
Finished Aug 03 04:25:38 PM PDT 24
Peak memory 191628 kb
Host smart-3682a1b5-ba5d-4286-a22e-17d2fc5972d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420610936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.2420610936
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.3222230503
Short name T63
Test name
Test status
Simulation time 70823833 ps
CPU time 0.6 seconds
Started Aug 03 04:25:27 PM PDT 24
Finished Aug 03 04:25:28 PM PDT 24
Peak memory 182988 kb
Host smart-c6bef97c-127a-4060-8594-770d13d21ce8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222230503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.3222230503
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.1948497661
Short name T422
Test name
Test status
Simulation time 10262321870 ps
CPU time 13.64 seconds
Started Aug 03 04:25:19 PM PDT 24
Finished Aug 03 04:25:32 PM PDT 24
Peak memory 183288 kb
Host smart-1d14efb2-8e81-400f-b419-52b99a4d9fc8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948497661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.1948497661
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.3284383621
Short name T387
Test name
Test status
Simulation time 65899310060 ps
CPU time 103.44 seconds
Started Aug 03 04:25:30 PM PDT 24
Finished Aug 03 04:27:13 PM PDT 24
Peak memory 183296 kb
Host smart-730a878f-af2e-4753-b408-ca068ee6dee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284383621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.3284383621
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.2816781143
Short name T187
Test name
Test status
Simulation time 1698720783540 ps
CPU time 488.27 seconds
Started Aug 03 04:25:25 PM PDT 24
Finished Aug 03 04:33:34 PM PDT 24
Peak memory 191488 kb
Host smart-d0833c58-79b9-4612-8bc6-dd9dc75e7c9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816781143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.2816781143
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.1399181042
Short name T71
Test name
Test status
Simulation time 147681940136 ps
CPU time 136.88 seconds
Started Aug 03 04:25:08 PM PDT 24
Finished Aug 03 04:27:25 PM PDT 24
Peak memory 183248 kb
Host smart-0840472c-b738-4f40-8993-248047b413c9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399181042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.1399181042
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.1655357698
Short name T392
Test name
Test status
Simulation time 84760106812 ps
CPU time 73.61 seconds
Started Aug 03 04:25:33 PM PDT 24
Finished Aug 03 04:26:47 PM PDT 24
Peak memory 183340 kb
Host smart-1cdbe4e0-a995-4d55-aafe-dcde7e7457d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655357698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.1655357698
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.2959040126
Short name T38
Test name
Test status
Simulation time 341570017075 ps
CPU time 2040.97 seconds
Started Aug 03 04:24:58 PM PDT 24
Finished Aug 03 04:58:59 PM PDT 24
Peak memory 191460 kb
Host smart-8b56cb3c-d514-4dbd-830e-8a4006e2dd10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959040126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.2959040126
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.1925841503
Short name T312
Test name
Test status
Simulation time 53613156255 ps
CPU time 59.8 seconds
Started Aug 03 04:24:55 PM PDT 24
Finished Aug 03 04:25:55 PM PDT 24
Peak memory 191508 kb
Host smart-5724ec16-b367-4989-996e-cff021d930a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925841503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.1925841503
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/51.rv_timer_random.2705026019
Short name T189
Test name
Test status
Simulation time 465424434852 ps
CPU time 972.67 seconds
Started Aug 03 04:25:52 PM PDT 24
Finished Aug 03 04:42:05 PM PDT 24
Peak memory 191504 kb
Host smart-7947ac7a-5260-430a-924b-26efc6bed2e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705026019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.2705026019
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.2228105701
Short name T228
Test name
Test status
Simulation time 170417118389 ps
CPU time 157.5 seconds
Started Aug 03 04:25:30 PM PDT 24
Finished Aug 03 04:28:07 PM PDT 24
Peak memory 191504 kb
Host smart-5c5d468c-a6b7-42c9-92dc-67f602859bc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228105701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.2228105701
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.116137599
Short name T137
Test name
Test status
Simulation time 246673456247 ps
CPU time 123.23 seconds
Started Aug 03 04:25:32 PM PDT 24
Finished Aug 03 04:27:35 PM PDT 24
Peak memory 191428 kb
Host smart-4b071654-c16c-4f62-bfd0-259ea37bb6ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116137599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.116137599
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.584286287
Short name T207
Test name
Test status
Simulation time 211165152314 ps
CPU time 61.29 seconds
Started Aug 03 04:25:27 PM PDT 24
Finished Aug 03 04:26:28 PM PDT 24
Peak memory 193832 kb
Host smart-884b72fc-bdb1-4066-bb73-8b8111a2fd24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584286287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.584286287
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.3483726141
Short name T84
Test name
Test status
Simulation time 356502457338 ps
CPU time 156.5 seconds
Started Aug 03 04:25:53 PM PDT 24
Finished Aug 03 04:28:30 PM PDT 24
Peak memory 191540 kb
Host smart-5e875fce-7947-4566-a9f5-097c1209c641
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483726141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.3483726141
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.3829165529
Short name T344
Test name
Test status
Simulation time 148335654385 ps
CPU time 114.88 seconds
Started Aug 03 04:25:31 PM PDT 24
Finished Aug 03 04:27:26 PM PDT 24
Peak memory 183096 kb
Host smart-f19c24c0-4b00-422d-a7fa-686d8779aac9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829165529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.3829165529
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.2309757001
Short name T354
Test name
Test status
Simulation time 612771674541 ps
CPU time 309.08 seconds
Started Aug 03 04:25:34 PM PDT 24
Finished Aug 03 04:30:43 PM PDT 24
Peak memory 191448 kb
Host smart-03131eaa-bb01-4db1-aafb-d2232108be3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309757001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.2309757001
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.3904080223
Short name T278
Test name
Test status
Simulation time 585767086266 ps
CPU time 521.72 seconds
Started Aug 03 04:25:02 PM PDT 24
Finished Aug 03 04:33:44 PM PDT 24
Peak memory 183300 kb
Host smart-d06d3484-266d-463c-b369-a04dd3a9dd36
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904080223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.3904080223
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.4161367321
Short name T398
Test name
Test status
Simulation time 872717495195 ps
CPU time 250.4 seconds
Started Aug 03 04:24:57 PM PDT 24
Finished Aug 03 04:29:08 PM PDT 24
Peak memory 183196 kb
Host smart-7afa05c6-fc59-4a11-9459-05c0a2cc33c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161367321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.4161367321
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.2977474548
Short name T316
Test name
Test status
Simulation time 57134957833 ps
CPU time 91.55 seconds
Started Aug 03 04:25:00 PM PDT 24
Finished Aug 03 04:26:31 PM PDT 24
Peak memory 191540 kb
Host smart-5855b776-af08-4b3f-ae16-3e4df737f1bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977474548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.2977474548
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.2262351152
Short name T280
Test name
Test status
Simulation time 97060750385 ps
CPU time 150.87 seconds
Started Aug 03 04:25:13 PM PDT 24
Finished Aug 03 04:27:54 PM PDT 24
Peak memory 191480 kb
Host smart-44fdf30e-cb95-4a17-9328-425cfa606251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262351152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.2262351152
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.1423858210
Short name T279
Test name
Test status
Simulation time 373001740003 ps
CPU time 548.43 seconds
Started Aug 03 04:25:02 PM PDT 24
Finished Aug 03 04:34:11 PM PDT 24
Peak memory 195112 kb
Host smart-5c153664-2162-438c-80be-64c83c810655
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423858210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
1423858210
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/60.rv_timer_random.378825068
Short name T281
Test name
Test status
Simulation time 124091921808 ps
CPU time 468.52 seconds
Started Aug 03 04:25:15 PM PDT 24
Finished Aug 03 04:33:04 PM PDT 24
Peak memory 193872 kb
Host smart-bf2a181a-d4c0-4a2f-becb-96e6f49c7bea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378825068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.378825068
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.2300784821
Short name T458
Test name
Test status
Simulation time 142597725491 ps
CPU time 105.76 seconds
Started Aug 03 04:25:32 PM PDT 24
Finished Aug 03 04:27:18 PM PDT 24
Peak memory 191468 kb
Host smart-ea4eafc1-72af-484f-9770-7e6fab7fb25e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300784821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.2300784821
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.1439393959
Short name T266
Test name
Test status
Simulation time 510311290235 ps
CPU time 262.49 seconds
Started Aug 03 04:25:52 PM PDT 24
Finished Aug 03 04:30:15 PM PDT 24
Peak memory 191564 kb
Host smart-0b395576-5c74-4ba5-a90b-97c5b8bbda96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439393959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.1439393959
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.3547271887
Short name T351
Test name
Test status
Simulation time 73927967424 ps
CPU time 173.45 seconds
Started Aug 03 04:25:47 PM PDT 24
Finished Aug 03 04:28:40 PM PDT 24
Peak memory 183220 kb
Host smart-55fdffd5-aac1-4e52-ac98-050fa1cb4931
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547271887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.3547271887
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.2178906263
Short name T359
Test name
Test status
Simulation time 23171299582 ps
CPU time 40.78 seconds
Started Aug 03 04:25:41 PM PDT 24
Finished Aug 03 04:26:22 PM PDT 24
Peak memory 183256 kb
Host smart-f04844af-d0fa-486e-801d-b592f2d8e71d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178906263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.2178906263
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.2111629761
Short name T213
Test name
Test status
Simulation time 176364652744 ps
CPU time 110.34 seconds
Started Aug 03 04:25:34 PM PDT 24
Finished Aug 03 04:27:25 PM PDT 24
Peak memory 191604 kb
Host smart-4138ae01-3b54-4519-ac9c-b17cf88a3999
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111629761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.2111629761
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.2326799740
Short name T336
Test name
Test status
Simulation time 42218911498 ps
CPU time 51.74 seconds
Started Aug 03 04:25:17 PM PDT 24
Finished Aug 03 04:26:09 PM PDT 24
Peak memory 194964 kb
Host smart-507afb42-431c-4047-9b80-d1f0eb59329f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326799740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.2326799740
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.1452798017
Short name T365
Test name
Test status
Simulation time 91478734102 ps
CPU time 357.42 seconds
Started Aug 03 04:25:55 PM PDT 24
Finished Aug 03 04:31:52 PM PDT 24
Peak memory 191472 kb
Host smart-3f54d7b5-48ac-419c-85e8-7bf72c395a13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452798017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.1452798017
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.84296889
Short name T261
Test name
Test status
Simulation time 10871564581 ps
CPU time 18.48 seconds
Started Aug 03 04:25:26 PM PDT 24
Finished Aug 03 04:25:49 PM PDT 24
Peak memory 183300 kb
Host smart-cb831f36-ebbd-4713-903b-c4031d870786
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84296889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.84296889
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.2052389916
Short name T367
Test name
Test status
Simulation time 261124921839 ps
CPU time 146.54 seconds
Started Aug 03 04:25:23 PM PDT 24
Finished Aug 03 04:27:50 PM PDT 24
Peak memory 183244 kb
Host smart-2ca6242e-7c73-4d57-8ed1-b84bc7a8f58a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052389916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.2052389916
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.1464048509
Short name T277
Test name
Test status
Simulation time 619397398677 ps
CPU time 587.22 seconds
Started Aug 03 04:25:08 PM PDT 24
Finished Aug 03 04:34:55 PM PDT 24
Peak memory 183336 kb
Host smart-3426a770-79f3-45bb-95d8-c8312639f6f6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464048509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.1464048509
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.2350586059
Short name T401
Test name
Test status
Simulation time 131591756195 ps
CPU time 202.13 seconds
Started Aug 03 04:25:03 PM PDT 24
Finished Aug 03 04:28:25 PM PDT 24
Peak memory 183280 kb
Host smart-ce1e64a2-dabe-491a-a622-4a9753c01cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350586059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.2350586059
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.2992548344
Short name T270
Test name
Test status
Simulation time 817071517913 ps
CPU time 451.77 seconds
Started Aug 03 04:24:56 PM PDT 24
Finished Aug 03 04:32:28 PM PDT 24
Peak memory 191488 kb
Host smart-f028e30f-1e90-46a9-a8a6-fb0d5aea6728
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992548344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.2992548344
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.224256170
Short name T407
Test name
Test status
Simulation time 466384071 ps
CPU time 0.75 seconds
Started Aug 03 04:25:12 PM PDT 24
Finished Aug 03 04:25:13 PM PDT 24
Peak memory 191716 kb
Host smart-59f3e772-f071-4fdb-949c-4450fc6d6464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224256170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.224256170
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.96253412
Short name T426
Test name
Test status
Simulation time 121145461592 ps
CPU time 205.06 seconds
Started Aug 03 04:25:39 PM PDT 24
Finished Aug 03 04:29:05 PM PDT 24
Peak memory 191472 kb
Host smart-4b1b1830-df21-4471-a2c2-bfdce44b0c10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96253412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.96253412
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.3309390902
Short name T237
Test name
Test status
Simulation time 432671307087 ps
CPU time 213.12 seconds
Started Aug 03 04:25:55 PM PDT 24
Finished Aug 03 04:29:29 PM PDT 24
Peak memory 191560 kb
Host smart-136e39b3-607b-470b-b4d4-9d947d5493e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309390902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.3309390902
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.3589546772
Short name T306
Test name
Test status
Simulation time 174288854897 ps
CPU time 420.87 seconds
Started Aug 03 04:25:41 PM PDT 24
Finished Aug 03 04:32:42 PM PDT 24
Peak memory 191564 kb
Host smart-54197d66-8d18-4952-9bba-675f88c7f9d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589546772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.3589546772
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.2510681987
Short name T348
Test name
Test status
Simulation time 96269137397 ps
CPU time 45.43 seconds
Started Aug 03 04:25:51 PM PDT 24
Finished Aug 03 04:26:37 PM PDT 24
Peak memory 183240 kb
Host smart-a9a34b27-1686-4397-a8b6-01e39de4449a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510681987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.2510681987
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.3837047576
Short name T215
Test name
Test status
Simulation time 552099023509 ps
CPU time 740.4 seconds
Started Aug 03 04:25:23 PM PDT 24
Finished Aug 03 04:37:44 PM PDT 24
Peak memory 191500 kb
Host smart-9e3a7ad4-50f7-40b9-8570-0edc1bd8cacd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837047576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.3837047576
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.2519351233
Short name T364
Test name
Test status
Simulation time 49071143516 ps
CPU time 89.37 seconds
Started Aug 03 04:25:21 PM PDT 24
Finished Aug 03 04:26:51 PM PDT 24
Peak memory 183292 kb
Host smart-3d2681b7-769c-4927-a625-75a47530bb42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519351233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.2519351233
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.3342558082
Short name T231
Test name
Test status
Simulation time 306639356303 ps
CPU time 203.03 seconds
Started Aug 03 04:25:21 PM PDT 24
Finished Aug 03 04:28:44 PM PDT 24
Peak memory 191164 kb
Host smart-612d3a1f-e9c3-4a1e-b55a-948f561be842
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342558082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.3342558082
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.739153802
Short name T454
Test name
Test status
Simulation time 41939507991 ps
CPU time 72.61 seconds
Started Aug 03 04:25:38 PM PDT 24
Finished Aug 03 04:26:51 PM PDT 24
Peak memory 191468 kb
Host smart-254e0d78-faaf-4dbb-a76f-487f18e3bbd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739153802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.739153802
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.555708196
Short name T284
Test name
Test status
Simulation time 634515898149 ps
CPU time 202.65 seconds
Started Aug 03 04:25:44 PM PDT 24
Finished Aug 03 04:29:06 PM PDT 24
Peak memory 191428 kb
Host smart-5d40a443-c87e-4550-928a-ee2d4d7b10a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555708196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.555708196
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.385897073
Short name T455
Test name
Test status
Simulation time 99819439260 ps
CPU time 107.12 seconds
Started Aug 03 04:24:57 PM PDT 24
Finished Aug 03 04:26:45 PM PDT 24
Peak memory 183216 kb
Host smart-370958b0-474d-4a54-81b4-a1e239116765
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385897073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.rv_timer_cfg_update_on_fly.385897073
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.59551963
Short name T374
Test name
Test status
Simulation time 179229647867 ps
CPU time 151.97 seconds
Started Aug 03 04:25:05 PM PDT 24
Finished Aug 03 04:27:38 PM PDT 24
Peak memory 182428 kb
Host smart-27609821-70bf-45c0-bf20-186e054c76f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59551963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.59551963
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.912741527
Short name T257
Test name
Test status
Simulation time 130330073808 ps
CPU time 127.59 seconds
Started Aug 03 04:24:53 PM PDT 24
Finished Aug 03 04:27:01 PM PDT 24
Peak memory 191460 kb
Host smart-8076922c-baba-4b72-8859-b24d3f5df78c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912741527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.912741527
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.3197086380
Short name T415
Test name
Test status
Simulation time 30579573495 ps
CPU time 114.04 seconds
Started Aug 03 04:25:00 PM PDT 24
Finished Aug 03 04:26:54 PM PDT 24
Peak memory 191420 kb
Host smart-e6b0f101-9c2d-47a8-b7bc-1f500841ff13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197086380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.3197086380
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.1282693492
Short name T333
Test name
Test status
Simulation time 29683280177 ps
CPU time 393.76 seconds
Started Aug 03 04:26:04 PM PDT 24
Finished Aug 03 04:32:38 PM PDT 24
Peak memory 183332 kb
Host smart-3b3bfbf8-95a7-4b9a-a3d7-0fce56f114cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282693492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.1282693492
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.1727759523
Short name T184
Test name
Test status
Simulation time 332655597054 ps
CPU time 1616.89 seconds
Started Aug 03 04:25:37 PM PDT 24
Finished Aug 03 04:52:35 PM PDT 24
Peak memory 191472 kb
Host smart-e6fbd729-bb01-4def-a0ef-d8cd40d8c033
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727759523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.1727759523
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.157584815
Short name T209
Test name
Test status
Simulation time 281784326464 ps
CPU time 152.47 seconds
Started Aug 03 04:25:54 PM PDT 24
Finished Aug 03 04:28:27 PM PDT 24
Peak memory 191428 kb
Host smart-0c3b8fec-0f9a-4d63-a80c-96e9d7da51f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157584815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.157584815
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.779945856
Short name T241
Test name
Test status
Simulation time 86731965299 ps
CPU time 72.12 seconds
Started Aug 03 04:25:46 PM PDT 24
Finished Aug 03 04:26:58 PM PDT 24
Peak memory 183268 kb
Host smart-5e47a505-5d26-4af0-9110-8a447c047000
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779945856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.779945856
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.2875005013
Short name T130
Test name
Test status
Simulation time 45448739248 ps
CPU time 93.18 seconds
Started Aug 03 04:25:20 PM PDT 24
Finished Aug 03 04:26:53 PM PDT 24
Peak memory 191484 kb
Host smart-00873374-133f-49cb-b0b1-eaa03c7ebc65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875005013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.2875005013
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.4071208566
Short name T139
Test name
Test status
Simulation time 17769108970 ps
CPU time 24.4 seconds
Started Aug 03 04:25:50 PM PDT 24
Finished Aug 03 04:26:14 PM PDT 24
Peak memory 191604 kb
Host smart-38c5bf85-8c08-465c-bddd-5962544e047a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071208566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.4071208566
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.1216392438
Short name T255
Test name
Test status
Simulation time 170819046950 ps
CPU time 176.16 seconds
Started Aug 03 04:25:18 PM PDT 24
Finished Aug 03 04:28:14 PM PDT 24
Peak memory 191508 kb
Host smart-19786c49-c717-4d78-8928-2e2ea1556fb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216392438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.1216392438
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.4005723920
Short name T288
Test name
Test status
Simulation time 201319566772 ps
CPU time 29.67 seconds
Started Aug 03 04:25:43 PM PDT 24
Finished Aug 03 04:26:13 PM PDT 24
Peak memory 183228 kb
Host smart-c0232620-b64e-4a9a-b466-03dd1cfda262
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005723920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.4005723920
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.1751970295
Short name T8
Test name
Test status
Simulation time 63651728108 ps
CPU time 107.41 seconds
Started Aug 03 04:24:55 PM PDT 24
Finished Aug 03 04:26:43 PM PDT 24
Peak memory 183244 kb
Host smart-7a709fa0-5da2-4de9-a3a0-75b5619c27d5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751970295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.1751970295
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.2365321221
Short name T372
Test name
Test status
Simulation time 240463319194 ps
CPU time 184.53 seconds
Started Aug 03 04:25:26 PM PDT 24
Finished Aug 03 04:28:31 PM PDT 24
Peak memory 183288 kb
Host smart-7d993d06-7d66-44c9-9696-8b5a88685e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365321221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.2365321221
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.3058682586
Short name T54
Test name
Test status
Simulation time 591574535517 ps
CPU time 518.33 seconds
Started Aug 03 04:25:07 PM PDT 24
Finished Aug 03 04:33:56 PM PDT 24
Peak memory 191496 kb
Host smart-53a65a71-8a54-4197-9910-7a32997f4bc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058682586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.3058682586
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.1114893580
Short name T214
Test name
Test status
Simulation time 157575613388 ps
CPU time 83.29 seconds
Started Aug 03 04:25:27 PM PDT 24
Finished Aug 03 04:26:50 PM PDT 24
Peak memory 183328 kb
Host smart-c5d3b954-bbc5-4562-b30b-dc6790495a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114893580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.1114893580
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.1080722688
Short name T161
Test name
Test status
Simulation time 46872299046 ps
CPU time 75.11 seconds
Started Aug 03 04:25:24 PM PDT 24
Finished Aug 03 04:26:39 PM PDT 24
Peak memory 183292 kb
Host smart-78972552-737e-4985-9fd2-8349a9cc2563
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080722688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.1080722688
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.3470972745
Short name T210
Test name
Test status
Simulation time 318637182304 ps
CPU time 394.15 seconds
Started Aug 03 04:25:55 PM PDT 24
Finished Aug 03 04:32:30 PM PDT 24
Peak memory 183320 kb
Host smart-4581324c-5edf-49e3-b999-7fd9ffba3d04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470972745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.3470972745
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.2712798755
Short name T313
Test name
Test status
Simulation time 4448891957 ps
CPU time 8.66 seconds
Started Aug 03 04:25:48 PM PDT 24
Finished Aug 03 04:25:56 PM PDT 24
Peak memory 183332 kb
Host smart-2e582e49-c831-4ff8-8316-628a2cee2e8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712798755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.2712798755
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.2932416628
Short name T244
Test name
Test status
Simulation time 235125234082 ps
CPU time 195.35 seconds
Started Aug 03 04:25:50 PM PDT 24
Finished Aug 03 04:29:06 PM PDT 24
Peak memory 191164 kb
Host smart-fbf36805-c68b-4587-bc8b-56885f3b87b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932416628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.2932416628
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.624035699
Short name T217
Test name
Test status
Simulation time 37466126109 ps
CPU time 59.77 seconds
Started Aug 03 04:25:56 PM PDT 24
Finished Aug 03 04:26:55 PM PDT 24
Peak memory 191536 kb
Host smart-e7b4f5dd-993e-4d6d-9664-97ab7902716c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624035699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.624035699
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.2545560443
Short name T245
Test name
Test status
Simulation time 40329501172 ps
CPU time 157.63 seconds
Started Aug 03 04:25:41 PM PDT 24
Finished Aug 03 04:28:18 PM PDT 24
Peak memory 194344 kb
Host smart-b8868ead-9c1e-4978-b3c9-545f3747d1a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545560443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.2545560443
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.2534172912
Short name T427
Test name
Test status
Simulation time 84964342835 ps
CPU time 469.31 seconds
Started Aug 03 04:25:44 PM PDT 24
Finished Aug 03 04:33:33 PM PDT 24
Peak memory 191500 kb
Host smart-b91ff3c3-5e91-4332-9a52-ede9900234ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534172912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.2534172912
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.3533005003
Short name T154
Test name
Test status
Simulation time 556748656844 ps
CPU time 501.47 seconds
Started Aug 03 04:25:32 PM PDT 24
Finished Aug 03 04:33:54 PM PDT 24
Peak memory 191452 kb
Host smart-dccca71b-c5e8-44bc-846d-47667f91853e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533005003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.3533005003
Directory /workspace/98.rv_timer_random/latest
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