Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.62 99.36 98.73 100.00 100.00 100.00 99.66


Total test records in report: 574
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T509 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3298212047 Aug 04 04:35:25 PM PDT 24 Aug 04 04:35:26 PM PDT 24 48219404 ps
T510 /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.695593594 Aug 04 04:35:36 PM PDT 24 Aug 04 04:35:38 PM PDT 24 622144721 ps
T511 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3139297995 Aug 04 04:35:39 PM PDT 24 Aug 04 04:35:41 PM PDT 24 24324434 ps
T83 /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.506483466 Aug 04 04:35:30 PM PDT 24 Aug 04 04:35:31 PM PDT 24 10858152 ps
T512 /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.2917456230 Aug 04 04:35:15 PM PDT 24 Aug 04 04:35:16 PM PDT 24 15887211 ps
T513 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.301318246 Aug 04 04:35:26 PM PDT 24 Aug 04 04:35:27 PM PDT 24 195965073 ps
T514 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.1081581366 Aug 04 04:35:53 PM PDT 24 Aug 04 04:35:54 PM PDT 24 64894594 ps
T515 /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.367159875 Aug 04 04:35:41 PM PDT 24 Aug 04 04:35:42 PM PDT 24 29428082 ps
T516 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.3035034074 Aug 04 04:35:50 PM PDT 24 Aug 04 04:35:51 PM PDT 24 11611368 ps
T517 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.139081961 Aug 04 04:35:55 PM PDT 24 Aug 04 04:35:56 PM PDT 24 69474264 ps
T518 /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.2283686190 Aug 04 04:35:38 PM PDT 24 Aug 04 04:35:39 PM PDT 24 28549133 ps
T84 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.3737297533 Aug 04 04:35:41 PM PDT 24 Aug 04 04:35:41 PM PDT 24 42338049 ps
T519 /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1836365710 Aug 04 04:35:44 PM PDT 24 Aug 04 04:35:44 PM PDT 24 53279626 ps
T520 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.1173287285 Aug 04 04:35:33 PM PDT 24 Aug 04 04:35:34 PM PDT 24 28518410 ps
T521 /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.240822456 Aug 04 04:35:49 PM PDT 24 Aug 04 04:35:49 PM PDT 24 19950875 ps
T522 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3231307 Aug 04 04:35:32 PM PDT 24 Aug 04 04:35:33 PM PDT 24 18958505 ps
T523 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.2525135162 Aug 04 04:35:54 PM PDT 24 Aug 04 04:35:55 PM PDT 24 36473270 ps
T524 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3664846621 Aug 04 04:35:38 PM PDT 24 Aug 04 04:35:41 PM PDT 24 989825371 ps
T525 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.1801731299 Aug 04 04:35:49 PM PDT 24 Aug 04 04:35:49 PM PDT 24 20711820 ps
T103 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.2577116747 Aug 04 04:35:47 PM PDT 24 Aug 04 04:35:48 PM PDT 24 42818380 ps
T526 /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.659092010 Aug 04 04:35:43 PM PDT 24 Aug 04 04:35:44 PM PDT 24 47368950 ps
T85 /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.2995217321 Aug 04 04:35:33 PM PDT 24 Aug 04 04:35:34 PM PDT 24 19942462 ps
T527 /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.1195520831 Aug 04 04:35:45 PM PDT 24 Aug 04 04:35:46 PM PDT 24 63031292 ps
T528 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.2835183050 Aug 04 04:35:26 PM PDT 24 Aug 04 04:35:27 PM PDT 24 36972411 ps
T529 /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.2929592186 Aug 04 04:35:45 PM PDT 24 Aug 04 04:35:46 PM PDT 24 132182173 ps
T530 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.396727104 Aug 04 04:35:31 PM PDT 24 Aug 04 04:35:32 PM PDT 24 17969913 ps
T531 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.2031895644 Aug 04 04:35:46 PM PDT 24 Aug 04 04:35:46 PM PDT 24 13404416 ps
T532 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.4045701608 Aug 04 04:35:45 PM PDT 24 Aug 04 04:35:47 PM PDT 24 91422033 ps
T533 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.3965680419 Aug 04 04:35:50 PM PDT 24 Aug 04 04:35:51 PM PDT 24 36619852 ps
T534 /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.2678121484 Aug 04 04:35:38 PM PDT 24 Aug 04 04:35:44 PM PDT 24 83487270 ps
T535 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.941685043 Aug 04 04:35:52 PM PDT 24 Aug 04 04:35:53 PM PDT 24 50785883 ps
T536 /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.3454111475 Aug 04 04:35:44 PM PDT 24 Aug 04 04:35:44 PM PDT 24 25035340 ps
T537 /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.3056895025 Aug 04 04:35:34 PM PDT 24 Aug 04 04:35:36 PM PDT 24 28371105 ps
T538 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.1804613853 Aug 04 04:35:44 PM PDT 24 Aug 04 04:35:45 PM PDT 24 11496673 ps
T104 /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1809309934 Aug 04 04:35:38 PM PDT 24 Aug 04 04:35:39 PM PDT 24 39848160 ps
T539 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.831765730 Aug 04 04:35:35 PM PDT 24 Aug 04 04:35:36 PM PDT 24 28754562 ps
T540 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.1704072194 Aug 04 04:35:43 PM PDT 24 Aug 04 04:35:44 PM PDT 24 11911359 ps
T541 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.1227469152 Aug 04 04:35:45 PM PDT 24 Aug 04 04:35:47 PM PDT 24 142250030 ps
T542 /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.3945386789 Aug 04 04:35:15 PM PDT 24 Aug 04 04:35:15 PM PDT 24 23036324 ps
T543 /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.3286283575 Aug 04 04:35:33 PM PDT 24 Aug 04 04:35:33 PM PDT 24 22692223 ps
T544 /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.2392473310 Aug 04 04:35:17 PM PDT 24 Aug 04 04:35:21 PM PDT 24 1138197661 ps
T545 /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.735308674 Aug 04 04:35:35 PM PDT 24 Aug 04 04:35:38 PM PDT 24 1818429662 ps
T546 /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2791591633 Aug 04 04:35:36 PM PDT 24 Aug 04 04:35:38 PM PDT 24 145145696 ps
T547 /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.515288885 Aug 04 04:35:52 PM PDT 24 Aug 04 04:35:53 PM PDT 24 24587374 ps
T548 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2655462363 Aug 04 04:35:46 PM PDT 24 Aug 04 04:35:48 PM PDT 24 116480677 ps
T549 /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.1247722153 Aug 04 04:35:46 PM PDT 24 Aug 04 04:35:47 PM PDT 24 26859615 ps
T550 /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.2999485702 Aug 04 04:35:31 PM PDT 24 Aug 04 04:35:32 PM PDT 24 32824578 ps
T551 /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.2759938148 Aug 04 04:35:36 PM PDT 24 Aug 04 04:35:37 PM PDT 24 21963097 ps
T552 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.145984498 Aug 04 04:35:38 PM PDT 24 Aug 04 04:35:39 PM PDT 24 47438657 ps
T86 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.3269450464 Aug 04 04:35:30 PM PDT 24 Aug 04 04:35:36 PM PDT 24 42198918 ps
T553 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.2029774591 Aug 04 04:35:40 PM PDT 24 Aug 04 04:35:41 PM PDT 24 284126284 ps
T554 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1528706473 Aug 04 04:35:53 PM PDT 24 Aug 04 04:35:53 PM PDT 24 15585967 ps
T555 /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.1278345830 Aug 04 04:35:52 PM PDT 24 Aug 04 04:35:53 PM PDT 24 42295547 ps
T556 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.2575909255 Aug 04 04:35:46 PM PDT 24 Aug 04 04:35:46 PM PDT 24 18945278 ps
T557 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.4182094208 Aug 04 04:35:21 PM PDT 24 Aug 04 04:35:23 PM PDT 24 110524306 ps
T558 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3664113234 Aug 04 04:35:56 PM PDT 24 Aug 04 04:35:58 PM PDT 24 259160393 ps
T559 /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.1192591991 Aug 04 04:35:14 PM PDT 24 Aug 04 04:35:15 PM PDT 24 167385326 ps
T560 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.2872078395 Aug 04 04:35:34 PM PDT 24 Aug 04 04:35:35 PM PDT 24 170163043 ps
T561 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3538159881 Aug 04 04:35:46 PM PDT 24 Aug 04 04:35:47 PM PDT 24 11001174 ps
T562 /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.4173956685 Aug 04 04:35:49 PM PDT 24 Aug 04 04:35:49 PM PDT 24 54309927 ps
T563 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2451038877 Aug 04 04:35:53 PM PDT 24 Aug 04 04:35:53 PM PDT 24 16618511 ps
T564 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1638795063 Aug 04 04:35:44 PM PDT 24 Aug 04 04:35:45 PM PDT 24 76016687 ps
T565 /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.1579254098 Aug 04 04:35:37 PM PDT 24 Aug 04 04:35:38 PM PDT 24 305075001 ps
T566 /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.742696832 Aug 04 04:35:38 PM PDT 24 Aug 04 04:35:39 PM PDT 24 34237935 ps
T567 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.423312088 Aug 04 04:35:50 PM PDT 24 Aug 04 04:35:51 PM PDT 24 33154647 ps
T568 /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.2085297050 Aug 04 04:35:38 PM PDT 24 Aug 04 04:35:39 PM PDT 24 44045491 ps
T87 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.745777547 Aug 04 04:35:26 PM PDT 24 Aug 04 04:35:27 PM PDT 24 41322498 ps
T569 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.695879661 Aug 04 04:36:02 PM PDT 24 Aug 04 04:36:03 PM PDT 24 67531735 ps
T570 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.2388333583 Aug 04 04:35:29 PM PDT 24 Aug 04 04:35:30 PM PDT 24 59377499 ps
T571 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.2248382622 Aug 04 04:35:44 PM PDT 24 Aug 04 04:35:46 PM PDT 24 151107581 ps
T572 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.1279139692 Aug 04 04:35:40 PM PDT 24 Aug 04 04:35:41 PM PDT 24 42192993 ps
T573 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.1591881789 Aug 04 04:35:38 PM PDT 24 Aug 04 04:35:39 PM PDT 24 97636479 ps
T574 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.800042574 Aug 04 04:35:55 PM PDT 24 Aug 04 04:35:55 PM PDT 24 36077205 ps
T88 /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.3048803254 Aug 04 04:35:45 PM PDT 24 Aug 04 04:35:46 PM PDT 24 14798038 ps

Test location /workspace/coverage/default/181.rv_timer_random.2803891898
Short name T2
Test name
Test status
Simulation time 115638875594 ps
CPU time 186.43 seconds
Started Aug 04 04:42:24 PM PDT 24
Finished Aug 04 04:45:30 PM PDT 24
Peak memory 195172 kb
Host smart-2017491e-14d0-4411-9eb1-9aa3f5b69b5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803891898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.2803891898
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all_with_rand_reset.1978476497
Short name T11
Test name
Test status
Simulation time 262847545579 ps
CPU time 535.29 seconds
Started Aug 04 04:41:40 PM PDT 24
Finished Aug 04 04:50:35 PM PDT 24
Peak memory 207332 kb
Host smart-12aa7bcb-c6fd-43d6-98b3-7b062dc176fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978476497 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all_with_rand_reset.1978476497
Directory /workspace/40.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.1044169552
Short name T121
Test name
Test status
Simulation time 1891331049262 ps
CPU time 1593.63 seconds
Started Aug 04 04:41:13 PM PDT 24
Finished Aug 04 05:07:47 PM PDT 24
Peak memory 191492 kb
Host smart-65d28dd5-3804-4b83-8586-207fabcfa4c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044169552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
1044169552
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.4107358090
Short name T160
Test name
Test status
Simulation time 2563268024957 ps
CPU time 6783.02 seconds
Started Aug 04 04:41:12 PM PDT 24
Finished Aug 04 06:34:16 PM PDT 24
Peak memory 196352 kb
Host smart-d5a9b17d-f769-4cee-b023-c4b3b1eec61b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107358090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.4107358090
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.873494375
Short name T18
Test name
Test status
Simulation time 800880580 ps
CPU time 0.85 seconds
Started Aug 04 04:41:06 PM PDT 24
Finished Aug 04 04:41:07 PM PDT 24
Peak memory 214512 kb
Host smart-6f5f07b9-48ed-4ac1-8d30-858352a4165c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873494375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.873494375
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.953392771
Short name T165
Test name
Test status
Simulation time 2887283275993 ps
CPU time 1743.29 seconds
Started Aug 04 04:41:48 PM PDT 24
Finished Aug 04 05:10:52 PM PDT 24
Peak memory 191576 kb
Host smart-12153b86-c049-4d3e-98ab-cd4fddb678d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953392771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all.
953392771
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.207752472
Short name T36
Test name
Test status
Simulation time 587830296169 ps
CPU time 492.25 seconds
Started Aug 04 04:41:46 PM PDT 24
Finished Aug 04 04:49:58 PM PDT 24
Peak memory 191540 kb
Host smart-b0ea799e-dad3-48a8-8a6e-e8598f179714
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207752472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all.
207752472
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.240081197
Short name T31
Test name
Test status
Simulation time 45581836 ps
CPU time 0.55 seconds
Started Aug 04 04:35:44 PM PDT 24
Finished Aug 04 04:35:45 PM PDT 24
Peak memory 182792 kb
Host smart-77739b83-3608-4841-b2e9-b89568f18781
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240081197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.240081197
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.358936036
Short name T62
Test name
Test status
Simulation time 722092417048 ps
CPU time 1984.79 seconds
Started Aug 04 04:41:40 PM PDT 24
Finished Aug 04 05:14:45 PM PDT 24
Peak memory 191552 kb
Host smart-8a435494-14a3-4e47-923f-d5a20e0c6cee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358936036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all.
358936036
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.4143489419
Short name T154
Test name
Test status
Simulation time 6141686893480 ps
CPU time 1842.98 seconds
Started Aug 04 04:41:45 PM PDT 24
Finished Aug 04 05:12:28 PM PDT 24
Peak memory 191552 kb
Host smart-db47d4a6-7642-421e-8e1c-2d5c127b90ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143489419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.4143489419
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.3212385708
Short name T122
Test name
Test status
Simulation time 351013561132 ps
CPU time 3436.15 seconds
Started Aug 04 04:41:39 PM PDT 24
Finished Aug 04 05:38:56 PM PDT 24
Peak memory 191576 kb
Host smart-86cb5223-148d-4b21-99b6-79b292ed7458
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212385708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.3212385708
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/104.rv_timer_random.2556144985
Short name T6
Test name
Test status
Simulation time 190529475251 ps
CPU time 2240.06 seconds
Started Aug 04 04:42:03 PM PDT 24
Finished Aug 04 05:19:23 PM PDT 24
Peak memory 191584 kb
Host smart-5801a6ec-673a-4e4e-b95b-81b9e23ddc76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556144985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.2556144985
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.2951758755
Short name T106
Test name
Test status
Simulation time 148668562 ps
CPU time 1.08 seconds
Started Aug 04 04:35:46 PM PDT 24
Finished Aug 04 04:35:57 PM PDT 24
Peak memory 183360 kb
Host smart-ba0bf99f-b75d-4c7a-a5a3-bc0027f6a3f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951758755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.2951758755
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.125825896
Short name T307
Test name
Test status
Simulation time 2953243227941 ps
CPU time 1413.47 seconds
Started Aug 04 04:41:45 PM PDT 24
Finished Aug 04 05:05:19 PM PDT 24
Peak memory 195600 kb
Host smart-7d50590b-bf41-47fe-982c-05a0f44f5b2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125825896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all.
125825896
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.3112334722
Short name T185
Test name
Test status
Simulation time 2316663047384 ps
CPU time 1307.78 seconds
Started Aug 04 04:41:28 PM PDT 24
Finished Aug 04 05:03:16 PM PDT 24
Peak memory 191532 kb
Host smart-38f6a662-9ce6-4445-b102-f4ad8e7a2dad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112334722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.3112334722
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.3132264577
Short name T268
Test name
Test status
Simulation time 2785768673874 ps
CPU time 1643.55 seconds
Started Aug 04 04:41:44 PM PDT 24
Finished Aug 04 05:09:08 PM PDT 24
Peak memory 191552 kb
Host smart-f92dd8ae-d781-439e-87c0-2c74ce57391f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132264577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.3132264577
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.3960130307
Short name T180
Test name
Test status
Simulation time 1016642250397 ps
CPU time 1639.04 seconds
Started Aug 04 04:41:46 PM PDT 24
Finished Aug 04 05:09:06 PM PDT 24
Peak memory 191640 kb
Host smart-333ee7eb-5023-4f26-831f-cd419d96e39a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960130307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.3960130307
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.3264479443
Short name T191
Test name
Test status
Simulation time 881033961584 ps
CPU time 871.79 seconds
Started Aug 04 04:41:36 PM PDT 24
Finished Aug 04 04:56:08 PM PDT 24
Peak memory 195568 kb
Host smart-9c4f7b5a-a9ff-43a3-accf-84360c136f6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264479443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.3264479443
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.3508544684
Short name T64
Test name
Test status
Simulation time 1087731829610 ps
CPU time 1863.41 seconds
Started Aug 04 04:41:10 PM PDT 24
Finished Aug 04 05:12:14 PM PDT 24
Peak memory 191552 kb
Host smart-ce4cf54e-114b-44d3-aefb-a47caffdc099
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508544684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
3508544684
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_random.3647448762
Short name T110
Test name
Test status
Simulation time 1041214346734 ps
CPU time 263.23 seconds
Started Aug 04 04:41:16 PM PDT 24
Finished Aug 04 04:45:40 PM PDT 24
Peak memory 191532 kb
Host smart-f7b51c72-0314-4fb8-8293-ec013df3bb64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647448762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.3647448762
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.3842928672
Short name T141
Test name
Test status
Simulation time 192359409931 ps
CPU time 567.15 seconds
Started Aug 04 04:41:44 PM PDT 24
Finished Aug 04 04:51:11 PM PDT 24
Peak memory 191524 kb
Host smart-b4167a29-4814-4aee-97c8-4dde668b28da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842928672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.3842928672
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.4173534089
Short name T61
Test name
Test status
Simulation time 1299952704878 ps
CPU time 1267.98 seconds
Started Aug 04 04:41:12 PM PDT 24
Finished Aug 04 05:02:21 PM PDT 24
Peak memory 195976 kb
Host smart-2d1246e2-5673-485c-bec9-e57d3cfb193b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173534089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.4173534089
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.270040886
Short name T237
Test name
Test status
Simulation time 245035035864 ps
CPU time 477.15 seconds
Started Aug 04 04:41:11 PM PDT 24
Finished Aug 04 04:49:08 PM PDT 24
Peak memory 191584 kb
Host smart-1d808339-8fa5-47fb-b400-99e289cf4a63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270040886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.270040886
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.1656407886
Short name T63
Test name
Test status
Simulation time 185184899150 ps
CPU time 325.21 seconds
Started Aug 04 04:41:07 PM PDT 24
Finished Aug 04 04:46:33 PM PDT 24
Peak memory 195756 kb
Host smart-57773641-d597-41d7-ae27-aa1f9806382f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656407886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
1656407886
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/117.rv_timer_random.3755189602
Short name T50
Test name
Test status
Simulation time 160268696920 ps
CPU time 419.96 seconds
Started Aug 04 04:42:05 PM PDT 24
Finished Aug 04 04:49:05 PM PDT 24
Peak memory 191584 kb
Host smart-faf5afb6-098d-449e-9a5d-08df4c3ddd24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755189602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.3755189602
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.3423226495
Short name T166
Test name
Test status
Simulation time 474458369795 ps
CPU time 367.93 seconds
Started Aug 04 04:41:49 PM PDT 24
Finished Aug 04 04:47:57 PM PDT 24
Peak memory 193656 kb
Host smart-46a03695-9969-4677-9908-1a89f704c63c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423226495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.3423226495
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.2095701668
Short name T125
Test name
Test status
Simulation time 306529230166 ps
CPU time 359.45 seconds
Started Aug 04 04:42:17 PM PDT 24
Finished Aug 04 04:48:17 PM PDT 24
Peak memory 191580 kb
Host smart-fe36e794-653a-48e5-95e1-9128f2c9b56c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095701668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.2095701668
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.495615309
Short name T158
Test name
Test status
Simulation time 557500470210 ps
CPU time 456.27 seconds
Started Aug 04 04:42:24 PM PDT 24
Finished Aug 04 04:50:00 PM PDT 24
Peak memory 191568 kb
Host smart-224772f1-ad02-431a-b332-43177b3d5775
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495615309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.495615309
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random.2758499376
Short name T329
Test name
Test status
Simulation time 636198900008 ps
CPU time 347.66 seconds
Started Aug 04 04:41:24 PM PDT 24
Finished Aug 04 04:47:12 PM PDT 24
Peak memory 191548 kb
Host smart-82b89395-16e5-4518-9d7f-f34796d8ffad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758499376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.2758499376
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.2415516832
Short name T203
Test name
Test status
Simulation time 135436605176 ps
CPU time 237.63 seconds
Started Aug 04 04:42:00 PM PDT 24
Finished Aug 04 04:45:58 PM PDT 24
Peak memory 191664 kb
Host smart-a6eb0f09-ff15-4705-beef-c9127622ceac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415516832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.2415516832
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random.2492633213
Short name T208
Test name
Test status
Simulation time 462873233561 ps
CPU time 550.63 seconds
Started Aug 04 04:41:24 PM PDT 24
Finished Aug 04 04:50:34 PM PDT 24
Peak memory 191520 kb
Host smart-40718e28-82c0-4bc8-b6d8-c9efa5553622
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492633213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.2492633213
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/150.rv_timer_random.2683126963
Short name T318
Test name
Test status
Simulation time 346957911580 ps
CPU time 413.31 seconds
Started Aug 04 04:42:12 PM PDT 24
Finished Aug 04 04:49:06 PM PDT 24
Peak memory 191552 kb
Host smart-829a6d55-ca53-40cf-ae34-b3c0c112dc3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683126963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.2683126963
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.118849066
Short name T263
Test name
Test status
Simulation time 826993343184 ps
CPU time 1061.79 seconds
Started Aug 04 04:41:41 PM PDT 24
Finished Aug 04 04:59:23 PM PDT 24
Peak memory 191548 kb
Host smart-34e27a92-d934-4bd2-b02e-e62b93281d22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118849066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all.
118849066
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/137.rv_timer_random.4282746117
Short name T244
Test name
Test status
Simulation time 367107069199 ps
CPU time 371.36 seconds
Started Aug 04 04:42:13 PM PDT 24
Finished Aug 04 04:48:24 PM PDT 24
Peak memory 191560 kb
Host smart-58d827d8-6de5-4100-81c3-0c22ea35f696
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282746117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.4282746117
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random.3147927155
Short name T342
Test name
Test status
Simulation time 238730742914 ps
CPU time 276.78 seconds
Started Aug 04 04:41:26 PM PDT 24
Finished Aug 04 04:46:02 PM PDT 24
Peak memory 191616 kb
Host smart-a9a8bd05-4ca8-4903-a796-4685ce56d84d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147927155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.3147927155
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.3429490546
Short name T188
Test name
Test status
Simulation time 163794919336 ps
CPU time 363.19 seconds
Started Aug 04 04:42:19 PM PDT 24
Finished Aug 04 04:48:23 PM PDT 24
Peak memory 191528 kb
Host smart-5ed42299-5ed4-4642-b498-d4c3f683b1a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429490546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.3429490546
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random.2060975586
Short name T288
Test name
Test status
Simulation time 756265568644 ps
CPU time 576.56 seconds
Started Aug 04 04:41:44 PM PDT 24
Finished Aug 04 04:51:20 PM PDT 24
Peak memory 191568 kb
Host smart-042bb610-b351-4357-9a28-aac17a48babf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060975586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.2060975586
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.182574951
Short name T114
Test name
Test status
Simulation time 658544714378 ps
CPU time 882.03 seconds
Started Aug 04 04:41:10 PM PDT 24
Finished Aug 04 04:55:52 PM PDT 24
Peak memory 191604 kb
Host smart-5691ef87-5c42-4225-a1e3-abdd58fcc081
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182574951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.182574951
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.2263155841
Short name T174
Test name
Test status
Simulation time 345296186683 ps
CPU time 2732.18 seconds
Started Aug 04 04:41:42 PM PDT 24
Finished Aug 04 05:27:15 PM PDT 24
Peak memory 197604 kb
Host smart-a6bb00d6-4a7e-4af1-9da1-489773d076e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263155841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.2263155841
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_random.2303901974
Short name T226
Test name
Test status
Simulation time 124097330408 ps
CPU time 137.62 seconds
Started Aug 04 04:41:16 PM PDT 24
Finished Aug 04 04:43:34 PM PDT 24
Peak memory 191596 kb
Host smart-43a80d8a-ac92-4493-9116-3ae80e799371
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303901974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.2303901974
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.1325161291
Short name T213
Test name
Test status
Simulation time 405948145780 ps
CPU time 297.05 seconds
Started Aug 04 04:42:24 PM PDT 24
Finished Aug 04 04:47:21 PM PDT 24
Peak memory 191584 kb
Host smart-bdc9afcc-c5c7-41df-890d-ee01f60f095e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325161291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.1325161291
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random.2539196836
Short name T327
Test name
Test status
Simulation time 386205658918 ps
CPU time 549.35 seconds
Started Aug 04 04:41:23 PM PDT 24
Finished Aug 04 04:50:33 PM PDT 24
Peak memory 191576 kb
Host smart-9af5d2bf-028b-427c-b4a7-06e2b2c6069f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539196836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.2539196836
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.690848066
Short name T44
Test name
Test status
Simulation time 24772757512 ps
CPU time 36.72 seconds
Started Aug 04 04:41:00 PM PDT 24
Finished Aug 04 04:41:37 PM PDT 24
Peak memory 183288 kb
Host smart-9387784e-9ae9-435e-8006-05b46ea5beff
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690848066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.rv_timer_cfg_update_on_fly.690848066
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.2666490002
Short name T196
Test name
Test status
Simulation time 1386377964921 ps
CPU time 737.3 seconds
Started Aug 04 04:41:37 PM PDT 24
Finished Aug 04 04:53:55 PM PDT 24
Peak memory 183448 kb
Host smart-0a422fe8-04ab-4047-ac88-2b6bcc226e10
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666490002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.2666490002
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_random.1160068694
Short name T1
Test name
Test status
Simulation time 830944500456 ps
CPU time 656.82 seconds
Started Aug 04 04:41:28 PM PDT 24
Finished Aug 04 04:52:25 PM PDT 24
Peak memory 191532 kb
Host smart-816b18f8-2e74-4af7-b9b0-791ea99105b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160068694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.1160068694
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.1520398828
Short name T306
Test name
Test status
Simulation time 556253426711 ps
CPU time 288.1 seconds
Started Aug 04 04:42:12 PM PDT 24
Finished Aug 04 04:47:01 PM PDT 24
Peak memory 191568 kb
Host smart-7a2766e6-dd5c-4417-9ee1-8a0454033d8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520398828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.1520398828
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.921989616
Short name T152
Test name
Test status
Simulation time 25675395298 ps
CPU time 38.1 seconds
Started Aug 04 04:42:10 PM PDT 24
Finished Aug 04 04:42:48 PM PDT 24
Peak memory 191496 kb
Host smart-9287727f-0e73-44c8-a5c0-6451bbdf647c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921989616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.921989616
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.764004285
Short name T292
Test name
Test status
Simulation time 74060826795 ps
CPU time 127.26 seconds
Started Aug 04 04:42:15 PM PDT 24
Finished Aug 04 04:44:22 PM PDT 24
Peak memory 191652 kb
Host smart-c8dd3209-112e-4410-9b66-5a8e75133731
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764004285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.764004285
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.621267908
Short name T450
Test name
Test status
Simulation time 307820093801 ps
CPU time 2298.34 seconds
Started Aug 04 04:42:27 PM PDT 24
Finished Aug 04 05:20:46 PM PDT 24
Peak memory 191576 kb
Host smart-b8cc7249-f726-4c3a-a322-3c32bee9de53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621267908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.621267908
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.607373289
Short name T171
Test name
Test status
Simulation time 432349025034 ps
CPU time 736.71 seconds
Started Aug 04 04:41:16 PM PDT 24
Finished Aug 04 04:53:32 PM PDT 24
Peak memory 191532 kb
Host smart-8b6d6910-ee07-4abf-bdb9-aa2c2d8465f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607373289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.607373289
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.2920727087
Short name T299
Test name
Test status
Simulation time 408658209898 ps
CPU time 186.01 seconds
Started Aug 04 04:41:23 PM PDT 24
Finished Aug 04 04:44:29 PM PDT 24
Peak memory 191564 kb
Host smart-9bcd80dd-01cd-41b8-abd4-fe411fb85258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920727087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.2920727087
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.1158877207
Short name T96
Test name
Test status
Simulation time 80590015264 ps
CPU time 142.49 seconds
Started Aug 04 04:41:14 PM PDT 24
Finished Aug 04 04:43:36 PM PDT 24
Peak memory 191608 kb
Host smart-42ef60dc-0ecf-4ada-8b5a-7100790570dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158877207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.1158877207
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/72.rv_timer_random.366968754
Short name T250
Test name
Test status
Simulation time 133175230954 ps
CPU time 670.84 seconds
Started Aug 04 04:41:47 PM PDT 24
Finished Aug 04 04:52:58 PM PDT 24
Peak memory 191576 kb
Host smart-ca70bddf-746b-4d91-9880-abf2608baff3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366968754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.366968754
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.3523607402
Short name T277
Test name
Test status
Simulation time 62455191956 ps
CPU time 1130.3 seconds
Started Aug 04 04:41:58 PM PDT 24
Finished Aug 04 05:00:49 PM PDT 24
Peak memory 191556 kb
Host smart-f4f1613f-9cb5-4e3f-a403-ec6697947ce2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523607402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.3523607402
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.1856503209
Short name T80
Test name
Test status
Simulation time 21416445 ps
CPU time 0.52 seconds
Started Aug 04 04:35:42 PM PDT 24
Finished Aug 04 04:35:43 PM PDT 24
Peak memory 182752 kb
Host smart-11489e75-10c5-4781-ae12-fb7193107589
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856503209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.1856503209
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.7014136
Short name T198
Test name
Test status
Simulation time 4379300691862 ps
CPU time 1467.31 seconds
Started Aug 04 04:41:08 PM PDT 24
Finished Aug 04 05:05:35 PM PDT 24
Peak memory 191588 kb
Host smart-4a7dcad1-80f1-48e5-992d-a59fc40536cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7014136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_a
ll_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.7014136
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/105.rv_timer_random.387362837
Short name T294
Test name
Test status
Simulation time 49895942834 ps
CPU time 65.51 seconds
Started Aug 04 04:41:59 PM PDT 24
Finished Aug 04 04:43:05 PM PDT 24
Peak memory 195092 kb
Host smart-41055d36-f5e2-4a7d-96ca-0ae9a899727c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387362837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.387362837
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.862070354
Short name T209
Test name
Test status
Simulation time 50294270337 ps
CPU time 84.57 seconds
Started Aug 04 04:41:58 PM PDT 24
Finished Aug 04 04:43:23 PM PDT 24
Peak memory 191604 kb
Host smart-89da94c2-b1d2-4c54-8a8d-d42466d93e95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862070354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.862070354
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.3289671694
Short name T192
Test name
Test status
Simulation time 146673252437 ps
CPU time 141.06 seconds
Started Aug 04 04:42:00 PM PDT 24
Finished Aug 04 04:44:21 PM PDT 24
Peak memory 191556 kb
Host smart-d7a5b048-642a-4d87-8192-ccbf7b6c6481
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289671694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.3289671694
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/120.rv_timer_random.3805859368
Short name T168
Test name
Test status
Simulation time 167537129237 ps
CPU time 555.53 seconds
Started Aug 04 04:42:03 PM PDT 24
Finished Aug 04 04:51:18 PM PDT 24
Peak memory 191584 kb
Host smart-8e36445f-8c9d-45d9-8b64-4ab0830874e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805859368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.3805859368
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.1281209789
Short name T233
Test name
Test status
Simulation time 55360381967 ps
CPU time 208.57 seconds
Started Aug 04 04:42:08 PM PDT 24
Finished Aug 04 04:45:37 PM PDT 24
Peak memory 191544 kb
Host smart-8188bc3e-1e7b-47aa-b40a-b94804db96fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281209789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.1281209789
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.154025749
Short name T67
Test name
Test status
Simulation time 1576775354421 ps
CPU time 797.34 seconds
Started Aug 04 04:41:21 PM PDT 24
Finished Aug 04 04:54:38 PM PDT 24
Peak memory 183372 kb
Host smart-c913466e-4227-4b35-bdc5-0fa72ac1db60
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154025749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.rv_timer_cfg_update_on_fly.154025749
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/171.rv_timer_random.935075597
Short name T322
Test name
Test status
Simulation time 619787444711 ps
CPU time 279.23 seconds
Started Aug 04 04:42:23 PM PDT 24
Finished Aug 04 04:47:02 PM PDT 24
Peak memory 191640 kb
Host smart-bcbf8ab6-c0e4-423b-a0f1-f3773f04bf58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935075597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.935075597
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.3440609196
Short name T313
Test name
Test status
Simulation time 411835242211 ps
CPU time 604.91 seconds
Started Aug 04 04:42:24 PM PDT 24
Finished Aug 04 04:52:29 PM PDT 24
Peak memory 191500 kb
Host smart-be30e973-7550-437e-beea-b5cdda920896
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440609196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.3440609196
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random.3849836564
Short name T117
Test name
Test status
Simulation time 296802717821 ps
CPU time 327.92 seconds
Started Aug 04 04:41:16 PM PDT 24
Finished Aug 04 04:46:44 PM PDT 24
Peak memory 191568 kb
Host smart-de9e2686-1bf7-4178-b585-d5070e26abf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849836564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.3849836564
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.3525223401
Short name T115
Test name
Test status
Simulation time 1280894332354 ps
CPU time 746.68 seconds
Started Aug 04 04:42:30 PM PDT 24
Finished Aug 04 04:54:57 PM PDT 24
Peak memory 191624 kb
Host smart-d34a6892-558e-41e8-bcfb-ea004b3faa78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525223401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.3525223401
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.2716653651
Short name T99
Test name
Test status
Simulation time 383364787161 ps
CPU time 157.83 seconds
Started Aug 04 04:41:16 PM PDT 24
Finished Aug 04 04:43:54 PM PDT 24
Peak memory 191544 kb
Host smart-eb2679cc-001a-4425-a476-0103deae210a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716653651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.2716653651
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_random.1684849301
Short name T248
Test name
Test status
Simulation time 39899344487 ps
CPU time 275.5 seconds
Started Aug 04 04:41:02 PM PDT 24
Finished Aug 04 04:45:38 PM PDT 24
Peak memory 191560 kb
Host smart-569b9f5d-177d-4b53-8ce7-cbd32c11d9d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684849301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.1684849301
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.1104826305
Short name T184
Test name
Test status
Simulation time 207004041159 ps
CPU time 196.31 seconds
Started Aug 04 04:41:27 PM PDT 24
Finished Aug 04 04:44:43 PM PDT 24
Peak memory 183248 kb
Host smart-69690cc7-027c-4166-98a2-bbfaaeac9e4b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104826305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.1104826305
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.2713408054
Short name T135
Test name
Test status
Simulation time 40985899808 ps
CPU time 66.95 seconds
Started Aug 04 04:41:45 PM PDT 24
Finished Aug 04 04:42:52 PM PDT 24
Peak memory 191528 kb
Host smart-0fb01df9-c8df-482f-af9b-88c769b51ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713408054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.2713408054
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.1642954646
Short name T261
Test name
Test status
Simulation time 92746119192 ps
CPU time 354.94 seconds
Started Aug 04 04:41:44 PM PDT 24
Finished Aug 04 04:47:39 PM PDT 24
Peak memory 191564 kb
Host smart-11e99404-658d-4fea-bb32-cc2f2899d91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642954646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.1642954646
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/77.rv_timer_random.9235378
Short name T239
Test name
Test status
Simulation time 106624135147 ps
CPU time 172.48 seconds
Started Aug 04 04:41:51 PM PDT 24
Finished Aug 04 04:44:44 PM PDT 24
Peak memory 193748 kb
Host smart-a4a0dcf9-ba88-4cfe-8583-b8ab253632bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9235378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.9235378
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.615804644
Short name T319
Test name
Test status
Simulation time 478369468518 ps
CPU time 250.65 seconds
Started Aug 04 04:42:00 PM PDT 24
Finished Aug 04 04:46:11 PM PDT 24
Peak memory 195084 kb
Host smart-ecd47c3f-653f-474b-a52e-90bf9c3d2481
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615804644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.615804644
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.1542856688
Short name T111
Test name
Test status
Simulation time 267532833697 ps
CPU time 528.47 seconds
Started Aug 04 04:41:55 PM PDT 24
Finished Aug 04 04:50:44 PM PDT 24
Peak memory 195180 kb
Host smart-46ba13f6-f3e3-42c6-9457-7d0476930e0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542856688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.1542856688
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1809309934
Short name T104
Test name
Test status
Simulation time 39848160 ps
CPU time 0.8 seconds
Started Aug 04 04:35:38 PM PDT 24
Finished Aug 04 04:35:39 PM PDT 24
Peak memory 193704 kb
Host smart-75ab3b02-3845-42f2-8e56-5ac9fbf3016a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809309934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.1809309934
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/10.rv_timer_random.1536640746
Short name T259
Test name
Test status
Simulation time 254103257640 ps
CPU time 94.21 seconds
Started Aug 04 04:41:34 PM PDT 24
Finished Aug 04 04:43:08 PM PDT 24
Peak memory 194972 kb
Host smart-30b0527f-a8ba-4c8b-8d4f-c85cc4cff215
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536640746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.1536640746
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.3111590206
Short name T21
Test name
Test status
Simulation time 111052457102 ps
CPU time 297.67 seconds
Started Aug 04 04:42:00 PM PDT 24
Finished Aug 04 04:46:58 PM PDT 24
Peak memory 191544 kb
Host smart-77b5bfcf-b6ce-4ba6-b5c1-4d3f22c9487e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111590206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.3111590206
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.482238750
Short name T207
Test name
Test status
Simulation time 422147550765 ps
CPU time 470.42 seconds
Started Aug 04 04:41:07 PM PDT 24
Finished Aug 04 04:48:58 PM PDT 24
Peak memory 183348 kb
Host smart-7bd4cdb2-4e8c-4da1-af58-87d8721f8d03
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482238750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.rv_timer_cfg_update_on_fly.482238750
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/112.rv_timer_random.1747277161
Short name T332
Test name
Test status
Simulation time 17008287164 ps
CPU time 19.05 seconds
Started Aug 04 04:42:00 PM PDT 24
Finished Aug 04 04:42:19 PM PDT 24
Peak memory 183336 kb
Host smart-1fe63fee-a35c-407b-b5cc-326f72e9e5b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747277161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.1747277161
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.3358001893
Short name T7
Test name
Test status
Simulation time 197364529411 ps
CPU time 104.21 seconds
Started Aug 04 04:42:04 PM PDT 24
Finished Aug 04 04:43:48 PM PDT 24
Peak memory 191564 kb
Host smart-ef9a2858-1cef-4a88-9c9c-19c386883052
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358001893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.3358001893
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.912306470
Short name T200
Test name
Test status
Simulation time 1223544817147 ps
CPU time 226.38 seconds
Started Aug 04 04:42:04 PM PDT 24
Finished Aug 04 04:45:51 PM PDT 24
Peak memory 191540 kb
Host smart-585a5511-99e3-423e-893f-5db99798fe68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912306470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.912306470
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.3645432145
Short name T273
Test name
Test status
Simulation time 690016399522 ps
CPU time 173.61 seconds
Started Aug 04 04:42:02 PM PDT 24
Finished Aug 04 04:44:56 PM PDT 24
Peak memory 191540 kb
Host smart-7872a4d3-12fc-47ef-9f35-b44af68ad95d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645432145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.3645432145
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.959630539
Short name T205
Test name
Test status
Simulation time 114673398952 ps
CPU time 265.08 seconds
Started Aug 04 04:42:07 PM PDT 24
Finished Aug 04 04:46:32 PM PDT 24
Peak memory 191616 kb
Host smart-8e41a51a-f17d-48c5-a7c8-4b31b3bf2db5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959630539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.959630539
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/140.rv_timer_random.3513152272
Short name T137
Test name
Test status
Simulation time 313524667008 ps
CPU time 509.47 seconds
Started Aug 04 04:42:11 PM PDT 24
Finished Aug 04 04:50:41 PM PDT 24
Peak memory 191516 kb
Host smart-2afaf80e-a297-49bc-9a4c-22ecf3fbeb7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513152272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.3513152272
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.1655666073
Short name T275
Test name
Test status
Simulation time 633521522098 ps
CPU time 400.24 seconds
Started Aug 04 04:42:09 PM PDT 24
Finished Aug 04 04:48:50 PM PDT 24
Peak memory 191544 kb
Host smart-dccff686-66be-438f-834b-a2c58c5b909f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655666073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.1655666073
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.3593639971
Short name T35
Test name
Test status
Simulation time 544133296827 ps
CPU time 952.4 seconds
Started Aug 04 04:41:05 PM PDT 24
Finished Aug 04 04:56:57 PM PDT 24
Peak memory 195844 kb
Host smart-3dd6fea9-60cf-4175-aa69-2290c142992a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593639971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.3593639971
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/154.rv_timer_random.3592227775
Short name T193
Test name
Test status
Simulation time 634730179166 ps
CPU time 1829.42 seconds
Started Aug 04 04:42:18 PM PDT 24
Finished Aug 04 05:12:48 PM PDT 24
Peak memory 191552 kb
Host smart-a5bc6f2c-1b73-4dc7-9a17-96c73fd7c829
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592227775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.3592227775
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.311800391
Short name T287
Test name
Test status
Simulation time 970880425300 ps
CPU time 757.48 seconds
Started Aug 04 04:42:19 PM PDT 24
Finished Aug 04 04:54:57 PM PDT 24
Peak memory 191528 kb
Host smart-c16c102c-09ba-4380-a4ce-941274472060
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311800391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.311800391
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.3397950565
Short name T279
Test name
Test status
Simulation time 235925399268 ps
CPU time 246.92 seconds
Started Aug 04 04:42:22 PM PDT 24
Finished Aug 04 04:46:29 PM PDT 24
Peak memory 193312 kb
Host smart-b9f99b08-0abf-4d35-82bf-eeb227274517
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397950565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.3397950565
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/180.rv_timer_random.351469149
Short name T204
Test name
Test status
Simulation time 236477778993 ps
CPU time 149.41 seconds
Started Aug 04 04:42:24 PM PDT 24
Finished Aug 04 04:44:54 PM PDT 24
Peak memory 183312 kb
Host smart-b22acd31-690d-41ea-b304-02b8d7961ada
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351469149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.351469149
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.2911516112
Short name T27
Test name
Test status
Simulation time 509101515811 ps
CPU time 956.15 seconds
Started Aug 04 04:42:24 PM PDT 24
Finished Aug 04 04:58:20 PM PDT 24
Peak memory 191596 kb
Host smart-d5db8481-60b1-4a0f-8495-66e05dca691b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911516112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.2911516112
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.3151823180
Short name T223
Test name
Test status
Simulation time 372757543534 ps
CPU time 297.39 seconds
Started Aug 04 04:42:31 PM PDT 24
Finished Aug 04 04:47:28 PM PDT 24
Peak memory 194884 kb
Host smart-7328e29a-7de1-47f4-a92d-5126999a8e0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151823180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.3151823180
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.1440711508
Short name T323
Test name
Test status
Simulation time 636548716553 ps
CPU time 424.19 seconds
Started Aug 04 04:42:31 PM PDT 24
Finished Aug 04 04:49:35 PM PDT 24
Peak memory 190968 kb
Host smart-b8fb945a-b23b-47e1-85bd-73fd281436cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440711508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.1440711508
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.2378459262
Short name T361
Test name
Test status
Simulation time 398911715839 ps
CPU time 655.1 seconds
Started Aug 04 04:41:15 PM PDT 24
Finished Aug 04 04:52:10 PM PDT 24
Peak memory 183268 kb
Host smart-7c982a2e-e82d-4bc8-877d-c11ca5629b57
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378459262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.2378459262
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_random.423493335
Short name T195
Test name
Test status
Simulation time 484052447044 ps
CPU time 1024.76 seconds
Started Aug 04 04:41:37 PM PDT 24
Finished Aug 04 04:58:42 PM PDT 24
Peak memory 191636 kb
Host smart-59a0d808-c93d-48b9-9453-1abad85b3798
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423493335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.423493335
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.2883061918
Short name T316
Test name
Test status
Simulation time 1657781273989 ps
CPU time 461.84 seconds
Started Aug 04 04:41:45 PM PDT 24
Finished Aug 04 04:49:27 PM PDT 24
Peak memory 183380 kb
Host smart-78af0b0c-1a1e-4798-a16f-ffd596b88569
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883061918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.2883061918
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/90.rv_timer_random.3829322152
Short name T109
Test name
Test status
Simulation time 531820521610 ps
CPU time 428.26 seconds
Started Aug 04 04:41:57 PM PDT 24
Finished Aug 04 04:49:06 PM PDT 24
Peak memory 191636 kb
Host smart-be624e05-5435-4cc1-af58-b4e719357828
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829322152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.3829322152
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.1359767982
Short name T494
Test name
Test status
Simulation time 60700811 ps
CPU time 0.73 seconds
Started Aug 04 04:35:27 PM PDT 24
Finished Aug 04 04:35:27 PM PDT 24
Peak memory 192660 kb
Host smart-86b80036-5161-4a24-9fdc-1d3080588a52
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359767982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.1359767982
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3664846621
Short name T524
Test name
Test status
Simulation time 989825371 ps
CPU time 2.73 seconds
Started Aug 04 04:35:38 PM PDT 24
Finished Aug 04 04:35:41 PM PDT 24
Peak memory 191308 kb
Host smart-862e1130-ee43-4835-bc84-7e0f29397df7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664846621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.3664846621
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.2120543514
Short name T472
Test name
Test status
Simulation time 93475334 ps
CPU time 0.58 seconds
Started Aug 04 04:35:18 PM PDT 24
Finished Aug 04 04:35:19 PM PDT 24
Peak memory 182744 kb
Host smart-375ea72a-9749-4300-ab7a-3d0811a7f503
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120543514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.2120543514
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.2283686190
Short name T518
Test name
Test status
Simulation time 28549133 ps
CPU time 1.32 seconds
Started Aug 04 04:35:38 PM PDT 24
Finished Aug 04 04:35:39 PM PDT 24
Peak memory 197632 kb
Host smart-b175fab3-bf41-40f6-964b-b9e0f2807292
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283686190 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.2283686190
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.3639481718
Short name T101
Test name
Test status
Simulation time 15140272 ps
CPU time 0.62 seconds
Started Aug 04 04:35:27 PM PDT 24
Finished Aug 04 04:35:28 PM PDT 24
Peak memory 182796 kb
Host smart-9e807f10-a0ee-41d7-8449-b699520301fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639481718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.3639481718
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.3619623387
Short name T457
Test name
Test status
Simulation time 17320586 ps
CPU time 0.59 seconds
Started Aug 04 04:35:38 PM PDT 24
Finished Aug 04 04:35:39 PM PDT 24
Peak memory 182620 kb
Host smart-49fa185d-d2f2-4868-944f-26473a979a24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619623387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.3619623387
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.1579254098
Short name T565
Test name
Test status
Simulation time 305075001 ps
CPU time 0.61 seconds
Started Aug 04 04:35:37 PM PDT 24
Finished Aug 04 04:35:38 PM PDT 24
Peak memory 191464 kb
Host smart-1e4c7c30-2f96-4f01-be2b-ffdda09a1736
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579254098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.1579254098
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.1227469152
Short name T541
Test name
Test status
Simulation time 142250030 ps
CPU time 2.12 seconds
Started Aug 04 04:35:45 PM PDT 24
Finished Aug 04 04:35:47 PM PDT 24
Peak memory 197300 kb
Host smart-866e8b55-e135-4c48-867f-500b9d944ebd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227469152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.1227469152
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1144489417
Short name T29
Test name
Test status
Simulation time 1247596944 ps
CPU time 1.3 seconds
Started Aug 04 04:35:36 PM PDT 24
Finished Aug 04 04:35:37 PM PDT 24
Peak memory 195492 kb
Host smart-5f010e82-200a-49fa-9feb-e8dbfd637fc8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144489417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.1144489417
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.3269450464
Short name T86
Test name
Test status
Simulation time 42198918 ps
CPU time 0.8 seconds
Started Aug 04 04:35:30 PM PDT 24
Finished Aug 04 04:35:36 PM PDT 24
Peak memory 182776 kb
Host smart-d16ec31f-83fb-4f2b-8d09-0c20d2a636d5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269450464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.3269450464
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2791591633
Short name T546
Test name
Test status
Simulation time 145145696 ps
CPU time 1.54 seconds
Started Aug 04 04:35:36 PM PDT 24
Finished Aug 04 04:35:38 PM PDT 24
Peak memory 192200 kb
Host smart-3dd7fba2-004d-46a5-9d90-f2ceb7494fb3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791591633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.2791591633
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.3144391015
Short name T500
Test name
Test status
Simulation time 27601707 ps
CPU time 0.56 seconds
Started Aug 04 04:35:32 PM PDT 24
Finished Aug 04 04:35:32 PM PDT 24
Peak memory 182780 kb
Host smart-66d6635e-2e3f-4764-ad92-ead096a28689
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144391015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.3144391015
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.1311146549
Short name T452
Test name
Test status
Simulation time 14536465 ps
CPU time 0.65 seconds
Started Aug 04 04:35:34 PM PDT 24
Finished Aug 04 04:35:39 PM PDT 24
Peak memory 194424 kb
Host smart-509df40a-1ac8-4033-aeab-5240bece24d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311146549 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.1311146549
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.2085297050
Short name T568
Test name
Test status
Simulation time 44045491 ps
CPU time 0.6 seconds
Started Aug 04 04:35:38 PM PDT 24
Finished Aug 04 04:35:39 PM PDT 24
Peak memory 182772 kb
Host smart-da58ca71-41b4-48f4-8dd3-bee1673c4a93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085297050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.2085297050
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.3522203957
Short name T477
Test name
Test status
Simulation time 12498999 ps
CPU time 0.55 seconds
Started Aug 04 04:35:36 PM PDT 24
Finished Aug 04 04:35:36 PM PDT 24
Peak memory 182132 kb
Host smart-b9d77189-4b26-4eca-a069-8836a4151133
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522203957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.3522203957
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.742696832
Short name T566
Test name
Test status
Simulation time 34237935 ps
CPU time 0.71 seconds
Started Aug 04 04:35:38 PM PDT 24
Finished Aug 04 04:35:39 PM PDT 24
Peak memory 191760 kb
Host smart-43d07b50-08f8-4a06-be6d-2a575f174f93
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742696832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_tim
er_same_csr_outstanding.742696832
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.1375784900
Short name T454
Test name
Test status
Simulation time 59797795 ps
CPU time 2.8 seconds
Started Aug 04 04:35:26 PM PDT 24
Finished Aug 04 04:35:29 PM PDT 24
Peak memory 197540 kb
Host smart-d759467d-233c-4a66-bbb3-00a1a9b3b027
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375784900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.1375784900
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3298212047
Short name T509
Test name
Test status
Simulation time 48219404 ps
CPU time 0.81 seconds
Started Aug 04 04:35:25 PM PDT 24
Finished Aug 04 04:35:26 PM PDT 24
Peak memory 183092 kb
Host smart-c2621455-eb4a-4313-a104-4fe883627e37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298212047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.3298212047
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.1279139692
Short name T572
Test name
Test status
Simulation time 42192993 ps
CPU time 0.88 seconds
Started Aug 04 04:35:40 PM PDT 24
Finished Aug 04 04:35:41 PM PDT 24
Peak memory 196920 kb
Host smart-6bbd4b91-16ae-4746-a587-cf6c196b6524
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279139692 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.1279139692
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.3198507423
Short name T81
Test name
Test status
Simulation time 57328392 ps
CPU time 0.61 seconds
Started Aug 04 04:35:49 PM PDT 24
Finished Aug 04 04:35:50 PM PDT 24
Peak memory 182824 kb
Host smart-fad2449c-0dca-4020-b4f8-515e87473554
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198507423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.3198507423
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.396727104
Short name T530
Test name
Test status
Simulation time 17969913 ps
CPU time 0.56 seconds
Started Aug 04 04:35:31 PM PDT 24
Finished Aug 04 04:35:32 PM PDT 24
Peak memory 182528 kb
Host smart-711a3f9d-81ec-4074-9801-1b597f91149b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396727104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.396727104
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.139081961
Short name T517
Test name
Test status
Simulation time 69474264 ps
CPU time 0.62 seconds
Started Aug 04 04:35:55 PM PDT 24
Finished Aug 04 04:35:56 PM PDT 24
Peak memory 191720 kb
Host smart-c388aaf9-1c74-4cfd-a771-098674f420e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139081961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_ti
mer_same_csr_outstanding.139081961
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.444936332
Short name T468
Test name
Test status
Simulation time 61995626 ps
CPU time 2.85 seconds
Started Aug 04 04:35:32 PM PDT 24
Finished Aug 04 04:35:35 PM PDT 24
Peak memory 197524 kb
Host smart-b361b3d0-d2a3-4e6c-891a-3a9db14efccc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444936332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.444936332
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.94260851
Short name T28
Test name
Test status
Simulation time 368806742 ps
CPU time 1.05 seconds
Started Aug 04 04:35:45 PM PDT 24
Finished Aug 04 04:35:46 PM PDT 24
Peak memory 195232 kb
Host smart-8402c6d8-aead-4577-a14d-c00d7619c8a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94260851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_int
g_err.94260851
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.4205114877
Short name T462
Test name
Test status
Simulation time 16231352 ps
CPU time 0.69 seconds
Started Aug 04 04:35:29 PM PDT 24
Finished Aug 04 04:35:30 PM PDT 24
Peak memory 194772 kb
Host smart-0919a25b-96fd-414a-8579-5d845d2b4477
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205114877 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.4205114877
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.3566214771
Short name T487
Test name
Test status
Simulation time 22012922 ps
CPU time 0.54 seconds
Started Aug 04 04:35:47 PM PDT 24
Finished Aug 04 04:35:48 PM PDT 24
Peak memory 182316 kb
Host smart-09b4d596-fe68-4e6d-aedd-ca75e4721876
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566214771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.3566214771
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3300586159
Short name T54
Test name
Test status
Simulation time 56930309 ps
CPU time 0.7 seconds
Started Aug 04 04:35:41 PM PDT 24
Finished Aug 04 04:35:41 PM PDT 24
Peak memory 193412 kb
Host smart-ce6ca2df-e2c7-4216-a1ef-63eaa6291e28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300586159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.3300586159
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.1252798399
Short name T495
Test name
Test status
Simulation time 56249960 ps
CPU time 2.61 seconds
Started Aug 04 04:35:42 PM PDT 24
Finished Aug 04 04:35:45 PM PDT 24
Peak memory 197544 kb
Host smart-aed0956a-e934-4c21-80c1-d619e36d6aac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252798399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.1252798399
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.2880884173
Short name T102
Test name
Test status
Simulation time 41933266 ps
CPU time 0.83 seconds
Started Aug 04 04:35:51 PM PDT 24
Finished Aug 04 04:35:51 PM PDT 24
Peak memory 183200 kb
Host smart-83e021ba-2037-4c40-999e-bc41cacf29cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880884173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.2880884173
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.1591881789
Short name T573
Test name
Test status
Simulation time 97636479 ps
CPU time 0.85 seconds
Started Aug 04 04:35:38 PM PDT 24
Finished Aug 04 04:35:39 PM PDT 24
Peak memory 196688 kb
Host smart-5d65ece0-4e66-4278-a449-c59eb1e09531
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591881789 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.1591881789
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1770794807
Short name T55
Test name
Test status
Simulation time 41938567 ps
CPU time 0.57 seconds
Started Aug 04 04:35:44 PM PDT 24
Finished Aug 04 04:35:45 PM PDT 24
Peak memory 192020 kb
Host smart-936220a3-2cea-4403-bfe4-9b5a6aac767f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770794807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.1770794807
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.831765730
Short name T539
Test name
Test status
Simulation time 28754562 ps
CPU time 0.53 seconds
Started Aug 04 04:35:35 PM PDT 24
Finished Aug 04 04:35:36 PM PDT 24
Peak memory 182576 kb
Host smart-e361e32f-c9d5-4aac-bb3a-f712a58a6460
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831765730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.831765730
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3231307
Short name T522
Test name
Test status
Simulation time 18958505 ps
CPU time 0.68 seconds
Started Aug 04 04:35:32 PM PDT 24
Finished Aug 04 04:35:33 PM PDT 24
Peak memory 193128 kb
Host smart-4ed42189-3dba-46ed-b1a0-218716394522
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_t
imer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_time
r_same_csr_outstanding.3231307
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.735308674
Short name T545
Test name
Test status
Simulation time 1818429662 ps
CPU time 2.82 seconds
Started Aug 04 04:35:35 PM PDT 24
Finished Aug 04 04:35:38 PM PDT 24
Peak memory 197496 kb
Host smart-bf452a82-6dee-4ac8-bbdd-b561e43381d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735308674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.735308674
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.1440075813
Short name T60
Test name
Test status
Simulation time 49142472 ps
CPU time 0.96 seconds
Started Aug 04 04:35:35 PM PDT 24
Finished Aug 04 04:35:36 PM PDT 24
Peak memory 197120 kb
Host smart-4e0a6053-318e-48e4-958d-7cb13cc4efa7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440075813 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.1440075813
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3605102163
Short name T508
Test name
Test status
Simulation time 85985102 ps
CPU time 0.58 seconds
Started Aug 04 04:35:40 PM PDT 24
Finished Aug 04 04:35:41 PM PDT 24
Peak memory 182804 kb
Host smart-1f0fb759-9034-490c-879a-2c5fdb59c38a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605102163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.3605102163
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.2872078395
Short name T560
Test name
Test status
Simulation time 170163043 ps
CPU time 0.52 seconds
Started Aug 04 04:35:34 PM PDT 24
Finished Aug 04 04:35:35 PM PDT 24
Peak memory 182108 kb
Host smart-04de4108-4313-4efd-a755-c4dc09c81e5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872078395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.2872078395
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.423312088
Short name T567
Test name
Test status
Simulation time 33154647 ps
CPU time 0.69 seconds
Started Aug 04 04:35:50 PM PDT 24
Finished Aug 04 04:35:51 PM PDT 24
Peak memory 193364 kb
Host smart-aa36ff1d-b90b-4c40-bfc1-e4cf5074b4f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423312088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_ti
mer_same_csr_outstanding.423312088
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.3627505748
Short name T481
Test name
Test status
Simulation time 293112525 ps
CPU time 1.28 seconds
Started Aug 04 04:35:42 PM PDT 24
Finished Aug 04 04:35:43 PM PDT 24
Peak memory 197348 kb
Host smart-ede83e8a-5660-4d3d-9bb8-77760251f745
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627505748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.3627505748
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.4173956685
Short name T562
Test name
Test status
Simulation time 54309927 ps
CPU time 0.74 seconds
Started Aug 04 04:35:49 PM PDT 24
Finished Aug 04 04:35:49 PM PDT 24
Peak memory 195248 kb
Host smart-f4f70b3c-3818-45fa-912e-d3a323f87ef3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173956685 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.4173956685
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3272489641
Short name T82
Test name
Test status
Simulation time 11606890 ps
CPU time 0.54 seconds
Started Aug 04 04:35:52 PM PDT 24
Finished Aug 04 04:35:58 PM PDT 24
Peak memory 182796 kb
Host smart-79fde2c5-fccd-4ab0-aec3-c496988a941e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272489641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.3272489641
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.3111731874
Short name T504
Test name
Test status
Simulation time 214573673 ps
CPU time 0.58 seconds
Started Aug 04 04:35:51 PM PDT 24
Finished Aug 04 04:35:51 PM PDT 24
Peak memory 182628 kb
Host smart-f557f135-94ea-4649-935a-e7f9a7630a0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111731874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.3111731874
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.3459608524
Short name T493
Test name
Test status
Simulation time 96257349 ps
CPU time 0.55 seconds
Started Aug 04 04:35:44 PM PDT 24
Finished Aug 04 04:35:45 PM PDT 24
Peak memory 191692 kb
Host smart-5aa25bcf-805f-40eb-bd13-6b9699784ad2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459608524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.3459608524
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.1473666073
Short name T482
Test name
Test status
Simulation time 547978847 ps
CPU time 2.44 seconds
Started Aug 04 04:35:54 PM PDT 24
Finished Aug 04 04:35:56 PM PDT 24
Peak memory 197560 kb
Host smart-b2e851c6-b23b-4c39-a2a2-f7177a258914
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473666073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.1473666073
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.2063322904
Short name T30
Test name
Test status
Simulation time 431875543 ps
CPU time 0.83 seconds
Started Aug 04 04:35:40 PM PDT 24
Finished Aug 04 04:35:41 PM PDT 24
Peak memory 193596 kb
Host smart-a644da9e-b43a-4c11-ab25-481d395b9f08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063322904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.2063322904
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.3736702883
Short name T453
Test name
Test status
Simulation time 86796672 ps
CPU time 1.34 seconds
Started Aug 04 04:35:44 PM PDT 24
Finished Aug 04 04:35:46 PM PDT 24
Peak memory 197560 kb
Host smart-da2987de-fcd7-4ec9-acd6-8f1f8fb8fb33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736702883 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.3736702883
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.3757486780
Short name T78
Test name
Test status
Simulation time 43720948 ps
CPU time 0.57 seconds
Started Aug 04 04:35:45 PM PDT 24
Finished Aug 04 04:35:45 PM PDT 24
Peak memory 182796 kb
Host smart-81c657bf-94d7-4910-b1f1-960602450025
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757486780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.3757486780
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.1173287285
Short name T520
Test name
Test status
Simulation time 28518410 ps
CPU time 0.55 seconds
Started Aug 04 04:35:33 PM PDT 24
Finished Aug 04 04:35:34 PM PDT 24
Peak memory 182092 kb
Host smart-ecde9752-f380-47d3-81f7-c5623889af43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173287285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.1173287285
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.481754875
Short name T74
Test name
Test status
Simulation time 17748841 ps
CPU time 0.73 seconds
Started Aug 04 04:35:45 PM PDT 24
Finished Aug 04 04:35:45 PM PDT 24
Peak memory 191716 kb
Host smart-cd7bd43b-6409-49dd-99e3-343eb1262952
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481754875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_ti
mer_same_csr_outstanding.481754875
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.2248382622
Short name T571
Test name
Test status
Simulation time 151107581 ps
CPU time 1.92 seconds
Started Aug 04 04:35:44 PM PDT 24
Finished Aug 04 04:35:46 PM PDT 24
Peak memory 197536 kb
Host smart-3a93e65b-793e-4613-9da0-5ed8e4f4faf9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248382622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.2248382622
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1638795063
Short name T564
Test name
Test status
Simulation time 76016687 ps
CPU time 0.82 seconds
Started Aug 04 04:35:44 PM PDT 24
Finished Aug 04 04:35:45 PM PDT 24
Peak memory 194112 kb
Host smart-30d0e84c-e797-4d53-926f-0750a2d46040
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638795063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.1638795063
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.2749288111
Short name T33
Test name
Test status
Simulation time 65037860 ps
CPU time 0.92 seconds
Started Aug 04 04:35:34 PM PDT 24
Finished Aug 04 04:35:35 PM PDT 24
Peak memory 196960 kb
Host smart-9e4a5cf2-b143-4953-b758-c1da8d4a473b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749288111 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.2749288111
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.2031895644
Short name T531
Test name
Test status
Simulation time 13404416 ps
CPU time 0.57 seconds
Started Aug 04 04:35:46 PM PDT 24
Finished Aug 04 04:35:46 PM PDT 24
Peak memory 182816 kb
Host smart-10ced7ad-526c-47f9-8f93-faf3bd4ed98f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031895644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.2031895644
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.4034765096
Short name T464
Test name
Test status
Simulation time 38242232 ps
CPU time 0.54 seconds
Started Aug 04 04:35:42 PM PDT 24
Finished Aug 04 04:35:43 PM PDT 24
Peak memory 182644 kb
Host smart-af3eb144-6e1d-405f-9bef-2eecb57d53f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034765096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.4034765096
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.3965680419
Short name T533
Test name
Test status
Simulation time 36619852 ps
CPU time 0.8 seconds
Started Aug 04 04:35:50 PM PDT 24
Finished Aug 04 04:35:51 PM PDT 24
Peak memory 191004 kb
Host smart-afa4f234-33e8-4136-83a6-427f0cea11c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965680419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.3965680419
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.1659964001
Short name T52
Test name
Test status
Simulation time 1039916746 ps
CPU time 3.15 seconds
Started Aug 04 04:35:36 PM PDT 24
Finished Aug 04 04:35:40 PM PDT 24
Peak memory 197568 kb
Host smart-9b0110f4-9640-403c-b2d1-0f145c2b5566
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659964001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.1659964001
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.3697185388
Short name T107
Test name
Test status
Simulation time 69249575 ps
CPU time 1.06 seconds
Started Aug 04 04:35:45 PM PDT 24
Finished Aug 04 04:35:46 PM PDT 24
Peak memory 182956 kb
Host smart-8b7c400f-8c42-4abe-810b-1271b240405c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697185388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.3697185388
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.1733208299
Short name T53
Test name
Test status
Simulation time 107928645 ps
CPU time 0.78 seconds
Started Aug 04 04:35:39 PM PDT 24
Finished Aug 04 04:35:40 PM PDT 24
Peak memory 196096 kb
Host smart-92a8992a-2f65-40a7-aa90-c26720fa4f75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733208299 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.1733208299
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.2525135162
Short name T523
Test name
Test status
Simulation time 36473270 ps
CPU time 0.51 seconds
Started Aug 04 04:35:54 PM PDT 24
Finished Aug 04 04:35:55 PM PDT 24
Peak memory 182604 kb
Host smart-617e4256-f4e5-49e3-8343-5811ee3eb367
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525135162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.2525135162
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3538159881
Short name T561
Test name
Test status
Simulation time 11001174 ps
CPU time 0.54 seconds
Started Aug 04 04:35:46 PM PDT 24
Finished Aug 04 04:35:47 PM PDT 24
Peak memory 182148 kb
Host smart-9914cfc3-ce69-4738-bab7-0324d20784fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538159881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.3538159881
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.515288885
Short name T547
Test name
Test status
Simulation time 24587374 ps
CPU time 0.59 seconds
Started Aug 04 04:35:52 PM PDT 24
Finished Aug 04 04:35:53 PM PDT 24
Peak memory 191732 kb
Host smart-a3e792d9-5427-4ef1-88b0-2ceeb29e85b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515288885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_ti
mer_same_csr_outstanding.515288885
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.2310100015
Short name T41
Test name
Test status
Simulation time 171720423 ps
CPU time 2.2 seconds
Started Aug 04 04:35:38 PM PDT 24
Finished Aug 04 04:35:41 PM PDT 24
Peak memory 197516 kb
Host smart-f8124f2b-85ed-4abd-a344-0a9eeaca16b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310100015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.2310100015
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.379884138
Short name T496
Test name
Test status
Simulation time 139829186 ps
CPU time 1.02 seconds
Started Aug 04 04:36:04 PM PDT 24
Finished Aug 04 04:36:05 PM PDT 24
Peak memory 195072 kb
Host smart-ca165eff-39a2-4d55-9bef-4d61e827179c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379884138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_in
tg_err.379884138
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.1981751967
Short name T488
Test name
Test status
Simulation time 24723036 ps
CPU time 0.76 seconds
Started Aug 04 04:36:02 PM PDT 24
Finished Aug 04 04:36:03 PM PDT 24
Peak memory 195608 kb
Host smart-a716da5c-2b13-4499-a7fc-c7feb8dc85be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981751967 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.1981751967
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.174472497
Short name T475
Test name
Test status
Simulation time 43801868 ps
CPU time 0.55 seconds
Started Aug 04 04:35:40 PM PDT 24
Finished Aug 04 04:35:41 PM PDT 24
Peak memory 182288 kb
Host smart-6b07054a-236b-446f-93cb-4832bce16ce0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174472497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.174472497
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.2418840515
Short name T56
Test name
Test status
Simulation time 100023780 ps
CPU time 0.7 seconds
Started Aug 04 04:35:44 PM PDT 24
Finished Aug 04 04:35:45 PM PDT 24
Peak memory 192348 kb
Host smart-1ee4d25a-1524-42dd-9890-aba06374b07f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418840515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.2418840515
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3664113234
Short name T558
Test name
Test status
Simulation time 259160393 ps
CPU time 1.87 seconds
Started Aug 04 04:35:56 PM PDT 24
Finished Aug 04 04:35:58 PM PDT 24
Peak memory 197616 kb
Host smart-b42b7ceb-ff34-4fe4-b0ce-e2c509bbfbe8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664113234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.3664113234
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.2577116747
Short name T103
Test name
Test status
Simulation time 42818380 ps
CPU time 0.8 seconds
Started Aug 04 04:35:47 PM PDT 24
Finished Aug 04 04:35:48 PM PDT 24
Peak memory 183132 kb
Host smart-d6ae00e9-edb4-4fcb-b620-97930c053480
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577116747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.2577116747
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3620023009
Short name T506
Test name
Test status
Simulation time 25544154 ps
CPU time 0.7 seconds
Started Aug 04 04:35:42 PM PDT 24
Finished Aug 04 04:35:43 PM PDT 24
Peak memory 194760 kb
Host smart-034b2d16-3563-425c-bb77-7cf39efc21fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620023009 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.3620023009
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.3048803254
Short name T88
Test name
Test status
Simulation time 14798038 ps
CPU time 0.54 seconds
Started Aug 04 04:35:45 PM PDT 24
Finished Aug 04 04:35:46 PM PDT 24
Peak memory 182484 kb
Host smart-e7d4072d-82df-4d20-a51d-a308b382e920
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048803254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.3048803254
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.695879661
Short name T569
Test name
Test status
Simulation time 67531735 ps
CPU time 0.54 seconds
Started Aug 04 04:36:02 PM PDT 24
Finished Aug 04 04:36:03 PM PDT 24
Peak memory 182056 kb
Host smart-b1e1ea2c-df03-4066-b211-a00d870e9241
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695879661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.695879661
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.670029399
Short name T91
Test name
Test status
Simulation time 21233175 ps
CPU time 0.76 seconds
Started Aug 04 04:35:51 PM PDT 24
Finished Aug 04 04:35:52 PM PDT 24
Peak memory 192060 kb
Host smart-2312a4fc-b88b-4b1f-973f-2e72edd767bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670029399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_ti
mer_same_csr_outstanding.670029399
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3352856127
Short name T490
Test name
Test status
Simulation time 151859500 ps
CPU time 1.93 seconds
Started Aug 04 04:35:38 PM PDT 24
Finished Aug 04 04:35:40 PM PDT 24
Peak memory 197552 kb
Host smart-ae4b1857-fb21-4dfd-b21d-b4e5d627e88c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352856127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.3352856127
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2655462363
Short name T548
Test name
Test status
Simulation time 116480677 ps
CPU time 1.37 seconds
Started Aug 04 04:35:46 PM PDT 24
Finished Aug 04 04:35:48 PM PDT 24
Peak memory 195432 kb
Host smart-92b8570b-becf-4c34-a489-a67baa986cc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655462363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.2655462363
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.2995217321
Short name T85
Test name
Test status
Simulation time 19942462 ps
CPU time 0.62 seconds
Started Aug 04 04:35:33 PM PDT 24
Finished Aug 04 04:35:34 PM PDT 24
Peak memory 191960 kb
Host smart-afb63f44-17cf-4ef5-a5fd-2ecde56c950e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995217321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.2995217321
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.301318246
Short name T513
Test name
Test status
Simulation time 195965073 ps
CPU time 1.41 seconds
Started Aug 04 04:35:26 PM PDT 24
Finished Aug 04 04:35:27 PM PDT 24
Peak memory 192212 kb
Host smart-3c16f652-98f3-4d46-b67b-df3456693ba4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301318246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_b
ash.301318246
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.3945386789
Short name T542
Test name
Test status
Simulation time 23036324 ps
CPU time 0.56 seconds
Started Aug 04 04:35:15 PM PDT 24
Finished Aug 04 04:35:15 PM PDT 24
Peak memory 182852 kb
Host smart-5668ae7a-bb15-4def-9e9d-1a6167376cfb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945386789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.3945386789
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.2388333583
Short name T570
Test name
Test status
Simulation time 59377499 ps
CPU time 0.77 seconds
Started Aug 04 04:35:29 PM PDT 24
Finished Aug 04 04:35:30 PM PDT 24
Peak memory 195572 kb
Host smart-04616674-a6fd-4d5b-a98d-6165808f8867
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388333583 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.2388333583
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.4062473093
Short name T75
Test name
Test status
Simulation time 29004534 ps
CPU time 0.61 seconds
Started Aug 04 04:35:34 PM PDT 24
Finished Aug 04 04:35:35 PM PDT 24
Peak memory 183096 kb
Host smart-6d86d2cc-8f54-44cc-a5e9-1b7aabd4912b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062473093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.4062473093
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.931929618
Short name T455
Test name
Test status
Simulation time 16018841 ps
CPU time 0.6 seconds
Started Aug 04 04:35:22 PM PDT 24
Finished Aug 04 04:35:23 PM PDT 24
Peak memory 182572 kb
Host smart-fe823cbe-6c71-4ab5-8433-802db3d765ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931929618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.931929618
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.2318234426
Short name T79
Test name
Test status
Simulation time 30973671 ps
CPU time 0.59 seconds
Started Aug 04 04:35:43 PM PDT 24
Finished Aug 04 04:35:44 PM PDT 24
Peak memory 192048 kb
Host smart-58ddd954-b031-40b6-8b76-06218a8ae698
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318234426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.2318234426
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.2835183050
Short name T528
Test name
Test status
Simulation time 36972411 ps
CPU time 0.98 seconds
Started Aug 04 04:35:26 PM PDT 24
Finished Aug 04 04:35:27 PM PDT 24
Peak memory 197348 kb
Host smart-c1c0db06-f275-462b-8a22-c6c29b203ba8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835183050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.2835183050
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.1192591991
Short name T559
Test name
Test status
Simulation time 167385326 ps
CPU time 0.86 seconds
Started Aug 04 04:35:14 PM PDT 24
Finished Aug 04 04:35:15 PM PDT 24
Peak memory 193728 kb
Host smart-a8731d9a-2393-460b-b276-2649ec866db5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192591991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.1192591991
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.288080166
Short name T470
Test name
Test status
Simulation time 38788618 ps
CPU time 0.55 seconds
Started Aug 04 04:35:49 PM PDT 24
Finished Aug 04 04:35:49 PM PDT 24
Peak memory 182508 kb
Host smart-0a09806b-9304-41d1-bb05-11f88a0046af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288080166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.288080166
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.3347721140
Short name T458
Test name
Test status
Simulation time 20390994 ps
CPU time 0.61 seconds
Started Aug 04 04:35:43 PM PDT 24
Finished Aug 04 04:35:44 PM PDT 24
Peak memory 182864 kb
Host smart-8599ec94-e407-466d-b4e4-358cd8f2a437
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347721140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.3347721140
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.240822456
Short name T521
Test name
Test status
Simulation time 19950875 ps
CPU time 0.56 seconds
Started Aug 04 04:35:49 PM PDT 24
Finished Aug 04 04:35:49 PM PDT 24
Peak memory 182580 kb
Host smart-280eec41-0e96-4de3-a37c-e29d582d2da3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240822456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.240822456
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.1532610936
Short name T467
Test name
Test status
Simulation time 117991613 ps
CPU time 0.56 seconds
Started Aug 04 04:35:42 PM PDT 24
Finished Aug 04 04:35:42 PM PDT 24
Peak memory 182704 kb
Host smart-87ce4618-33d2-4515-96fb-23e599094ca9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532610936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.1532610936
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.659092010
Short name T526
Test name
Test status
Simulation time 47368950 ps
CPU time 0.6 seconds
Started Aug 04 04:35:43 PM PDT 24
Finished Aug 04 04:35:44 PM PDT 24
Peak memory 182696 kb
Host smart-33a8a223-6a42-440d-abf2-2a6013bb7692
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659092010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.659092010
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.650599107
Short name T459
Test name
Test status
Simulation time 42389442 ps
CPU time 0.52 seconds
Started Aug 04 04:35:49 PM PDT 24
Finished Aug 04 04:35:49 PM PDT 24
Peak memory 182624 kb
Host smart-c5c9048b-51fb-4b6c-98cf-2f99b704bc69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650599107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.650599107
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1930822755
Short name T501
Test name
Test status
Simulation time 31235355 ps
CPU time 0.53 seconds
Started Aug 04 04:35:55 PM PDT 24
Finished Aug 04 04:35:55 PM PDT 24
Peak memory 182664 kb
Host smart-8d23890d-6404-443b-8ced-ff6ef7bd0ffe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930822755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.1930822755
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.378089920
Short name T491
Test name
Test status
Simulation time 95398591 ps
CPU time 0.55 seconds
Started Aug 04 04:35:47 PM PDT 24
Finished Aug 04 04:35:48 PM PDT 24
Peak memory 182080 kb
Host smart-1e469639-8fc8-4d17-b008-788502906532
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378089920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.378089920
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.3015019272
Short name T469
Test name
Test status
Simulation time 16334452 ps
CPU time 0.51 seconds
Started Aug 04 04:35:40 PM PDT 24
Finished Aug 04 04:35:41 PM PDT 24
Peak memory 182148 kb
Host smart-3a6fc8c5-faa0-43f5-bbad-45dbd97a77fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015019272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.3015019272
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.1081581366
Short name T514
Test name
Test status
Simulation time 64894594 ps
CPU time 0.54 seconds
Started Aug 04 04:35:53 PM PDT 24
Finished Aug 04 04:35:54 PM PDT 24
Peak memory 182588 kb
Host smart-a75c8451-d785-49e3-bf9b-503952d2da73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081581366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.1081581366
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.2029774591
Short name T553
Test name
Test status
Simulation time 284126284 ps
CPU time 0.83 seconds
Started Aug 04 04:35:40 PM PDT 24
Finished Aug 04 04:35:41 PM PDT 24
Peak memory 192752 kb
Host smart-d9ac3f3b-3d53-4b0b-b094-9891670ff401
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029774591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.2029774591
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.428765998
Short name T465
Test name
Test status
Simulation time 36194648 ps
CPU time 1.42 seconds
Started Aug 04 04:35:21 PM PDT 24
Finished Aug 04 04:35:22 PM PDT 24
Peak memory 182920 kb
Host smart-0eeb3567-c269-40b5-be92-3fe60d8f2503
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428765998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_b
ash.428765998
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.2995141446
Short name T461
Test name
Test status
Simulation time 40110568 ps
CPU time 0.61 seconds
Started Aug 04 04:35:34 PM PDT 24
Finished Aug 04 04:35:35 PM PDT 24
Peak memory 182836 kb
Host smart-10454aef-c3bb-409b-be2d-fc885a91aa87
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995141446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.2995141446
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.500950013
Short name T507
Test name
Test status
Simulation time 187032007 ps
CPU time 0.85 seconds
Started Aug 04 04:35:32 PM PDT 24
Finished Aug 04 04:35:32 PM PDT 24
Peak memory 197408 kb
Host smart-5b03f363-8732-48d9-ac6f-f6f11bd03ac4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500950013 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.500950013
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.3318554238
Short name T32
Test name
Test status
Simulation time 40799213 ps
CPU time 0.53 seconds
Started Aug 04 04:35:23 PM PDT 24
Finished Aug 04 04:35:24 PM PDT 24
Peak memory 182808 kb
Host smart-64c1e1c8-b413-4dfd-a303-8413f7027ed9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318554238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.3318554238
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.2917456230
Short name T512
Test name
Test status
Simulation time 15887211 ps
CPU time 0.54 seconds
Started Aug 04 04:35:15 PM PDT 24
Finished Aug 04 04:35:16 PM PDT 24
Peak memory 182644 kb
Host smart-56ca1ffc-5cd4-4e4a-bd51-fb543373b92e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917456230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.2917456230
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.2004898471
Short name T502
Test name
Test status
Simulation time 76457234 ps
CPU time 0.62 seconds
Started Aug 04 04:35:34 PM PDT 24
Finished Aug 04 04:35:35 PM PDT 24
Peak memory 191472 kb
Host smart-90fcae6f-a2ef-4f2e-a647-1c8a7ebad73e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004898471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.2004898471
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3414471336
Short name T42
Test name
Test status
Simulation time 567994488 ps
CPU time 2.18 seconds
Started Aug 04 04:35:31 PM PDT 24
Finished Aug 04 04:35:34 PM PDT 24
Peak memory 191236 kb
Host smart-9f7d8723-4b70-4a88-9809-99b0045d3db5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414471336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.3414471336
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.2678121484
Short name T534
Test name
Test status
Simulation time 83487270 ps
CPU time 0.87 seconds
Started Aug 04 04:35:38 PM PDT 24
Finished Aug 04 04:35:44 PM PDT 24
Peak memory 183496 kb
Host smart-654516af-4ef3-4900-a378-e2efc1c2d4f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678121484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.2678121484
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.97548038
Short name T498
Test name
Test status
Simulation time 23698325 ps
CPU time 0.54 seconds
Started Aug 04 04:36:13 PM PDT 24
Finished Aug 04 04:36:14 PM PDT 24
Peak memory 182544 kb
Host smart-f5a2f830-b6fa-405b-863e-1a58a5fbcab8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97548038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.97548038
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.2596267354
Short name T476
Test name
Test status
Simulation time 17770825 ps
CPU time 0.56 seconds
Started Aug 04 04:35:41 PM PDT 24
Finished Aug 04 04:35:42 PM PDT 24
Peak memory 182564 kb
Host smart-05fe7ee8-88b8-4cce-a429-42de707232f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596267354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.2596267354
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.930434162
Short name T489
Test name
Test status
Simulation time 29331037 ps
CPU time 0.53 seconds
Started Aug 04 04:35:52 PM PDT 24
Finished Aug 04 04:35:53 PM PDT 24
Peak memory 182628 kb
Host smart-8a9c5bcb-36ac-4bb6-833c-494ae6334f60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930434162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.930434162
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1528706473
Short name T554
Test name
Test status
Simulation time 15585967 ps
CPU time 0.51 seconds
Started Aug 04 04:35:53 PM PDT 24
Finished Aug 04 04:35:53 PM PDT 24
Peak memory 182092 kb
Host smart-d1a8735d-f04b-450a-92f3-bb42c454216d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528706473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.1528706473
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.800042574
Short name T574
Test name
Test status
Simulation time 36077205 ps
CPU time 0.57 seconds
Started Aug 04 04:35:55 PM PDT 24
Finished Aug 04 04:35:55 PM PDT 24
Peak memory 182640 kb
Host smart-7dca585c-fd53-497a-bd55-5761f9961035
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800042574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.800042574
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.941685043
Short name T535
Test name
Test status
Simulation time 50785883 ps
CPU time 0.52 seconds
Started Aug 04 04:35:52 PM PDT 24
Finished Aug 04 04:35:53 PM PDT 24
Peak memory 182064 kb
Host smart-14376438-f44e-4feb-9bf0-cb2c41fa9c7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941685043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.941685043
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.367159875
Short name T515
Test name
Test status
Simulation time 29428082 ps
CPU time 0.53 seconds
Started Aug 04 04:35:41 PM PDT 24
Finished Aug 04 04:35:42 PM PDT 24
Peak memory 182116 kb
Host smart-7f18302c-349c-41c7-9ffa-3fd255c9ddcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367159875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.367159875
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.1188873194
Short name T473
Test name
Test status
Simulation time 15133497 ps
CPU time 0.54 seconds
Started Aug 04 04:35:53 PM PDT 24
Finished Aug 04 04:35:53 PM PDT 24
Peak memory 182576 kb
Host smart-3c440f19-d018-4607-9d94-069e2c9d55e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188873194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.1188873194
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.1886255327
Short name T474
Test name
Test status
Simulation time 13481908 ps
CPU time 0.57 seconds
Started Aug 04 04:35:41 PM PDT 24
Finished Aug 04 04:35:41 PM PDT 24
Peak memory 182252 kb
Host smart-e34971be-8f1f-4027-9353-26ba43a30798
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886255327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.1886255327
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.116058184
Short name T484
Test name
Test status
Simulation time 55031742 ps
CPU time 0.56 seconds
Started Aug 04 04:35:47 PM PDT 24
Finished Aug 04 04:35:47 PM PDT 24
Peak memory 182556 kb
Host smart-787bd4a6-777e-4a54-b5b2-2641d9b27689
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116058184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.116058184
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1651701593
Short name T76
Test name
Test status
Simulation time 259421655 ps
CPU time 0.8 seconds
Started Aug 04 04:35:34 PM PDT 24
Finished Aug 04 04:35:35 PM PDT 24
Peak memory 190972 kb
Host smart-1191ea2f-5902-43b2-aa2b-f2be8f0cf565
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651701593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.1651701593
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.2392473310
Short name T544
Test name
Test status
Simulation time 1138197661 ps
CPU time 3.57 seconds
Started Aug 04 04:35:17 PM PDT 24
Finished Aug 04 04:35:21 PM PDT 24
Peak memory 194172 kb
Host smart-237ef541-6a9b-45f8-ae99-bc2e07c953c6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392473310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.2392473310
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.4228409827
Short name T463
Test name
Test status
Simulation time 12203979 ps
CPU time 0.54 seconds
Started Aug 04 04:35:30 PM PDT 24
Finished Aug 04 04:35:31 PM PDT 24
Peak memory 182740 kb
Host smart-bda8d5e0-132f-47ed-9e5d-39e26cc3f78d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228409827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.4228409827
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.2500263866
Short name T460
Test name
Test status
Simulation time 65754900 ps
CPU time 1.47 seconds
Started Aug 04 04:35:53 PM PDT 24
Finished Aug 04 04:35:54 PM PDT 24
Peak memory 197576 kb
Host smart-467d3691-b96f-4926-9754-5b3cabd951d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500263866 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.2500263866
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.745777547
Short name T87
Test name
Test status
Simulation time 41322498 ps
CPU time 0.53 seconds
Started Aug 04 04:35:26 PM PDT 24
Finished Aug 04 04:35:27 PM PDT 24
Peak memory 182448 kb
Host smart-59316d82-38c2-4ad2-9143-16139ff26c0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745777547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.745777547
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.1436043949
Short name T478
Test name
Test status
Simulation time 41352901 ps
CPU time 0.54 seconds
Started Aug 04 04:35:12 PM PDT 24
Finished Aug 04 04:35:12 PM PDT 24
Peak memory 182388 kb
Host smart-2fb2f4b0-77b5-4643-a988-aaef13dba533
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436043949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.1436043949
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.2759938148
Short name T551
Test name
Test status
Simulation time 21963097 ps
CPU time 0.65 seconds
Started Aug 04 04:35:36 PM PDT 24
Finished Aug 04 04:35:37 PM PDT 24
Peak memory 192164 kb
Host smart-9bb5581f-e5d4-4a9d-9522-ad0e52a72dee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759938148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.2759938148
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.3364212407
Short name T497
Test name
Test status
Simulation time 481521368 ps
CPU time 2.16 seconds
Started Aug 04 04:35:29 PM PDT 24
Finished Aug 04 04:35:31 PM PDT 24
Peak memory 197532 kb
Host smart-2b0c732e-7a73-488c-82cf-ce74c477a22a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364212407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.3364212407
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.4182094208
Short name T557
Test name
Test status
Simulation time 110524306 ps
CPU time 1.08 seconds
Started Aug 04 04:35:21 PM PDT 24
Finished Aug 04 04:35:23 PM PDT 24
Peak memory 195188 kb
Host smart-da38a6ea-b18a-4795-8dfd-b6e59f407b25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182094208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.4182094208
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.2575909255
Short name T556
Test name
Test status
Simulation time 18945278 ps
CPU time 0.58 seconds
Started Aug 04 04:35:46 PM PDT 24
Finished Aug 04 04:35:46 PM PDT 24
Peak memory 182636 kb
Host smart-7156d0d8-501b-4ca2-9396-fcea8a1df18b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575909255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.2575909255
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.1278345830
Short name T555
Test name
Test status
Simulation time 42295547 ps
CPU time 0.53 seconds
Started Aug 04 04:35:52 PM PDT 24
Finished Aug 04 04:35:53 PM PDT 24
Peak memory 182524 kb
Host smart-42b909fd-ba5f-4ea2-9b41-2c856319a43c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278345830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.1278345830
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1836365710
Short name T519
Test name
Test status
Simulation time 53279626 ps
CPU time 0.54 seconds
Started Aug 04 04:35:44 PM PDT 24
Finished Aug 04 04:35:44 PM PDT 24
Peak memory 182540 kb
Host smart-59ac4c70-4d5b-4a20-9b4d-b95a088a3046
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836365710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.1836365710
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.3501971289
Short name T466
Test name
Test status
Simulation time 130896067 ps
CPU time 0.53 seconds
Started Aug 04 04:35:44 PM PDT 24
Finished Aug 04 04:35:45 PM PDT 24
Peak memory 182048 kb
Host smart-7cba749a-3d2e-4757-ba6d-d25ab6f624e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501971289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.3501971289
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.1588161941
Short name T479
Test name
Test status
Simulation time 32725349 ps
CPU time 0.53 seconds
Started Aug 04 04:35:46 PM PDT 24
Finished Aug 04 04:35:47 PM PDT 24
Peak memory 182636 kb
Host smart-e4269568-e87d-4274-b3ad-73e57dc4fe5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588161941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.1588161941
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.3035034074
Short name T516
Test name
Test status
Simulation time 11611368 ps
CPU time 0.58 seconds
Started Aug 04 04:35:50 PM PDT 24
Finished Aug 04 04:35:51 PM PDT 24
Peak memory 182068 kb
Host smart-9d0f2386-7398-44e7-9657-ba27e927e394
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035034074 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.3035034074
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.1232339558
Short name T485
Test name
Test status
Simulation time 57101759 ps
CPU time 0.53 seconds
Started Aug 04 04:35:45 PM PDT 24
Finished Aug 04 04:35:46 PM PDT 24
Peak memory 182048 kb
Host smart-a391f032-6555-4ed8-9bb1-4da0d589f9d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232339558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.1232339558
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2451038877
Short name T563
Test name
Test status
Simulation time 16618511 ps
CPU time 0.57 seconds
Started Aug 04 04:35:53 PM PDT 24
Finished Aug 04 04:35:53 PM PDT 24
Peak memory 182600 kb
Host smart-d962332a-e42b-420b-a0d8-2d655cfbf590
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451038877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.2451038877
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.1704072194
Short name T540
Test name
Test status
Simulation time 11911359 ps
CPU time 0.51 seconds
Started Aug 04 04:35:43 PM PDT 24
Finished Aug 04 04:35:44 PM PDT 24
Peak memory 182068 kb
Host smart-8e3ccf6c-ec2e-4cd6-a015-931905ce51e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704072194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.1704072194
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.1801731299
Short name T525
Test name
Test status
Simulation time 20711820 ps
CPU time 0.52 seconds
Started Aug 04 04:35:49 PM PDT 24
Finished Aug 04 04:35:49 PM PDT 24
Peak memory 182288 kb
Host smart-0646290f-e270-4dc1-89e8-0bd15f62ad45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801731299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.1801731299
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.655282371
Short name T486
Test name
Test status
Simulation time 28350853 ps
CPU time 0.74 seconds
Started Aug 04 04:35:34 PM PDT 24
Finished Aug 04 04:35:34 PM PDT 24
Peak memory 194924 kb
Host smart-2cae2297-da91-4977-bd07-a5bd8690e521
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655282371 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.655282371
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.506483466
Short name T83
Test name
Test status
Simulation time 10858152 ps
CPU time 0.54 seconds
Started Aug 04 04:35:30 PM PDT 24
Finished Aug 04 04:35:31 PM PDT 24
Peak memory 182512 kb
Host smart-45cfee44-4cf6-4228-8e3b-bb0bf1bf38a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506483466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.506483466
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.3454111475
Short name T536
Test name
Test status
Simulation time 25035340 ps
CPU time 0.56 seconds
Started Aug 04 04:35:44 PM PDT 24
Finished Aug 04 04:35:44 PM PDT 24
Peak memory 182784 kb
Host smart-5ded471d-76c3-4b88-8523-fb6dd5329481
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454111475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.3454111475
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.3750322357
Short name T89
Test name
Test status
Simulation time 66317404 ps
CPU time 0.65 seconds
Started Aug 04 04:35:33 PM PDT 24
Finished Aug 04 04:35:34 PM PDT 24
Peak memory 192080 kb
Host smart-25da512e-fc11-41fc-b687-171a8944bf9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750322357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.3750322357
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.1247722153
Short name T549
Test name
Test status
Simulation time 26859615 ps
CPU time 1.15 seconds
Started Aug 04 04:35:46 PM PDT 24
Finished Aug 04 04:35:47 PM PDT 24
Peak memory 197568 kb
Host smart-37dbf669-b3ed-4e31-afd6-d8998f752ada
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247722153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.1247722153
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3238888288
Short name T471
Test name
Test status
Simulation time 40067082 ps
CPU time 0.81 seconds
Started Aug 04 04:35:44 PM PDT 24
Finished Aug 04 04:35:44 PM PDT 24
Peak memory 192880 kb
Host smart-718438bc-83d5-4081-9ee4-789aadf67b39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238888288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.3238888288
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.695593594
Short name T510
Test name
Test status
Simulation time 622144721 ps
CPU time 1.42 seconds
Started Aug 04 04:35:36 PM PDT 24
Finished Aug 04 04:35:38 PM PDT 24
Peak memory 197720 kb
Host smart-e498519f-a10c-4825-9d28-d52ab09e836b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695593594 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.695593594
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.129818892
Short name T480
Test name
Test status
Simulation time 42589457 ps
CPU time 0.54 seconds
Started Aug 04 04:35:29 PM PDT 24
Finished Aug 04 04:35:30 PM PDT 24
Peak memory 182488 kb
Host smart-3975fe36-0654-4dd1-b502-8145518aedd4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129818892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.129818892
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.1804613853
Short name T538
Test name
Test status
Simulation time 11496673 ps
CPU time 0.54 seconds
Started Aug 04 04:35:44 PM PDT 24
Finished Aug 04 04:35:45 PM PDT 24
Peak memory 182564 kb
Host smart-096c58bf-1d6f-4a15-aa4b-29aabedb7074
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804613853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.1804613853
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.1864137083
Short name T90
Test name
Test status
Simulation time 72645773 ps
CPU time 0.79 seconds
Started Aug 04 04:35:47 PM PDT 24
Finished Aug 04 04:35:48 PM PDT 24
Peak memory 191156 kb
Host smart-45b94d6e-1ae1-4416-b1a9-a6176d1b63b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864137083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.1864137083
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.2245762657
Short name T58
Test name
Test status
Simulation time 604537782 ps
CPU time 2.51 seconds
Started Aug 04 04:35:30 PM PDT 24
Finished Aug 04 04:35:33 PM PDT 24
Peak memory 197564 kb
Host smart-4f9fbba3-2ed3-442a-99f0-5577bc456a0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245762657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.2245762657
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.2929592186
Short name T529
Test name
Test status
Simulation time 132182173 ps
CPU time 0.79 seconds
Started Aug 04 04:35:45 PM PDT 24
Finished Aug 04 04:35:46 PM PDT 24
Peak memory 193904 kb
Host smart-d5511c36-c9d3-4f35-8529-d3c12aedf981
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929592186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.2929592186
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2088896438
Short name T456
Test name
Test status
Simulation time 54112247 ps
CPU time 0.8 seconds
Started Aug 04 04:35:39 PM PDT 24
Finished Aug 04 04:35:40 PM PDT 24
Peak memory 195380 kb
Host smart-a2058de0-b423-4c6c-96f4-37f030af9326
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088896438 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.2088896438
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.1801212387
Short name T57
Test name
Test status
Simulation time 14647612 ps
CPU time 0.59 seconds
Started Aug 04 04:35:41 PM PDT 24
Finished Aug 04 04:35:42 PM PDT 24
Peak memory 182928 kb
Host smart-c197aa4e-b508-493c-b341-a664454e0897
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801212387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.1801212387
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.1195520831
Short name T527
Test name
Test status
Simulation time 63031292 ps
CPU time 0.58 seconds
Started Aug 04 04:35:45 PM PDT 24
Finished Aug 04 04:35:46 PM PDT 24
Peak memory 182720 kb
Host smart-063ec14d-2b8f-4ef3-b134-a46728076669
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195520831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.1195520831
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.2734602898
Short name T492
Test name
Test status
Simulation time 44571458 ps
CPU time 0.69 seconds
Started Aug 04 04:35:37 PM PDT 24
Finished Aug 04 04:35:38 PM PDT 24
Peak memory 191896 kb
Host smart-a25d8255-a691-413d-9482-46f8b03289d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734602898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.2734602898
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.3056895025
Short name T537
Test name
Test status
Simulation time 28371105 ps
CPU time 1.19 seconds
Started Aug 04 04:35:34 PM PDT 24
Finished Aug 04 04:35:36 PM PDT 24
Peak memory 197508 kb
Host smart-0b388641-f168-4928-99b3-341169d4b518
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056895025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.3056895025
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.3382325954
Short name T503
Test name
Test status
Simulation time 591524114 ps
CPU time 1.32 seconds
Started Aug 04 04:35:27 PM PDT 24
Finished Aug 04 04:35:28 PM PDT 24
Peak memory 183580 kb
Host smart-4a039ca6-6585-4f49-9430-fea6f1f3865f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382325954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.3382325954
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.145984498
Short name T552
Test name
Test status
Simulation time 47438657 ps
CPU time 0.68 seconds
Started Aug 04 04:35:38 PM PDT 24
Finished Aug 04 04:35:39 PM PDT 24
Peak memory 195224 kb
Host smart-739d0b34-1ec8-48c1-bc20-a7c2f1a69158
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145984498 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.145984498
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.3737297533
Short name T84
Test name
Test status
Simulation time 42338049 ps
CPU time 0.54 seconds
Started Aug 04 04:35:41 PM PDT 24
Finished Aug 04 04:35:41 PM PDT 24
Peak memory 182448 kb
Host smart-c5e8abc1-4bda-4e8a-9f74-d516f361f44f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737297533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.3737297533
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.3286283575
Short name T543
Test name
Test status
Simulation time 22692223 ps
CPU time 0.58 seconds
Started Aug 04 04:35:33 PM PDT 24
Finished Aug 04 04:35:33 PM PDT 24
Peak memory 182632 kb
Host smart-0d70c693-61f3-4649-ad8c-ee3f6ef98324
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286283575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.3286283575
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.112849503
Short name T59
Test name
Test status
Simulation time 63180327 ps
CPU time 0.58 seconds
Started Aug 04 04:35:39 PM PDT 24
Finished Aug 04 04:35:39 PM PDT 24
Peak memory 191568 kb
Host smart-301b76eb-4447-4eac-8709-f0cb8c225446
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112849503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_tim
er_same_csr_outstanding.112849503
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3139297995
Short name T511
Test name
Test status
Simulation time 24324434 ps
CPU time 1.27 seconds
Started Aug 04 04:35:39 PM PDT 24
Finished Aug 04 04:35:41 PM PDT 24
Peak memory 197536 kb
Host smart-c552856c-c444-4f6a-89ed-033a5b781e7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139297995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.3139297995
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.3871564163
Short name T105
Test name
Test status
Simulation time 140553368 ps
CPU time 0.84 seconds
Started Aug 04 04:35:42 PM PDT 24
Finished Aug 04 04:35:43 PM PDT 24
Peak memory 193144 kb
Host smart-bdc4ecbc-1b98-4253-a3d9-bf5c1ff31fc9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871564163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.3871564163
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.2999485702
Short name T550
Test name
Test status
Simulation time 32824578 ps
CPU time 0.82 seconds
Started Aug 04 04:35:31 PM PDT 24
Finished Aug 04 04:35:32 PM PDT 24
Peak memory 196716 kb
Host smart-adb1d90a-caa3-4338-95a5-fd0aa7460e95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999485702 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.2999485702
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.1127565378
Short name T77
Test name
Test status
Simulation time 39956712 ps
CPU time 0.53 seconds
Started Aug 04 04:35:55 PM PDT 24
Finished Aug 04 04:35:56 PM PDT 24
Peak memory 182768 kb
Host smart-1c4d2dcf-e418-4696-b76f-2e4328a88e26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127565378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.1127565378
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.3699175266
Short name T505
Test name
Test status
Simulation time 14044188 ps
CPU time 0.53 seconds
Started Aug 04 04:35:39 PM PDT 24
Finished Aug 04 04:35:40 PM PDT 24
Peak memory 182132 kb
Host smart-539bc63d-3b5b-423e-9f6d-1e23ddcfd2c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699175266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.3699175266
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.235955186
Short name T499
Test name
Test status
Simulation time 140377759 ps
CPU time 0.88 seconds
Started Aug 04 04:35:47 PM PDT 24
Finished Aug 04 04:35:48 PM PDT 24
Peak memory 193596 kb
Host smart-e9e353a9-f002-4587-9c55-50aded13ec01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235955186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_tim
er_same_csr_outstanding.235955186
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.696416152
Short name T483
Test name
Test status
Simulation time 89857345 ps
CPU time 1.13 seconds
Started Aug 04 04:35:51 PM PDT 24
Finished Aug 04 04:35:52 PM PDT 24
Peak memory 196628 kb
Host smart-9624ae42-ff2b-43e8-89af-dd1f478fbf10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696416152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.696416152
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.4045701608
Short name T532
Test name
Test status
Simulation time 91422033 ps
CPU time 1.14 seconds
Started Aug 04 04:35:45 PM PDT 24
Finished Aug 04 04:35:47 PM PDT 24
Peak memory 183616 kb
Host smart-fdb9f687-c03f-4302-8d36-c339912203be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045701608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.4045701608
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.3722501037
Short name T133
Test name
Test status
Simulation time 13676776520 ps
CPU time 15.49 seconds
Started Aug 04 04:41:11 PM PDT 24
Finished Aug 04 04:41:27 PM PDT 24
Peak memory 183372 kb
Host smart-4c51996d-0e16-4af1-9b6a-ddc7c7ca947f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722501037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.3722501037
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.3275645674
Short name T392
Test name
Test status
Simulation time 196117780076 ps
CPU time 82.19 seconds
Started Aug 04 04:41:04 PM PDT 24
Finished Aug 04 04:42:26 PM PDT 24
Peak memory 183360 kb
Host smart-18e0a725-d867-4bda-a296-86e7e78b7461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275645674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.3275645674
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.1587463407
Short name T285
Test name
Test status
Simulation time 811682936238 ps
CPU time 1066.57 seconds
Started Aug 04 04:41:10 PM PDT 24
Finished Aug 04 04:58:57 PM PDT 24
Peak memory 191592 kb
Host smart-43ce2b3a-3db5-4d8e-a1a7-a9ce23417301
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587463407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.1587463407
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.1162453188
Short name T212
Test name
Test status
Simulation time 111325336050 ps
CPU time 192.03 seconds
Started Aug 04 04:41:14 PM PDT 24
Finished Aug 04 04:44:26 PM PDT 24
Peak memory 183304 kb
Host smart-592067c2-4a8b-4284-8c4a-c472d8069fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162453188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.1162453188
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.2954385457
Short name T197
Test name
Test status
Simulation time 198875759559 ps
CPU time 239.8 seconds
Started Aug 04 04:41:11 PM PDT 24
Finished Aug 04 04:45:11 PM PDT 24
Peak memory 183344 kb
Host smart-7478f486-32cf-42ba-b351-551ceedc5e20
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954385457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.2954385457
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.2786148372
Short name T399
Test name
Test status
Simulation time 141667839870 ps
CPU time 52.83 seconds
Started Aug 04 04:41:04 PM PDT 24
Finished Aug 04 04:41:57 PM PDT 24
Peak memory 183360 kb
Host smart-015edc2c-44cb-4307-94f1-b657bad88235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786148372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.2786148372
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.1558864345
Short name T325
Test name
Test status
Simulation time 118508542450 ps
CPU time 210.9 seconds
Started Aug 04 04:41:12 PM PDT 24
Finished Aug 04 04:44:43 PM PDT 24
Peak memory 191488 kb
Host smart-b32955f7-51a8-44e1-8aaf-510c9b3053ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558864345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.1558864345
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.3162946981
Short name T256
Test name
Test status
Simulation time 81061128286 ps
CPU time 140.06 seconds
Started Aug 04 04:41:07 PM PDT 24
Finished Aug 04 04:43:28 PM PDT 24
Peak memory 191648 kb
Host smart-db1f1643-1200-406b-bb14-02c021fd2d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162946981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.3162946981
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.1991175168
Short name T17
Test name
Test status
Simulation time 36393652 ps
CPU time 0.77 seconds
Started Aug 04 04:41:16 PM PDT 24
Finished Aug 04 04:41:17 PM PDT 24
Peak memory 213992 kb
Host smart-4df57929-9396-416e-bb24-65605da4304b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991175168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.1991175168
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.3443202906
Short name T243
Test name
Test status
Simulation time 423438240047 ps
CPU time 210.53 seconds
Started Aug 04 04:41:14 PM PDT 24
Finished Aug 04 04:44:45 PM PDT 24
Peak memory 183384 kb
Host smart-c649f893-7c39-4533-b317-874ecc22e211
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443202906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.3443202906
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.1279763847
Short name T391
Test name
Test status
Simulation time 73683493492 ps
CPU time 107.02 seconds
Started Aug 04 04:41:11 PM PDT 24
Finished Aug 04 04:42:58 PM PDT 24
Peak memory 183360 kb
Host smart-e2f1f8f2-ad0b-4b6b-bf28-3aaa24d3558c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279763847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.1279763847
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.929163436
Short name T396
Test name
Test status
Simulation time 30250320958 ps
CPU time 27.72 seconds
Started Aug 04 04:41:13 PM PDT 24
Finished Aug 04 04:41:41 PM PDT 24
Peak memory 191480 kb
Host smart-3bcd3ea1-a504-4407-b7b1-88a312765200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929163436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.929163436
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.1816051765
Short name T413
Test name
Test status
Simulation time 726348362972 ps
CPU time 198.84 seconds
Started Aug 04 04:41:09 PM PDT 24
Finished Aug 04 04:44:28 PM PDT 24
Peak memory 183272 kb
Host smart-dc7b1437-6572-4b9b-b36c-da7c646226f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816051765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.1816051765
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/100.rv_timer_random.2191035696
Short name T25
Test name
Test status
Simulation time 286424137125 ps
CPU time 217.77 seconds
Started Aug 04 04:42:03 PM PDT 24
Finished Aug 04 04:45:41 PM PDT 24
Peak memory 191516 kb
Host smart-11f7200b-9a26-4b29-bcbf-37b3c28de37a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191035696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.2191035696
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.3798487194
Short name T221
Test name
Test status
Simulation time 448361167128 ps
CPU time 334.11 seconds
Started Aug 04 04:41:59 PM PDT 24
Finished Aug 04 04:47:34 PM PDT 24
Peak memory 191676 kb
Host smart-919f4c78-c27d-4810-8834-04ab50b04565
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798487194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.3798487194
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.3967741546
Short name T387
Test name
Test status
Simulation time 110436558838 ps
CPU time 74.22 seconds
Started Aug 04 04:41:59 PM PDT 24
Finished Aug 04 04:43:14 PM PDT 24
Peak memory 183384 kb
Host smart-2332495f-0c6c-4f57-b6fd-a02f29326578
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967741546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.3967741546
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.2753789065
Short name T199
Test name
Test status
Simulation time 561273347243 ps
CPU time 392.53 seconds
Started Aug 04 04:42:01 PM PDT 24
Finished Aug 04 04:48:33 PM PDT 24
Peak memory 191464 kb
Host smart-88f88e73-eaee-4004-b7bf-fddd2abf86b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753789065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.2753789065
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.3008127158
Short name T252
Test name
Test status
Simulation time 5858104652 ps
CPU time 52.45 seconds
Started Aug 04 04:42:00 PM PDT 24
Finished Aug 04 04:42:53 PM PDT 24
Peak memory 183376 kb
Host smart-f41263e9-ff5f-4b1e-a9ca-e8cae921f453
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008127158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.3008127158
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random.3396750973
Short name T266
Test name
Test status
Simulation time 816347054887 ps
CPU time 278.96 seconds
Started Aug 04 04:41:08 PM PDT 24
Finished Aug 04 04:45:47 PM PDT 24
Peak memory 195248 kb
Host smart-32d6f947-67f4-4fb0-a19b-eeff61da5951
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396750973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.3396750973
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.450920034
Short name T123
Test name
Test status
Simulation time 167549197204 ps
CPU time 94.34 seconds
Started Aug 04 04:41:04 PM PDT 24
Finished Aug 04 04:42:39 PM PDT 24
Peak memory 183660 kb
Host smart-c811a312-80e6-45d2-8140-7370de6eac3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450920034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.450920034
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.2032207657
Short name T298
Test name
Test status
Simulation time 4040797345955 ps
CPU time 1163.22 seconds
Started Aug 04 04:41:06 PM PDT 24
Finished Aug 04 05:00:29 PM PDT 24
Peak memory 191564 kb
Host smart-c8349ddf-b6d1-46ca-a2b9-abf17a6fb963
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032207657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.2032207657
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all_with_rand_reset.4218253519
Short name T39
Test name
Test status
Simulation time 55739020515 ps
CPU time 643.38 seconds
Started Aug 04 04:41:15 PM PDT 24
Finished Aug 04 04:51:58 PM PDT 24
Peak memory 206284 kb
Host smart-b39f84b5-773e-4b60-b81b-7e7f836fbd85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218253519 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all_with_rand_reset.4218253519
Directory /workspace/11.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.rv_timer_random.1102128607
Short name T359
Test name
Test status
Simulation time 51985611940 ps
CPU time 81.4 seconds
Started Aug 04 04:42:02 PM PDT 24
Finished Aug 04 04:43:24 PM PDT 24
Peak memory 191556 kb
Host smart-73fed106-e30f-4d7c-a9ad-bece321ca239
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102128607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.1102128607
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.2393714136
Short name T249
Test name
Test status
Simulation time 33983208518 ps
CPU time 50.72 seconds
Started Aug 04 04:42:02 PM PDT 24
Finished Aug 04 04:42:53 PM PDT 24
Peak memory 191556 kb
Host smart-2e7ae71d-c173-4c6a-bb1a-b83ba1b7c2cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393714136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.2393714136
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.1099877759
Short name T257
Test name
Test status
Simulation time 1360632410927 ps
CPU time 1497 seconds
Started Aug 04 04:42:01 PM PDT 24
Finished Aug 04 05:06:58 PM PDT 24
Peak memory 191544 kb
Host smart-8a1a7918-b5ac-41d9-af28-f5f00d740b82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099877759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.1099877759
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.3248673684
Short name T170
Test name
Test status
Simulation time 12770435330 ps
CPU time 26.6 seconds
Started Aug 04 04:42:00 PM PDT 24
Finished Aug 04 04:42:26 PM PDT 24
Peak memory 183348 kb
Host smart-5006e4d6-b014-4236-971e-ffc0ccc43d12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248673684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.3248673684
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.1500903101
Short name T255
Test name
Test status
Simulation time 180791043053 ps
CPU time 338.89 seconds
Started Aug 04 04:42:05 PM PDT 24
Finished Aug 04 04:47:44 PM PDT 24
Peak memory 191564 kb
Host smart-64abb1dd-55ce-4883-b4f5-3834fb264878
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500903101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.1500903101
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.3584075855
Short name T272
Test name
Test status
Simulation time 92057208990 ps
CPU time 459.83 seconds
Started Aug 04 04:42:01 PM PDT 24
Finished Aug 04 04:49:41 PM PDT 24
Peak memory 191552 kb
Host smart-f07331da-c010-415a-aa82-efc3b7e01e78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584075855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.3584075855
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.3605230003
Short name T159
Test name
Test status
Simulation time 121225510921 ps
CPU time 196.27 seconds
Started Aug 04 04:41:11 PM PDT 24
Finished Aug 04 04:44:28 PM PDT 24
Peak memory 183324 kb
Host smart-8d09476d-e028-42c9-afd1-54cd45612f4c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605230003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.3605230003
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.684099059
Short name T372
Test name
Test status
Simulation time 33748173028 ps
CPU time 53.57 seconds
Started Aug 04 04:41:14 PM PDT 24
Finished Aug 04 04:42:08 PM PDT 24
Peak memory 183376 kb
Host smart-d03305f5-6f96-4070-b2f9-361d3af44473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684099059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.684099059
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.76873137
Short name T222
Test name
Test status
Simulation time 697471454374 ps
CPU time 347.33 seconds
Started Aug 04 04:41:13 PM PDT 24
Finished Aug 04 04:47:00 PM PDT 24
Peak memory 191492 kb
Host smart-81a908c5-494b-4691-868f-330638c2d2c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76873137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.76873137
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.1810111358
Short name T183
Test name
Test status
Simulation time 60719219821 ps
CPU time 81.91 seconds
Started Aug 04 04:41:22 PM PDT 24
Finished Aug 04 04:42:44 PM PDT 24
Peak memory 183364 kb
Host smart-7e8a11de-4d04-42de-86d7-48e52294d2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810111358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.1810111358
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.1111381508
Short name T412
Test name
Test status
Simulation time 177773648405 ps
CPU time 71.48 seconds
Started Aug 04 04:41:20 PM PDT 24
Finished Aug 04 04:42:32 PM PDT 24
Peak memory 183348 kb
Host smart-5398f337-0c40-4977-bddd-e55a6fc1a0af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111381508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.1111381508
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/122.rv_timer_random.279103520
Short name T153
Test name
Test status
Simulation time 1104254337380 ps
CPU time 762.72 seconds
Started Aug 04 04:42:04 PM PDT 24
Finished Aug 04 04:54:47 PM PDT 24
Peak memory 191540 kb
Host smart-bda5f38a-6853-4775-8611-00c079934345
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279103520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.279103520
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.1859773770
Short name T230
Test name
Test status
Simulation time 49156375395 ps
CPU time 62.57 seconds
Started Aug 04 04:42:04 PM PDT 24
Finished Aug 04 04:43:07 PM PDT 24
Peak memory 193640 kb
Host smart-0b48824e-2202-477c-871e-95ffaaf8accb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859773770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.1859773770
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.2336136684
Short name T211
Test name
Test status
Simulation time 414731353802 ps
CPU time 236.37 seconds
Started Aug 04 04:42:04 PM PDT 24
Finished Aug 04 04:46:01 PM PDT 24
Peak memory 191584 kb
Host smart-c5ca0db4-9810-49aa-93c0-e3ddcad4f8b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336136684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.2336136684
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.2721904577
Short name T172
Test name
Test status
Simulation time 275692192419 ps
CPU time 353.49 seconds
Started Aug 04 04:42:04 PM PDT 24
Finished Aug 04 04:47:57 PM PDT 24
Peak memory 191548 kb
Host smart-5c8a2925-bea9-41c9-af26-a9d33cb6c99c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721904577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.2721904577
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.4189798772
Short name T217
Test name
Test status
Simulation time 169701998054 ps
CPU time 1393.31 seconds
Started Aug 04 04:42:07 PM PDT 24
Finished Aug 04 05:05:20 PM PDT 24
Peak memory 191584 kb
Host smart-ae9fdd6f-c75e-49be-a19a-35cc28fd4c8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189798772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.4189798772
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.1841104828
Short name T227
Test name
Test status
Simulation time 23402691833 ps
CPU time 67.32 seconds
Started Aug 04 04:42:07 PM PDT 24
Finished Aug 04 04:43:15 PM PDT 24
Peak memory 183460 kb
Host smart-36ac3eed-4d84-4305-8a44-f45e03fb64f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841104828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.1841104828
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.3987331444
Short name T235
Test name
Test status
Simulation time 60988213578 ps
CPU time 98.01 seconds
Started Aug 04 04:41:18 PM PDT 24
Finished Aug 04 04:42:56 PM PDT 24
Peak memory 183368 kb
Host smart-d4519f58-e4ff-4b5b-a05f-aae2f717d9e3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987331444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.3987331444
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.2227797961
Short name T384
Test name
Test status
Simulation time 49799584803 ps
CPU time 66.09 seconds
Started Aug 04 04:41:09 PM PDT 24
Finished Aug 04 04:42:15 PM PDT 24
Peak memory 183356 kb
Host smart-5d7be7b5-5e40-4501-8486-665d4e774ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227797961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.2227797961
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.2946451472
Short name T419
Test name
Test status
Simulation time 30737874338 ps
CPU time 50.67 seconds
Started Aug 04 04:41:23 PM PDT 24
Finished Aug 04 04:42:14 PM PDT 24
Peak memory 183416 kb
Host smart-2dbf9c3c-ee25-4850-b462-3f5f5b2e40a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946451472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.2946451472
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.556070555
Short name T304
Test name
Test status
Simulation time 371192276156 ps
CPU time 1560.61 seconds
Started Aug 04 04:41:19 PM PDT 24
Finished Aug 04 05:07:20 PM PDT 24
Peak memory 191572 kb
Host smart-20fc3ef7-34f0-4337-8d01-d122c834f05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556070555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.556070555
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.3207264004
Short name T156
Test name
Test status
Simulation time 1132311689087 ps
CPU time 528.91 seconds
Started Aug 04 04:41:23 PM PDT 24
Finished Aug 04 04:50:12 PM PDT 24
Peak memory 191576 kb
Host smart-cb773e34-0e59-4fdc-b726-bd75b45a4463
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207264004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.3207264004
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/130.rv_timer_random.338928965
Short name T240
Test name
Test status
Simulation time 229190285493 ps
CPU time 403.99 seconds
Started Aug 04 04:42:07 PM PDT 24
Finished Aug 04 04:48:51 PM PDT 24
Peak memory 191516 kb
Host smart-0e76f68d-d4a5-478c-afb9-3e6ec9621ee8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338928965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.338928965
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.2845316858
Short name T161
Test name
Test status
Simulation time 242026021821 ps
CPU time 282.44 seconds
Started Aug 04 04:42:07 PM PDT 24
Finished Aug 04 04:46:50 PM PDT 24
Peak memory 195240 kb
Host smart-1d29baa6-5d8f-4e71-b428-e843b2a3c75c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845316858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.2845316858
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.202438132
Short name T443
Test name
Test status
Simulation time 12845191907 ps
CPU time 15.96 seconds
Started Aug 04 04:42:07 PM PDT 24
Finished Aug 04 04:42:23 PM PDT 24
Peak memory 183328 kb
Host smart-199c8d4b-da76-4e7d-82a0-1a098b444582
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202438132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.202438132
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.4197533082
Short name T131
Test name
Test status
Simulation time 329916677427 ps
CPU time 352.87 seconds
Started Aug 04 04:42:07 PM PDT 24
Finished Aug 04 04:48:00 PM PDT 24
Peak memory 191620 kb
Host smart-3799553a-6250-4cc3-96da-616ddc516526
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197533082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.4197533082
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.3321903038
Short name T51
Test name
Test status
Simulation time 46831764086 ps
CPU time 90.99 seconds
Started Aug 04 04:42:10 PM PDT 24
Finished Aug 04 04:43:41 PM PDT 24
Peak memory 191552 kb
Host smart-f68aca52-bded-469d-9a70-3a009c1a8f12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321903038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.3321903038
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.1448531489
Short name T151
Test name
Test status
Simulation time 15551573120 ps
CPU time 21.43 seconds
Started Aug 04 04:42:09 PM PDT 24
Finished Aug 04 04:42:30 PM PDT 24
Peak memory 183304 kb
Host smart-8701573f-d4f4-40a3-a189-f9c95320de33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448531489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.1448531489
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.3797379097
Short name T128
Test name
Test status
Simulation time 72159684379 ps
CPU time 30.54 seconds
Started Aug 04 04:42:13 PM PDT 24
Finished Aug 04 04:42:43 PM PDT 24
Peak memory 183368 kb
Host smart-eab82257-db98-49df-b487-34da49d8d2a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797379097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.3797379097
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.2714958866
Short name T424
Test name
Test status
Simulation time 103597066117 ps
CPU time 155.99 seconds
Started Aug 04 04:41:11 PM PDT 24
Finished Aug 04 04:43:47 PM PDT 24
Peak memory 183300 kb
Host smart-ab4fd923-7636-4f17-8a34-5c0934450c82
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714958866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.2714958866
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.3504081211
Short name T408
Test name
Test status
Simulation time 451598575504 ps
CPU time 188.23 seconds
Started Aug 04 04:41:13 PM PDT 24
Finished Aug 04 04:44:22 PM PDT 24
Peak memory 183364 kb
Host smart-8e3d8712-f8d9-4b78-b101-f2855f8b393d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504081211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.3504081211
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.3149548941
Short name T423
Test name
Test status
Simulation time 14277757952 ps
CPU time 6.28 seconds
Started Aug 04 04:41:17 PM PDT 24
Finished Aug 04 04:41:23 PM PDT 24
Peak memory 191556 kb
Host smart-de36d3f6-38b3-4f52-aac1-a534817332e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149548941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.3149548941
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/141.rv_timer_random.4223140208
Short name T201
Test name
Test status
Simulation time 42054532278 ps
CPU time 53.56 seconds
Started Aug 04 04:42:10 PM PDT 24
Finished Aug 04 04:43:03 PM PDT 24
Peak memory 183248 kb
Host smart-c25f309a-b5d6-446a-9ea6-e1ead6dad910
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223140208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.4223140208
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.1596522471
Short name T260
Test name
Test status
Simulation time 144778910786 ps
CPU time 97.54 seconds
Started Aug 04 04:42:14 PM PDT 24
Finished Aug 04 04:43:52 PM PDT 24
Peak memory 183268 kb
Host smart-b1d70c9e-680c-4f01-b3e5-344a5d11a400
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596522471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.1596522471
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.2745747720
Short name T236
Test name
Test status
Simulation time 154113983179 ps
CPU time 464.16 seconds
Started Aug 04 04:42:17 PM PDT 24
Finished Aug 04 04:50:02 PM PDT 24
Peak memory 191540 kb
Host smart-f959a5c0-4708-46a4-978f-b31f7183127f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745747720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.2745747720
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.148844422
Short name T295
Test name
Test status
Simulation time 276509320512 ps
CPU time 540.81 seconds
Started Aug 04 04:42:14 PM PDT 24
Finished Aug 04 04:51:15 PM PDT 24
Peak memory 191544 kb
Host smart-8630e2f8-cc7d-485f-a250-a8467bdf7964
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148844422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.148844422
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.2729749465
Short name T229
Test name
Test status
Simulation time 71920093441 ps
CPU time 224.99 seconds
Started Aug 04 04:42:15 PM PDT 24
Finished Aug 04 04:46:00 PM PDT 24
Peak memory 191556 kb
Host smart-378811f2-e453-467b-977c-98b8c525393c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729749465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.2729749465
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.750623386
Short name T182
Test name
Test status
Simulation time 862647028862 ps
CPU time 314.03 seconds
Started Aug 04 04:42:13 PM PDT 24
Finished Aug 04 04:47:27 PM PDT 24
Peak memory 191552 kb
Host smart-51111d10-95e3-4547-afbd-636ae5f79174
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750623386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.750623386
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.1675112805
Short name T426
Test name
Test status
Simulation time 60659473056 ps
CPU time 31.51 seconds
Started Aug 04 04:41:16 PM PDT 24
Finished Aug 04 04:41:47 PM PDT 24
Peak memory 183460 kb
Host smart-b1b938ba-e2d1-48c5-9517-85fc66746a9e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675112805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.1675112805
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.1023303483
Short name T19
Test name
Test status
Simulation time 283935008972 ps
CPU time 211.56 seconds
Started Aug 04 04:41:04 PM PDT 24
Finished Aug 04 04:44:36 PM PDT 24
Peak memory 183384 kb
Host smart-ad56a953-38f2-4be0-9422-b7f629834a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023303483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.1023303483
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.3526166957
Short name T308
Test name
Test status
Simulation time 196062523638 ps
CPU time 1735.33 seconds
Started Aug 04 04:41:15 PM PDT 24
Finished Aug 04 05:10:10 PM PDT 24
Peak memory 194088 kb
Host smart-962b55a5-bd03-4f89-80b7-4fdc69c00a30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526166957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.3526166957
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.1143953619
Short name T378
Test name
Test status
Simulation time 17435499 ps
CPU time 0.53 seconds
Started Aug 04 04:41:16 PM PDT 24
Finished Aug 04 04:41:17 PM PDT 24
Peak memory 183096 kb
Host smart-6ceedcb4-8f43-4430-9cb5-5004cf07e9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143953619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.1143953619
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/151.rv_timer_random.3038059849
Short name T46
Test name
Test status
Simulation time 364984707500 ps
CPU time 52.52 seconds
Started Aug 04 04:42:13 PM PDT 24
Finished Aug 04 04:43:05 PM PDT 24
Peak memory 183460 kb
Host smart-eb0c103a-c6f0-4b06-afe5-3cd4a7595fee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038059849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.3038059849
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.679875863
Short name T98
Test name
Test status
Simulation time 168301147320 ps
CPU time 804.77 seconds
Started Aug 04 04:42:13 PM PDT 24
Finished Aug 04 04:55:38 PM PDT 24
Peak memory 191576 kb
Host smart-8297eea5-359f-4fc8-a0f0-4ca9a4b17506
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679875863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.679875863
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.2824939541
Short name T71
Test name
Test status
Simulation time 167942497775 ps
CPU time 74.31 seconds
Started Aug 04 04:42:19 PM PDT 24
Finished Aug 04 04:43:33 PM PDT 24
Peak memory 191552 kb
Host smart-15987a88-d6cd-468e-8d9a-19d075e8e0d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824939541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.2824939541
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.1534988086
Short name T305
Test name
Test status
Simulation time 104090408343 ps
CPU time 48.82 seconds
Started Aug 04 04:42:17 PM PDT 24
Finished Aug 04 04:43:06 PM PDT 24
Peak memory 183376 kb
Host smart-7332a227-6207-4c6a-9848-ec3c5afdbb4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534988086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.1534988086
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.4035249243
Short name T94
Test name
Test status
Simulation time 169539846790 ps
CPU time 475.92 seconds
Started Aug 04 04:42:18 PM PDT 24
Finished Aug 04 04:50:14 PM PDT 24
Peak memory 191544 kb
Host smart-a614360c-9cc0-4b74-898c-f17679d2d5b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035249243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.4035249243
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.3577246617
Short name T120
Test name
Test status
Simulation time 574471118224 ps
CPU time 537.02 seconds
Started Aug 04 04:42:18 PM PDT 24
Finished Aug 04 04:51:15 PM PDT 24
Peak memory 191536 kb
Host smart-9e9c7578-376a-4cf9-8f82-e07eb5e6566a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577246617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.3577246617
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.2722679561
Short name T187
Test name
Test status
Simulation time 212743493874 ps
CPU time 1689.74 seconds
Started Aug 04 04:42:18 PM PDT 24
Finished Aug 04 05:10:28 PM PDT 24
Peak memory 191620 kb
Host smart-9bc5fe18-2469-4791-bc2a-9928a59b4983
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722679561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.2722679561
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.680658190
Short name T400
Test name
Test status
Simulation time 272401700176 ps
CPU time 159.79 seconds
Started Aug 04 04:41:19 PM PDT 24
Finished Aug 04 04:43:59 PM PDT 24
Peak memory 183652 kb
Host smart-15d1c0fe-191d-4d3d-8951-d52734e516dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680658190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.680658190
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.2719845811
Short name T357
Test name
Test status
Simulation time 6317055355 ps
CPU time 6.61 seconds
Started Aug 04 04:41:13 PM PDT 24
Finished Aug 04 04:41:20 PM PDT 24
Peak memory 191660 kb
Host smart-36a2bc89-1904-4ad7-b984-359ca4473192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719845811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.2719845811
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all_with_rand_reset.1891399065
Short name T40
Test name
Test status
Simulation time 119059047181 ps
CPU time 1286.83 seconds
Started Aug 04 04:41:21 PM PDT 24
Finished Aug 04 05:02:48 PM PDT 24
Peak memory 209368 kb
Host smart-c5ef988e-a6c5-4697-99db-7ddd3e6ccf5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891399065 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all_with_rand_reset.1891399065
Directory /workspace/16.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.1821169754
Short name T363
Test name
Test status
Simulation time 68773201183 ps
CPU time 392.33 seconds
Started Aug 04 04:42:18 PM PDT 24
Finished Aug 04 04:48:51 PM PDT 24
Peak memory 183344 kb
Host smart-2a023855-2126-42d2-8dd0-4b156b76beaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821169754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.1821169754
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.2061011149
Short name T349
Test name
Test status
Simulation time 199812027412 ps
CPU time 267.13 seconds
Started Aug 04 04:42:20 PM PDT 24
Finished Aug 04 04:46:47 PM PDT 24
Peak memory 191592 kb
Host smart-62b968b0-5856-42c5-9487-049199e27556
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061011149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.2061011149
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.3676745671
Short name T390
Test name
Test status
Simulation time 85226985030 ps
CPU time 754.59 seconds
Started Aug 04 04:42:17 PM PDT 24
Finished Aug 04 04:54:52 PM PDT 24
Peak memory 183340 kb
Host smart-0aac54cd-d211-4d32-b0dc-d71407c85b8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676745671 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.3676745671
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.208690208
Short name T303
Test name
Test status
Simulation time 420068865911 ps
CPU time 1248.5 seconds
Started Aug 04 04:42:19 PM PDT 24
Finished Aug 04 05:03:07 PM PDT 24
Peak memory 193640 kb
Host smart-3e2f21ed-44ab-4e6c-aff7-8923098780af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208690208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.208690208
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.627594782
Short name T167
Test name
Test status
Simulation time 94449938995 ps
CPU time 365.71 seconds
Started Aug 04 04:42:19 PM PDT 24
Finished Aug 04 04:48:25 PM PDT 24
Peak memory 191552 kb
Host smart-c101a28c-b8ee-4953-bffa-e659456a0137
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627594782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.627594782
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.215527372
Short name T264
Test name
Test status
Simulation time 112875261922 ps
CPU time 506.25 seconds
Started Aug 04 04:42:20 PM PDT 24
Finished Aug 04 04:50:46 PM PDT 24
Peak memory 191612 kb
Host smart-33e93709-853d-47a9-a552-f766de70d027
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215527372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.215527372
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.2015675442
Short name T43
Test name
Test status
Simulation time 45421198575 ps
CPU time 76.68 seconds
Started Aug 04 04:42:21 PM PDT 24
Finished Aug 04 04:43:38 PM PDT 24
Peak memory 183300 kb
Host smart-bd6fbaf8-f446-4f10-b730-25f182883f9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015675442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.2015675442
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.1698273295
Short name T290
Test name
Test status
Simulation time 702984127278 ps
CPU time 1192.26 seconds
Started Aug 04 04:41:14 PM PDT 24
Finished Aug 04 05:01:06 PM PDT 24
Peak memory 183372 kb
Host smart-6779eb07-f2e8-4155-899b-4ebd96693df4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698273295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.1698273295
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.42571596
Short name T421
Test name
Test status
Simulation time 339231441457 ps
CPU time 236.76 seconds
Started Aug 04 04:41:11 PM PDT 24
Finished Aug 04 04:45:08 PM PDT 24
Peak memory 183444 kb
Host smart-8ebcffe6-67d9-49ec-82ce-95dbc75a2b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42571596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.42571596
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.110613394
Short name T388
Test name
Test status
Simulation time 247737863 ps
CPU time 1.58 seconds
Started Aug 04 04:41:21 PM PDT 24
Finished Aug 04 04:41:23 PM PDT 24
Peak memory 183332 kb
Host smart-822bb570-d7a1-4b57-b689-278ccdaeabb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110613394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.110613394
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.3317045677
Short name T331
Test name
Test status
Simulation time 700962790659 ps
CPU time 733.59 seconds
Started Aug 04 04:41:14 PM PDT 24
Finished Aug 04 04:53:28 PM PDT 24
Peak memory 191504 kb
Host smart-419b1062-fa27-4d12-a089-649e7b28b7ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317045677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.3317045677
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.2235333078
Short name T13
Test name
Test status
Simulation time 238013370855 ps
CPU time 660.67 seconds
Started Aug 04 04:41:21 PM PDT 24
Finished Aug 04 04:52:22 PM PDT 24
Peak memory 208896 kb
Host smart-18f65a2b-89b4-43d3-a3b5-42c2bf3ad5db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235333078 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all_with_rand_reset.2235333078
Directory /workspace/17.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.3018995533
Short name T281
Test name
Test status
Simulation time 42125754809 ps
CPU time 77.87 seconds
Started Aug 04 04:42:22 PM PDT 24
Finished Aug 04 04:43:40 PM PDT 24
Peak memory 191560 kb
Host smart-211f56b6-4fcb-440c-ae11-4ae610645529
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018995533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.3018995533
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.2323683673
Short name T26
Test name
Test status
Simulation time 71451385787 ps
CPU time 46.15 seconds
Started Aug 04 04:42:21 PM PDT 24
Finished Aug 04 04:43:07 PM PDT 24
Peak memory 183144 kb
Host smart-9fbe8175-3477-47ec-a0bc-eb43e3162b67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323683673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.2323683673
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.1329628837
Short name T280
Test name
Test status
Simulation time 80719398475 ps
CPU time 237.19 seconds
Started Aug 04 04:42:20 PM PDT 24
Finished Aug 04 04:46:18 PM PDT 24
Peak memory 191592 kb
Host smart-56102bd4-9335-491c-af41-66e7df6aace2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329628837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.1329628837
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.2894150671
Short name T267
Test name
Test status
Simulation time 379652875934 ps
CPU time 698.63 seconds
Started Aug 04 04:42:21 PM PDT 24
Finished Aug 04 04:54:00 PM PDT 24
Peak memory 191592 kb
Host smart-d46ee8c9-0869-4654-88da-2fdc5f46e11b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894150671 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.2894150671
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.668246146
Short name T242
Test name
Test status
Simulation time 275449150110 ps
CPU time 303.89 seconds
Started Aug 04 04:42:21 PM PDT 24
Finished Aug 04 04:47:25 PM PDT 24
Peak memory 191512 kb
Host smart-d64cd3fa-97b7-42aa-93d0-fc1cf9b0ebeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668246146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.668246146
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.3573315434
Short name T311
Test name
Test status
Simulation time 199993666626 ps
CPU time 205.7 seconds
Started Aug 04 04:42:23 PM PDT 24
Finished Aug 04 04:45:49 PM PDT 24
Peak memory 191544 kb
Host smart-aacf83a5-3c45-4b60-9f89-be8292740748
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573315434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.3573315434
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.3711367524
Short name T232
Test name
Test status
Simulation time 284608553821 ps
CPU time 134.63 seconds
Started Aug 04 04:41:16 PM PDT 24
Finished Aug 04 04:43:31 PM PDT 24
Peak memory 183364 kb
Host smart-2d3b1eb1-ab67-4f18-a841-2a5f7d17b656
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711367524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.3711367524
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.1159343058
Short name T417
Test name
Test status
Simulation time 364735478640 ps
CPU time 146.34 seconds
Started Aug 04 04:41:20 PM PDT 24
Finished Aug 04 04:43:47 PM PDT 24
Peak memory 183384 kb
Host smart-2c709033-bfb4-4652-9447-8c4d5c488ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159343058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.1159343058
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.1467374988
Short name T126
Test name
Test status
Simulation time 39447768194 ps
CPU time 111.6 seconds
Started Aug 04 04:41:15 PM PDT 24
Finished Aug 04 04:43:07 PM PDT 24
Peak memory 191660 kb
Host smart-a0b8d729-96f4-417f-9ab1-6d18e2395445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467374988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.1467374988
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.2067636314
Short name T422
Test name
Test status
Simulation time 4115431831 ps
CPU time 8.82 seconds
Started Aug 04 04:41:14 PM PDT 24
Finished Aug 04 04:41:23 PM PDT 24
Peak memory 183396 kb
Host smart-5af4945a-1e77-4d74-bbd9-ae7f0c8abdb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067636314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.2067636314
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/182.rv_timer_random.3175805046
Short name T353
Test name
Test status
Simulation time 167280362741 ps
CPU time 476.03 seconds
Started Aug 04 04:42:23 PM PDT 24
Finished Aug 04 04:50:20 PM PDT 24
Peak memory 191580 kb
Host smart-de66321b-393a-4781-a557-84bbfe4ee35d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175805046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.3175805046
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.2882606101
Short name T5
Test name
Test status
Simulation time 212950728022 ps
CPU time 108.72 seconds
Started Aug 04 04:42:24 PM PDT 24
Finished Aug 04 04:44:13 PM PDT 24
Peak memory 191536 kb
Host smart-7259a854-cf2b-419a-a633-bbe648b2f69a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882606101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.2882606101
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.1398006597
Short name T301
Test name
Test status
Simulation time 59332040548 ps
CPU time 86.8 seconds
Started Aug 04 04:42:24 PM PDT 24
Finished Aug 04 04:43:51 PM PDT 24
Peak memory 183460 kb
Host smart-5a2e67a4-56b2-4866-862b-342aa2202b20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398006597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.1398006597
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.2268032207
Short name T238
Test name
Test status
Simulation time 1051379287217 ps
CPU time 875.2 seconds
Started Aug 04 04:42:23 PM PDT 24
Finished Aug 04 04:56:59 PM PDT 24
Peak memory 191556 kb
Host smart-2e51e40c-6910-443b-9b3f-ba23b3454112
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268032207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.2268032207
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.2943378498
Short name T447
Test name
Test status
Simulation time 54378902307 ps
CPU time 95.25 seconds
Started Aug 04 04:42:24 PM PDT 24
Finished Aug 04 04:44:00 PM PDT 24
Peak memory 191552 kb
Host smart-4a29f1ed-33cd-48f3-be3a-011a061983f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943378498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.2943378498
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.293306455
Short name T214
Test name
Test status
Simulation time 656271558447 ps
CPU time 584.51 seconds
Started Aug 04 04:42:24 PM PDT 24
Finished Aug 04 04:52:08 PM PDT 24
Peak memory 193620 kb
Host smart-c0dbc276-d8b4-41bd-8602-0ac2c88969d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293306455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.293306455
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.4209646908
Short name T169
Test name
Test status
Simulation time 45608101488 ps
CPU time 25.83 seconds
Started Aug 04 04:41:19 PM PDT 24
Finished Aug 04 04:41:45 PM PDT 24
Peak memory 183348 kb
Host smart-079cd075-378b-4a46-a4c7-86edcbc939f2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209646908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.4209646908
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.3412049426
Short name T435
Test name
Test status
Simulation time 95133754303 ps
CPU time 121.12 seconds
Started Aug 04 04:41:30 PM PDT 24
Finished Aug 04 04:43:31 PM PDT 24
Peak memory 183360 kb
Host smart-9dc11d1a-3694-4f7b-8f1f-603b9cfd6b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412049426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.3412049426
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.1908224227
Short name T437
Test name
Test status
Simulation time 28172768089 ps
CPU time 42.13 seconds
Started Aug 04 04:41:18 PM PDT 24
Finished Aug 04 04:42:00 PM PDT 24
Peak memory 183384 kb
Host smart-0beb615d-0911-42c6-8323-f564afd05d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908224227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.1908224227
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.1345754496
Short name T385
Test name
Test status
Simulation time 2203317316891 ps
CPU time 477.92 seconds
Started Aug 04 04:41:21 PM PDT 24
Finished Aug 04 04:49:19 PM PDT 24
Peak memory 191556 kb
Host smart-d0b57160-1769-49d8-ad62-c9cbf2bf8d54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345754496 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.1345754496
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/190.rv_timer_random.1325950209
Short name T216
Test name
Test status
Simulation time 631146868121 ps
CPU time 686.21 seconds
Started Aug 04 04:42:22 PM PDT 24
Finished Aug 04 04:53:49 PM PDT 24
Peak memory 195024 kb
Host smart-97ecd7c1-d745-4257-b08c-e155ab36e42f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325950209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.1325950209
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.1733277365
Short name T241
Test name
Test status
Simulation time 491331321045 ps
CPU time 314.86 seconds
Started Aug 04 04:42:27 PM PDT 24
Finished Aug 04 04:47:42 PM PDT 24
Peak memory 191636 kb
Host smart-5e2b4d31-c3f0-402e-98e7-b333188f4d64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733277365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.1733277365
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.1770731522
Short name T282
Test name
Test status
Simulation time 578078129113 ps
CPU time 317.64 seconds
Started Aug 04 04:42:31 PM PDT 24
Finished Aug 04 04:47:49 PM PDT 24
Peak memory 190960 kb
Host smart-7f181e63-5dc6-477e-bf84-e98c472276e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770731522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.1770731522
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.1062480539
Short name T162
Test name
Test status
Simulation time 225410024750 ps
CPU time 466.25 seconds
Started Aug 04 04:42:27 PM PDT 24
Finished Aug 04 04:50:13 PM PDT 24
Peak memory 191532 kb
Host smart-05e783ba-2ff3-4005-9dfb-ceec88b53466
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062480539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.1062480539
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.4078337046
Short name T202
Test name
Test status
Simulation time 79956346996 ps
CPU time 519.14 seconds
Started Aug 04 04:42:31 PM PDT 24
Finished Aug 04 04:51:10 PM PDT 24
Peak memory 191640 kb
Host smart-9ad9d781-2f64-4a8f-93b0-caa545bb78e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078337046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.4078337046
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.3860367172
Short name T231
Test name
Test status
Simulation time 15382710241 ps
CPU time 31.69 seconds
Started Aug 04 04:42:27 PM PDT 24
Finished Aug 04 04:42:59 PM PDT 24
Peak memory 183360 kb
Host smart-8c6aa4f2-f9dc-41d7-ae2a-e42c67b38310
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860367172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.3860367172
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.1276093720
Short name T365
Test name
Test status
Simulation time 100643708411 ps
CPU time 129.05 seconds
Started Aug 04 04:41:07 PM PDT 24
Finished Aug 04 04:43:16 PM PDT 24
Peak memory 183328 kb
Host smart-cfc3a506-1921-4863-9f3f-7acb114a03a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276093720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.1276093720
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.4278742603
Short name T254
Test name
Test status
Simulation time 88114718241 ps
CPU time 147.88 seconds
Started Aug 04 04:41:05 PM PDT 24
Finished Aug 04 04:43:33 PM PDT 24
Peak memory 191628 kb
Host smart-9c1a4507-4626-4fec-9baf-6dae5e494171
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278742603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.4278742603
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.3499248055
Short name T383
Test name
Test status
Simulation time 1539421728 ps
CPU time 4.05 seconds
Started Aug 04 04:41:04 PM PDT 24
Finished Aug 04 04:41:08 PM PDT 24
Peak memory 183348 kb
Host smart-779fd7bc-fc42-40c0-a3cf-30d6ed65283d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499248055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.3499248055
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.3862242869
Short name T15
Test name
Test status
Simulation time 70407818 ps
CPU time 0.74 seconds
Started Aug 04 04:41:16 PM PDT 24
Finished Aug 04 04:41:17 PM PDT 24
Peak memory 214072 kb
Host smart-c4dc3010-08ad-4caa-833d-428023b201f7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862242869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.3862242869
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.4220425381
Short name T369
Test name
Test status
Simulation time 590091789806 ps
CPU time 183.53 seconds
Started Aug 04 04:41:20 PM PDT 24
Finished Aug 04 04:44:24 PM PDT 24
Peak memory 183452 kb
Host smart-767bfa3e-78b6-4a2c-805f-aa0e61029237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220425381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.4220425381
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.485468602
Short name T113
Test name
Test status
Simulation time 660965710441 ps
CPU time 352.54 seconds
Started Aug 04 04:41:27 PM PDT 24
Finished Aug 04 04:47:19 PM PDT 24
Peak memory 191560 kb
Host smart-a4862256-b518-4880-bdbc-ca6ebfc7c12e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485468602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.485468602
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.223701930
Short name T20
Test name
Test status
Simulation time 55290752347 ps
CPU time 68.81 seconds
Started Aug 04 04:41:11 PM PDT 24
Finished Aug 04 04:42:20 PM PDT 24
Peak memory 183364 kb
Host smart-3494f6ed-bc98-43b4-ac6a-a001c80d6938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223701930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.223701930
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.837236207
Short name T262
Test name
Test status
Simulation time 236699901491 ps
CPU time 183.5 seconds
Started Aug 04 04:41:23 PM PDT 24
Finished Aug 04 04:44:27 PM PDT 24
Peak memory 183424 kb
Host smart-cb427171-0cbb-4eb9-a1f1-665b30ead94b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837236207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.rv_timer_cfg_update_on_fly.837236207
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.1096402065
Short name T366
Test name
Test status
Simulation time 139945305425 ps
CPU time 106.19 seconds
Started Aug 04 04:41:11 PM PDT 24
Finished Aug 04 04:42:57 PM PDT 24
Peak memory 183332 kb
Host smart-2f2a65ec-0b62-40fc-8168-ee5c45b6c424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096402065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.1096402065
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.609810734
Short name T127
Test name
Test status
Simulation time 174788159985 ps
CPU time 188.74 seconds
Started Aug 04 04:41:20 PM PDT 24
Finished Aug 04 04:44:29 PM PDT 24
Peak memory 193580 kb
Host smart-db48bcbc-6014-45f6-9ec3-902c34eef498
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609810734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.609810734
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.2119671968
Short name T375
Test name
Test status
Simulation time 66332288 ps
CPU time 0.59 seconds
Started Aug 04 04:41:16 PM PDT 24
Finished Aug 04 04:41:17 PM PDT 24
Peak memory 183200 kb
Host smart-13550eaf-1fd6-4169-ad07-543bafb76e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119671968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.2119671968
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.1303910964
Short name T95
Test name
Test status
Simulation time 1062938446692 ps
CPU time 1012.4 seconds
Started Aug 04 04:41:13 PM PDT 24
Finished Aug 04 04:58:06 PM PDT 24
Peak memory 191652 kb
Host smart-8b542a5a-c282-4bde-a1ea-037c15689cec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303910964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.1303910964
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.2471886307
Short name T289
Test name
Test status
Simulation time 210002053142 ps
CPU time 337.66 seconds
Started Aug 04 04:41:15 PM PDT 24
Finished Aug 04 04:46:53 PM PDT 24
Peak memory 183092 kb
Host smart-6bf18fd7-59e2-4440-a6fc-ab5a4af5981c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471886307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.2471886307
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.3467229834
Short name T451
Test name
Test status
Simulation time 261439226330 ps
CPU time 179.14 seconds
Started Aug 04 04:41:18 PM PDT 24
Finished Aug 04 04:44:17 PM PDT 24
Peak memory 183412 kb
Host smart-48056f61-0580-4017-bf39-fcffbfae167a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467229834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.3467229834
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.160501602
Short name T164
Test name
Test status
Simulation time 450690055968 ps
CPU time 208.9 seconds
Started Aug 04 04:41:17 PM PDT 24
Finished Aug 04 04:44:46 PM PDT 24
Peak memory 191624 kb
Host smart-b5718768-7da9-414b-8354-23b5122cf36c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160501602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.160501602
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.3368678949
Short name T414
Test name
Test status
Simulation time 389040690 ps
CPU time 0.82 seconds
Started Aug 04 04:41:29 PM PDT 24
Finished Aug 04 04:41:30 PM PDT 24
Peak memory 183048 kb
Host smart-0b20e704-b029-4ccf-851c-a228c1fca9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368678949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.3368678949
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.2651533308
Short name T215
Test name
Test status
Simulation time 192983132776 ps
CPU time 1673.42 seconds
Started Aug 04 04:41:20 PM PDT 24
Finished Aug 04 05:09:14 PM PDT 24
Peak memory 191492 kb
Host smart-129a9d70-b5ee-4aeb-9796-fe489af75c94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651533308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.2651533308
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.2991913408
Short name T296
Test name
Test status
Simulation time 727353730795 ps
CPU time 379.82 seconds
Started Aug 04 04:41:17 PM PDT 24
Finished Aug 04 04:47:37 PM PDT 24
Peak memory 183360 kb
Host smart-659e4fcf-0f8e-4555-8a6a-bf962be25259
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991913408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.2991913408
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.342754800
Short name T393
Test name
Test status
Simulation time 482540152561 ps
CPU time 86.1 seconds
Started Aug 04 04:41:15 PM PDT 24
Finished Aug 04 04:42:41 PM PDT 24
Peak memory 183356 kb
Host smart-b37f51ec-c092-4d0d-b39e-ebc1149f66ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342754800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.342754800
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.1694426535
Short name T118
Test name
Test status
Simulation time 146951520040 ps
CPU time 418.47 seconds
Started Aug 04 04:41:26 PM PDT 24
Finished Aug 04 04:48:25 PM PDT 24
Peak memory 191576 kb
Host smart-dde539ee-ea44-4fc1-8851-ea54b72b9dfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694426535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.1694426535
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.3440959367
Short name T425
Test name
Test status
Simulation time 745235029949 ps
CPU time 296.14 seconds
Started Aug 04 04:41:23 PM PDT 24
Finished Aug 04 04:46:20 PM PDT 24
Peak memory 183356 kb
Host smart-35be72a7-d727-4626-8436-0a1bb8887897
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440959367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.3440959367
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.277354725
Short name T37
Test name
Test status
Simulation time 228250483683 ps
CPU time 1184.3 seconds
Started Aug 04 04:41:26 PM PDT 24
Finished Aug 04 05:01:10 PM PDT 24
Peak memory 198112 kb
Host smart-49ab3a7b-c2df-4288-978c-1a05d4b19d9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277354725 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_reset.277354725
Directory /workspace/23.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.3434359291
Short name T45
Test name
Test status
Simulation time 829740454897 ps
CPU time 446.67 seconds
Started Aug 04 04:41:23 PM PDT 24
Finished Aug 04 04:48:50 PM PDT 24
Peak memory 183652 kb
Host smart-060021f0-7f9e-4d3c-8f8a-01c63129c565
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434359291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.3434359291
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.4067038507
Short name T434
Test name
Test status
Simulation time 18602899044 ps
CPU time 28.9 seconds
Started Aug 04 04:41:25 PM PDT 24
Finished Aug 04 04:41:54 PM PDT 24
Peak memory 183336 kb
Host smart-030aac10-9df7-46dc-8e16-fdca4a4ae842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067038507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.4067038507
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.1250678888
Short name T265
Test name
Test status
Simulation time 201466228867 ps
CPU time 73.39 seconds
Started Aug 04 04:41:17 PM PDT 24
Finished Aug 04 04:42:31 PM PDT 24
Peak memory 183372 kb
Host smart-943bdddf-283b-4a48-b27a-e563b9a403a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250678888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.1250678888
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.1389367619
Short name T108
Test name
Test status
Simulation time 123798521582 ps
CPU time 91.77 seconds
Started Aug 04 04:41:21 PM PDT 24
Finished Aug 04 04:42:53 PM PDT 24
Peak memory 191568 kb
Host smart-c4c0991d-2b0d-4b4c-b5b3-daa6b8fc8ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389367619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.1389367619
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.453300628
Short name T251
Test name
Test status
Simulation time 2190153351560 ps
CPU time 1081.41 seconds
Started Aug 04 04:41:23 PM PDT 24
Finished Aug 04 04:59:25 PM PDT 24
Peak memory 196100 kb
Host smart-52813e2c-5841-453e-9550-c8ba6c6f0c07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453300628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.
453300628
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all_with_rand_reset.4002641435
Short name T12
Test name
Test status
Simulation time 58912481245 ps
CPU time 446 seconds
Started Aug 04 04:41:26 PM PDT 24
Finished Aug 04 04:48:52 PM PDT 24
Peak memory 206260 kb
Host smart-403ba328-733e-440e-8a0b-d4d202b8b1c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002641435 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all_with_rand_reset.4002641435
Directory /workspace/24.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.1349809397
Short name T247
Test name
Test status
Simulation time 391070367129 ps
CPU time 654.88 seconds
Started Aug 04 04:41:18 PM PDT 24
Finished Aug 04 04:52:13 PM PDT 24
Peak memory 183420 kb
Host smart-6cbb6890-be2b-4fbb-93d1-c3b95662f877
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349809397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.1349809397
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.701609067
Short name T377
Test name
Test status
Simulation time 98769660700 ps
CPU time 65.98 seconds
Started Aug 04 04:41:23 PM PDT 24
Finished Aug 04 04:42:29 PM PDT 24
Peak memory 183400 kb
Host smart-fc0f541c-45cc-477a-98fb-c67159dad9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701609067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.701609067
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.3447777357
Short name T438
Test name
Test status
Simulation time 686591526011 ps
CPU time 596.73 seconds
Started Aug 04 04:41:25 PM PDT 24
Finished Aug 04 04:51:22 PM PDT 24
Peak memory 191544 kb
Host smart-e568d8ab-b836-4b2a-af8b-9af0e871328f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447777357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.3447777357
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.2842674660
Short name T328
Test name
Test status
Simulation time 210446047391 ps
CPU time 211.72 seconds
Started Aug 04 04:41:23 PM PDT 24
Finished Aug 04 04:44:54 PM PDT 24
Peak memory 191576 kb
Host smart-878aa0fc-9c94-4df1-84ff-7d140917746a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842674660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.2842674660
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.4236556643
Short name T100
Test name
Test status
Simulation time 2053142231467 ps
CPU time 1835.02 seconds
Started Aug 04 04:41:20 PM PDT 24
Finished Aug 04 05:11:55 PM PDT 24
Peak memory 195488 kb
Host smart-2e35cf5c-b018-443a-9972-2c6537de39bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236556643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.4236556643
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.3682452533
Short name T300
Test name
Test status
Simulation time 82514907364 ps
CPU time 124.6 seconds
Started Aug 04 04:41:24 PM PDT 24
Finished Aug 04 04:43:29 PM PDT 24
Peak memory 183324 kb
Host smart-05eb378d-8b09-4aee-97ec-c5f6e1ec4e6e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682452533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.3682452533
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.4190442077
Short name T446
Test name
Test status
Simulation time 91526810529 ps
CPU time 70.83 seconds
Started Aug 04 04:41:29 PM PDT 24
Finished Aug 04 04:42:40 PM PDT 24
Peak memory 183280 kb
Host smart-c6b5a05a-1e3a-4f51-882f-a1c63172b954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190442077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.4190442077
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.2405173970
Short name T194
Test name
Test status
Simulation time 590973735145 ps
CPU time 1016.46 seconds
Started Aug 04 04:41:23 PM PDT 24
Finished Aug 04 04:58:19 PM PDT 24
Peak memory 191636 kb
Host smart-44adcdac-4e95-4232-b55d-b3b42c98a80b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405173970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.2405173970
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.2034296051
Short name T97
Test name
Test status
Simulation time 44126529963 ps
CPU time 76.97 seconds
Started Aug 04 04:41:25 PM PDT 24
Finished Aug 04 04:42:42 PM PDT 24
Peak memory 183356 kb
Host smart-da52ccab-82d2-4b1f-9db1-0a4030ee4fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034296051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.2034296051
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.3199109548
Short name T356
Test name
Test status
Simulation time 184416428508 ps
CPU time 1110.1 seconds
Started Aug 04 04:41:27 PM PDT 24
Finished Aug 04 05:00:03 PM PDT 24
Peak memory 191516 kb
Host smart-bb4fa808-eede-4915-bab2-24fa9f0ae309
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199109548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.3199109548
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.3956815990
Short name T140
Test name
Test status
Simulation time 949618709080 ps
CPU time 486.83 seconds
Started Aug 04 04:41:25 PM PDT 24
Finished Aug 04 04:49:32 PM PDT 24
Peak memory 183344 kb
Host smart-29cf86ec-fe63-44f0-ab1b-c5689a37c6a8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956815990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.3956815990
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.3174804707
Short name T445
Test name
Test status
Simulation time 36481011226 ps
CPU time 24.95 seconds
Started Aug 04 04:41:22 PM PDT 24
Finished Aug 04 04:41:47 PM PDT 24
Peak memory 183396 kb
Host smart-d4548142-0fab-4839-b601-7e2c27582eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174804707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.3174804707
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.3616898748
Short name T350
Test name
Test status
Simulation time 7582343491 ps
CPU time 91.24 seconds
Started Aug 04 04:41:24 PM PDT 24
Finished Aug 04 04:42:56 PM PDT 24
Peak memory 183332 kb
Host smart-d039279d-6999-481d-a6f9-38ebbefa73b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616898748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.3616898748
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.2125329968
Short name T10
Test name
Test status
Simulation time 111945361305 ps
CPU time 21.91 seconds
Started Aug 04 04:41:25 PM PDT 24
Finished Aug 04 04:41:47 PM PDT 24
Peak memory 191556 kb
Host smart-12bb448c-4fa5-4e9c-a774-41921a9f6d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125329968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.2125329968
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.3150778670
Short name T354
Test name
Test status
Simulation time 727847930984 ps
CPU time 226.07 seconds
Started Aug 04 04:41:30 PM PDT 24
Finished Aug 04 04:45:16 PM PDT 24
Peak memory 183332 kb
Host smart-12b4372c-3238-4969-81e5-2c18ea058315
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150778670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.3150778670
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.3534629374
Short name T147
Test name
Test status
Simulation time 253773311576 ps
CPU time 155.57 seconds
Started Aug 04 04:41:42 PM PDT 24
Finished Aug 04 04:44:18 PM PDT 24
Peak memory 183352 kb
Host smart-2f0c2251-4c57-4617-a6a3-81dc5c7a7834
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534629374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.3534629374
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.568381089
Short name T403
Test name
Test status
Simulation time 43602172248 ps
CPU time 67.2 seconds
Started Aug 04 04:41:22 PM PDT 24
Finished Aug 04 04:42:29 PM PDT 24
Peak memory 183412 kb
Host smart-3bc96e4a-61e9-4943-a60d-07b0caeed760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568381089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.568381089
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.1250623995
Short name T428
Test name
Test status
Simulation time 166722864 ps
CPU time 0.83 seconds
Started Aug 04 04:41:20 PM PDT 24
Finished Aug 04 04:41:21 PM PDT 24
Peak memory 191728 kb
Host smart-95a3b8fa-e261-4f4e-b764-ebf7f8361fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250623995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.1250623995
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.477547873
Short name T70
Test name
Test status
Simulation time 841379584391 ps
CPU time 818.13 seconds
Started Aug 04 04:41:25 PM PDT 24
Finished Aug 04 04:55:03 PM PDT 24
Peak memory 183352 kb
Host smart-b172c415-8257-47b3-9b20-d0886ca716c4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477547873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.rv_timer_cfg_update_on_fly.477547873
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.2913897148
Short name T436
Test name
Test status
Simulation time 443253387696 ps
CPU time 160.81 seconds
Started Aug 04 04:41:29 PM PDT 24
Finished Aug 04 04:44:10 PM PDT 24
Peak memory 183384 kb
Host smart-e2766911-225c-474d-b97e-3f93da5444be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913897148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.2913897148
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.3308274694
Short name T206
Test name
Test status
Simulation time 400203323759 ps
CPU time 314.54 seconds
Started Aug 04 04:41:29 PM PDT 24
Finished Aug 04 04:46:43 PM PDT 24
Peak memory 191592 kb
Host smart-3571b529-4b4f-451f-bb9b-ab139a5ca0e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308274694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.3308274694
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.2170550685
Short name T116
Test name
Test status
Simulation time 523608527438 ps
CPU time 103.22 seconds
Started Aug 04 04:41:29 PM PDT 24
Finished Aug 04 04:43:12 PM PDT 24
Peak memory 194012 kb
Host smart-8e1a6822-6285-4b69-a7e7-cf9806c99fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170550685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.2170550685
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.3274996962
Short name T283
Test name
Test status
Simulation time 152484306845 ps
CPU time 149.77 seconds
Started Aug 04 04:41:40 PM PDT 24
Finished Aug 04 04:44:09 PM PDT 24
Peak memory 191536 kb
Host smart-3dd50c6d-aeb1-4075-afed-5148892d57e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274996962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.3274996962
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.3587506373
Short name T93
Test name
Test status
Simulation time 864515538931 ps
CPU time 394.91 seconds
Started Aug 04 04:41:06 PM PDT 24
Finished Aug 04 04:47:41 PM PDT 24
Peak memory 183292 kb
Host smart-05ec3caa-3d00-4e51-81eb-8f32c873ca16
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587506373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.3587506373
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.584464848
Short name T448
Test name
Test status
Simulation time 294914240617 ps
CPU time 193.21 seconds
Started Aug 04 04:41:05 PM PDT 24
Finished Aug 04 04:44:18 PM PDT 24
Peak memory 183332 kb
Host smart-fa5c26a3-7982-484a-8c80-91e445bbbddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584464848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.584464848
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.1276150046
Short name T418
Test name
Test status
Simulation time 14366740657 ps
CPU time 25.79 seconds
Started Aug 04 04:41:08 PM PDT 24
Finished Aug 04 04:41:34 PM PDT 24
Peak memory 183368 kb
Host smart-e3c92999-4c37-46f9-bb27-a04b0aa93e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276150046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.1276150046
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.2962564996
Short name T16
Test name
Test status
Simulation time 39078280 ps
CPU time 0.76 seconds
Started Aug 04 04:41:05 PM PDT 24
Finished Aug 04 04:41:06 PM PDT 24
Peak memory 213944 kb
Host smart-72487e47-2ff1-4a60-a490-c95ef54dc0a9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962564996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.2962564996
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.4161686566
Short name T246
Test name
Test status
Simulation time 8327028330288 ps
CPU time 2017.39 seconds
Started Aug 04 04:41:11 PM PDT 24
Finished Aug 04 05:14:49 PM PDT 24
Peak memory 191544 kb
Host smart-09db1a28-9893-4d4c-8f47-3f6ec88ba203
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161686566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
4161686566
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.3010558850
Short name T73
Test name
Test status
Simulation time 42216859152 ps
CPU time 56.68 seconds
Started Aug 04 04:41:38 PM PDT 24
Finished Aug 04 04:42:35 PM PDT 24
Peak memory 183364 kb
Host smart-50c1578d-635d-45f7-a99e-243c67cca82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010558850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.3010558850
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.2940702200
Short name T47
Test name
Test status
Simulation time 180887726720 ps
CPU time 301.98 seconds
Started Aug 04 04:41:28 PM PDT 24
Finished Aug 04 04:46:30 PM PDT 24
Peak memory 191548 kb
Host smart-4029c0f8-0ffa-45d5-8695-1c15edd4e24d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940702200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.2940702200
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.2265142000
Short name T145
Test name
Test status
Simulation time 47476485118 ps
CPU time 83.53 seconds
Started Aug 04 04:41:33 PM PDT 24
Finished Aug 04 04:42:57 PM PDT 24
Peak memory 183340 kb
Host smart-93319507-bf13-4f35-a706-816356c148df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265142000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.2265142000
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.270784467
Short name T144
Test name
Test status
Simulation time 309156378639 ps
CPU time 507.21 seconds
Started Aug 04 04:41:37 PM PDT 24
Finished Aug 04 04:50:04 PM PDT 24
Peak memory 183292 kb
Host smart-0d1e5e49-1b68-46a3-93ae-b4185737e2f6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270784467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.rv_timer_cfg_update_on_fly.270784467
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.1343899428
Short name T395
Test name
Test status
Simulation time 91826224944 ps
CPU time 21.39 seconds
Started Aug 04 04:41:33 PM PDT 24
Finished Aug 04 04:41:55 PM PDT 24
Peak memory 183296 kb
Host smart-cb16fff6-51b2-49a4-94dd-2587fceafae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343899428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.1343899428
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.2757399543
Short name T278
Test name
Test status
Simulation time 35332592649 ps
CPU time 50.97 seconds
Started Aug 04 04:41:34 PM PDT 24
Finished Aug 04 04:42:25 PM PDT 24
Peak memory 183304 kb
Host smart-e72a7fb0-af2f-4176-9909-eb6f0c158cfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757399543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.2757399543
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.3976334581
Short name T210
Test name
Test status
Simulation time 2110582338 ps
CPU time 11.45 seconds
Started Aug 04 04:41:29 PM PDT 24
Finished Aug 04 04:41:40 PM PDT 24
Peak memory 191548 kb
Host smart-5c54855b-be55-422f-9277-b7570c672ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976334581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.3976334581
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.1125463170
Short name T9
Test name
Test status
Simulation time 488963699217 ps
CPU time 167.15 seconds
Started Aug 04 04:41:26 PM PDT 24
Finished Aug 04 04:44:13 PM PDT 24
Peak memory 183324 kb
Host smart-01fc57bb-0d98-4d93-9f5a-b724c1397fc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125463170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.1125463170
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.2737278084
Short name T228
Test name
Test status
Simulation time 38303906461 ps
CPU time 20.56 seconds
Started Aug 04 04:41:32 PM PDT 24
Finished Aug 04 04:41:52 PM PDT 24
Peak memory 183276 kb
Host smart-8889aff7-263e-491b-86cb-129de5d20eea
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737278084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.2737278084
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_random.2043420280
Short name T66
Test name
Test status
Simulation time 114348348035 ps
CPU time 58.23 seconds
Started Aug 04 04:41:38 PM PDT 24
Finished Aug 04 04:42:37 PM PDT 24
Peak memory 191636 kb
Host smart-6a759aca-59e3-4d66-8e47-6795c10465f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043420280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.2043420280
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.1501168085
Short name T351
Test name
Test status
Simulation time 35921989450 ps
CPU time 30.75 seconds
Started Aug 04 04:41:33 PM PDT 24
Finished Aug 04 04:42:03 PM PDT 24
Peak memory 183384 kb
Host smart-c2b5cfec-c09d-4864-b796-8c53c874f249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501168085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.1501168085
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.1720592337
Short name T335
Test name
Test status
Simulation time 34523230226 ps
CPU time 276.24 seconds
Started Aug 04 04:41:38 PM PDT 24
Finished Aug 04 04:46:15 PM PDT 24
Peak memory 183348 kb
Host smart-d6493332-edd8-45aa-af68-7bbcb41bfb7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720592337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.1720592337
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.2109261196
Short name T245
Test name
Test status
Simulation time 2673718734923 ps
CPU time 774.65 seconds
Started Aug 04 04:41:30 PM PDT 24
Finished Aug 04 04:54:24 PM PDT 24
Peak memory 183348 kb
Host smart-187ea5bb-1a92-4e8c-8f73-d70d0943c592
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109261196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.2109261196
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.2540477932
Short name T402
Test name
Test status
Simulation time 162383428442 ps
CPU time 100.49 seconds
Started Aug 04 04:41:32 PM PDT 24
Finished Aug 04 04:43:12 PM PDT 24
Peak memory 183472 kb
Host smart-e6a443ba-7658-40de-838b-0045b76d3edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540477932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.2540477932
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.1602667363
Short name T293
Test name
Test status
Simulation time 947433176844 ps
CPU time 1091.73 seconds
Started Aug 04 04:41:31 PM PDT 24
Finished Aug 04 04:59:43 PM PDT 24
Peak memory 191528 kb
Host smart-6d443687-a0c5-4dd4-a433-a71f76d37f8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602667363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.1602667363
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.2538250921
Short name T379
Test name
Test status
Simulation time 1334825904 ps
CPU time 2.28 seconds
Started Aug 04 04:41:32 PM PDT 24
Finished Aug 04 04:41:34 PM PDT 24
Peak memory 183064 kb
Host smart-7b793fec-71ab-44c0-a881-4f832439b90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538250921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.2538250921
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.2437826853
Short name T439
Test name
Test status
Simulation time 1368788115960 ps
CPU time 1506.39 seconds
Started Aug 04 04:41:46 PM PDT 24
Finished Aug 04 05:06:52 PM PDT 24
Peak memory 191548 kb
Host smart-4a36abd5-9dd7-49f9-9cc4-43b7e1fbc22d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437826853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.2437826853
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.847322807
Short name T432
Test name
Test status
Simulation time 568352171198 ps
CPU time 266.75 seconds
Started Aug 04 04:41:27 PM PDT 24
Finished Aug 04 04:45:54 PM PDT 24
Peak memory 183364 kb
Host smart-a43e1a39-7ec1-4a25-86c2-11c39100cff5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847322807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.rv_timer_cfg_update_on_fly.847322807
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.3028360966
Short name T411
Test name
Test status
Simulation time 179682698915 ps
CPU time 74.16 seconds
Started Aug 04 04:41:36 PM PDT 24
Finished Aug 04 04:42:50 PM PDT 24
Peak memory 183376 kb
Host smart-6612627a-a9e5-4a34-85d5-af7cd25b7a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028360966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.3028360966
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.495927601
Short name T155
Test name
Test status
Simulation time 311037311469 ps
CPU time 257.02 seconds
Started Aug 04 04:41:27 PM PDT 24
Finished Aug 04 04:45:44 PM PDT 24
Peak memory 195164 kb
Host smart-f39e2f1a-9389-4fab-943f-d8ac334958b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495927601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.495927601
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.3604256404
Short name T407
Test name
Test status
Simulation time 132502013 ps
CPU time 0.71 seconds
Started Aug 04 04:41:29 PM PDT 24
Finished Aug 04 04:41:30 PM PDT 24
Peak memory 183072 kb
Host smart-95d0b913-d6f7-4a51-acb7-168f6ceb43e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604256404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.3604256404
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.3410620922
Short name T175
Test name
Test status
Simulation time 444452191886 ps
CPU time 683.39 seconds
Started Aug 04 04:41:28 PM PDT 24
Finished Aug 04 04:52:52 PM PDT 24
Peak memory 191580 kb
Host smart-5b8e8fcb-5ff9-4983-85fc-51e40a63f93c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410620922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.3410620922
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.2573069469
Short name T389
Test name
Test status
Simulation time 478245057915 ps
CPU time 167.97 seconds
Started Aug 04 04:41:35 PM PDT 24
Finished Aug 04 04:44:23 PM PDT 24
Peak memory 183376 kb
Host smart-48d66a41-ede2-4ae8-b880-f7377f2d237b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573069469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.2573069469
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.130568284
Short name T371
Test name
Test status
Simulation time 663739005 ps
CPU time 1.53 seconds
Started Aug 04 04:41:26 PM PDT 24
Finished Aug 04 04:41:28 PM PDT 24
Peak memory 183076 kb
Host smart-23add143-a4cb-480c-b5b1-7798f98af81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130568284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.130568284
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.4248726421
Short name T326
Test name
Test status
Simulation time 20814208576 ps
CPU time 31.6 seconds
Started Aug 04 04:41:35 PM PDT 24
Finished Aug 04 04:42:06 PM PDT 24
Peak memory 183268 kb
Host smart-ae482ac2-fbf6-4a3c-ad98-3935710a35ee
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248726421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.4248726421
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.4258491518
Short name T368
Test name
Test status
Simulation time 10307594916 ps
CPU time 7.72 seconds
Started Aug 04 04:41:36 PM PDT 24
Finished Aug 04 04:41:43 PM PDT 24
Peak memory 183344 kb
Host smart-24e1956b-3a77-4aed-ae04-d8b89b0867be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258491518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.4258491518
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.1784696183
Short name T178
Test name
Test status
Simulation time 928721410554 ps
CPU time 331.91 seconds
Started Aug 04 04:41:35 PM PDT 24
Finished Aug 04 04:47:07 PM PDT 24
Peak memory 196328 kb
Host smart-58d0a51a-d3ab-4b64-8995-459a356f9ec0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784696183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.1784696183
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.1093917103
Short name T362
Test name
Test status
Simulation time 578741813212 ps
CPU time 310.98 seconds
Started Aug 04 04:41:37 PM PDT 24
Finished Aug 04 04:46:48 PM PDT 24
Peak memory 183356 kb
Host smart-845c2be9-d067-4bcf-bbb3-db835e863b6f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093917103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.1093917103
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.2810783135
Short name T374
Test name
Test status
Simulation time 46881475593 ps
CPU time 68.28 seconds
Started Aug 04 04:41:32 PM PDT 24
Finished Aug 04 04:42:40 PM PDT 24
Peak memory 183656 kb
Host smart-bf0f457c-1454-4563-9c8a-e507e17eb9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810783135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.2810783135
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.2289733543
Short name T189
Test name
Test status
Simulation time 183024860073 ps
CPU time 73.68 seconds
Started Aug 04 04:41:40 PM PDT 24
Finished Aug 04 04:42:54 PM PDT 24
Peak memory 191560 kb
Host smart-da16b569-a538-4c2e-b4c2-ce7d3142c865
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289733543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.2289733543
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.3877053987
Short name T8
Test name
Test status
Simulation time 149700185 ps
CPU time 1.04 seconds
Started Aug 04 04:41:48 PM PDT 24
Finished Aug 04 04:41:49 PM PDT 24
Peak memory 194124 kb
Host smart-bb657dee-029b-4361-80c7-63d61fd23c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877053987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.3877053987
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.7247190
Short name T444
Test name
Test status
Simulation time 22902546 ps
CPU time 0.58 seconds
Started Aug 04 04:41:35 PM PDT 24
Finished Aug 04 04:41:36 PM PDT 24
Peak memory 183096 kb
Host smart-4962afa2-984b-4ce4-b623-4f39852cd611
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7247190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_a
ll_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all.7247190
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.4033566335
Short name T112
Test name
Test status
Simulation time 772893716362 ps
CPU time 1169.69 seconds
Started Aug 04 04:41:35 PM PDT 24
Finished Aug 04 05:01:05 PM PDT 24
Peak memory 183288 kb
Host smart-c619e92b-c43c-4f02-a23f-c9f97790a23c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033566335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.4033566335
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.2790873748
Short name T420
Test name
Test status
Simulation time 389569076504 ps
CPU time 182.84 seconds
Started Aug 04 04:41:44 PM PDT 24
Finished Aug 04 04:44:47 PM PDT 24
Peak memory 183356 kb
Host smart-f5a2d8f3-4a13-44ec-95ea-a2530ad3e4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790873748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.2790873748
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.1273278858
Short name T48
Test name
Test status
Simulation time 21223848 ps
CPU time 0.53 seconds
Started Aug 04 04:41:40 PM PDT 24
Finished Aug 04 04:41:40 PM PDT 24
Peak memory 183184 kb
Host smart-f798aee3-c446-490b-921d-c1a8b57f6a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273278858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.1273278858
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.3475609026
Short name T65
Test name
Test status
Simulation time 181415667933 ps
CPU time 292.84 seconds
Started Aug 04 04:41:44 PM PDT 24
Finished Aug 04 04:46:37 PM PDT 24
Peak memory 195972 kb
Host smart-08ca7a9b-f135-4a57-a247-faa2d4185fe7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475609026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.3475609026
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.717628509
Short name T142
Test name
Test status
Simulation time 429606629459 ps
CPU time 208.44 seconds
Started Aug 04 04:41:40 PM PDT 24
Finished Aug 04 04:45:08 PM PDT 24
Peak memory 183356 kb
Host smart-6a88a7f9-f43c-4be8-8521-f81bdc990904
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717628509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.rv_timer_cfg_update_on_fly.717628509
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.4260138709
Short name T370
Test name
Test status
Simulation time 167570438863 ps
CPU time 143.81 seconds
Started Aug 04 04:41:32 PM PDT 24
Finished Aug 04 04:43:56 PM PDT 24
Peak memory 183260 kb
Host smart-bc54bdcb-5489-4f1f-b908-e1ec12f0f38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260138709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.4260138709
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.4116033278
Short name T186
Test name
Test status
Simulation time 70790103706 ps
CPU time 361.3 seconds
Started Aug 04 04:41:33 PM PDT 24
Finished Aug 04 04:47:35 PM PDT 24
Peak memory 191508 kb
Host smart-de55a63a-7a45-4a36-b040-89e4ed956574
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116033278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.4116033278
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.3930148419
Short name T320
Test name
Test status
Simulation time 78488879094 ps
CPU time 250.85 seconds
Started Aug 04 04:41:32 PM PDT 24
Finished Aug 04 04:45:43 PM PDT 24
Peak memory 183296 kb
Host smart-a285f19b-80f4-47b6-b288-20f7e59f6bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930148419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.3930148419
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.3015983105
Short name T291
Test name
Test status
Simulation time 273469900771 ps
CPU time 420.93 seconds
Started Aug 04 04:41:35 PM PDT 24
Finished Aug 04 04:48:36 PM PDT 24
Peak memory 191624 kb
Host smart-8bb65cde-626d-43c5-b097-cc1d640cff75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015983105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.3015983105
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.4275330419
Short name T338
Test name
Test status
Simulation time 677592492288 ps
CPU time 391.06 seconds
Started Aug 04 04:41:17 PM PDT 24
Finished Aug 04 04:47:49 PM PDT 24
Peak memory 183372 kb
Host smart-fb068c4f-008d-4e1b-9471-97323269037f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275330419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.4275330419
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.3724145516
Short name T69
Test name
Test status
Simulation time 419961652102 ps
CPU time 225.62 seconds
Started Aug 04 04:41:16 PM PDT 24
Finished Aug 04 04:45:02 PM PDT 24
Peak memory 183448 kb
Host smart-685cfbcd-3b91-4f8e-a90c-b8954a4d6665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724145516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.3724145516
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.4032823594
Short name T136
Test name
Test status
Simulation time 222197323943 ps
CPU time 158.64 seconds
Started Aug 04 04:41:13 PM PDT 24
Finished Aug 04 04:43:51 PM PDT 24
Peak memory 191596 kb
Host smart-010b7894-152b-41d0-b1ef-e0572e5e9d0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032823594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.4032823594
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.501620444
Short name T14
Test name
Test status
Simulation time 87524702 ps
CPU time 0.86 seconds
Started Aug 04 04:41:04 PM PDT 24
Finished Aug 04 04:41:05 PM PDT 24
Peak memory 214848 kb
Host smart-3fe3ca3c-f3a2-447a-b285-9021d0a5e5d2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501620444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.501620444
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.3288271468
Short name T258
Test name
Test status
Simulation time 126960734500 ps
CPU time 64.01 seconds
Started Aug 04 04:41:38 PM PDT 24
Finished Aug 04 04:42:42 PM PDT 24
Peak memory 183384 kb
Host smart-fd780302-4587-4816-8930-88c2cb6024d2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288271468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.3288271468
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.2443300102
Short name T427
Test name
Test status
Simulation time 170488747244 ps
CPU time 256.22 seconds
Started Aug 04 04:41:39 PM PDT 24
Finished Aug 04 04:45:56 PM PDT 24
Peak memory 183356 kb
Host smart-0a285ca8-8360-41ae-8b30-7fa578df24fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443300102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.2443300102
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.3918311899
Short name T339
Test name
Test status
Simulation time 840428750 ps
CPU time 1.9 seconds
Started Aug 04 04:41:41 PM PDT 24
Finished Aug 04 04:41:43 PM PDT 24
Peak memory 183100 kb
Host smart-9e5ba33a-a5ca-4fae-9ccb-94db5862f86c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918311899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.3918311899
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.2398068426
Short name T364
Test name
Test status
Simulation time 16136542568 ps
CPU time 278.21 seconds
Started Aug 04 04:41:46 PM PDT 24
Finished Aug 04 04:46:24 PM PDT 24
Peak memory 183336 kb
Host smart-1210d86d-1542-46b1-a03e-55069af73483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398068426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.2398068426
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.2903770183
Short name T218
Test name
Test status
Simulation time 343479201731 ps
CPU time 171.43 seconds
Started Aug 04 04:41:42 PM PDT 24
Finished Aug 04 04:44:34 PM PDT 24
Peak memory 183356 kb
Host smart-ab0ab310-f3c4-4f9f-aa38-3433104733fc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903770183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.2903770183
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.1468134849
Short name T405
Test name
Test status
Simulation time 103273280517 ps
CPU time 63.97 seconds
Started Aug 04 04:41:39 PM PDT 24
Finished Aug 04 04:42:43 PM PDT 24
Peak memory 183300 kb
Host smart-8051655d-9ddc-4427-9696-3dea31add723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468134849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.1468134849
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.632251280
Short name T442
Test name
Test status
Simulation time 735126793560 ps
CPU time 389.49 seconds
Started Aug 04 04:41:40 PM PDT 24
Finished Aug 04 04:48:10 PM PDT 24
Peak memory 191552 kb
Host smart-b5510cf2-cc5e-4ac5-b91f-be0231d97c81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632251280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.632251280
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.2220897209
Short name T343
Test name
Test status
Simulation time 39066029972 ps
CPU time 30.49 seconds
Started Aug 04 04:41:48 PM PDT 24
Finished Aug 04 04:42:19 PM PDT 24
Peak memory 183400 kb
Host smart-0205d866-fa94-43b8-85fd-5f1cf2a323cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220897209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.2220897209
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.457550058
Short name T253
Test name
Test status
Simulation time 245258066251 ps
CPU time 359.75 seconds
Started Aug 04 04:41:50 PM PDT 24
Finished Aug 04 04:47:50 PM PDT 24
Peak memory 183372 kb
Host smart-8fb59ad5-f96b-4d0e-8bd2-c34a1356b558
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457550058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.rv_timer_cfg_update_on_fly.457550058
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.2523313574
Short name T397
Test name
Test status
Simulation time 297356873766 ps
CPU time 103.99 seconds
Started Aug 04 04:41:42 PM PDT 24
Finished Aug 04 04:43:26 PM PDT 24
Peak memory 183364 kb
Host smart-8498e5b6-1158-4373-9035-a72e23a6e717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523313574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.2523313574
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.2568599245
Short name T269
Test name
Test status
Simulation time 511561948237 ps
CPU time 309.88 seconds
Started Aug 04 04:41:43 PM PDT 24
Finished Aug 04 04:46:53 PM PDT 24
Peak memory 194808 kb
Host smart-fbda1c45-a3a7-4a16-82fe-342057ec88aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568599245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.2568599245
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.794652224
Short name T129
Test name
Test status
Simulation time 218040596597 ps
CPU time 180.49 seconds
Started Aug 04 04:41:49 PM PDT 24
Finished Aug 04 04:44:50 PM PDT 24
Peak memory 183356 kb
Host smart-db070e76-9718-4090-8ac2-c411fab151e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794652224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.794652224
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all_with_rand_reset.4051689451
Short name T38
Test name
Test status
Simulation time 77800182826 ps
CPU time 156.57 seconds
Started Aug 04 04:41:49 PM PDT 24
Finished Aug 04 04:44:26 PM PDT 24
Peak memory 198132 kb
Host smart-9cd80e78-a04a-4a25-b73b-59cbcad20ec1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051689451 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all_with_rand_reset.4051689451
Directory /workspace/42.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.2734039850
Short name T310
Test name
Test status
Simulation time 6081000703 ps
CPU time 9.23 seconds
Started Aug 04 04:41:36 PM PDT 24
Finished Aug 04 04:41:46 PM PDT 24
Peak memory 183308 kb
Host smart-4368fd7e-70db-4d7b-b3ed-35906c562a26
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734039850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.2734039850
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.3810034436
Short name T415
Test name
Test status
Simulation time 310796110236 ps
CPU time 134.07 seconds
Started Aug 04 04:41:43 PM PDT 24
Finished Aug 04 04:43:57 PM PDT 24
Peak memory 183348 kb
Host smart-26c3e576-0958-48dd-b889-ab3502b9aaea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810034436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.3810034436
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.2178290204
Short name T72
Test name
Test status
Simulation time 25796472002 ps
CPU time 43.9 seconds
Started Aug 04 04:41:44 PM PDT 24
Finished Aug 04 04:42:28 PM PDT 24
Peak memory 183384 kb
Host smart-90a53e5e-18af-4414-94c3-c8ad76390cdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178290204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.2178290204
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.499065342
Short name T297
Test name
Test status
Simulation time 42414769356 ps
CPU time 19.06 seconds
Started Aug 04 04:41:46 PM PDT 24
Finished Aug 04 04:42:05 PM PDT 24
Peak memory 183156 kb
Host smart-7915657d-82f7-4eae-98da-b9858e67b099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499065342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.499065342
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.372220200
Short name T143
Test name
Test status
Simulation time 19069746973 ps
CPU time 16.72 seconds
Started Aug 04 04:41:40 PM PDT 24
Finished Aug 04 04:41:57 PM PDT 24
Peak memory 183352 kb
Host smart-34c80b93-7f40-4fc0-81b3-783a969d5e02
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372220200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.rv_timer_cfg_update_on_fly.372220200
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.4281475053
Short name T429
Test name
Test status
Simulation time 437433486540 ps
CPU time 166.79 seconds
Started Aug 04 04:41:42 PM PDT 24
Finished Aug 04 04:44:29 PM PDT 24
Peak memory 183356 kb
Host smart-de9b03e8-d95e-4568-93da-885b93599b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281475053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.4281475053
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.1147978584
Short name T219
Test name
Test status
Simulation time 227131817005 ps
CPU time 1538.34 seconds
Started Aug 04 04:41:39 PM PDT 24
Finished Aug 04 05:07:18 PM PDT 24
Peak memory 191576 kb
Host smart-9b29f535-965c-4d07-8923-850ddc75a351
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147978584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.1147978584
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.3322182252
Short name T394
Test name
Test status
Simulation time 122620714305 ps
CPU time 179.46 seconds
Started Aug 04 04:41:46 PM PDT 24
Finished Aug 04 04:44:46 PM PDT 24
Peak memory 183440 kb
Host smart-d99f5ce3-0895-4ee4-aecd-0d79d26113c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322182252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.3322182252
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.3062503242
Short name T324
Test name
Test status
Simulation time 460702867232 ps
CPU time 1608.31 seconds
Started Aug 04 04:41:44 PM PDT 24
Finished Aug 04 05:08:32 PM PDT 24
Peak memory 191604 kb
Host smart-5cca2c6d-28aa-462d-ad48-0c92eeaa3890
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062503242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.3062503242
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.4076064430
Short name T333
Test name
Test status
Simulation time 28641791346 ps
CPU time 38.77 seconds
Started Aug 04 04:41:47 PM PDT 24
Finished Aug 04 04:42:26 PM PDT 24
Peak memory 191496 kb
Host smart-4c21d484-25f7-40c1-ad97-3d59d27907e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076064430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.4076064430
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.144129089
Short name T179
Test name
Test status
Simulation time 208691611253 ps
CPU time 358.91 seconds
Started Aug 04 04:41:49 PM PDT 24
Finished Aug 04 04:47:48 PM PDT 24
Peak memory 183372 kb
Host smart-92424e7a-334b-4f6f-ae6f-0a6260682377
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144129089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.rv_timer_cfg_update_on_fly.144129089
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.3407489536
Short name T373
Test name
Test status
Simulation time 82048926425 ps
CPU time 126 seconds
Started Aug 04 04:41:41 PM PDT 24
Finished Aug 04 04:43:47 PM PDT 24
Peak memory 183340 kb
Host smart-fa1b8efd-e3d8-4038-a204-eeacdfba3e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407489536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.3407489536
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.3753153131
Short name T23
Test name
Test status
Simulation time 43546022354 ps
CPU time 61.4 seconds
Started Aug 04 04:41:44 PM PDT 24
Finished Aug 04 04:42:45 PM PDT 24
Peak memory 183376 kb
Host smart-3dfc1959-59d4-406b-bcb4-6af3bff7eee2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753153131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.3753153131
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.3690023455
Short name T430
Test name
Test status
Simulation time 137645496166 ps
CPU time 119.63 seconds
Started Aug 04 04:41:40 PM PDT 24
Finished Aug 04 04:43:39 PM PDT 24
Peak memory 195368 kb
Host smart-ebec44eb-5459-40b6-9018-3da717b3f690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690023455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.3690023455
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.1772590917
Short name T134
Test name
Test status
Simulation time 541186217574 ps
CPU time 851.74 seconds
Started Aug 04 04:41:45 PM PDT 24
Finished Aug 04 04:55:57 PM PDT 24
Peak memory 183288 kb
Host smart-c9d8087e-3a8f-47d0-9f23-2b51f9debee4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772590917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.1772590917
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.3683696940
Short name T376
Test name
Test status
Simulation time 386746256372 ps
CPU time 140.91 seconds
Started Aug 04 04:41:44 PM PDT 24
Finished Aug 04 04:44:05 PM PDT 24
Peak memory 183352 kb
Host smart-bfd65299-1509-4a54-a128-49ad6e149d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683696940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.3683696940
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.1179673449
Short name T190
Test name
Test status
Simulation time 121802531321 ps
CPU time 200.93 seconds
Started Aug 04 04:41:51 PM PDT 24
Finished Aug 04 04:45:12 PM PDT 24
Peak memory 191664 kb
Host smart-4b533d32-005e-4126-aa94-aee02c1c1651
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179673449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.1179673449
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.1153443622
Short name T406
Test name
Test status
Simulation time 42985642 ps
CPU time 0.69 seconds
Started Aug 04 04:41:45 PM PDT 24
Finished Aug 04 04:41:46 PM PDT 24
Peak memory 192824 kb
Host smart-39f18c5f-adc3-4054-8e29-80e81abcdc5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153443622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.1153443622
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.446999742
Short name T163
Test name
Test status
Simulation time 840915267441 ps
CPU time 617.8 seconds
Started Aug 04 04:41:47 PM PDT 24
Finished Aug 04 04:52:05 PM PDT 24
Peak memory 191584 kb
Host smart-82a6e256-8d13-4cfe-a939-73e746d3de59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446999742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all.
446999742
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.3890649450
Short name T309
Test name
Test status
Simulation time 74731659484 ps
CPU time 76.81 seconds
Started Aug 04 04:41:47 PM PDT 24
Finished Aug 04 04:43:04 PM PDT 24
Peak memory 183368 kb
Host smart-b73aa18c-829b-435d-bb74-7adf8377bc3a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890649450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.3890649450
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.1307434740
Short name T381
Test name
Test status
Simulation time 568316458539 ps
CPU time 241.12 seconds
Started Aug 04 04:41:41 PM PDT 24
Finished Aug 04 04:45:43 PM PDT 24
Peak memory 183440 kb
Host smart-6fdf96ea-2201-4afe-b669-813f97dd7c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307434740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.1307434740
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.1856790946
Short name T330
Test name
Test status
Simulation time 3625221226 ps
CPU time 1.64 seconds
Started Aug 04 04:41:49 PM PDT 24
Finished Aug 04 04:41:51 PM PDT 24
Peak memory 183144 kb
Host smart-bcf2e861-4fbf-4292-b5b5-ac5af268219c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856790946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.1856790946
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.4028489916
Short name T386
Test name
Test status
Simulation time 91565082 ps
CPU time 0.63 seconds
Started Aug 04 04:41:46 PM PDT 24
Finished Aug 04 04:41:47 PM PDT 24
Peak memory 183132 kb
Host smart-fb32e431-8ceb-444a-95da-7e9bc02317dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028489916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.4028489916
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.3470405014
Short name T341
Test name
Test status
Simulation time 17528494612 ps
CPU time 26.69 seconds
Started Aug 04 04:41:46 PM PDT 24
Finished Aug 04 04:42:12 PM PDT 24
Peak memory 182980 kb
Host smart-af7d5ce4-5777-4bde-bae2-ebbfb45c81d7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470405014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.3470405014
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.696101704
Short name T367
Test name
Test status
Simulation time 34308250326 ps
CPU time 56.35 seconds
Started Aug 04 04:41:45 PM PDT 24
Finished Aug 04 04:42:42 PM PDT 24
Peak memory 183472 kb
Host smart-c17d02c7-32dc-4ee6-a6a0-eb815bd1c244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696101704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.696101704
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.3815879829
Short name T314
Test name
Test status
Simulation time 154166831250 ps
CPU time 388.58 seconds
Started Aug 04 04:41:45 PM PDT 24
Finished Aug 04 04:48:14 PM PDT 24
Peak memory 191672 kb
Host smart-fe4500d3-33be-4a14-b061-01146d635eb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815879829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.3815879829
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.2721438679
Short name T49
Test name
Test status
Simulation time 116298435 ps
CPU time 0.7 seconds
Started Aug 04 04:41:43 PM PDT 24
Finished Aug 04 04:41:43 PM PDT 24
Peak memory 183092 kb
Host smart-dfa28ecc-76c6-413e-b512-c8168a62dc27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721438679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.2721438679
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.142911058
Short name T360
Test name
Test status
Simulation time 32927802480 ps
CPU time 59.12 seconds
Started Aug 04 04:41:11 PM PDT 24
Finished Aug 04 04:42:10 PM PDT 24
Peak memory 183344 kb
Host smart-72fe6d80-e47e-4345-aec4-a791c39d308d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142911058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.rv_timer_cfg_update_on_fly.142911058
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.3219079184
Short name T24
Test name
Test status
Simulation time 450805833994 ps
CPU time 180.43 seconds
Started Aug 04 04:41:08 PM PDT 24
Finished Aug 04 04:44:08 PM PDT 24
Peak memory 183400 kb
Host smart-23e2483e-2676-4287-b1f3-f7e827d02d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219079184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.3219079184
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.2676796840
Short name T4
Test name
Test status
Simulation time 418570899750 ps
CPU time 279.62 seconds
Started Aug 04 04:41:10 PM PDT 24
Finished Aug 04 04:45:50 PM PDT 24
Peak memory 191616 kb
Host smart-36353929-22df-4ba7-bb33-d677ec735a46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676796840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.2676796840
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.3964490477
Short name T440
Test name
Test status
Simulation time 65363922704 ps
CPU time 98.99 seconds
Started Aug 04 04:41:13 PM PDT 24
Finished Aug 04 04:42:52 PM PDT 24
Peak memory 183320 kb
Host smart-97793511-4397-43b6-86d0-308f44e4b917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964490477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.3964490477
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.3445388860
Short name T146
Test name
Test status
Simulation time 92717568367 ps
CPU time 132.86 seconds
Started Aug 04 04:41:46 PM PDT 24
Finished Aug 04 04:43:59 PM PDT 24
Peak memory 183400 kb
Host smart-597823d9-87df-47ef-a9db-ae917aa87d0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445388860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.3445388860
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.1833205946
Short name T431
Test name
Test status
Simulation time 13107608880 ps
CPU time 21.66 seconds
Started Aug 04 04:41:42 PM PDT 24
Finished Aug 04 04:42:04 PM PDT 24
Peak memory 183316 kb
Host smart-2944b674-c009-4385-856e-4545e779fa5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833205946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.1833205946
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.37855943
Short name T181
Test name
Test status
Simulation time 486559272274 ps
CPU time 603.67 seconds
Started Aug 04 04:41:45 PM PDT 24
Finished Aug 04 04:51:49 PM PDT 24
Peak memory 191612 kb
Host smart-f88c512d-e520-4ee3-8380-0338807e6a45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37855943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.37855943
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.3840601469
Short name T344
Test name
Test status
Simulation time 82919251261 ps
CPU time 116.87 seconds
Started Aug 04 04:41:49 PM PDT 24
Finished Aug 04 04:43:46 PM PDT 24
Peak memory 191600 kb
Host smart-4229b95a-db30-4014-92e6-e43602cd76c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840601469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.3840601469
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.546418007
Short name T352
Test name
Test status
Simulation time 9062066022 ps
CPU time 16.85 seconds
Started Aug 04 04:41:47 PM PDT 24
Finished Aug 04 04:42:04 PM PDT 24
Peak memory 183344 kb
Host smart-13a1a2d0-94c3-441e-8e2e-1c5902681274
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546418007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.546418007
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.1629552001
Short name T284
Test name
Test status
Simulation time 253809010068 ps
CPU time 120.65 seconds
Started Aug 04 04:41:47 PM PDT 24
Finished Aug 04 04:43:47 PM PDT 24
Peak memory 191560 kb
Host smart-a68608f8-ad96-4952-bd76-e05bb64f7730
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629552001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.1629552001
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.2219844772
Short name T286
Test name
Test status
Simulation time 542860666810 ps
CPU time 301.48 seconds
Started Aug 04 04:41:49 PM PDT 24
Finished Aug 04 04:46:51 PM PDT 24
Peak memory 193640 kb
Host smart-a6b01e63-4fc7-4e28-9bfc-8f62a8e99a2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219844772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.2219844772
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.3400140079
Short name T149
Test name
Test status
Simulation time 420657545531 ps
CPU time 1465.57 seconds
Started Aug 04 04:41:51 PM PDT 24
Finished Aug 04 05:06:17 PM PDT 24
Peak memory 191596 kb
Host smart-b1fd5ffe-a054-4d66-a80a-e01c78d99df4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400140079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.3400140079
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.1653332094
Short name T348
Test name
Test status
Simulation time 1036634855575 ps
CPU time 541.96 seconds
Started Aug 04 04:41:14 PM PDT 24
Finished Aug 04 04:50:16 PM PDT 24
Peak memory 183372 kb
Host smart-0b77efff-dc8d-459b-a81c-6314bbdb687e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653332094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.1653332094
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.4205956274
Short name T382
Test name
Test status
Simulation time 445774032248 ps
CPU time 179.42 seconds
Started Aug 04 04:41:13 PM PDT 24
Finished Aug 04 04:44:13 PM PDT 24
Peak memory 183396 kb
Host smart-905eadc3-7a63-4867-92ee-3c16f65320f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205956274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.4205956274
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.1956130956
Short name T337
Test name
Test status
Simulation time 17587709007 ps
CPU time 35.71 seconds
Started Aug 04 04:41:10 PM PDT 24
Finished Aug 04 04:41:46 PM PDT 24
Peak memory 183376 kb
Host smart-69d371b0-8086-4ca7-9663-ae1ddd7968df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956130956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.1956130956
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.3765884389
Short name T119
Test name
Test status
Simulation time 19640591836 ps
CPU time 44.94 seconds
Started Aug 04 04:41:08 PM PDT 24
Finished Aug 04 04:41:53 PM PDT 24
Peak memory 183340 kb
Host smart-270812ad-7238-49d3-b5cf-3b1ee2368951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765884389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.3765884389
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.2415732307
Short name T22
Test name
Test status
Simulation time 172524255424 ps
CPU time 70.04 seconds
Started Aug 04 04:41:44 PM PDT 24
Finished Aug 04 04:42:54 PM PDT 24
Peak memory 183344 kb
Host smart-9fc6836f-7f5f-4414-8d82-2e5fa2721e28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415732307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.2415732307
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.3302183322
Short name T139
Test name
Test status
Simulation time 174876699333 ps
CPU time 2354.13 seconds
Started Aug 04 04:41:44 PM PDT 24
Finished Aug 04 05:20:58 PM PDT 24
Peak memory 191624 kb
Host smart-2f8763d9-f360-474a-9a7b-fa3ca5806a3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302183322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.3302183322
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.2052999106
Short name T270
Test name
Test status
Simulation time 535859883462 ps
CPU time 73.06 seconds
Started Aug 04 04:41:50 PM PDT 24
Finished Aug 04 04:43:03 PM PDT 24
Peak memory 183328 kb
Host smart-2b6adadb-1b26-40aa-8007-d5b160c1e473
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052999106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.2052999106
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.3493240758
Short name T224
Test name
Test status
Simulation time 250021366288 ps
CPU time 376.37 seconds
Started Aug 04 04:41:48 PM PDT 24
Finished Aug 04 04:48:05 PM PDT 24
Peak memory 191592 kb
Host smart-2c45b252-788c-43be-a1b5-0a2ba6182c5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493240758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.3493240758
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.3369353351
Short name T3
Test name
Test status
Simulation time 279025827608 ps
CPU time 1719.23 seconds
Started Aug 04 04:41:46 PM PDT 24
Finished Aug 04 05:10:25 PM PDT 24
Peak memory 191048 kb
Host smart-58f9630f-7bbc-4f09-888b-6f6c8931a79b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369353351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.3369353351
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.142937722
Short name T220
Test name
Test status
Simulation time 37143459647 ps
CPU time 58.81 seconds
Started Aug 04 04:41:47 PM PDT 24
Finished Aug 04 04:42:46 PM PDT 24
Peak memory 183400 kb
Host smart-9b0efaaf-90c9-4928-9e18-33cc2f1a9cdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142937722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.142937722
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.2112208395
Short name T68
Test name
Test status
Simulation time 902024096538 ps
CPU time 261.71 seconds
Started Aug 04 04:41:46 PM PDT 24
Finished Aug 04 04:46:08 PM PDT 24
Peak memory 191456 kb
Host smart-8ac0ee81-2d13-46bf-8592-170b88399b23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112208395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.2112208395
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.2504077102
Short name T225
Test name
Test status
Simulation time 98548640368 ps
CPU time 129.28 seconds
Started Aug 04 04:41:49 PM PDT 24
Finished Aug 04 04:43:58 PM PDT 24
Peak memory 195064 kb
Host smart-381ef768-11ea-4e11-9b38-26392b280c32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504077102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.2504077102
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.103055130
Short name T271
Test name
Test status
Simulation time 444414062203 ps
CPU time 469.63 seconds
Started Aug 04 04:41:51 PM PDT 24
Finished Aug 04 04:49:41 PM PDT 24
Peak memory 191596 kb
Host smart-5bee3f0f-6388-4c9a-8bcc-1f79cc91d2ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103055130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.103055130
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.2167178222
Short name T157
Test name
Test status
Simulation time 3307865925260 ps
CPU time 472.96 seconds
Started Aug 04 04:41:51 PM PDT 24
Finished Aug 04 04:49:44 PM PDT 24
Peak memory 191588 kb
Host smart-8eca0691-1495-40d9-b597-a0c51a177e24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167178222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.2167178222
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.3628436198
Short name T449
Test name
Test status
Simulation time 578748033 ps
CPU time 1.45 seconds
Started Aug 04 04:41:13 PM PDT 24
Finished Aug 04 04:41:14 PM PDT 24
Peak memory 183144 kb
Host smart-30e2fb26-197f-4e74-93f6-a1afc0d136fe
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628436198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.3628436198
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.2438447346
Short name T401
Test name
Test status
Simulation time 549280724860 ps
CPU time 231.45 seconds
Started Aug 04 04:41:13 PM PDT 24
Finished Aug 04 04:45:05 PM PDT 24
Peak memory 183448 kb
Host smart-116df059-0bdb-4a9c-9a56-79c1c5c69d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438447346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.2438447346
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.1939283163
Short name T347
Test name
Test status
Simulation time 52812861910 ps
CPU time 117.95 seconds
Started Aug 04 04:41:06 PM PDT 24
Finished Aug 04 04:43:04 PM PDT 24
Peak memory 183368 kb
Host smart-2186ab4e-7238-4cff-9094-f738730195a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939283163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.1939283163
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.1521582445
Short name T398
Test name
Test status
Simulation time 1892852132847 ps
CPU time 307.77 seconds
Started Aug 04 04:41:16 PM PDT 24
Finished Aug 04 04:46:24 PM PDT 24
Peak memory 183356 kb
Host smart-4bb3aede-275c-4d12-88d8-d78212ea684c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521582445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
1521582445
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/70.rv_timer_random.727829007
Short name T138
Test name
Test status
Simulation time 68327346466 ps
CPU time 92.27 seconds
Started Aug 04 04:41:52 PM PDT 24
Finished Aug 04 04:43:25 PM PDT 24
Peak memory 191556 kb
Host smart-28b330b4-6ee9-4a35-864d-1c8597828574
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727829007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.727829007
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.3480806976
Short name T124
Test name
Test status
Simulation time 76297559906 ps
CPU time 1964.1 seconds
Started Aug 04 04:41:43 PM PDT 24
Finished Aug 04 05:14:28 PM PDT 24
Peak memory 191576 kb
Host smart-ff896b49-c294-4493-9839-70db71572d0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480806976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.3480806976
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.1648442517
Short name T130
Test name
Test status
Simulation time 34847914917 ps
CPU time 49.55 seconds
Started Aug 04 04:41:53 PM PDT 24
Finished Aug 04 04:42:42 PM PDT 24
Peak memory 191456 kb
Host smart-54f13e84-8717-4c78-81b2-30021178c242
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648442517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.1648442517
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.1920068162
Short name T416
Test name
Test status
Simulation time 9302432274 ps
CPU time 11.58 seconds
Started Aug 04 04:41:46 PM PDT 24
Finished Aug 04 04:41:58 PM PDT 24
Peak memory 183192 kb
Host smart-553dda02-01ad-4f12-b418-f1e0822d20be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920068162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.1920068162
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.2493848853
Short name T176
Test name
Test status
Simulation time 1181193459216 ps
CPU time 865.13 seconds
Started Aug 04 04:41:51 PM PDT 24
Finished Aug 04 04:56:17 PM PDT 24
Peak memory 191576 kb
Host smart-f9d8da40-9e98-43d9-b3b0-6bbe90461d03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493848853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.2493848853
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.3240463626
Short name T312
Test name
Test status
Simulation time 103822004967 ps
CPU time 209.72 seconds
Started Aug 04 04:41:51 PM PDT 24
Finished Aug 04 04:45:20 PM PDT 24
Peak memory 191488 kb
Host smart-dc3a165b-cc2f-4d67-be3c-c1d5f8693d18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240463626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.3240463626
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.167804698
Short name T150
Test name
Test status
Simulation time 331216248339 ps
CPU time 203.05 seconds
Started Aug 04 04:41:51 PM PDT 24
Finished Aug 04 04:45:14 PM PDT 24
Peak memory 193748 kb
Host smart-7c8ac421-2b14-47ec-9148-be5c5eaa9e4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167804698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.167804698
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.3080452707
Short name T433
Test name
Test status
Simulation time 51296906179 ps
CPU time 21.87 seconds
Started Aug 04 04:41:55 PM PDT 24
Finished Aug 04 04:42:17 PM PDT 24
Peak memory 183412 kb
Host smart-0d026a61-f98b-4fb8-87b6-bf215e61c9d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080452707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.3080452707
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.1229256199
Short name T355
Test name
Test status
Simulation time 554075806312 ps
CPU time 317.98 seconds
Started Aug 04 04:41:07 PM PDT 24
Finished Aug 04 04:46:25 PM PDT 24
Peak memory 183312 kb
Host smart-58a5ad87-acde-48b8-8074-8f17dcdb4048
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229256199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.1229256199
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.3386648718
Short name T380
Test name
Test status
Simulation time 694928075689 ps
CPU time 178.5 seconds
Started Aug 04 04:41:13 PM PDT 24
Finished Aug 04 04:44:12 PM PDT 24
Peak memory 183364 kb
Host smart-9d226d0f-75c0-4271-9e67-d903b580f632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386648718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.3386648718
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.2664252457
Short name T441
Test name
Test status
Simulation time 101671911727 ps
CPU time 79.71 seconds
Started Aug 04 04:41:08 PM PDT 24
Finished Aug 04 04:42:28 PM PDT 24
Peak memory 191540 kb
Host smart-71b70707-85ab-4b59-bf37-21528b0edbb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664252457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.2664252457
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.166129492
Short name T340
Test name
Test status
Simulation time 78328235962 ps
CPU time 40.91 seconds
Started Aug 04 04:41:09 PM PDT 24
Finished Aug 04 04:41:50 PM PDT 24
Peak memory 191604 kb
Host smart-00999b8d-41b0-4f22-ace1-9e72906112d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166129492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.166129492
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.4079255412
Short name T34
Test name
Test status
Simulation time 577303561329 ps
CPU time 1012.28 seconds
Started Aug 04 04:41:10 PM PDT 24
Finished Aug 04 04:58:02 PM PDT 24
Peak memory 194608 kb
Host smart-be856f54-0e93-48b8-abc7-ec7c3e741cef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079255412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
4079255412
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/80.rv_timer_random.2665417350
Short name T148
Test name
Test status
Simulation time 153074634706 ps
CPU time 191.91 seconds
Started Aug 04 04:41:56 PM PDT 24
Finished Aug 04 04:45:08 PM PDT 24
Peak memory 191576 kb
Host smart-c639a5f1-42a7-4fc8-a1b7-67c1b7af0c51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665417350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.2665417350
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.3655054179
Short name T234
Test name
Test status
Simulation time 388950807230 ps
CPU time 412.53 seconds
Started Aug 04 04:41:51 PM PDT 24
Finished Aug 04 04:48:43 PM PDT 24
Peak memory 191548 kb
Host smart-e242caa4-ebdd-4855-9c5d-ab862d3c5fce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655054179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.3655054179
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.1522922180
Short name T315
Test name
Test status
Simulation time 236611175426 ps
CPU time 909.67 seconds
Started Aug 04 04:41:59 PM PDT 24
Finished Aug 04 04:57:09 PM PDT 24
Peak memory 191536 kb
Host smart-4e699a41-d741-4e3b-b027-f6197e580249
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522922180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.1522922180
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.3957177061
Short name T92
Test name
Test status
Simulation time 86968982912 ps
CPU time 185.09 seconds
Started Aug 04 04:41:59 PM PDT 24
Finished Aug 04 04:45:05 PM PDT 24
Peak memory 191672 kb
Host smart-9fc71fa7-1385-4ebf-9692-39a1e1de09ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957177061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.3957177061
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.2573529714
Short name T173
Test name
Test status
Simulation time 558238231666 ps
CPU time 304.75 seconds
Started Aug 04 04:41:55 PM PDT 24
Finished Aug 04 04:46:59 PM PDT 24
Peak memory 191564 kb
Host smart-53b0793d-65aa-41bb-91d4-a942916d3650
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573529714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.2573529714
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.2336870243
Short name T321
Test name
Test status
Simulation time 80635776580 ps
CPU time 233.64 seconds
Started Aug 04 04:41:51 PM PDT 24
Finished Aug 04 04:45:45 PM PDT 24
Peak memory 183400 kb
Host smart-0914fef3-f6f7-4082-b1cc-1970370c0e95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336870243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.2336870243
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.4142691434
Short name T404
Test name
Test status
Simulation time 54626112353 ps
CPU time 407.7 seconds
Started Aug 04 04:41:52 PM PDT 24
Finished Aug 04 04:48:40 PM PDT 24
Peak memory 195092 kb
Host smart-73eb3bde-8bb8-4a61-bdc7-5bfab317bc4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142691434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.4142691434
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.3805384836
Short name T302
Test name
Test status
Simulation time 76157698622 ps
CPU time 274.17 seconds
Started Aug 04 04:41:51 PM PDT 24
Finished Aug 04 04:46:25 PM PDT 24
Peak memory 194808 kb
Host smart-e5868b99-87c2-4442-9a9c-c32bc9c94926
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805384836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.3805384836
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.434082142
Short name T358
Test name
Test status
Simulation time 83179543895 ps
CPU time 450.67 seconds
Started Aug 04 04:41:55 PM PDT 24
Finished Aug 04 04:49:26 PM PDT 24
Peak memory 191508 kb
Host smart-634db0fd-32a4-47f0-b31b-6a6faae06621
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434082142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.434082142
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.2114218069
Short name T274
Test name
Test status
Simulation time 162338866670 ps
CPU time 240.75 seconds
Started Aug 04 04:41:54 PM PDT 24
Finished Aug 04 04:45:55 PM PDT 24
Peak memory 191552 kb
Host smart-05ea5446-be74-4a20-81a5-399d53dfb35e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114218069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.2114218069
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.2515983737
Short name T317
Test name
Test status
Simulation time 2184366895450 ps
CPU time 615.84 seconds
Started Aug 04 04:41:07 PM PDT 24
Finished Aug 04 04:51:23 PM PDT 24
Peak memory 183348 kb
Host smart-b88b9b0d-2a86-461d-bb13-e71c5faccbc3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515983737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.2515983737
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.4097005128
Short name T409
Test name
Test status
Simulation time 215047023559 ps
CPU time 81.22 seconds
Started Aug 04 04:41:14 PM PDT 24
Finished Aug 04 04:42:35 PM PDT 24
Peak memory 183396 kb
Host smart-2a151d59-0aad-4b0c-acc1-4ce7fd1b3ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097005128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.4097005128
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.260390007
Short name T336
Test name
Test status
Simulation time 3334198421 ps
CPU time 3.54 seconds
Started Aug 04 04:41:07 PM PDT 24
Finished Aug 04 04:41:11 PM PDT 24
Peak memory 183308 kb
Host smart-57a7deed-be8b-4c88-8864-d2045973eda7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260390007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.260390007
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.3782298593
Short name T177
Test name
Test status
Simulation time 699429651969 ps
CPU time 189.36 seconds
Started Aug 04 04:41:05 PM PDT 24
Finished Aug 04 04:44:15 PM PDT 24
Peak memory 183456 kb
Host smart-40ac1c46-80ed-42e7-b037-90cb77cce952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782298593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.3782298593
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/91.rv_timer_random.1950496109
Short name T346
Test name
Test status
Simulation time 132966303902 ps
CPU time 80.02 seconds
Started Aug 04 04:41:58 PM PDT 24
Finished Aug 04 04:43:18 PM PDT 24
Peak memory 191480 kb
Host smart-19f08ce3-3a83-49c5-b80c-465726f537d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950496109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.1950496109
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.1477330593
Short name T410
Test name
Test status
Simulation time 210918067518 ps
CPU time 88.14 seconds
Started Aug 04 04:41:54 PM PDT 24
Finished Aug 04 04:43:23 PM PDT 24
Peak memory 183364 kb
Host smart-040d86bb-48fb-4879-965e-d40023b7c410
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477330593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.1477330593
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.3939263192
Short name T345
Test name
Test status
Simulation time 80279917759 ps
CPU time 304.8 seconds
Started Aug 04 04:41:55 PM PDT 24
Finished Aug 04 04:47:00 PM PDT 24
Peak memory 191484 kb
Host smart-a25cfa1a-19bd-48df-8509-de43f742c185
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939263192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.3939263192
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.461313480
Short name T276
Test name
Test status
Simulation time 28812703692 ps
CPU time 105.05 seconds
Started Aug 04 04:41:58 PM PDT 24
Finished Aug 04 04:43:43 PM PDT 24
Peak memory 183452 kb
Host smart-92a8f3bb-4b60-4745-93da-dab2552535e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461313480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.461313480
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.2462284339
Short name T334
Test name
Test status
Simulation time 227202989982 ps
CPU time 96.5 seconds
Started Aug 04 04:42:00 PM PDT 24
Finished Aug 04 04:43:37 PM PDT 24
Peak memory 191600 kb
Host smart-e6e31424-c844-4beb-8f6f-99b041d66a32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462284339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.2462284339
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.2853951843
Short name T132
Test name
Test status
Simulation time 262033602770 ps
CPU time 510.6 seconds
Started Aug 04 04:41:59 PM PDT 24
Finished Aug 04 04:50:30 PM PDT 24
Peak memory 191496 kb
Host smart-4fba204a-c386-4d43-89ff-caddaa8b1bd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853951843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.2853951843
Directory /workspace/99.rv_timer_random/latest
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