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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.61 99.36 98.73 100.00 100.00 100.00 99.55


Total test records in report: 581
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T505 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2591055396 Aug 05 05:49:43 PM PDT 24 Aug 05 05:49:48 PM PDT 24 14462047 ps
T506 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.3110318681 Aug 05 05:49:50 PM PDT 24 Aug 05 05:49:51 PM PDT 24 18688169 ps
T507 /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.2229915072 Aug 05 05:49:25 PM PDT 24 Aug 05 05:49:26 PM PDT 24 30577088 ps
T508 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.2096617807 Aug 05 05:49:23 PM PDT 24 Aug 05 05:49:24 PM PDT 24 14881825 ps
T509 /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.671031095 Aug 05 05:49:43 PM PDT 24 Aug 05 05:49:44 PM PDT 24 180744094 ps
T510 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.3342015066 Aug 05 05:49:40 PM PDT 24 Aug 05 05:49:41 PM PDT 24 21686525 ps
T511 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.511279760 Aug 05 05:49:46 PM PDT 24 Aug 05 05:49:48 PM PDT 24 92605682 ps
T512 /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.4162647775 Aug 05 05:49:52 PM PDT 24 Aug 05 05:49:53 PM PDT 24 49247670 ps
T513 /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.1209961505 Aug 05 05:49:41 PM PDT 24 Aug 05 05:49:41 PM PDT 24 110963969 ps
T514 /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.1923189535 Aug 05 05:49:56 PM PDT 24 Aug 05 05:49:56 PM PDT 24 19141841 ps
T515 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.2947448342 Aug 05 05:49:25 PM PDT 24 Aug 05 05:49:27 PM PDT 24 146957996 ps
T516 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.4162391235 Aug 05 05:49:35 PM PDT 24 Aug 05 05:49:36 PM PDT 24 27524745 ps
T517 /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.4151619696 Aug 05 05:49:54 PM PDT 24 Aug 05 05:49:57 PM PDT 24 143572401 ps
T518 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.2741873534 Aug 05 05:49:38 PM PDT 24 Aug 05 05:49:39 PM PDT 24 16795454 ps
T519 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.314302038 Aug 05 05:49:55 PM PDT 24 Aug 05 05:49:55 PM PDT 24 37805255 ps
T520 /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.2466795653 Aug 05 05:49:51 PM PDT 24 Aug 05 05:49:51 PM PDT 24 14375925 ps
T521 /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.3415474134 Aug 05 05:49:32 PM PDT 24 Aug 05 05:49:33 PM PDT 24 494701745 ps
T522 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.121146129 Aug 05 05:49:41 PM PDT 24 Aug 05 05:49:42 PM PDT 24 81964257 ps
T523 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.3841422929 Aug 05 05:49:50 PM PDT 24 Aug 05 05:49:50 PM PDT 24 57036836 ps
T524 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.3515959529 Aug 05 05:49:51 PM PDT 24 Aug 05 05:49:52 PM PDT 24 24696704 ps
T525 /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.3827816240 Aug 05 05:49:49 PM PDT 24 Aug 05 05:49:50 PM PDT 24 19664520 ps
T526 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.1679338595 Aug 05 05:49:44 PM PDT 24 Aug 05 05:49:46 PM PDT 24 140593577 ps
T527 /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.3855808746 Aug 05 05:49:41 PM PDT 24 Aug 05 05:49:42 PM PDT 24 30584703 ps
T80 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.844758438 Aug 05 05:49:25 PM PDT 24 Aug 05 05:49:26 PM PDT 24 24491893 ps
T81 /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.3706020775 Aug 05 05:49:22 PM PDT 24 Aug 05 05:49:22 PM PDT 24 27518161 ps
T528 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.2681033443 Aug 05 05:49:27 PM PDT 24 Aug 05 05:49:29 PM PDT 24 323904433 ps
T529 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2422291658 Aug 05 05:49:28 PM PDT 24 Aug 05 05:49:29 PM PDT 24 265563901 ps
T530 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.1509930749 Aug 05 05:49:40 PM PDT 24 Aug 05 05:49:41 PM PDT 24 39951967 ps
T531 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.3574096391 Aug 05 05:49:29 PM PDT 24 Aug 05 05:49:30 PM PDT 24 52400396 ps
T532 /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.1905608223 Aug 05 05:49:25 PM PDT 24 Aug 05 05:49:26 PM PDT 24 117420537 ps
T533 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.900644355 Aug 05 05:50:00 PM PDT 24 Aug 05 05:50:01 PM PDT 24 20804409 ps
T534 /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2717678895 Aug 05 05:49:48 PM PDT 24 Aug 05 05:49:53 PM PDT 24 1051574560 ps
T535 /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.2501285795 Aug 05 05:49:36 PM PDT 24 Aug 05 05:49:37 PM PDT 24 635952779 ps
T536 /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.3718632458 Aug 05 05:49:38 PM PDT 24 Aug 05 05:49:40 PM PDT 24 346677624 ps
T537 /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.530651882 Aug 05 05:49:37 PM PDT 24 Aug 05 05:49:38 PM PDT 24 13094831 ps
T538 /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.3148902488 Aug 05 05:49:38 PM PDT 24 Aug 05 05:49:39 PM PDT 24 29782915 ps
T539 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.524354179 Aug 05 05:49:41 PM PDT 24 Aug 05 05:49:41 PM PDT 24 18517387 ps
T540 /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.2082754668 Aug 05 05:49:50 PM PDT 24 Aug 05 05:49:51 PM PDT 24 16637034 ps
T541 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2677858568 Aug 05 05:49:51 PM PDT 24 Aug 05 05:49:56 PM PDT 24 22414201 ps
T542 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3370916281 Aug 05 05:49:44 PM PDT 24 Aug 05 05:49:45 PM PDT 24 13323445 ps
T543 /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.2307690254 Aug 05 05:49:45 PM PDT 24 Aug 05 05:49:48 PM PDT 24 118862422 ps
T544 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3578567209 Aug 05 05:49:31 PM PDT 24 Aug 05 05:49:32 PM PDT 24 115585630 ps
T545 /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.959580170 Aug 05 05:49:44 PM PDT 24 Aug 05 05:49:45 PM PDT 24 44544913 ps
T546 /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.2487812103 Aug 05 05:49:49 PM PDT 24 Aug 05 05:49:49 PM PDT 24 155684515 ps
T547 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.782530917 Aug 05 05:49:39 PM PDT 24 Aug 05 05:49:40 PM PDT 24 154857274 ps
T82 /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.1405588964 Aug 05 05:49:33 PM PDT 24 Aug 05 05:49:33 PM PDT 24 38558702 ps
T548 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1592309119 Aug 05 05:49:39 PM PDT 24 Aug 05 05:49:40 PM PDT 24 33140135 ps
T549 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.784431116 Aug 05 05:49:39 PM PDT 24 Aug 05 05:49:47 PM PDT 24 563730960 ps
T83 /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.513642887 Aug 05 05:49:36 PM PDT 24 Aug 05 05:49:37 PM PDT 24 21035278 ps
T550 /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.4287929417 Aug 05 05:49:44 PM PDT 24 Aug 05 05:49:45 PM PDT 24 80402805 ps
T551 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.2697273359 Aug 05 05:49:42 PM PDT 24 Aug 05 05:49:44 PM PDT 24 196895424 ps
T552 /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.4216208754 Aug 05 05:49:42 PM PDT 24 Aug 05 05:49:43 PM PDT 24 14491384 ps
T553 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.859049776 Aug 05 05:49:52 PM PDT 24 Aug 05 05:49:53 PM PDT 24 24025907 ps
T554 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2997467847 Aug 05 05:49:58 PM PDT 24 Aug 05 05:49:59 PM PDT 24 15452305 ps
T555 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.1502366652 Aug 05 05:49:38 PM PDT 24 Aug 05 05:49:39 PM PDT 24 36544262 ps
T556 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.610213432 Aug 05 05:49:53 PM PDT 24 Aug 05 05:49:54 PM PDT 24 13115892 ps
T557 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.560070465 Aug 05 05:49:27 PM PDT 24 Aug 05 05:49:28 PM PDT 24 36516177 ps
T558 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.2014305064 Aug 05 05:49:50 PM PDT 24 Aug 05 05:49:51 PM PDT 24 14274591 ps
T559 /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3085693526 Aug 05 05:49:59 PM PDT 24 Aug 05 05:50:00 PM PDT 24 19835031 ps
T560 /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.1125902190 Aug 05 05:49:27 PM PDT 24 Aug 05 05:49:28 PM PDT 24 15525001 ps
T561 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.3634621469 Aug 05 05:49:44 PM PDT 24 Aug 05 05:49:45 PM PDT 24 50740282 ps
T562 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.508305182 Aug 05 05:49:52 PM PDT 24 Aug 05 05:49:52 PM PDT 24 14368035 ps
T563 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.772724308 Aug 05 05:49:52 PM PDT 24 Aug 05 05:49:53 PM PDT 24 20030014 ps
T564 /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.1464083405 Aug 05 05:49:40 PM PDT 24 Aug 05 05:49:41 PM PDT 24 41293980 ps
T565 /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.2268016045 Aug 05 05:49:47 PM PDT 24 Aug 05 05:49:48 PM PDT 24 16839995 ps
T566 /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.1042989304 Aug 05 05:49:52 PM PDT 24 Aug 05 05:49:53 PM PDT 24 15668372 ps
T567 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.1389930336 Aug 05 05:49:41 PM PDT 24 Aug 05 05:49:42 PM PDT 24 27317543 ps
T568 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.2233116571 Aug 05 05:49:40 PM PDT 24 Aug 05 05:49:41 PM PDT 24 343918347 ps
T569 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.553271974 Aug 05 05:49:25 PM PDT 24 Aug 05 05:49:26 PM PDT 24 39960000 ps
T570 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.3156520339 Aug 05 05:49:30 PM PDT 24 Aug 05 05:49:31 PM PDT 24 75665240 ps
T571 /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.1119818700 Aug 05 05:49:56 PM PDT 24 Aug 05 05:49:57 PM PDT 24 104350218 ps
T572 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3914645355 Aug 05 05:49:43 PM PDT 24 Aug 05 05:49:46 PM PDT 24 309155953 ps
T573 /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.3252947483 Aug 05 05:49:36 PM PDT 24 Aug 05 05:49:42 PM PDT 24 15187051 ps
T574 /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.4255266722 Aug 05 05:49:48 PM PDT 24 Aug 05 05:49:49 PM PDT 24 12256763 ps
T575 /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.3606132322 Aug 05 05:49:55 PM PDT 24 Aug 05 05:49:55 PM PDT 24 23503338 ps
T576 /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.3300075807 Aug 05 05:49:44 PM PDT 24 Aug 05 05:49:44 PM PDT 24 34476009 ps
T577 /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2413199598 Aug 05 05:49:29 PM PDT 24 Aug 05 05:49:32 PM PDT 24 52210053 ps
T578 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.4113730073 Aug 05 05:49:39 PM PDT 24 Aug 05 05:49:41 PM PDT 24 468156872 ps
T579 /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.380184534 Aug 05 05:49:41 PM PDT 24 Aug 05 05:49:42 PM PDT 24 66401592 ps
T580 /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.426479126 Aug 05 05:49:49 PM PDT 24 Aug 05 05:49:50 PM PDT 24 22130476 ps
T581 /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.2816904622 Aug 05 05:49:38 PM PDT 24 Aug 05 05:49:39 PM PDT 24 53161846 ps

Test location /workspace/coverage/default/14.rv_timer_stress_all.257149996
Short name T1
Test name
Test status
Simulation time 469550123503 ps
CPU time 1101.19 seconds
Started Aug 05 05:54:22 PM PDT 24
Finished Aug 05 06:12:44 PM PDT 24
Peak memory 191588 kb
Host smart-e33f4546-89e4-455f-aa8a-3932dcbc609f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257149996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all.
257149996
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.1899395396
Short name T13
Test name
Test status
Simulation time 64329091906 ps
CPU time 249.14 seconds
Started Aug 05 05:54:06 PM PDT 24
Finished Aug 05 05:58:16 PM PDT 24
Peak memory 198168 kb
Host smart-85b4274d-f540-44df-8d32-ef147b89574c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899395396 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_reset.1899395396
Directory /workspace/10.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/194.rv_timer_random.2948182636
Short name T59
Test name
Test status
Simulation time 1519779602106 ps
CPU time 825.74 seconds
Started Aug 05 05:58:46 PM PDT 24
Finished Aug 05 06:12:32 PM PDT 24
Peak memory 191664 kb
Host smart-2b3f2cc6-9f2f-4caf-901b-88683b17fbb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948182636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.2948182636
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.1176811126
Short name T30
Test name
Test status
Simulation time 119021753 ps
CPU time 1.06 seconds
Started Aug 05 05:49:48 PM PDT 24
Finished Aug 05 05:49:49 PM PDT 24
Peak memory 195508 kb
Host smart-f572977a-060d-4ba3-a984-91f561d86bd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176811126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.1176811126
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.1896526322
Short name T176
Test name
Test status
Simulation time 4111065061004 ps
CPU time 2275.1 seconds
Started Aug 05 05:53:53 PM PDT 24
Finished Aug 05 06:31:48 PM PDT 24
Peak memory 196140 kb
Host smart-359e5293-eedc-4525-a16f-1f0562ebf2c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896526322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
1896526322
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.2845546473
Short name T44
Test name
Test status
Simulation time 679421621216 ps
CPU time 1117.44 seconds
Started Aug 05 05:55:04 PM PDT 24
Finished Aug 05 06:13:42 PM PDT 24
Peak memory 191660 kb
Host smart-78f45c01-174e-4976-82ca-bc4a72e3edfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845546473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.2845546473
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.2575241921
Short name T146
Test name
Test status
Simulation time 1180503941860 ps
CPU time 1863.72 seconds
Started Aug 05 05:54:23 PM PDT 24
Finished Aug 05 06:25:27 PM PDT 24
Peak memory 191632 kb
Host smart-eb0f5a5b-70e7-425c-8de4-6d3877ce7dd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575241921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.2575241921
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.3949380902
Short name T161
Test name
Test status
Simulation time 5437687151902 ps
CPU time 2291.01 seconds
Started Aug 05 05:54:49 PM PDT 24
Finished Aug 05 06:33:00 PM PDT 24
Peak memory 191628 kb
Host smart-f087291e-2339-4c53-91e7-1952a65d36d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949380902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.3949380902
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.2761734224
Short name T57
Test name
Test status
Simulation time 1456443709629 ps
CPU time 1670.81 seconds
Started Aug 05 05:54:03 PM PDT 24
Finished Aug 05 06:21:54 PM PDT 24
Peak memory 191664 kb
Host smart-e5d4fd68-0ae6-4ef2-a900-4ea85d3172c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761734224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.2761734224
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.379815403
Short name T71
Test name
Test status
Simulation time 30983006 ps
CPU time 0.56 seconds
Started Aug 05 05:49:28 PM PDT 24
Finished Aug 05 05:49:29 PM PDT 24
Peak memory 182944 kb
Host smart-786667a3-6442-44d5-b97b-9ec818359f47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379815403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.379815403
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.2005899640
Short name T164
Test name
Test status
Simulation time 620476702275 ps
CPU time 1213.73 seconds
Started Aug 05 05:56:46 PM PDT 24
Finished Aug 05 06:17:00 PM PDT 24
Peak memory 191652 kb
Host smart-7d101ee6-1203-4e9f-a39e-85b67d4918a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005899640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.2005899640
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.4148480550
Short name T135
Test name
Test status
Simulation time 2076963679366 ps
CPU time 889.78 seconds
Started Aug 05 05:53:50 PM PDT 24
Finished Aug 05 06:08:40 PM PDT 24
Peak memory 191712 kb
Host smart-e448ab6f-f593-4a2f-903d-0403c7e4b8a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148480550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
4148480550
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.1384486938
Short name T227
Test name
Test status
Simulation time 632780321475 ps
CPU time 1968.01 seconds
Started Aug 05 05:53:38 PM PDT 24
Finished Aug 05 06:26:26 PM PDT 24
Peak memory 191680 kb
Host smart-126e8d54-2096-4db1-b37e-5dce68d3cc9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384486938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
1384486938
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.2766872564
Short name T201
Test name
Test status
Simulation time 594735267442 ps
CPU time 1579.97 seconds
Started Aug 05 05:53:45 PM PDT 24
Finished Aug 05 06:20:05 PM PDT 24
Peak memory 191652 kb
Host smart-d92ae4a0-5f29-427e-9a04-871b65cf19ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766872564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
2766872564
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.2543356871
Short name T148
Test name
Test status
Simulation time 2205066895407 ps
CPU time 1974.86 seconds
Started Aug 05 05:56:56 PM PDT 24
Finished Aug 05 06:29:52 PM PDT 24
Peak memory 191664 kb
Host smart-c9472137-33fe-4a6f-9ea6-d8ce6fa03ec4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543356871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.2543356871
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.169821605
Short name T17
Test name
Test status
Simulation time 43212231 ps
CPU time 0.74 seconds
Started Aug 05 05:53:37 PM PDT 24
Finished Aug 05 05:53:38 PM PDT 24
Peak memory 213996 kb
Host smart-5e08a91c-35ca-4a5c-a031-b51c93d3dc9c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169821605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.169821605
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.3209281575
Short name T179
Test name
Test status
Simulation time 2365876774292 ps
CPU time 1129.31 seconds
Started Aug 05 05:56:34 PM PDT 24
Finished Aug 05 06:15:24 PM PDT 24
Peak memory 196420 kb
Host smart-d4ee26c1-ce59-4865-bc77-875ea683bdd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209281575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.3209281575
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.427110896
Short name T54
Test name
Test status
Simulation time 2443176554581 ps
CPU time 1058.42 seconds
Started Aug 05 05:54:04 PM PDT 24
Finished Aug 05 06:11:43 PM PDT 24
Peak memory 191676 kb
Host smart-d24634ca-0288-4670-8433-96c35191d044
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427110896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.427110896
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.212676937
Short name T199
Test name
Test status
Simulation time 475268558252 ps
CPU time 710.83 seconds
Started Aug 05 05:53:37 PM PDT 24
Finished Aug 05 06:05:28 PM PDT 24
Peak memory 191676 kb
Host smart-d9ca505e-d66d-4256-b2e1-f1f7778b487e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212676937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.212676937
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/162.rv_timer_random.948193839
Short name T244
Test name
Test status
Simulation time 475433404852 ps
CPU time 394.78 seconds
Started Aug 05 05:58:15 PM PDT 24
Finished Aug 05 06:04:50 PM PDT 24
Peak memory 191668 kb
Host smart-728614fd-9c1b-4a36-b905-c1a054750531
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948193839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.948193839
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random.2625824569
Short name T95
Test name
Test status
Simulation time 507311383936 ps
CPU time 253.94 seconds
Started Aug 05 05:55:52 PM PDT 24
Finished Aug 05 06:00:07 PM PDT 24
Peak memory 191700 kb
Host smart-002c064f-e80f-4618-bd6d-f6c17921fa0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625824569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.2625824569
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.3543154530
Short name T118
Test name
Test status
Simulation time 218314379352 ps
CPU time 411.37 seconds
Started Aug 05 05:57:46 PM PDT 24
Finished Aug 05 06:04:38 PM PDT 24
Peak memory 195252 kb
Host smart-efae2304-b10e-4518-856f-9abffdc5c04d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543154530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.3543154530
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.1222661702
Short name T156
Test name
Test status
Simulation time 166845492813 ps
CPU time 301.55 seconds
Started Aug 05 05:57:45 PM PDT 24
Finished Aug 05 06:02:47 PM PDT 24
Peak memory 191644 kb
Host smart-ab0577c8-2008-4e2b-900c-4b3f719b10f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222661702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.1222661702
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.1279574605
Short name T239
Test name
Test status
Simulation time 830124975273 ps
CPU time 767.83 seconds
Started Aug 05 05:58:06 PM PDT 24
Finished Aug 05 06:10:54 PM PDT 24
Peak memory 194832 kb
Host smart-9064849c-a803-4f3d-9672-0f5dc1dab50a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279574605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.1279574605
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.1330101004
Short name T284
Test name
Test status
Simulation time 185593665073 ps
CPU time 1098.57 seconds
Started Aug 05 05:57:45 PM PDT 24
Finished Aug 05 06:16:04 PM PDT 24
Peak memory 191640 kb
Host smart-fdea0808-cdcf-4107-9b86-69e610f99916
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330101004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.1330101004
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/150.rv_timer_random.3139280383
Short name T210
Test name
Test status
Simulation time 170395374667 ps
CPU time 522.75 seconds
Started Aug 05 05:58:11 PM PDT 24
Finished Aug 05 06:06:54 PM PDT 24
Peak memory 191648 kb
Host smart-b3366972-1484-4b3e-9162-ca61415e7ad0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139280383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.3139280383
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.1903075601
Short name T155
Test name
Test status
Simulation time 146000636490 ps
CPU time 264.97 seconds
Started Aug 05 05:55:21 PM PDT 24
Finished Aug 05 05:59:46 PM PDT 24
Peak memory 191656 kb
Host smart-707ad79c-5c1a-45cc-b29d-7b849aefd9cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903075601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.1903075601
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_random.3240690040
Short name T202
Test name
Test status
Simulation time 399361705642 ps
CPU time 465.16 seconds
Started Aug 05 05:56:28 PM PDT 24
Finished Aug 05 06:04:14 PM PDT 24
Peak memory 191668 kb
Host smart-e15d30d0-11e4-41f4-9a60-2970ef33dfa5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240690040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.3240690040
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.2842022370
Short name T276
Test name
Test status
Simulation time 222557784211 ps
CPU time 516.32 seconds
Started Aug 05 05:58:10 PM PDT 24
Finished Aug 05 06:06:47 PM PDT 24
Peak memory 191596 kb
Host smart-90992e07-4fde-40d4-a648-f1c99b9edef7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842022370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.2842022370
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.2067327018
Short name T121
Test name
Test status
Simulation time 128177903280 ps
CPU time 1617.44 seconds
Started Aug 05 05:58:11 PM PDT 24
Finished Aug 05 06:25:09 PM PDT 24
Peak memory 191660 kb
Host smart-3886b624-50ad-4c8b-9d70-73ee1eaf435c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067327018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.2067327018
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.2930901661
Short name T233
Test name
Test status
Simulation time 456289744358 ps
CPU time 644.99 seconds
Started Aug 05 05:58:47 PM PDT 24
Finished Aug 05 06:09:32 PM PDT 24
Peak memory 191876 kb
Host smart-0a465b6d-1799-4de7-8aba-634dd33da283
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930901661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.2930901661
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.1378614674
Short name T247
Test name
Test status
Simulation time 556237937480 ps
CPU time 946.22 seconds
Started Aug 05 05:53:34 PM PDT 24
Finished Aug 05 06:09:20 PM PDT 24
Peak memory 183484 kb
Host smart-7c351307-72e1-4e35-9796-00199c29be68
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378614674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.1378614674
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.2263295889
Short name T131
Test name
Test status
Simulation time 754111731161 ps
CPU time 659.95 seconds
Started Aug 05 05:54:06 PM PDT 24
Finished Aug 05 06:05:06 PM PDT 24
Peak memory 183468 kb
Host smart-274276c7-1f05-44de-bdcb-7ec2f318ef6d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263295889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.2263295889
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/161.rv_timer_random.2238809660
Short name T138
Test name
Test status
Simulation time 49784070656 ps
CPU time 46.24 seconds
Started Aug 05 05:58:17 PM PDT 24
Finished Aug 05 05:59:03 PM PDT 24
Peak memory 191652 kb
Host smart-7328c33f-64cf-48cb-9fa2-61f58daba64a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238809660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.2238809660
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.1410092390
Short name T126
Test name
Test status
Simulation time 432922380662 ps
CPU time 1802.25 seconds
Started Aug 05 05:58:24 PM PDT 24
Finished Aug 05 06:28:26 PM PDT 24
Peak memory 191660 kb
Host smart-03ab14ac-825e-4cf1-b56b-c3ca3c823eb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410092390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.1410092390
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.1173973065
Short name T113
Test name
Test status
Simulation time 315662971009 ps
CPU time 154.57 seconds
Started Aug 05 05:56:36 PM PDT 24
Finished Aug 05 05:59:10 PM PDT 24
Peak memory 191656 kb
Host smart-de8bc66b-2e73-40d0-b1ce-ed3be89cd529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173973065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.1173973065
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_random.275760618
Short name T314
Test name
Test status
Simulation time 135681215954 ps
CPU time 618.07 seconds
Started Aug 05 05:53:55 PM PDT 24
Finished Aug 05 06:04:13 PM PDT 24
Peak memory 191668 kb
Host smart-264c2782-3ca2-412a-819c-ec7f1ae9a8eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275760618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.275760618
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random.2602127864
Short name T278
Test name
Test status
Simulation time 526045807340 ps
CPU time 1528.04 seconds
Started Aug 05 05:54:05 PM PDT 24
Finished Aug 05 06:19:34 PM PDT 24
Peak memory 191668 kb
Host smart-7d89e5f7-ed46-423d-af87-4895d94df031
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602127864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.2602127864
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.4235529805
Short name T307
Test name
Test status
Simulation time 478507939260 ps
CPU time 187.56 seconds
Started Aug 05 05:57:50 PM PDT 24
Finished Aug 05 06:00:57 PM PDT 24
Peak memory 191668 kb
Host smart-9293f475-56f0-4725-b9e0-4bd52cd908dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235529805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.4235529805
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random.1488459031
Short name T315
Test name
Test status
Simulation time 1683375899557 ps
CPU time 555.23 seconds
Started Aug 05 05:54:22 PM PDT 24
Finished Aug 05 06:03:38 PM PDT 24
Peak memory 191616 kb
Host smart-514383e7-25e4-41dc-bd17-16685aa0e909
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488459031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.1488459031
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random.1198779234
Short name T189
Test name
Test status
Simulation time 137941698054 ps
CPU time 735.67 seconds
Started Aug 05 05:54:32 PM PDT 24
Finished Aug 05 06:06:48 PM PDT 24
Peak memory 191648 kb
Host smart-5e9bfb1b-24f6-4965-8d64-e7ddd770673b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198779234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.1198779234
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.1482073449
Short name T96
Test name
Test status
Simulation time 173487879140 ps
CPU time 793.62 seconds
Started Aug 05 05:58:27 PM PDT 24
Finished Aug 05 06:11:41 PM PDT 24
Peak memory 191640 kb
Host smart-6f7af148-f410-4e8d-8e89-08b1ed29e6d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482073449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.1482073449
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random.1765345722
Short name T279
Test name
Test status
Simulation time 314050237584 ps
CPU time 262.48 seconds
Started Aug 05 05:54:55 PM PDT 24
Finished Aug 05 05:59:18 PM PDT 24
Peak memory 191608 kb
Host smart-42ea4525-b556-496a-9e6d-d7423bc6a356
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765345722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.1765345722
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.630365868
Short name T43
Test name
Test status
Simulation time 155083338486 ps
CPU time 270.32 seconds
Started Aug 05 05:54:53 PM PDT 24
Finished Aug 05 05:59:24 PM PDT 24
Peak memory 191632 kb
Host smart-70a2984a-34a4-4df5-aa33-c7ae43073b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630365868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.630365868
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_random.4029506944
Short name T317
Test name
Test status
Simulation time 267891172579 ps
CPU time 152.87 seconds
Started Aug 05 05:56:07 PM PDT 24
Finished Aug 05 05:58:40 PM PDT 24
Peak memory 191692 kb
Host smart-e21236d8-01c2-4f40-8cdc-78755bc5e0f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029506944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.4029506944
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.1459311957
Short name T211
Test name
Test status
Simulation time 394279231632 ps
CPU time 281.45 seconds
Started Aug 05 05:57:45 PM PDT 24
Finished Aug 05 06:02:27 PM PDT 24
Peak memory 194196 kb
Host smart-be55fde3-d1f8-480d-96df-3d7b873a674d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459311957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.1459311957
Directory /workspace/99.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.2553024376
Short name T291
Test name
Test status
Simulation time 316483592213 ps
CPU time 187.26 seconds
Started Aug 05 05:54:11 PM PDT 24
Finished Aug 05 05:57:18 PM PDT 24
Peak memory 191688 kb
Host smart-ce41d03e-ee5f-453d-9600-ab7081d71c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553024376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.2553024376
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/129.rv_timer_random.3203149480
Short name T256
Test name
Test status
Simulation time 545281286212 ps
CPU time 527.01 seconds
Started Aug 05 05:58:01 PM PDT 24
Finished Aug 05 06:06:48 PM PDT 24
Peak memory 191648 kb
Host smart-3119a030-8026-4dd6-80d8-1ba2618e4460
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203149480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.3203149480
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random.3333758109
Short name T324
Test name
Test status
Simulation time 174991112955 ps
CPU time 200.12 seconds
Started Aug 05 05:54:22 PM PDT 24
Finished Aug 05 05:57:43 PM PDT 24
Peak memory 191700 kb
Host smart-c9250c59-3a47-4e8b-a7a6-1af91fcc6e24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333758109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.3333758109
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.1408789930
Short name T110
Test name
Test status
Simulation time 548908523009 ps
CPU time 617.54 seconds
Started Aug 05 05:58:15 PM PDT 24
Finished Aug 05 06:08:32 PM PDT 24
Peak memory 191668 kb
Host smart-95de6461-1284-47a5-8461-d2f6ea3e0655
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408789930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.1408789930
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.3085522412
Short name T208
Test name
Test status
Simulation time 480227022041 ps
CPU time 587.72 seconds
Started Aug 05 05:58:22 PM PDT 24
Finished Aug 05 06:08:09 PM PDT 24
Peak memory 191576 kb
Host smart-0438d9c1-e49f-45fb-8c7f-c5a30122ca03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085522412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.3085522412
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.3612178064
Short name T251
Test name
Test status
Simulation time 156565433501 ps
CPU time 1601.2 seconds
Started Aug 05 05:58:48 PM PDT 24
Finished Aug 05 06:25:29 PM PDT 24
Peak memory 191612 kb
Host smart-00a2613b-7f54-4637-bdc0-0cfdfe93d95c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612178064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.3612178064
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.1194028369
Short name T249
Test name
Test status
Simulation time 2939392335446 ps
CPU time 864.59 seconds
Started Aug 05 05:55:21 PM PDT 24
Finished Aug 05 06:09:46 PM PDT 24
Peak memory 191676 kb
Host smart-5eb3618c-810c-495b-8732-e2a3664fa903
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194028369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.1194028369
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_random.4285219707
Short name T104
Test name
Test status
Simulation time 234341999436 ps
CPU time 211.5 seconds
Started Aug 05 05:55:52 PM PDT 24
Finished Aug 05 05:59:24 PM PDT 24
Peak memory 191644 kb
Host smart-96b210c2-6607-42d2-8714-9dbfaf7883dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285219707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.4285219707
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.1257972600
Short name T58
Test name
Test status
Simulation time 416152129957 ps
CPU time 735.94 seconds
Started Aug 05 05:56:52 PM PDT 24
Finished Aug 05 06:09:08 PM PDT 24
Peak memory 196028 kb
Host smart-f36b99fd-6367-4229-9194-a3bfff7f2ad5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257972600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.1257972600
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/73.rv_timer_random.2741943260
Short name T297
Test name
Test status
Simulation time 446527636857 ps
CPU time 450.43 seconds
Started Aug 05 05:57:21 PM PDT 24
Finished Aug 05 06:04:51 PM PDT 24
Peak memory 191680 kb
Host smart-6a0d715e-fb87-45bd-a9b6-61c1944dce91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741943260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.2741943260
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3549926369
Short name T34
Test name
Test status
Simulation time 62911601 ps
CPU time 0.59 seconds
Started Aug 05 05:49:43 PM PDT 24
Finished Aug 05 05:49:44 PM PDT 24
Peak memory 192168 kb
Host smart-722f78e4-5089-47ee-9549-32b046e4cc50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549926369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.3549926369
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.1474503905
Short name T140
Test name
Test status
Simulation time 20115846009 ps
CPU time 35.43 seconds
Started Aug 05 05:53:38 PM PDT 24
Finished Aug 05 05:54:13 PM PDT 24
Peak memory 194408 kb
Host smart-0a0550f5-3ca1-410b-8fff-db698042f670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474503905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.1474503905
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.2988643413
Short name T139
Test name
Test status
Simulation time 232132344830 ps
CPU time 183.91 seconds
Started Aug 05 05:54:10 PM PDT 24
Finished Aug 05 05:57:14 PM PDT 24
Peak memory 183436 kb
Host smart-9ab01734-75bf-495c-bf0c-348820af0734
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988643413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.2988643413
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/112.rv_timer_random.1055448339
Short name T112
Test name
Test status
Simulation time 99106061318 ps
CPU time 155.32 seconds
Started Aug 05 05:57:50 PM PDT 24
Finished Aug 05 06:00:25 PM PDT 24
Peak memory 191648 kb
Host smart-b2b098a5-6f32-42a6-9ae8-cb7ec059fe0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055448339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.1055448339
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.3620344279
Short name T229
Test name
Test status
Simulation time 83575044956 ps
CPU time 231.92 seconds
Started Aug 05 05:57:48 PM PDT 24
Finished Aug 05 06:01:41 PM PDT 24
Peak memory 191644 kb
Host smart-9e50ab2f-97f7-4c47-b3c7-14b11383281b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620344279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.3620344279
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.2638785566
Short name T261
Test name
Test status
Simulation time 315465315180 ps
CPU time 1604.63 seconds
Started Aug 05 05:57:56 PM PDT 24
Finished Aug 05 06:24:41 PM PDT 24
Peak memory 191636 kb
Host smart-5e4f78d5-f392-45ec-b5e8-ce673a03f8bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638785566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.2638785566
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.1233759753
Short name T304
Test name
Test status
Simulation time 310818454886 ps
CPU time 277.66 seconds
Started Aug 05 05:58:06 PM PDT 24
Finished Aug 05 06:02:44 PM PDT 24
Peak memory 191640 kb
Host smart-22131671-9c23-49c5-9c15-8c0329cee2be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233759753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.1233759753
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.3556634425
Short name T327
Test name
Test status
Simulation time 250815495024 ps
CPU time 126.57 seconds
Started Aug 05 05:58:05 PM PDT 24
Finished Aug 05 06:00:11 PM PDT 24
Peak memory 191664 kb
Host smart-3b13cfa2-e5c7-43a4-a2b8-6da1eedaba8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556634425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.3556634425
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.2530314517
Short name T8
Test name
Test status
Simulation time 286320326630 ps
CPU time 441.85 seconds
Started Aug 05 05:58:11 PM PDT 24
Finished Aug 05 06:05:33 PM PDT 24
Peak memory 191636 kb
Host smart-d9e5c2e8-777e-408f-9a62-5e77b98eb3ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530314517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.2530314517
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.718484357
Short name T194
Test name
Test status
Simulation time 140312394562 ps
CPU time 130.05 seconds
Started Aug 05 05:58:10 PM PDT 24
Finished Aug 05 06:00:20 PM PDT 24
Peak memory 191656 kb
Host smart-1451bf60-230c-4913-93c3-dbcf59241220
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718484357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.718484357
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/170.rv_timer_random.2046125193
Short name T213
Test name
Test status
Simulation time 112047303333 ps
CPU time 747.49 seconds
Started Aug 05 05:58:20 PM PDT 24
Finished Aug 05 06:10:47 PM PDT 24
Peak memory 191700 kb
Host smart-89b7b7fa-8706-4ede-8d17-4ffa620ae76f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046125193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.2046125193
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.774810430
Short name T159
Test name
Test status
Simulation time 932355103345 ps
CPU time 381.99 seconds
Started Aug 05 05:58:40 PM PDT 24
Finished Aug 05 06:05:02 PM PDT 24
Peak memory 191620 kb
Host smart-a042c394-173a-4ef2-8bc2-67bb274919bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774810430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.774810430
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.1452176510
Short name T56
Test name
Test status
Simulation time 232846348726 ps
CPU time 238.52 seconds
Started Aug 05 05:54:59 PM PDT 24
Finished Aug 05 05:58:58 PM PDT 24
Peak memory 191608 kb
Host smart-83897f92-34e1-4b52-864d-8cebe04db3e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452176510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.1452176510
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.1802474881
Short name T340
Test name
Test status
Simulation time 390736467476 ps
CPU time 351.08 seconds
Started Aug 05 05:55:04 PM PDT 24
Finished Aug 05 06:00:55 PM PDT 24
Peak memory 183428 kb
Host smart-b8afffee-46ff-4778-b9cd-6411dbe8c2e6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802474881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.1802474881
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.2184492978
Short name T169
Test name
Test status
Simulation time 850627126291 ps
CPU time 378.17 seconds
Started Aug 05 05:53:44 PM PDT 24
Finished Aug 05 06:00:02 PM PDT 24
Peak memory 183444 kb
Host smart-7cea5f71-8d75-4844-a3eb-5cebf27356ab
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184492978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.2184492978
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_random.1734412090
Short name T351
Test name
Test status
Simulation time 116575123041 ps
CPU time 192.38 seconds
Started Aug 05 05:55:41 PM PDT 24
Finished Aug 05 05:58:53 PM PDT 24
Peak memory 191648 kb
Host smart-25f70a9a-d02e-4d87-b63b-0c632a8f9ad5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734412090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.1734412090
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random.143035063
Short name T182
Test name
Test status
Simulation time 111191176891 ps
CPU time 220.1 seconds
Started Aug 05 05:56:07 PM PDT 24
Finished Aug 05 05:59:47 PM PDT 24
Peak memory 191660 kb
Host smart-c427c7ac-139c-426a-9abd-28b2b6a0174f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143035063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.143035063
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.519593365
Short name T267
Test name
Test status
Simulation time 343084580416 ps
CPU time 245.05 seconds
Started Aug 05 05:57:23 PM PDT 24
Finished Aug 05 06:01:28 PM PDT 24
Peak memory 191692 kb
Host smart-ecccb439-cf57-4fc4-82a9-c132343c4b53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519593365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.519593365
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3232244326
Short name T99
Test name
Test status
Simulation time 186122027 ps
CPU time 1.24 seconds
Started Aug 05 05:49:47 PM PDT 24
Finished Aug 05 05:49:48 PM PDT 24
Peak memory 195236 kb
Host smart-510d0997-af03-451f-b7cb-6b781febb128
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232244326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.3232244326
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.2132698627
Short name T358
Test name
Test status
Simulation time 38477585406 ps
CPU time 197.78 seconds
Started Aug 05 05:53:30 PM PDT 24
Finished Aug 05 05:56:48 PM PDT 24
Peak memory 191672 kb
Host smart-7b51936f-e42a-4b5b-bf7f-7136cbd0e9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132698627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.2132698627
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.2263762760
Short name T322
Test name
Test status
Simulation time 165677032023 ps
CPU time 209.88 seconds
Started Aug 05 05:54:03 PM PDT 24
Finished Aug 05 05:57:33 PM PDT 24
Peak memory 183400 kb
Host smart-7e97c0a4-4194-4a1d-b5fa-4cef2ac8851b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263762760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.2263762760
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/100.rv_timer_random.2515897981
Short name T341
Test name
Test status
Simulation time 156384078849 ps
CPU time 259.6 seconds
Started Aug 05 05:57:46 PM PDT 24
Finished Aug 05 06:02:06 PM PDT 24
Peak memory 191648 kb
Host smart-ef75b3c1-699f-410d-a1f3-55f315d766e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515897981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.2515897981
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.4022658902
Short name T216
Test name
Test status
Simulation time 138378338140 ps
CPU time 1559.31 seconds
Started Aug 05 05:57:50 PM PDT 24
Finished Aug 05 06:23:49 PM PDT 24
Peak memory 191664 kb
Host smart-7fc2b2bc-7f6b-4213-b33d-b467d37f7f8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022658902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.4022658902
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.1239796078
Short name T173
Test name
Test status
Simulation time 231070883235 ps
CPU time 450.83 seconds
Started Aug 05 05:58:01 PM PDT 24
Finished Aug 05 06:05:32 PM PDT 24
Peak memory 191660 kb
Host smart-1080b030-0146-4c8c-a4c8-2de293b409f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239796078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.1239796078
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.2811793200
Short name T125
Test name
Test status
Simulation time 140914892487 ps
CPU time 245.03 seconds
Started Aug 05 05:58:05 PM PDT 24
Finished Aug 05 06:02:10 PM PDT 24
Peak memory 191648 kb
Host smart-e50e99fd-9bf5-473b-a3c9-7bc45bdd59aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811793200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.2811793200
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random.3776201602
Short name T290
Test name
Test status
Simulation time 121915762073 ps
CPU time 200.97 seconds
Started Aug 05 05:54:16 PM PDT 24
Finished Aug 05 05:57:37 PM PDT 24
Peak memory 191644 kb
Host smart-7c553a23-9a93-4e29-ab42-29d6a36f70d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776201602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.3776201602
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.4223350122
Short name T190
Test name
Test status
Simulation time 39246887376 ps
CPU time 56.62 seconds
Started Aug 05 05:58:16 PM PDT 24
Finished Aug 05 05:59:13 PM PDT 24
Peak memory 193680 kb
Host smart-6d3c0b1b-17c6-4642-ba4d-f715f325a9e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223350122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.4223350122
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.4158855623
Short name T120
Test name
Test status
Simulation time 221614343313 ps
CPU time 352.03 seconds
Started Aug 05 05:58:17 PM PDT 24
Finished Aug 05 06:04:09 PM PDT 24
Peak memory 191640 kb
Host smart-cfd01ee9-6457-4273-8d59-f36ada52be87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158855623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.4158855623
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.2394181027
Short name T243
Test name
Test status
Simulation time 304239750714 ps
CPU time 468.87 seconds
Started Aug 05 05:58:16 PM PDT 24
Finished Aug 05 06:06:05 PM PDT 24
Peak memory 191864 kb
Host smart-750a7ca7-22ba-47ac-bf00-0e52304bc1b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394181027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.2394181027
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.4207402964
Short name T24
Test name
Test status
Simulation time 86339505730 ps
CPU time 105.3 seconds
Started Aug 05 05:54:32 PM PDT 24
Finished Aug 05 05:56:17 PM PDT 24
Peak memory 191664 kb
Host smart-ba836a7e-2563-4959-b728-e1f758657516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207402964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.4207402964
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_random.3697252860
Short name T289
Test name
Test status
Simulation time 110962072190 ps
CPU time 789.37 seconds
Started Aug 05 05:54:36 PM PDT 24
Finished Aug 05 06:07:45 PM PDT 24
Peak memory 191692 kb
Host smart-5ecf8076-236d-4839-8664-8a96b221c6a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697252860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.3697252860
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random.2144984990
Short name T271
Test name
Test status
Simulation time 180002250128 ps
CPU time 760.48 seconds
Started Aug 05 05:54:44 PM PDT 24
Finished Aug 05 06:07:25 PM PDT 24
Peak memory 191648 kb
Host smart-66083385-bd90-4605-ab93-72d66b5f6fd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144984990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.2144984990
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.2847719887
Short name T150
Test name
Test status
Simulation time 484668477993 ps
CPU time 139.36 seconds
Started Aug 05 05:54:49 PM PDT 24
Finished Aug 05 05:57:09 PM PDT 24
Peak memory 183444 kb
Host smart-153b1dff-1056-4298-ab2c-80640fe5e264
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847719887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.2847719887
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.3846344317
Short name T144
Test name
Test status
Simulation time 180513416730 ps
CPU time 260.41 seconds
Started Aug 05 05:54:52 PM PDT 24
Finished Aug 05 05:59:13 PM PDT 24
Peak memory 183440 kb
Host smart-9b4174a7-9ed1-4af3-9a1f-f5418f88e099
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846344317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.3846344317
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.3447607408
Short name T171
Test name
Test status
Simulation time 2501148080062 ps
CPU time 1192.96 seconds
Started Aug 05 05:54:59 PM PDT 24
Finished Aug 05 06:14:52 PM PDT 24
Peak memory 183484 kb
Host smart-8de0ff77-46c2-4b79-893c-4842204f11f5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447607408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.3447607408
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_random.4269964490
Short name T109
Test name
Test status
Simulation time 104720588355 ps
CPU time 165.66 seconds
Started Aug 05 05:55:00 PM PDT 24
Finished Aug 05 05:57:46 PM PDT 24
Peak memory 183488 kb
Host smart-6ed6f9bf-5a10-4e29-9a25-6c38b23b49ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269964490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.4269964490
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random.1468402873
Short name T105
Test name
Test status
Simulation time 368462947726 ps
CPU time 719.91 seconds
Started Aug 05 05:55:00 PM PDT 24
Finished Aug 05 06:07:00 PM PDT 24
Peak memory 191660 kb
Host smart-2871a805-2515-456e-bbed-fe3a9c885c22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468402873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.1468402873
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random.3718770370
Short name T26
Test name
Test status
Simulation time 260977312078 ps
CPU time 668.42 seconds
Started Aug 05 05:55:21 PM PDT 24
Finished Aug 05 06:06:29 PM PDT 24
Peak memory 191692 kb
Host smart-cf407a07-4d4b-4fdc-91e8-0afdcc30335e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718770370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.3718770370
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random.1707360513
Short name T357
Test name
Test status
Simulation time 66416365374 ps
CPU time 90.81 seconds
Started Aug 05 05:55:30 PM PDT 24
Finished Aug 05 05:57:01 PM PDT 24
Peak memory 191668 kb
Host smart-9439489c-e5f1-43e9-854a-da476ed7fd6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707360513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.1707360513
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random.3435873886
Short name T287
Test name
Test status
Simulation time 605734212755 ps
CPU time 1524.46 seconds
Started Aug 05 05:55:36 PM PDT 24
Finished Aug 05 06:21:01 PM PDT 24
Peak memory 191636 kb
Host smart-2362628d-c21f-4d78-927e-bb9924516b80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435873886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.3435873886
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.1819640036
Short name T329
Test name
Test status
Simulation time 391442353468 ps
CPU time 193.77 seconds
Started Aug 05 05:55:35 PM PDT 24
Finished Aug 05 05:58:49 PM PDT 24
Peak memory 191716 kb
Host smart-562f94a0-1252-41e8-95db-40f010a81c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819640036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.1819640036
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.2647298598
Short name T237
Test name
Test status
Simulation time 44034352336 ps
CPU time 21.67 seconds
Started Aug 05 05:56:08 PM PDT 24
Finished Aug 05 05:56:29 PM PDT 24
Peak memory 191672 kb
Host smart-b9966abf-b5b0-4d6f-bd64-da64f91c45ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647298598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.2647298598
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_random.2143821132
Short name T205
Test name
Test status
Simulation time 396148605927 ps
CPU time 922.2 seconds
Started Aug 05 05:56:47 PM PDT 24
Finished Aug 05 06:12:09 PM PDT 24
Peak memory 191632 kb
Host smart-508cd4df-73ce-43ac-bd48-cf8f118a0930
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143821132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.2143821132
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.2658228598
Short name T90
Test name
Test status
Simulation time 28118577359 ps
CPU time 14.99 seconds
Started Aug 05 05:57:17 PM PDT 24
Finished Aug 05 05:57:32 PM PDT 24
Peak memory 183412 kb
Host smart-f6f3b167-1005-479f-8c90-fa97d9437f1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658228598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.2658228598
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.4104947473
Short name T231
Test name
Test status
Simulation time 314327475426 ps
CPU time 277.99 seconds
Started Aug 05 05:57:22 PM PDT 24
Finished Aug 05 06:02:00 PM PDT 24
Peak memory 191664 kb
Host smart-01577be6-1887-48b6-8f5b-9751131d03f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104947473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.4104947473
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.2327491920
Short name T206
Test name
Test status
Simulation time 32001403626 ps
CPU time 354.31 seconds
Started Aug 05 05:57:39 PM PDT 24
Finished Aug 05 06:03:33 PM PDT 24
Peak memory 183436 kb
Host smart-90c558bb-aacc-48da-8810-46e28627d946
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327491920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.2327491920
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3877964998
Short name T70
Test name
Test status
Simulation time 15481140 ps
CPU time 0.71 seconds
Started Aug 05 05:49:25 PM PDT 24
Finished Aug 05 05:49:26 PM PDT 24
Peak memory 182936 kb
Host smart-5d7224a0-2317-4e63-89eb-265264afe430
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877964998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.3877964998
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3914645355
Short name T572
Test name
Test status
Simulation time 309155953 ps
CPU time 3.19 seconds
Started Aug 05 05:49:43 PM PDT 24
Finished Aug 05 05:49:46 PM PDT 24
Peak memory 191304 kb
Host smart-9573f92f-93d7-42cc-9b9b-e5468b0a9f38
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914645355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.3914645355
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.513642887
Short name T83
Test name
Test status
Simulation time 21035278 ps
CPU time 0.6 seconds
Started Aug 05 05:49:36 PM PDT 24
Finished Aug 05 05:49:37 PM PDT 24
Peak memory 182900 kb
Host smart-9def3a21-0d8b-4e80-b905-210b9df3d041
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513642887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_re
set.513642887
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.2229915072
Short name T507
Test name
Test status
Simulation time 30577088 ps
CPU time 0.91 seconds
Started Aug 05 05:49:25 PM PDT 24
Finished Aug 05 05:49:26 PM PDT 24
Peak memory 196832 kb
Host smart-5f714f6b-80e5-432d-9eaa-a0d983651d68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229915072 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.2229915072
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.3706020775
Short name T81
Test name
Test status
Simulation time 27518161 ps
CPU time 0.6 seconds
Started Aug 05 05:49:22 PM PDT 24
Finished Aug 05 05:49:22 PM PDT 24
Peak memory 182948 kb
Host smart-5ef1367b-abfa-48f7-8d88-02f296193937
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706020775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.3706020775
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.3820921161
Short name T498
Test name
Test status
Simulation time 14191449 ps
CPU time 0.56 seconds
Started Aug 05 05:49:25 PM PDT 24
Finished Aug 05 05:49:30 PM PDT 24
Peak memory 182748 kb
Host smart-e9af826a-6705-4703-bc12-b686991fe045
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820921161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.3820921161
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.1905608223
Short name T532
Test name
Test status
Simulation time 117420537 ps
CPU time 0.76 seconds
Started Aug 05 05:49:25 PM PDT 24
Finished Aug 05 05:49:26 PM PDT 24
Peak memory 193384 kb
Host smart-6e2dda35-487b-495d-81d8-b467ee70021e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905608223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.1905608223
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.3581398254
Short name T475
Test name
Test status
Simulation time 174541674 ps
CPU time 2.42 seconds
Started Aug 05 05:49:29 PM PDT 24
Finished Aug 05 05:49:31 PM PDT 24
Peak memory 197632 kb
Host smart-76e83079-8258-4d2f-b570-5afee05fea19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581398254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.3581398254
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.2768688530
Short name T50
Test name
Test status
Simulation time 434794204 ps
CPU time 1.38 seconds
Started Aug 05 05:49:25 PM PDT 24
Finished Aug 05 05:49:26 PM PDT 24
Peak memory 195720 kb
Host smart-ca54872e-888a-4b40-95ff-2ef44a01da63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768688530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.2768688530
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.844758438
Short name T80
Test name
Test status
Simulation time 24491893 ps
CPU time 0.68 seconds
Started Aug 05 05:49:25 PM PDT 24
Finished Aug 05 05:49:26 PM PDT 24
Peak memory 192092 kb
Host smart-5b7239f8-4482-4112-873f-67ae0ff2d77e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844758438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alias
ing.844758438
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2717678895
Short name T534
Test name
Test status
Simulation time 1051574560 ps
CPU time 2.59 seconds
Started Aug 05 05:49:48 PM PDT 24
Finished Aug 05 05:49:53 PM PDT 24
Peak memory 191320 kb
Host smart-76950ee7-44fc-48f9-898e-dfe156aec77d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717678895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.2717678895
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.2096617807
Short name T508
Test name
Test status
Simulation time 14881825 ps
CPU time 0.59 seconds
Started Aug 05 05:49:23 PM PDT 24
Finished Aug 05 05:49:24 PM PDT 24
Peak memory 182928 kb
Host smart-c7f0aa90-0670-41df-bd82-55414366524f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096617807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.2096617807
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.3515959529
Short name T524
Test name
Test status
Simulation time 24696704 ps
CPU time 1.11 seconds
Started Aug 05 05:49:51 PM PDT 24
Finished Aug 05 05:49:52 PM PDT 24
Peak memory 197568 kb
Host smart-38481d00-d402-43df-91af-e738d50badeb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515959529 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.3515959529
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.3004860259
Short name T79
Test name
Test status
Simulation time 31538598 ps
CPU time 0.63 seconds
Started Aug 05 05:49:26 PM PDT 24
Finished Aug 05 05:49:26 PM PDT 24
Peak memory 182940 kb
Host smart-ed97ae2b-8935-4c4e-9f18-153733011fae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004860259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.3004860259
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.965604256
Short name T453
Test name
Test status
Simulation time 30598860 ps
CPU time 0.56 seconds
Started Aug 05 05:49:49 PM PDT 24
Finished Aug 05 05:49:55 PM PDT 24
Peak memory 182788 kb
Host smart-b53f7e83-d68f-4d59-87e4-f567f6adadd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965604256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.965604256
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.514925490
Short name T69
Test name
Test status
Simulation time 141703251 ps
CPU time 0.83 seconds
Started Aug 05 05:49:23 PM PDT 24
Finished Aug 05 05:49:24 PM PDT 24
Peak memory 193752 kb
Host smart-a2bb10a4-2c37-490b-9115-18eeacd498dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514925490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_tim
er_same_csr_outstanding.514925490
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.2487812103
Short name T546
Test name
Test status
Simulation time 155684515 ps
CPU time 0.88 seconds
Started Aug 05 05:49:49 PM PDT 24
Finished Aug 05 05:49:49 PM PDT 24
Peak memory 191348 kb
Host smart-5205fffd-b055-45eb-97d7-c5a5a039144e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487812103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.2487812103
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.1487853909
Short name T32
Test name
Test status
Simulation time 417858934 ps
CPU time 0.86 seconds
Started Aug 05 05:49:47 PM PDT 24
Finished Aug 05 05:49:53 PM PDT 24
Peak memory 183248 kb
Host smart-4a9624e2-a077-4c77-89f2-5f11e42c8200
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487853909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.1487853909
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.2233116571
Short name T568
Test name
Test status
Simulation time 343918347 ps
CPU time 0.81 seconds
Started Aug 05 05:49:40 PM PDT 24
Finished Aug 05 05:49:41 PM PDT 24
Peak memory 196240 kb
Host smart-9ec13340-557b-4de6-80ad-f3c2b071e99a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233116571 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.2233116571
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.2741873534
Short name T518
Test name
Test status
Simulation time 16795454 ps
CPU time 0.55 seconds
Started Aug 05 05:49:38 PM PDT 24
Finished Aug 05 05:49:39 PM PDT 24
Peak memory 182748 kb
Host smart-5dd51541-caea-4c31-9f8d-1baba4ae6f0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741873534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.2741873534
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2591055396
Short name T505
Test name
Test status
Simulation time 14462047 ps
CPU time 0.59 seconds
Started Aug 05 05:49:43 PM PDT 24
Finished Aug 05 05:49:48 PM PDT 24
Peak memory 192164 kb
Host smart-62d8d85b-5c1f-4a8a-8159-7d065c345332
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591055396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.2591055396
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.511279760
Short name T511
Test name
Test status
Simulation time 92605682 ps
CPU time 1.9 seconds
Started Aug 05 05:49:46 PM PDT 24
Finished Aug 05 05:49:48 PM PDT 24
Peak memory 197496 kb
Host smart-6cc7c95f-278a-4554-b7b5-02b7568bd7c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511279760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.511279760
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.959580170
Short name T545
Test name
Test status
Simulation time 44544913 ps
CPU time 0.8 seconds
Started Aug 05 05:49:44 PM PDT 24
Finished Aug 05 05:49:45 PM PDT 24
Peak memory 183208 kb
Host smart-49e7f996-3d61-473f-a1fd-6b5c5d222b0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959580170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_in
tg_err.959580170
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.2801997779
Short name T503
Test name
Test status
Simulation time 42433473 ps
CPU time 0.75 seconds
Started Aug 05 05:49:49 PM PDT 24
Finished Aug 05 05:49:50 PM PDT 24
Peak memory 195160 kb
Host smart-9e79b12f-ab32-4d79-83e2-ceb4349d7515
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801997779 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.2801997779
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.1405588964
Short name T82
Test name
Test status
Simulation time 38558702 ps
CPU time 0.57 seconds
Started Aug 05 05:49:33 PM PDT 24
Finished Aug 05 05:49:33 PM PDT 24
Peak memory 182924 kb
Host smart-60897277-f614-48ef-8eeb-7855ed80b00e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405588964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.1405588964
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.4216208754
Short name T552
Test name
Test status
Simulation time 14491384 ps
CPU time 0.54 seconds
Started Aug 05 05:49:42 PM PDT 24
Finished Aug 05 05:49:43 PM PDT 24
Peak memory 182440 kb
Host smart-47c96fac-7bd4-4b97-a6f5-5bb0a8a3f59f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216208754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.4216208754
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.1929547852
Short name T500
Test name
Test status
Simulation time 21611550 ps
CPU time 0.61 seconds
Started Aug 05 05:49:46 PM PDT 24
Finished Aug 05 05:49:46 PM PDT 24
Peak memory 192244 kb
Host smart-29c452a0-76e0-4e49-ab7c-a1b81b4b0dad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929547852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.1929547852
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.146549944
Short name T488
Test name
Test status
Simulation time 54918287 ps
CPU time 1.31 seconds
Started Aug 05 05:49:51 PM PDT 24
Finished Aug 05 05:49:53 PM PDT 24
Peak memory 197636 kb
Host smart-0e7f91a8-a8b7-4c0a-b319-a52b9e45503d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146549944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.146549944
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.4093487981
Short name T480
Test name
Test status
Simulation time 219368641 ps
CPU time 1.42 seconds
Started Aug 05 05:49:47 PM PDT 24
Finished Aug 05 05:49:48 PM PDT 24
Peak memory 183684 kb
Host smart-441ad544-29ba-4eab-89bf-b6acba0d90c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093487981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.4093487981
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3578567209
Short name T544
Test name
Test status
Simulation time 115585630 ps
CPU time 0.77 seconds
Started Aug 05 05:49:31 PM PDT 24
Finished Aug 05 05:49:32 PM PDT 24
Peak memory 195752 kb
Host smart-7898dd19-4087-450c-9053-92f5ab010916
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578567209 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.3578567209
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1448523116
Short name T486
Test name
Test status
Simulation time 40751336 ps
CPU time 0.54 seconds
Started Aug 05 05:49:51 PM PDT 24
Finished Aug 05 05:49:52 PM PDT 24
Peak memory 182660 kb
Host smart-7c62d74b-1bdc-428d-8aca-b2e9580ecc00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448523116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.1448523116
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.1929774237
Short name T473
Test name
Test status
Simulation time 24053198 ps
CPU time 0.57 seconds
Started Aug 05 05:49:33 PM PDT 24
Finished Aug 05 05:49:34 PM PDT 24
Peak memory 182808 kb
Host smart-d87615ac-2ce7-4b27-b8c8-2ef1c8322a1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929774237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.1929774237
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.3537311472
Short name T454
Test name
Test status
Simulation time 40006495 ps
CPU time 1.09 seconds
Started Aug 05 05:49:36 PM PDT 24
Finished Aug 05 05:49:38 PM PDT 24
Peak memory 197508 kb
Host smart-a01d813a-457b-493c-9b26-fe3a3adb47a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537311472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.3537311472
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.1679338595
Short name T526
Test name
Test status
Simulation time 140593577 ps
CPU time 1.4 seconds
Started Aug 05 05:49:44 PM PDT 24
Finished Aug 05 05:49:46 PM PDT 24
Peak memory 194764 kb
Host smart-df2ed32d-b0ae-4bb5-9422-9d1bf1f6db84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679338595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.1679338595
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.3827816240
Short name T525
Test name
Test status
Simulation time 19664520 ps
CPU time 0.68 seconds
Started Aug 05 05:49:49 PM PDT 24
Finished Aug 05 05:49:50 PM PDT 24
Peak memory 195272 kb
Host smart-e00b181c-69aa-4225-a53c-fac6a4854b18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827816240 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.3827816240
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3651705581
Short name T33
Test name
Test status
Simulation time 13684608 ps
CPU time 0.55 seconds
Started Aug 05 05:49:39 PM PDT 24
Finished Aug 05 05:49:40 PM PDT 24
Peak memory 182972 kb
Host smart-12421237-6025-4497-a07c-24402a3663d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651705581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.3651705581
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3813735437
Short name T476
Test name
Test status
Simulation time 12436111 ps
CPU time 0.53 seconds
Started Aug 05 05:49:49 PM PDT 24
Finished Aug 05 05:49:51 PM PDT 24
Peak memory 182228 kb
Host smart-781f0f33-9e07-4e75-93e6-883673ab85f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813735437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.3813735437
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1592309119
Short name T548
Test name
Test status
Simulation time 33140135 ps
CPU time 0.73 seconds
Started Aug 05 05:49:39 PM PDT 24
Finished Aug 05 05:49:40 PM PDT 24
Peak memory 193660 kb
Host smart-e244994e-a425-4519-927b-368095f0c3eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592309119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.1592309119
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.1659540640
Short name T464
Test name
Test status
Simulation time 52803797 ps
CPU time 1.27 seconds
Started Aug 05 05:49:35 PM PDT 24
Finished Aug 05 05:49:36 PM PDT 24
Peak memory 197552 kb
Host smart-5c665859-5ef7-417e-ade9-a3e8c0429533
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659540640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.1659540640
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1636724163
Short name T31
Test name
Test status
Simulation time 154698915 ps
CPU time 0.79 seconds
Started Aug 05 05:49:42 PM PDT 24
Finished Aug 05 05:49:43 PM PDT 24
Peak memory 193732 kb
Host smart-73a01318-5aac-4e22-add6-516ff92f2d7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636724163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.1636724163
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.3148902488
Short name T538
Test name
Test status
Simulation time 29782915 ps
CPU time 0.87 seconds
Started Aug 05 05:49:38 PM PDT 24
Finished Aug 05 05:49:39 PM PDT 24
Peak memory 197576 kb
Host smart-d7119e9e-b3e0-416a-a854-051bf28c6173
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148902488 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.3148902488
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.4200356867
Short name T85
Test name
Test status
Simulation time 14590494 ps
CPU time 0.54 seconds
Started Aug 05 05:49:40 PM PDT 24
Finished Aug 05 05:49:41 PM PDT 24
Peak memory 182356 kb
Host smart-07435b5e-bb01-47ff-a164-bbb02beea1d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200356867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.4200356867
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.3252947483
Short name T573
Test name
Test status
Simulation time 15187051 ps
CPU time 0.55 seconds
Started Aug 05 05:49:36 PM PDT 24
Finished Aug 05 05:49:42 PM PDT 24
Peak memory 182836 kb
Host smart-e2fc0697-0486-4618-bc8b-64f33fc8c2ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252947483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.3252947483
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.204443990
Short name T84
Test name
Test status
Simulation time 140250696 ps
CPU time 0.57 seconds
Started Aug 05 05:49:37 PM PDT 24
Finished Aug 05 05:49:38 PM PDT 24
Peak memory 191568 kb
Host smart-65a9c6a5-0d43-4a2c-abcf-c4b707645ebb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204443990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_ti
mer_same_csr_outstanding.204443990
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2413199598
Short name T577
Test name
Test status
Simulation time 52210053 ps
CPU time 2.43 seconds
Started Aug 05 05:49:29 PM PDT 24
Finished Aug 05 05:49:32 PM PDT 24
Peak memory 197732 kb
Host smart-670c6344-918c-4f5c-bce4-aab385df041c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413199598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.2413199598
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.2697273359
Short name T551
Test name
Test status
Simulation time 196895424 ps
CPU time 1.26 seconds
Started Aug 05 05:49:42 PM PDT 24
Finished Aug 05 05:49:44 PM PDT 24
Peak memory 194452 kb
Host smart-eb99d0ff-d265-4023-98a2-7c2c746aed7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697273359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.2697273359
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.3606132322
Short name T575
Test name
Test status
Simulation time 23503338 ps
CPU time 0.65 seconds
Started Aug 05 05:49:55 PM PDT 24
Finished Aug 05 05:49:55 PM PDT 24
Peak memory 194192 kb
Host smart-d598b4f0-99e9-4b04-8b7a-2b56d71b33ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606132322 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.3606132322
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.1042989304
Short name T566
Test name
Test status
Simulation time 15668372 ps
CPU time 0.59 seconds
Started Aug 05 05:49:52 PM PDT 24
Finished Aug 05 05:49:53 PM PDT 24
Peak memory 182944 kb
Host smart-af3a9d22-0a6d-473f-a03d-f2005a5113a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042989304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.1042989304
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.3593020310
Short name T497
Test name
Test status
Simulation time 11253699 ps
CPU time 0.55 seconds
Started Aug 05 05:49:43 PM PDT 24
Finished Aug 05 05:49:43 PM PDT 24
Peak memory 182264 kb
Host smart-6d43322b-1f0f-4c03-b221-cd4d879bb284
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593020310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.3593020310
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.3634621469
Short name T561
Test name
Test status
Simulation time 50740282 ps
CPU time 0.62 seconds
Started Aug 05 05:49:44 PM PDT 24
Finished Aug 05 05:49:45 PM PDT 24
Peak memory 192264 kb
Host smart-a87f0b2c-11ac-489e-bd5e-69c6b84c4773
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634621469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.3634621469
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1361943557
Short name T501
Test name
Test status
Simulation time 41873352 ps
CPU time 1.13 seconds
Started Aug 05 05:49:42 PM PDT 24
Finished Aug 05 05:49:43 PM PDT 24
Peak memory 197476 kb
Host smart-bf27fca7-99b3-4591-8b65-9f298df8f324
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361943557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.1361943557
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.3423721796
Short name T463
Test name
Test status
Simulation time 61266773 ps
CPU time 0.69 seconds
Started Aug 05 05:49:50 PM PDT 24
Finished Aug 05 05:49:51 PM PDT 24
Peak memory 194764 kb
Host smart-117b23ae-f188-4eef-abbd-1ba18deabef9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423721796 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.3423721796
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.3343365019
Short name T78
Test name
Test status
Simulation time 188602742 ps
CPU time 0.6 seconds
Started Aug 05 05:50:01 PM PDT 24
Finished Aug 05 05:50:02 PM PDT 24
Peak memory 183048 kb
Host smart-40f9d237-68b2-4114-8d8e-3e5cddf57d75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343365019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.3343365019
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.3760924098
Short name T451
Test name
Test status
Simulation time 14326166 ps
CPU time 0.56 seconds
Started Aug 05 05:49:46 PM PDT 24
Finished Aug 05 05:49:46 PM PDT 24
Peak memory 182784 kb
Host smart-eb9332b8-9ec3-4086-9cf1-49e5237109d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760924098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.3760924098
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.3110318681
Short name T506
Test name
Test status
Simulation time 18688169 ps
CPU time 0.61 seconds
Started Aug 05 05:49:50 PM PDT 24
Finished Aug 05 05:49:51 PM PDT 24
Peak memory 191776 kb
Host smart-e7f484e7-4a65-44ac-b03e-1d361c046435
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110318681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.3110318681
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.1119818700
Short name T571
Test name
Test status
Simulation time 104350218 ps
CPU time 1.4 seconds
Started Aug 05 05:49:56 PM PDT 24
Finished Aug 05 05:49:57 PM PDT 24
Peak memory 197640 kb
Host smart-28a12e21-4785-4376-b8b8-70909f7e1cd1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119818700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.1119818700
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.772724308
Short name T563
Test name
Test status
Simulation time 20030014 ps
CPU time 0.77 seconds
Started Aug 05 05:49:52 PM PDT 24
Finished Aug 05 05:49:53 PM PDT 24
Peak memory 195552 kb
Host smart-8a27aca4-5952-46fd-99f0-d44b06258b2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772724308 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.772724308
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.3342015066
Short name T510
Test name
Test status
Simulation time 21686525 ps
CPU time 0.54 seconds
Started Aug 05 05:49:40 PM PDT 24
Finished Aug 05 05:49:41 PM PDT 24
Peak memory 182052 kb
Host smart-ba386dd6-9646-4cb5-baed-079272cf423d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342015066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.3342015066
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3370916281
Short name T542
Test name
Test status
Simulation time 13323445 ps
CPU time 0.55 seconds
Started Aug 05 05:49:44 PM PDT 24
Finished Aug 05 05:49:45 PM PDT 24
Peak memory 182736 kb
Host smart-b5f04269-9820-45b4-9820-b32a7419de20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370916281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.3370916281
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.1450456762
Short name T495
Test name
Test status
Simulation time 20485570 ps
CPU time 0.65 seconds
Started Aug 05 05:50:03 PM PDT 24
Finished Aug 05 05:50:04 PM PDT 24
Peak memory 191568 kb
Host smart-be6a296a-e41f-41d8-80b2-409d54278de6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450456762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.1450456762
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.3609984361
Short name T468
Test name
Test status
Simulation time 93555533 ps
CPU time 1.84 seconds
Started Aug 05 05:49:52 PM PDT 24
Finished Aug 05 05:49:54 PM PDT 24
Peak memory 197696 kb
Host smart-daf3d622-2423-4bd5-9cde-91d218fcf072
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609984361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.3609984361
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.671031095
Short name T509
Test name
Test status
Simulation time 180744094 ps
CPU time 0.84 seconds
Started Aug 05 05:49:43 PM PDT 24
Finished Aug 05 05:49:44 PM PDT 24
Peak memory 194144 kb
Host smart-8e5598f1-cc87-4a08-9ae9-807f60fc36f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671031095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_in
tg_err.671031095
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.782530917
Short name T547
Test name
Test status
Simulation time 154857274 ps
CPU time 1.02 seconds
Started Aug 05 05:49:39 PM PDT 24
Finished Aug 05 05:49:40 PM PDT 24
Peak memory 197572 kb
Host smart-22b6e2be-1665-4eb9-a2a0-c8c0895ff8e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782530917 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.782530917
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.2206059337
Short name T68
Test name
Test status
Simulation time 14117724 ps
CPU time 0.55 seconds
Started Aug 05 05:49:39 PM PDT 24
Finished Aug 05 05:49:40 PM PDT 24
Peak memory 182708 kb
Host smart-d8c5c483-5cae-4a7c-912e-b820ee734836
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206059337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.2206059337
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.4255266722
Short name T574
Test name
Test status
Simulation time 12256763 ps
CPU time 0.56 seconds
Started Aug 05 05:49:48 PM PDT 24
Finished Aug 05 05:49:49 PM PDT 24
Peak memory 182224 kb
Host smart-0e61f61f-dd39-4c70-85d8-b88a469c1706
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255266722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.4255266722
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1188527474
Short name T87
Test name
Test status
Simulation time 52558006 ps
CPU time 0.71 seconds
Started Aug 05 05:49:54 PM PDT 24
Finished Aug 05 05:49:55 PM PDT 24
Peak memory 193612 kb
Host smart-da47f69c-80c3-482c-8fcd-f709e231d3b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188527474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.1188527474
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.784431116
Short name T549
Test name
Test status
Simulation time 563730960 ps
CPU time 2.62 seconds
Started Aug 05 05:49:39 PM PDT 24
Finished Aug 05 05:49:47 PM PDT 24
Peak memory 191328 kb
Host smart-a013197c-569e-4232-8965-a1a58ae8799a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784431116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.784431116
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.4113730073
Short name T578
Test name
Test status
Simulation time 468156872 ps
CPU time 1.37 seconds
Started Aug 05 05:49:39 PM PDT 24
Finished Aug 05 05:49:41 PM PDT 24
Peak memory 195600 kb
Host smart-ebebd6ce-7a83-4bf6-a860-c0242e7b2e33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113730073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.4113730073
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.859049776
Short name T553
Test name
Test status
Simulation time 24025907 ps
CPU time 1.06 seconds
Started Aug 05 05:49:52 PM PDT 24
Finished Aug 05 05:49:53 PM PDT 24
Peak memory 197760 kb
Host smart-f91284b9-4064-4122-8c4f-5e3ac909d4d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859049776 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.859049776
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.3855808746
Short name T527
Test name
Test status
Simulation time 30584703 ps
CPU time 0.55 seconds
Started Aug 05 05:49:41 PM PDT 24
Finished Aug 05 05:49:42 PM PDT 24
Peak memory 182880 kb
Host smart-92a73cdb-c2e0-4e1c-9be3-af4182d9c799
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855808746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.3855808746
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.1389930336
Short name T567
Test name
Test status
Simulation time 27317543 ps
CPU time 0.56 seconds
Started Aug 05 05:49:41 PM PDT 24
Finished Aug 05 05:49:42 PM PDT 24
Peak memory 182768 kb
Host smart-925749cc-a5fb-42ea-be0d-cf318fd7eaaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389930336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.1389930336
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2335691029
Short name T49
Test name
Test status
Simulation time 41433893 ps
CPU time 0.64 seconds
Started Aug 05 05:49:40 PM PDT 24
Finished Aug 05 05:49:41 PM PDT 24
Peak memory 191796 kb
Host smart-d6ca0e9d-e449-43d7-ab2a-039f0efff219
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335691029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.2335691029
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3085693526
Short name T559
Test name
Test status
Simulation time 19835031 ps
CPU time 0.97 seconds
Started Aug 05 05:49:59 PM PDT 24
Finished Aug 05 05:50:00 PM PDT 24
Peak memory 197444 kb
Host smart-4f32b1f1-23f8-49d0-b942-c823474bc62e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085693526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.3085693526
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.3357018370
Short name T485
Test name
Test status
Simulation time 82564004 ps
CPU time 0.81 seconds
Started Aug 05 05:49:42 PM PDT 24
Finished Aug 05 05:49:43 PM PDT 24
Peak memory 193712 kb
Host smart-9f053d22-7f6a-47e3-86f2-412f2559fad2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357018370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.3357018370
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.1089232774
Short name T72
Test name
Test status
Simulation time 88002380 ps
CPU time 0.73 seconds
Started Aug 05 05:49:25 PM PDT 24
Finished Aug 05 05:49:27 PM PDT 24
Peak memory 192788 kb
Host smart-24c76c89-d64e-4d25-9970-f6674c5b2be6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089232774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.1089232774
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.2115131899
Short name T97
Test name
Test status
Simulation time 193327090 ps
CPU time 2.62 seconds
Started Aug 05 05:49:53 PM PDT 24
Finished Aug 05 05:49:55 PM PDT 24
Peak memory 191316 kb
Host smart-6eb0fd62-c39e-4d7e-ae01-ebacc4999ad1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115131899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.2115131899
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.4162647775
Short name T512
Test name
Test status
Simulation time 49247670 ps
CPU time 0.56 seconds
Started Aug 05 05:49:52 PM PDT 24
Finished Aug 05 05:49:53 PM PDT 24
Peak memory 182932 kb
Host smart-8fb2ad68-17d8-42dc-9931-3ad26523c270
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162647775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.4162647775
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3753412059
Short name T489
Test name
Test status
Simulation time 16915515 ps
CPU time 0.8 seconds
Started Aug 05 05:49:25 PM PDT 24
Finished Aug 05 05:49:26 PM PDT 24
Peak memory 195736 kb
Host smart-e43b259e-2b2d-4126-b209-9d55d1600974
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753412059 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.3753412059
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.3574096391
Short name T531
Test name
Test status
Simulation time 52400396 ps
CPU time 0.57 seconds
Started Aug 05 05:49:29 PM PDT 24
Finished Aug 05 05:49:30 PM PDT 24
Peak memory 182960 kb
Host smart-251cff1e-526f-41c8-a038-eeffa2892f59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574096391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.3574096391
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.2237864095
Short name T490
Test name
Test status
Simulation time 11288412 ps
CPU time 0.55 seconds
Started Aug 05 05:49:47 PM PDT 24
Finished Aug 05 05:49:48 PM PDT 24
Peak memory 182824 kb
Host smart-3a84cbb6-8fce-4113-a77f-4f6c423cefc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237864095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.2237864095
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.1791536492
Short name T74
Test name
Test status
Simulation time 50707120 ps
CPU time 0.67 seconds
Started Aug 05 05:49:26 PM PDT 24
Finished Aug 05 05:49:27 PM PDT 24
Peak memory 192512 kb
Host smart-0de1ed8f-38d3-4728-9df8-955619f3bc27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791536492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.1791536492
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.1137145312
Short name T470
Test name
Test status
Simulation time 133446380 ps
CPU time 1.03 seconds
Started Aug 05 05:49:26 PM PDT 24
Finished Aug 05 05:49:27 PM PDT 24
Peak memory 197492 kb
Host smart-f1f04dde-f9a9-4b76-918f-890ae953adae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137145312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.1137145312
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.3414776332
Short name T101
Test name
Test status
Simulation time 200750650 ps
CPU time 1.09 seconds
Started Aug 05 05:49:25 PM PDT 24
Finished Aug 05 05:49:26 PM PDT 24
Peak memory 195364 kb
Host smart-c1d29793-3b20-4af1-a516-dfec405376a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414776332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.3414776332
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.1945262818
Short name T460
Test name
Test status
Simulation time 11528332 ps
CPU time 0.56 seconds
Started Aug 05 05:49:55 PM PDT 24
Finished Aug 05 05:49:56 PM PDT 24
Peak memory 182800 kb
Host smart-c6ee013d-7c69-4afc-a515-a0d9bc822ded
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945262818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.1945262818
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.508305182
Short name T562
Test name
Test status
Simulation time 14368035 ps
CPU time 0.57 seconds
Started Aug 05 05:49:52 PM PDT 24
Finished Aug 05 05:49:52 PM PDT 24
Peak memory 182736 kb
Host smart-8cf753db-bee0-4aa3-89c7-622797606edd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508305182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.508305182
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.2268016045
Short name T565
Test name
Test status
Simulation time 16839995 ps
CPU time 0.54 seconds
Started Aug 05 05:49:47 PM PDT 24
Finished Aug 05 05:49:48 PM PDT 24
Peak memory 182764 kb
Host smart-371dcfd6-99f7-4713-85e8-c0d89cbe7ca5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268016045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.2268016045
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.426479126
Short name T580
Test name
Test status
Simulation time 22130476 ps
CPU time 0.54 seconds
Started Aug 05 05:49:49 PM PDT 24
Finished Aug 05 05:49:50 PM PDT 24
Peak memory 182224 kb
Host smart-8ad58817-fc8b-44a0-96b0-9fddddfa54a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426479126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.426479126
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.1923189535
Short name T514
Test name
Test status
Simulation time 19141841 ps
CPU time 0.54 seconds
Started Aug 05 05:49:56 PM PDT 24
Finished Aug 05 05:49:56 PM PDT 24
Peak memory 182240 kb
Host smart-812fc963-6770-4717-afc7-9c2d82d02bea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923189535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.1923189535
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.4287929417
Short name T550
Test name
Test status
Simulation time 80402805 ps
CPU time 0.55 seconds
Started Aug 05 05:49:44 PM PDT 24
Finished Aug 05 05:49:45 PM PDT 24
Peak memory 182664 kb
Host smart-e5fdb423-996f-42a7-8a64-1a9dbc52662f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287929417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.4287929417
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1637396541
Short name T471
Test name
Test status
Simulation time 44067146 ps
CPU time 0.57 seconds
Started Aug 05 05:49:52 PM PDT 24
Finished Aug 05 05:49:53 PM PDT 24
Peak memory 182420 kb
Host smart-75c34860-9017-4e06-8d82-80bcd95d39ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637396541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.1637396541
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.1509930749
Short name T530
Test name
Test status
Simulation time 39951967 ps
CPU time 0.52 seconds
Started Aug 05 05:49:40 PM PDT 24
Finished Aug 05 05:49:41 PM PDT 24
Peak memory 182252 kb
Host smart-127229dc-04f3-41af-88c9-11a23488c6a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509930749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.1509930749
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2997467847
Short name T554
Test name
Test status
Simulation time 15452305 ps
CPU time 0.56 seconds
Started Aug 05 05:49:58 PM PDT 24
Finished Aug 05 05:49:59 PM PDT 24
Peak memory 182712 kb
Host smart-d92b0984-8496-45d9-bb3a-34aa94aee2b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997467847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.2997467847
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.100684762
Short name T479
Test name
Test status
Simulation time 13226972 ps
CPU time 0.58 seconds
Started Aug 05 05:50:01 PM PDT 24
Finished Aug 05 05:50:02 PM PDT 24
Peak memory 182712 kb
Host smart-f6029d1f-95ca-4df1-9c9f-cc0b04418ede
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100684762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.100684762
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.1502366652
Short name T555
Test name
Test status
Simulation time 36544262 ps
CPU time 0.61 seconds
Started Aug 05 05:49:38 PM PDT 24
Finished Aug 05 05:49:39 PM PDT 24
Peak memory 182936 kb
Host smart-cb920f7c-9f60-41a2-b200-e3755d72d82c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502366652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.1502366652
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.3624066842
Short name T77
Test name
Test status
Simulation time 134747140 ps
CPU time 2.24 seconds
Started Aug 05 05:49:25 PM PDT 24
Finished Aug 05 05:49:28 PM PDT 24
Peak memory 192464 kb
Host smart-d58f08ac-4e32-40df-99c6-8929c1415955
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624066842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.3624066842
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.365407888
Short name T98
Test name
Test status
Simulation time 65696018 ps
CPU time 0.58 seconds
Started Aug 05 05:49:37 PM PDT 24
Finished Aug 05 05:49:42 PM PDT 24
Peak memory 182892 kb
Host smart-48f7a4f1-009e-4cf8-b27d-1afc4aa85857
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365407888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_re
set.365407888
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.2947448342
Short name T515
Test name
Test status
Simulation time 146957996 ps
CPU time 0.84 seconds
Started Aug 05 05:49:25 PM PDT 24
Finished Aug 05 05:49:27 PM PDT 24
Peak memory 196652 kb
Host smart-050df956-094b-4f3b-9205-651bc953bfa0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947448342 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.2947448342
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.2014305064
Short name T558
Test name
Test status
Simulation time 14274591 ps
CPU time 0.55 seconds
Started Aug 05 05:49:50 PM PDT 24
Finished Aug 05 05:49:51 PM PDT 24
Peak memory 182884 kb
Host smart-a7c7c7b4-e758-43f6-b7be-ddd8c7e39716
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014305064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.2014305064
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.1125902190
Short name T560
Test name
Test status
Simulation time 15525001 ps
CPU time 0.55 seconds
Started Aug 05 05:49:27 PM PDT 24
Finished Aug 05 05:49:28 PM PDT 24
Peak memory 182224 kb
Host smart-f329ae3f-4a18-48c2-8506-8cb87e0651bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125902190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.1125902190
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.1394058841
Short name T494
Test name
Test status
Simulation time 36245669 ps
CPU time 0.8 seconds
Started Aug 05 05:49:47 PM PDT 24
Finished Aug 05 05:49:47 PM PDT 24
Peak memory 193648 kb
Host smart-4d8f9330-130b-4a5d-be14-9e1837683bda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394058841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.1394058841
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.4151619696
Short name T517
Test name
Test status
Simulation time 143572401 ps
CPU time 2.95 seconds
Started Aug 05 05:49:54 PM PDT 24
Finished Aug 05 05:49:57 PM PDT 24
Peak memory 197704 kb
Host smart-661cab81-e62e-472e-949d-6105743ff6e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151619696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.4151619696
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.3577642055
Short name T100
Test name
Test status
Simulation time 46116929 ps
CPU time 0.9 seconds
Started Aug 05 05:49:29 PM PDT 24
Finished Aug 05 05:49:30 PM PDT 24
Peak memory 193896 kb
Host smart-fb20d0dd-91ca-4dd9-ad7a-2bfd75772e77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577642055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.3577642055
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.1350561539
Short name T457
Test name
Test status
Simulation time 14001043 ps
CPU time 0.54 seconds
Started Aug 05 05:49:44 PM PDT 24
Finished Aug 05 05:49:44 PM PDT 24
Peak memory 182432 kb
Host smart-e0372245-72a0-4fba-8e49-2e659a5ef1e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350561539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.1350561539
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.3536898474
Short name T469
Test name
Test status
Simulation time 46441606 ps
CPU time 0.56 seconds
Started Aug 05 05:50:02 PM PDT 24
Finished Aug 05 05:50:02 PM PDT 24
Peak memory 182712 kb
Host smart-85ca5bd8-a7f7-40c4-b4e0-4728d9629fe0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536898474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.3536898474
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.999514043
Short name T452
Test name
Test status
Simulation time 30977172 ps
CPU time 0.53 seconds
Started Aug 05 05:49:43 PM PDT 24
Finished Aug 05 05:49:54 PM PDT 24
Peak memory 182244 kb
Host smart-5277bcca-dcde-451e-8240-45a5652b35e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999514043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.999514043
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.900644355
Short name T533
Test name
Test status
Simulation time 20804409 ps
CPU time 0.55 seconds
Started Aug 05 05:50:00 PM PDT 24
Finished Aug 05 05:50:01 PM PDT 24
Peak memory 182440 kb
Host smart-6b8e42f3-9a56-4e55-b933-d2cfb19ed879
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900644355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.900644355
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.2129597709
Short name T491
Test name
Test status
Simulation time 41150667 ps
CPU time 0.58 seconds
Started Aug 05 05:50:00 PM PDT 24
Finished Aug 05 05:50:01 PM PDT 24
Peak memory 182792 kb
Host smart-be552d03-b685-4d7f-af51-9205ca245bce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129597709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.2129597709
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.314302038
Short name T519
Test name
Test status
Simulation time 37805255 ps
CPU time 0.53 seconds
Started Aug 05 05:49:55 PM PDT 24
Finished Aug 05 05:49:55 PM PDT 24
Peak memory 182224 kb
Host smart-30b5a866-99c7-4367-8d4c-3f6fa3070fd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314302038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.314302038
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.3300075807
Short name T576
Test name
Test status
Simulation time 34476009 ps
CPU time 0.55 seconds
Started Aug 05 05:49:44 PM PDT 24
Finished Aug 05 05:49:44 PM PDT 24
Peak memory 182464 kb
Host smart-093b1fa1-333c-4ce2-82bd-4003beb24617
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300075807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.3300075807
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.1194023162
Short name T472
Test name
Test status
Simulation time 13088911 ps
CPU time 0.54 seconds
Started Aug 05 05:50:03 PM PDT 24
Finished Aug 05 05:50:04 PM PDT 24
Peak memory 182224 kb
Host smart-a7e9a930-84e2-49f9-abda-afadd3ceea4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194023162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.1194023162
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.1464083405
Short name T564
Test name
Test status
Simulation time 41293980 ps
CPU time 0.52 seconds
Started Aug 05 05:49:40 PM PDT 24
Finished Aug 05 05:49:41 PM PDT 24
Peak memory 182196 kb
Host smart-6bf9fb09-2dd0-40e4-8b68-5ca8d57dec44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464083405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.1464083405
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.3693000733
Short name T459
Test name
Test status
Simulation time 30210772 ps
CPU time 0.53 seconds
Started Aug 05 05:49:51 PM PDT 24
Finished Aug 05 05:49:52 PM PDT 24
Peak memory 182792 kb
Host smart-aed44cb9-8747-430c-8768-d54e10dd5a56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693000733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.3693000733
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.4162391235
Short name T516
Test name
Test status
Simulation time 27524745 ps
CPU time 0.77 seconds
Started Aug 05 05:49:35 PM PDT 24
Finished Aug 05 05:49:36 PM PDT 24
Peak memory 192788 kb
Host smart-88b4c1d6-1fa5-463f-a2d0-e19e3f218705
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162391235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.4162391235
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.2157178779
Short name T482
Test name
Test status
Simulation time 1089423476 ps
CPU time 3.42 seconds
Started Aug 05 05:49:49 PM PDT 24
Finished Aug 05 05:49:53 PM PDT 24
Peak memory 191320 kb
Host smart-4e18b2d0-b29c-4422-baf7-4ea1c35bfc40
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157178779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.2157178779
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2677858568
Short name T541
Test name
Test status
Simulation time 22414201 ps
CPU time 0.54 seconds
Started Aug 05 05:49:51 PM PDT 24
Finished Aug 05 05:49:56 PM PDT 24
Peak memory 182424 kb
Host smart-6ab9979e-f63a-490e-a051-add2cd72873f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677858568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.2677858568
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.1209961505
Short name T513
Test name
Test status
Simulation time 110963969 ps
CPU time 0.83 seconds
Started Aug 05 05:49:41 PM PDT 24
Finished Aug 05 05:49:41 PM PDT 24
Peak memory 195940 kb
Host smart-9eb2b452-421c-479a-97e2-c092471ae373
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209961505 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.1209961505
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.3973161410
Short name T73
Test name
Test status
Simulation time 14034498 ps
CPU time 0.54 seconds
Started Aug 05 05:49:25 PM PDT 24
Finished Aug 05 05:49:25 PM PDT 24
Peak memory 182956 kb
Host smart-25125391-0030-4536-ab57-62409e073200
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973161410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.3973161410
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.2082754668
Short name T540
Test name
Test status
Simulation time 16637034 ps
CPU time 0.56 seconds
Started Aug 05 05:49:50 PM PDT 24
Finished Aug 05 05:49:51 PM PDT 24
Peak memory 182808 kb
Host smart-410ba2ce-47e0-4aff-9d62-7260d364edf0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082754668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.2082754668
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.4029152304
Short name T86
Test name
Test status
Simulation time 19256231 ps
CPU time 0.6 seconds
Started Aug 05 05:49:24 PM PDT 24
Finished Aug 05 05:49:25 PM PDT 24
Peak memory 191772 kb
Host smart-1b81c100-5256-4e3b-bb1e-ef8211586989
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029152304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.4029152304
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2422291658
Short name T529
Test name
Test status
Simulation time 265563901 ps
CPU time 1.48 seconds
Started Aug 05 05:49:28 PM PDT 24
Finished Aug 05 05:49:29 PM PDT 24
Peak memory 197740 kb
Host smart-ea5e4b52-8770-4a24-906c-e53f5500117e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422291658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.2422291658
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.3156520339
Short name T570
Test name
Test status
Simulation time 75665240 ps
CPU time 0.83 seconds
Started Aug 05 05:49:30 PM PDT 24
Finished Aug 05 05:49:31 PM PDT 24
Peak memory 183236 kb
Host smart-4cb6153e-f62a-4bcc-9c6d-ad7b79d4be32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156520339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.3156520339
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.3476109859
Short name T474
Test name
Test status
Simulation time 51593648 ps
CPU time 0.57 seconds
Started Aug 05 05:49:43 PM PDT 24
Finished Aug 05 05:49:44 PM PDT 24
Peak memory 182784 kb
Host smart-0e59f2f9-ef67-4911-849a-f07b91a57419
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476109859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.3476109859
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.307622261
Short name T467
Test name
Test status
Simulation time 14678134 ps
CPU time 0.55 seconds
Started Aug 05 05:49:51 PM PDT 24
Finished Aug 05 05:49:52 PM PDT 24
Peak memory 182624 kb
Host smart-b65a63fe-229e-4be6-8433-20b977217071
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307622261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.307622261
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.2867660649
Short name T456
Test name
Test status
Simulation time 41072706 ps
CPU time 0.55 seconds
Started Aug 05 05:49:45 PM PDT 24
Finished Aug 05 05:49:45 PM PDT 24
Peak memory 182268 kb
Host smart-9c05f662-4149-4335-bc3f-8f4cdf605d1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867660649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.2867660649
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.1094684590
Short name T477
Test name
Test status
Simulation time 20104134 ps
CPU time 0.54 seconds
Started Aug 05 05:49:51 PM PDT 24
Finished Aug 05 05:49:52 PM PDT 24
Peak memory 182660 kb
Host smart-fe0c3b17-e524-4e38-b37e-b743ba766344
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094684590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.1094684590
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.2161250042
Short name T493
Test name
Test status
Simulation time 28770964 ps
CPU time 0.55 seconds
Started Aug 05 05:50:00 PM PDT 24
Finished Aug 05 05:50:01 PM PDT 24
Peak memory 182748 kb
Host smart-27292c2f-9ca1-461a-b388-d5625aa4b50d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161250042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.2161250042
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.2806535070
Short name T478
Test name
Test status
Simulation time 27611729 ps
CPU time 0.52 seconds
Started Aug 05 05:49:40 PM PDT 24
Finished Aug 05 05:49:41 PM PDT 24
Peak memory 182740 kb
Host smart-02eb893b-4034-46b7-80af-f7795b1edd15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806535070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.2806535070
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.121146129
Short name T522
Test name
Test status
Simulation time 81964257 ps
CPU time 0.57 seconds
Started Aug 05 05:49:41 PM PDT 24
Finished Aug 05 05:49:42 PM PDT 24
Peak memory 182792 kb
Host smart-f84186e0-cb55-4ae6-b885-bc19e34d8891
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121146129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.121146129
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2181087367
Short name T484
Test name
Test status
Simulation time 17807007 ps
CPU time 0.61 seconds
Started Aug 05 05:50:03 PM PDT 24
Finished Aug 05 05:50:03 PM PDT 24
Peak memory 182768 kb
Host smart-39f5bffd-cda1-45d6-92d7-7473eeeae015
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181087367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.2181087367
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.712842694
Short name T466
Test name
Test status
Simulation time 25489370 ps
CPU time 0.54 seconds
Started Aug 05 05:49:51 PM PDT 24
Finished Aug 05 05:49:52 PM PDT 24
Peak memory 182728 kb
Host smart-d1d919cf-75ae-4ea2-900b-fddc7a4d9a48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712842694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.712842694
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.4109376063
Short name T502
Test name
Test status
Simulation time 17515626 ps
CPU time 0.58 seconds
Started Aug 05 05:49:45 PM PDT 24
Finished Aug 05 05:49:46 PM PDT 24
Peak memory 182796 kb
Host smart-4a066225-e6f0-4237-b59d-cee5ab0c09d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109376063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.4109376063
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.3841422929
Short name T523
Test name
Test status
Simulation time 57036836 ps
CPU time 0.63 seconds
Started Aug 05 05:49:50 PM PDT 24
Finished Aug 05 05:49:50 PM PDT 24
Peak memory 193600 kb
Host smart-066419ec-7470-4bec-a31c-47395d6ed5e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841422929 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.3841422929
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.2551389770
Short name T483
Test name
Test status
Simulation time 19591745 ps
CPU time 0.54 seconds
Started Aug 05 05:49:50 PM PDT 24
Finished Aug 05 05:49:51 PM PDT 24
Peak memory 182700 kb
Host smart-120f30df-3954-4310-aba3-174f4daf5544
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551389770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.2551389770
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.2466795653
Short name T520
Test name
Test status
Simulation time 14375925 ps
CPU time 0.54 seconds
Started Aug 05 05:49:51 PM PDT 24
Finished Aug 05 05:49:51 PM PDT 24
Peak memory 182760 kb
Host smart-61b60cf3-028e-439a-b65d-ddbb327275f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466795653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.2466795653
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.3244271017
Short name T48
Test name
Test status
Simulation time 105570333 ps
CPU time 0.58 seconds
Started Aug 05 05:49:29 PM PDT 24
Finished Aug 05 05:49:29 PM PDT 24
Peak memory 191480 kb
Host smart-f6529f26-3160-4d2c-b6d2-8e67d0d5e073
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244271017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.3244271017
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.3718632458
Short name T536
Test name
Test status
Simulation time 346677624 ps
CPU time 1.36 seconds
Started Aug 05 05:49:38 PM PDT 24
Finished Aug 05 05:49:40 PM PDT 24
Peak memory 197704 kb
Host smart-767a4ea2-995c-47a9-bfa5-7b8892125ce9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718632458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.3718632458
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.647777686
Short name T481
Test name
Test status
Simulation time 424057333 ps
CPU time 1.04 seconds
Started Aug 05 05:49:42 PM PDT 24
Finished Aug 05 05:49:43 PM PDT 24
Peak memory 195164 kb
Host smart-e31cfeec-20ae-4432-b8be-cde219d256e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647777686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_int
g_err.647777686
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3262071431
Short name T504
Test name
Test status
Simulation time 33873427 ps
CPU time 0.76 seconds
Started Aug 05 05:49:25 PM PDT 24
Finished Aug 05 05:49:31 PM PDT 24
Peak memory 195488 kb
Host smart-8b636d91-e12f-4112-b8a6-fa6ed2921eaa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262071431 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.3262071431
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.610213432
Short name T556
Test name
Test status
Simulation time 13115892 ps
CPU time 0.58 seconds
Started Aug 05 05:49:53 PM PDT 24
Finished Aug 05 05:49:54 PM PDT 24
Peak memory 182936 kb
Host smart-e30a0649-0397-492f-9478-782cafac3be6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610213432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.610213432
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.560070465
Short name T557
Test name
Test status
Simulation time 36516177 ps
CPU time 0.51 seconds
Started Aug 05 05:49:27 PM PDT 24
Finished Aug 05 05:49:28 PM PDT 24
Peak memory 182236 kb
Host smart-8984621f-b8fc-466d-bce4-d1a1e5ab7e85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560070465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.560070465
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.1605144574
Short name T492
Test name
Test status
Simulation time 42467102 ps
CPU time 0.83 seconds
Started Aug 05 05:49:38 PM PDT 24
Finished Aug 05 05:49:39 PM PDT 24
Peak memory 192048 kb
Host smart-4ac58bd0-917a-4d86-a0bf-b872ea4e852c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605144574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.1605144574
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.3621454515
Short name T52
Test name
Test status
Simulation time 423012747 ps
CPU time 2.09 seconds
Started Aug 05 05:49:26 PM PDT 24
Finished Aug 05 05:49:29 PM PDT 24
Peak memory 197664 kb
Host smart-8e9825b6-5ec8-4419-9708-c509a314dc97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621454515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.3621454515
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.3415474134
Short name T521
Test name
Test status
Simulation time 494701745 ps
CPU time 1.35 seconds
Started Aug 05 05:49:32 PM PDT 24
Finished Aug 05 05:49:33 PM PDT 24
Peak memory 195680 kb
Host smart-75bf28b8-878f-452f-ba1d-6b60e873853e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415474134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.3415474134
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.336522767
Short name T47
Test name
Test status
Simulation time 26292053 ps
CPU time 0.77 seconds
Started Aug 05 05:49:42 PM PDT 24
Finished Aug 05 05:49:43 PM PDT 24
Peak memory 195836 kb
Host smart-7088a7d5-80e1-45fa-ad7e-8c6e36c1fc12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336522767 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.336522767
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.2345034405
Short name T51
Test name
Test status
Simulation time 26048143 ps
CPU time 0.55 seconds
Started Aug 05 05:49:46 PM PDT 24
Finished Aug 05 05:49:46 PM PDT 24
Peak memory 182948 kb
Host smart-6a0f6592-7c5d-41ce-bcb8-f69c42135913
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345034405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.2345034405
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.2396289677
Short name T458
Test name
Test status
Simulation time 13822732 ps
CPU time 0.5 seconds
Started Aug 05 05:49:42 PM PDT 24
Finished Aug 05 05:49:43 PM PDT 24
Peak memory 182232 kb
Host smart-0eac52df-ba72-4855-a636-a3de8ffba757
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396289677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.2396289677
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.380184534
Short name T579
Test name
Test status
Simulation time 66401592 ps
CPU time 0.73 seconds
Started Aug 05 05:49:41 PM PDT 24
Finished Aug 05 05:49:42 PM PDT 24
Peak memory 193632 kb
Host smart-09f50bd4-567a-4585-a901-3a73a6cb95af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380184534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_tim
er_same_csr_outstanding.380184534
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.3642096493
Short name T461
Test name
Test status
Simulation time 443710419 ps
CPU time 1.86 seconds
Started Aug 05 05:49:44 PM PDT 24
Finished Aug 05 05:49:46 PM PDT 24
Peak memory 197668 kb
Host smart-ed729028-6c91-49e4-b9b9-a8ad47f7156d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642096493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.3642096493
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.3175512394
Short name T499
Test name
Test status
Simulation time 612664252 ps
CPU time 0.81 seconds
Started Aug 05 05:49:40 PM PDT 24
Finished Aug 05 05:49:41 PM PDT 24
Peak memory 183212 kb
Host smart-be100ff8-c670-4970-84bf-97f6fb9b8bf4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175512394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.3175512394
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3171569975
Short name T487
Test name
Test status
Simulation time 18682211 ps
CPU time 0.87 seconds
Started Aug 05 05:49:23 PM PDT 24
Finished Aug 05 05:49:24 PM PDT 24
Peak memory 197348 kb
Host smart-2e9bfea7-30cf-4828-b02c-f7b976063eb3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171569975 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.3171569975
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.553271974
Short name T569
Test name
Test status
Simulation time 39960000 ps
CPU time 0.56 seconds
Started Aug 05 05:49:25 PM PDT 24
Finished Aug 05 05:49:26 PM PDT 24
Peak memory 182688 kb
Host smart-f24f8bc2-90ef-4e5c-952a-de2d185a61bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553271974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.553271974
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.530651882
Short name T537
Test name
Test status
Simulation time 13094831 ps
CPU time 0.55 seconds
Started Aug 05 05:49:37 PM PDT 24
Finished Aug 05 05:49:38 PM PDT 24
Peak memory 182792 kb
Host smart-f6c71f0e-030d-49b1-9a54-21796eab07fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530651882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.530651882
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.524354179
Short name T539
Test name
Test status
Simulation time 18517387 ps
CPU time 0.83 seconds
Started Aug 05 05:49:41 PM PDT 24
Finished Aug 05 05:49:41 PM PDT 24
Peak memory 193540 kb
Host smart-110b7c85-34e3-4b8e-ad24-09bb4357f316
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524354179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_tim
er_same_csr_outstanding.524354179
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.2681033443
Short name T528
Test name
Test status
Simulation time 323904433 ps
CPU time 1.82 seconds
Started Aug 05 05:49:27 PM PDT 24
Finished Aug 05 05:49:29 PM PDT 24
Peak memory 191296 kb
Host smart-25bf86fe-5313-4a18-8b25-ba978a82834a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681033443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.2681033443
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.2501285795
Short name T535
Test name
Test status
Simulation time 635952779 ps
CPU time 1.25 seconds
Started Aug 05 05:49:36 PM PDT 24
Finished Aug 05 05:49:37 PM PDT 24
Peak memory 195256 kb
Host smart-40739dd0-1b9c-4944-a1c9-7c02d3a1db96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501285795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.2501285795
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.2816904622
Short name T581
Test name
Test status
Simulation time 53161846 ps
CPU time 0.94 seconds
Started Aug 05 05:49:38 PM PDT 24
Finished Aug 05 05:49:39 PM PDT 24
Peak memory 197580 kb
Host smart-0d4745c1-dfc7-4795-b79a-a2c046a7233a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816904622 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.2816904622
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.1842888810
Short name T465
Test name
Test status
Simulation time 27706419 ps
CPU time 0.61 seconds
Started Aug 05 05:49:39 PM PDT 24
Finished Aug 05 05:49:39 PM PDT 24
Peak memory 192168 kb
Host smart-54a22d7d-8b55-44fc-a8bd-0dcfe25186da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842888810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.1842888810
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.99658543
Short name T455
Test name
Test status
Simulation time 14043390 ps
CPU time 0.56 seconds
Started Aug 05 05:49:40 PM PDT 24
Finished Aug 05 05:49:41 PM PDT 24
Peak memory 182768 kb
Host smart-0692d187-65b0-4438-a147-c527c01e4067
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99658543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.99658543
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.781062600
Short name T496
Test name
Test status
Simulation time 38181945 ps
CPU time 0.63 seconds
Started Aug 05 05:49:47 PM PDT 24
Finished Aug 05 05:49:47 PM PDT 24
Peak memory 192388 kb
Host smart-a5ad2503-b4c0-4104-a819-958c099635f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781062600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_tim
er_same_csr_outstanding.781062600
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.2307690254
Short name T543
Test name
Test status
Simulation time 118862422 ps
CPU time 2.28 seconds
Started Aug 05 05:49:45 PM PDT 24
Finished Aug 05 05:49:48 PM PDT 24
Peak memory 197696 kb
Host smart-443e5188-e7e1-472b-936b-aae87451a169
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307690254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.2307690254
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.2776300932
Short name T462
Test name
Test status
Simulation time 109312508 ps
CPU time 1.42 seconds
Started Aug 05 05:49:28 PM PDT 24
Finished Aug 05 05:49:29 PM PDT 24
Peak memory 195816 kb
Host smart-dca40622-d15a-4c69-a6cf-a57fad550539
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776300932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.2776300932
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.1886731746
Short name T382
Test name
Test status
Simulation time 199157180834 ps
CPU time 270.01 seconds
Started Aug 05 05:53:34 PM PDT 24
Finished Aug 05 05:58:04 PM PDT 24
Peak memory 183460 kb
Host smart-ee5f9296-e96d-4c97-9d15-2feeaaadb437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886731746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.1886731746
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.181046568
Short name T123
Test name
Test status
Simulation time 1425194051096 ps
CPU time 996.5 seconds
Started Aug 05 05:53:32 PM PDT 24
Finished Aug 05 06:10:09 PM PDT 24
Peak memory 191656 kb
Host smart-1b09746b-fce5-4fef-b1ee-004b50a73de6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181046568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.181046568
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all_with_rand_reset.1672485538
Short name T41
Test name
Test status
Simulation time 89187519789 ps
CPU time 576.27 seconds
Started Aug 05 05:53:34 PM PDT 24
Finished Aug 05 06:03:10 PM PDT 24
Peak memory 209232 kb
Host smart-a7e5a41e-8719-4d8c-aeb8-682b41a83552
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672485538 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all_with_rand_reset.1672485538
Directory /workspace/0.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.2444385373
Short name T360
Test name
Test status
Simulation time 9534748043 ps
CPU time 15.22 seconds
Started Aug 05 05:53:40 PM PDT 24
Finished Aug 05 05:53:55 PM PDT 24
Peak memory 183448 kb
Host smart-d262f599-304e-435a-97eb-8090a1a81b16
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444385373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.2444385373
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.2878030469
Short name T369
Test name
Test status
Simulation time 148761081777 ps
CPU time 56.35 seconds
Started Aug 05 05:53:36 PM PDT 24
Finished Aug 05 05:54:32 PM PDT 24
Peak memory 183444 kb
Host smart-899fc305-3ca0-4f2e-a215-cd098372c56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878030469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.2878030469
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.2671360353
Short name T283
Test name
Test status
Simulation time 61142788547 ps
CPU time 97.63 seconds
Started Aug 05 05:53:38 PM PDT 24
Finished Aug 05 05:55:16 PM PDT 24
Peak memory 191656 kb
Host smart-be571aa4-64b2-46ce-b41d-f9e4da51cd3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671360353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.2671360353
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.2358206054
Short name T18
Test name
Test status
Simulation time 56227092 ps
CPU time 0.72 seconds
Started Aug 05 05:53:45 PM PDT 24
Finished Aug 05 05:53:45 PM PDT 24
Peak memory 213992 kb
Host smart-bd610e14-47b2-430d-99bf-3f55ce5c3396
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358206054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.2358206054
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/10.rv_timer_random.49873383
Short name T217
Test name
Test status
Simulation time 17170074499 ps
CPU time 24.17 seconds
Started Aug 05 05:54:05 PM PDT 24
Finished Aug 05 05:54:29 PM PDT 24
Peak memory 191672 kb
Host smart-62b313d2-660a-4902-9441-8a5f6b06f3ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49873383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.49873383
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.3369896266
Short name T270
Test name
Test status
Simulation time 971394163340 ps
CPU time 305.09 seconds
Started Aug 05 05:57:43 PM PDT 24
Finished Aug 05 06:02:49 PM PDT 24
Peak memory 191576 kb
Host smart-466e377b-2eab-4833-a23f-92d05fe5f504
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369896266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.3369896266
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.1341045886
Short name T7
Test name
Test status
Simulation time 2663986967 ps
CPU time 20.07 seconds
Started Aug 05 05:57:43 PM PDT 24
Finished Aug 05 05:58:03 PM PDT 24
Peak memory 183472 kb
Host smart-ed07c18b-5afe-4d0b-b046-b11543ae22ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341045886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.1341045886
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.1839863192
Short name T63
Test name
Test status
Simulation time 91487877621 ps
CPU time 33.71 seconds
Started Aug 05 05:57:45 PM PDT 24
Finished Aug 05 05:58:19 PM PDT 24
Peak memory 183288 kb
Host smart-4112bd49-3235-40bd-8a14-6ee4262671ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839863192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.1839863192
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.3914087434
Short name T163
Test name
Test status
Simulation time 700130651290 ps
CPU time 449.93 seconds
Started Aug 05 05:57:45 PM PDT 24
Finished Aug 05 06:05:15 PM PDT 24
Peak memory 191608 kb
Host smart-e7369ac6-cbe8-4b4e-966f-a2a63a516604
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914087434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.3914087434
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.3019264941
Short name T326
Test name
Test status
Simulation time 177471334232 ps
CPU time 149.28 seconds
Started Aug 05 05:57:44 PM PDT 24
Finished Aug 05 06:00:13 PM PDT 24
Peak memory 183436 kb
Host smart-10e7b477-c7c4-4f90-a0d6-25d1078bad0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019264941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.3019264941
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.2694322273
Short name T301
Test name
Test status
Simulation time 54822594315 ps
CPU time 27.7 seconds
Started Aug 05 05:57:45 PM PDT 24
Finished Aug 05 05:58:13 PM PDT 24
Peak memory 183460 kb
Host smart-dbfe410f-e5e4-4782-96e2-bf99f65077dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694322273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.2694322273
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.1929206548
Short name T407
Test name
Test status
Simulation time 317604237201 ps
CPU time 113.12 seconds
Started Aug 05 05:54:06 PM PDT 24
Finished Aug 05 05:55:59 PM PDT 24
Peak memory 183472 kb
Host smart-07e59f49-867d-4ec0-ba0d-2fa3b9ae6f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929206548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.1929206548
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.1316314694
Short name T61
Test name
Test status
Simulation time 186331183 ps
CPU time 1.08 seconds
Started Aug 05 05:54:13 PM PDT 24
Finished Aug 05 05:54:14 PM PDT 24
Peak memory 193052 kb
Host smart-5448e534-d85c-4f49-9072-bf043c3a26c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316314694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.1316314694
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.2291880120
Short name T55
Test name
Test status
Simulation time 285110307678 ps
CPU time 521.97 seconds
Started Aug 05 05:54:09 PM PDT 24
Finished Aug 05 06:02:51 PM PDT 24
Peak memory 191744 kb
Host smart-74220674-602e-4c10-b1da-2bfe804f69e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291880120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.2291880120
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/110.rv_timer_random.2061578289
Short name T334
Test name
Test status
Simulation time 226540727990 ps
CPU time 219.49 seconds
Started Aug 05 05:57:43 PM PDT 24
Finished Aug 05 06:01:22 PM PDT 24
Peak memory 183476 kb
Host smart-b79b9996-2128-45aa-a401-f61e6e328753
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061578289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.2061578289
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.818091431
Short name T258
Test name
Test status
Simulation time 219140864844 ps
CPU time 1319.74 seconds
Started Aug 05 05:57:50 PM PDT 24
Finished Aug 05 06:19:50 PM PDT 24
Peak memory 191656 kb
Host smart-74f07299-0e31-4edf-b091-e06033a6ae13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818091431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.818091431
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.667313054
Short name T277
Test name
Test status
Simulation time 374655885224 ps
CPU time 302.73 seconds
Started Aug 05 05:57:48 PM PDT 24
Finished Aug 05 06:02:51 PM PDT 24
Peak memory 191592 kb
Host smart-10f17f6a-cc31-48e7-a9a1-d78681f7b97b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667313054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.667313054
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.2333031507
Short name T356
Test name
Test status
Simulation time 33412005978 ps
CPU time 53.65 seconds
Started Aug 05 05:57:49 PM PDT 24
Finished Aug 05 05:58:43 PM PDT 24
Peak memory 183436 kb
Host smart-b3d9c3a1-7629-45f6-8079-3ac4ee0b174d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333031507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.2333031507
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.154076078
Short name T219
Test name
Test status
Simulation time 426233815264 ps
CPU time 321.22 seconds
Started Aug 05 05:57:49 PM PDT 24
Finished Aug 05 06:03:10 PM PDT 24
Peak memory 191648 kb
Host smart-115f1d3e-9a7e-4453-ada6-4bc5a8f4b64c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154076078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.154076078
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.2693330975
Short name T342
Test name
Test status
Simulation time 74196189174 ps
CPU time 123.39 seconds
Started Aug 05 05:57:49 PM PDT 24
Finished Aug 05 05:59:53 PM PDT 24
Peak memory 191676 kb
Host smart-f28f6dbd-f74b-467f-b1e3-c041eb6f5767
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693330975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.2693330975
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.1331878875
Short name T209
Test name
Test status
Simulation time 15605615151 ps
CPU time 8.59 seconds
Started Aug 05 05:54:11 PM PDT 24
Finished Aug 05 05:54:20 PM PDT 24
Peak memory 183664 kb
Host smart-b1857dcc-3350-41c4-9e09-1b887345cd7d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331878875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.1331878875
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.2493883680
Short name T381
Test name
Test status
Simulation time 26310650036 ps
CPU time 36.69 seconds
Started Aug 05 05:54:10 PM PDT 24
Finished Aug 05 05:54:47 PM PDT 24
Peak memory 183448 kb
Host smart-f95c2855-ceec-4397-b234-8695182059e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493883680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.2493883680
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.2717935729
Short name T424
Test name
Test status
Simulation time 384301396637 ps
CPU time 455.64 seconds
Started Aug 05 05:54:09 PM PDT 24
Finished Aug 05 06:01:45 PM PDT 24
Peak memory 191656 kb
Host smart-3dfb647c-48cb-4c48-9bbd-1cd63327c99b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717935729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.2717935729
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.2552796200
Short name T416
Test name
Test status
Simulation time 462671324190 ps
CPU time 434.17 seconds
Started Aug 05 05:54:18 PM PDT 24
Finished Aug 05 06:01:32 PM PDT 24
Peak memory 191672 kb
Host smart-481f7fb6-19ba-48de-a8b4-296b02c3019d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552796200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.2552796200
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/120.rv_timer_random.2624240130
Short name T252
Test name
Test status
Simulation time 195298318440 ps
CPU time 1213.93 seconds
Started Aug 05 05:57:49 PM PDT 24
Finished Aug 05 06:18:03 PM PDT 24
Peak memory 191620 kb
Host smart-faf81c59-0377-4e7f-9fbe-82239c9103a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624240130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.2624240130
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.750211816
Short name T132
Test name
Test status
Simulation time 7842525019 ps
CPU time 7.74 seconds
Started Aug 05 05:57:56 PM PDT 24
Finished Aug 05 05:58:04 PM PDT 24
Peak memory 183488 kb
Host smart-338438cb-c7fb-40e8-a490-f30e14340b72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750211816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.750211816
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.2060577019
Short name T154
Test name
Test status
Simulation time 239109287332 ps
CPU time 602.13 seconds
Started Aug 05 05:57:54 PM PDT 24
Finished Aug 05 06:07:57 PM PDT 24
Peak memory 191660 kb
Host smart-fe62a3ed-5e40-42bd-87f7-dd88affb04cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060577019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.2060577019
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.682047918
Short name T166
Test name
Test status
Simulation time 374262953006 ps
CPU time 246.14 seconds
Started Aug 05 05:57:56 PM PDT 24
Finished Aug 05 06:02:02 PM PDT 24
Peak memory 191672 kb
Host smart-6c7b3720-ec56-471d-8a38-fdea63247813
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682047918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.682047918
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.1645953542
Short name T119
Test name
Test status
Simulation time 109920923988 ps
CPU time 62.21 seconds
Started Aug 05 05:57:56 PM PDT 24
Finished Aug 05 05:58:58 PM PDT 24
Peak memory 191632 kb
Host smart-43e244f2-7ab3-4b6d-a881-2b4beafb719a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645953542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.1645953542
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.2313211395
Short name T204
Test name
Test status
Simulation time 143642414525 ps
CPU time 108.07 seconds
Started Aug 05 05:57:56 PM PDT 24
Finished Aug 05 05:59:44 PM PDT 24
Peak memory 191664 kb
Host smart-b228b779-822e-4ac2-bfa3-034a48070588
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313211395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.2313211395
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.198406107
Short name T337
Test name
Test status
Simulation time 285690641422 ps
CPU time 245.78 seconds
Started Aug 05 05:57:54 PM PDT 24
Finished Aug 05 06:02:00 PM PDT 24
Peak memory 191652 kb
Host smart-734bd36f-2bcc-4859-a743-634c246537ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198406107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.198406107
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.282421300
Short name T274
Test name
Test status
Simulation time 68868331300 ps
CPU time 224.44 seconds
Started Aug 05 05:57:59 PM PDT 24
Finished Aug 05 06:01:44 PM PDT 24
Peak memory 191700 kb
Host smart-97003bb9-02dd-4442-ae4f-e5bfaddde46d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282421300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.282421300
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.2466356943
Short name T172
Test name
Test status
Simulation time 5065992729 ps
CPU time 5.58 seconds
Started Aug 05 05:54:16 PM PDT 24
Finished Aug 05 05:54:21 PM PDT 24
Peak memory 183444 kb
Host smart-0dc89426-be6e-4d24-84b4-381fa071ec74
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466356943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.2466356943
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.1327036152
Short name T441
Test name
Test status
Simulation time 222635835019 ps
CPU time 288.83 seconds
Started Aug 05 05:54:16 PM PDT 24
Finished Aug 05 05:59:05 PM PDT 24
Peak memory 183448 kb
Host smart-3e3a2895-a6a2-4733-b661-b1f4d87c1f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327036152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.1327036152
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.620347172
Short name T263
Test name
Test status
Simulation time 251157841458 ps
CPU time 378.78 seconds
Started Aug 05 05:54:18 PM PDT 24
Finished Aug 05 06:00:37 PM PDT 24
Peak memory 191876 kb
Host smart-37d25d97-f025-4969-b41e-e1cabad91187
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620347172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.620347172
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.3609826302
Short name T384
Test name
Test status
Simulation time 74305053 ps
CPU time 0.64 seconds
Started Aug 05 05:54:15 PM PDT 24
Finished Aug 05 05:54:16 PM PDT 24
Peak memory 183196 kb
Host smart-aa1929b5-4c7e-48bb-b007-4be34dacfc67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609826302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.3609826302
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.3642189605
Short name T406
Test name
Test status
Simulation time 899281498610 ps
CPU time 258.61 seconds
Started Aug 05 05:54:17 PM PDT 24
Finished Aug 05 05:58:36 PM PDT 24
Peak memory 191644 kb
Host smart-45579652-5d5f-45d4-8fb8-ef761a94c954
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642189605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.3642189605
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/130.rv_timer_random.765042205
Short name T160
Test name
Test status
Simulation time 807383505472 ps
CPU time 1552.16 seconds
Started Aug 05 05:58:00 PM PDT 24
Finished Aug 05 06:23:52 PM PDT 24
Peak memory 191652 kb
Host smart-65bba050-7c14-47e6-bad0-1b69af8d52e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765042205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.765042205
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.2926970350
Short name T195
Test name
Test status
Simulation time 214955961257 ps
CPU time 141.53 seconds
Started Aug 05 05:58:06 PM PDT 24
Finished Aug 05 06:00:27 PM PDT 24
Peak memory 191620 kb
Host smart-3e534532-6a63-41c8-a9f9-e00da9ee0e8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926970350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.2926970350
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.2623826055
Short name T108
Test name
Test status
Simulation time 68916454973 ps
CPU time 122.24 seconds
Started Aug 05 05:58:04 PM PDT 24
Finished Aug 05 06:00:06 PM PDT 24
Peak memory 191708 kb
Host smart-82fea37e-dcaa-4186-8ced-6ed9c3e8aa0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623826055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.2623826055
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.717823236
Short name T168
Test name
Test status
Simulation time 115599020915 ps
CPU time 198.71 seconds
Started Aug 05 05:58:05 PM PDT 24
Finished Aug 05 06:01:24 PM PDT 24
Peak memory 191872 kb
Host smart-1fb738f8-124c-4209-88d2-77d7c58cca4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717823236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.717823236
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.761559387
Short name T234
Test name
Test status
Simulation time 473026116049 ps
CPU time 249.57 seconds
Started Aug 05 05:58:06 PM PDT 24
Finished Aug 05 06:02:16 PM PDT 24
Peak memory 191592 kb
Host smart-89b7834c-bdb2-4df2-9c76-04d20d19653f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761559387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.761559387
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.2630217231
Short name T310
Test name
Test status
Simulation time 244857023792 ps
CPU time 544.13 seconds
Started Aug 05 05:58:07 PM PDT 24
Finished Aug 05 06:07:11 PM PDT 24
Peak memory 191648 kb
Host smart-40f62576-a988-40e5-809e-42c00d7adf61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630217231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.2630217231
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.1836670575
Short name T196
Test name
Test status
Simulation time 34439166508 ps
CPU time 34.35 seconds
Started Aug 05 05:54:18 PM PDT 24
Finished Aug 05 05:54:53 PM PDT 24
Peak memory 183360 kb
Host smart-ac268d48-a9df-4b7c-a2c7-02f34904f8ae
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836670575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.1836670575
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.641147094
Short name T67
Test name
Test status
Simulation time 162993361274 ps
CPU time 264.72 seconds
Started Aug 05 05:54:17 PM PDT 24
Finished Aug 05 05:58:42 PM PDT 24
Peak memory 183476 kb
Host smart-3c5b6475-58fd-482b-a88f-61c486075ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641147094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.641147094
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.966473905
Short name T306
Test name
Test status
Simulation time 35002781633 ps
CPU time 187.13 seconds
Started Aug 05 05:54:23 PM PDT 24
Finished Aug 05 05:57:30 PM PDT 24
Peak memory 195232 kb
Host smart-1a824a1d-7f43-4429-a8ce-351b48a13fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966473905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.966473905
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/140.rv_timer_random.1309808191
Short name T193
Test name
Test status
Simulation time 372103756004 ps
CPU time 729.58 seconds
Started Aug 05 05:58:06 PM PDT 24
Finished Aug 05 06:10:16 PM PDT 24
Peak memory 192728 kb
Host smart-aeea2d41-83a8-47fc-8e3a-a2859d2f3ed9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309808191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.1309808191
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.1609083876
Short name T117
Test name
Test status
Simulation time 11917110546 ps
CPU time 23.51 seconds
Started Aug 05 05:58:07 PM PDT 24
Finished Aug 05 05:58:30 PM PDT 24
Peak memory 183508 kb
Host smart-443a7b58-7cf3-4a89-b956-23c5bda95c54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609083876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.1609083876
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.2077132824
Short name T286
Test name
Test status
Simulation time 77921414806 ps
CPU time 166.25 seconds
Started Aug 05 05:58:05 PM PDT 24
Finished Aug 05 06:00:51 PM PDT 24
Peak memory 191648 kb
Host smart-0f08900e-ad3a-4b86-865b-fa44b3f28490
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077132824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.2077132824
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.3594896752
Short name T362
Test name
Test status
Simulation time 23967269386 ps
CPU time 389.76 seconds
Started Aug 05 05:58:07 PM PDT 24
Finished Aug 05 06:04:37 PM PDT 24
Peak memory 183460 kb
Host smart-3615479c-4679-4d08-9276-cf022b8530e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594896752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.3594896752
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.3911115224
Short name T442
Test name
Test status
Simulation time 9291099961 ps
CPU time 10.54 seconds
Started Aug 05 05:58:10 PM PDT 24
Finished Aug 05 05:58:21 PM PDT 24
Peak memory 183192 kb
Host smart-6a0ca4f1-8eac-4cea-84c1-abd98a4da89f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911115224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.3911115224
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.244605941
Short name T130
Test name
Test status
Simulation time 92486268204 ps
CPU time 83.24 seconds
Started Aug 05 05:58:11 PM PDT 24
Finished Aug 05 05:59:34 PM PDT 24
Peak memory 191644 kb
Host smart-bf075d43-c73c-4152-bb67-cc12361faa70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244605941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.244605941
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.1215773455
Short name T134
Test name
Test status
Simulation time 576294726222 ps
CPU time 734.03 seconds
Started Aug 05 05:58:11 PM PDT 24
Finished Aug 05 06:10:25 PM PDT 24
Peak memory 191664 kb
Host smart-2698ea4b-6587-4bd2-bf23-9fc3c5fabca6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215773455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.1215773455
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.2676018556
Short name T295
Test name
Test status
Simulation time 663657520920 ps
CPU time 334.26 seconds
Started Aug 05 05:54:24 PM PDT 24
Finished Aug 05 05:59:58 PM PDT 24
Peak memory 183416 kb
Host smart-67efb5d2-4a5a-413d-9b7e-1d11bbfd505f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676018556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.2676018556
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.2699691850
Short name T65
Test name
Test status
Simulation time 277839467296 ps
CPU time 227.31 seconds
Started Aug 05 05:54:23 PM PDT 24
Finished Aug 05 05:58:11 PM PDT 24
Peak memory 183428 kb
Host smart-c559c30a-133b-4b5e-8eac-e2c97133b0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699691850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.2699691850
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.1361480158
Short name T432
Test name
Test status
Simulation time 14758079734 ps
CPU time 9.02 seconds
Started Aug 05 05:54:22 PM PDT 24
Finished Aug 05 05:54:31 PM PDT 24
Peak memory 194320 kb
Host smart-9815b1ef-167e-4568-bffe-26d18f395328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361480158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.1361480158
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/152.rv_timer_random.3076789081
Short name T224
Test name
Test status
Simulation time 38642376231 ps
CPU time 41.31 seconds
Started Aug 05 05:58:12 PM PDT 24
Finished Aug 05 05:58:54 PM PDT 24
Peak memory 183464 kb
Host smart-0bb95d08-5e9d-419c-bdc5-3b69eb9afdf0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076789081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.3076789081
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.3666170831
Short name T282
Test name
Test status
Simulation time 200084384751 ps
CPU time 592.89 seconds
Started Aug 05 05:58:11 PM PDT 24
Finished Aug 05 06:08:04 PM PDT 24
Peak memory 191684 kb
Host smart-b9252f08-c1f9-4d37-9c14-18fa11fef426
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666170831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.3666170831
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.2597112579
Short name T92
Test name
Test status
Simulation time 114085532562 ps
CPU time 358.59 seconds
Started Aug 05 05:58:10 PM PDT 24
Finished Aug 05 06:04:09 PM PDT 24
Peak memory 191648 kb
Host smart-f542fe50-77e4-42a9-b4fa-f342d9c81056
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597112579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.2597112579
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.3707622190
Short name T433
Test name
Test status
Simulation time 82873175961 ps
CPU time 39.81 seconds
Started Aug 05 05:58:15 PM PDT 24
Finished Aug 05 05:58:55 PM PDT 24
Peak memory 183460 kb
Host smart-ccce27f8-a05e-4493-9224-4155dbf0ab0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707622190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.3707622190
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.855292247
Short name T448
Test name
Test status
Simulation time 784244968916 ps
CPU time 403.23 seconds
Started Aug 05 05:54:27 PM PDT 24
Finished Aug 05 06:01:10 PM PDT 24
Peak memory 183420 kb
Host smart-be921da3-a851-4415-9737-ff72c8d86bb8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855292247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.rv_timer_cfg_update_on_fly.855292247
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.1165791323
Short name T403
Test name
Test status
Simulation time 639751923133 ps
CPU time 265.22 seconds
Started Aug 05 05:54:27 PM PDT 24
Finished Aug 05 05:58:52 PM PDT 24
Peak memory 183464 kb
Host smart-8c793df3-7952-4710-8898-11ded1d7d94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165791323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.1165791323
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.2387930546
Short name T371
Test name
Test status
Simulation time 113627749 ps
CPU time 0.72 seconds
Started Aug 05 05:54:27 PM PDT 24
Finished Aug 05 05:54:27 PM PDT 24
Peak memory 183220 kb
Host smart-49524b95-c480-441a-9651-693a905c7c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387930546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.2387930546
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.103416540
Short name T28
Test name
Test status
Simulation time 64383274 ps
CPU time 0.55 seconds
Started Aug 05 05:54:35 PM PDT 24
Finished Aug 05 05:54:36 PM PDT 24
Peak memory 183200 kb
Host smart-0b719cf6-04e1-42c8-9f80-e351859d1fd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103416540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all.
103416540
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/160.rv_timer_random.1380808359
Short name T316
Test name
Test status
Simulation time 260147647254 ps
CPU time 698.67 seconds
Started Aug 05 05:58:17 PM PDT 24
Finished Aug 05 06:09:56 PM PDT 24
Peak memory 191656 kb
Host smart-a765ff14-2852-4fc3-900b-289999d9283e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380808359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.1380808359
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.3616389093
Short name T200
Test name
Test status
Simulation time 149592894365 ps
CPU time 553.06 seconds
Started Aug 05 05:58:14 PM PDT 24
Finished Aug 05 06:07:28 PM PDT 24
Peak memory 191660 kb
Host smart-aecd2f7f-2d1a-45d1-8ac3-70779a80b1b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616389093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.3616389093
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.764835511
Short name T133
Test name
Test status
Simulation time 227255110547 ps
CPU time 170.28 seconds
Started Aug 05 05:58:20 PM PDT 24
Finished Aug 05 06:01:10 PM PDT 24
Peak memory 191700 kb
Host smart-d79ac9d5-e063-49b1-9370-372dca48e1ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764835511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.764835511
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.2206225124
Short name T170
Test name
Test status
Simulation time 711267008623 ps
CPU time 1120.84 seconds
Started Aug 05 05:58:21 PM PDT 24
Finished Aug 05 06:17:02 PM PDT 24
Peak memory 191676 kb
Host smart-311e9c9c-1c8f-4f93-82e7-e8e349d03082
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206225124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.2206225124
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.1037930986
Short name T75
Test name
Test status
Simulation time 70781747605 ps
CPU time 117.63 seconds
Started Aug 05 05:58:21 PM PDT 24
Finished Aug 05 06:00:19 PM PDT 24
Peak memory 191628 kb
Host smart-a6ec0f0d-4e1f-4416-8d0b-1e1fff09b58f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037930986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.1037930986
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.3732527545
Short name T308
Test name
Test status
Simulation time 484886138469 ps
CPU time 271.15 seconds
Started Aug 05 05:58:20 PM PDT 24
Finished Aug 05 06:02:51 PM PDT 24
Peak memory 191620 kb
Host smart-bc4e25e6-c1a6-4b4b-a28d-24f74b13a2d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732527545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.3732527545
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.3488202804
Short name T198
Test name
Test status
Simulation time 2011436556366 ps
CPU time 1115.37 seconds
Started Aug 05 05:54:31 PM PDT 24
Finished Aug 05 06:13:07 PM PDT 24
Peak memory 183492 kb
Host smart-8b1cb56d-bd84-4d64-b771-d5281ee66abd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488202804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.3488202804
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.2370195466
Short name T88
Test name
Test status
Simulation time 575929360484 ps
CPU time 217.03 seconds
Started Aug 05 05:54:32 PM PDT 24
Finished Aug 05 05:58:09 PM PDT 24
Peak memory 183676 kb
Host smart-6f04868f-19ea-4c5a-a897-f1b6d65ff9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370195466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.2370195466
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.4252746893
Short name T440
Test name
Test status
Simulation time 92754093438 ps
CPU time 125.49 seconds
Started Aug 05 05:54:32 PM PDT 24
Finished Aug 05 05:56:38 PM PDT 24
Peak memory 183480 kb
Host smart-8cae3187-5be3-4f89-af13-fa34f7724dac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252746893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.4252746893
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/171.rv_timer_random.4176652732
Short name T128
Test name
Test status
Simulation time 92094926621 ps
CPU time 162.63 seconds
Started Aug 05 05:58:26 PM PDT 24
Finished Aug 05 06:01:09 PM PDT 24
Peak memory 191640 kb
Host smart-18da1fd9-2578-4e25-a15a-aa6f899738db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176652732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.4176652732
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.1830458017
Short name T9
Test name
Test status
Simulation time 194833513707 ps
CPU time 1826.84 seconds
Started Aug 05 05:58:25 PM PDT 24
Finished Aug 05 06:28:52 PM PDT 24
Peak memory 191584 kb
Host smart-b459c1ed-5100-4f23-9f7c-cfb7b31b83e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830458017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.1830458017
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.3167376488
Short name T111
Test name
Test status
Simulation time 59648902580 ps
CPU time 296.93 seconds
Started Aug 05 05:58:25 PM PDT 24
Finished Aug 05 06:03:23 PM PDT 24
Peak memory 191680 kb
Host smart-e43d4158-6c38-44a9-923e-d85d846afc68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167376488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.3167376488
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.3710832562
Short name T350
Test name
Test status
Simulation time 39935542736 ps
CPU time 80.32 seconds
Started Aug 05 05:58:34 PM PDT 24
Finished Aug 05 05:59:55 PM PDT 24
Peak memory 183448 kb
Host smart-3d80ed67-e039-407c-b981-742d7e5838f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710832562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.3710832562
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.3918590988
Short name T188
Test name
Test status
Simulation time 77665045687 ps
CPU time 67.53 seconds
Started Aug 05 05:58:30 PM PDT 24
Finished Aug 05 05:59:37 PM PDT 24
Peak memory 183472 kb
Host smart-6c7a8ff9-4e67-44b7-80dd-922fc1413c88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918590988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.3918590988
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.520626368
Short name T359
Test name
Test status
Simulation time 228845782564 ps
CPU time 370.89 seconds
Started Aug 05 05:58:28 PM PDT 24
Finished Aug 05 06:04:39 PM PDT 24
Peak memory 191592 kb
Host smart-1e6b60db-e51c-43fa-b070-8f0aa484c997
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520626368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.520626368
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.3042867459
Short name T423
Test name
Test status
Simulation time 34350414187 ps
CPU time 48.55 seconds
Started Aug 05 05:58:34 PM PDT 24
Finished Aug 05 05:59:23 PM PDT 24
Peak memory 183456 kb
Host smart-4a5ec66b-e94c-48b7-8525-8ec6c3f0d6b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042867459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.3042867459
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.2268376152
Short name T402
Test name
Test status
Simulation time 137632099316 ps
CPU time 219.91 seconds
Started Aug 05 05:54:37 PM PDT 24
Finished Aug 05 05:58:17 PM PDT 24
Peak memory 183444 kb
Host smart-a0a6d07d-b9de-4eb3-b751-aa557b6d47fb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268376152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.2268376152
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.3650055397
Short name T377
Test name
Test status
Simulation time 786664638975 ps
CPU time 287.1 seconds
Started Aug 05 05:54:37 PM PDT 24
Finished Aug 05 05:59:24 PM PDT 24
Peak memory 183392 kb
Host smart-0b954887-00f6-4e7e-bd13-39bb5c02317a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650055397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.3650055397
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.1386108457
Short name T444
Test name
Test status
Simulation time 58714588124 ps
CPU time 191.73 seconds
Started Aug 05 05:54:38 PM PDT 24
Finished Aug 05 05:57:50 PM PDT 24
Peak memory 191676 kb
Host smart-c59275f9-f750-4cb0-9882-50b23e32613c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386108457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.1386108457
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.746809817
Short name T21
Test name
Test status
Simulation time 335848692187 ps
CPU time 436.76 seconds
Started Aug 05 05:54:37 PM PDT 24
Finished Aug 05 06:01:55 PM PDT 24
Peak memory 191672 kb
Host smart-e2ec24d2-99b7-48bf-9014-7801f11e823c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746809817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all.
746809817
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/180.rv_timer_random.3957900344
Short name T265
Test name
Test status
Simulation time 898972722362 ps
CPU time 858.69 seconds
Started Aug 05 05:58:34 PM PDT 24
Finished Aug 05 06:12:53 PM PDT 24
Peak memory 191656 kb
Host smart-a0f16699-26c5-45f6-b05a-a93a5adc0115
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957900344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.3957900344
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.957907508
Short name T445
Test name
Test status
Simulation time 1662880131082 ps
CPU time 459 seconds
Started Aug 05 05:58:32 PM PDT 24
Finished Aug 05 06:06:11 PM PDT 24
Peak memory 191620 kb
Host smart-9049df4e-88aa-4c5f-b942-b5dfd614d494
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957907508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.957907508
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.1862747031
Short name T248
Test name
Test status
Simulation time 49341657762 ps
CPU time 70.28 seconds
Started Aug 05 05:58:39 PM PDT 24
Finished Aug 05 05:59:49 PM PDT 24
Peak memory 191644 kb
Host smart-28dbb548-da81-4eaa-a7b5-b25c83b99943
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862747031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.1862747031
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.3605882754
Short name T319
Test name
Test status
Simulation time 140356852564 ps
CPU time 407.25 seconds
Started Aug 05 05:58:39 PM PDT 24
Finished Aug 05 06:05:26 PM PDT 24
Peak memory 191580 kb
Host smart-262108e9-f9dd-447d-9d6a-a64d38ada0e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605882754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.3605882754
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.3555280150
Short name T141
Test name
Test status
Simulation time 1205612300029 ps
CPU time 908.67 seconds
Started Aug 05 05:58:34 PM PDT 24
Finished Aug 05 06:13:43 PM PDT 24
Peak memory 191644 kb
Host smart-7424b606-cdac-4297-ad4a-22e123368e3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555280150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.3555280150
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.4077833454
Short name T325
Test name
Test status
Simulation time 34139123427 ps
CPU time 57.31 seconds
Started Aug 05 05:58:39 PM PDT 24
Finished Aug 05 05:59:36 PM PDT 24
Peak memory 191680 kb
Host smart-1e0b1bc2-65d8-4a2c-bcfe-c46902d18ea3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077833454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.4077833454
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.1274988982
Short name T124
Test name
Test status
Simulation time 100701344653 ps
CPU time 91.27 seconds
Started Aug 05 05:58:42 PM PDT 24
Finished Aug 05 06:00:13 PM PDT 24
Peak memory 191680 kb
Host smart-3a4c7ae8-88ae-4219-b678-566335aef34b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274988982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.1274988982
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.2732315956
Short name T153
Test name
Test status
Simulation time 60583644796 ps
CPU time 442.5 seconds
Started Aug 05 05:58:40 PM PDT 24
Finished Aug 05 06:06:03 PM PDT 24
Peak memory 191644 kb
Host smart-b11b17ea-85ae-4158-a1c1-ba02b223275c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732315956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.2732315956
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.711424335
Short name T323
Test name
Test status
Simulation time 37872817649 ps
CPU time 29.95 seconds
Started Aug 05 05:58:38 PM PDT 24
Finished Aug 05 05:59:08 PM PDT 24
Peak memory 191692 kb
Host smart-54b0155e-0dbb-46a5-8701-7963aed4524b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711424335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.711424335
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.4032664486
Short name T177
Test name
Test status
Simulation time 646376667701 ps
CPU time 388.76 seconds
Started Aug 05 05:58:40 PM PDT 24
Finished Aug 05 06:05:09 PM PDT 24
Peak memory 194120 kb
Host smart-e0ac37b1-357e-46a5-8cc0-dd4e3c6a01fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032664486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.4032664486
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.2536309015
Short name T288
Test name
Test status
Simulation time 441866843851 ps
CPU time 641.97 seconds
Started Aug 05 05:54:43 PM PDT 24
Finished Aug 05 06:05:25 PM PDT 24
Peak memory 183444 kb
Host smart-b119a025-2dae-4a11-8fda-a578e627ed5f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536309015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.2536309015
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.1456484302
Short name T66
Test name
Test status
Simulation time 338185493013 ps
CPU time 90.31 seconds
Started Aug 05 05:54:44 PM PDT 24
Finished Aug 05 05:56:14 PM PDT 24
Peak memory 183452 kb
Host smart-a7c14ca5-bd33-4d0a-acf3-b415d4c9b203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456484302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.1456484302
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.2775375923
Short name T333
Test name
Test status
Simulation time 53094185000 ps
CPU time 62.04 seconds
Started Aug 05 05:54:44 PM PDT 24
Finished Aug 05 05:55:46 PM PDT 24
Peak memory 191656 kb
Host smart-b0349621-8ea8-40a6-9275-d2e746ac68a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775375923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.2775375923
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.2818924669
Short name T285
Test name
Test status
Simulation time 78134515515 ps
CPU time 168.02 seconds
Started Aug 05 05:54:43 PM PDT 24
Finished Aug 05 05:57:31 PM PDT 24
Peak memory 195444 kb
Host smart-05e5b5fa-5e95-4769-8b95-b4a056236353
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818924669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.2818924669
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/190.rv_timer_random.2480501357
Short name T266
Test name
Test status
Simulation time 41121814168 ps
CPU time 58.52 seconds
Started Aug 05 05:58:42 PM PDT 24
Finished Aug 05 05:59:40 PM PDT 24
Peak memory 183480 kb
Host smart-088dba8a-33e7-41aa-abcd-4ae61e4dc5d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480501357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.2480501357
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.171267091
Short name T292
Test name
Test status
Simulation time 316320146922 ps
CPU time 289.31 seconds
Started Aug 05 05:58:51 PM PDT 24
Finished Aug 05 06:03:41 PM PDT 24
Peak memory 191644 kb
Host smart-8fb68e5b-3423-4d5e-8d15-0eb1bb459a25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171267091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.171267091
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.2636466973
Short name T215
Test name
Test status
Simulation time 613293939840 ps
CPU time 385.84 seconds
Started Aug 05 05:58:47 PM PDT 24
Finished Aug 05 06:05:13 PM PDT 24
Peak memory 191660 kb
Host smart-acfa5581-8a61-4413-9430-93f12fe8832b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636466973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.2636466973
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.3355852535
Short name T339
Test name
Test status
Simulation time 527779663974 ps
CPU time 271.67 seconds
Started Aug 05 05:58:46 PM PDT 24
Finished Aug 05 06:03:18 PM PDT 24
Peak memory 191640 kb
Host smart-ffdd91bb-261d-438f-a426-96b39e35e52c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355852535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.3355852535
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.3698142778
Short name T25
Test name
Test status
Simulation time 230974533182 ps
CPU time 181.94 seconds
Started Aug 05 05:58:46 PM PDT 24
Finished Aug 05 06:01:48 PM PDT 24
Peak memory 194336 kb
Host smart-6cc65f6f-b4aa-46fd-953e-2bb9f217c91b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698142778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.3698142778
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.1766198928
Short name T180
Test name
Test status
Simulation time 229946312383 ps
CPU time 1683.64 seconds
Started Aug 05 05:58:46 PM PDT 24
Finished Aug 05 06:26:49 PM PDT 24
Peak memory 191584 kb
Host smart-8be0c8a2-1840-41e5-b5ad-4939f1162b22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766198928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.1766198928
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.1592786623
Short name T230
Test name
Test status
Simulation time 194714689461 ps
CPU time 297.49 seconds
Started Aug 05 05:53:43 PM PDT 24
Finished Aug 05 05:58:41 PM PDT 24
Peak memory 183420 kb
Host smart-c7620513-9554-45e7-a6a4-d100c2e01965
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592786623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.1592786623
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.2848223262
Short name T401
Test name
Test status
Simulation time 269344772738 ps
CPU time 102.24 seconds
Started Aug 05 05:53:43 PM PDT 24
Finished Aug 05 05:55:25 PM PDT 24
Peak memory 183480 kb
Host smart-f086624e-7127-4fb7-932e-b79b820f9b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848223262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.2848223262
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.2612272942
Short name T264
Test name
Test status
Simulation time 117068696511 ps
CPU time 389.52 seconds
Started Aug 05 05:53:42 PM PDT 24
Finished Aug 05 06:00:12 PM PDT 24
Peak memory 194124 kb
Host smart-fe908332-9738-49ef-bf25-5e1af63053b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612272942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.2612272942
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.1827089131
Short name T443
Test name
Test status
Simulation time 198857132 ps
CPU time 0.63 seconds
Started Aug 05 05:53:44 PM PDT 24
Finished Aug 05 05:53:45 PM PDT 24
Peak memory 183192 kb
Host smart-e2089a55-9771-401d-9cfc-70681f24905d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827089131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.1827089131
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.1140296466
Short name T20
Test name
Test status
Simulation time 52302050 ps
CPU time 0.79 seconds
Started Aug 05 05:53:42 PM PDT 24
Finished Aug 05 05:53:43 PM PDT 24
Peak memory 213952 kb
Host smart-86aab947-3dbb-413b-bf8e-ecc403577b28
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140296466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.1140296466
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all_with_rand_reset.1728317149
Short name T449
Test name
Test status
Simulation time 49342534486 ps
CPU time 388.04 seconds
Started Aug 05 05:53:43 PM PDT 24
Finished Aug 05 06:00:11 PM PDT 24
Peak memory 206404 kb
Host smart-59c853f7-7786-49b8-a6c5-b70c088f6748
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728317149 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all_with_rand_reset.1728317149
Directory /workspace/2.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.1718183544
Short name T426
Test name
Test status
Simulation time 212695995623 ps
CPU time 353.6 seconds
Started Aug 05 05:54:49 PM PDT 24
Finished Aug 05 06:00:43 PM PDT 24
Peak memory 183452 kb
Host smart-7bef18e6-e844-4d9b-80cd-070a6fb1395e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718183544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.1718183544
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.2574733155
Short name T390
Test name
Test status
Simulation time 512321527595 ps
CPU time 201.73 seconds
Started Aug 05 05:55:24 PM PDT 24
Finished Aug 05 05:58:46 PM PDT 24
Peak memory 183468 kb
Host smart-757a6d75-faea-4214-b5f7-17afe725ca2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574733155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.2574733155
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.3030717266
Short name T129
Test name
Test status
Simulation time 278035627541 ps
CPU time 260.05 seconds
Started Aug 05 05:54:49 PM PDT 24
Finished Aug 05 05:59:09 PM PDT 24
Peak memory 191652 kb
Host smart-82848f46-eec7-47bc-be94-12418e7bb2ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030717266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.3030717266
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.614322208
Short name T446
Test name
Test status
Simulation time 162020672149 ps
CPU time 448.92 seconds
Started Aug 05 05:54:48 PM PDT 24
Finished Aug 05 06:02:17 PM PDT 24
Peak memory 191640 kb
Host smart-e5a613fd-348b-4bd8-b8a1-ea17c42feea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614322208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.614322208
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.2221759969
Short name T430
Test name
Test status
Simulation time 21605311 ps
CPU time 0.56 seconds
Started Aug 05 05:54:47 PM PDT 24
Finished Aug 05 05:54:48 PM PDT 24
Peak memory 183196 kb
Host smart-7a0f86d5-dee1-4882-b5e0-ebf800a02c68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221759969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.2221759969
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.393596437
Short name T257
Test name
Test status
Simulation time 5977180177 ps
CPU time 5.59 seconds
Started Aug 05 05:54:48 PM PDT 24
Finished Aug 05 05:54:54 PM PDT 24
Peak memory 183340 kb
Host smart-a8fc3279-5548-4209-96e9-4da40a83b05d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393596437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.rv_timer_cfg_update_on_fly.393596437
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.2049644167
Short name T363
Test name
Test status
Simulation time 66518188244 ps
CPU time 53.97 seconds
Started Aug 05 05:54:49 PM PDT 24
Finished Aug 05 05:55:44 PM PDT 24
Peak memory 183392 kb
Host smart-f3cd7956-16d4-4449-8532-10a35071221b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049644167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.2049644167
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.3882096444
Short name T136
Test name
Test status
Simulation time 236248011787 ps
CPU time 417.97 seconds
Started Aug 05 05:54:48 PM PDT 24
Finished Aug 05 06:01:47 PM PDT 24
Peak memory 191648 kb
Host smart-035e5e7b-ddd8-4a41-b8ba-b869564184c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882096444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.3882096444
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.388301838
Short name T409
Test name
Test status
Simulation time 36478227881 ps
CPU time 21.01 seconds
Started Aug 05 05:54:47 PM PDT 24
Finished Aug 05 05:55:08 PM PDT 24
Peak memory 183452 kb
Host smart-2563c928-af27-4825-91d3-191737e8f30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388301838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.388301838
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.2272082353
Short name T29
Test name
Test status
Simulation time 463807476438 ps
CPU time 171.09 seconds
Started Aug 05 05:54:47 PM PDT 24
Finished Aug 05 05:57:38 PM PDT 24
Peak memory 183472 kb
Host smart-e1a2862a-91fe-480e-98c3-2957fd194bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272082353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.2272082353
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.1682154053
Short name T222
Test name
Test status
Simulation time 7139376042 ps
CPU time 11.63 seconds
Started Aug 05 05:54:48 PM PDT 24
Finished Aug 05 05:55:00 PM PDT 24
Peak memory 183436 kb
Host smart-16ea0290-84b5-44d7-bbbc-1ff0a8f12245
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682154053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.1682154053
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.2436389034
Short name T330
Test name
Test status
Simulation time 65757265106 ps
CPU time 51.1 seconds
Started Aug 05 05:54:48 PM PDT 24
Finished Aug 05 05:55:39 PM PDT 24
Peak memory 191664 kb
Host smart-3addc8dd-bf65-4cb7-88ff-9b22a540acf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436389034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.2436389034
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.3366894040
Short name T197
Test name
Test status
Simulation time 583888559843 ps
CPU time 480.56 seconds
Started Aug 05 05:54:50 PM PDT 24
Finished Aug 05 06:02:50 PM PDT 24
Peak memory 191652 kb
Host smart-1ae3a899-e4fe-400d-853d-33d873c2400d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366894040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.3366894040
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all_with_rand_reset.2516241231
Short name T15
Test name
Test status
Simulation time 177968956641 ps
CPU time 343.57 seconds
Started Aug 05 05:54:49 PM PDT 24
Finished Aug 05 06:00:33 PM PDT 24
Peak memory 206356 kb
Host smart-9eca28c1-a3ef-41f4-8f15-741c57a4c23f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516241231 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all_with_rand_reset.2516241231
Directory /workspace/22.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.3807529812
Short name T394
Test name
Test status
Simulation time 446758625079 ps
CPU time 157.19 seconds
Started Aug 05 05:54:53 PM PDT 24
Finished Aug 05 05:57:31 PM PDT 24
Peak memory 183676 kb
Host smart-741a71dc-b4ce-4157-b908-63bfaa39e746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807529812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.3807529812
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.2373750501
Short name T5
Test name
Test status
Simulation time 280045999425 ps
CPU time 311.03 seconds
Started Aug 05 05:55:00 PM PDT 24
Finished Aug 05 06:00:11 PM PDT 24
Peak memory 191708 kb
Host smart-6d0810a9-bba7-472a-ba8d-932c531ba8c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373750501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.2373750501
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.3738926109
Short name T398
Test name
Test status
Simulation time 14647413486 ps
CPU time 22.18 seconds
Started Aug 05 05:55:00 PM PDT 24
Finished Aug 05 05:55:23 PM PDT 24
Peak memory 183500 kb
Host smart-19539e2b-ca48-4013-9ba1-d30bb4eaa6c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738926109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.3738926109
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.2407605260
Short name T45
Test name
Test status
Simulation time 81134552371 ps
CPU time 88.5 seconds
Started Aug 05 05:55:00 PM PDT 24
Finished Aug 05 05:56:29 PM PDT 24
Peak memory 191680 kb
Host smart-9f6c7013-baf7-42f5-a2db-53d08a112289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407605260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.2407605260
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.346631319
Short name T298
Test name
Test status
Simulation time 365243734437 ps
CPU time 628.08 seconds
Started Aug 05 05:55:03 PM PDT 24
Finished Aug 05 06:05:32 PM PDT 24
Peak memory 183424 kb
Host smart-dfbb4562-7935-496f-8843-117f592db9b1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346631319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.rv_timer_cfg_update_on_fly.346631319
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.409582787
Short name T93
Test name
Test status
Simulation time 50306383747 ps
CPU time 76.9 seconds
Started Aug 05 05:54:59 PM PDT 24
Finished Aug 05 05:56:16 PM PDT 24
Peak memory 183440 kb
Host smart-debfee31-7c7a-49e2-bacb-7ab544f2c855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409582787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.409582787
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.1982491483
Short name T12
Test name
Test status
Simulation time 16003434392 ps
CPU time 25.7 seconds
Started Aug 05 05:55:05 PM PDT 24
Finished Aug 05 05:55:31 PM PDT 24
Peak memory 191612 kb
Host smart-b2afdac1-8001-4196-9ced-a546c24a8987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982491483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.1982491483
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all_with_rand_reset.1398144780
Short name T37
Test name
Test status
Simulation time 31444969207 ps
CPU time 232.08 seconds
Started Aug 05 05:55:02 PM PDT 24
Finished Aug 05 05:58:54 PM PDT 24
Peak memory 198212 kb
Host smart-2b41e738-74bf-4390-989a-7d7d80bcce94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398144780 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all_with_rand_reset.1398144780
Directory /workspace/25.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rv_timer_random.450604716
Short name T143
Test name
Test status
Simulation time 793066007552 ps
CPU time 361.07 seconds
Started Aug 05 05:55:04 PM PDT 24
Finished Aug 05 06:01:05 PM PDT 24
Peak memory 191620 kb
Host smart-ed5cc2ce-d5fc-41a4-993e-86f0bf46e3c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450604716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.450604716
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.2901425524
Short name T414
Test name
Test status
Simulation time 961157952 ps
CPU time 2.04 seconds
Started Aug 05 05:55:07 PM PDT 24
Finished Aug 05 05:55:09 PM PDT 24
Peak memory 183228 kb
Host smart-0d6f54ff-6ae8-40ef-a6e7-d39069259fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901425524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.2901425524
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.2255672619
Short name T91
Test name
Test status
Simulation time 2663370141191 ps
CPU time 959.25 seconds
Started Aug 05 05:55:12 PM PDT 24
Finished Aug 05 06:11:12 PM PDT 24
Peak memory 191704 kb
Host smart-195a59d8-6b8b-4b17-bc48-0ed3382a270d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255672619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.2255672619
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all_with_rand_reset.392571148
Short name T42
Test name
Test status
Simulation time 69836462318 ps
CPU time 423.14 seconds
Started Aug 05 05:55:05 PM PDT 24
Finished Aug 05 06:02:09 PM PDT 24
Peak memory 206880 kb
Host smart-3f840193-4348-49df-a9a7-4c9c4deec6e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392571148 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all_with_rand_reset.392571148
Directory /workspace/26.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.1354130387
Short name T235
Test name
Test status
Simulation time 631011447646 ps
CPU time 186.89 seconds
Started Aug 05 05:55:09 PM PDT 24
Finished Aug 05 05:58:16 PM PDT 24
Peak memory 183492 kb
Host smart-0d4f03ab-c78f-43e5-98b8-38c160e88d4d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354130387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.1354130387
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.3419009784
Short name T27
Test name
Test status
Simulation time 474206416396 ps
CPU time 184.91 seconds
Started Aug 05 05:55:08 PM PDT 24
Finished Aug 05 05:58:13 PM PDT 24
Peak memory 183428 kb
Host smart-848888c7-c14f-4275-83a2-56b35ebe4fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419009784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.3419009784
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.200276314
Short name T294
Test name
Test status
Simulation time 24768068748 ps
CPU time 42.58 seconds
Started Aug 05 05:55:10 PM PDT 24
Finished Aug 05 05:55:53 PM PDT 24
Peak memory 183492 kb
Host smart-5f1a067b-926c-4e99-958b-62bb80a383b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200276314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.200276314
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.775890345
Short name T410
Test name
Test status
Simulation time 10847763016 ps
CPU time 10.41 seconds
Started Aug 05 05:55:09 PM PDT 24
Finished Aug 05 05:55:19 PM PDT 24
Peak memory 191652 kb
Host smart-30f93be5-2f58-4d2d-94fa-b2bc6c85bade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775890345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.775890345
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all_with_rand_reset.1404407239
Short name T39
Test name
Test status
Simulation time 291541844419 ps
CPU time 826.16 seconds
Started Aug 05 05:55:21 PM PDT 24
Finished Aug 05 06:09:07 PM PDT 24
Peak memory 209908 kb
Host smart-49455dee-6a68-4601-83e0-4c65360df268
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404407239 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all_with_rand_reset.1404407239
Directory /workspace/27.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.2189554733
Short name T137
Test name
Test status
Simulation time 32104488187 ps
CPU time 56.77 seconds
Started Aug 05 05:55:21 PM PDT 24
Finished Aug 05 05:56:18 PM PDT 24
Peak memory 183444 kb
Host smart-918c4b25-b3fc-4730-823d-e7a2fbcf67c6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189554733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.2189554733
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.494190729
Short name T405
Test name
Test status
Simulation time 333623651189 ps
CPU time 135.1 seconds
Started Aug 05 05:55:23 PM PDT 24
Finished Aug 05 05:57:38 PM PDT 24
Peak memory 183472 kb
Host smart-9d95379c-0f8a-411c-afdd-f53654a730c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494190729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.494190729
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.324016919
Short name T312
Test name
Test status
Simulation time 32090002744 ps
CPU time 348.45 seconds
Started Aug 05 05:55:23 PM PDT 24
Finished Aug 05 06:01:12 PM PDT 24
Peak memory 183428 kb
Host smart-9732d7f7-c8fa-4c1b-b42d-fa14f0cbe2fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324016919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.324016919
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.2158039437
Short name T223
Test name
Test status
Simulation time 289175515735 ps
CPU time 135.74 seconds
Started Aug 05 05:55:22 PM PDT 24
Finished Aug 05 05:57:38 PM PDT 24
Peak memory 191728 kb
Host smart-894543c6-7306-430f-a4ca-654ef60929e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158039437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.2158039437
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.52466437
Short name T175
Test name
Test status
Simulation time 870619093983 ps
CPU time 195.45 seconds
Started Aug 05 05:55:22 PM PDT 24
Finished Aug 05 05:58:37 PM PDT 24
Peak memory 191636 kb
Host smart-f09631ef-0695-4a67-98b8-7401fb710117
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52466437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all.52466437
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.1083981145
Short name T191
Test name
Test status
Simulation time 813174442114 ps
CPU time 276.99 seconds
Started Aug 05 05:55:23 PM PDT 24
Finished Aug 05 06:00:00 PM PDT 24
Peak memory 183440 kb
Host smart-495ec6b0-73f1-4e7c-aebd-8ee45f37220c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083981145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.1083981145
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.1226789052
Short name T417
Test name
Test status
Simulation time 413158311854 ps
CPU time 276.41 seconds
Started Aug 05 05:55:23 PM PDT 24
Finished Aug 05 06:00:00 PM PDT 24
Peak memory 183464 kb
Host smart-d8df7c38-0f0b-4942-bc25-56aa7de648d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226789052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.1226789052
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.831150401
Short name T338
Test name
Test status
Simulation time 185583439521 ps
CPU time 1432.22 seconds
Started Aug 05 05:55:22 PM PDT 24
Finished Aug 05 06:19:15 PM PDT 24
Peak memory 191688 kb
Host smart-e3774418-b528-4499-b66d-af1d74453f88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831150401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.831150401
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.1565298888
Short name T293
Test name
Test status
Simulation time 107343510722 ps
CPU time 49.41 seconds
Started Aug 05 05:55:22 PM PDT 24
Finished Aug 05 05:56:12 PM PDT 24
Peak memory 183500 kb
Host smart-94f768f0-f7b6-4978-9af0-a42a47549ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565298888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.1565298888
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.1415228011
Short name T368
Test name
Test status
Simulation time 265305360702 ps
CPU time 213.93 seconds
Started Aug 05 05:53:44 PM PDT 24
Finished Aug 05 05:57:18 PM PDT 24
Peak memory 183484 kb
Host smart-46c409cc-33bb-4489-b011-d5b82685ec12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415228011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.1415228011
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.82105431
Short name T439
Test name
Test status
Simulation time 189555833251 ps
CPU time 95.71 seconds
Started Aug 05 05:53:44 PM PDT 24
Finished Aug 05 05:55:19 PM PDT 24
Peak memory 183448 kb
Host smart-441c342d-0cf9-46f2-999e-2d292c61dcbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82105431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.82105431
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.1108871537
Short name T184
Test name
Test status
Simulation time 575191537156 ps
CPU time 1125.44 seconds
Started Aug 05 05:53:51 PM PDT 24
Finished Aug 05 06:12:37 PM PDT 24
Peak memory 191708 kb
Host smart-d7c00bae-8ae3-488e-b4f2-15e1673ba6c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108871537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.1108871537
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.1486423911
Short name T16
Test name
Test status
Simulation time 128419462 ps
CPU time 0.74 seconds
Started Aug 05 05:53:49 PM PDT 24
Finished Aug 05 05:53:50 PM PDT 24
Peak memory 213956 kb
Host smart-32aaac7d-ce20-4e8d-8df9-4e85f32427e5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486423911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.1486423911
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.2943341651
Short name T331
Test name
Test status
Simulation time 2131337386632 ps
CPU time 902.24 seconds
Started Aug 05 05:53:51 PM PDT 24
Finished Aug 05 06:08:53 PM PDT 24
Peak memory 191668 kb
Host smart-8cb10212-3543-416e-8925-28cdec2e8bff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943341651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
2943341651
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.3975413819
Short name T281
Test name
Test status
Simulation time 1729185003218 ps
CPU time 641.73 seconds
Started Aug 05 05:55:26 PM PDT 24
Finished Aug 05 06:06:08 PM PDT 24
Peak memory 183452 kb
Host smart-6fa3578c-2a50-46a9-be7d-e0d7a60a2766
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975413819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.3975413819
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.1661120147
Short name T372
Test name
Test status
Simulation time 3424715535 ps
CPU time 5.42 seconds
Started Aug 05 05:55:25 PM PDT 24
Finished Aug 05 05:55:31 PM PDT 24
Peak memory 183268 kb
Host smart-37de7cdc-1f64-41a0-a543-6a94965a1d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661120147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.1661120147
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.1721611272
Short name T383
Test name
Test status
Simulation time 158262274 ps
CPU time 0.58 seconds
Started Aug 05 05:55:24 PM PDT 24
Finished Aug 05 05:55:25 PM PDT 24
Peak memory 183228 kb
Host smart-c96d57a1-d1d7-4341-a644-74533256bb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721611272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.1721611272
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.2101704795
Short name T11
Test name
Test status
Simulation time 1197997794299 ps
CPU time 3494.15 seconds
Started Aug 05 05:55:29 PM PDT 24
Finished Aug 05 06:53:43 PM PDT 24
Peak memory 191620 kb
Host smart-de086c6c-36bc-4f73-9ce1-bb4ea04c4697
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101704795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.2101704795
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.4064171140
Short name T228
Test name
Test status
Simulation time 172236894966 ps
CPU time 83.2 seconds
Started Aug 05 05:55:30 PM PDT 24
Finished Aug 05 05:56:54 PM PDT 24
Peak memory 183464 kb
Host smart-65c2070e-1c38-47f8-ae1e-c6c81495ee73
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064171140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.4064171140
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.428507623
Short name T386
Test name
Test status
Simulation time 158341226586 ps
CPU time 193.49 seconds
Started Aug 05 05:55:29 PM PDT 24
Finished Aug 05 05:58:43 PM PDT 24
Peak memory 183392 kb
Host smart-1e10f7e6-7037-4742-80bf-7cd2d9429491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428507623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.428507623
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.2281549787
Short name T321
Test name
Test status
Simulation time 122467426479 ps
CPU time 43.85 seconds
Started Aug 05 05:55:31 PM PDT 24
Finished Aug 05 05:56:15 PM PDT 24
Peak memory 191692 kb
Host smart-a6cd9d0e-b231-4975-98fa-3ab08e73b33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281549787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.2281549787
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.1504144322
Short name T232
Test name
Test status
Simulation time 119358259494 ps
CPU time 191.15 seconds
Started Aug 05 05:55:35 PM PDT 24
Finished Aug 05 05:58:46 PM PDT 24
Peak memory 195444 kb
Host smart-48c62657-6889-4416-a7c1-894b600f72f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504144322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.1504144322
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.774321299
Short name T262
Test name
Test status
Simulation time 123979728496 ps
CPU time 190.18 seconds
Started Aug 05 05:55:35 PM PDT 24
Finished Aug 05 05:58:46 PM PDT 24
Peak memory 183468 kb
Host smart-53dd0e59-487f-4cce-aada-946e696de1d7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774321299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.rv_timer_cfg_update_on_fly.774321299
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.2163091105
Short name T400
Test name
Test status
Simulation time 763325502885 ps
CPU time 237.63 seconds
Started Aug 05 05:55:36 PM PDT 24
Finished Aug 05 05:59:34 PM PDT 24
Peak memory 183428 kb
Host smart-7556b759-a753-4252-b206-a1369d4dc30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163091105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.2163091105
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.3658027909
Short name T127
Test name
Test status
Simulation time 11366850454 ps
CPU time 18.76 seconds
Started Aug 05 05:55:39 PM PDT 24
Finished Aug 05 05:55:58 PM PDT 24
Peak memory 195340 kb
Host smart-043e0d85-f045-4c7f-9ffe-268421bd15cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658027909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.3658027909
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.3843946019
Short name T149
Test name
Test status
Simulation time 407070307709 ps
CPU time 203.18 seconds
Started Aug 05 05:55:40 PM PDT 24
Finished Aug 05 05:59:04 PM PDT 24
Peak memory 183456 kb
Host smart-cc7a6743-82c1-4ab2-a740-27c01dd14eae
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843946019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.3843946019
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.1565965622
Short name T425
Test name
Test status
Simulation time 198556970016 ps
CPU time 158.16 seconds
Started Aug 05 05:55:41 PM PDT 24
Finished Aug 05 05:58:19 PM PDT 24
Peak memory 183452 kb
Host smart-606b3e65-e26f-466f-83d7-6121611e2872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565965622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.1565965622
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.1331219124
Short name T212
Test name
Test status
Simulation time 104822987529 ps
CPU time 463.58 seconds
Started Aug 05 05:55:40 PM PDT 24
Finished Aug 05 06:03:24 PM PDT 24
Peak memory 191656 kb
Host smart-09f8268d-3e75-4c77-8cff-dde8fd7ead3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331219124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.1331219124
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.147620143
Short name T411
Test name
Test status
Simulation time 13579599 ps
CPU time 0.57 seconds
Started Aug 05 05:55:40 PM PDT 24
Finished Aug 05 05:55:41 PM PDT 24
Peak memory 183252 kb
Host smart-aecaed15-542a-4f1e-bad7-828f289ba9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147620143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.147620143
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.1547917362
Short name T380
Test name
Test status
Simulation time 515408711793 ps
CPU time 747.04 seconds
Started Aug 05 05:55:42 PM PDT 24
Finished Aug 05 06:08:09 PM PDT 24
Peak memory 191692 kb
Host smart-eda436d1-06d2-4fd2-af81-1137e3655f98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547917362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.1547917362
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.2309150720
Short name T352
Test name
Test status
Simulation time 185096761936 ps
CPU time 97.32 seconds
Started Aug 05 05:55:45 PM PDT 24
Finished Aug 05 05:57:22 PM PDT 24
Peak memory 183448 kb
Host smart-16d4722a-f5ce-45a9-9777-37ce717f6bda
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309150720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.2309150720
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.4114603138
Short name T385
Test name
Test status
Simulation time 86962395625 ps
CPU time 68.27 seconds
Started Aug 05 05:55:41 PM PDT 24
Finished Aug 05 05:56:49 PM PDT 24
Peak memory 183448 kb
Host smart-ce546eba-5403-4585-a241-6ba7a811e939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114603138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.4114603138
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.929181614
Short name T408
Test name
Test status
Simulation time 47127881 ps
CPU time 0.59 seconds
Started Aug 05 05:55:46 PM PDT 24
Finished Aug 05 05:55:46 PM PDT 24
Peak memory 183220 kb
Host smart-cd1033b2-2911-4f34-927b-3ca99ba5fed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929181614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.929181614
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.320360921
Short name T422
Test name
Test status
Simulation time 239997800077 ps
CPU time 92.9 seconds
Started Aug 05 05:55:53 PM PDT 24
Finished Aug 05 05:57:26 PM PDT 24
Peak memory 195148 kb
Host smart-d0396106-0736-45e5-97d9-20e35379490a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320360921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all.
320360921
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.1604491369
Short name T187
Test name
Test status
Simulation time 227379769989 ps
CPU time 350.39 seconds
Started Aug 05 05:55:52 PM PDT 24
Finished Aug 05 06:01:43 PM PDT 24
Peak memory 183360 kb
Host smart-3670f314-46f4-48bb-a897-c02db48c8af9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604491369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.1604491369
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.1726483862
Short name T60
Test name
Test status
Simulation time 76580952040 ps
CPU time 68.4 seconds
Started Aug 05 05:55:52 PM PDT 24
Finished Aug 05 05:57:01 PM PDT 24
Peak memory 183452 kb
Host smart-9c4ee44b-11c3-4e84-bb9a-ba6e7cf05a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726483862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.1726483862
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.1953529299
Short name T242
Test name
Test status
Simulation time 162534108606 ps
CPU time 201.39 seconds
Started Aug 05 05:55:52 PM PDT 24
Finished Aug 05 05:59:13 PM PDT 24
Peak memory 195548 kb
Host smart-ed92070c-d14b-4add-bd2a-dbffe2f221c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953529299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.1953529299
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.2497569796
Short name T436
Test name
Test status
Simulation time 103694283 ps
CPU time 0.72 seconds
Started Aug 05 05:55:52 PM PDT 24
Finished Aug 05 05:55:53 PM PDT 24
Peak memory 183244 kb
Host smart-d6a9b151-1d40-49e2-92f3-372184a0b4eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497569796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.2497569796
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.3557084624
Short name T167
Test name
Test status
Simulation time 27172407389 ps
CPU time 43.4 seconds
Started Aug 05 05:55:57 PM PDT 24
Finished Aug 05 05:56:40 PM PDT 24
Peak memory 183424 kb
Host smart-7c9fa1ff-a489-481d-a2a8-3b2ee0bd3411
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557084624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.3557084624
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.740187667
Short name T399
Test name
Test status
Simulation time 190028500290 ps
CPU time 83.84 seconds
Started Aug 05 05:55:57 PM PDT 24
Finished Aug 05 05:57:21 PM PDT 24
Peak memory 183464 kb
Host smart-5ee6e11a-e782-4d3f-82f9-473196f0590b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740187667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.740187667
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.4109139381
Short name T370
Test name
Test status
Simulation time 11256293588 ps
CPU time 10.24 seconds
Started Aug 05 05:55:58 PM PDT 24
Finished Aug 05 05:56:09 PM PDT 24
Peak memory 194916 kb
Host smart-0ca3e12d-1fa2-46ee-9d2e-fc688b966221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109139381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.4109139381
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.469320189
Short name T365
Test name
Test status
Simulation time 276884630 ps
CPU time 0.58 seconds
Started Aug 05 05:56:03 PM PDT 24
Finished Aug 05 05:56:04 PM PDT 24
Peak memory 183188 kb
Host smart-3667e167-eaca-4b41-84c6-d2ed1044b39f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469320189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all.
469320189
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.3993862616
Short name T354
Test name
Test status
Simulation time 200176392767 ps
CPU time 72.41 seconds
Started Aug 05 05:56:01 PM PDT 24
Finished Aug 05 05:57:14 PM PDT 24
Peak memory 183456 kb
Host smart-6da579d4-f5ee-42e8-b10d-5ec4cffa0db9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993862616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.3993862616
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.1315741931
Short name T391
Test name
Test status
Simulation time 137357484540 ps
CPU time 188.63 seconds
Started Aug 05 05:56:03 PM PDT 24
Finished Aug 05 05:59:12 PM PDT 24
Peak memory 183472 kb
Host smart-2c170f33-c0f1-4217-9e84-40894cc51767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315741931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.1315741931
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.2954744212
Short name T178
Test name
Test status
Simulation time 117421467296 ps
CPU time 365.95 seconds
Started Aug 05 05:56:02 PM PDT 24
Finished Aug 05 06:02:08 PM PDT 24
Peak memory 191648 kb
Host smart-919db2c8-0feb-4c3f-bbfe-9de8f7e7c9a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954744212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.2954744212
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.2037886409
Short name T379
Test name
Test status
Simulation time 63101839 ps
CPU time 0.93 seconds
Started Aug 05 05:56:03 PM PDT 24
Finished Aug 05 05:56:04 PM PDT 24
Peak memory 183220 kb
Host smart-e8324d7f-49b3-42e5-bc5d-d2bdb03e3b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037886409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.2037886409
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.4280356049
Short name T434
Test name
Test status
Simulation time 5207568494426 ps
CPU time 975.56 seconds
Started Aug 05 05:56:09 PM PDT 24
Finished Aug 05 06:12:25 PM PDT 24
Peak memory 191648 kb
Host smart-a250c95a-8530-48a9-9a3c-6d4247cde51e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280356049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.4280356049
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.1467401272
Short name T347
Test name
Test status
Simulation time 11122149194 ps
CPU time 20.33 seconds
Started Aug 05 05:56:07 PM PDT 24
Finished Aug 05 05:56:27 PM PDT 24
Peak memory 183504 kb
Host smart-885204da-261e-4be8-991d-a75edadddde7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467401272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.1467401272
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.3317684926
Short name T374
Test name
Test status
Simulation time 291749435154 ps
CPU time 105.25 seconds
Started Aug 05 05:56:08 PM PDT 24
Finished Aug 05 05:57:53 PM PDT 24
Peak memory 183400 kb
Host smart-e1adf687-886b-4ccf-b400-e7e595b8f226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317684926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.3317684926
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.2460013238
Short name T376
Test name
Test status
Simulation time 53214906394 ps
CPU time 71.56 seconds
Started Aug 05 05:56:08 PM PDT 24
Finished Aug 05 05:57:19 PM PDT 24
Peak memory 183444 kb
Host smart-83d24332-38ce-416a-b381-bf1e0d7cdb06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460013238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.2460013238
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.3776924805
Short name T313
Test name
Test status
Simulation time 338517749297 ps
CPU time 486.46 seconds
Started Aug 05 05:56:13 PM PDT 24
Finished Aug 05 06:04:19 PM PDT 24
Peak memory 183444 kb
Host smart-921d6042-922c-4b7e-bb26-bd78c6ede160
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776924805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.3776924805
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.3058509072
Short name T378
Test name
Test status
Simulation time 360282832151 ps
CPU time 151.9 seconds
Started Aug 05 05:56:08 PM PDT 24
Finished Aug 05 05:58:40 PM PDT 24
Peak memory 183496 kb
Host smart-47069c96-c9b1-4321-8f65-2070e3f7ca01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058509072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.3058509072
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.113694213
Short name T240
Test name
Test status
Simulation time 33644004709 ps
CPU time 48.26 seconds
Started Aug 05 05:56:13 PM PDT 24
Finished Aug 05 05:57:02 PM PDT 24
Peak memory 195212 kb
Host smart-c72b01d8-0e83-48d5-8ef0-b1c8929ea6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113694213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.113694213
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.3618516988
Short name T241
Test name
Test status
Simulation time 97523201812 ps
CPU time 581.5 seconds
Started Aug 05 05:56:15 PM PDT 24
Finished Aug 05 06:05:56 PM PDT 24
Peak memory 195380 kb
Host smart-b556c53a-6376-4ccc-a1a5-17432bb63435
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618516988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.3618516988
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all_with_rand_reset.3657720700
Short name T46
Test name
Test status
Simulation time 78627741194 ps
CPU time 311.32 seconds
Started Aug 05 05:56:14 PM PDT 24
Finished Aug 05 06:01:25 PM PDT 24
Peak memory 198204 kb
Host smart-072eb059-b44d-4078-b0f0-d3aeeff0c86c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657720700 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all_with_rand_reset.3657720700
Directory /workspace/39.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.2681507161
Short name T269
Test name
Test status
Simulation time 200228448417 ps
CPU time 183.36 seconds
Started Aug 05 05:53:48 PM PDT 24
Finished Aug 05 05:56:51 PM PDT 24
Peak memory 183412 kb
Host smart-35a70ed8-e193-4a0b-950f-c92b72fd96f2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681507161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.2681507161
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.851048736
Short name T2
Test name
Test status
Simulation time 51206907433 ps
CPU time 77.26 seconds
Started Aug 05 05:53:51 PM PDT 24
Finished Aug 05 05:55:08 PM PDT 24
Peak memory 183456 kb
Host smart-74ccf9e0-b537-4e21-a3a8-3025da004200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851048736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.851048736
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.3422900728
Short name T428
Test name
Test status
Simulation time 278287569360 ps
CPU time 127.24 seconds
Started Aug 05 05:53:49 PM PDT 24
Finished Aug 05 05:55:56 PM PDT 24
Peak memory 191664 kb
Host smart-fe0a77ec-b1b4-429e-983f-4a2122fd2db5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422900728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.3422900728
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.3212705042
Short name T236
Test name
Test status
Simulation time 48303892454 ps
CPU time 77.58 seconds
Started Aug 05 05:53:49 PM PDT 24
Finished Aug 05 05:55:06 PM PDT 24
Peak memory 193904 kb
Host smart-544d21a8-c684-430d-ba63-ad58ed5af8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212705042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.3212705042
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.1327596971
Short name T19
Test name
Test status
Simulation time 216052258 ps
CPU time 1.05 seconds
Started Aug 05 05:53:49 PM PDT 24
Finished Aug 05 05:53:50 PM PDT 24
Peak memory 215164 kb
Host smart-18044199-5f9e-417f-b9d8-28fd8166a365
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327596971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.1327596971
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all_with_rand_reset.4186859290
Short name T437
Test name
Test status
Simulation time 27294866213 ps
CPU time 284.52 seconds
Started Aug 05 05:53:48 PM PDT 24
Finished Aug 05 05:58:32 PM PDT 24
Peak memory 206428 kb
Host smart-e35a4fa5-280f-40b8-819b-2353fce86a76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186859290 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all_with_rand_reset.4186859290
Directory /workspace/4.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.1835065249
Short name T152
Test name
Test status
Simulation time 446709619640 ps
CPU time 239.41 seconds
Started Aug 05 05:56:13 PM PDT 24
Finished Aug 05 06:00:12 PM PDT 24
Peak memory 183432 kb
Host smart-3432151b-c3d9-463b-8d63-dcf1f03dfc13
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835065249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.1835065249
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.2482515570
Short name T375
Test name
Test status
Simulation time 89813053957 ps
CPU time 138.36 seconds
Started Aug 05 05:56:14 PM PDT 24
Finished Aug 05 05:58:32 PM PDT 24
Peak memory 183464 kb
Host smart-5d618b84-6825-4273-bfd0-8765a720a191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482515570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.2482515570
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.1151066801
Short name T421
Test name
Test status
Simulation time 79550120967 ps
CPU time 149.67 seconds
Started Aug 05 05:56:14 PM PDT 24
Finished Aug 05 05:58:44 PM PDT 24
Peak memory 183500 kb
Host smart-46826be4-11d3-4912-b812-57a15a8b9bbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151066801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.1151066801
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.166502544
Short name T162
Test name
Test status
Simulation time 156015953153 ps
CPU time 192.66 seconds
Started Aug 05 05:56:18 PM PDT 24
Finished Aug 05 05:59:31 PM PDT 24
Peak memory 191608 kb
Host smart-ae546ff9-50ef-4098-8748-b6049329da88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166502544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.166502544
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.1389800421
Short name T203
Test name
Test status
Simulation time 349871716323 ps
CPU time 1031.06 seconds
Started Aug 05 05:56:19 PM PDT 24
Finished Aug 05 06:13:30 PM PDT 24
Peak memory 191648 kb
Host smart-1453af9f-0e5e-4246-9978-05bf68046276
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389800421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.1389800421
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.3555645307
Short name T6
Test name
Test status
Simulation time 368337270659 ps
CPU time 340.11 seconds
Started Aug 05 05:56:24 PM PDT 24
Finished Aug 05 06:02:04 PM PDT 24
Peak memory 183436 kb
Host smart-90e2e485-9889-4b0b-9a81-47f30fe700c4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555645307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.3555645307
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.1146447723
Short name T412
Test name
Test status
Simulation time 71483118089 ps
CPU time 110.41 seconds
Started Aug 05 05:56:22 PM PDT 24
Finished Aug 05 05:58:13 PM PDT 24
Peak memory 183472 kb
Host smart-f9b3e375-9a79-448e-8388-30404cc2df81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146447723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.1146447723
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.656736503
Short name T22
Test name
Test status
Simulation time 328559948154 ps
CPU time 61.9 seconds
Started Aug 05 05:56:22 PM PDT 24
Finished Aug 05 05:57:24 PM PDT 24
Peak memory 183452 kb
Host smart-880483e9-0032-425c-9bfe-da7729a6d625
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656736503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.656736503
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.1638858666
Short name T320
Test name
Test status
Simulation time 38261873062 ps
CPU time 23.96 seconds
Started Aug 05 05:56:24 PM PDT 24
Finished Aug 05 05:56:48 PM PDT 24
Peak memory 183464 kb
Host smart-d2e7e5d3-33d5-4805-9124-7ea3edab4d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638858666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.1638858666
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.3796082626
Short name T94
Test name
Test status
Simulation time 179817078592 ps
CPU time 302.83 seconds
Started Aug 05 05:56:28 PM PDT 24
Finished Aug 05 06:01:31 PM PDT 24
Peak memory 191644 kb
Host smart-4bff890b-e23a-45c2-8576-098efd5854ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796082626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.3796082626
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.1123947367
Short name T183
Test name
Test status
Simulation time 5754255245 ps
CPU time 10.5 seconds
Started Aug 05 05:56:29 PM PDT 24
Finished Aug 05 05:56:40 PM PDT 24
Peak memory 183424 kb
Host smart-2d60ed9b-4885-4978-8ff8-9aa9358a1a4c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123947367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.1123947367
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.2229028687
Short name T387
Test name
Test status
Simulation time 478145979683 ps
CPU time 202.51 seconds
Started Aug 05 05:56:28 PM PDT 24
Finished Aug 05 05:59:50 PM PDT 24
Peak memory 183464 kb
Host smart-d65d57bb-6953-412b-9046-43e8130e813e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229028687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.2229028687
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.981307055
Short name T273
Test name
Test status
Simulation time 192574474358 ps
CPU time 332.29 seconds
Started Aug 05 05:56:30 PM PDT 24
Finished Aug 05 06:02:03 PM PDT 24
Peak memory 191692 kb
Host smart-5786160f-483a-4dde-8754-b39c45a4bd78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981307055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.981307055
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.2458740754
Short name T246
Test name
Test status
Simulation time 57368362524 ps
CPU time 44.22 seconds
Started Aug 05 05:56:29 PM PDT 24
Finished Aug 05 05:57:13 PM PDT 24
Peak memory 183268 kb
Host smart-bd5de9c8-ba4c-483f-8d6a-8e149fb98c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458740754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.2458740754
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.411245317
Short name T35
Test name
Test status
Simulation time 1772942482683 ps
CPU time 565.57 seconds
Started Aug 05 05:56:29 PM PDT 24
Finished Aug 05 06:05:54 PM PDT 24
Peak memory 196468 kb
Host smart-5d3cde2e-1d5f-4bfa-929d-f015079bf01b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411245317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all.
411245317
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.1415592148
Short name T142
Test name
Test status
Simulation time 335330491539 ps
CPU time 424.48 seconds
Started Aug 05 05:56:35 PM PDT 24
Finished Aug 05 06:03:40 PM PDT 24
Peak memory 183436 kb
Host smart-c5e39531-79dd-4908-8f30-237e8fa02e40
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415592148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.1415592148
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.2310590446
Short name T397
Test name
Test status
Simulation time 825835973149 ps
CPU time 226.12 seconds
Started Aug 05 05:56:35 PM PDT 24
Finished Aug 05 06:00:21 PM PDT 24
Peak memory 183472 kb
Host smart-7f3be67c-8518-4c91-83a3-18e73b08e009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310590446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.2310590446
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.475304010
Short name T158
Test name
Test status
Simulation time 170236098531 ps
CPU time 135.35 seconds
Started Aug 05 05:56:35 PM PDT 24
Finished Aug 05 05:58:50 PM PDT 24
Peak memory 183468 kb
Host smart-283b1c05-1f1d-442b-a869-b7aec51ed773
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475304010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.rv_timer_cfg_update_on_fly.475304010
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.140771867
Short name T395
Test name
Test status
Simulation time 60888422102 ps
CPU time 65.19 seconds
Started Aug 05 05:56:33 PM PDT 24
Finished Aug 05 05:57:39 PM PDT 24
Peak memory 183672 kb
Host smart-ca35213f-b0c6-459a-b86c-6b32710c7cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140771867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.140771867
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.1242879219
Short name T447
Test name
Test status
Simulation time 87762866696 ps
CPU time 95.79 seconds
Started Aug 05 05:56:33 PM PDT 24
Finished Aug 05 05:58:09 PM PDT 24
Peak memory 191596 kb
Host smart-cc990e77-47a7-4648-80e8-8aca1ddc6b63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242879219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.1242879219
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.3700736163
Short name T336
Test name
Test status
Simulation time 63549560437 ps
CPU time 93.97 seconds
Started Aug 05 05:56:33 PM PDT 24
Finished Aug 05 05:58:07 PM PDT 24
Peak memory 183488 kb
Host smart-ac82baf2-dd0d-458b-9e41-5589ec098c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700736163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.3700736163
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.3229681992
Short name T420
Test name
Test status
Simulation time 65901970 ps
CPU time 0.55 seconds
Started Aug 05 05:56:39 PM PDT 24
Finished Aug 05 05:56:39 PM PDT 24
Peak memory 183240 kb
Host smart-10106faa-5572-4dc6-a5c2-1b16e5a201e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229681992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.3229681992
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.4042005416
Short name T245
Test name
Test status
Simulation time 4217644183306 ps
CPU time 1136.33 seconds
Started Aug 05 05:56:38 PM PDT 24
Finished Aug 05 06:15:35 PM PDT 24
Peak memory 183440 kb
Host smart-b3748d1b-c181-4fd8-aaaa-8f8ef70acb8b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042005416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.4042005416
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.1727227120
Short name T367
Test name
Test status
Simulation time 3905310351 ps
CPU time 6.13 seconds
Started Aug 05 05:56:41 PM PDT 24
Finished Aug 05 05:56:47 PM PDT 24
Peak memory 183280 kb
Host smart-5fbeffe3-1970-4a0d-b46f-49aafdc23913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727227120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.1727227120
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.3839038635
Short name T165
Test name
Test status
Simulation time 542009814521 ps
CPU time 445.76 seconds
Started Aug 05 05:56:39 PM PDT 24
Finished Aug 05 06:04:05 PM PDT 24
Peak memory 191680 kb
Host smart-21de94e6-5dcd-47ec-80e4-7ba4b26a0262
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839038635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.3839038635
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.3498269749
Short name T404
Test name
Test status
Simulation time 423309358 ps
CPU time 1.12 seconds
Started Aug 05 05:56:39 PM PDT 24
Finished Aug 05 05:56:40 PM PDT 24
Peak memory 193136 kb
Host smart-35529b33-60bb-4c4d-8b79-b9011d7035b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498269749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.3498269749
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.267791008
Short name T272
Test name
Test status
Simulation time 1828135987646 ps
CPU time 816.83 seconds
Started Aug 05 05:56:48 PM PDT 24
Finished Aug 05 06:10:24 PM PDT 24
Peak memory 183472 kb
Host smart-4ebc29ca-255b-4795-864f-f1eab6732f68
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267791008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.rv_timer_cfg_update_on_fly.267791008
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.3206409070
Short name T364
Test name
Test status
Simulation time 11913513749 ps
CPU time 18.81 seconds
Started Aug 05 05:56:46 PM PDT 24
Finished Aug 05 05:57:05 PM PDT 24
Peak memory 183440 kb
Host smart-2b6f6e1a-230f-466c-98c1-fbe4e65504b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206409070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.3206409070
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.3516526644
Short name T344
Test name
Test status
Simulation time 42109165951 ps
CPU time 58.51 seconds
Started Aug 05 05:56:45 PM PDT 24
Finished Aug 05 05:57:44 PM PDT 24
Peak memory 183516 kb
Host smart-aef29f0b-11b1-4292-b457-a7afc1172d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516526644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.3516526644
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.3830524703
Short name T89
Test name
Test status
Simulation time 1383014441786 ps
CPU time 1294.03 seconds
Started Aug 05 05:56:46 PM PDT 24
Finished Aug 05 06:18:20 PM PDT 24
Peak memory 191652 kb
Host smart-29418ab1-7338-43ee-b6ed-befbf7c2ef63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830524703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.3830524703
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all_with_rand_reset.3146692491
Short name T40
Test name
Test status
Simulation time 78284960770 ps
CPU time 738.09 seconds
Started Aug 05 05:56:46 PM PDT 24
Finished Aug 05 06:09:04 PM PDT 24
Peak memory 208344 kb
Host smart-14c24f64-de33-4a78-8de6-01e426d6d3fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146692491 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all_with_rand_reset.3146692491
Directory /workspace/46.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.4213840463
Short name T302
Test name
Test status
Simulation time 263176561630 ps
CPU time 481.93 seconds
Started Aug 05 05:56:51 PM PDT 24
Finished Aug 05 06:04:53 PM PDT 24
Peak memory 183432 kb
Host smart-2fd5bbf8-91e8-4669-a70e-8d41d776ad79
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213840463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.4213840463
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.2450743486
Short name T392
Test name
Test status
Simulation time 133511876578 ps
CPU time 211.4 seconds
Started Aug 05 05:56:51 PM PDT 24
Finished Aug 05 06:00:22 PM PDT 24
Peak memory 183472 kb
Host smart-6fb2ed3a-7191-4b05-803f-30887e8d494a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450743486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.2450743486
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.2945291844
Short name T185
Test name
Test status
Simulation time 373005968102 ps
CPU time 129.48 seconds
Started Aug 05 05:56:47 PM PDT 24
Finished Aug 05 05:58:57 PM PDT 24
Peak memory 191692 kb
Host smart-ab6de7b0-0fdf-4e3e-a666-1243fa042191
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945291844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.2945291844
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.3076110939
Short name T450
Test name
Test status
Simulation time 17190758803 ps
CPU time 22.51 seconds
Started Aug 05 05:56:50 PM PDT 24
Finished Aug 05 05:57:13 PM PDT 24
Peak memory 183440 kb
Host smart-ca3d916f-b520-46a4-ad96-68585ec58f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076110939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.3076110939
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all_with_rand_reset.1636487164
Short name T36
Test name
Test status
Simulation time 135451882183 ps
CPU time 694.27 seconds
Started Aug 05 05:56:51 PM PDT 24
Finished Aug 05 06:08:26 PM PDT 24
Peak memory 209136 kb
Host smart-adb1ac1f-48d4-4b70-a715-c760630f4328
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636487164 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all_with_rand_reset.1636487164
Directory /workspace/47.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.3434119961
Short name T226
Test name
Test status
Simulation time 178140694232 ps
CPU time 292.77 seconds
Started Aug 05 05:56:50 PM PDT 24
Finished Aug 05 06:01:43 PM PDT 24
Peak memory 183444 kb
Host smart-15efd1c0-d6b7-487e-9fa7-8d5facb862e3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434119961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.3434119961
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.161213248
Short name T396
Test name
Test status
Simulation time 502882191401 ps
CPU time 199.6 seconds
Started Aug 05 05:56:50 PM PDT 24
Finished Aug 05 06:00:10 PM PDT 24
Peak memory 183416 kb
Host smart-6246345a-bb09-473f-990b-3f7bb02b9d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161213248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.161213248
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.366055114
Short name T23
Test name
Test status
Simulation time 346119826391 ps
CPU time 320.12 seconds
Started Aug 05 05:56:50 PM PDT 24
Finished Aug 05 06:02:10 PM PDT 24
Peak memory 191664 kb
Host smart-edf66dde-6011-49d6-b970-f79484a011e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366055114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.366055114
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.2355125376
Short name T427
Test name
Test status
Simulation time 101198669828 ps
CPU time 90.02 seconds
Started Aug 05 05:56:49 PM PDT 24
Finished Aug 05 05:58:19 PM PDT 24
Peak memory 191876 kb
Host smart-cf602765-f2b2-456a-ac98-b344cd54cbcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355125376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.2355125376
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.793596465
Short name T115
Test name
Test status
Simulation time 1411944871562 ps
CPU time 581.18 seconds
Started Aug 05 05:56:57 PM PDT 24
Finished Aug 05 06:06:38 PM PDT 24
Peak memory 183468 kb
Host smart-0c1be064-3827-4027-90f5-5215b9625e9a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793596465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.rv_timer_cfg_update_on_fly.793596465
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.2136194580
Short name T413
Test name
Test status
Simulation time 269755592319 ps
CPU time 40.14 seconds
Started Aug 05 05:56:57 PM PDT 24
Finished Aug 05 05:57:38 PM PDT 24
Peak memory 183444 kb
Host smart-e591dc4c-fe62-4a06-893b-1e3191beda7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136194580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.2136194580
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.2865072838
Short name T254
Test name
Test status
Simulation time 138057490098 ps
CPU time 328.97 seconds
Started Aug 05 05:56:56 PM PDT 24
Finished Aug 05 06:02:26 PM PDT 24
Peak memory 191640 kb
Host smart-1f66801c-5441-4ccd-a65c-59a526bd574b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865072838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.2865072838
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.579052703
Short name T76
Test name
Test status
Simulation time 43245111960 ps
CPU time 36.52 seconds
Started Aug 05 05:56:56 PM PDT 24
Finished Aug 05 05:57:33 PM PDT 24
Peak memory 195472 kb
Host smart-7559ac15-d8f1-4946-b9df-d115e09adcd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579052703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.579052703
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.1080132848
Short name T389
Test name
Test status
Simulation time 519659411606 ps
CPU time 658.82 seconds
Started Aug 05 05:56:58 PM PDT 24
Finished Aug 05 06:07:57 PM PDT 24
Peak memory 191644 kb
Host smart-b71a63ad-e408-4758-9e62-1f1d19eb4506
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080132848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.1080132848
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all_with_rand_reset.4094664491
Short name T14
Test name
Test status
Simulation time 28398919823 ps
CPU time 298.63 seconds
Started Aug 05 05:56:57 PM PDT 24
Finished Aug 05 06:01:56 PM PDT 24
Peak memory 206380 kb
Host smart-bf68decf-e334-498e-a305-206e525c4144
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094664491 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all_with_rand_reset.4094664491
Directory /workspace/49.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.4142732278
Short name T309
Test name
Test status
Simulation time 1763676525877 ps
CPU time 1385.28 seconds
Started Aug 05 05:53:50 PM PDT 24
Finished Aug 05 06:16:55 PM PDT 24
Peak memory 183472 kb
Host smart-f600df8f-23d3-4050-a402-b4787fb0d9f2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142732278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.4142732278
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.3232476689
Short name T415
Test name
Test status
Simulation time 38499195581 ps
CPU time 50.77 seconds
Started Aug 05 05:53:49 PM PDT 24
Finished Aug 05 05:54:40 PM PDT 24
Peak memory 183436 kb
Host smart-77da301a-9dbc-4c73-946f-6530e3eddf7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232476689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.3232476689
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.3374280986
Short name T116
Test name
Test status
Simulation time 621017944853 ps
CPU time 779.76 seconds
Started Aug 05 05:53:52 PM PDT 24
Finished Aug 05 06:06:52 PM PDT 24
Peak memory 183460 kb
Host smart-879f22af-f0ec-4e34-a84a-b0a52295a450
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374280986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.3374280986
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.1888242874
Short name T107
Test name
Test status
Simulation time 11645388668 ps
CPU time 27.48 seconds
Started Aug 05 05:53:48 PM PDT 24
Finished Aug 05 05:54:16 PM PDT 24
Peak memory 191664 kb
Host smart-5d9a324e-e524-4c85-b58a-cb91b42fcf24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888242874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.1888242874
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.4095174199
Short name T53
Test name
Test status
Simulation time 1127779521496 ps
CPU time 466.08 seconds
Started Aug 05 05:53:55 PM PDT 24
Finished Aug 05 06:01:41 PM PDT 24
Peak memory 191584 kb
Host smart-c85e3131-4d30-4c57-ae22-41e5a9df28b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095174199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
4095174199
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/50.rv_timer_random.4229829217
Short name T114
Test name
Test status
Simulation time 230992563223 ps
CPU time 117.19 seconds
Started Aug 05 05:56:59 PM PDT 24
Finished Aug 05 05:58:56 PM PDT 24
Peak memory 191672 kb
Host smart-da74a269-7d32-4b56-91e6-b859f5ef4049
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229829217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.4229829217
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.1735621990
Short name T353
Test name
Test status
Simulation time 157884024767 ps
CPU time 248.04 seconds
Started Aug 05 05:56:58 PM PDT 24
Finished Aug 05 06:01:06 PM PDT 24
Peak memory 191648 kb
Host smart-45035cea-2dbe-4046-b4f2-26ca8b2c4ad3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735621990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.1735621990
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.2752306144
Short name T64
Test name
Test status
Simulation time 125277588242 ps
CPU time 393.4 seconds
Started Aug 05 05:57:00 PM PDT 24
Finished Aug 05 06:03:34 PM PDT 24
Peak memory 191680 kb
Host smart-1e4f73ec-e16f-445b-b808-3236a39dd55f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752306144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.2752306144
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.2327569712
Short name T268
Test name
Test status
Simulation time 116375469580 ps
CPU time 222.28 seconds
Started Aug 05 05:57:54 PM PDT 24
Finished Aug 05 06:01:37 PM PDT 24
Peak memory 195304 kb
Host smart-e251a9b4-6804-4070-b6ff-f56a3d994426
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327569712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.2327569712
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.3175837986
Short name T259
Test name
Test status
Simulation time 342564099209 ps
CPU time 253.37 seconds
Started Aug 05 05:57:01 PM PDT 24
Finished Aug 05 06:01:15 PM PDT 24
Peak memory 191652 kb
Host smart-b5785d95-c358-4ba1-8a98-0633f5f223ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175837986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.3175837986
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.1260460516
Short name T260
Test name
Test status
Simulation time 779121185578 ps
CPU time 1097.85 seconds
Started Aug 05 05:57:02 PM PDT 24
Finished Aug 05 06:15:21 PM PDT 24
Peak memory 191684 kb
Host smart-cfb7651c-f6bd-41ac-bbb1-e8c90ef9f281
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260460516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.1260460516
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.5672445
Short name T145
Test name
Test status
Simulation time 97816867584 ps
CPU time 76.99 seconds
Started Aug 05 05:57:06 PM PDT 24
Finished Aug 05 05:58:23 PM PDT 24
Peak memory 191652 kb
Host smart-ffed239c-14c4-4417-b83c-781bc7f1b0c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5672445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.5672445
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.588263250
Short name T300
Test name
Test status
Simulation time 229450273242 ps
CPU time 300.35 seconds
Started Aug 05 05:57:08 PM PDT 24
Finished Aug 05 06:02:09 PM PDT 24
Peak memory 191672 kb
Host smart-c48827a5-8479-4a10-aecb-77bafd47217e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588263250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.588263250
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.2436006761
Short name T418
Test name
Test status
Simulation time 47854579007 ps
CPU time 110.15 seconds
Started Aug 05 05:57:07 PM PDT 24
Finished Aug 05 05:58:57 PM PDT 24
Peak memory 191680 kb
Host smart-b9bfb6f1-fa97-4649-82b5-6e36c2efd3f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436006761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.2436006761
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.2280806117
Short name T3
Test name
Test status
Simulation time 282254900566 ps
CPU time 751.8 seconds
Started Aug 05 05:57:11 PM PDT 24
Finished Aug 05 06:09:43 PM PDT 24
Peak memory 191696 kb
Host smart-3ec65970-1b9f-41d4-9fc1-9eb57bff8d97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280806117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.2280806117
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.1215464372
Short name T174
Test name
Test status
Simulation time 74004638357 ps
CPU time 127.97 seconds
Started Aug 05 05:53:55 PM PDT 24
Finished Aug 05 05:56:03 PM PDT 24
Peak memory 183416 kb
Host smart-9d79c16c-f917-4805-99ae-4241a2765795
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215464372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.1215464372
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.2618334282
Short name T419
Test name
Test status
Simulation time 94379581842 ps
CPU time 135.77 seconds
Started Aug 05 05:53:56 PM PDT 24
Finished Aug 05 05:56:12 PM PDT 24
Peak memory 183464 kb
Host smart-a0f0dafb-9ee3-4253-b030-e9d2aebea678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618334282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.2618334282
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.3184480237
Short name T366
Test name
Test status
Simulation time 376207273 ps
CPU time 0.98 seconds
Started Aug 05 05:53:53 PM PDT 24
Finished Aug 05 05:53:55 PM PDT 24
Peak memory 183212 kb
Host smart-3919f92d-0d09-43a3-80d9-2ba4548298a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184480237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.3184480237
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all_with_rand_reset.1445184007
Short name T38
Test name
Test status
Simulation time 346133468158 ps
CPU time 446.1 seconds
Started Aug 05 05:53:55 PM PDT 24
Finished Aug 05 06:01:21 PM PDT 24
Peak memory 206332 kb
Host smart-93bdc23d-5ece-4ac1-b71e-18d3deabe187
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445184007 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all_with_rand_reset.1445184007
Directory /workspace/6.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.3346078480
Short name T332
Test name
Test status
Simulation time 163055449354 ps
CPU time 460.95 seconds
Started Aug 05 05:57:14 PM PDT 24
Finished Aug 05 06:04:55 PM PDT 24
Peak memory 191648 kb
Host smart-c46b6449-9844-406b-92cc-9242f6ebf7fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346078480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.3346078480
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.102514585
Short name T192
Test name
Test status
Simulation time 7992002897 ps
CPU time 12.66 seconds
Started Aug 05 05:57:15 PM PDT 24
Finished Aug 05 05:57:28 PM PDT 24
Peak memory 183448 kb
Host smart-4db8edd8-34c8-4411-a975-44f8263ad3a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102514585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.102514585
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.3878080894
Short name T255
Test name
Test status
Simulation time 326835310480 ps
CPU time 491.98 seconds
Started Aug 05 05:57:14 PM PDT 24
Finished Aug 05 06:05:27 PM PDT 24
Peak memory 191648 kb
Host smart-1bdf37d3-c621-48f9-b5e6-7f1dfcb63939
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878080894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.3878080894
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.2026850885
Short name T147
Test name
Test status
Simulation time 394884030836 ps
CPU time 339.43 seconds
Started Aug 05 05:57:11 PM PDT 24
Finished Aug 05 06:02:51 PM PDT 24
Peak memory 191628 kb
Host smart-fc811e7c-4283-438e-8061-8374e8585865
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026850885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.2026850885
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.2477339768
Short name T207
Test name
Test status
Simulation time 892053432052 ps
CPU time 1481.2 seconds
Started Aug 05 05:57:12 PM PDT 24
Finished Aug 05 06:21:53 PM PDT 24
Peak memory 191636 kb
Host smart-a285703a-c9dd-48f2-aa26-35ce9cf4c752
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477339768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.2477339768
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.3777376016
Short name T225
Test name
Test status
Simulation time 115148023633 ps
CPU time 241.34 seconds
Started Aug 05 05:57:13 PM PDT 24
Finished Aug 05 06:01:15 PM PDT 24
Peak memory 191684 kb
Host smart-79e129d8-4490-4e39-a1d1-83825faa656a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777376016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.3777376016
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.2081025327
Short name T181
Test name
Test status
Simulation time 229796330558 ps
CPU time 100.8 seconds
Started Aug 05 05:57:15 PM PDT 24
Finished Aug 05 05:58:56 PM PDT 24
Peak memory 191640 kb
Host smart-f24511ac-8a71-4731-9c54-892d3c16f158
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081025327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.2081025327
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.4248559825
Short name T250
Test name
Test status
Simulation time 125724591953 ps
CPU time 124.76 seconds
Started Aug 05 05:57:13 PM PDT 24
Finished Aug 05 05:59:18 PM PDT 24
Peak memory 191648 kb
Host smart-246e4964-cd29-4b27-a56b-5e27a63d6694
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248559825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.4248559825
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.1765382133
Short name T253
Test name
Test status
Simulation time 133876496774 ps
CPU time 239.8 seconds
Started Aug 05 05:57:15 PM PDT 24
Finished Aug 05 06:01:15 PM PDT 24
Peak memory 191664 kb
Host smart-f112eb52-de7a-4ec5-beb4-d473872a83b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765382133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.1765382133
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.1515743088
Short name T343
Test name
Test status
Simulation time 141014002663 ps
CPU time 225.25 seconds
Started Aug 05 05:54:01 PM PDT 24
Finished Aug 05 05:57:46 PM PDT 24
Peak memory 183400 kb
Host smart-c3bacfc8-601b-4ed5-93b5-008743a92ee2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515743088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.1515743088
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.3192712660
Short name T373
Test name
Test status
Simulation time 185971264815 ps
CPU time 299.04 seconds
Started Aug 05 05:54:00 PM PDT 24
Finished Aug 05 05:58:59 PM PDT 24
Peak memory 183672 kb
Host smart-4e326e0d-7d7c-4a11-bdd1-95a079513acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192712660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.3192712660
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.339363112
Short name T122
Test name
Test status
Simulation time 313734894443 ps
CPU time 127.78 seconds
Started Aug 05 05:54:01 PM PDT 24
Finished Aug 05 05:56:08 PM PDT 24
Peak memory 191684 kb
Host smart-811b1b64-467a-459c-9a46-2736f00e96e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339363112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.339363112
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.2436676279
Short name T355
Test name
Test status
Simulation time 13747386918 ps
CPU time 24.71 seconds
Started Aug 05 05:54:00 PM PDT 24
Finished Aug 05 05:54:25 PM PDT 24
Peak memory 183432 kb
Host smart-415ddbd6-d61c-410c-b17c-bdcf1559dd18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436676279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.2436676279
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.3239549477
Short name T220
Test name
Test status
Simulation time 2084633903492 ps
CPU time 456.15 seconds
Started Aug 05 05:53:59 PM PDT 24
Finished Aug 05 06:01:36 PM PDT 24
Peak memory 191632 kb
Host smart-0581cfd4-4a93-4c1e-a697-30329e9f179a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239549477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
3239549477
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/70.rv_timer_random.3256544877
Short name T318
Test name
Test status
Simulation time 12980007582 ps
CPU time 21.66 seconds
Started Aug 05 05:57:19 PM PDT 24
Finished Aug 05 05:57:40 PM PDT 24
Peak memory 183440 kb
Host smart-726632ec-ca57-48ac-b71d-b1b27f9c197e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256544877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.3256544877
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.2519572246
Short name T106
Test name
Test status
Simulation time 57876733765 ps
CPU time 158.38 seconds
Started Aug 05 05:57:26 PM PDT 24
Finished Aug 05 06:00:04 PM PDT 24
Peak memory 183448 kb
Host smart-6cfe01e8-ff5e-47a1-acff-da6197faff19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519572246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.2519572246
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.3757930734
Short name T221
Test name
Test status
Simulation time 42490071134 ps
CPU time 194.84 seconds
Started Aug 05 05:57:24 PM PDT 24
Finished Aug 05 06:00:39 PM PDT 24
Peak memory 191656 kb
Host smart-bd21f12f-4722-448b-a36e-7f26debbb8f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757930734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.3757930734
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.3400735990
Short name T346
Test name
Test status
Simulation time 698532456155 ps
CPU time 335.76 seconds
Started Aug 05 05:57:23 PM PDT 24
Finished Aug 05 06:02:59 PM PDT 24
Peak memory 191672 kb
Host smart-1462a9fe-034f-4b3d-a702-c4e8ef735cb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400735990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.3400735990
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.4283637641
Short name T186
Test name
Test status
Simulation time 4569066654 ps
CPU time 8.56 seconds
Started Aug 05 05:57:22 PM PDT 24
Finished Aug 05 05:57:31 PM PDT 24
Peak memory 183448 kb
Host smart-4b7e0e16-6674-4934-986a-70eb2d13845e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283637641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.4283637641
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.3691823270
Short name T218
Test name
Test status
Simulation time 24142286505 ps
CPU time 225.9 seconds
Started Aug 05 05:57:21 PM PDT 24
Finished Aug 05 06:01:07 PM PDT 24
Peak memory 183388 kb
Host smart-153a9fa7-79e6-4f27-99fa-63a12c72bb10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691823270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.3691823270
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.3417458396
Short name T103
Test name
Test status
Simulation time 213046858532 ps
CPU time 355.08 seconds
Started Aug 05 05:57:24 PM PDT 24
Finished Aug 05 06:03:19 PM PDT 24
Peak memory 195144 kb
Host smart-b6a2c012-147a-4d5c-832b-b592a57dc040
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417458396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.3417458396
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.1523025660
Short name T311
Test name
Test status
Simulation time 55226499911 ps
CPU time 105.17 seconds
Started Aug 05 05:57:26 PM PDT 24
Finished Aug 05 05:59:12 PM PDT 24
Peak memory 191640 kb
Host smart-ccc51721-9bec-4363-afe3-a1dc1c81edce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523025660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.1523025660
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.3789104475
Short name T214
Test name
Test status
Simulation time 163900188014 ps
CPU time 91.18 seconds
Started Aug 05 05:53:59 PM PDT 24
Finished Aug 05 05:55:30 PM PDT 24
Peak memory 183440 kb
Host smart-487e29dd-65c7-426c-a4f3-23e4828d0e32
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789104475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.3789104475
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.2511554640
Short name T435
Test name
Test status
Simulation time 34528683483 ps
CPU time 25.62 seconds
Started Aug 05 05:54:00 PM PDT 24
Finished Aug 05 05:54:26 PM PDT 24
Peak memory 183472 kb
Host smart-4b72508d-a995-4a69-bc87-9a03d37dfa86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511554640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.2511554640
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.3254278220
Short name T328
Test name
Test status
Simulation time 72390523219 ps
CPU time 66.33 seconds
Started Aug 05 05:54:00 PM PDT 24
Finished Aug 05 05:55:07 PM PDT 24
Peak memory 191668 kb
Host smart-2d6bec75-4864-4efc-936f-a288e5dbc405
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254278220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.3254278220
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.3085990330
Short name T157
Test name
Test status
Simulation time 45948007453 ps
CPU time 77.45 seconds
Started Aug 05 05:54:01 PM PDT 24
Finished Aug 05 05:55:19 PM PDT 24
Peak memory 183464 kb
Host smart-a43ef6ed-e51e-4809-820a-3deabfa3c446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085990330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.3085990330
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.4215104762
Short name T4
Test name
Test status
Simulation time 486039189661 ps
CPU time 1206.96 seconds
Started Aug 05 05:53:59 PM PDT 24
Finished Aug 05 06:14:06 PM PDT 24
Peak memory 191580 kb
Host smart-d8461a41-9be7-4f9a-b382-38ac38a158bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215104762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
4215104762
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/80.rv_timer_random.2723141442
Short name T429
Test name
Test status
Simulation time 65087593587 ps
CPU time 349.32 seconds
Started Aug 05 05:57:22 PM PDT 24
Finished Aug 05 06:03:12 PM PDT 24
Peak memory 191688 kb
Host smart-b4a6f76e-e60c-4f07-abe8-37daf3271358
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723141442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.2723141442
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.538235202
Short name T296
Test name
Test status
Simulation time 326070392798 ps
CPU time 1048.09 seconds
Started Aug 05 05:57:22 PM PDT 24
Finished Aug 05 06:14:50 PM PDT 24
Peak memory 191672 kb
Host smart-1edb2563-ac83-4937-a3e5-48454676b412
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538235202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.538235202
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.1242923249
Short name T348
Test name
Test status
Simulation time 319599712334 ps
CPU time 445.81 seconds
Started Aug 05 05:57:28 PM PDT 24
Finished Aug 05 06:04:53 PM PDT 24
Peak memory 191656 kb
Host smart-087cdfa1-9cc5-4c99-b956-625cf9c41769
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242923249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.1242923249
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.1252558571
Short name T10
Test name
Test status
Simulation time 19800837398 ps
CPU time 30.69 seconds
Started Aug 05 05:57:28 PM PDT 24
Finished Aug 05 05:57:58 PM PDT 24
Peak memory 183472 kb
Host smart-80e361d2-c9fc-4138-8ab8-ef01a61ab61c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252558571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.1252558571
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.497750879
Short name T393
Test name
Test status
Simulation time 272973573869 ps
CPU time 78.82 seconds
Started Aug 05 05:57:27 PM PDT 24
Finished Aug 05 05:58:46 PM PDT 24
Peak memory 183428 kb
Host smart-dcc065c9-0865-44a7-97e6-843bed917b47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497750879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.497750879
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.3809073
Short name T238
Test name
Test status
Simulation time 14015984713 ps
CPU time 25.22 seconds
Started Aug 05 05:57:27 PM PDT 24
Finished Aug 05 05:57:53 PM PDT 24
Peak memory 183480 kb
Host smart-fb2fc7d8-8030-4c74-bc71-78cd3cdf6f2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.3809073
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.2204310088
Short name T275
Test name
Test status
Simulation time 24395274753 ps
CPU time 12.69 seconds
Started Aug 05 05:57:28 PM PDT 24
Finished Aug 05 05:57:40 PM PDT 24
Peak memory 183472 kb
Host smart-6f762541-dc19-4d2e-8861-1b087b62f77a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204310088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.2204310088
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.1467298065
Short name T303
Test name
Test status
Simulation time 624934408892 ps
CPU time 215.67 seconds
Started Aug 05 05:57:39 PM PDT 24
Finished Aug 05 06:01:15 PM PDT 24
Peak memory 191644 kb
Host smart-cca04b87-60cf-47c3-b8b1-d0b665788dd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467298065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.1467298065
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.1719157693
Short name T299
Test name
Test status
Simulation time 699404347640 ps
CPU time 510.91 seconds
Started Aug 05 05:53:59 PM PDT 24
Finished Aug 05 06:02:30 PM PDT 24
Peak memory 183448 kb
Host smart-3a86bbec-e5ae-478e-b995-98bc1a0ddd65
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719157693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.1719157693
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.2757899118
Short name T388
Test name
Test status
Simulation time 78377947215 ps
CPU time 28.36 seconds
Started Aug 05 05:54:01 PM PDT 24
Finished Aug 05 05:54:29 PM PDT 24
Peak memory 183452 kb
Host smart-7c869c1d-5242-4307-b8b6-519cd028d97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757899118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.2757899118
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.4023780924
Short name T349
Test name
Test status
Simulation time 648146555201 ps
CPU time 531.07 seconds
Started Aug 05 05:53:59 PM PDT 24
Finished Aug 05 06:02:50 PM PDT 24
Peak memory 191720 kb
Host smart-07753508-6f0f-46f7-8b5a-6919dff740b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023780924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.4023780924
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.495431456
Short name T335
Test name
Test status
Simulation time 7514609926 ps
CPU time 5.4 seconds
Started Aug 05 05:54:06 PM PDT 24
Finished Aug 05 05:54:12 PM PDT 24
Peak memory 195144 kb
Host smart-6fd8b4c7-d4a7-47c0-9d56-ff7d88308631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495431456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.495431456
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.3377438718
Short name T361
Test name
Test status
Simulation time 203191702405 ps
CPU time 119.54 seconds
Started Aug 05 05:57:34 PM PDT 24
Finished Aug 05 05:59:34 PM PDT 24
Peak memory 183460 kb
Host smart-c00c52f3-f603-4d76-815b-e1ff3a013f80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377438718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.3377438718
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.3206154502
Short name T151
Test name
Test status
Simulation time 20761206647 ps
CPU time 413.56 seconds
Started Aug 05 05:57:39 PM PDT 24
Finished Aug 05 06:04:33 PM PDT 24
Peak memory 191644 kb
Host smart-7bf3e415-3c36-4245-aa35-3a7583c73751
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206154502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.3206154502
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.1486768241
Short name T280
Test name
Test status
Simulation time 65970860896 ps
CPU time 80.32 seconds
Started Aug 05 05:57:39 PM PDT 24
Finished Aug 05 05:58:59 PM PDT 24
Peak memory 183452 kb
Host smart-e3e1125a-3329-4162-b602-5f3871e5071a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486768241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.1486768241
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.4179769310
Short name T102
Test name
Test status
Simulation time 147974329238 ps
CPU time 196.5 seconds
Started Aug 05 05:57:40 PM PDT 24
Finished Aug 05 06:00:57 PM PDT 24
Peak memory 191636 kb
Host smart-3970453e-7051-466c-9078-00a4e5f34e29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179769310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.4179769310
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.2680954473
Short name T62
Test name
Test status
Simulation time 277395279075 ps
CPU time 65.75 seconds
Started Aug 05 05:57:40 PM PDT 24
Finished Aug 05 05:58:46 PM PDT 24
Peak memory 183456 kb
Host smart-1379b2d1-a8b5-4f7d-98f1-8aa6a0b986ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680954473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.2680954473
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.2685563525
Short name T345
Test name
Test status
Simulation time 888563344545 ps
CPU time 253.02 seconds
Started Aug 05 05:57:39 PM PDT 24
Finished Aug 05 06:01:52 PM PDT 24
Peak memory 191656 kb
Host smart-8c002065-543a-433a-ba86-e3b8ed078d1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685563525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.2685563525
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.3823849894
Short name T305
Test name
Test status
Simulation time 121837717325 ps
CPU time 174.35 seconds
Started Aug 05 05:57:40 PM PDT 24
Finished Aug 05 06:00:35 PM PDT 24
Peak memory 191636 kb
Host smart-7e0473e3-2ada-4ebd-b758-7c14c78c412d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823849894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.3823849894
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.477769004
Short name T431
Test name
Test status
Simulation time 77888611602 ps
CPU time 151.56 seconds
Started Aug 05 05:57:37 PM PDT 24
Finished Aug 05 06:00:09 PM PDT 24
Peak memory 191680 kb
Host smart-555f0a2f-3d98-41d8-ab44-080f37eaf331
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477769004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.477769004
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.4034130002
Short name T438
Test name
Test status
Simulation time 403695899492 ps
CPU time 224.52 seconds
Started Aug 05 05:57:48 PM PDT 24
Finished Aug 05 06:01:33 PM PDT 24
Peak memory 191636 kb
Host smart-131fb377-9c14-4585-a2bf-94859b8daaa4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034130002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.4034130002
Directory /workspace/98.rv_timer_random/latest
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