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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.61 99.36 98.73 100.00 100.00 100.00 99.55


Total test records in report: 582
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T505 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.3740104968 Aug 06 07:04:52 PM PDT 24 Aug 06 07:04:54 PM PDT 24 74265140 ps
T506 /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.339754608 Aug 06 07:04:55 PM PDT 24 Aug 06 07:04:55 PM PDT 24 103864184 ps
T507 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.502071948 Aug 06 07:04:49 PM PDT 24 Aug 06 07:04:50 PM PDT 24 565888355 ps
T508 /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.292977878 Aug 06 07:04:24 PM PDT 24 Aug 06 07:04:26 PM PDT 24 101526219 ps
T509 /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.3444147411 Aug 06 07:04:22 PM PDT 24 Aug 06 07:04:23 PM PDT 24 332245547 ps
T510 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.2434497564 Aug 06 07:04:59 PM PDT 24 Aug 06 07:05:00 PM PDT 24 28473082 ps
T511 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.4197745204 Aug 06 07:05:03 PM PDT 24 Aug 06 07:05:03 PM PDT 24 45448737 ps
T512 /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.880862875 Aug 06 07:04:53 PM PDT 24 Aug 06 07:04:55 PM PDT 24 118194745 ps
T513 /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1368087438 Aug 06 07:04:51 PM PDT 24 Aug 06 07:04:52 PM PDT 24 38032665 ps
T514 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3100726756 Aug 06 07:04:24 PM PDT 24 Aug 06 07:04:25 PM PDT 24 84991109 ps
T515 /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.2328625621 Aug 06 07:04:05 PM PDT 24 Aug 06 07:04:05 PM PDT 24 35016978 ps
T516 /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.2633313697 Aug 06 07:04:52 PM PDT 24 Aug 06 07:04:53 PM PDT 24 12980053 ps
T517 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.4249121745 Aug 06 07:04:50 PM PDT 24 Aug 06 07:04:51 PM PDT 24 427768850 ps
T518 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.2939424863 Aug 06 07:04:52 PM PDT 24 Aug 06 07:04:53 PM PDT 24 21840235 ps
T519 /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2747506156 Aug 06 07:04:50 PM PDT 24 Aug 06 07:04:51 PM PDT 24 47979318 ps
T520 /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.2687367297 Aug 06 07:04:14 PM PDT 24 Aug 06 07:04:15 PM PDT 24 149675493 ps
T96 /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.1575204825 Aug 06 07:04:23 PM PDT 24 Aug 06 07:04:25 PM PDT 24 137486425 ps
T521 /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.1180019780 Aug 06 07:04:23 PM PDT 24 Aug 06 07:04:24 PM PDT 24 38718534 ps
T522 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.4234868401 Aug 06 07:04:57 PM PDT 24 Aug 06 07:04:58 PM PDT 24 89278406 ps
T523 /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.1413149564 Aug 06 07:04:20 PM PDT 24 Aug 06 07:04:21 PM PDT 24 259128921 ps
T524 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3499129863 Aug 06 07:04:52 PM PDT 24 Aug 06 07:04:53 PM PDT 24 36433974 ps
T525 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.3687407858 Aug 06 07:05:00 PM PDT 24 Aug 06 07:05:00 PM PDT 24 37503270 ps
T526 /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.3840121495 Aug 06 07:04:50 PM PDT 24 Aug 06 07:04:51 PM PDT 24 133909250 ps
T527 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.247394187 Aug 06 07:04:18 PM PDT 24 Aug 06 07:04:18 PM PDT 24 64906177 ps
T528 /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.3835746231 Aug 06 07:04:25 PM PDT 24 Aug 06 07:04:26 PM PDT 24 451045654 ps
T529 /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.3454832557 Aug 06 07:04:53 PM PDT 24 Aug 06 07:04:54 PM PDT 24 26968719 ps
T81 /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.1292753086 Aug 06 07:04:52 PM PDT 24 Aug 06 07:04:52 PM PDT 24 72869165 ps
T530 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.1337109388 Aug 06 07:04:08 PM PDT 24 Aug 06 07:04:10 PM PDT 24 104015508 ps
T531 /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.120189198 Aug 06 07:04:51 PM PDT 24 Aug 06 07:04:52 PM PDT 24 28640953 ps
T532 /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.989675351 Aug 06 07:04:18 PM PDT 24 Aug 06 07:04:19 PM PDT 24 41171716 ps
T533 /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.2152565812 Aug 06 07:04:56 PM PDT 24 Aug 06 07:04:57 PM PDT 24 12637422 ps
T534 /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.3143840405 Aug 06 07:04:57 PM PDT 24 Aug 06 07:04:57 PM PDT 24 22417026 ps
T535 /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.2387051008 Aug 06 07:04:51 PM PDT 24 Aug 06 07:04:52 PM PDT 24 153719415 ps
T82 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.2832916936 Aug 06 07:04:12 PM PDT 24 Aug 06 07:04:14 PM PDT 24 198188730 ps
T536 /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.3478207377 Aug 06 07:04:57 PM PDT 24 Aug 06 07:04:58 PM PDT 24 34217940 ps
T537 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3562652900 Aug 06 07:04:50 PM PDT 24 Aug 06 07:04:51 PM PDT 24 16918160 ps
T538 /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.941147548 Aug 06 07:04:17 PM PDT 24 Aug 06 07:04:18 PM PDT 24 20239868 ps
T539 /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.2667030238 Aug 06 07:04:55 PM PDT 24 Aug 06 07:04:56 PM PDT 24 17261459 ps
T540 /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.2448641450 Aug 06 07:04:11 PM PDT 24 Aug 06 07:04:12 PM PDT 24 19349512 ps
T541 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1667283040 Aug 06 07:04:53 PM PDT 24 Aug 06 07:04:53 PM PDT 24 32600520 ps
T542 /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.2643337741 Aug 06 07:04:57 PM PDT 24 Aug 06 07:04:58 PM PDT 24 83459102 ps
T543 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.3483915793 Aug 06 07:04:16 PM PDT 24 Aug 06 07:04:17 PM PDT 24 16535965 ps
T544 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.1294240944 Aug 06 07:04:52 PM PDT 24 Aug 06 07:04:53 PM PDT 24 44344715 ps
T545 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.3506195543 Aug 06 07:04:08 PM PDT 24 Aug 06 07:04:09 PM PDT 24 14452067 ps
T546 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.2086347924 Aug 06 07:04:08 PM PDT 24 Aug 06 07:04:10 PM PDT 24 151170674 ps
T547 /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.2155406536 Aug 06 07:04:09 PM PDT 24 Aug 06 07:04:11 PM PDT 24 111113633 ps
T548 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1465096606 Aug 06 07:04:51 PM PDT 24 Aug 06 07:04:52 PM PDT 24 165568270 ps
T549 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.1495915175 Aug 06 07:04:51 PM PDT 24 Aug 06 07:04:53 PM PDT 24 36922377 ps
T550 /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3176887770 Aug 06 07:04:50 PM PDT 24 Aug 06 07:04:51 PM PDT 24 16598098 ps
T551 /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.3429650337 Aug 06 07:05:01 PM PDT 24 Aug 06 07:05:02 PM PDT 24 31202611 ps
T552 /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.465964777 Aug 06 07:04:24 PM PDT 24 Aug 06 07:04:24 PM PDT 24 54634519 ps
T553 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.737331178 Aug 06 07:04:23 PM PDT 24 Aug 06 07:04:24 PM PDT 24 80038637 ps
T554 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.3920314985 Aug 06 07:04:50 PM PDT 24 Aug 06 07:04:51 PM PDT 24 20439707 ps
T555 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1704520342 Aug 06 07:04:05 PM PDT 24 Aug 06 07:04:07 PM PDT 24 148101258 ps
T556 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.525791421 Aug 06 07:04:55 PM PDT 24 Aug 06 07:04:55 PM PDT 24 87379546 ps
T557 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.3083385655 Aug 06 07:04:09 PM PDT 24 Aug 06 07:04:10 PM PDT 24 47711428 ps
T558 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.3271475989 Aug 06 07:04:25 PM PDT 24 Aug 06 07:04:26 PM PDT 24 24512875 ps
T559 /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.3250089378 Aug 06 07:04:52 PM PDT 24 Aug 06 07:04:53 PM PDT 24 60312735 ps
T560 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2783353917 Aug 06 07:04:19 PM PDT 24 Aug 06 07:04:20 PM PDT 24 38932641 ps
T561 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3311718325 Aug 06 07:04:12 PM PDT 24 Aug 06 07:04:13 PM PDT 24 328216298 ps
T562 /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.4110989417 Aug 06 07:04:25 PM PDT 24 Aug 06 07:04:26 PM PDT 24 11687842 ps
T563 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.14155829 Aug 06 07:04:55 PM PDT 24 Aug 06 07:04:56 PM PDT 24 27738584 ps
T564 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.998262153 Aug 06 07:04:59 PM PDT 24 Aug 06 07:05:00 PM PDT 24 14212128 ps
T565 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3084513537 Aug 06 07:04:50 PM PDT 24 Aug 06 07:04:50 PM PDT 24 131592061 ps
T566 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.1972941094 Aug 06 07:04:51 PM PDT 24 Aug 06 07:04:51 PM PDT 24 139564559 ps
T83 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.124810622 Aug 06 07:04:23 PM PDT 24 Aug 06 07:04:24 PM PDT 24 19115066 ps
T567 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.3676287005 Aug 06 07:04:08 PM PDT 24 Aug 06 07:04:08 PM PDT 24 20094706 ps
T568 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.3380277526 Aug 06 07:04:23 PM PDT 24 Aug 06 07:04:24 PM PDT 24 47481486 ps
T569 /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.1156831509 Aug 06 07:04:07 PM PDT 24 Aug 06 07:04:08 PM PDT 24 19194242 ps
T570 /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.3541396604 Aug 06 07:04:56 PM PDT 24 Aug 06 07:04:56 PM PDT 24 13397165 ps
T571 /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.263092873 Aug 06 07:04:50 PM PDT 24 Aug 06 07:04:51 PM PDT 24 25140360 ps
T572 /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.2270848213 Aug 06 07:04:59 PM PDT 24 Aug 06 07:05:00 PM PDT 24 108221758 ps
T573 /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.867791019 Aug 06 07:04:51 PM PDT 24 Aug 06 07:04:52 PM PDT 24 271553691 ps
T574 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2124461578 Aug 06 07:04:57 PM PDT 24 Aug 06 07:04:57 PM PDT 24 10750202 ps
T575 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.87647743 Aug 06 07:04:18 PM PDT 24 Aug 06 07:04:19 PM PDT 24 26832047 ps
T576 /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2065510355 Aug 06 07:04:49 PM PDT 24 Aug 06 07:04:50 PM PDT 24 77326733 ps
T577 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.1007188557 Aug 06 07:04:18 PM PDT 24 Aug 06 07:04:18 PM PDT 24 38109476 ps
T578 /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.1420234221 Aug 06 07:04:11 PM PDT 24 Aug 06 07:04:12 PM PDT 24 340722425 ps
T579 /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.794295204 Aug 06 07:04:53 PM PDT 24 Aug 06 07:04:54 PM PDT 24 24531197 ps
T580 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.2705985275 Aug 06 07:04:53 PM PDT 24 Aug 06 07:04:53 PM PDT 24 15480619 ps
T581 /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.2170242049 Aug 06 07:04:51 PM PDT 24 Aug 06 07:04:51 PM PDT 24 167542487 ps
T582 /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.1652635992 Aug 06 07:04:53 PM PDT 24 Aug 06 07:04:54 PM PDT 24 12107664 ps

Test location /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.2119385784
Short name T5
Test name
Test status
Simulation time 28944854017 ps
CPU time 215.74 seconds
Started Aug 06 07:05:07 PM PDT 24
Finished Aug 06 07:08:43 PM PDT 24
Peak memory 198136 kb
Host smart-821ae6d5-2e35-439a-9274-46f54b0302a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119385784 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_reset.2119385784
Directory /workspace/23.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/132.rv_timer_random.2358075059
Short name T38
Test name
Test status
Simulation time 452652812844 ps
CPU time 241.71 seconds
Started Aug 06 07:06:05 PM PDT 24
Finished Aug 06 07:10:07 PM PDT 24
Peak memory 191620 kb
Host smart-c4fc7496-a0dc-4562-ac61-298ed5cb444a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358075059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.2358075059
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.2705483675
Short name T58
Test name
Test status
Simulation time 1330925456488 ps
CPU time 3160.71 seconds
Started Aug 06 07:05:08 PM PDT 24
Finished Aug 06 07:57:50 PM PDT 24
Peak memory 194352 kb
Host smart-188686e8-0819-475a-ac7f-a3d311d8ff46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705483675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.2705483675
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.2980634585
Short name T100
Test name
Test status
Simulation time 963719268150 ps
CPU time 1219.15 seconds
Started Aug 06 07:05:01 PM PDT 24
Finished Aug 06 07:25:21 PM PDT 24
Peak memory 191632 kb
Host smart-3d65f4ae-32d5-4dd9-aa09-0bc8cd6d9173
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980634585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.2980634585
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.1491084081
Short name T28
Test name
Test status
Simulation time 423365538 ps
CPU time 1.12 seconds
Started Aug 06 07:04:08 PM PDT 24
Finished Aug 06 07:04:10 PM PDT 24
Peak memory 194424 kb
Host smart-d9a96cf0-4411-488f-b6ff-87ebed37bfe3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491084081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.1491084081
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.502539583
Short name T25
Test name
Test status
Simulation time 470073622140 ps
CPU time 4181.37 seconds
Started Aug 06 07:04:58 PM PDT 24
Finished Aug 06 08:14:40 PM PDT 24
Peak memory 191648 kb
Host smart-c2a804c2-4459-4273-9cb6-79eefe76ffde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502539583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.502539583
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.4003067929
Short name T127
Test name
Test status
Simulation time 1708664288271 ps
CPU time 2311.87 seconds
Started Aug 06 07:05:27 PM PDT 24
Finished Aug 06 07:43:59 PM PDT 24
Peak memory 191544 kb
Host smart-e244d141-e2f8-42a7-9d0d-67fda1a9be47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003067929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.4003067929
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.3940308325
Short name T192
Test name
Test status
Simulation time 1059490093279 ps
CPU time 3179.14 seconds
Started Aug 06 07:04:58 PM PDT 24
Finished Aug 06 07:57:57 PM PDT 24
Peak memory 191636 kb
Host smart-db10ebd9-1df3-44e4-9811-ac45c8f621ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940308325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.3940308325
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.110207136
Short name T149
Test name
Test status
Simulation time 4437769912366 ps
CPU time 2336.54 seconds
Started Aug 06 07:05:15 PM PDT 24
Finished Aug 06 07:44:11 PM PDT 24
Peak memory 196368 kb
Host smart-550742cf-180c-47f6-b0e1-198c91c14bda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110207136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all.
110207136
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.929514571
Short name T148
Test name
Test status
Simulation time 3881130328741 ps
CPU time 1379.03 seconds
Started Aug 06 07:05:15 PM PDT 24
Finished Aug 06 07:28:15 PM PDT 24
Peak memory 191668 kb
Host smart-af98890e-95f7-4959-a007-842c90cd3e7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929514571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all.
929514571
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.166465466
Short name T30
Test name
Test status
Simulation time 103894410 ps
CPU time 0.72 seconds
Started Aug 06 07:04:10 PM PDT 24
Finished Aug 06 07:04:11 PM PDT 24
Peak memory 193332 kb
Host smart-e0c2e29b-b601-4cbb-a8bc-abd519d0ccfe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166465466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_tim
er_same_csr_outstanding.166465466
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/157.rv_timer_random.1706960886
Short name T18
Test name
Test status
Simulation time 114492700234 ps
CPU time 234.37 seconds
Started Aug 06 07:06:14 PM PDT 24
Finished Aug 06 07:10:09 PM PDT 24
Peak memory 191488 kb
Host smart-e0820e4b-9631-47be-b8eb-ff0e7a000131
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706960886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.1706960886
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.3124874766
Short name T135
Test name
Test status
Simulation time 4636440458649 ps
CPU time 4774.85 seconds
Started Aug 06 07:05:26 PM PDT 24
Finished Aug 06 08:25:02 PM PDT 24
Peak memory 196228 kb
Host smart-c8a44bb2-4675-476d-8684-6274e53057e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124874766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.3124874766
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.1913545945
Short name T73
Test name
Test status
Simulation time 14544206 ps
CPU time 0.59 seconds
Started Aug 06 07:04:51 PM PDT 24
Finished Aug 06 07:04:52 PM PDT 24
Peak memory 182836 kb
Host smart-90ed11a1-2072-432a-8896-9f6571839bcd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913545945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.1913545945
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.565244884
Short name T15
Test name
Test status
Simulation time 84136379 ps
CPU time 0.95 seconds
Started Aug 06 07:04:57 PM PDT 24
Finished Aug 06 07:04:58 PM PDT 24
Peak memory 215104 kb
Host smart-3e40180c-7880-4434-882a-776a92ddb111
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565244884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.565244884
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/169.rv_timer_random.1412396915
Short name T118
Test name
Test status
Simulation time 610484142142 ps
CPU time 502.42 seconds
Started Aug 06 07:06:22 PM PDT 24
Finished Aug 06 07:14:44 PM PDT 24
Peak memory 191628 kb
Host smart-cb6897a9-103f-4991-a0ac-5ce3953513ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412396915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.1412396915
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.2696830518
Short name T22
Test name
Test status
Simulation time 170543584048 ps
CPU time 564.2 seconds
Started Aug 06 07:06:04 PM PDT 24
Finished Aug 06 07:15:28 PM PDT 24
Peak memory 191632 kb
Host smart-45b5eebb-1cdd-4b65-a3f9-f3576d9d7ea2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696830518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.2696830518
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.1936230414
Short name T108
Test name
Test status
Simulation time 1430863798157 ps
CPU time 1558.58 seconds
Started Aug 06 07:06:05 PM PDT 24
Finished Aug 06 07:32:04 PM PDT 24
Peak memory 191632 kb
Host smart-a96979ef-dd03-49a1-8ae6-c2ee56c494ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936230414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.1936230414
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/190.rv_timer_random.1065646847
Short name T141
Test name
Test status
Simulation time 1153299684096 ps
CPU time 933.92 seconds
Started Aug 06 07:06:22 PM PDT 24
Finished Aug 06 07:21:56 PM PDT 24
Peak memory 191516 kb
Host smart-20ea975f-a92e-4bf7-89c0-34821d6d48c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065646847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.1065646847
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.2161723841
Short name T196
Test name
Test status
Simulation time 662183956004 ps
CPU time 1146.91 seconds
Started Aug 06 07:05:27 PM PDT 24
Finished Aug 06 07:24:34 PM PDT 24
Peak memory 191664 kb
Host smart-08522d41-5941-4083-b5ed-5d39c89fe4b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161723841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.2161723841
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/108.rv_timer_random.113239173
Short name T291
Test name
Test status
Simulation time 212692013200 ps
CPU time 350.84 seconds
Started Aug 06 07:06:05 PM PDT 24
Finished Aug 06 07:11:56 PM PDT 24
Peak memory 191640 kb
Host smart-77980b7b-7a59-4e3b-b140-33f84061b361
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113239173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.113239173
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.2902476482
Short name T6
Test name
Test status
Simulation time 226037627050 ps
CPU time 389.77 seconds
Started Aug 06 07:05:01 PM PDT 24
Finished Aug 06 07:11:31 PM PDT 24
Peak memory 191640 kb
Host smart-8a82e1f8-f137-46f1-aaba-a518be04451d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902476482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
2902476482
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/182.rv_timer_random.270523879
Short name T106
Test name
Test status
Simulation time 324102568765 ps
CPU time 430.28 seconds
Started Aug 06 07:06:21 PM PDT 24
Finished Aug 06 07:13:32 PM PDT 24
Peak memory 190916 kb
Host smart-47937097-3678-4e8a-8b98-e8ffc8dc7939
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270523879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.270523879
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random.4049491041
Short name T257
Test name
Test status
Simulation time 145368194448 ps
CPU time 203.16 seconds
Started Aug 06 07:05:06 PM PDT 24
Finished Aug 06 07:08:30 PM PDT 24
Peak memory 191524 kb
Host smart-607229e9-6dff-4c61-bf09-6b4bfc17c1fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049491041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.4049491041
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.3543692613
Short name T62
Test name
Test status
Simulation time 1614414520281 ps
CPU time 1157.74 seconds
Started Aug 06 07:05:11 PM PDT 24
Finished Aug 06 07:24:29 PM PDT 24
Peak memory 191548 kb
Host smart-fe2ac5a6-f38d-4f30-84b3-580b3855a674
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543692613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.3543692613
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/68.rv_timer_random.3596018594
Short name T345
Test name
Test status
Simulation time 114791998462 ps
CPU time 252.79 seconds
Started Aug 06 07:05:58 PM PDT 24
Finished Aug 06 07:10:11 PM PDT 24
Peak memory 191864 kb
Host smart-f8ee2b02-ef19-45ce-bc96-f0c7e0c2cded
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596018594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.3596018594
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.1664927596
Short name T150
Test name
Test status
Simulation time 199493437949 ps
CPU time 327.29 seconds
Started Aug 06 07:06:08 PM PDT 24
Finished Aug 06 07:11:36 PM PDT 24
Peak memory 191672 kb
Host smart-31e41936-0b1c-4133-a0a2-d09ac7170a4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664927596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.1664927596
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.3212731229
Short name T216
Test name
Test status
Simulation time 354099627048 ps
CPU time 985.01 seconds
Started Aug 06 07:06:29 PM PDT 24
Finished Aug 06 07:22:55 PM PDT 24
Peak memory 191608 kb
Host smart-fbd940e3-7f41-4044-bbca-7e7f636beedf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212731229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.3212731229
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random.3280134153
Short name T109
Test name
Test status
Simulation time 172520821826 ps
CPU time 480.55 seconds
Started Aug 06 07:05:05 PM PDT 24
Finished Aug 06 07:13:11 PM PDT 24
Peak memory 191640 kb
Host smart-ede2a89a-77a7-4a24-b29c-28a3ac385bab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280134153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.3280134153
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.1455402773
Short name T68
Test name
Test status
Simulation time 50774154914 ps
CPU time 25.69 seconds
Started Aug 06 07:05:26 PM PDT 24
Finished Aug 06 07:05:52 PM PDT 24
Peak memory 183336 kb
Host smart-2ae59815-3073-42a7-bcd1-7f45735f4669
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455402773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.1455402773
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/63.rv_timer_random.235248239
Short name T145
Test name
Test status
Simulation time 266751183778 ps
CPU time 491.51 seconds
Started Aug 06 07:05:59 PM PDT 24
Finished Aug 06 07:14:11 PM PDT 24
Peak memory 191624 kb
Host smart-9b1d5966-22e3-43c1-a41a-f1e9ce0530d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235248239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.235248239
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.1149273541
Short name T174
Test name
Test status
Simulation time 137149683357 ps
CPU time 375.87 seconds
Started Aug 06 07:06:08 PM PDT 24
Finished Aug 06 07:12:24 PM PDT 24
Peak memory 191680 kb
Host smart-16a33b6b-1aa9-4713-8636-4f3a96a38d91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149273541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.1149273541
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.2804423197
Short name T152
Test name
Test status
Simulation time 886297166651 ps
CPU time 1051.23 seconds
Started Aug 06 07:05:08 PM PDT 24
Finished Aug 06 07:22:39 PM PDT 24
Peak memory 196028 kb
Host smart-44c64a91-aa87-4f7d-8fd7-27afe08b222a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804423197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.2804423197
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.3220603494
Short name T133
Test name
Test status
Simulation time 955198883231 ps
CPU time 496.07 seconds
Started Aug 06 07:05:26 PM PDT 24
Finished Aug 06 07:13:42 PM PDT 24
Peak memory 191640 kb
Host smart-27eed9eb-e316-4113-8ba0-17bb7653ab4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220603494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.3220603494
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/64.rv_timer_random.1372407788
Short name T24
Test name
Test status
Simulation time 639135049337 ps
CPU time 257.24 seconds
Started Aug 06 07:05:57 PM PDT 24
Finished Aug 06 07:10:14 PM PDT 24
Peak memory 191648 kb
Host smart-eef27e2a-7524-4257-9d01-eaa8ade6a02e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372407788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.1372407788
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/90.rv_timer_random.3730998260
Short name T9
Test name
Test status
Simulation time 193867267652 ps
CPU time 172.92 seconds
Started Aug 06 07:05:57 PM PDT 24
Finished Aug 06 07:08:50 PM PDT 24
Peak memory 195232 kb
Host smart-5316134b-2ff2-48b4-8e0b-b180cd51ece2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730998260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.3730998260
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random.3603198346
Short name T204
Test name
Test status
Simulation time 148273520243 ps
CPU time 302.01 seconds
Started Aug 06 07:05:01 PM PDT 24
Finished Aug 06 07:10:04 PM PDT 24
Peak memory 191684 kb
Host smart-0c386172-a933-4f1d-b821-cd09a18bbec6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603198346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.3603198346
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.1138320040
Short name T56
Test name
Test status
Simulation time 368824010437 ps
CPU time 598.06 seconds
Started Aug 06 07:04:57 PM PDT 24
Finished Aug 06 07:14:56 PM PDT 24
Peak memory 196172 kb
Host smart-ae89ea98-8583-48cf-9ffd-7d33c488461b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138320040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
1138320040
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/119.rv_timer_random.3930904188
Short name T251
Test name
Test status
Simulation time 251495097011 ps
CPU time 171.37 seconds
Started Aug 06 07:06:05 PM PDT 24
Finished Aug 06 07:08:56 PM PDT 24
Peak memory 191616 kb
Host smart-5d233c64-43fc-4644-9294-9fd5c606395e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930904188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.3930904188
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random.2904499228
Short name T331
Test name
Test status
Simulation time 165661085874 ps
CPU time 436.75 seconds
Started Aug 06 07:05:00 PM PDT 24
Finished Aug 06 07:12:17 PM PDT 24
Peak memory 191652 kb
Host smart-9b07e088-7811-432f-89fa-affc6a8b62e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904499228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.2904499228
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.3499187202
Short name T172
Test name
Test status
Simulation time 355960468325 ps
CPU time 146.53 seconds
Started Aug 06 07:06:28 PM PDT 24
Finished Aug 06 07:08:54 PM PDT 24
Peak memory 195240 kb
Host smart-95aae7a3-94fe-4e0a-a8af-c33023ee02f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499187202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.3499187202
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random.2498803796
Short name T237
Test name
Test status
Simulation time 755426711995 ps
CPU time 2575.9 seconds
Started Aug 06 07:05:25 PM PDT 24
Finished Aug 06 07:48:22 PM PDT 24
Peak memory 191692 kb
Host smart-77dbd3f1-6461-40af-965f-fd6e2172f842
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498803796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.2498803796
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.3928375762
Short name T194
Test name
Test status
Simulation time 503744732469 ps
CPU time 252.25 seconds
Started Aug 06 07:04:59 PM PDT 24
Finished Aug 06 07:09:11 PM PDT 24
Peak memory 183412 kb
Host smart-fdce2a16-8f5b-4a04-8aa9-2b5914b37f5d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928375762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.3928375762
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/156.rv_timer_random.2234617797
Short name T23
Test name
Test status
Simulation time 708296355753 ps
CPU time 1967.2 seconds
Started Aug 06 07:06:15 PM PDT 24
Finished Aug 06 07:39:03 PM PDT 24
Peak memory 191628 kb
Host smart-6c901a18-0e3e-4ebc-8e19-de234f714a60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234617797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.2234617797
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.1224360705
Short name T198
Test name
Test status
Simulation time 288373862053 ps
CPU time 600.64 seconds
Started Aug 06 07:06:23 PM PDT 24
Finished Aug 06 07:16:24 PM PDT 24
Peak memory 191640 kb
Host smart-a0bcf329-5b64-4cc2-b28d-aa8e6452cf3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224360705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.1224360705
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.4294378732
Short name T160
Test name
Test status
Simulation time 1285683773826 ps
CPU time 1110.26 seconds
Started Aug 06 07:05:08 PM PDT 24
Finished Aug 06 07:23:38 PM PDT 24
Peak memory 183432 kb
Host smart-fd6473f1-a413-4ce1-8f82-b3be627f4048
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294378732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.4294378732
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_random.3039151347
Short name T208
Test name
Test status
Simulation time 1019852043324 ps
CPU time 376.23 seconds
Started Aug 06 07:05:02 PM PDT 24
Finished Aug 06 07:11:18 PM PDT 24
Peak memory 191664 kb
Host smart-5bd2b55c-69cf-4bff-97f5-c96445988a25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039151347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.3039151347
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.886357292
Short name T246
Test name
Test status
Simulation time 656010041781 ps
CPU time 321.2 seconds
Started Aug 06 07:06:23 PM PDT 24
Finished Aug 06 07:11:44 PM PDT 24
Peak memory 191624 kb
Host smart-a7e77abd-f915-43f0-8a07-a157fae16e6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886357292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.886357292
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.1166563639
Short name T298
Test name
Test status
Simulation time 57836309439 ps
CPU time 321.54 seconds
Started Aug 06 07:05:01 PM PDT 24
Finished Aug 06 07:10:22 PM PDT 24
Peak memory 191620 kb
Host smart-33be6596-95ab-4ae7-a163-63d7cd2b9229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166563639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.1166563639
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.2661505636
Short name T286
Test name
Test status
Simulation time 318565680757 ps
CPU time 2080.87 seconds
Started Aug 06 07:05:15 PM PDT 24
Finished Aug 06 07:39:56 PM PDT 24
Peak memory 195844 kb
Host smart-90fade93-5abe-4176-a35a-eca5086ef1bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661505636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.2661505636
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.3315796875
Short name T179
Test name
Test status
Simulation time 322538781668 ps
CPU time 485.2 seconds
Started Aug 06 07:04:59 PM PDT 24
Finished Aug 06 07:13:05 PM PDT 24
Peak memory 183452 kb
Host smart-26d18ea6-4c75-42fc-b494-d48851d54bc6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315796875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.3315796875
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/59.rv_timer_random.3742436784
Short name T339
Test name
Test status
Simulation time 833228211560 ps
CPU time 1362.18 seconds
Started Aug 06 07:06:04 PM PDT 24
Finished Aug 06 07:28:46 PM PDT 24
Peak memory 191596 kb
Host smart-5e17b662-3077-448d-8e54-b4badc4902f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742436784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.3742436784
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.2898664335
Short name T197
Test name
Test status
Simulation time 590927330311 ps
CPU time 280.48 seconds
Started Aug 06 07:06:00 PM PDT 24
Finished Aug 06 07:10:41 PM PDT 24
Peak memory 191672 kb
Host smart-41da3d74-b33d-4efc-b694-b7b86178dfda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898664335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.2898664335
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random.3187054636
Short name T105
Test name
Test status
Simulation time 371686251495 ps
CPU time 317.48 seconds
Started Aug 06 07:04:57 PM PDT 24
Finished Aug 06 07:10:15 PM PDT 24
Peak memory 191672 kb
Host smart-bd082ba1-599b-455a-a8a6-d8c1a3a9170d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187054636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.3187054636
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.245314345
Short name T95
Test name
Test status
Simulation time 221177548 ps
CPU time 1.34 seconds
Started Aug 06 07:04:53 PM PDT 24
Finished Aug 06 07:04:54 PM PDT 24
Peak memory 195600 kb
Host smart-155f06e3-45e2-4bb8-ba5e-443d1061df01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245314345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_in
tg_err.245314345
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.2790587026
Short name T211
Test name
Test status
Simulation time 75516802043 ps
CPU time 54.49 seconds
Started Aug 06 07:04:59 PM PDT 24
Finished Aug 06 07:05:54 PM PDT 24
Peak memory 195260 kb
Host smart-85f7ef77-5b2e-43a5-8486-3eaf16ccef47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790587026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.2790587026
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/100.rv_timer_random.1751539626
Short name T287
Test name
Test status
Simulation time 175803933132 ps
CPU time 545.66 seconds
Started Aug 06 07:06:04 PM PDT 24
Finished Aug 06 07:15:10 PM PDT 24
Peak memory 191692 kb
Host smart-eb0ecb52-e6e4-4b35-90d0-3f776f704486
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751539626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.1751539626
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.323091793
Short name T202
Test name
Test status
Simulation time 58363114605 ps
CPU time 78.03 seconds
Started Aug 06 07:06:01 PM PDT 24
Finished Aug 06 07:07:19 PM PDT 24
Peak memory 191632 kb
Host smart-ba2d1fcf-ab93-4d65-aedc-a2d20a038c16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323091793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.323091793
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.3485696905
Short name T66
Test name
Test status
Simulation time 355752128123 ps
CPU time 502.11 seconds
Started Aug 06 07:06:06 PM PDT 24
Finished Aug 06 07:14:28 PM PDT 24
Peak memory 191620 kb
Host smart-a6950100-017e-4a4f-b299-08f624994d38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485696905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.3485696905
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.1785378673
Short name T256
Test name
Test status
Simulation time 171860036399 ps
CPU time 137.04 seconds
Started Aug 06 07:06:03 PM PDT 24
Finished Aug 06 07:08:21 PM PDT 24
Peak memory 191688 kb
Host smart-423a1b51-8d02-43c4-aecb-375873a87f1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785378673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.1785378673
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.1617099744
Short name T285
Test name
Test status
Simulation time 5972656126974 ps
CPU time 2412.03 seconds
Started Aug 06 07:05:06 PM PDT 24
Finished Aug 06 07:45:19 PM PDT 24
Peak memory 183328 kb
Host smart-81c9e5b3-aeac-4273-ba2e-d99ec0079836
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617099744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.1617099744
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/161.rv_timer_random.3885438624
Short name T164
Test name
Test status
Simulation time 114656889025 ps
CPU time 315.21 seconds
Started Aug 06 07:06:16 PM PDT 24
Finished Aug 06 07:11:31 PM PDT 24
Peak memory 191648 kb
Host smart-c4425ab2-f1da-4176-9a43-d20d3b992995
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885438624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.3885438624
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.664704027
Short name T281
Test name
Test status
Simulation time 320522712148 ps
CPU time 637.44 seconds
Started Aug 06 07:06:21 PM PDT 24
Finished Aug 06 07:16:59 PM PDT 24
Peak memory 183524 kb
Host smart-8cb6af36-18b6-46c2-b69c-5941b4a11234
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664704027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.664704027
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.803150750
Short name T232
Test name
Test status
Simulation time 478026714029 ps
CPU time 669.16 seconds
Started Aug 06 07:06:15 PM PDT 24
Finished Aug 06 07:17:25 PM PDT 24
Peak memory 191724 kb
Host smart-35968952-281e-4210-9e38-85f48a30ceef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803150750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.803150750
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.690066186
Short name T171
Test name
Test status
Simulation time 50970978778 ps
CPU time 79.74 seconds
Started Aug 06 07:06:22 PM PDT 24
Finished Aug 06 07:07:42 PM PDT 24
Peak memory 191664 kb
Host smart-df069848-2e9b-42d4-a14f-08e9dce31523
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690066186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.690066186
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.1477710037
Short name T101
Test name
Test status
Simulation time 79517921597 ps
CPU time 443.06 seconds
Started Aug 06 07:06:22 PM PDT 24
Finished Aug 06 07:13:45 PM PDT 24
Peak memory 191616 kb
Host smart-85ae8b9d-0fdb-4f61-99d4-2bf9089c7126
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477710037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.1477710037
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.1011317338
Short name T272
Test name
Test status
Simulation time 162815333639 ps
CPU time 123.3 seconds
Started Aug 06 07:06:26 PM PDT 24
Finished Aug 06 07:08:29 PM PDT 24
Peak memory 191540 kb
Host smart-a43f1e2b-0e26-4d67-ba73-0ab8387e1b02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011317338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.1011317338
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.3947652124
Short name T268
Test name
Test status
Simulation time 1327016076416 ps
CPU time 1329.57 seconds
Started Aug 06 07:06:26 PM PDT 24
Finished Aug 06 07:28:36 PM PDT 24
Peak memory 191540 kb
Host smart-2fa598ba-6efc-4a91-8b67-4a14162b2c5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947652124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.3947652124
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.1304347419
Short name T143
Test name
Test status
Simulation time 378786016810 ps
CPU time 261.65 seconds
Started Aug 06 07:05:03 PM PDT 24
Finished Aug 06 07:09:25 PM PDT 24
Peak memory 191868 kb
Host smart-167e6191-78c8-482a-8321-a24090937753
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304347419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
1304347419
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.144135759
Short name T224
Test name
Test status
Simulation time 8586940103 ps
CPU time 13.9 seconds
Started Aug 06 07:05:01 PM PDT 24
Finished Aug 06 07:05:15 PM PDT 24
Peak memory 183440 kb
Host smart-d1235d07-b426-4650-8176-a2d26d16bb35
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144135759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.rv_timer_cfg_update_on_fly.144135759
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.585670326
Short name T290
Test name
Test status
Simulation time 159925376046 ps
CPU time 77.15 seconds
Started Aug 06 07:05:14 PM PDT 24
Finished Aug 06 07:06:31 PM PDT 24
Peak memory 194872 kb
Host smart-b4406121-1ca4-4308-9f17-96117339dbd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585670326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.585670326
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/66.rv_timer_random.4256460152
Short name T344
Test name
Test status
Simulation time 85861785775 ps
CPU time 600.18 seconds
Started Aug 06 07:06:02 PM PDT 24
Finished Aug 06 07:16:03 PM PDT 24
Peak memory 191604 kb
Host smart-c2e2cc2e-b1fd-4971-b39e-4181d0a22c53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256460152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.4256460152
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.1525695286
Short name T1
Test name
Test status
Simulation time 917155901560 ps
CPU time 509.17 seconds
Started Aug 06 07:04:57 PM PDT 24
Finished Aug 06 07:13:27 PM PDT 24
Peak memory 183404 kb
Host smart-fc7a2e06-de84-416b-9e38-ed61de90879c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525695286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.1525695286
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/91.rv_timer_random.2979871619
Short name T167
Test name
Test status
Simulation time 178565466183 ps
CPU time 805.8 seconds
Started Aug 06 07:06:04 PM PDT 24
Finished Aug 06 07:19:30 PM PDT 24
Peak memory 191704 kb
Host smart-6cb36519-e9f5-4a23-8f34-66d9b2a710d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979871619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.2979871619
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.3446722349
Short name T4
Test name
Test status
Simulation time 150493817489 ps
CPU time 549.86 seconds
Started Aug 06 07:06:04 PM PDT 24
Finished Aug 06 07:15:14 PM PDT 24
Peak memory 191696 kb
Host smart-a74a0583-50a6-423d-b5e9-32b668a8ea11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446722349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.3446722349
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.4023859608
Short name T293
Test name
Test status
Simulation time 358420430463 ps
CPU time 325.7 seconds
Started Aug 06 07:05:04 PM PDT 24
Finished Aug 06 07:10:30 PM PDT 24
Peak memory 183412 kb
Host smart-2fb9a0c3-0415-4115-92e2-6af8b19ea9bf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023859608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.4023859608
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.3015655619
Short name T258
Test name
Test status
Simulation time 375941611815 ps
CPU time 661.79 seconds
Started Aug 06 07:04:58 PM PDT 24
Finished Aug 06 07:16:00 PM PDT 24
Peak memory 183412 kb
Host smart-995fa07f-d6a5-42d2-9d26-9ff7188f9f1c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015655619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.3015655619
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_random.2142501134
Short name T223
Test name
Test status
Simulation time 400581849552 ps
CPU time 178.67 seconds
Started Aug 06 07:05:02 PM PDT 24
Finished Aug 06 07:08:01 PM PDT 24
Peak memory 194156 kb
Host smart-7d0dc104-f27f-4074-bff4-6336d88f4454
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142501134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.2142501134
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.175976616
Short name T264
Test name
Test status
Simulation time 48904060100 ps
CPU time 85.49 seconds
Started Aug 06 07:06:05 PM PDT 24
Finished Aug 06 07:07:31 PM PDT 24
Peak memory 191616 kb
Host smart-09b7f8b6-bef7-41a8-b2ff-5cf801b3b970
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175976616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.175976616
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.377167796
Short name T125
Test name
Test status
Simulation time 39808794973 ps
CPU time 1210.85 seconds
Started Aug 06 07:04:54 PM PDT 24
Finished Aug 06 07:25:05 PM PDT 24
Peak memory 183428 kb
Host smart-eb837120-6d71-4dd2-80a8-c64ebfa9987e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377167796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.377167796
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/111.rv_timer_random.1646010952
Short name T266
Test name
Test status
Simulation time 28956988858 ps
CPU time 48.71 seconds
Started Aug 06 07:06:05 PM PDT 24
Finished Aug 06 07:06:54 PM PDT 24
Peak memory 191616 kb
Host smart-4d0a33ef-fac8-435c-a2cd-b92e8e34169f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646010952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.1646010952
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.1293357657
Short name T330
Test name
Test status
Simulation time 129987528991 ps
CPU time 674.22 seconds
Started Aug 06 07:06:05 PM PDT 24
Finished Aug 06 07:17:20 PM PDT 24
Peak memory 194372 kb
Host smart-42743c07-e859-4d26-a8b6-9c2f9a527698
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293357657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.1293357657
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.1511944819
Short name T229
Test name
Test status
Simulation time 18626622839 ps
CPU time 55.4 seconds
Started Aug 06 07:06:04 PM PDT 24
Finished Aug 06 07:07:00 PM PDT 24
Peak memory 191628 kb
Host smart-b59e5cdd-95ca-4556-a30d-bee6fbb10b21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511944819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.1511944819
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.2266156257
Short name T138
Test name
Test status
Simulation time 450635053228 ps
CPU time 226.92 seconds
Started Aug 06 07:05:01 PM PDT 24
Finished Aug 06 07:08:48 PM PDT 24
Peak memory 183464 kb
Host smart-a3700e21-b48f-48b9-87fe-1961e5301862
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266156257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.2266156257
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_random.354720993
Short name T316
Test name
Test status
Simulation time 103851953696 ps
CPU time 120.04 seconds
Started Aug 06 07:04:57 PM PDT 24
Finished Aug 06 07:06:58 PM PDT 24
Peak memory 191688 kb
Host smart-53d36bf3-55e1-4cb4-b07f-dc75836ce9e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354720993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.354720993
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.48802979
Short name T408
Test name
Test status
Simulation time 46337781449 ps
CPU time 71.01 seconds
Started Aug 06 07:06:01 PM PDT 24
Finished Aug 06 07:07:12 PM PDT 24
Peak memory 191692 kb
Host smart-a9ec109c-373c-468b-ae4b-8ba251118d81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48802979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.48802979
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.2984698091
Short name T222
Test name
Test status
Simulation time 578405323766 ps
CPU time 572.34 seconds
Started Aug 06 07:06:23 PM PDT 24
Finished Aug 06 07:15:56 PM PDT 24
Peak memory 191616 kb
Host smart-4d02b719-cbca-44e2-85e7-b50b521b6afe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984698091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.2984698091
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random.1345507495
Short name T121
Test name
Test status
Simulation time 93520800874 ps
CPU time 126.92 seconds
Started Aug 06 07:05:06 PM PDT 24
Finished Aug 06 07:07:13 PM PDT 24
Peak memory 192840 kb
Host smart-ebbe931f-8636-43d9-8204-7a92f4b11756
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345507495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.1345507495
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.1685619315
Short name T134
Test name
Test status
Simulation time 842371528347 ps
CPU time 1866.97 seconds
Started Aug 06 07:05:07 PM PDT 24
Finished Aug 06 07:36:14 PM PDT 24
Peak memory 191532 kb
Host smart-430abfa3-7e16-4466-be6b-aa28032a7dce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685619315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.1685619315
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.1377999784
Short name T297
Test name
Test status
Simulation time 79400578320 ps
CPU time 28.75 seconds
Started Aug 06 07:05:14 PM PDT 24
Finished Aug 06 07:05:43 PM PDT 24
Peak memory 183460 kb
Host smart-e7e798fe-81d4-4e79-905f-0cb192d1ab5d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377999784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.1377999784
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_random.1294629929
Short name T302
Test name
Test status
Simulation time 135738744726 ps
CPU time 245.91 seconds
Started Aug 06 07:05:15 PM PDT 24
Finished Aug 06 07:09:21 PM PDT 24
Peak memory 191628 kb
Host smart-0941986e-4dae-42b2-95b8-0900092e2697
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294629929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.1294629929
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.808834506
Short name T136
Test name
Test status
Simulation time 243742934900 ps
CPU time 88.64 seconds
Started Aug 06 07:05:25 PM PDT 24
Finished Aug 06 07:06:54 PM PDT 24
Peak memory 183420 kb
Host smart-45bfb36c-f344-4aa0-9b35-b845843936b9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808834506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.rv_timer_cfg_update_on_fly.808834506
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_random.3012185887
Short name T190
Test name
Test status
Simulation time 46645730735 ps
CPU time 41.34 seconds
Started Aug 06 07:05:13 PM PDT 24
Finished Aug 06 07:05:54 PM PDT 24
Peak memory 183416 kb
Host smart-7e634ce7-dd01-4c7b-a62d-e0a6f681f727
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012185887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.3012185887
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.1793301326
Short name T219
Test name
Test status
Simulation time 131656688483 ps
CPU time 125.5 seconds
Started Aug 06 07:04:52 PM PDT 24
Finished Aug 06 07:06:58 PM PDT 24
Peak memory 194844 kb
Host smart-e37c2c53-45a0-4e4d-9d7c-b6925e615ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793301326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.1793301326
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.3752299401
Short name T253
Test name
Test status
Simulation time 1277606759995 ps
CPU time 1096.79 seconds
Started Aug 06 07:05:00 PM PDT 24
Finished Aug 06 07:23:17 PM PDT 24
Peak memory 191680 kb
Host smart-f40071c3-8023-4f51-88a6-69ec893dbbc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752299401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
3752299401
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/67.rv_timer_random.1108574359
Short name T273
Test name
Test status
Simulation time 179462760975 ps
CPU time 157.29 seconds
Started Aug 06 07:06:03 PM PDT 24
Finished Aug 06 07:08:40 PM PDT 24
Peak memory 191540 kb
Host smart-7af4be8f-e77d-4540-b65e-edcebacc34d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108574359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.1108574359
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.4046678286
Short name T154
Test name
Test status
Simulation time 115830331562 ps
CPU time 173.36 seconds
Started Aug 06 07:04:57 PM PDT 24
Finished Aug 06 07:07:50 PM PDT 24
Peak memory 183428 kb
Host smart-b14321b6-45ed-4039-9c0d-6fa32c1da11f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046678286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.4046678286
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3142999592
Short name T72
Test name
Test status
Simulation time 104940385 ps
CPU time 0.79 seconds
Started Aug 06 07:04:06 PM PDT 24
Finished Aug 06 07:04:07 PM PDT 24
Peak memory 192764 kb
Host smart-13fa3951-d887-4707-8dd5-141275c9ae33
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142999592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.3142999592
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.2832916936
Short name T82
Test name
Test status
Simulation time 198188730 ps
CPU time 2.35 seconds
Started Aug 06 07:04:12 PM PDT 24
Finished Aug 06 07:04:14 PM PDT 24
Peak memory 191324 kb
Host smart-74872786-2c0c-437f-942e-03695fd0a6c7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832916936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.2832916936
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.2231848088
Short name T489
Test name
Test status
Simulation time 27121582 ps
CPU time 0.57 seconds
Started Aug 06 07:04:07 PM PDT 24
Finished Aug 06 07:04:08 PM PDT 24
Peak memory 182948 kb
Host smart-9ddde576-d169-466f-9089-89bf43c8590c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231848088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.2231848088
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.1413149564
Short name T523
Test name
Test status
Simulation time 259128921 ps
CPU time 0.74 seconds
Started Aug 06 07:04:20 PM PDT 24
Finished Aug 06 07:04:21 PM PDT 24
Peak memory 195224 kb
Host smart-fe7ccdf2-1dbb-4475-b286-82bfe3cde989
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413149564 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.1413149564
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.2810834286
Short name T495
Test name
Test status
Simulation time 15865781 ps
CPU time 0.52 seconds
Started Aug 06 07:04:17 PM PDT 24
Finished Aug 06 07:04:18 PM PDT 24
Peak memory 182740 kb
Host smart-bbefa159-f1c0-4d9c-8b04-a514c8ba5cba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810834286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.2810834286
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.3506195543
Short name T545
Test name
Test status
Simulation time 14452067 ps
CPU time 0.58 seconds
Started Aug 06 07:04:08 PM PDT 24
Finished Aug 06 07:04:09 PM PDT 24
Peak memory 182700 kb
Host smart-84e44638-6db9-4612-b496-c074a32e83ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506195543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.3506195543
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.1337109388
Short name T530
Test name
Test status
Simulation time 104015508 ps
CPU time 1.92 seconds
Started Aug 06 07:04:08 PM PDT 24
Finished Aug 06 07:04:10 PM PDT 24
Peak memory 197608 kb
Host smart-178877d6-5873-45ed-839e-878b9441d954
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337109388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.1337109388
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.3083385655
Short name T557
Test name
Test status
Simulation time 47711428 ps
CPU time 0.9 seconds
Started Aug 06 07:04:09 PM PDT 24
Finished Aug 06 07:04:10 PM PDT 24
Peak memory 193672 kb
Host smart-3a43ede9-3b7b-47da-ad94-a4faf2764e62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083385655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.3083385655
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.820345658
Short name T477
Test name
Test status
Simulation time 140805023 ps
CPU time 0.79 seconds
Started Aug 06 07:04:12 PM PDT 24
Finished Aug 06 07:04:13 PM PDT 24
Peak memory 192188 kb
Host smart-5cd1d4fd-316b-449c-a025-8e5e714e8026
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820345658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alias
ing.820345658
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.101589318
Short name T43
Test name
Test status
Simulation time 1694335023 ps
CPU time 3.44 seconds
Started Aug 06 07:04:24 PM PDT 24
Finished Aug 06 07:04:28 PM PDT 24
Peak memory 190488 kb
Host smart-e616f0e6-0a26-4b09-a48c-9fe633a8a41c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101589318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_b
ash.101589318
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.2786592573
Short name T75
Test name
Test status
Simulation time 26177057 ps
CPU time 0.58 seconds
Started Aug 06 07:04:18 PM PDT 24
Finished Aug 06 07:04:19 PM PDT 24
Peak memory 182936 kb
Host smart-55c9e14b-edff-4e4d-a85f-b214a8eec733
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786592573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.2786592573
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.2601839978
Short name T465
Test name
Test status
Simulation time 65906409 ps
CPU time 1.53 seconds
Started Aug 06 07:04:18 PM PDT 24
Finished Aug 06 07:04:20 PM PDT 24
Peak memory 197768 kb
Host smart-46b0c952-ff51-4eae-bc8a-15389cc9ccac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601839978 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.2601839978
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.3654648834
Short name T80
Test name
Test status
Simulation time 12665852 ps
CPU time 0.6 seconds
Started Aug 06 07:04:09 PM PDT 24
Finished Aug 06 07:04:10 PM PDT 24
Peak memory 182920 kb
Host smart-831c022d-ee7a-40f0-b9f5-39ca75465667
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654648834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.3654648834
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.989675351
Short name T532
Test name
Test status
Simulation time 41171716 ps
CPU time 0.55 seconds
Started Aug 06 07:04:18 PM PDT 24
Finished Aug 06 07:04:19 PM PDT 24
Peak memory 182744 kb
Host smart-b0a7a020-3533-4431-b395-9de920b33db8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989675351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.989675351
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.2448641450
Short name T540
Test name
Test status
Simulation time 19349512 ps
CPU time 0.79 seconds
Started Aug 06 07:04:11 PM PDT 24
Finished Aug 06 07:04:12 PM PDT 24
Peak memory 193784 kb
Host smart-e0034241-6746-4e13-b6da-d73bba1f83c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448641450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.2448641450
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.2687367297
Short name T520
Test name
Test status
Simulation time 149675493 ps
CPU time 0.87 seconds
Started Aug 06 07:04:14 PM PDT 24
Finished Aug 06 07:04:15 PM PDT 24
Peak memory 195376 kb
Host smart-dbfedeec-3870-4071-b356-c704288ecc46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687367297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.2687367297
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3311718325
Short name T561
Test name
Test status
Simulation time 328216298 ps
CPU time 1.07 seconds
Started Aug 06 07:04:12 PM PDT 24
Finished Aug 06 07:04:13 PM PDT 24
Peak memory 195448 kb
Host smart-d4a2d24b-c749-43a9-9d42-89f14ea5ba1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311718325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.3311718325
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.3899957617
Short name T472
Test name
Test status
Simulation time 121859013 ps
CPU time 0.9 seconds
Started Aug 06 07:04:49 PM PDT 24
Finished Aug 06 07:04:50 PM PDT 24
Peak memory 197072 kb
Host smart-2d22a31d-a21a-4d82-b424-4bf7b1aabd94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899957617 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.3899957617
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.1972941094
Short name T566
Test name
Test status
Simulation time 139564559 ps
CPU time 0.59 seconds
Started Aug 06 07:04:51 PM PDT 24
Finished Aug 06 07:04:51 PM PDT 24
Peak memory 182876 kb
Host smart-81dc5ce9-dda1-49d0-a020-3f9c8d4513a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972941094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.1972941094
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.3816867153
Short name T458
Test name
Test status
Simulation time 13903304 ps
CPU time 0.54 seconds
Started Aug 06 07:04:52 PM PDT 24
Finished Aug 06 07:04:53 PM PDT 24
Peak memory 182248 kb
Host smart-b3b68f6e-7179-405e-86b5-4eab682199c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816867153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.3816867153
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.344951961
Short name T44
Test name
Test status
Simulation time 103065065 ps
CPU time 0.76 seconds
Started Aug 06 07:04:52 PM PDT 24
Finished Aug 06 07:04:53 PM PDT 24
Peak memory 191688 kb
Host smart-e6ae56ed-4694-4a6a-bfe0-96c9905dd46c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344951961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_ti
mer_same_csr_outstanding.344951961
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.3962326543
Short name T479
Test name
Test status
Simulation time 107780113 ps
CPU time 2.23 seconds
Started Aug 06 07:04:49 PM PDT 24
Finished Aug 06 07:04:51 PM PDT 24
Peak memory 197676 kb
Host smart-31653773-5cb4-4faf-ba4b-b529b572ba49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962326543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.3962326543
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.2659912117
Short name T29
Test name
Test status
Simulation time 52955195 ps
CPU time 0.85 seconds
Started Aug 06 07:04:52 PM PDT 24
Finished Aug 06 07:04:53 PM PDT 24
Peak memory 192980 kb
Host smart-453fd334-961f-48f8-b4ce-bd8facbfc4b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659912117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.2659912117
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.880862875
Short name T512
Test name
Test status
Simulation time 118194745 ps
CPU time 1.42 seconds
Started Aug 06 07:04:53 PM PDT 24
Finished Aug 06 07:04:55 PM PDT 24
Peak memory 197672 kb
Host smart-10fe1d15-1263-42c9-8232-0a3990e29f7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880862875 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.880862875
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.1064078658
Short name T76
Test name
Test status
Simulation time 61340604 ps
CPU time 0.58 seconds
Started Aug 06 07:04:51 PM PDT 24
Finished Aug 06 07:04:52 PM PDT 24
Peak memory 182616 kb
Host smart-705ebff0-868b-4af2-be20-0f30133e5238
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064078658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.1064078658
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.2170242049
Short name T581
Test name
Test status
Simulation time 167542487 ps
CPU time 0.69 seconds
Started Aug 06 07:04:51 PM PDT 24
Finished Aug 06 07:04:51 PM PDT 24
Peak memory 182728 kb
Host smart-d73dc66c-636d-4b26-a661-c90647953b00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170242049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.2170242049
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3176887770
Short name T550
Test name
Test status
Simulation time 16598098 ps
CPU time 0.76 seconds
Started Aug 06 07:04:50 PM PDT 24
Finished Aug 06 07:04:51 PM PDT 24
Peak memory 193644 kb
Host smart-ee778859-519d-4788-a25f-a7611b322d71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176887770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.3176887770
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.3740104968
Short name T505
Test name
Test status
Simulation time 74265140 ps
CPU time 1.52 seconds
Started Aug 06 07:04:52 PM PDT 24
Finished Aug 06 07:04:54 PM PDT 24
Peak memory 197668 kb
Host smart-b372ac2f-a188-4179-90dc-ddfc41dad0ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740104968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.3740104968
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.565865331
Short name T491
Test name
Test status
Simulation time 105845898 ps
CPU time 0.9 seconds
Started Aug 06 07:04:51 PM PDT 24
Finished Aug 06 07:04:52 PM PDT 24
Peak memory 194048 kb
Host smart-841f7000-a226-45a9-9e56-0eb3d6e17783
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565865331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_in
tg_err.565865331
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.4249121745
Short name T517
Test name
Test status
Simulation time 427768850 ps
CPU time 0.73 seconds
Started Aug 06 07:04:50 PM PDT 24
Finished Aug 06 07:04:51 PM PDT 24
Peak memory 195396 kb
Host smart-5a786feb-e38f-4c1a-a4f5-39b9c84d1412
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249121745 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.4249121745
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.597379841
Short name T478
Test name
Test status
Simulation time 15388079 ps
CPU time 0.57 seconds
Started Aug 06 07:04:49 PM PDT 24
Finished Aug 06 07:04:50 PM PDT 24
Peak memory 182940 kb
Host smart-3c91f6a7-49cd-4743-be60-b90ed3b1ef5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597379841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.597379841
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.1251599231
Short name T469
Test name
Test status
Simulation time 37936088 ps
CPU time 0.56 seconds
Started Aug 06 07:04:51 PM PDT 24
Finished Aug 06 07:04:51 PM PDT 24
Peak memory 182772 kb
Host smart-be8fef22-0fa4-47a6-9828-83e00f295a41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251599231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.1251599231
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3084513537
Short name T565
Test name
Test status
Simulation time 131592061 ps
CPU time 0.61 seconds
Started Aug 06 07:04:50 PM PDT 24
Finished Aug 06 07:04:50 PM PDT 24
Peak memory 191628 kb
Host smart-47967f82-6c68-4484-83a0-4588fe7ecafe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084513537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.3084513537
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.1797761012
Short name T497
Test name
Test status
Simulation time 97378488 ps
CPU time 2.02 seconds
Started Aug 06 07:04:55 PM PDT 24
Finished Aug 06 07:04:57 PM PDT 24
Peak memory 197504 kb
Host smart-34d92e61-7608-4e02-88b9-8895e576ed55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797761012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.1797761012
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.502071948
Short name T507
Test name
Test status
Simulation time 565888355 ps
CPU time 0.82 seconds
Started Aug 06 07:04:49 PM PDT 24
Finished Aug 06 07:04:50 PM PDT 24
Peak memory 183316 kb
Host smart-6ce06b39-0d5c-41ec-a6c4-271f6abbc306
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502071948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_in
tg_err.502071948
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2979811939
Short name T46
Test name
Test status
Simulation time 30131037 ps
CPU time 0.82 seconds
Started Aug 06 07:04:49 PM PDT 24
Finished Aug 06 07:04:50 PM PDT 24
Peak memory 195468 kb
Host smart-0f4a14bb-e167-49d7-b41c-4f1a9b58b87b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979811939 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.2979811939
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3468873721
Short name T504
Test name
Test status
Simulation time 19016347 ps
CPU time 0.57 seconds
Started Aug 06 07:04:49 PM PDT 24
Finished Aug 06 07:04:49 PM PDT 24
Peak memory 182860 kb
Host smart-82578b9b-83fe-4297-864a-e3d42f0ecd81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468873721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.3468873721
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.1038655781
Short name T471
Test name
Test status
Simulation time 192845912 ps
CPU time 0.55 seconds
Started Aug 06 07:04:49 PM PDT 24
Finished Aug 06 07:04:50 PM PDT 24
Peak memory 182816 kb
Host smart-686600fb-ffc2-462e-9c25-89c8b31a46ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038655781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.1038655781
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.2926069855
Short name T90
Test name
Test status
Simulation time 106808026 ps
CPU time 0.74 seconds
Started Aug 06 07:04:53 PM PDT 24
Finished Aug 06 07:04:54 PM PDT 24
Peak memory 191712 kb
Host smart-5cd6e5be-2738-4050-86d5-8be58c6c6db6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926069855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.2926069855
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.3606674578
Short name T496
Test name
Test status
Simulation time 54393629 ps
CPU time 1.86 seconds
Started Aug 06 07:04:50 PM PDT 24
Finished Aug 06 07:04:52 PM PDT 24
Peak memory 197712 kb
Host smart-dcacdaee-c25c-42cb-9c09-0f3ec471f1ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606674578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.3606674578
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.867791019
Short name T573
Test name
Test status
Simulation time 271553691 ps
CPU time 0.84 seconds
Started Aug 06 07:04:51 PM PDT 24
Finished Aug 06 07:04:52 PM PDT 24
Peak memory 183204 kb
Host smart-fe09c58e-b6d7-415b-8855-f65a396f7ea3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867791019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_in
tg_err.867791019
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.263092873
Short name T571
Test name
Test status
Simulation time 25140360 ps
CPU time 0.7 seconds
Started Aug 06 07:04:50 PM PDT 24
Finished Aug 06 07:04:51 PM PDT 24
Peak memory 194916 kb
Host smart-7c0ce65c-1ba4-4e66-b04c-de53c58c08a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263092873 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.263092873
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.120189198
Short name T531
Test name
Test status
Simulation time 28640953 ps
CPU time 0.56 seconds
Started Aug 06 07:04:51 PM PDT 24
Finished Aug 06 07:04:52 PM PDT 24
Peak memory 182688 kb
Host smart-a50d259d-0640-46ab-b5b1-df19038a8086
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120189198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.120189198
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.339754608
Short name T506
Test name
Test status
Simulation time 103864184 ps
CPU time 0.6 seconds
Started Aug 06 07:04:55 PM PDT 24
Finished Aug 06 07:04:55 PM PDT 24
Peak memory 191520 kb
Host smart-d6c4a24c-0146-4fb8-80bb-ce33f67fb274
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339754608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_ti
mer_same_csr_outstanding.339754608
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.3250089378
Short name T559
Test name
Test status
Simulation time 60312735 ps
CPU time 0.96 seconds
Started Aug 06 07:04:52 PM PDT 24
Finished Aug 06 07:04:53 PM PDT 24
Peak memory 197388 kb
Host smart-f4cedc9f-a4eb-48dc-9aee-8a453a62ceac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250089378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.3250089378
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.1329022465
Short name T93
Test name
Test status
Simulation time 69305947 ps
CPU time 1.13 seconds
Started Aug 06 07:04:50 PM PDT 24
Finished Aug 06 07:04:51 PM PDT 24
Peak memory 183588 kb
Host smart-6892a54b-47bd-4167-a5a5-1e6f23136016
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329022465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.1329022465
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.3946578259
Short name T47
Test name
Test status
Simulation time 127319563 ps
CPU time 0.79 seconds
Started Aug 06 07:04:51 PM PDT 24
Finished Aug 06 07:04:51 PM PDT 24
Peak memory 196208 kb
Host smart-d95428b1-1e6a-4119-b5a7-364ee28d025e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946578259 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.3946578259
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.395133604
Short name T77
Test name
Test status
Simulation time 14709269 ps
CPU time 0.54 seconds
Started Aug 06 07:04:50 PM PDT 24
Finished Aug 06 07:04:50 PM PDT 24
Peak memory 182604 kb
Host smart-d61281e2-bedf-40a4-a214-cd816a78bafd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395133604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.395133604
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.3299528371
Short name T474
Test name
Test status
Simulation time 59481239 ps
CPU time 0.51 seconds
Started Aug 06 07:04:50 PM PDT 24
Finished Aug 06 07:04:51 PM PDT 24
Peak memory 182252 kb
Host smart-b192957f-e06f-49f0-90b1-af081bcf7e23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299528371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.3299528371
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.2939424863
Short name T518
Test name
Test status
Simulation time 21840235 ps
CPU time 0.78 seconds
Started Aug 06 07:04:52 PM PDT 24
Finished Aug 06 07:04:53 PM PDT 24
Peak memory 191888 kb
Host smart-f7c07bca-113a-4787-aab7-9154784294f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939424863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.2939424863
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1893300281
Short name T466
Test name
Test status
Simulation time 68162653 ps
CPU time 1.33 seconds
Started Aug 06 07:04:50 PM PDT 24
Finished Aug 06 07:04:51 PM PDT 24
Peak memory 197588 kb
Host smart-836dcbec-117d-4a79-9851-8bd35bb626ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893300281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.1893300281
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.4255273703
Short name T98
Test name
Test status
Simulation time 175339029 ps
CPU time 0.93 seconds
Started Aug 06 07:04:51 PM PDT 24
Finished Aug 06 07:04:52 PM PDT 24
Peak memory 194028 kb
Host smart-42664635-52b8-45e3-ad35-890d88c8bfe8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255273703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.4255273703
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.2387051008
Short name T535
Test name
Test status
Simulation time 153719415 ps
CPU time 1.02 seconds
Started Aug 06 07:04:51 PM PDT 24
Finished Aug 06 07:04:52 PM PDT 24
Peak memory 197504 kb
Host smart-c7511001-a417-4ebd-ba6e-6b4e45e7ebc2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387051008 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.2387051008
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.525791421
Short name T556
Test name
Test status
Simulation time 87379546 ps
CPU time 0.55 seconds
Started Aug 06 07:04:55 PM PDT 24
Finished Aug 06 07:04:55 PM PDT 24
Peak memory 182944 kb
Host smart-2a7750a5-5774-437a-bdad-602b1f30b0db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525791421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.525791421
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2747506156
Short name T519
Test name
Test status
Simulation time 47979318 ps
CPU time 0.54 seconds
Started Aug 06 07:04:50 PM PDT 24
Finished Aug 06 07:04:51 PM PDT 24
Peak memory 182708 kb
Host smart-ea693742-6481-4f51-8a9f-04bd449d9643
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747506156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.2747506156
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.3591826166
Short name T501
Test name
Test status
Simulation time 28891282 ps
CPU time 0.74 seconds
Started Aug 06 07:04:49 PM PDT 24
Finished Aug 06 07:04:50 PM PDT 24
Peak memory 193604 kb
Host smart-c2f87262-5daa-412a-91b0-d5c7f8a2baa8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591826166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.3591826166
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.2896990993
Short name T498
Test name
Test status
Simulation time 31485912 ps
CPU time 1.53 seconds
Started Aug 06 07:04:53 PM PDT 24
Finished Aug 06 07:04:55 PM PDT 24
Peak memory 197700 kb
Host smart-01668b34-f3cc-4b87-93b1-7f3dba4e6d66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896990993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.2896990993
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.3840121495
Short name T526
Test name
Test status
Simulation time 133909250 ps
CPU time 1.14 seconds
Started Aug 06 07:04:50 PM PDT 24
Finished Aug 06 07:04:51 PM PDT 24
Peak memory 195516 kb
Host smart-e83a2333-447f-407b-81a1-325fbc6bff9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840121495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.3840121495
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.1495915175
Short name T549
Test name
Test status
Simulation time 36922377 ps
CPU time 1.72 seconds
Started Aug 06 07:04:51 PM PDT 24
Finished Aug 06 07:04:53 PM PDT 24
Peak memory 197696 kb
Host smart-4226cf0f-6d31-4773-bf45-76d2d5f15804
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495915175 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.1495915175
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.3920314985
Short name T554
Test name
Test status
Simulation time 20439707 ps
CPU time 0.54 seconds
Started Aug 06 07:04:50 PM PDT 24
Finished Aug 06 07:04:51 PM PDT 24
Peak memory 182548 kb
Host smart-47feba49-b81b-4f1d-b9de-1eae44625587
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920314985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.3920314985
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.830114858
Short name T456
Test name
Test status
Simulation time 20533485 ps
CPU time 0.54 seconds
Started Aug 06 07:04:49 PM PDT 24
Finished Aug 06 07:04:50 PM PDT 24
Peak memory 182468 kb
Host smart-2f17eb51-3c0c-40a9-bae6-a562fe939bdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830114858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.830114858
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.3419545325
Short name T85
Test name
Test status
Simulation time 36576805 ps
CPU time 0.77 seconds
Started Aug 06 07:04:52 PM PDT 24
Finished Aug 06 07:04:53 PM PDT 24
Peak memory 191900 kb
Host smart-804d6743-df3b-4956-945f-a6aaab499cc3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419545325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.3419545325
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.2638238608
Short name T503
Test name
Test status
Simulation time 16386538 ps
CPU time 0.7 seconds
Started Aug 06 07:04:48 PM PDT 24
Finished Aug 06 07:04:49 PM PDT 24
Peak memory 191892 kb
Host smart-d43ad01d-4c0d-4fe0-9782-2d889055a1c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638238608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.2638238608
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.1869445872
Short name T494
Test name
Test status
Simulation time 61007817 ps
CPU time 0.73 seconds
Started Aug 06 07:04:53 PM PDT 24
Finished Aug 06 07:04:54 PM PDT 24
Peak memory 195132 kb
Host smart-a3b17645-2fb1-4b4e-8ebe-b563c9ea7780
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869445872 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.1869445872
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.794295204
Short name T579
Test name
Test status
Simulation time 24531197 ps
CPU time 0.58 seconds
Started Aug 06 07:04:53 PM PDT 24
Finished Aug 06 07:04:54 PM PDT 24
Peak memory 182860 kb
Host smart-403fefda-d8b7-46ee-b725-9d167431ea62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794295204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.794295204
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.3454832557
Short name T529
Test name
Test status
Simulation time 26968719 ps
CPU time 0.54 seconds
Started Aug 06 07:04:53 PM PDT 24
Finished Aug 06 07:04:54 PM PDT 24
Peak memory 182764 kb
Host smart-6a0ce485-a51c-4535-8f3a-f80e12988753
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454832557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.3454832557
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1368087438
Short name T513
Test name
Test status
Simulation time 38032665 ps
CPU time 0.6 seconds
Started Aug 06 07:04:51 PM PDT 24
Finished Aug 06 07:04:52 PM PDT 24
Peak memory 191440 kb
Host smart-4f71ec96-7027-4167-839e-104ae48df0bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368087438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.1368087438
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3581710352
Short name T486
Test name
Test status
Simulation time 42627125 ps
CPU time 0.98 seconds
Started Aug 06 07:04:50 PM PDT 24
Finished Aug 06 07:04:51 PM PDT 24
Peak memory 196524 kb
Host smart-528d9f66-e61a-49dc-899f-8e518cadd605
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581710352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.3581710352
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1465096606
Short name T548
Test name
Test status
Simulation time 165568270 ps
CPU time 0.83 seconds
Started Aug 06 07:04:51 PM PDT 24
Finished Aug 06 07:04:52 PM PDT 24
Peak memory 183256 kb
Host smart-2759725a-c364-4ce3-91d6-19672b3fe24b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465096606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.1465096606
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3562652900
Short name T537
Test name
Test status
Simulation time 16918160 ps
CPU time 0.62 seconds
Started Aug 06 07:04:50 PM PDT 24
Finished Aug 06 07:04:51 PM PDT 24
Peak memory 193944 kb
Host smart-3e172bee-290a-4989-a20d-9f0ff8924a3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562652900 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.3562652900
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.1292753086
Short name T81
Test name
Test status
Simulation time 72869165 ps
CPU time 0.57 seconds
Started Aug 06 07:04:52 PM PDT 24
Finished Aug 06 07:04:52 PM PDT 24
Peak memory 182688 kb
Host smart-7efde51e-b91b-4a68-9394-30c35aa55270
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292753086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.1292753086
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.2826786282
Short name T473
Test name
Test status
Simulation time 22901807 ps
CPU time 0.55 seconds
Started Aug 06 07:04:52 PM PDT 24
Finished Aug 06 07:04:52 PM PDT 24
Peak memory 182608 kb
Host smart-e0b1e7fb-44f8-435d-b418-7b2464f598c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826786282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.2826786282
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2065510355
Short name T576
Test name
Test status
Simulation time 77326733 ps
CPU time 0.81 seconds
Started Aug 06 07:04:49 PM PDT 24
Finished Aug 06 07:04:50 PM PDT 24
Peak memory 193692 kb
Host smart-b0b20072-7a30-47f6-9de2-d9e17aae76b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065510355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.2065510355
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.2528517541
Short name T460
Test name
Test status
Simulation time 623597602 ps
CPU time 3.25 seconds
Started Aug 06 07:04:51 PM PDT 24
Finished Aug 06 07:04:54 PM PDT 24
Peak memory 197680 kb
Host smart-c79f0a53-2fe5-4fdd-9d6a-86b6a0c70015
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528517541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.2528517541
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1077662832
Short name T482
Test name
Test status
Simulation time 80584278 ps
CPU time 1.07 seconds
Started Aug 06 07:04:49 PM PDT 24
Finished Aug 06 07:04:51 PM PDT 24
Peak memory 195288 kb
Host smart-c6ce0b67-6295-491a-93cc-d82058821ddd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077662832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.1077662832
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.3090925169
Short name T79
Test name
Test status
Simulation time 46118478 ps
CPU time 0.63 seconds
Started Aug 06 07:04:08 PM PDT 24
Finished Aug 06 07:04:08 PM PDT 24
Peak memory 192140 kb
Host smart-e6ce8e90-adda-4297-8c5b-163fc8e9e829
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090925169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.3090925169
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.3491621373
Short name T485
Test name
Test status
Simulation time 1101347743 ps
CPU time 3.53 seconds
Started Aug 06 07:04:11 PM PDT 24
Finished Aug 06 07:04:14 PM PDT 24
Peak memory 183112 kb
Host smart-2131c087-0f6e-4270-9b33-232c6e30665b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491621373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.3491621373
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.2565033374
Short name T45
Test name
Test status
Simulation time 34247920 ps
CPU time 0.53 seconds
Started Aug 06 07:04:18 PM PDT 24
Finished Aug 06 07:04:19 PM PDT 24
Peak memory 182936 kb
Host smart-1b9b497a-b3df-4fbb-9591-9ffad03f8d5f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565033374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.2565033374
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3100726756
Short name T514
Test name
Test status
Simulation time 84991109 ps
CPU time 0.7 seconds
Started Aug 06 07:04:24 PM PDT 24
Finished Aug 06 07:04:25 PM PDT 24
Peak memory 194580 kb
Host smart-fff0ec27-6e99-42f5-94bf-5f2eb5fddd12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100726756 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.3100726756
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.1007188557
Short name T577
Test name
Test status
Simulation time 38109476 ps
CPU time 0.53 seconds
Started Aug 06 07:04:18 PM PDT 24
Finished Aug 06 07:04:18 PM PDT 24
Peak memory 182680 kb
Host smart-5aadeead-a9c5-4660-8727-a0b024767751
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007188557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.1007188557
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.917361519
Short name T468
Test name
Test status
Simulation time 14919361 ps
CPU time 0.57 seconds
Started Aug 06 07:04:08 PM PDT 24
Finished Aug 06 07:04:09 PM PDT 24
Peak memory 182688 kb
Host smart-f8d9cb5a-01eb-4efa-bf61-05633e5491b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917361519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.917361519
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.2328625621
Short name T515
Test name
Test status
Simulation time 35016978 ps
CPU time 0.63 seconds
Started Aug 06 07:04:05 PM PDT 24
Finished Aug 06 07:04:05 PM PDT 24
Peak memory 191700 kb
Host smart-d1a1c42c-dc75-430e-a10c-582ac681f66d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328625621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.2328625621
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.2086347924
Short name T546
Test name
Test status
Simulation time 151170674 ps
CPU time 1.83 seconds
Started Aug 06 07:04:08 PM PDT 24
Finished Aug 06 07:04:10 PM PDT 24
Peak memory 197740 kb
Host smart-ef679998-4e57-4428-bd51-fd7cdd7008d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086347924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.2086347924
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.1420234221
Short name T578
Test name
Test status
Simulation time 340722425 ps
CPU time 0.89 seconds
Started Aug 06 07:04:11 PM PDT 24
Finished Aug 06 07:04:12 PM PDT 24
Peak memory 193572 kb
Host smart-f3c796a7-49bd-4441-a9da-e8747cbfa822
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420234221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.1420234221
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.2906564977
Short name T457
Test name
Test status
Simulation time 20351540 ps
CPU time 0.57 seconds
Started Aug 06 07:04:53 PM PDT 24
Finished Aug 06 07:04:54 PM PDT 24
Peak memory 182772 kb
Host smart-4733e831-195d-4839-a17b-a451278bdd3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906564977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.2906564977
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.2705985275
Short name T580
Test name
Test status
Simulation time 15480619 ps
CPU time 0.56 seconds
Started Aug 06 07:04:53 PM PDT 24
Finished Aug 06 07:04:53 PM PDT 24
Peak memory 182808 kb
Host smart-81bbe3cc-ae82-4dbd-abcd-0883ff745cde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705985275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.2705985275
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.1378450703
Short name T500
Test name
Test status
Simulation time 50060994 ps
CPU time 0.57 seconds
Started Aug 06 07:04:53 PM PDT 24
Finished Aug 06 07:04:53 PM PDT 24
Peak memory 182444 kb
Host smart-5a6b31d7-53d8-4cc7-a1b4-ef0ce1e93dcf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378450703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.1378450703
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.1652635992
Short name T582
Test name
Test status
Simulation time 12107664 ps
CPU time 0.56 seconds
Started Aug 06 07:04:53 PM PDT 24
Finished Aug 06 07:04:54 PM PDT 24
Peak memory 182788 kb
Host smart-3ca91542-cfe5-4b5a-b6c2-ec15ceed529e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652635992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.1652635992
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.531376593
Short name T488
Test name
Test status
Simulation time 19636433 ps
CPU time 0.59 seconds
Started Aug 06 07:04:54 PM PDT 24
Finished Aug 06 07:04:54 PM PDT 24
Peak memory 182692 kb
Host smart-fec92802-f744-48d3-aebf-1ea2b7e45229
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531376593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.531376593
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.250278453
Short name T475
Test name
Test status
Simulation time 42890659 ps
CPU time 0.55 seconds
Started Aug 06 07:04:56 PM PDT 24
Finished Aug 06 07:04:57 PM PDT 24
Peak memory 182736 kb
Host smart-f58f6916-4f5f-490a-8726-47da7827be23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250278453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.250278453
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.2633313697
Short name T516
Test name
Test status
Simulation time 12980053 ps
CPU time 0.54 seconds
Started Aug 06 07:04:52 PM PDT 24
Finished Aug 06 07:04:53 PM PDT 24
Peak memory 182780 kb
Host smart-39edeb5f-7586-4373-8bd5-0723ce709895
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633313697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.2633313697
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.1075722276
Short name T463
Test name
Test status
Simulation time 106427199 ps
CPU time 0.55 seconds
Started Aug 06 07:05:01 PM PDT 24
Finished Aug 06 07:05:02 PM PDT 24
Peak memory 182800 kb
Host smart-80abe2fc-b475-4bea-b142-877082f265f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075722276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.1075722276
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1667283040
Short name T541
Test name
Test status
Simulation time 32600520 ps
CPU time 0.5 seconds
Started Aug 06 07:04:53 PM PDT 24
Finished Aug 06 07:04:53 PM PDT 24
Peak memory 182236 kb
Host smart-6f889cd0-0d3d-45da-a09e-40e40315c429
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667283040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.1667283040
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.2972867718
Short name T454
Test name
Test status
Simulation time 16665885 ps
CPU time 0.57 seconds
Started Aug 06 07:04:53 PM PDT 24
Finished Aug 06 07:04:54 PM PDT 24
Peak memory 182716 kb
Host smart-16fb71f5-91e8-4859-b0d9-470598ccfbc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972867718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.2972867718
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.247394187
Short name T527
Test name
Test status
Simulation time 64906177 ps
CPU time 0.6 seconds
Started Aug 06 07:04:18 PM PDT 24
Finished Aug 06 07:04:18 PM PDT 24
Peak memory 182692 kb
Host smart-5c73f4dc-6035-42aa-987b-72a4e029d6e5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247394187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alias
ing.247394187
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.2155406536
Short name T547
Test name
Test status
Simulation time 111113633 ps
CPU time 1.43 seconds
Started Aug 06 07:04:09 PM PDT 24
Finished Aug 06 07:04:11 PM PDT 24
Peak memory 193376 kb
Host smart-96659ec4-2423-40e1-9796-6dd833982c51
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155406536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.2155406536
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.1977833549
Short name T483
Test name
Test status
Simulation time 216471431 ps
CPU time 0.55 seconds
Started Aug 06 07:04:06 PM PDT 24
Finished Aug 06 07:04:07 PM PDT 24
Peak memory 182884 kb
Host smart-d19ae9ed-c051-438d-912f-c3cc05bc5623
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977833549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.1977833549
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.87647743
Short name T575
Test name
Test status
Simulation time 26832047 ps
CPU time 0.72 seconds
Started Aug 06 07:04:18 PM PDT 24
Finished Aug 06 07:04:19 PM PDT 24
Peak memory 195200 kb
Host smart-b3a3bd0f-c13f-4512-8724-f95a82adf0b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87647743 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.87647743
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.3483915793
Short name T543
Test name
Test status
Simulation time 16535965 ps
CPU time 0.53 seconds
Started Aug 06 07:04:16 PM PDT 24
Finished Aug 06 07:04:17 PM PDT 24
Peak memory 182864 kb
Host smart-733d6c0f-b40e-4e1c-9b99-58ff1f59c5ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483915793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.3483915793
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.941147548
Short name T538
Test name
Test status
Simulation time 20239868 ps
CPU time 0.56 seconds
Started Aug 06 07:04:17 PM PDT 24
Finished Aug 06 07:04:18 PM PDT 24
Peak memory 182744 kb
Host smart-ff9e9d49-62e8-4979-8dc0-41c89b0d2ee0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941147548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.941147548
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.1470000973
Short name T88
Test name
Test status
Simulation time 26460839 ps
CPU time 0.66 seconds
Started Aug 06 07:04:14 PM PDT 24
Finished Aug 06 07:04:15 PM PDT 24
Peak memory 191936 kb
Host smart-1c365329-c9f2-4ecf-8bcf-519ceca06cbc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470000973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.1470000973
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.1156831509
Short name T569
Test name
Test status
Simulation time 19194242 ps
CPU time 0.94 seconds
Started Aug 06 07:04:07 PM PDT 24
Finished Aug 06 07:04:08 PM PDT 24
Peak memory 195680 kb
Host smart-d8bd505f-d0d3-4544-824e-3eae96d5f776
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156831509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.1156831509
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.3212091702
Short name T94
Test name
Test status
Simulation time 132776225 ps
CPU time 1.36 seconds
Started Aug 06 07:04:13 PM PDT 24
Finished Aug 06 07:04:15 PM PDT 24
Peak memory 195836 kb
Host smart-e5ff9880-17a6-4eb4-ae2d-a06f52c76bdc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212091702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.3212091702
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.2667030238
Short name T539
Test name
Test status
Simulation time 17261459 ps
CPU time 0.53 seconds
Started Aug 06 07:04:55 PM PDT 24
Finished Aug 06 07:04:56 PM PDT 24
Peak memory 182396 kb
Host smart-3e51fd8d-625f-4f75-81d6-9758482f5516
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667030238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.2667030238
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.3143840405
Short name T534
Test name
Test status
Simulation time 22417026 ps
CPU time 0.57 seconds
Started Aug 06 07:04:57 PM PDT 24
Finished Aug 06 07:04:57 PM PDT 24
Peak memory 182716 kb
Host smart-6eb24fb1-021f-4abd-80f9-049475fd46a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143840405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.3143840405
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.4234868401
Short name T522
Test name
Test status
Simulation time 89278406 ps
CPU time 0.54 seconds
Started Aug 06 07:04:57 PM PDT 24
Finished Aug 06 07:04:58 PM PDT 24
Peak memory 182236 kb
Host smart-ccf22bb9-ed7b-47e5-ab82-023684eba654
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234868401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.4234868401
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3499129863
Short name T524
Test name
Test status
Simulation time 36433974 ps
CPU time 0.59 seconds
Started Aug 06 07:04:52 PM PDT 24
Finished Aug 06 07:04:53 PM PDT 24
Peak memory 182436 kb
Host smart-cff03af0-029f-464f-9ed8-e285e8a19dab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499129863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.3499129863
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.1294240944
Short name T544
Test name
Test status
Simulation time 44344715 ps
CPU time 0.6 seconds
Started Aug 06 07:04:52 PM PDT 24
Finished Aug 06 07:04:53 PM PDT 24
Peak memory 182456 kb
Host smart-53327b10-2d9f-4481-8ad6-defc8aa2aa70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294240944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.1294240944
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2124461578
Short name T574
Test name
Test status
Simulation time 10750202 ps
CPU time 0.52 seconds
Started Aug 06 07:04:57 PM PDT 24
Finished Aug 06 07:04:57 PM PDT 24
Peak memory 182228 kb
Host smart-b2fc893b-30e8-4710-911f-533e296964d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124461578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.2124461578
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.2643337741
Short name T542
Test name
Test status
Simulation time 83459102 ps
CPU time 0.53 seconds
Started Aug 06 07:04:57 PM PDT 24
Finished Aug 06 07:04:58 PM PDT 24
Peak memory 182228 kb
Host smart-60909a30-c97e-4664-a753-66f16d57e074
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643337741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.2643337741
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.3541396604
Short name T570
Test name
Test status
Simulation time 13397165 ps
CPU time 0.53 seconds
Started Aug 06 07:04:56 PM PDT 24
Finished Aug 06 07:04:56 PM PDT 24
Peak memory 182264 kb
Host smart-925d0512-a8d8-4fc7-9bca-69a4bb78c31c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541396604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.3541396604
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.2152565812
Short name T533
Test name
Test status
Simulation time 12637422 ps
CPU time 0.61 seconds
Started Aug 06 07:04:56 PM PDT 24
Finished Aug 06 07:04:57 PM PDT 24
Peak memory 182768 kb
Host smart-da8c2d19-045b-4f2d-bcbe-8394863e3ed5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152565812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.2152565812
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.2270848213
Short name T572
Test name
Test status
Simulation time 108221758 ps
CPU time 0.54 seconds
Started Aug 06 07:04:59 PM PDT 24
Finished Aug 06 07:05:00 PM PDT 24
Peak memory 182740 kb
Host smart-283be7cf-9151-4d46-bc64-f2692fd50a0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270848213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.2270848213
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.2253467789
Short name T492
Test name
Test status
Simulation time 34810500 ps
CPU time 0.79 seconds
Started Aug 06 07:04:21 PM PDT 24
Finished Aug 06 07:04:22 PM PDT 24
Peak memory 182924 kb
Host smart-f377fbf4-805b-4a00-9429-cf52e80c1d9c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253467789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.2253467789
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.2770103009
Short name T84
Test name
Test status
Simulation time 281138065 ps
CPU time 2.71 seconds
Started Aug 06 07:04:23 PM PDT 24
Finished Aug 06 07:04:26 PM PDT 24
Peak memory 183132 kb
Host smart-a4e8c835-cdaf-4f69-8c3e-233dddd9c69c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770103009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.2770103009
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2783353917
Short name T560
Test name
Test status
Simulation time 38932641 ps
CPU time 0.54 seconds
Started Aug 06 07:04:19 PM PDT 24
Finished Aug 06 07:04:20 PM PDT 24
Peak memory 182688 kb
Host smart-75889410-3926-4db6-ad37-cde8c495bc5e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783353917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.2783353917
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3270988872
Short name T480
Test name
Test status
Simulation time 21243036 ps
CPU time 0.67 seconds
Started Aug 06 07:04:22 PM PDT 24
Finished Aug 06 07:04:22 PM PDT 24
Peak memory 194552 kb
Host smart-c561b315-8d4b-41f3-bc51-aa98c9e78ab8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270988872 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.3270988872
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.3676287005
Short name T567
Test name
Test status
Simulation time 20094706 ps
CPU time 0.54 seconds
Started Aug 06 07:04:08 PM PDT 24
Finished Aug 06 07:04:08 PM PDT 24
Peak memory 182860 kb
Host smart-3a4039cf-0bb1-475b-9aff-3f109dab5d0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676287005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.3676287005
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.501056538
Short name T481
Test name
Test status
Simulation time 54001542 ps
CPU time 0.54 seconds
Started Aug 06 07:04:18 PM PDT 24
Finished Aug 06 07:04:19 PM PDT 24
Peak memory 182516 kb
Host smart-e673f36e-ac2d-41bd-a26b-19af4d23ab26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501056538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.501056538
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.9883296
Short name T91
Test name
Test status
Simulation time 16096255 ps
CPU time 0.74 seconds
Started Aug 06 07:04:23 PM PDT 24
Finished Aug 06 07:04:24 PM PDT 24
Peak memory 191912 kb
Host smart-77ff6214-24d2-479c-bff6-1c5a27fe7aa0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9883296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_t
imer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer
_same_csr_outstanding.9883296
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1704520342
Short name T555
Test name
Test status
Simulation time 148101258 ps
CPU time 1.77 seconds
Started Aug 06 07:04:05 PM PDT 24
Finished Aug 06 07:04:07 PM PDT 24
Peak memory 197660 kb
Host smart-5f5e587f-7909-4394-86e0-6763112c685f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704520342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.1704520342
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.14155829
Short name T563
Test name
Test status
Simulation time 27738584 ps
CPU time 0.56 seconds
Started Aug 06 07:04:55 PM PDT 24
Finished Aug 06 07:04:56 PM PDT 24
Peak memory 182788 kb
Host smart-2f9a9266-7e4e-4b19-badd-225c2bc2ffae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14155829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.14155829
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.3478207377
Short name T536
Test name
Test status
Simulation time 34217940 ps
CPU time 0.56 seconds
Started Aug 06 07:04:57 PM PDT 24
Finished Aug 06 07:04:58 PM PDT 24
Peak memory 182720 kb
Host smart-0d7aac04-b5be-4406-9315-d2be84d9ca13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478207377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.3478207377
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.3429650337
Short name T551
Test name
Test status
Simulation time 31202611 ps
CPU time 0.54 seconds
Started Aug 06 07:05:01 PM PDT 24
Finished Aug 06 07:05:02 PM PDT 24
Peak memory 182712 kb
Host smart-258fc35e-3e38-45c8-9c7f-2e027284dd5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429650337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.3429650337
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.2273783775
Short name T502
Test name
Test status
Simulation time 13449316 ps
CPU time 0.54 seconds
Started Aug 06 07:04:59 PM PDT 24
Finished Aug 06 07:05:00 PM PDT 24
Peak memory 182268 kb
Host smart-38e592e8-080b-4520-a13e-d15edcea1b64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273783775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.2273783775
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.2434497564
Short name T510
Test name
Test status
Simulation time 28473082 ps
CPU time 0.55 seconds
Started Aug 06 07:04:59 PM PDT 24
Finished Aug 06 07:05:00 PM PDT 24
Peak memory 182260 kb
Host smart-6b091d6d-f9c2-4d1a-8cbc-7258c024df50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434497564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.2434497564
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.229246318
Short name T459
Test name
Test status
Simulation time 45337583 ps
CPU time 0.55 seconds
Started Aug 06 07:04:58 PM PDT 24
Finished Aug 06 07:04:58 PM PDT 24
Peak memory 182792 kb
Host smart-5391cad3-2713-4d17-a35a-4e18643a1289
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229246318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.229246318
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.2607271920
Short name T490
Test name
Test status
Simulation time 16888838 ps
CPU time 0.56 seconds
Started Aug 06 07:04:51 PM PDT 24
Finished Aug 06 07:04:52 PM PDT 24
Peak memory 182784 kb
Host smart-73d6f719-86a5-4ef9-b64c-baa2d1f7d972
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607271920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.2607271920
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.3687407858
Short name T525
Test name
Test status
Simulation time 37503270 ps
CPU time 0.56 seconds
Started Aug 06 07:05:00 PM PDT 24
Finished Aug 06 07:05:00 PM PDT 24
Peak memory 182788 kb
Host smart-84ef3cf2-af10-4670-872b-d5a776d80f95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687407858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.3687407858
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.998262153
Short name T564
Test name
Test status
Simulation time 14212128 ps
CPU time 0.54 seconds
Started Aug 06 07:04:59 PM PDT 24
Finished Aug 06 07:05:00 PM PDT 24
Peak memory 182200 kb
Host smart-021c6174-02a4-4c73-a252-ca082236b511
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998262153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.998262153
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.4197745204
Short name T511
Test name
Test status
Simulation time 45448737 ps
CPU time 0.53 seconds
Started Aug 06 07:05:03 PM PDT 24
Finished Aug 06 07:05:03 PM PDT 24
Peak memory 182244 kb
Host smart-8294c613-1d26-4a17-9776-b4ac019f6176
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197745204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.4197745204
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2471817853
Short name T487
Test name
Test status
Simulation time 81844391 ps
CPU time 0.9 seconds
Started Aug 06 07:04:25 PM PDT 24
Finished Aug 06 07:04:26 PM PDT 24
Peak memory 196888 kb
Host smart-15233bf2-e0ee-4644-a7b0-2749bb6ccabc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471817853 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.2471817853
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.1180019780
Short name T521
Test name
Test status
Simulation time 38718534 ps
CPU time 0.57 seconds
Started Aug 06 07:04:23 PM PDT 24
Finished Aug 06 07:04:24 PM PDT 24
Peak memory 182920 kb
Host smart-b3c8ce80-feb0-49b4-ae49-1224c22f1849
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180019780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.1180019780
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.2197793279
Short name T464
Test name
Test status
Simulation time 17025596 ps
CPU time 0.57 seconds
Started Aug 06 07:04:25 PM PDT 24
Finished Aug 06 07:04:26 PM PDT 24
Peak memory 182784 kb
Host smart-6ffc767b-158e-42e5-8159-63b01de8488d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197793279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.2197793279
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2943008145
Short name T87
Test name
Test status
Simulation time 26103534 ps
CPU time 0.68 seconds
Started Aug 06 07:04:22 PM PDT 24
Finished Aug 06 07:04:23 PM PDT 24
Peak memory 192428 kb
Host smart-0c72970f-c1f8-4c23-88f2-bf809fe6c4e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943008145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.2943008145
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.1613184650
Short name T467
Test name
Test status
Simulation time 56686983 ps
CPU time 1.34 seconds
Started Aug 06 07:04:25 PM PDT 24
Finished Aug 06 07:04:26 PM PDT 24
Peak memory 197688 kb
Host smart-3c858a28-963d-41a1-9c49-190828ab57fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613184650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.1613184650
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3997150131
Short name T27
Test name
Test status
Simulation time 115048589 ps
CPU time 0.88 seconds
Started Aug 06 07:04:27 PM PDT 24
Finished Aug 06 07:04:28 PM PDT 24
Peak memory 193696 kb
Host smart-1a731f8b-0f49-4c72-bc55-097ed200e688
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997150131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.3997150131
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.2354743224
Short name T470
Test name
Test status
Simulation time 45776234 ps
CPU time 1.14 seconds
Started Aug 06 07:04:28 PM PDT 24
Finished Aug 06 07:04:30 PM PDT 24
Peak memory 197652 kb
Host smart-8dfb9bcf-896d-4ad0-b619-9dc655f21c20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354743224 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.2354743224
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.3271475989
Short name T558
Test name
Test status
Simulation time 24512875 ps
CPU time 0.61 seconds
Started Aug 06 07:04:25 PM PDT 24
Finished Aug 06 07:04:26 PM PDT 24
Peak memory 183004 kb
Host smart-b58841ca-675f-4e91-bc5e-e55c844f681b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271475989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.3271475989
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.1394838730
Short name T493
Test name
Test status
Simulation time 16029029 ps
CPU time 0.57 seconds
Started Aug 06 07:04:24 PM PDT 24
Finished Aug 06 07:04:24 PM PDT 24
Peak memory 182696 kb
Host smart-19c2ee1c-ff29-4488-8238-7c5ab0419908
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394838730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.1394838730
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.1642216028
Short name T89
Test name
Test status
Simulation time 17962138 ps
CPU time 0.75 seconds
Started Aug 06 07:04:26 PM PDT 24
Finished Aug 06 07:04:26 PM PDT 24
Peak memory 193340 kb
Host smart-c68495ea-5cb4-46a0-a8a3-b7e2efca9a89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642216028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.1642216028
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.292977878
Short name T508
Test name
Test status
Simulation time 101526219 ps
CPU time 2.2 seconds
Started Aug 06 07:04:24 PM PDT 24
Finished Aug 06 07:04:26 PM PDT 24
Peak memory 197692 kb
Host smart-bdcf6c69-0f63-44e5-b94d-1071dee4cb23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292977878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.292977878
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.3444147411
Short name T509
Test name
Test status
Simulation time 332245547 ps
CPU time 1.11 seconds
Started Aug 06 07:04:22 PM PDT 24
Finished Aug 06 07:04:23 PM PDT 24
Peak memory 195256 kb
Host smart-c7c6d4aa-a498-45ed-aa33-436421f25e0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444147411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.3444147411
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.737331178
Short name T553
Test name
Test status
Simulation time 80038637 ps
CPU time 0.76 seconds
Started Aug 06 07:04:23 PM PDT 24
Finished Aug 06 07:04:24 PM PDT 24
Peak memory 194888 kb
Host smart-3e3d5bc7-26c2-453d-bea2-4a6d8549f55b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737331178 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.737331178
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.566218374
Short name T484
Test name
Test status
Simulation time 47776592 ps
CPU time 0.59 seconds
Started Aug 06 07:04:25 PM PDT 24
Finished Aug 06 07:04:26 PM PDT 24
Peak memory 182864 kb
Host smart-b6f55d3f-f450-4932-a45c-7746f3ac1687
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566218374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.566218374
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.793353985
Short name T455
Test name
Test status
Simulation time 138325424 ps
CPU time 0.51 seconds
Started Aug 06 07:04:21 PM PDT 24
Finished Aug 06 07:04:22 PM PDT 24
Peak memory 182432 kb
Host smart-1e0a4728-05ef-4cdb-b8a1-bd66793ede16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793353985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.793353985
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.106156871
Short name T86
Test name
Test status
Simulation time 138936126 ps
CPU time 0.76 seconds
Started Aug 06 07:04:24 PM PDT 24
Finished Aug 06 07:04:24 PM PDT 24
Peak memory 193552 kb
Host smart-460e3ff8-37e5-42d3-944f-14134210fb75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106156871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_tim
er_same_csr_outstanding.106156871
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.4099107849
Short name T499
Test name
Test status
Simulation time 47846508 ps
CPU time 2.2 seconds
Started Aug 06 07:04:24 PM PDT 24
Finished Aug 06 07:04:27 PM PDT 24
Peak memory 197696 kb
Host smart-777f7759-c9db-4e32-b6be-bed9096fa7ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099107849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.4099107849
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.1575204825
Short name T96
Test name
Test status
Simulation time 137486425 ps
CPU time 1.27 seconds
Started Aug 06 07:04:23 PM PDT 24
Finished Aug 06 07:04:25 PM PDT 24
Peak memory 195384 kb
Host smart-00524802-be92-427d-9ccc-ed3a8d4211e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575204825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.1575204825
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3441435212
Short name T461
Test name
Test status
Simulation time 22817575 ps
CPU time 1.02 seconds
Started Aug 06 07:04:25 PM PDT 24
Finished Aug 06 07:04:26 PM PDT 24
Peak memory 197612 kb
Host smart-7fb5f8e4-705a-42e0-a05c-b38c8665c61a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441435212 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.3441435212
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.124810622
Short name T83
Test name
Test status
Simulation time 19115066 ps
CPU time 0.56 seconds
Started Aug 06 07:04:23 PM PDT 24
Finished Aug 06 07:04:24 PM PDT 24
Peak memory 182940 kb
Host smart-c512d7ed-a39b-4ee2-9907-c943e3d0831d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124810622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.124810622
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.465964777
Short name T552
Test name
Test status
Simulation time 54634519 ps
CPU time 0.56 seconds
Started Aug 06 07:04:24 PM PDT 24
Finished Aug 06 07:04:24 PM PDT 24
Peak memory 182660 kb
Host smart-2723bd0c-a66c-44a9-8920-2f3462a30638
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465964777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.465964777
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.3380277526
Short name T568
Test name
Test status
Simulation time 47481486 ps
CPU time 0.94 seconds
Started Aug 06 07:04:23 PM PDT 24
Finished Aug 06 07:04:24 PM PDT 24
Peak memory 194928 kb
Host smart-688fcd62-8804-4eca-b2b2-8c28a48a34cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380277526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.3380277526
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.1787301376
Short name T476
Test name
Test status
Simulation time 313084162 ps
CPU time 2.87 seconds
Started Aug 06 07:04:23 PM PDT 24
Finished Aug 06 07:04:26 PM PDT 24
Peak memory 197652 kb
Host smart-d72ae37d-d3e2-4c0a-b1a9-38f09d11071c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787301376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.1787301376
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.3835746231
Short name T528
Test name
Test status
Simulation time 451045654 ps
CPU time 1.35 seconds
Started Aug 06 07:04:25 PM PDT 24
Finished Aug 06 07:04:26 PM PDT 24
Peak memory 195448 kb
Host smart-cda436cd-aa09-45f6-86ae-a07b8a0c6af6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835746231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.3835746231
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.2332527737
Short name T462
Test name
Test status
Simulation time 95242535 ps
CPU time 1.51 seconds
Started Aug 06 07:04:52 PM PDT 24
Finished Aug 06 07:04:54 PM PDT 24
Peak memory 197728 kb
Host smart-df4c5688-af84-4bf6-ad1b-1234c535f22b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332527737 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.2332527737
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.3844104366
Short name T78
Test name
Test status
Simulation time 20367412 ps
CPU time 0.53 seconds
Started Aug 06 07:04:24 PM PDT 24
Finished Aug 06 07:04:25 PM PDT 24
Peak memory 182992 kb
Host smart-562c466f-eaaf-4e08-b61b-5648041ff98c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844104366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.3844104366
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.4110989417
Short name T562
Test name
Test status
Simulation time 11687842 ps
CPU time 0.54 seconds
Started Aug 06 07:04:25 PM PDT 24
Finished Aug 06 07:04:26 PM PDT 24
Peak memory 182156 kb
Host smart-58eec5de-53a7-4281-8d12-dd2b1bd16bed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110989417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.4110989417
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1852842134
Short name T74
Test name
Test status
Simulation time 298384162 ps
CPU time 0.8 seconds
Started Aug 06 07:04:25 PM PDT 24
Finished Aug 06 07:04:26 PM PDT 24
Peak memory 191164 kb
Host smart-bf47a817-3af2-49ae-85ee-b63365c28a8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852842134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.1852842134
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.1919344377
Short name T453
Test name
Test status
Simulation time 307742407 ps
CPU time 3.02 seconds
Started Aug 06 07:04:23 PM PDT 24
Finished Aug 06 07:04:26 PM PDT 24
Peak memory 197688 kb
Host smart-88a6e434-5095-4990-b8e8-89095a7fc687
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919344377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.1919344377
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.4186794664
Short name T97
Test name
Test status
Simulation time 70427879 ps
CPU time 1.08 seconds
Started Aug 06 07:04:23 PM PDT 24
Finished Aug 06 07:04:24 PM PDT 24
Peak memory 195568 kb
Host smart-6eb9f577-f901-4dcc-8604-8bab36133f73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186794664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.4186794664
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.1517297138
Short name T360
Test name
Test status
Simulation time 432253127417 ps
CPU time 146.78 seconds
Started Aug 06 07:05:04 PM PDT 24
Finished Aug 06 07:07:31 PM PDT 24
Peak memory 183436 kb
Host smart-6c9b07a8-b409-417d-a5c8-c266aeb52500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517297138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.1517297138
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.3489933746
Short name T421
Test name
Test status
Simulation time 82684963254 ps
CPU time 156.6 seconds
Started Aug 06 07:05:01 PM PDT 24
Finished Aug 06 07:07:38 PM PDT 24
Peak memory 191700 kb
Host smart-f989a71a-d486-43c4-a8b8-fd77e45b3d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489933746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.3489933746
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.1413138741
Short name T103
Test name
Test status
Simulation time 452294410598 ps
CPU time 697.15 seconds
Started Aug 06 07:05:03 PM PDT 24
Finished Aug 06 07:16:40 PM PDT 24
Peak memory 183636 kb
Host smart-4f90109c-8ec1-4f4d-b5f9-54fbbe5279f0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413138741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.1413138741
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.2107544078
Short name T372
Test name
Test status
Simulation time 208509718514 ps
CPU time 155.48 seconds
Started Aug 06 07:05:04 PM PDT 24
Finished Aug 06 07:07:39 PM PDT 24
Peak memory 183436 kb
Host smart-a3d7071b-91ac-4ee8-b38b-b9f7905abc69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107544078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.2107544078
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.4070154227
Short name T306
Test name
Test status
Simulation time 684601227827 ps
CPU time 1596.04 seconds
Started Aug 06 07:05:04 PM PDT 24
Finished Aug 06 07:31:40 PM PDT 24
Peak memory 191620 kb
Host smart-3927bf2d-68b6-47c5-b83c-f5d4cfb3714b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070154227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.4070154227
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.838524119
Short name T207
Test name
Test status
Simulation time 35719499693 ps
CPU time 15.98 seconds
Started Aug 06 07:05:04 PM PDT 24
Finished Aug 06 07:05:20 PM PDT 24
Peak memory 183432 kb
Host smart-b5e706c1-0437-4e66-9fb5-db29e6dbbd1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838524119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.838524119
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.765017394
Short name T14
Test name
Test status
Simulation time 330635975 ps
CPU time 0.84 seconds
Started Aug 06 07:04:57 PM PDT 24
Finished Aug 06 07:04:58 PM PDT 24
Peak memory 213968 kb
Host smart-d950bf4e-e091-464f-aae6-2aa5c92882dd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765017394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.765017394
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.421702814
Short name T413
Test name
Test status
Simulation time 34775043 ps
CPU time 0.6 seconds
Started Aug 06 07:04:57 PM PDT 24
Finished Aug 06 07:04:58 PM PDT 24
Peak memory 183160 kb
Host smart-bbfa355a-cf24-4e49-8b6c-fd1a355dcdb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421702814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.421702814
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all_with_rand_reset.3392955979
Short name T31
Test name
Test status
Simulation time 52435195212 ps
CPU time 291.91 seconds
Started Aug 06 07:04:53 PM PDT 24
Finished Aug 06 07:09:45 PM PDT 24
Peak memory 198188 kb
Host smart-8e1ef264-c954-46a8-94a9-e8257d634223
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392955979 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all_with_rand_reset.3392955979
Directory /workspace/1.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.3324855500
Short name T409
Test name
Test status
Simulation time 139274595326 ps
CPU time 169.63 seconds
Started Aug 06 07:05:02 PM PDT 24
Finished Aug 06 07:07:52 PM PDT 24
Peak memory 183672 kb
Host smart-4cd0087d-fa9b-4d3e-af9e-d1bdd71c0c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324855500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.3324855500
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.992918580
Short name T366
Test name
Test status
Simulation time 156217959530 ps
CPU time 53.28 seconds
Started Aug 06 07:05:00 PM PDT 24
Finished Aug 06 07:05:53 PM PDT 24
Peak memory 183400 kb
Host smart-a26867d9-edd5-4517-9685-a00cb26bef0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992918580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all.
992918580
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/101.rv_timer_random.1162620255
Short name T254
Test name
Test status
Simulation time 344124142577 ps
CPU time 163.21 seconds
Started Aug 06 07:06:01 PM PDT 24
Finished Aug 06 07:08:44 PM PDT 24
Peak memory 191616 kb
Host smart-e94c3483-7ffc-4ea2-9863-8b860baf9891
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162620255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.1162620255
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.1143767699
Short name T308
Test name
Test status
Simulation time 1715082582466 ps
CPU time 339.94 seconds
Started Aug 06 07:06:01 PM PDT 24
Finished Aug 06 07:11:41 PM PDT 24
Peak memory 191672 kb
Host smart-8282d3d9-0554-42fa-957a-aaf01f41aa5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143767699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.1143767699
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.1727076494
Short name T157
Test name
Test status
Simulation time 67845985932 ps
CPU time 120.26 seconds
Started Aug 06 07:06:02 PM PDT 24
Finished Aug 06 07:08:03 PM PDT 24
Peak memory 191640 kb
Host smart-9fc0e268-db13-48c3-ad75-850d989a7a99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727076494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.1727076494
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.20215549
Short name T284
Test name
Test status
Simulation time 21028792371 ps
CPU time 41.48 seconds
Started Aug 06 07:05:59 PM PDT 24
Finished Aug 06 07:06:41 PM PDT 24
Peak memory 183432 kb
Host smart-4a461c15-12b3-4bae-83f0-7071694879f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20215549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.20215549
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.430521581
Short name T432
Test name
Test status
Simulation time 178416091639 ps
CPU time 184.4 seconds
Started Aug 06 07:06:02 PM PDT 24
Finished Aug 06 07:09:07 PM PDT 24
Peak memory 191604 kb
Host smart-eb3dd51b-c7aa-4d5c-a48f-eb6f05f974e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430521581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.430521581
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.3871940292
Short name T442
Test name
Test status
Simulation time 147207146636 ps
CPU time 265.65 seconds
Started Aug 06 07:06:01 PM PDT 24
Finished Aug 06 07:10:27 PM PDT 24
Peak memory 191624 kb
Host smart-3584d9c6-7455-49f8-9ec1-9a094798ab35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871940292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.3871940292
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.1825850635
Short name T220
Test name
Test status
Simulation time 1249103532758 ps
CPU time 726.36 seconds
Started Aug 06 07:04:53 PM PDT 24
Finished Aug 06 07:17:00 PM PDT 24
Peak memory 183400 kb
Host smart-bc6e7243-9f5e-442b-94ab-e6fe809fc98e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825850635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.1825850635
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.3456659125
Short name T393
Test name
Test status
Simulation time 35241004053 ps
CPU time 54.23 seconds
Started Aug 06 07:04:55 PM PDT 24
Finished Aug 06 07:05:49 PM PDT 24
Peak memory 183432 kb
Host smart-1031733d-ccb7-4437-bd46-b4e6a8506d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456659125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.3456659125
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.1977025691
Short name T452
Test name
Test status
Simulation time 45753918249 ps
CPU time 80.49 seconds
Started Aug 06 07:04:52 PM PDT 24
Finished Aug 06 07:06:13 PM PDT 24
Peak memory 183444 kb
Host smart-f8f3764d-b191-425e-8ee3-5260e9fdafb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977025691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.1977025691
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.3941862220
Short name T55
Test name
Test status
Simulation time 2331896184508 ps
CPU time 1146.52 seconds
Started Aug 06 07:04:56 PM PDT 24
Finished Aug 06 07:24:03 PM PDT 24
Peak memory 191596 kb
Host smart-76d7a5a5-5896-4e6c-8889-97f9d3025606
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941862220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.3941862220
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/110.rv_timer_random.3109171565
Short name T242
Test name
Test status
Simulation time 203820947839 ps
CPU time 598.77 seconds
Started Aug 06 07:06:03 PM PDT 24
Finished Aug 06 07:16:02 PM PDT 24
Peak memory 191596 kb
Host smart-32a78391-a8ff-45b3-8ab9-be3738dc9193
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109171565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.3109171565
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.2484929135
Short name T156
Test name
Test status
Simulation time 133639266700 ps
CPU time 63.51 seconds
Started Aug 06 07:06:05 PM PDT 24
Finished Aug 06 07:07:09 PM PDT 24
Peak memory 191612 kb
Host smart-21a0b6d2-229f-4e40-bf3e-bbfe12b69289
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484929135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.2484929135
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.2143618715
Short name T120
Test name
Test status
Simulation time 188066933187 ps
CPU time 177.99 seconds
Started Aug 06 07:06:03 PM PDT 24
Finished Aug 06 07:09:01 PM PDT 24
Peak memory 191652 kb
Host smart-502f0be0-008e-4cb0-9e9b-d30225eccc81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143618715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.2143618715
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.889059962
Short name T274
Test name
Test status
Simulation time 452125984588 ps
CPU time 357.63 seconds
Started Aug 06 07:06:04 PM PDT 24
Finished Aug 06 07:12:02 PM PDT 24
Peak memory 191648 kb
Host smart-b7477b11-d558-41ca-86c1-2e2a7491ce69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889059962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.889059962
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.3433925608
Short name T289
Test name
Test status
Simulation time 57575830266 ps
CPU time 102.65 seconds
Started Aug 06 07:06:04 PM PDT 24
Finished Aug 06 07:07:47 PM PDT 24
Peak memory 191596 kb
Host smart-9f2eb122-765c-4dd7-a115-feea9053c517
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433925608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.3433925608
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.2996185052
Short name T238
Test name
Test status
Simulation time 105271206385 ps
CPU time 444.96 seconds
Started Aug 06 07:06:04 PM PDT 24
Finished Aug 06 07:13:29 PM PDT 24
Peak memory 191596 kb
Host smart-1bd5e610-b612-4797-9496-ea2afaef0f1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996185052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.2996185052
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.241019777
Short name T187
Test name
Test status
Simulation time 190181363338 ps
CPU time 224.19 seconds
Started Aug 06 07:06:03 PM PDT 24
Finished Aug 06 07:09:47 PM PDT 24
Peak memory 191664 kb
Host smart-d0def6d9-b081-4090-b25d-86f09bcf86ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241019777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.241019777
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.3167620933
Short name T231
Test name
Test status
Simulation time 473412040578 ps
CPU time 234.52 seconds
Started Aug 06 07:04:57 PM PDT 24
Finished Aug 06 07:08:52 PM PDT 24
Peak memory 183396 kb
Host smart-d11e0172-0b52-411d-a1f2-2495653355b9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167620933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.3167620933
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.1342233502
Short name T400
Test name
Test status
Simulation time 20635723624 ps
CPU time 29.03 seconds
Started Aug 06 07:04:56 PM PDT 24
Finished Aug 06 07:05:25 PM PDT 24
Peak memory 183440 kb
Host smart-307eeb00-e9cf-4590-8688-08897eb7938b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342233502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.1342233502
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.720273565
Short name T182
Test name
Test status
Simulation time 169194459742 ps
CPU time 95.05 seconds
Started Aug 06 07:04:56 PM PDT 24
Finished Aug 06 07:06:31 PM PDT 24
Peak memory 191640 kb
Host smart-0971a829-6fab-4a38-9385-6d747d5845a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720273565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.720273565
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.1972450881
Short name T278
Test name
Test status
Simulation time 67832438089 ps
CPU time 25.47 seconds
Started Aug 06 07:04:56 PM PDT 24
Finished Aug 06 07:05:21 PM PDT 24
Peak memory 191656 kb
Host smart-f9641f7e-e170-4ff9-92da-6d11e9fe821e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972450881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.1972450881
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.3927343445
Short name T369
Test name
Test status
Simulation time 48726294423 ps
CPU time 70.13 seconds
Started Aug 06 07:04:56 PM PDT 24
Finished Aug 06 07:06:06 PM PDT 24
Peak memory 194896 kb
Host smart-957a0958-27f7-44ed-9272-d4caab215e5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927343445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.3927343445
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all_with_rand_reset.2173495993
Short name T36
Test name
Test status
Simulation time 283920572077 ps
CPU time 604.29 seconds
Started Aug 06 07:04:56 PM PDT 24
Finished Aug 06 07:15:00 PM PDT 24
Peak memory 206304 kb
Host smart-2aff2c3a-b578-48fe-a4a9-a173e058d420
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173495993 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all_with_rand_reset.2173495993
Directory /workspace/12.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.rv_timer_random.3379459834
Short name T212
Test name
Test status
Simulation time 80950957119 ps
CPU time 147.17 seconds
Started Aug 06 07:06:03 PM PDT 24
Finished Aug 06 07:08:31 PM PDT 24
Peak memory 191652 kb
Host smart-79ca39f3-468e-44d1-b907-6e25c7e2de66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379459834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.3379459834
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.1061636129
Short name T435
Test name
Test status
Simulation time 95377402611 ps
CPU time 178.9 seconds
Started Aug 06 07:06:05 PM PDT 24
Finished Aug 06 07:09:04 PM PDT 24
Peak memory 191608 kb
Host smart-8f50f076-6b0e-4d94-9a06-2db3c988ca5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061636129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.1061636129
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.3936188875
Short name T407
Test name
Test status
Simulation time 77963832708 ps
CPU time 117.59 seconds
Started Aug 06 07:06:05 PM PDT 24
Finished Aug 06 07:08:03 PM PDT 24
Peak memory 183464 kb
Host smart-9af732eb-55d3-4c7b-b1aa-431fffe51d7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936188875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.3936188875
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.3591307716
Short name T348
Test name
Test status
Simulation time 154262961513 ps
CPU time 145.74 seconds
Started Aug 06 07:06:05 PM PDT 24
Finished Aug 06 07:08:31 PM PDT 24
Peak memory 191480 kb
Host smart-7c2011b6-1478-431b-848d-603e4c695b2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591307716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.3591307716
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.3782756696
Short name T259
Test name
Test status
Simulation time 64266856639 ps
CPU time 315.41 seconds
Started Aug 06 07:06:04 PM PDT 24
Finished Aug 06 07:11:20 PM PDT 24
Peak memory 191656 kb
Host smart-b69f36a9-7560-4f84-9069-46982b653699
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782756696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.3782756696
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.766034550
Short name T176
Test name
Test status
Simulation time 81657537167 ps
CPU time 108.5 seconds
Started Aug 06 07:06:05 PM PDT 24
Finished Aug 06 07:07:54 PM PDT 24
Peak memory 191628 kb
Host smart-b719ca77-6b68-42a6-88e8-9b8dee6a284f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766034550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.766034550
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.268633253
Short name T294
Test name
Test status
Simulation time 217086023235 ps
CPU time 209.41 seconds
Started Aug 06 07:06:05 PM PDT 24
Finished Aug 06 07:09:34 PM PDT 24
Peak memory 183420 kb
Host smart-69fa785e-86c8-45a4-8f35-02c5514d35b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268633253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.268633253
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.4226648873
Short name T323
Test name
Test status
Simulation time 19260470011 ps
CPU time 29.65 seconds
Started Aug 06 07:06:04 PM PDT 24
Finished Aug 06 07:06:33 PM PDT 24
Peak memory 183432 kb
Host smart-e6302c1d-5c18-463c-8fe1-1c43090bc210
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226648873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.4226648873
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.2757914233
Short name T325
Test name
Test status
Simulation time 434085475062 ps
CPU time 650.39 seconds
Started Aug 06 07:06:05 PM PDT 24
Finished Aug 06 07:16:56 PM PDT 24
Peak memory 191636 kb
Host smart-a65be970-a8d6-4029-aa84-bf4f25b43a98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757914233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.2757914233
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.2470864625
Short name T433
Test name
Test status
Simulation time 177505550496 ps
CPU time 136.71 seconds
Started Aug 06 07:05:59 PM PDT 24
Finished Aug 06 07:08:16 PM PDT 24
Peak memory 191624 kb
Host smart-3d94b318-ce32-4080-857d-35dc8d28cffa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470864625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.2470864625
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.4107457776
Short name T384
Test name
Test status
Simulation time 292767099266 ps
CPU time 465.39 seconds
Started Aug 06 07:04:56 PM PDT 24
Finished Aug 06 07:12:41 PM PDT 24
Peak memory 183420 kb
Host smart-00f31b14-805b-4123-8d28-6a35207eac77
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107457776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.4107457776
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.1793493323
Short name T377
Test name
Test status
Simulation time 20528937198 ps
CPU time 7.33 seconds
Started Aug 06 07:04:56 PM PDT 24
Finished Aug 06 07:05:03 PM PDT 24
Peak memory 183440 kb
Host smart-36cee06b-f873-4044-9712-0306bbbb9d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793493323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.1793493323
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.1880122008
Short name T188
Test name
Test status
Simulation time 261447007276 ps
CPU time 1303.48 seconds
Started Aug 06 07:04:56 PM PDT 24
Finished Aug 06 07:26:40 PM PDT 24
Peak memory 191696 kb
Host smart-9a68ae80-2b22-4e4c-a774-5d304e12896c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880122008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.1880122008
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.534342080
Short name T399
Test name
Test status
Simulation time 76760687 ps
CPU time 0.68 seconds
Started Aug 06 07:04:56 PM PDT 24
Finished Aug 06 07:04:57 PM PDT 24
Peak memory 183204 kb
Host smart-54fbe09e-db7d-4950-8d82-ed7e2af1fd2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534342080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.534342080
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.1748096207
Short name T404
Test name
Test status
Simulation time 166290801705 ps
CPU time 112.99 seconds
Started Aug 06 07:06:04 PM PDT 24
Finished Aug 06 07:07:57 PM PDT 24
Peak memory 183428 kb
Host smart-73e271c5-b146-4f3b-b57e-f22ab787f038
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748096207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.1748096207
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.1680886143
Short name T130
Test name
Test status
Simulation time 292590300786 ps
CPU time 385.13 seconds
Started Aug 06 07:06:06 PM PDT 24
Finished Aug 06 07:12:31 PM PDT 24
Peak memory 191620 kb
Host smart-b257120f-7354-47ae-988b-e646ad0bf7aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680886143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.1680886143
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.229487064
Short name T163
Test name
Test status
Simulation time 2876519993349 ps
CPU time 641.37 seconds
Started Aug 06 07:06:04 PM PDT 24
Finished Aug 06 07:16:46 PM PDT 24
Peak memory 191628 kb
Host smart-600f0925-c5e8-4c83-a5c7-0414cfaee47e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229487064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.229487064
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.3545134586
Short name T314
Test name
Test status
Simulation time 60710794030 ps
CPU time 1498.39 seconds
Started Aug 06 07:06:06 PM PDT 24
Finished Aug 06 07:31:05 PM PDT 24
Peak memory 182836 kb
Host smart-7fc264e3-adb4-48f8-825d-0ebda5bdf73c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545134586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.3545134586
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.4112379053
Short name T114
Test name
Test status
Simulation time 99085905646 ps
CPU time 99.8 seconds
Started Aug 06 07:06:04 PM PDT 24
Finished Aug 06 07:07:44 PM PDT 24
Peak memory 191632 kb
Host smart-6728990b-86fa-4af9-9d2a-51c1a3457ee5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112379053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.4112379053
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.2028261639
Short name T124
Test name
Test status
Simulation time 208818339829 ps
CPU time 155.68 seconds
Started Aug 06 07:06:03 PM PDT 24
Finished Aug 06 07:08:39 PM PDT 24
Peak memory 191612 kb
Host smart-40e24803-cc4d-4791-a208-b907f0ab2c70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028261639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.2028261639
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.3928715478
Short name T370
Test name
Test status
Simulation time 202708820830 ps
CPU time 314.06 seconds
Started Aug 06 07:05:01 PM PDT 24
Finished Aug 06 07:10:15 PM PDT 24
Peak memory 183468 kb
Host smart-1ed80456-58c2-46af-be18-d5a4ec6ec40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928715478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.3928715478
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.1981881701
Short name T365
Test name
Test status
Simulation time 76054319 ps
CPU time 0.71 seconds
Started Aug 06 07:05:01 PM PDT 24
Finished Aug 06 07:05:02 PM PDT 24
Peak memory 183248 kb
Host smart-39af7cb4-2938-411d-ad1e-6a6260b60850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981881701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.1981881701
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.2757459810
Short name T375
Test name
Test status
Simulation time 525052582754 ps
CPU time 227.51 seconds
Started Aug 06 07:05:11 PM PDT 24
Finished Aug 06 07:08:59 PM PDT 24
Peak memory 194892 kb
Host smart-4db5ebd3-854e-40b7-8c4c-185a83a9403b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757459810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.2757459810
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all_with_rand_reset.3203783109
Short name T34
Test name
Test status
Simulation time 23725833926 ps
CPU time 129.16 seconds
Started Aug 06 07:05:00 PM PDT 24
Finished Aug 06 07:07:09 PM PDT 24
Peak memory 198172 kb
Host smart-e21c1761-d8fd-42c2-a3ce-8b1f9189c27b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203783109 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all_with_rand_reset.3203783109
Directory /workspace/14.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.rv_timer_random.3884829358
Short name T131
Test name
Test status
Simulation time 113656136019 ps
CPU time 522.48 seconds
Started Aug 06 07:06:04 PM PDT 24
Finished Aug 06 07:14:47 PM PDT 24
Peak memory 191676 kb
Host smart-88407265-b267-4602-b6e3-9adbb63e1f0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884829358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.3884829358
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.2640053539
Short name T128
Test name
Test status
Simulation time 151456007174 ps
CPU time 675.6 seconds
Started Aug 06 07:06:06 PM PDT 24
Finished Aug 06 07:17:22 PM PDT 24
Peak memory 191048 kb
Host smart-c4d0bbda-5dcd-494e-b416-ed612bbd6fb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640053539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.2640053539
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.3591330740
Short name T283
Test name
Test status
Simulation time 337098606432 ps
CPU time 166.13 seconds
Started Aug 06 07:06:05 PM PDT 24
Finished Aug 06 07:08:51 PM PDT 24
Peak memory 191676 kb
Host smart-7d8f3fc1-279c-434c-b36d-074a85d1158b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591330740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.3591330740
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.1229714605
Short name T175
Test name
Test status
Simulation time 8402544710 ps
CPU time 25.34 seconds
Started Aug 06 07:06:04 PM PDT 24
Finished Aug 06 07:06:30 PM PDT 24
Peak memory 194292 kb
Host smart-1f2dfb9a-6657-495e-957a-8014f73e53c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229714605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.1229714605
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.3531936847
Short name T303
Test name
Test status
Simulation time 63624384818 ps
CPU time 108.23 seconds
Started Aug 06 07:06:08 PM PDT 24
Finished Aug 06 07:07:57 PM PDT 24
Peak memory 191664 kb
Host smart-25442e54-dbd5-4202-bb20-94873f6a7162
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531936847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.3531936847
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.2608000648
Short name T317
Test name
Test status
Simulation time 88660232760 ps
CPU time 63.7 seconds
Started Aug 06 07:06:05 PM PDT 24
Finished Aug 06 07:07:09 PM PDT 24
Peak memory 183476 kb
Host smart-193ec334-4e08-4239-beb5-d45ecf49f1ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608000648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.2608000648
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.178597591
Short name T417
Test name
Test status
Simulation time 46021161516 ps
CPU time 63.73 seconds
Started Aug 06 07:05:05 PM PDT 24
Finished Aug 06 07:06:14 PM PDT 24
Peak memory 183408 kb
Host smart-7a6faf15-f84d-4483-996b-13438242fbec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178597591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.178597591
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.4059660209
Short name T356
Test name
Test status
Simulation time 97237049 ps
CPU time 0.69 seconds
Started Aug 06 07:05:11 PM PDT 24
Finished Aug 06 07:05:12 PM PDT 24
Peak memory 183128 kb
Host smart-f21b31b8-b588-487c-9054-63be9467d000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059660209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.4059660209
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.1128459139
Short name T57
Test name
Test status
Simulation time 348744627855 ps
CPU time 318.2 seconds
Started Aug 06 07:05:08 PM PDT 24
Finished Aug 06 07:10:32 PM PDT 24
Peak memory 196724 kb
Host smart-10abd374-88fd-4cdd-8bc9-ed09a8f0c5e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128459139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.1128459139
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/150.rv_timer_random.187527196
Short name T186
Test name
Test status
Simulation time 77819571387 ps
CPU time 65.64 seconds
Started Aug 06 07:06:07 PM PDT 24
Finished Aug 06 07:07:13 PM PDT 24
Peak memory 191672 kb
Host smart-37ef2f55-5402-4bbf-a9fb-8aa62ce0e067
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187527196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.187527196
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.215432379
Short name T233
Test name
Test status
Simulation time 83258522001 ps
CPU time 119.89 seconds
Started Aug 06 07:06:00 PM PDT 24
Finished Aug 06 07:08:00 PM PDT 24
Peak memory 191632 kb
Host smart-6c9dd663-e322-41d7-801c-6271cc5e2e1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215432379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.215432379
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.386231778
Short name T151
Test name
Test status
Simulation time 69305442743 ps
CPU time 123.9 seconds
Started Aug 06 07:06:05 PM PDT 24
Finished Aug 06 07:08:09 PM PDT 24
Peak memory 194860 kb
Host smart-88aa42f2-4f85-4c3d-adea-f1fd45660b3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386231778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.386231778
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.629851055
Short name T338
Test name
Test status
Simulation time 226787146148 ps
CPU time 129.84 seconds
Started Aug 06 07:06:04 PM PDT 24
Finished Aug 06 07:08:14 PM PDT 24
Peak memory 191640 kb
Host smart-bd70864a-f430-4c4c-ac4c-8fdb493e0635
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629851055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.629851055
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.2492886975
Short name T217
Test name
Test status
Simulation time 929259005708 ps
CPU time 302.55 seconds
Started Aug 06 07:06:17 PM PDT 24
Finished Aug 06 07:11:20 PM PDT 24
Peak memory 194240 kb
Host smart-e9b24aa7-aa81-4c06-a634-3957a3ccf3b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492886975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.2492886975
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.3406650502
Short name T209
Test name
Test status
Simulation time 78224344534 ps
CPU time 112.36 seconds
Started Aug 06 07:06:15 PM PDT 24
Finished Aug 06 07:08:08 PM PDT 24
Peak memory 191604 kb
Host smart-836f3031-bd5b-4958-a3c8-4038fd81471d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406650502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.3406650502
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.21249466
Short name T2
Test name
Test status
Simulation time 84901497619 ps
CPU time 142.12 seconds
Started Aug 06 07:06:15 PM PDT 24
Finished Aug 06 07:08:37 PM PDT 24
Peak memory 191540 kb
Host smart-d38fd03f-c7bf-4dd8-8af0-95204718d725
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21249466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.21249466
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.4186111300
Short name T426
Test name
Test status
Simulation time 153717901287 ps
CPU time 205.42 seconds
Started Aug 06 07:05:08 PM PDT 24
Finished Aug 06 07:08:34 PM PDT 24
Peak memory 183508 kb
Host smart-30f56324-955c-4ddb-a04c-87586b853cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186111300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.4186111300
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.3981956278
Short name T165
Test name
Test status
Simulation time 145877836618 ps
CPU time 194.63 seconds
Started Aug 06 07:05:06 PM PDT 24
Finished Aug 06 07:08:20 PM PDT 24
Peak memory 191616 kb
Host smart-98d40c84-9836-4ce4-9977-6d472d17645a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981956278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.3981956278
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.3978757192
Short name T423
Test name
Test status
Simulation time 127169450 ps
CPU time 0.56 seconds
Started Aug 06 07:05:08 PM PDT 24
Finished Aug 06 07:05:08 PM PDT 24
Peak memory 183268 kb
Host smart-e0992a6f-1022-4016-b779-a942070f4bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978757192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.3978757192
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.3475202554
Short name T193
Test name
Test status
Simulation time 77784039304 ps
CPU time 111.94 seconds
Started Aug 06 07:06:16 PM PDT 24
Finished Aug 06 07:08:08 PM PDT 24
Peak memory 191632 kb
Host smart-bb40e850-6c11-468b-97ec-2a39cc9b960d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475202554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.3475202554
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.2131100201
Short name T318
Test name
Test status
Simulation time 61329397440 ps
CPU time 62.8 seconds
Started Aug 06 07:06:15 PM PDT 24
Finished Aug 06 07:07:18 PM PDT 24
Peak memory 191640 kb
Host smart-d8de5c31-88bb-4b3b-b441-b44e586cea47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131100201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.2131100201
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.1562104299
Short name T205
Test name
Test status
Simulation time 171589462891 ps
CPU time 526.85 seconds
Started Aug 06 07:06:21 PM PDT 24
Finished Aug 06 07:15:08 PM PDT 24
Peak memory 191636 kb
Host smart-80b71a9d-d258-4f7a-9e48-3d481ae18917
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562104299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.1562104299
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.2910434155
Short name T110
Test name
Test status
Simulation time 271645491951 ps
CPU time 585.84 seconds
Started Aug 06 07:06:22 PM PDT 24
Finished Aug 06 07:16:08 PM PDT 24
Peak memory 191668 kb
Host smart-5295e7f3-1471-48f1-a971-b65a7e41de4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910434155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.2910434155
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.1209338570
Short name T416
Test name
Test status
Simulation time 324310405166 ps
CPU time 130.36 seconds
Started Aug 06 07:05:08 PM PDT 24
Finished Aug 06 07:07:19 PM PDT 24
Peak memory 183420 kb
Host smart-e8adf5a1-c9c7-4913-beaf-877b37971224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209338570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.1209338570
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.1014238139
Short name T181
Test name
Test status
Simulation time 97471622181 ps
CPU time 230.43 seconds
Started Aug 06 07:04:58 PM PDT 24
Finished Aug 06 07:08:49 PM PDT 24
Peak memory 195068 kb
Host smart-1d185052-1145-472a-a234-73610e3922f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014238139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.1014238139
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.87357705
Short name T107
Test name
Test status
Simulation time 157387213058 ps
CPU time 101.22 seconds
Started Aug 06 07:05:11 PM PDT 24
Finished Aug 06 07:06:52 PM PDT 24
Peak memory 195336 kb
Host smart-0a633731-5b47-49a0-a09b-4982d2df3281
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87357705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all.87357705
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.125333027
Short name T32
Test name
Test status
Simulation time 85761814919 ps
CPU time 435.54 seconds
Started Aug 06 07:05:14 PM PDT 24
Finished Aug 06 07:12:30 PM PDT 24
Peak memory 198100 kb
Host smart-d26e0fe8-ab8f-4cd0-b33d-cbbd0aafc259
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125333027 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all_with_rand_reset.125333027
Directory /workspace/17.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.4219671752
Short name T104
Test name
Test status
Simulation time 266721197073 ps
CPU time 1447.93 seconds
Started Aug 06 07:06:21 PM PDT 24
Finished Aug 06 07:30:29 PM PDT 24
Peak memory 191684 kb
Host smart-8ecc7a20-a217-4501-be3f-2a13078d9d12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219671752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.4219671752
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.1880959574
Short name T439
Test name
Test status
Simulation time 61357096821 ps
CPU time 44.29 seconds
Started Aug 06 07:06:22 PM PDT 24
Finished Aug 06 07:07:06 PM PDT 24
Peak memory 183284 kb
Host smart-0c9d9edb-6b29-41af-9fa5-9136344b5522
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880959574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.1880959574
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.173565191
Short name T132
Test name
Test status
Simulation time 141677677108 ps
CPU time 267.03 seconds
Started Aug 06 07:06:21 PM PDT 24
Finished Aug 06 07:10:48 PM PDT 24
Peak memory 191660 kb
Host smart-59aec80e-430a-4307-b4d0-a6f5246354c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173565191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.173565191
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.1629029313
Short name T67
Test name
Test status
Simulation time 130492332016 ps
CPU time 2677.57 seconds
Started Aug 06 07:06:26 PM PDT 24
Finished Aug 06 07:51:04 PM PDT 24
Peak memory 191672 kb
Host smart-cc8090b5-4aa0-472a-b044-70fe7233a21c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629029313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.1629029313
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.427461536
Short name T200
Test name
Test status
Simulation time 244816956904 ps
CPU time 208.68 seconds
Started Aug 06 07:06:26 PM PDT 24
Finished Aug 06 07:09:55 PM PDT 24
Peak memory 191672 kb
Host smart-affaa2ba-ebb6-4ecf-88fe-1d7717f81663
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427461536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.427461536
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.561650683
Short name T169
Test name
Test status
Simulation time 102143112728 ps
CPU time 154.23 seconds
Started Aug 06 07:06:23 PM PDT 24
Finished Aug 06 07:08:58 PM PDT 24
Peak memory 191632 kb
Host smart-9dcfc49c-2304-46d9-97a0-711614aa362c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561650683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.561650683
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.3456885741
Short name T447
Test name
Test status
Simulation time 270158720815 ps
CPU time 416.9 seconds
Started Aug 06 07:05:05 PM PDT 24
Finished Aug 06 07:12:02 PM PDT 24
Peak memory 183424 kb
Host smart-fee0a19b-e39a-42b3-bae6-3aeeddc1bba8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456885741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.3456885741
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.1021805096
Short name T449
Test name
Test status
Simulation time 58765657832 ps
CPU time 89.44 seconds
Started Aug 06 07:05:07 PM PDT 24
Finished Aug 06 07:06:37 PM PDT 24
Peak memory 183340 kb
Host smart-16c6a198-2781-4afc-bcc7-c3b387661995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021805096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.1021805096
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.3606879789
Short name T292
Test name
Test status
Simulation time 293914697484 ps
CPU time 504.29 seconds
Started Aug 06 07:05:07 PM PDT 24
Finished Aug 06 07:13:31 PM PDT 24
Peak memory 195436 kb
Host smart-f48d9a01-45b0-4704-b650-30d573caa022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606879789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.3606879789
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.2398629161
Short name T225
Test name
Test status
Simulation time 207416921426 ps
CPU time 88.5 seconds
Started Aug 06 07:04:59 PM PDT 24
Finished Aug 06 07:06:28 PM PDT 24
Peak memory 191620 kb
Host smart-f0e87435-fc60-480e-ac54-c835d2271b09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398629161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.2398629161
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/180.rv_timer_random.3601876644
Short name T301
Test name
Test status
Simulation time 132500214197 ps
CPU time 742.35 seconds
Started Aug 06 07:06:23 PM PDT 24
Finished Aug 06 07:18:45 PM PDT 24
Peak memory 191668 kb
Host smart-9a502368-fd24-4a05-9075-1a1d3cf3212c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601876644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.3601876644
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.1929359781
Short name T170
Test name
Test status
Simulation time 114142031822 ps
CPU time 242.47 seconds
Started Aug 06 07:06:22 PM PDT 24
Finished Aug 06 07:10:25 PM PDT 24
Peak memory 191668 kb
Host smart-60768124-fe05-4294-9fe3-ef26c8b2f63f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929359781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.1929359781
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.1382051098
Short name T199
Test name
Test status
Simulation time 44440124019 ps
CPU time 102.96 seconds
Started Aug 06 07:06:27 PM PDT 24
Finished Aug 06 07:08:10 PM PDT 24
Peak memory 183456 kb
Host smart-6fc0c07a-6f39-4c3e-a6dc-13bea73a18d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382051098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.1382051098
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.1503899856
Short name T39
Test name
Test status
Simulation time 506574313143 ps
CPU time 291.74 seconds
Started Aug 06 07:06:28 PM PDT 24
Finished Aug 06 07:11:20 PM PDT 24
Peak memory 191656 kb
Host smart-2c6ad36c-e6e0-4a97-add2-99763ded538b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503899856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.1503899856
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.1520079187
Short name T147
Test name
Test status
Simulation time 66918639627 ps
CPU time 110.11 seconds
Started Aug 06 07:06:26 PM PDT 24
Finished Aug 06 07:08:16 PM PDT 24
Peak memory 191532 kb
Host smart-f563d576-df93-49b1-be98-84c49feb4f1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520079187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.1520079187
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.1684456122
Short name T241
Test name
Test status
Simulation time 34999057539 ps
CPU time 25.1 seconds
Started Aug 06 07:06:28 PM PDT 24
Finished Aug 06 07:06:54 PM PDT 24
Peak memory 183468 kb
Host smart-cbd61687-fe96-4f9a-a6e6-fe2a59624531
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684456122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.1684456122
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.3566257894
Short name T276
Test name
Test status
Simulation time 148978599378 ps
CPU time 46.08 seconds
Started Aug 06 07:06:28 PM PDT 24
Finished Aug 06 07:07:14 PM PDT 24
Peak memory 183456 kb
Host smart-13eb3ec3-5791-467e-8456-a600e3dbd028
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566257894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.3566257894
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.2851017333
Short name T146
Test name
Test status
Simulation time 404297286843 ps
CPU time 560.4 seconds
Started Aug 06 07:05:11 PM PDT 24
Finished Aug 06 07:14:32 PM PDT 24
Peak memory 183344 kb
Host smart-ee0f6bd3-7440-4195-82ad-e2316d78d5e1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851017333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.2851017333
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.3626143006
Short name T19
Test name
Test status
Simulation time 102114709558 ps
CPU time 15.1 seconds
Started Aug 06 07:05:14 PM PDT 24
Finished Aug 06 07:05:29 PM PDT 24
Peak memory 183516 kb
Host smart-cf86a4c3-d0db-448e-ac07-148eb4524ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626143006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.3626143006
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.1875666293
Short name T243
Test name
Test status
Simulation time 45546493547 ps
CPU time 71.87 seconds
Started Aug 06 07:05:07 PM PDT 24
Finished Aug 06 07:06:19 PM PDT 24
Peak memory 191644 kb
Host smart-7230f86e-dd6f-4c0e-8caa-5b21c411512a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875666293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.1875666293
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.3260839804
Short name T319
Test name
Test status
Simulation time 6091561034 ps
CPU time 8.79 seconds
Started Aug 06 07:05:07 PM PDT 24
Finished Aug 06 07:05:16 PM PDT 24
Peak memory 183460 kb
Host smart-6a3ac3b1-ddeb-4da3-89f8-c6aaeb90dc2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260839804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.3260839804
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/192.rv_timer_random.3363059547
Short name T406
Test name
Test status
Simulation time 1113984759581 ps
CPU time 423.55 seconds
Started Aug 06 07:06:30 PM PDT 24
Finished Aug 06 07:13:33 PM PDT 24
Peak memory 191592 kb
Host smart-a7be11b5-419b-4a79-bb8e-99cb06cb07e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363059547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.3363059547
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.2956757312
Short name T310
Test name
Test status
Simulation time 142295096682 ps
CPU time 1289.2 seconds
Started Aug 06 07:06:31 PM PDT 24
Finished Aug 06 07:28:00 PM PDT 24
Peak memory 191616 kb
Host smart-ee1c8667-dae9-491d-944e-8684e6b59e6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956757312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.2956757312
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.3449649338
Short name T343
Test name
Test status
Simulation time 223431491027 ps
CPU time 193.88 seconds
Started Aug 06 07:06:30 PM PDT 24
Finished Aug 06 07:09:45 PM PDT 24
Peak memory 191668 kb
Host smart-594ee776-220c-447c-9b69-1d690eef1770
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449649338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.3449649338
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.908978861
Short name T195
Test name
Test status
Simulation time 274489989463 ps
CPU time 544.34 seconds
Started Aug 06 07:06:30 PM PDT 24
Finished Aug 06 07:15:34 PM PDT 24
Peak memory 191624 kb
Host smart-f0f7abaf-27ff-4772-8acc-2be02f028305
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908978861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.908978861
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.1935733689
Short name T115
Test name
Test status
Simulation time 683216242787 ps
CPU time 197.25 seconds
Started Aug 06 07:06:30 PM PDT 24
Finished Aug 06 07:09:47 PM PDT 24
Peak memory 195284 kb
Host smart-3c94776a-12ee-41ed-af01-08d5782bd3e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935733689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.1935733689
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.2973497593
Short name T235
Test name
Test status
Simulation time 50413666928 ps
CPU time 89.3 seconds
Started Aug 06 07:06:31 PM PDT 24
Finished Aug 06 07:08:00 PM PDT 24
Peak memory 183400 kb
Host smart-10445ac4-60e5-4d3a-bfd4-811923a5871f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973497593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.2973497593
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.2220364449
Short name T50
Test name
Test status
Simulation time 146602705475 ps
CPU time 601.12 seconds
Started Aug 06 07:06:29 PM PDT 24
Finished Aug 06 07:16:31 PM PDT 24
Peak memory 191656 kb
Host smart-a46eda02-72d5-40f5-8a7b-b1834afa5415
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220364449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.2220364449
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.643820280
Short name T239
Test name
Test status
Simulation time 235985618423 ps
CPU time 979.13 seconds
Started Aug 06 07:06:29 PM PDT 24
Finished Aug 06 07:22:48 PM PDT 24
Peak memory 194056 kb
Host smart-be6d711c-a65f-4c6a-9008-0d96fcf619bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643820280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.643820280
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.4188170228
Short name T180
Test name
Test status
Simulation time 77460995564 ps
CPU time 112.85 seconds
Started Aug 06 07:05:03 PM PDT 24
Finished Aug 06 07:06:56 PM PDT 24
Peak memory 183660 kb
Host smart-01a6c552-7ab6-4299-9c59-8f3c4496decd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188170228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.4188170228
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.360813299
Short name T367
Test name
Test status
Simulation time 283167069308 ps
CPU time 109.54 seconds
Started Aug 06 07:05:03 PM PDT 24
Finished Aug 06 07:06:53 PM PDT 24
Peak memory 183676 kb
Host smart-96496bbb-e81d-4643-a945-1d6dd89fccb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360813299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.360813299
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.702805605
Short name T327
Test name
Test status
Simulation time 20297893900 ps
CPU time 12.36 seconds
Started Aug 06 07:05:04 PM PDT 24
Finished Aug 06 07:05:16 PM PDT 24
Peak memory 183668 kb
Host smart-fe38c40c-4f27-4666-81a4-0080d71bd3b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702805605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.702805605
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.2089793346
Short name T361
Test name
Test status
Simulation time 612870773 ps
CPU time 1.32 seconds
Started Aug 06 07:05:01 PM PDT 24
Finished Aug 06 07:05:02 PM PDT 24
Peak memory 183188 kb
Host smart-e69f7dac-b3aa-498e-b88c-8f03aa9ca1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089793346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.2089793346
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.1152758304
Short name T13
Test name
Test status
Simulation time 381599709 ps
CPU time 1.02 seconds
Started Aug 06 07:04:53 PM PDT 24
Finished Aug 06 07:04:54 PM PDT 24
Peak memory 214072 kb
Host smart-c670bebe-ecdd-48ca-bfc5-6f50bd5a889b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152758304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.1152758304
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all_with_rand_reset.244336274
Short name T92
Test name
Test status
Simulation time 92004467543 ps
CPU time 1269.19 seconds
Started Aug 06 07:05:00 PM PDT 24
Finished Aug 06 07:26:10 PM PDT 24
Peak memory 206332 kb
Host smart-b5a6d041-348c-412d-824a-94277a928af8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244336274 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all_with_rand_reset.244336274
Directory /workspace/2.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.1660318949
Short name T295
Test name
Test status
Simulation time 641856828387 ps
CPU time 999.62 seconds
Started Aug 06 07:05:11 PM PDT 24
Finished Aug 06 07:21:51 PM PDT 24
Peak memory 183316 kb
Host smart-14377e26-c560-41d6-b438-1d5b4ac1be0b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660318949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.1660318949
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.2945872075
Short name T376
Test name
Test status
Simulation time 159183573684 ps
CPU time 63.25 seconds
Started Aug 06 07:05:01 PM PDT 24
Finished Aug 06 07:06:04 PM PDT 24
Peak memory 183392 kb
Host smart-213d8dbb-3c30-4a76-8939-90732d7edad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945872075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.2945872075
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.543063875
Short name T332
Test name
Test status
Simulation time 82792581560 ps
CPU time 143.74 seconds
Started Aug 06 07:05:00 PM PDT 24
Finished Aug 06 07:07:23 PM PDT 24
Peak memory 191636 kb
Host smart-b4500f17-221e-4cde-b486-83f674f410c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543063875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.543063875
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.1693906010
Short name T434
Test name
Test status
Simulation time 16816170500 ps
CPU time 31.57 seconds
Started Aug 06 07:05:14 PM PDT 24
Finished Aug 06 07:05:46 PM PDT 24
Peak memory 191708 kb
Host smart-04884a34-103b-40f6-9f1f-4239ec17002f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693906010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.1693906010
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.3925718945
Short name T60
Test name
Test status
Simulation time 672686501533 ps
CPU time 886.76 seconds
Started Aug 06 07:05:09 PM PDT 24
Finished Aug 06 07:19:56 PM PDT 24
Peak memory 191604 kb
Host smart-a9622a6b-2c81-4c56-ab10-f7f30debca56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925718945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.3925718945
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.2095045579
Short name T446
Test name
Test status
Simulation time 247829534378 ps
CPU time 122.67 seconds
Started Aug 06 07:05:07 PM PDT 24
Finished Aug 06 07:07:10 PM PDT 24
Peak memory 183276 kb
Host smart-6227c94e-fcb6-4ec5-a378-173a5bc81a7e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095045579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.2095045579
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.2995310270
Short name T396
Test name
Test status
Simulation time 132174612023 ps
CPU time 90.51 seconds
Started Aug 06 07:05:08 PM PDT 24
Finished Aug 06 07:06:39 PM PDT 24
Peak memory 183420 kb
Host smart-d1f37e25-d8f6-43e0-8cdb-a4d5cbf107ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995310270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.2995310270
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.755470165
Short name T228
Test name
Test status
Simulation time 139609643175 ps
CPU time 255.94 seconds
Started Aug 06 07:04:59 PM PDT 24
Finished Aug 06 07:09:15 PM PDT 24
Peak memory 191632 kb
Host smart-3a57d181-97db-4675-8842-0b399c325859
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755470165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.755470165
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.1978997285
Short name T342
Test name
Test status
Simulation time 47785802394 ps
CPU time 20.81 seconds
Started Aug 06 07:05:08 PM PDT 24
Finished Aug 06 07:05:29 PM PDT 24
Peak memory 183460 kb
Host smart-dc65bff5-ec61-44b3-bdbe-9b25a054b32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978997285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.1978997285
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.2435372575
Short name T451
Test name
Test status
Simulation time 255840641081 ps
CPU time 690.06 seconds
Started Aug 06 07:05:08 PM PDT 24
Finished Aug 06 07:16:38 PM PDT 24
Peak memory 196840 kb
Host smart-7e5e49d6-1888-4ba9-8cae-6d290ba7d1ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435372575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.2435372575
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.703845963
Short name T280
Test name
Test status
Simulation time 519154610997 ps
CPU time 375.51 seconds
Started Aug 06 07:05:08 PM PDT 24
Finished Aug 06 07:11:23 PM PDT 24
Peak memory 183272 kb
Host smart-1d28a3dc-cf0a-47d0-ac6e-67650848bac2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703845963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.rv_timer_cfg_update_on_fly.703845963
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_random.4086836581
Short name T227
Test name
Test status
Simulation time 406386863353 ps
CPU time 246.76 seconds
Started Aug 06 07:05:08 PM PDT 24
Finished Aug 06 07:09:15 PM PDT 24
Peak memory 191620 kb
Host smart-bf733377-4dca-4e04-8a22-e0f0cc813915
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086836581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.4086836581
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.273368675
Short name T363
Test name
Test status
Simulation time 16548660340 ps
CPU time 14.8 seconds
Started Aug 06 07:05:07 PM PDT 24
Finished Aug 06 07:05:22 PM PDT 24
Peak memory 191556 kb
Host smart-647ef1aa-3d79-4fc5-81cc-ceaeeabfe67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273368675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.273368675
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.1908839976
Short name T21
Test name
Test status
Simulation time 409794761325 ps
CPU time 365.83 seconds
Started Aug 06 07:05:05 PM PDT 24
Finished Aug 06 07:11:11 PM PDT 24
Peak memory 195840 kb
Host smart-bc137b6f-07e7-4906-9d3a-fb00beb4b0b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908839976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.1908839976
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.1219369920
Short name T70
Test name
Test status
Simulation time 198415999028 ps
CPU time 220.92 seconds
Started Aug 06 07:05:07 PM PDT 24
Finished Aug 06 07:08:48 PM PDT 24
Peak memory 183276 kb
Host smart-d1ae9937-6fac-46ef-a642-d0e859c283ee
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219369920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.1219369920
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.2951870482
Short name T355
Test name
Test status
Simulation time 107420922761 ps
CPU time 156.82 seconds
Started Aug 06 07:05:00 PM PDT 24
Finished Aug 06 07:07:37 PM PDT 24
Peak memory 183436 kb
Host smart-11a0bc71-2969-462c-a756-0a9f50be6465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951870482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.2951870482
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.1883875108
Short name T321
Test name
Test status
Simulation time 179933860992 ps
CPU time 75.97 seconds
Started Aug 06 07:05:04 PM PDT 24
Finished Aug 06 07:06:20 PM PDT 24
Peak memory 195464 kb
Host smart-a9fb4d7c-90e0-4cb2-a004-422bdef31694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883875108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.1883875108
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.1473343780
Short name T309
Test name
Test status
Simulation time 346730320407 ps
CPU time 302.81 seconds
Started Aug 06 07:05:08 PM PDT 24
Finished Aug 06 07:10:11 PM PDT 24
Peak memory 183252 kb
Host smart-8234c5df-1c41-48bb-be10-35b2e27b0f19
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473343780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.1473343780
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.3351336382
Short name T374
Test name
Test status
Simulation time 40665458320 ps
CPU time 62.32 seconds
Started Aug 06 07:05:06 PM PDT 24
Finished Aug 06 07:06:08 PM PDT 24
Peak memory 183292 kb
Host smart-fc3c6bc2-1ae2-4e4e-9911-a34537c3958e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351336382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.3351336382
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.2621348664
Short name T240
Test name
Test status
Simulation time 53636867118 ps
CPU time 84.09 seconds
Started Aug 06 07:05:09 PM PDT 24
Finished Aug 06 07:06:33 PM PDT 24
Peak memory 183524 kb
Host smart-4b385d9c-99f5-4d4d-bec5-398f7f3ff484
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621348664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.2621348664
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.159697760
Short name T255
Test name
Test status
Simulation time 80325931407 ps
CPU time 61.63 seconds
Started Aug 06 07:05:00 PM PDT 24
Finished Aug 06 07:06:02 PM PDT 24
Peak memory 183408 kb
Host smart-63b524f6-8ce8-4edc-af88-a9a4c07ac24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159697760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.159697760
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.629426173
Short name T444
Test name
Test status
Simulation time 330946513129 ps
CPU time 206.3 seconds
Started Aug 06 07:05:08 PM PDT 24
Finished Aug 06 07:08:34 PM PDT 24
Peak memory 195104 kb
Host smart-e4952c77-41c6-438f-8bc7-462d325da1e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629426173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.
629426173
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.1983813296
Short name T333
Test name
Test status
Simulation time 10514698987 ps
CPU time 16.76 seconds
Started Aug 06 07:05:06 PM PDT 24
Finished Aug 06 07:05:23 PM PDT 24
Peak memory 183420 kb
Host smart-a04aefac-f628-4e35-acf3-f5374c1ec2f6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983813296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.1983813296
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.1639913396
Short name T371
Test name
Test status
Simulation time 408600770995 ps
CPU time 171.74 seconds
Started Aug 06 07:05:06 PM PDT 24
Finished Aug 06 07:07:57 PM PDT 24
Peak memory 183408 kb
Host smart-a5b3e7b2-c5b2-4707-bd83-9e2c48bfd446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639913396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.1639913396
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.1972666281
Short name T102
Test name
Test status
Simulation time 304213510612 ps
CPU time 394.12 seconds
Started Aug 06 07:05:11 PM PDT 24
Finished Aug 06 07:11:46 PM PDT 24
Peak memory 191548 kb
Host smart-77458b68-4600-49d3-8d4c-63483d259428
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972666281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.1972666281
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.3288017363
Short name T226
Test name
Test status
Simulation time 63845533986 ps
CPU time 149.47 seconds
Started Aug 06 07:05:03 PM PDT 24
Finished Aug 06 07:07:32 PM PDT 24
Peak memory 191660 kb
Host smart-585c9375-7621-4e78-82dd-8ce30b3fa6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288017363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.3288017363
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.816693091
Short name T346
Test name
Test status
Simulation time 193649656292 ps
CPU time 324.63 seconds
Started Aug 06 07:05:05 PM PDT 24
Finished Aug 06 07:10:30 PM PDT 24
Peak memory 183400 kb
Host smart-82ef113c-c3ef-4d49-bef9-3badb2615e00
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816693091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.rv_timer_cfg_update_on_fly.816693091
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.2021171602
Short name T359
Test name
Test status
Simulation time 92311866306 ps
CPU time 116.06 seconds
Started Aug 06 07:05:01 PM PDT 24
Finished Aug 06 07:06:57 PM PDT 24
Peak memory 183392 kb
Host smart-20be1bb6-a967-4e07-983d-4d8818f411e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021171602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.2021171602
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.2983813243
Short name T112
Test name
Test status
Simulation time 1156806288179 ps
CPU time 258.37 seconds
Started Aug 06 07:05:06 PM PDT 24
Finished Aug 06 07:09:25 PM PDT 24
Peak memory 191608 kb
Host smart-5a0dfc7a-9987-4354-8e1c-83a9406651ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983813243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.2983813243
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.3447068950
Short name T430
Test name
Test status
Simulation time 221917183 ps
CPU time 0.61 seconds
Started Aug 06 07:04:57 PM PDT 24
Finished Aug 06 07:04:58 PM PDT 24
Peak memory 183208 kb
Host smart-0f9dac14-2df0-4cbd-8966-9ef750cbed17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447068950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.3447068950
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.177557536
Short name T265
Test name
Test status
Simulation time 150887137635 ps
CPU time 375.55 seconds
Started Aug 06 07:05:05 PM PDT 24
Finished Aug 06 07:11:21 PM PDT 24
Peak memory 191600 kb
Host smart-0547fe50-5d9d-4f40-98f9-26e141a3db09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177557536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all.
177557536
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.3364707743
Short name T26
Test name
Test status
Simulation time 85177760398 ps
CPU time 110.99 seconds
Started Aug 06 07:05:01 PM PDT 24
Finished Aug 06 07:06:52 PM PDT 24
Peak memory 183408 kb
Host smart-9fd6cf2c-57ff-4182-b5b2-471906d7d7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364707743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.3364707743
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.3244418818
Short name T305
Test name
Test status
Simulation time 283224202999 ps
CPU time 257.54 seconds
Started Aug 06 07:05:04 PM PDT 24
Finished Aug 06 07:09:22 PM PDT 24
Peak memory 183424 kb
Host smart-bceb7651-bd57-4d87-ab54-572b4a745092
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244418818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.3244418818
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.1260584190
Short name T49
Test name
Test status
Simulation time 454598430722 ps
CPU time 145.62 seconds
Started Aug 06 07:04:59 PM PDT 24
Finished Aug 06 07:07:25 PM PDT 24
Peak memory 183448 kb
Host smart-785d5bdb-2ee0-4fdb-aab9-46c9d62ead0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260584190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.1260584190
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.935530837
Short name T41
Test name
Test status
Simulation time 141304499626 ps
CPU time 70.85 seconds
Started Aug 06 07:05:05 PM PDT 24
Finished Aug 06 07:06:15 PM PDT 24
Peak memory 183440 kb
Host smart-e2d0d99b-76bb-476c-97d9-c0074f6436a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935530837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.935530837
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.1442361825
Short name T260
Test name
Test status
Simulation time 588226895556 ps
CPU time 216.64 seconds
Started Aug 06 07:05:05 PM PDT 24
Finished Aug 06 07:08:42 PM PDT 24
Peak memory 191640 kb
Host smart-83e3ce42-cd59-4fbd-9f16-fa984fd2914e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442361825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.1442361825
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.1265645908
Short name T328
Test name
Test status
Simulation time 443585956565 ps
CPU time 647.77 seconds
Started Aug 06 07:05:08 PM PDT 24
Finished Aug 06 07:16:01 PM PDT 24
Peak memory 191636 kb
Host smart-466c2c36-4b17-4d2b-be9d-89ef973f4b5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265645908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.1265645908
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.97526782
Short name T329
Test name
Test status
Simulation time 349083411887 ps
CPU time 177.24 seconds
Started Aug 06 07:05:27 PM PDT 24
Finished Aug 06 07:08:24 PM PDT 24
Peak memory 183412 kb
Host smart-97199974-7ea9-42d1-9db6-f16eebdc09b1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97526782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.rv_timer_cfg_update_on_fly.97526782
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.3260899456
Short name T386
Test name
Test status
Simulation time 165402967217 ps
CPU time 48.83 seconds
Started Aug 06 07:05:07 PM PDT 24
Finished Aug 06 07:05:56 PM PDT 24
Peak memory 183436 kb
Host smart-93c2f742-016f-470e-9d7f-9330d49cd244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260899456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.3260899456
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.1203757740
Short name T203
Test name
Test status
Simulation time 158450647472 ps
CPU time 221.02 seconds
Started Aug 06 07:05:01 PM PDT 24
Finished Aug 06 07:08:42 PM PDT 24
Peak memory 191624 kb
Host smart-cc892f7f-4fc9-4aea-994b-20fe1f8929bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203757740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.1203757740
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.2285497814
Short name T445
Test name
Test status
Simulation time 12436263 ps
CPU time 0.57 seconds
Started Aug 06 07:05:27 PM PDT 24
Finished Aug 06 07:05:27 PM PDT 24
Peak memory 183248 kb
Host smart-51283a02-b835-4c16-8e92-d72419c28787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285497814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.2285497814
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.2595722109
Short name T249
Test name
Test status
Simulation time 497472776403 ps
CPU time 238.77 seconds
Started Aug 06 07:05:00 PM PDT 24
Finished Aug 06 07:08:59 PM PDT 24
Peak memory 183368 kb
Host smart-0307847c-b66f-415c-a0b1-a0bfcd7a1fa4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595722109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.2595722109
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.1160195769
Short name T385
Test name
Test status
Simulation time 364856800451 ps
CPU time 238.56 seconds
Started Aug 06 07:04:53 PM PDT 24
Finished Aug 06 07:08:52 PM PDT 24
Peak memory 183428 kb
Host smart-e849097f-6495-44b8-a0ff-6ccfbcc10039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160195769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.1160195769
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.3921810134
Short name T271
Test name
Test status
Simulation time 40404195844 ps
CPU time 557.7 seconds
Started Aug 06 07:05:02 PM PDT 24
Finished Aug 06 07:14:19 PM PDT 24
Peak memory 183420 kb
Host smart-16c7bcb8-204e-4dfb-95d9-71505e747ab9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921810134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.3921810134
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.1713320419
Short name T428
Test name
Test status
Simulation time 214101686 ps
CPU time 1.74 seconds
Started Aug 06 07:04:53 PM PDT 24
Finished Aug 06 07:04:55 PM PDT 24
Peak memory 183356 kb
Host smart-f364ee7c-b439-4386-a649-566b31620438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713320419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.1713320419
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.5785071
Short name T16
Test name
Test status
Simulation time 180543803 ps
CPU time 0.93 seconds
Started Aug 06 07:04:52 PM PDT 24
Finished Aug 06 07:04:54 PM PDT 24
Peak memory 215176 kb
Host smart-f50825aa-a0bd-4fd6-a848-157cac18faf1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5785071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.5785071
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.3061029528
Short name T61
Test name
Test status
Simulation time 196714036072 ps
CPU time 65.39 seconds
Started Aug 06 07:04:53 PM PDT 24
Finished Aug 06 07:05:59 PM PDT 24
Peak memory 194416 kb
Host smart-da2b3654-edb0-44c9-94cb-a4c94a5e7c1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061029528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
3061029528
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.3515903986
Short name T168
Test name
Test status
Simulation time 137303395080 ps
CPU time 113.78 seconds
Started Aug 06 07:05:16 PM PDT 24
Finished Aug 06 07:07:10 PM PDT 24
Peak memory 183392 kb
Host smart-c7ec6a12-0718-45f7-a2c3-85479d19d6bc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515903986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.3515903986
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.3617050314
Short name T381
Test name
Test status
Simulation time 37303439350 ps
CPU time 49.96 seconds
Started Aug 06 07:05:12 PM PDT 24
Finished Aug 06 07:06:02 PM PDT 24
Peak memory 183496 kb
Host smart-35a82efa-757f-44e2-84f8-b221749b9965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617050314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.3617050314
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.1861238833
Short name T262
Test name
Test status
Simulation time 445829103058 ps
CPU time 87.54 seconds
Started Aug 06 07:05:21 PM PDT 24
Finished Aug 06 07:06:49 PM PDT 24
Peak memory 191636 kb
Host smart-52609897-a902-40dc-8597-937926c920d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861238833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.1861238833
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.1103897330
Short name T335
Test name
Test status
Simulation time 5911698037 ps
CPU time 3.23 seconds
Started Aug 06 07:05:13 PM PDT 24
Finished Aug 06 07:05:17 PM PDT 24
Peak memory 191720 kb
Host smart-d3058bac-205c-4e39-b9a8-da81e3f902c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103897330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.1103897330
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.1298467560
Short name T161
Test name
Test status
Simulation time 420045948384 ps
CPU time 475.82 seconds
Started Aug 06 07:05:26 PM PDT 24
Finished Aug 06 07:13:22 PM PDT 24
Peak memory 191644 kb
Host smart-19b85b1d-cd9d-444a-ba53-7d94efcf1163
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298467560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.1298467560
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.2097933114
Short name T336
Test name
Test status
Simulation time 12875293518 ps
CPU time 20.19 seconds
Started Aug 06 07:05:13 PM PDT 24
Finished Aug 06 07:05:34 PM PDT 24
Peak memory 183392 kb
Host smart-c9e50182-b80a-460e-8470-73a608d228ea
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097933114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.2097933114
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.1382679941
Short name T429
Test name
Test status
Simulation time 351557552546 ps
CPU time 138.52 seconds
Started Aug 06 07:05:14 PM PDT 24
Finished Aug 06 07:07:33 PM PDT 24
Peak memory 183440 kb
Host smart-d9243b5c-638f-49ba-bcae-79be1299eef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382679941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.1382679941
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.1829531218
Short name T126
Test name
Test status
Simulation time 44951491749 ps
CPU time 62.5 seconds
Started Aug 06 07:05:28 PM PDT 24
Finished Aug 06 07:06:31 PM PDT 24
Peak memory 191652 kb
Host smart-0e20483f-489e-4fc8-bc9d-848dc8dc61fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829531218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.1829531218
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.3980952103
Short name T162
Test name
Test status
Simulation time 198271504675 ps
CPU time 112.33 seconds
Started Aug 06 07:05:23 PM PDT 24
Finished Aug 06 07:07:15 PM PDT 24
Peak memory 191660 kb
Host smart-76f73d5d-718b-4004-b6d0-6921b51d8612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980952103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.3980952103
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all_with_rand_reset.2379880451
Short name T42
Test name
Test status
Simulation time 24297202654 ps
CPU time 88.85 seconds
Started Aug 06 07:05:18 PM PDT 24
Finished Aug 06 07:06:47 PM PDT 24
Peak memory 198116 kb
Host smart-850836cd-a7e0-4388-8691-cac040b613c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379880451 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all_with_rand_reset.2379880451
Directory /workspace/31.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.573605952
Short name T282
Test name
Test status
Simulation time 326196403372 ps
CPU time 519.24 seconds
Started Aug 06 07:05:18 PM PDT 24
Finished Aug 06 07:13:58 PM PDT 24
Peak memory 183472 kb
Host smart-d7b5feda-a5c4-46f1-b3e9-a4afb6afee55
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573605952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.rv_timer_cfg_update_on_fly.573605952
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.3986271961
Short name T448
Test name
Test status
Simulation time 574632543182 ps
CPU time 176.04 seconds
Started Aug 06 07:05:13 PM PDT 24
Finished Aug 06 07:08:09 PM PDT 24
Peak memory 183436 kb
Host smart-50feaa75-4c51-496c-b328-2620e6e9955c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986271961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.3986271961
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.462884165
Short name T419
Test name
Test status
Simulation time 82006718263 ps
CPU time 320.76 seconds
Started Aug 06 07:05:19 PM PDT 24
Finished Aug 06 07:10:40 PM PDT 24
Peak memory 191612 kb
Host smart-3a753c08-967b-4d06-af4c-ccbf9eb870cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462884165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.462884165
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.1619265185
Short name T388
Test name
Test status
Simulation time 199638472 ps
CPU time 0.65 seconds
Started Aug 06 07:05:32 PM PDT 24
Finished Aug 06 07:05:33 PM PDT 24
Peak memory 183060 kb
Host smart-96978461-dfd6-4c93-8f9d-6b05a9d02c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619265185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.1619265185
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.3761487653
Short name T389
Test name
Test status
Simulation time 839795851586 ps
CPU time 394.21 seconds
Started Aug 06 07:05:26 PM PDT 24
Finished Aug 06 07:12:00 PM PDT 24
Peak memory 183448 kb
Host smart-f47b834f-e0d8-4eb6-9da3-9f481eca0d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761487653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.3761487653
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.3514173806
Short name T431
Test name
Test status
Simulation time 109015253294 ps
CPU time 168.71 seconds
Started Aug 06 07:05:26 PM PDT 24
Finished Aug 06 07:08:15 PM PDT 24
Peak memory 191640 kb
Host smart-e5d2e9c8-ea56-4eea-b756-c623e3dadd61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514173806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.3514173806
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.405916550
Short name T337
Test name
Test status
Simulation time 90097644120 ps
CPU time 40.03 seconds
Started Aug 06 07:05:26 PM PDT 24
Finished Aug 06 07:06:06 PM PDT 24
Peak memory 183440 kb
Host smart-45c1cdf0-c501-426c-b449-02544571b33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405916550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.405916550
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.2102303284
Short name T277
Test name
Test status
Simulation time 627707797185 ps
CPU time 695.92 seconds
Started Aug 06 07:05:27 PM PDT 24
Finished Aug 06 07:17:03 PM PDT 24
Peak memory 191644 kb
Host smart-cef43331-9c12-49d7-abdc-51a796e6ddc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102303284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.2102303284
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all_with_rand_reset.268130025
Short name T422
Test name
Test status
Simulation time 37308008551 ps
CPU time 398.18 seconds
Started Aug 06 07:05:24 PM PDT 24
Finished Aug 06 07:12:03 PM PDT 24
Peak memory 198188 kb
Host smart-3da21623-6a6e-4098-9242-c12cadc6d5ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268130025 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all_with_rand_reset.268130025
Directory /workspace/33.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.3395698007
Short name T311
Test name
Test status
Simulation time 161417665466 ps
CPU time 231.4 seconds
Started Aug 06 07:05:30 PM PDT 24
Finished Aug 06 07:09:21 PM PDT 24
Peak memory 183288 kb
Host smart-102c415b-1da1-495b-8126-d3fd5c326eec
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395698007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.3395698007
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.3451915693
Short name T368
Test name
Test status
Simulation time 238813415101 ps
CPU time 108.42 seconds
Started Aug 06 07:05:14 PM PDT 24
Finished Aug 06 07:07:02 PM PDT 24
Peak memory 183448 kb
Host smart-69dfac70-3a4f-4531-9996-0578e93807e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451915693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.3451915693
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.3211824336
Short name T405
Test name
Test status
Simulation time 44204867866 ps
CPU time 75.8 seconds
Started Aug 06 07:05:29 PM PDT 24
Finished Aug 06 07:06:45 PM PDT 24
Peak memory 183448 kb
Host smart-0c937aa2-6c82-477c-84d6-e834a308f36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211824336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.3211824336
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.2649241586
Short name T139
Test name
Test status
Simulation time 714941891376 ps
CPU time 457.21 seconds
Started Aug 06 07:05:15 PM PDT 24
Finished Aug 06 07:12:53 PM PDT 24
Peak memory 191680 kb
Host smart-7cb9c812-9a24-4ed2-a68b-cc53b4455a1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649241586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.2649241586
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all_with_rand_reset.2217625427
Short name T440
Test name
Test status
Simulation time 19807617587 ps
CPU time 215.44 seconds
Started Aug 06 07:05:26 PM PDT 24
Finished Aug 06 07:09:02 PM PDT 24
Peak memory 198148 kb
Host smart-5881af0c-e4db-46ff-8049-d1e3820170f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217625427 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all_with_rand_reset.2217625427
Directory /workspace/34.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.197677903
Short name T299
Test name
Test status
Simulation time 567122322177 ps
CPU time 497.94 seconds
Started Aug 06 07:05:19 PM PDT 24
Finished Aug 06 07:13:37 PM PDT 24
Peak memory 183408 kb
Host smart-f4a62518-bf37-4dc8-a96e-f3a2c92daaf1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197677903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.rv_timer_cfg_update_on_fly.197677903
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.1912098788
Short name T354
Test name
Test status
Simulation time 158369083426 ps
CPU time 120.51 seconds
Started Aug 06 07:05:21 PM PDT 24
Finished Aug 06 07:07:21 PM PDT 24
Peak memory 183420 kb
Host smart-51164f2b-3f18-4a97-b1d1-d1ee659afa1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912098788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.1912098788
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.959063281
Short name T20
Test name
Test status
Simulation time 614362742638 ps
CPU time 203.36 seconds
Started Aug 06 07:05:15 PM PDT 24
Finished Aug 06 07:08:39 PM PDT 24
Peak memory 191600 kb
Host smart-e01b9694-4eb8-41a1-aa25-7670d6bc07e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959063281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.959063281
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.2146944312
Short name T40
Test name
Test status
Simulation time 670067547575 ps
CPU time 163.81 seconds
Started Aug 06 07:05:19 PM PDT 24
Finished Aug 06 07:08:03 PM PDT 24
Peak memory 183412 kb
Host smart-6f32b036-c08a-462f-9912-52537b80db01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146944312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.2146944312
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.696265044
Short name T412
Test name
Test status
Simulation time 218618781 ps
CPU time 0.54 seconds
Started Aug 06 07:05:27 PM PDT 24
Finished Aug 06 07:05:28 PM PDT 24
Peak memory 183204 kb
Host smart-9eb2a893-e52d-4798-8d95-97408b2e9c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696265044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.696265044
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.3736693854
Short name T425
Test name
Test status
Simulation time 3234560193 ps
CPU time 6.1 seconds
Started Aug 06 07:05:28 PM PDT 24
Finished Aug 06 07:05:34 PM PDT 24
Peak memory 183360 kb
Host smart-448e0907-fc4b-467a-8cb2-419f12d916c0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736693854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.3736693854
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.2963013638
Short name T394
Test name
Test status
Simulation time 46297604044 ps
CPU time 63.15 seconds
Started Aug 06 07:05:15 PM PDT 24
Finished Aug 06 07:06:18 PM PDT 24
Peak memory 183456 kb
Host smart-6b5aeaee-f5a1-417f-88f1-f493028054db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963013638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.2963013638
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.1781150627
Short name T373
Test name
Test status
Simulation time 144017918 ps
CPU time 0.76 seconds
Started Aug 06 07:05:13 PM PDT 24
Finished Aug 06 07:05:14 PM PDT 24
Peak memory 183228 kb
Host smart-e11694f8-9fe8-43a4-b08a-cf17a51fd329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781150627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.1781150627
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.4267252036
Short name T420
Test name
Test status
Simulation time 446538330065 ps
CPU time 158.23 seconds
Started Aug 06 07:05:13 PM PDT 24
Finished Aug 06 07:07:51 PM PDT 24
Peak memory 183492 kb
Host smart-01793026-cc8a-441c-88b0-c75cfc2c933e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267252036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.4267252036
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.3503545833
Short name T364
Test name
Test status
Simulation time 78589053328 ps
CPU time 53.25 seconds
Started Aug 06 07:05:13 PM PDT 24
Finished Aug 06 07:06:06 PM PDT 24
Peak memory 183472 kb
Host smart-ed4aa68b-5d37-4d98-a8e4-c36b331b1dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503545833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.3503545833
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.968583661
Short name T153
Test name
Test status
Simulation time 55929918650 ps
CPU time 28.18 seconds
Started Aug 06 07:05:35 PM PDT 24
Finished Aug 06 07:06:03 PM PDT 24
Peak memory 183416 kb
Host smart-c15ddc39-714c-47e3-93ea-03f7908a5883
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968583661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.968583661
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.2890972500
Short name T341
Test name
Test status
Simulation time 1973068481 ps
CPU time 3.62 seconds
Started Aug 06 07:05:27 PM PDT 24
Finished Aug 06 07:05:31 PM PDT 24
Peak memory 183252 kb
Host smart-0e03acc0-0dc5-4e4b-9d28-03520c754079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890972500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.2890972500
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.1883828359
Short name T119
Test name
Test status
Simulation time 1035211273583 ps
CPU time 1331.92 seconds
Started Aug 06 07:05:20 PM PDT 24
Finished Aug 06 07:27:32 PM PDT 24
Peak memory 191608 kb
Host smart-7370338c-5088-42f8-b7e4-829581484369
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883828359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.1883828359
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.2040313503
Short name T450
Test name
Test status
Simulation time 305224197416 ps
CPU time 476.58 seconds
Started Aug 06 07:05:31 PM PDT 24
Finished Aug 06 07:13:28 PM PDT 24
Peak memory 183436 kb
Host smart-cb0b0502-f6dd-4487-8fec-bfd5911a038f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040313503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.2040313503
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.2599557155
Short name T403
Test name
Test status
Simulation time 106999592597 ps
CPU time 166.66 seconds
Started Aug 06 07:05:35 PM PDT 24
Finished Aug 06 07:08:21 PM PDT 24
Peak memory 183472 kb
Host smart-89eb7f80-94e5-485b-9038-b88a05343322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599557155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.2599557155
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.3984950335
Short name T185
Test name
Test status
Simulation time 171445459273 ps
CPU time 1090.22 seconds
Started Aug 06 07:05:29 PM PDT 24
Finished Aug 06 07:23:39 PM PDT 24
Peak memory 191644 kb
Host smart-05a95116-1358-43f3-8889-3ca785a784c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984950335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.3984950335
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.140731120
Short name T380
Test name
Test status
Simulation time 36645979 ps
CPU time 0.54 seconds
Started Aug 06 07:05:25 PM PDT 24
Finished Aug 06 07:05:26 PM PDT 24
Peak memory 183164 kb
Host smart-5e3dc9fc-1fdd-4aef-99c8-de9833ef5188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140731120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.140731120
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.1312215513
Short name T391
Test name
Test status
Simulation time 30547730662 ps
CPU time 46.65 seconds
Started Aug 06 07:05:26 PM PDT 24
Finished Aug 06 07:06:13 PM PDT 24
Peak memory 183444 kb
Host smart-191f77d6-ba96-4f92-ab07-c8a6c25e8a1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312215513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.1312215513
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.2148752057
Short name T436
Test name
Test status
Simulation time 691638239071 ps
CPU time 402.5 seconds
Started Aug 06 07:04:57 PM PDT 24
Finished Aug 06 07:11:40 PM PDT 24
Peak memory 183428 kb
Host smart-49ab3c06-3890-46c0-a293-bd424b666b05
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148752057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.2148752057
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.4101624972
Short name T441
Test name
Test status
Simulation time 10996475798 ps
CPU time 3.62 seconds
Started Aug 06 07:04:56 PM PDT 24
Finished Aug 06 07:05:00 PM PDT 24
Peak memory 183416 kb
Host smart-98ef8d69-1771-4ca4-87d8-e66be55e7861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101624972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.4101624972
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.3557058545
Short name T142
Test name
Test status
Simulation time 184078467254 ps
CPU time 92.75 seconds
Started Aug 06 07:04:52 PM PDT 24
Finished Aug 06 07:06:25 PM PDT 24
Peak memory 191620 kb
Host smart-a9fc3c0c-1f18-48f9-af65-8f56c9e02fc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557058545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.3557058545
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.2938288529
Short name T17
Test name
Test status
Simulation time 41642318 ps
CPU time 0.76 seconds
Started Aug 06 07:04:57 PM PDT 24
Finished Aug 06 07:04:58 PM PDT 24
Peak memory 214680 kb
Host smart-fe9e9e76-a72a-4439-8bac-5622a8646454
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938288529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.2938288529
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.1334577929
Short name T247
Test name
Test status
Simulation time 779285790643 ps
CPU time 1035.95 seconds
Started Aug 06 07:04:56 PM PDT 24
Finished Aug 06 07:22:13 PM PDT 24
Peak memory 191632 kb
Host smart-8ccc4990-62d6-4fae-9166-27bc6334e2c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334577929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
1334577929
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.3077811434
Short name T244
Test name
Test status
Simulation time 61673222634 ps
CPU time 104.67 seconds
Started Aug 06 07:05:29 PM PDT 24
Finished Aug 06 07:07:14 PM PDT 24
Peak memory 183452 kb
Host smart-7c2dc665-5eef-4abc-9667-3aa09352edee
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077811434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.3077811434
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.2049909718
Short name T8
Test name
Test status
Simulation time 462448470293 ps
CPU time 237.76 seconds
Started Aug 06 07:05:26 PM PDT 24
Finished Aug 06 07:09:24 PM PDT 24
Peak memory 183468 kb
Host smart-3bc01b4f-15be-4eb7-87da-ca6ab9fa2c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049909718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.2049909718
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.2684983631
Short name T159
Test name
Test status
Simulation time 211585104746 ps
CPU time 367.73 seconds
Started Aug 06 07:05:18 PM PDT 24
Finished Aug 06 07:11:26 PM PDT 24
Peak memory 191600 kb
Host smart-1de5ce81-fc0b-48f5-85de-fc442da34dfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684983631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.2684983631
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.1676115230
Short name T189
Test name
Test status
Simulation time 259082703953 ps
CPU time 122.27 seconds
Started Aug 06 07:05:29 PM PDT 24
Finished Aug 06 07:07:31 PM PDT 24
Peak memory 183480 kb
Host smart-d7c44393-d257-43b8-8ea7-747abe5eca55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676115230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.1676115230
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.2034874553
Short name T443
Test name
Test status
Simulation time 189170812783 ps
CPU time 161.43 seconds
Started Aug 06 07:05:31 PM PDT 24
Finished Aug 06 07:08:12 PM PDT 24
Peak memory 191652 kb
Host smart-3d023ce6-e8af-43cd-89f9-71837be6f6fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034874553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.2034874553
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all_with_rand_reset.2866694987
Short name T12
Test name
Test status
Simulation time 87411130386 ps
CPU time 461.07 seconds
Started Aug 06 07:05:14 PM PDT 24
Finished Aug 06 07:12:56 PM PDT 24
Peak memory 198128 kb
Host smart-e5ecee97-0604-4d54-8696-ffb03294006a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866694987 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all_with_rand_reset.2866694987
Directory /workspace/40.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.1861801108
Short name T53
Test name
Test status
Simulation time 423729051292 ps
CPU time 235.12 seconds
Started Aug 06 07:05:32 PM PDT 24
Finished Aug 06 07:09:27 PM PDT 24
Peak memory 183456 kb
Host smart-3513b882-c9df-4328-b552-614050a637c9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861801108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.1861801108
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.123653749
Short name T382
Test name
Test status
Simulation time 71699392055 ps
CPU time 58.06 seconds
Started Aug 06 07:05:26 PM PDT 24
Finished Aug 06 07:06:24 PM PDT 24
Peak memory 183492 kb
Host smart-c1fc8790-7611-42a9-a6bf-63b26df3b5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123653749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.123653749
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.119676212
Short name T173
Test name
Test status
Simulation time 527196328668 ps
CPU time 2463.9 seconds
Started Aug 06 07:05:30 PM PDT 24
Finished Aug 06 07:46:35 PM PDT 24
Peak memory 191672 kb
Host smart-4a9b44a4-7446-4262-8e0f-2838abe8c4fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119676212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.119676212
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.748770050
Short name T414
Test name
Test status
Simulation time 28218025802 ps
CPU time 31.3 seconds
Started Aug 06 07:05:27 PM PDT 24
Finished Aug 06 07:05:58 PM PDT 24
Peak memory 191692 kb
Host smart-2dc25f78-e926-4bdb-a780-a70faa3d9ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748770050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.748770050
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.1228108645
Short name T322
Test name
Test status
Simulation time 339041537694 ps
CPU time 187.1 seconds
Started Aug 06 07:05:32 PM PDT 24
Finished Aug 06 07:08:40 PM PDT 24
Peak memory 195312 kb
Host smart-5d7deeae-4a8f-4d8a-9e12-c299c56619d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228108645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.1228108645
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.425578955
Short name T324
Test name
Test status
Simulation time 367875126676 ps
CPU time 634.54 seconds
Started Aug 06 07:05:34 PM PDT 24
Finished Aug 06 07:16:08 PM PDT 24
Peak memory 183440 kb
Host smart-f19f90a7-fd7e-4387-acb9-0f2e6555b456
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425578955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.rv_timer_cfg_update_on_fly.425578955
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.1499573414
Short name T378
Test name
Test status
Simulation time 580696527137 ps
CPU time 201.39 seconds
Started Aug 06 07:05:34 PM PDT 24
Finished Aug 06 07:08:56 PM PDT 24
Peak memory 183468 kb
Host smart-64dbede4-ed7e-44c1-8b5a-014af5c2e196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499573414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.1499573414
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.2912997643
Short name T111
Test name
Test status
Simulation time 228527093012 ps
CPU time 191.86 seconds
Started Aug 06 07:05:26 PM PDT 24
Finished Aug 06 07:08:38 PM PDT 24
Peak memory 191660 kb
Host smart-4e927031-5d67-4599-a15b-e198f91aa945
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912997643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.2912997643
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.2553287806
Short name T54
Test name
Test status
Simulation time 45872342536 ps
CPU time 108.74 seconds
Started Aug 06 07:05:28 PM PDT 24
Finished Aug 06 07:07:17 PM PDT 24
Peak memory 183368 kb
Host smart-ab9423d4-ff86-449c-a116-f023ff54e8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553287806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.2553287806
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.372109085
Short name T245
Test name
Test status
Simulation time 88992288104 ps
CPU time 140.45 seconds
Started Aug 06 07:05:31 PM PDT 24
Finished Aug 06 07:07:52 PM PDT 24
Peak memory 183444 kb
Host smart-2ea58856-3f9e-421e-a900-260fa76276d5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372109085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.rv_timer_cfg_update_on_fly.372109085
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.1280764547
Short name T383
Test name
Test status
Simulation time 186856776480 ps
CPU time 148.38 seconds
Started Aug 06 07:05:27 PM PDT 24
Finished Aug 06 07:07:55 PM PDT 24
Peak memory 183340 kb
Host smart-2f606a07-6596-4420-94bc-bc2a9997570d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280764547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.1280764547
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.423501358
Short name T221
Test name
Test status
Simulation time 90867971861 ps
CPU time 472.55 seconds
Started Aug 06 07:05:29 PM PDT 24
Finished Aug 06 07:13:22 PM PDT 24
Peak memory 192728 kb
Host smart-7a0d5677-c638-4d21-9890-3f4342d8fd87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423501358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.423501358
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.1928565863
Short name T3
Test name
Test status
Simulation time 6614217626 ps
CPU time 6.01 seconds
Started Aug 06 07:05:26 PM PDT 24
Finished Aug 06 07:05:33 PM PDT 24
Peak memory 194808 kb
Host smart-2c1aa282-ddc3-4864-a129-f9539ba741ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928565863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.1928565863
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.3966144187
Short name T418
Test name
Test status
Simulation time 739407809 ps
CPU time 1.65 seconds
Started Aug 06 07:05:28 PM PDT 24
Finished Aug 06 07:05:29 PM PDT 24
Peak memory 183092 kb
Host smart-85488ebc-f35e-43c8-a7c1-02762da5a158
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966144187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.3966144187
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.52159846
Short name T35
Test name
Test status
Simulation time 26341324407 ps
CPU time 189.45 seconds
Started Aug 06 07:05:28 PM PDT 24
Finished Aug 06 07:08:37 PM PDT 24
Peak memory 198016 kb
Host smart-8827fb8e-afc6-41d0-a120-2b3e815af939
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52159846 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.52159846
Directory /workspace/43.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.3494825196
Short name T392
Test name
Test status
Simulation time 446958990060 ps
CPU time 167.07 seconds
Started Aug 06 07:05:26 PM PDT 24
Finished Aug 06 07:08:13 PM PDT 24
Peak memory 183468 kb
Host smart-272ef5ea-3eb8-44ec-b927-58c622f6997e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494825196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.3494825196
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.687860759
Short name T155
Test name
Test status
Simulation time 287678722750 ps
CPU time 2638.94 seconds
Started Aug 06 07:05:27 PM PDT 24
Finished Aug 06 07:49:27 PM PDT 24
Peak memory 191548 kb
Host smart-dac9d52e-3cd8-475f-bf91-ce254ad4d7b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687860759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.687860759
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.789454570
Short name T352
Test name
Test status
Simulation time 156592180 ps
CPU time 1.21 seconds
Started Aug 06 07:05:27 PM PDT 24
Finished Aug 06 07:05:28 PM PDT 24
Peak memory 191504 kb
Host smart-60f245c5-4499-4963-8a8c-5fc12e604021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789454570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.789454570
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.3083838464
Short name T390
Test name
Test status
Simulation time 249667232695 ps
CPU time 303.69 seconds
Started Aug 06 07:05:31 PM PDT 24
Finished Aug 06 07:10:34 PM PDT 24
Peak memory 191588 kb
Host smart-fc2e4e49-153b-4507-bc51-d4c4962aa174
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083838464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.3083838464
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.3260910233
Short name T99
Test name
Test status
Simulation time 581173398288 ps
CPU time 336.05 seconds
Started Aug 06 07:05:31 PM PDT 24
Finished Aug 06 07:11:07 PM PDT 24
Peak memory 183428 kb
Host smart-ac2b43e6-6b71-4cd1-8606-62bf7df02961
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260910233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.3260910233
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.1779629889
Short name T402
Test name
Test status
Simulation time 925440404456 ps
CPU time 363.59 seconds
Started Aug 06 07:05:29 PM PDT 24
Finished Aug 06 07:11:33 PM PDT 24
Peak memory 183432 kb
Host smart-47e2065a-6eb3-4d29-9445-8dd0fd394047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779629889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.1779629889
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.551332897
Short name T48
Test name
Test status
Simulation time 651355601873 ps
CPU time 372.89 seconds
Started Aug 06 07:05:31 PM PDT 24
Finished Aug 06 07:11:44 PM PDT 24
Peak memory 191640 kb
Host smart-f6b79b9e-62a8-469e-a25f-02fffdba355a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551332897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.551332897
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.290266124
Short name T279
Test name
Test status
Simulation time 148606549226 ps
CPU time 63.63 seconds
Started Aug 06 07:05:30 PM PDT 24
Finished Aug 06 07:06:34 PM PDT 24
Peak memory 191624 kb
Host smart-3868888b-40ae-4ce5-b381-daf7268c0f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290266124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.290266124
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.2840106319
Short name T437
Test name
Test status
Simulation time 450662359657 ps
CPU time 698.53 seconds
Started Aug 06 07:05:32 PM PDT 24
Finished Aug 06 07:17:11 PM PDT 24
Peak memory 191588 kb
Host smart-374c785d-db3b-4f5a-8053-5ea5db6919a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840106319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.2840106319
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.1279360782
Short name T263
Test name
Test status
Simulation time 756918546765 ps
CPU time 392.2 seconds
Started Aug 06 07:05:35 PM PDT 24
Finished Aug 06 07:12:08 PM PDT 24
Peak memory 183428 kb
Host smart-3445134d-7e4a-4d27-af19-6a4ce326593f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279360782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.1279360782
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.2461124020
Short name T401
Test name
Test status
Simulation time 195810238894 ps
CPU time 92.11 seconds
Started Aug 06 07:05:48 PM PDT 24
Finished Aug 06 07:07:20 PM PDT 24
Peak memory 183448 kb
Host smart-55b41099-cfe9-4817-a270-c63bfb3aa3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461124020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.2461124020
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.1118111166
Short name T63
Test name
Test status
Simulation time 8060911701 ps
CPU time 15.63 seconds
Started Aug 06 07:05:33 PM PDT 24
Finished Aug 06 07:05:48 PM PDT 24
Peak memory 183400 kb
Host smart-c87b7bb6-73c4-4951-be01-e369306cf905
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118111166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.1118111166
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.462317500
Short name T65
Test name
Test status
Simulation time 130473630130 ps
CPU time 409.36 seconds
Started Aug 06 07:05:36 PM PDT 24
Finished Aug 06 07:12:26 PM PDT 24
Peak memory 191632 kb
Host smart-ac915193-179f-4f66-835e-7f07e091a095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462317500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.462317500
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.3906974670
Short name T312
Test name
Test status
Simulation time 1694129678921 ps
CPU time 639.74 seconds
Started Aug 06 07:05:32 PM PDT 24
Finished Aug 06 07:16:12 PM PDT 24
Peak memory 191604 kb
Host smart-929de4fb-3ddb-4498-a812-f3a3a2b86ed6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906974670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.3906974670
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.2764089511
Short name T201
Test name
Test status
Simulation time 180275293892 ps
CPU time 141.28 seconds
Started Aug 06 07:05:40 PM PDT 24
Finished Aug 06 07:08:02 PM PDT 24
Peak memory 183280 kb
Host smart-2fb2c663-7ffd-47ae-a1bf-5d3b78356924
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764089511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.2764089511
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.3183970019
Short name T379
Test name
Test status
Simulation time 96908391242 ps
CPU time 148.47 seconds
Started Aug 06 07:05:33 PM PDT 24
Finished Aug 06 07:08:02 PM PDT 24
Peak memory 183300 kb
Host smart-e81344fb-b5d2-413b-a4e5-ef9b032fd9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183970019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.3183970019
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.1389809040
Short name T275
Test name
Test status
Simulation time 22230089541 ps
CPU time 43.02 seconds
Started Aug 06 07:05:38 PM PDT 24
Finished Aug 06 07:06:21 PM PDT 24
Peak memory 191696 kb
Host smart-d3c43016-f3b0-43ba-8e96-ae442b5526e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389809040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.1389809040
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.560349933
Short name T71
Test name
Test status
Simulation time 61936601079 ps
CPU time 178.28 seconds
Started Aug 06 07:05:30 PM PDT 24
Finished Aug 06 07:08:28 PM PDT 24
Peak memory 194548 kb
Host smart-8cf1c1a7-e74b-49c8-8f1d-08db9db245ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560349933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.560349933
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.2123813228
Short name T397
Test name
Test status
Simulation time 94074348 ps
CPU time 0.55 seconds
Started Aug 06 07:05:35 PM PDT 24
Finished Aug 06 07:05:36 PM PDT 24
Peak memory 183232 kb
Host smart-1b5d5b5d-03ea-4493-8c27-faa6a631ad05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123813228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.2123813228
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.4256729081
Short name T300
Test name
Test status
Simulation time 2335182539053 ps
CPU time 884.28 seconds
Started Aug 06 07:05:35 PM PDT 24
Finished Aug 06 07:20:20 PM PDT 24
Peak memory 183408 kb
Host smart-7d851c1b-ec04-4389-a16d-829959913fcc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256729081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.4256729081
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.1449480301
Short name T411
Test name
Test status
Simulation time 205621668762 ps
CPU time 328.4 seconds
Started Aug 06 07:05:30 PM PDT 24
Finished Aug 06 07:10:58 PM PDT 24
Peak memory 183476 kb
Host smart-6ecca562-bc2e-40e2-bec9-6b2f56d747ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449480301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.1449480301
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.3168088547
Short name T313
Test name
Test status
Simulation time 74149851452 ps
CPU time 100.76 seconds
Started Aug 06 07:05:31 PM PDT 24
Finished Aug 06 07:07:12 PM PDT 24
Peak memory 191640 kb
Host smart-0d8b5d13-0ef1-4531-9138-f769c95f4ec9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168088547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.3168088547
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.487965026
Short name T350
Test name
Test status
Simulation time 64225042471 ps
CPU time 44.02 seconds
Started Aug 06 07:05:32 PM PDT 24
Finished Aug 06 07:06:16 PM PDT 24
Peak memory 191620 kb
Host smart-b1925f42-5623-4b74-9437-14efc41e26c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487965026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.487965026
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.537797757
Short name T144
Test name
Test status
Simulation time 603779508548 ps
CPU time 1662.21 seconds
Started Aug 06 07:06:03 PM PDT 24
Finished Aug 06 07:33:46 PM PDT 24
Peak memory 191608 kb
Host smart-cc5add3b-323f-4f60-bb45-823c1487f115
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537797757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all.
537797757
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.4289206316
Short name T158
Test name
Test status
Simulation time 1874508195116 ps
CPU time 1033.09 seconds
Started Aug 06 07:05:58 PM PDT 24
Finished Aug 06 07:23:12 PM PDT 24
Peak memory 183396 kb
Host smart-e810b662-e381-43c4-9cd7-5532d9d488ae
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289206316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.4289206316
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.3729588288
Short name T395
Test name
Test status
Simulation time 194435963945 ps
CPU time 120.58 seconds
Started Aug 06 07:05:57 PM PDT 24
Finished Aug 06 07:07:58 PM PDT 24
Peak memory 183436 kb
Host smart-98ccdab9-740d-4c7c-b52f-aa4df2045f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729588288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.3729588288
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.4075841224
Short name T252
Test name
Test status
Simulation time 220890932314 ps
CPU time 132.23 seconds
Started Aug 06 07:06:04 PM PDT 24
Finished Aug 06 07:08:16 PM PDT 24
Peak memory 191548 kb
Host smart-a7606de3-057a-4e36-a1b4-5b5af47e964a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075841224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.4075841224
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.2919425710
Short name T7
Test name
Test status
Simulation time 167199048285 ps
CPU time 61.12 seconds
Started Aug 06 07:06:03 PM PDT 24
Finished Aug 06 07:07:04 PM PDT 24
Peak memory 195220 kb
Host smart-9bc20260-797a-4598-83d4-a3369565eb14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919425710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.2919425710
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.3474590977
Short name T59
Test name
Test status
Simulation time 175558682470 ps
CPU time 132.03 seconds
Started Aug 06 07:05:57 PM PDT 24
Finished Aug 06 07:08:10 PM PDT 24
Peak memory 191604 kb
Host smart-9e8bc562-899e-4cb6-b3c4-013647e116de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474590977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.3474590977
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all_with_rand_reset.1323722094
Short name T11
Test name
Test status
Simulation time 118313672618 ps
CPU time 1272.52 seconds
Started Aug 06 07:05:58 PM PDT 24
Finished Aug 06 07:27:11 PM PDT 24
Peak memory 207672 kb
Host smart-39d4986e-55bd-4953-a8d4-a1d8e406d0ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323722094 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all_with_rand_reset.1323722094
Directory /workspace/49.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rv_timer_random.3663799833
Short name T236
Test name
Test status
Simulation time 126860416784 ps
CPU time 172.45 seconds
Started Aug 06 07:04:59 PM PDT 24
Finished Aug 06 07:07:51 PM PDT 24
Peak memory 191660 kb
Host smart-5051f786-2bdf-48d0-8b96-0ffbb1ea554e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663799833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.3663799833
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.2843934522
Short name T117
Test name
Test status
Simulation time 51064945383 ps
CPU time 108.43 seconds
Started Aug 06 07:04:56 PM PDT 24
Finished Aug 06 07:06:45 PM PDT 24
Peak memory 183476 kb
Host smart-f54a75cb-a0c1-4edf-a33d-dc5cbf8afd63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843934522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.2843934522
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all_with_rand_reset.2587066763
Short name T37
Test name
Test status
Simulation time 550120890534 ps
CPU time 496.4 seconds
Started Aug 06 07:04:58 PM PDT 24
Finished Aug 06 07:13:14 PM PDT 24
Peak memory 208056 kb
Host smart-e0b6258d-be43-4f57-b95c-83e5eeac6959
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587066763 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all_with_rand_reset.2587066763
Directory /workspace/5.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.3140419572
Short name T261
Test name
Test status
Simulation time 164444003137 ps
CPU time 276.56 seconds
Started Aug 06 07:06:00 PM PDT 24
Finished Aug 06 07:10:36 PM PDT 24
Peak memory 191672 kb
Host smart-5b0cbe8c-84ef-41f8-ac50-b17f09ed07e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140419572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.3140419572
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.2827741836
Short name T424
Test name
Test status
Simulation time 274317677994 ps
CPU time 134.77 seconds
Started Aug 06 07:06:05 PM PDT 24
Finished Aug 06 07:08:20 PM PDT 24
Peak memory 191672 kb
Host smart-5cdade5b-4084-4a6d-b5bb-a89d59ef5749
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827741836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.2827741836
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.2210802000
Short name T51
Test name
Test status
Simulation time 121181316723 ps
CPU time 508.09 seconds
Started Aug 06 07:05:59 PM PDT 24
Finished Aug 06 07:14:27 PM PDT 24
Peak memory 191632 kb
Host smart-87a3c3dd-a450-4cce-ab6d-65c11ad3e515
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210802000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.2210802000
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.2214093931
Short name T351
Test name
Test status
Simulation time 46971439171 ps
CPU time 74.08 seconds
Started Aug 06 07:06:04 PM PDT 24
Finished Aug 06 07:07:18 PM PDT 24
Peak memory 191704 kb
Host smart-10804b84-5362-4151-accc-65425e04f884
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214093931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.2214093931
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.4149764676
Short name T340
Test name
Test status
Simulation time 127711415607 ps
CPU time 549.4 seconds
Started Aug 06 07:06:03 PM PDT 24
Finished Aug 06 07:15:13 PM PDT 24
Peak memory 191632 kb
Host smart-2c1d1abc-cdc7-41ac-9270-201a2ccd655b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149764676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.4149764676
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.831746732
Short name T387
Test name
Test status
Simulation time 155123854080 ps
CPU time 247.39 seconds
Started Aug 06 07:06:01 PM PDT 24
Finished Aug 06 07:10:09 PM PDT 24
Peak memory 183416 kb
Host smart-87589acd-a332-46b5-aaa8-ba38254f22a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831746732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.831746732
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.1269403811
Short name T122
Test name
Test status
Simulation time 382043942480 ps
CPU time 166.46 seconds
Started Aug 06 07:06:04 PM PDT 24
Finished Aug 06 07:08:51 PM PDT 24
Peak memory 191664 kb
Host smart-35d12c44-a7ea-4140-9ae4-07500e8b6021
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269403811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.1269403811
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.879619689
Short name T230
Test name
Test status
Simulation time 150147809264 ps
CPU time 232.49 seconds
Started Aug 06 07:06:03 PM PDT 24
Finished Aug 06 07:09:55 PM PDT 24
Peak memory 191624 kb
Host smart-1dd5541f-cf19-4397-821a-d1138b61b923
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879619689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.879619689
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.2735895521
Short name T250
Test name
Test status
Simulation time 245074331046 ps
CPU time 259.02 seconds
Started Aug 06 07:05:58 PM PDT 24
Finished Aug 06 07:10:18 PM PDT 24
Peak memory 191524 kb
Host smart-9bbf2ae2-292c-4e62-bb52-24ade5e2fa1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735895521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.2735895521
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.967129588
Short name T69
Test name
Test status
Simulation time 87658782005 ps
CPU time 147.04 seconds
Started Aug 06 07:05:00 PM PDT 24
Finished Aug 06 07:07:27 PM PDT 24
Peak memory 183468 kb
Host smart-f7e24a33-13ad-46e6-bc3c-a9db499a93f8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967129588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.rv_timer_cfg_update_on_fly.967129588
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.3730116557
Short name T438
Test name
Test status
Simulation time 57606420732 ps
CPU time 35.08 seconds
Started Aug 06 07:04:59 PM PDT 24
Finished Aug 06 07:05:34 PM PDT 24
Peak memory 183456 kb
Host smart-1849f0ee-54b2-4c08-be01-ccfa81a8253e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730116557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.3730116557
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.1437069197
Short name T347
Test name
Test status
Simulation time 9107421484 ps
CPU time 4.3 seconds
Started Aug 06 07:04:57 PM PDT 24
Finished Aug 06 07:05:02 PM PDT 24
Peak memory 183268 kb
Host smart-02d68c92-c8be-4d4f-91ae-7fa5b4aa9faf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437069197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.1437069197
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.2405721116
Short name T362
Test name
Test status
Simulation time 2052873721 ps
CPU time 3.28 seconds
Started Aug 06 07:05:00 PM PDT 24
Finished Aug 06 07:05:03 PM PDT 24
Peak memory 191928 kb
Host smart-2a0de219-4c09-4258-b22f-d8d7c37c0aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405721116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.2405721116
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.4175667970
Short name T140
Test name
Test status
Simulation time 228197737619 ps
CPU time 654.06 seconds
Started Aug 06 07:06:02 PM PDT 24
Finished Aug 06 07:16:57 PM PDT 24
Peak memory 191588 kb
Host smart-7e0d6429-f4ca-4695-ba1e-fa07a064ffdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175667970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.4175667970
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.2717690184
Short name T307
Test name
Test status
Simulation time 248002132861 ps
CPU time 376.02 seconds
Started Aug 06 07:05:59 PM PDT 24
Finished Aug 06 07:12:15 PM PDT 24
Peak memory 195104 kb
Host smart-b3d19644-b73a-420e-945d-398dd045abe9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717690184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.2717690184
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.216561917
Short name T215
Test name
Test status
Simulation time 193139199034 ps
CPU time 997.58 seconds
Started Aug 06 07:05:59 PM PDT 24
Finished Aug 06 07:22:37 PM PDT 24
Peak memory 191676 kb
Host smart-bfab0e0a-40eb-47de-94c4-d9a7959f2bb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216561917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.216561917
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.1695439500
Short name T248
Test name
Test status
Simulation time 10446841856 ps
CPU time 16.1 seconds
Started Aug 06 07:05:57 PM PDT 24
Finished Aug 06 07:06:13 PM PDT 24
Peak memory 183444 kb
Host smart-ad3d4236-2e5d-4f1d-96b4-387386671de8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695439500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.1695439500
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.2695540092
Short name T415
Test name
Test status
Simulation time 457747645843 ps
CPU time 317.87 seconds
Started Aug 06 07:05:00 PM PDT 24
Finished Aug 06 07:10:18 PM PDT 24
Peak memory 183492 kb
Host smart-68e7d1da-be8e-49cf-aaf0-eaf857bb2985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695540092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.2695540092
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.3733351641
Short name T52
Test name
Test status
Simulation time 34660202435 ps
CPU time 54.89 seconds
Started Aug 06 07:05:00 PM PDT 24
Finished Aug 06 07:05:55 PM PDT 24
Peak memory 183476 kb
Host smart-07126363-ed94-42d9-b773-7f5232a05373
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733351641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.3733351641
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.553109515
Short name T304
Test name
Test status
Simulation time 141093834548 ps
CPU time 42.07 seconds
Started Aug 06 07:04:59 PM PDT 24
Finished Aug 06 07:05:41 PM PDT 24
Peak memory 191620 kb
Host smart-a4848c46-a13b-4513-a919-52dd8ad31095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553109515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.553109515
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.1074540304
Short name T357
Test name
Test status
Simulation time 192313294370 ps
CPU time 287.17 seconds
Started Aug 06 07:04:57 PM PDT 24
Finished Aug 06 07:09:45 PM PDT 24
Peak memory 183464 kb
Host smart-41079196-4c7e-41c7-af20-6d260338a51a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074540304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
1074540304
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.519617545
Short name T33
Test name
Test status
Simulation time 23596154091 ps
CPU time 192.44 seconds
Started Aug 06 07:05:00 PM PDT 24
Finished Aug 06 07:08:12 PM PDT 24
Peak memory 198136 kb
Host smart-0e0c294b-db3b-4870-855a-19fd097737ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519617545 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all_with_rand_reset.519617545
Directory /workspace/7.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.3806348497
Short name T166
Test name
Test status
Simulation time 308050622135 ps
CPU time 252.57 seconds
Started Aug 06 07:06:03 PM PDT 24
Finished Aug 06 07:10:16 PM PDT 24
Peak memory 191652 kb
Host smart-2489b104-c724-4dc9-a63b-3c5c0bf796b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806348497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.3806348497
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.2214831291
Short name T296
Test name
Test status
Simulation time 98087066948 ps
CPU time 88.58 seconds
Started Aug 06 07:05:59 PM PDT 24
Finished Aug 06 07:07:28 PM PDT 24
Peak memory 191616 kb
Host smart-cebb0ffc-120f-411c-8b79-f7025285e42c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214831291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.2214831291
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.931674510
Short name T288
Test name
Test status
Simulation time 739242425688 ps
CPU time 733.82 seconds
Started Aug 06 07:05:58 PM PDT 24
Finished Aug 06 07:18:12 PM PDT 24
Peak memory 191868 kb
Host smart-9f98a1cd-6bb0-4e79-b15e-d3df4ca62d8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931674510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.931674510
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.645374391
Short name T334
Test name
Test status
Simulation time 184588961848 ps
CPU time 205.41 seconds
Started Aug 06 07:06:05 PM PDT 24
Finished Aug 06 07:09:30 PM PDT 24
Peak memory 191556 kb
Host smart-2f424e96-e7b1-417a-87c2-a6b64b77e2ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645374391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.645374391
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.2168803400
Short name T210
Test name
Test status
Simulation time 1129124034109 ps
CPU time 316.5 seconds
Started Aug 06 07:06:00 PM PDT 24
Finished Aug 06 07:11:17 PM PDT 24
Peak memory 191672 kb
Host smart-9909918b-824c-4af7-aa64-b7a067ebe5ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168803400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.2168803400
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.3926439532
Short name T129
Test name
Test status
Simulation time 94822051121 ps
CPU time 547.52 seconds
Started Aug 06 07:06:00 PM PDT 24
Finished Aug 06 07:15:07 PM PDT 24
Peak memory 191668 kb
Host smart-83810fed-731a-4152-86dd-1272c045f9ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926439532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.3926439532
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.1557334362
Short name T326
Test name
Test status
Simulation time 113638082071 ps
CPU time 284.41 seconds
Started Aug 06 07:06:02 PM PDT 24
Finished Aug 06 07:10:46 PM PDT 24
Peak memory 191648 kb
Host smart-f899b8ae-f93b-4e38-89a5-711676b1c8aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557334362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.1557334362
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.3325946211
Short name T183
Test name
Test status
Simulation time 438632120713 ps
CPU time 544.61 seconds
Started Aug 06 07:06:02 PM PDT 24
Finished Aug 06 07:15:06 PM PDT 24
Peak memory 191648 kb
Host smart-7007058a-64a1-49cc-8a3f-1fbfa93e73db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325946211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.3325946211
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.4096000880
Short name T116
Test name
Test status
Simulation time 82694029796 ps
CPU time 353.88 seconds
Started Aug 06 07:05:58 PM PDT 24
Finished Aug 06 07:11:52 PM PDT 24
Peak memory 191592 kb
Host smart-52c6ba34-12f8-4346-aafa-fc87a34c7c55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096000880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.4096000880
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.1253797149
Short name T213
Test name
Test status
Simulation time 133751567470 ps
CPU time 208.7 seconds
Started Aug 06 07:05:57 PM PDT 24
Finished Aug 06 07:09:26 PM PDT 24
Peak memory 191632 kb
Host smart-c41bbb35-f0f8-4198-87f5-aeeb794f4b3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253797149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.1253797149
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.51529113
Short name T358
Test name
Test status
Simulation time 326132402535 ps
CPU time 225.39 seconds
Started Aug 06 07:04:56 PM PDT 24
Finished Aug 06 07:08:42 PM PDT 24
Peak memory 183464 kb
Host smart-079db455-d14b-4202-b9e9-eca3d5d9ab52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51529113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.51529113
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.2104589335
Short name T315
Test name
Test status
Simulation time 92361890625 ps
CPU time 65.84 seconds
Started Aug 06 07:04:58 PM PDT 24
Finished Aug 06 07:06:04 PM PDT 24
Peak memory 183404 kb
Host smart-2971e410-5b7a-46e1-8541-4b16881e8238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104589335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.2104589335
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.2511260896
Short name T234
Test name
Test status
Simulation time 218557081664 ps
CPU time 311.53 seconds
Started Aug 06 07:05:01 PM PDT 24
Finished Aug 06 07:10:12 PM PDT 24
Peak memory 195136 kb
Host smart-b03d5408-4c60-4c98-8889-7b2e0cb8f39a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511260896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
2511260896
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/80.rv_timer_random.2590565035
Short name T123
Test name
Test status
Simulation time 401678897508 ps
CPU time 1135.95 seconds
Started Aug 06 07:06:05 PM PDT 24
Finished Aug 06 07:25:01 PM PDT 24
Peak memory 191628 kb
Host smart-1549fcf6-2d37-4f61-b0fd-b4605aa9d46c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590565035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.2590565035
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.606543808
Short name T267
Test name
Test status
Simulation time 7343678717 ps
CPU time 12.63 seconds
Started Aug 06 07:06:02 PM PDT 24
Finished Aug 06 07:06:15 PM PDT 24
Peak memory 183408 kb
Host smart-f2e81b23-7d4c-4170-b701-87c2017d5a39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606543808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.606543808
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.3982654605
Short name T320
Test name
Test status
Simulation time 218834266082 ps
CPU time 266.99 seconds
Started Aug 06 07:06:00 PM PDT 24
Finished Aug 06 07:10:27 PM PDT 24
Peak memory 183472 kb
Host smart-4474f357-4d1f-49b0-a291-32a3acc9e8ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982654605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.3982654605
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.1596940384
Short name T178
Test name
Test status
Simulation time 177088484905 ps
CPU time 167.06 seconds
Started Aug 06 07:06:02 PM PDT 24
Finished Aug 06 07:08:49 PM PDT 24
Peak memory 191632 kb
Host smart-91cb0268-d85c-4a13-ae13-abfb9a856728
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596940384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.1596940384
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.958079921
Short name T214
Test name
Test status
Simulation time 985174380993 ps
CPU time 424.41 seconds
Started Aug 06 07:06:00 PM PDT 24
Finished Aug 06 07:13:04 PM PDT 24
Peak memory 191680 kb
Host smart-e708f31b-8b57-488a-99b9-0c8f783ed306
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958079921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.958079921
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.3666099385
Short name T410
Test name
Test status
Simulation time 32810626744 ps
CPU time 53.81 seconds
Started Aug 06 07:06:05 PM PDT 24
Finished Aug 06 07:06:59 PM PDT 24
Peak memory 183448 kb
Host smart-e248a3de-c189-49d6-805c-e1a3d301457c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666099385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.3666099385
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.2914006044
Short name T113
Test name
Test status
Simulation time 122683711561 ps
CPU time 94.89 seconds
Started Aug 06 07:06:03 PM PDT 24
Finished Aug 06 07:07:38 PM PDT 24
Peak memory 191608 kb
Host smart-2bee65ca-8cf5-4907-ac1c-618bd74ee533
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914006044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.2914006044
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.1857006973
Short name T218
Test name
Test status
Simulation time 1122668883925 ps
CPU time 431.37 seconds
Started Aug 06 07:06:04 PM PDT 24
Finished Aug 06 07:13:16 PM PDT 24
Peak memory 191660 kb
Host smart-6524c5f6-6896-40c8-b3a5-3f7fb6aead7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857006973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.1857006973
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.515321115
Short name T184
Test name
Test status
Simulation time 369139146782 ps
CPU time 824.85 seconds
Started Aug 06 07:05:59 PM PDT 24
Finished Aug 06 07:19:44 PM PDT 24
Peak memory 191632 kb
Host smart-d1371f27-87c5-42c2-8770-edd9d532382f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515321115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.515321115
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.3763964868
Short name T10
Test name
Test status
Simulation time 18069580539 ps
CPU time 56.14 seconds
Started Aug 06 07:06:04 PM PDT 24
Finished Aug 06 07:07:00 PM PDT 24
Peak memory 183504 kb
Host smart-6f935fa2-374f-4361-95fc-ac38bddf5e67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763964868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.3763964868
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.2940338455
Short name T64
Test name
Test status
Simulation time 51926302262 ps
CPU time 20.82 seconds
Started Aug 06 07:04:50 PM PDT 24
Finished Aug 06 07:05:11 PM PDT 24
Peak memory 182740 kb
Host smart-01e192b6-0d7f-46ca-bd4c-48e8cf83f634
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940338455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.2940338455
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.276538536
Short name T353
Test name
Test status
Simulation time 889147116170 ps
CPU time 245.14 seconds
Started Aug 06 07:04:57 PM PDT 24
Finished Aug 06 07:09:03 PM PDT 24
Peak memory 183404 kb
Host smart-ffe38db8-317e-489d-ad94-bdeca2f026ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276538536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.276538536
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.3876259054
Short name T206
Test name
Test status
Simulation time 214898011900 ps
CPU time 238.32 seconds
Started Aug 06 07:05:04 PM PDT 24
Finished Aug 06 07:09:02 PM PDT 24
Peak memory 193960 kb
Host smart-6e8e4989-fe4e-468d-a35b-3aa0e4883f52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876259054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.3876259054
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.2952495893
Short name T427
Test name
Test status
Simulation time 41004445533 ps
CPU time 339.2 seconds
Started Aug 06 07:05:01 PM PDT 24
Finished Aug 06 07:10:41 PM PDT 24
Peak memory 183448 kb
Host smart-f22041e0-6fa0-46f4-bc72-7644e04ee994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952495893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.2952495893
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/92.rv_timer_random.2821480515
Short name T137
Test name
Test status
Simulation time 139261728130 ps
CPU time 872.73 seconds
Started Aug 06 07:06:01 PM PDT 24
Finished Aug 06 07:20:34 PM PDT 24
Peak memory 191680 kb
Host smart-458f944c-8f16-4ce8-a5eb-18936be2837c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821480515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.2821480515
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.621493089
Short name T177
Test name
Test status
Simulation time 444622858830 ps
CPU time 767.52 seconds
Started Aug 06 07:06:01 PM PDT 24
Finished Aug 06 07:18:49 PM PDT 24
Peak memory 191632 kb
Host smart-a0eb708c-7fa5-40ef-a3a7-99d452b8603e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621493089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.621493089
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.1341693679
Short name T269
Test name
Test status
Simulation time 579814612052 ps
CPU time 594.61 seconds
Started Aug 06 07:06:05 PM PDT 24
Finished Aug 06 07:16:00 PM PDT 24
Peak memory 191672 kb
Host smart-46e15ab6-6f7a-4d14-b670-411039ea5069
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341693679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.1341693679
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.2537032312
Short name T191
Test name
Test status
Simulation time 314840744910 ps
CPU time 114.59 seconds
Started Aug 06 07:06:01 PM PDT 24
Finished Aug 06 07:07:56 PM PDT 24
Peak memory 191684 kb
Host smart-e8c29b82-44a6-4471-8158-8617e43d4bc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537032312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.2537032312
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.3816656085
Short name T349
Test name
Test status
Simulation time 9985901721 ps
CPU time 22.85 seconds
Started Aug 06 07:06:03 PM PDT 24
Finished Aug 06 07:06:26 PM PDT 24
Peak memory 183396 kb
Host smart-b5368d1f-d064-4389-8d0c-b3cfdf22a865
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816656085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.3816656085
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.3710756539
Short name T270
Test name
Test status
Simulation time 80811852970 ps
CPU time 321.4 seconds
Started Aug 06 07:05:58 PM PDT 24
Finished Aug 06 07:11:20 PM PDT 24
Peak memory 191724 kb
Host smart-386e94fd-92ec-4c24-b220-bcc8d179c782
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710756539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.3710756539
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.1078364117
Short name T398
Test name
Test status
Simulation time 5861304235 ps
CPU time 5.71 seconds
Started Aug 06 07:06:05 PM PDT 24
Finished Aug 06 07:06:10 PM PDT 24
Peak memory 183460 kb
Host smart-0848ef21-900d-4fd7-ba1a-e61c68162d55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078364117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.1078364117
Directory /workspace/99.rv_timer_random/latest
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