Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.61 99.36 98.73 100.00 100.00 100.00 99.55


Total test records in report: 581
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T508 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.3630747728 Aug 07 07:13:57 PM PDT 24 Aug 07 07:13:59 PM PDT 24 230334424 ps
T509 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3056428341 Aug 07 07:14:23 PM PDT 24 Aug 07 07:14:24 PM PDT 24 11406443 ps
T510 /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.565422231 Aug 07 07:14:05 PM PDT 24 Aug 07 07:14:06 PM PDT 24 14246752 ps
T78 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.994502074 Aug 07 07:14:14 PM PDT 24 Aug 07 07:14:14 PM PDT 24 13315228 ps
T511 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.90400279 Aug 07 07:14:24 PM PDT 24 Aug 07 07:14:25 PM PDT 24 21582257 ps
T512 /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.1388727999 Aug 07 07:14:13 PM PDT 24 Aug 07 07:14:13 PM PDT 24 15855663 ps
T513 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.894889341 Aug 07 07:13:55 PM PDT 24 Aug 07 07:13:55 PM PDT 24 53520391 ps
T514 /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.3306638109 Aug 07 07:14:06 PM PDT 24 Aug 07 07:14:07 PM PDT 24 152149504 ps
T515 /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.3948340414 Aug 07 07:14:23 PM PDT 24 Aug 07 07:14:25 PM PDT 24 99341740 ps
T98 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1734519671 Aug 07 07:14:35 PM PDT 24 Aug 07 07:14:36 PM PDT 24 236683164 ps
T516 /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.1149432454 Aug 07 07:14:34 PM PDT 24 Aug 07 07:14:35 PM PDT 24 49252203 ps
T517 /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.1141612339 Aug 07 07:14:04 PM PDT 24 Aug 07 07:14:05 PM PDT 24 29970388 ps
T518 /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.676410262 Aug 07 07:13:55 PM PDT 24 Aug 07 07:13:56 PM PDT 24 93143071 ps
T519 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.2607906795 Aug 07 07:14:47 PM PDT 24 Aug 07 07:14:47 PM PDT 24 19152535 ps
T520 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.3467394418 Aug 07 07:14:34 PM PDT 24 Aug 07 07:14:34 PM PDT 24 68846002 ps
T521 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1894989523 Aug 07 07:14:04 PM PDT 24 Aug 07 07:14:06 PM PDT 24 56656071 ps
T522 /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.1054191509 Aug 07 07:14:35 PM PDT 24 Aug 07 07:14:36 PM PDT 24 10649453 ps
T523 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.796989046 Aug 07 07:14:44 PM PDT 24 Aug 07 07:14:45 PM PDT 24 25054421 ps
T524 /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.3958160217 Aug 07 07:14:07 PM PDT 24 Aug 07 07:14:08 PM PDT 24 22645791 ps
T525 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.1585979155 Aug 07 07:14:45 PM PDT 24 Aug 07 07:14:46 PM PDT 24 54681091 ps
T526 /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.476771021 Aug 07 07:13:56 PM PDT 24 Aug 07 07:13:57 PM PDT 24 85090916 ps
T527 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1435656209 Aug 07 07:14:26 PM PDT 24 Aug 07 07:14:27 PM PDT 24 61579201 ps
T528 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.4189908944 Aug 07 07:14:45 PM PDT 24 Aug 07 07:14:46 PM PDT 24 13869020 ps
T529 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.1704709680 Aug 07 07:13:56 PM PDT 24 Aug 07 07:13:57 PM PDT 24 75330224 ps
T530 /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.3552553730 Aug 07 07:14:43 PM PDT 24 Aug 07 07:14:44 PM PDT 24 45964026 ps
T531 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.2622237777 Aug 07 07:14:43 PM PDT 24 Aug 07 07:14:44 PM PDT 24 155823516 ps
T99 /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.545812375 Aug 07 07:14:23 PM PDT 24 Aug 07 07:14:24 PM PDT 24 70794683 ps
T532 /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.2589183830 Aug 07 07:14:06 PM PDT 24 Aug 07 07:14:08 PM PDT 24 194424262 ps
T533 /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.152597760 Aug 07 07:14:05 PM PDT 24 Aug 07 07:14:08 PM PDT 24 175973505 ps
T534 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.4163462634 Aug 07 07:14:44 PM PDT 24 Aug 07 07:14:46 PM PDT 24 80822554 ps
T79 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.2127045764 Aug 07 07:13:54 PM PDT 24 Aug 07 07:13:55 PM PDT 24 30239205 ps
T535 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.2238724807 Aug 07 07:13:55 PM PDT 24 Aug 07 07:13:56 PM PDT 24 44389902 ps
T536 /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.31198718 Aug 07 07:14:16 PM PDT 24 Aug 07 07:14:18 PM PDT 24 221030852 ps
T537 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.3940937549 Aug 07 07:14:14 PM PDT 24 Aug 07 07:14:16 PM PDT 24 37469249 ps
T538 /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.3768763440 Aug 07 07:14:17 PM PDT 24 Aug 07 07:14:18 PM PDT 24 40857363 ps
T80 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.315895094 Aug 07 07:14:06 PM PDT 24 Aug 07 07:14:07 PM PDT 24 39737663 ps
T539 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.2891130378 Aug 07 07:14:23 PM PDT 24 Aug 07 07:14:23 PM PDT 24 51998004 ps
T540 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.557092884 Aug 07 07:13:56 PM PDT 24 Aug 07 07:13:57 PM PDT 24 51624002 ps
T541 /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.175087442 Aug 07 07:14:24 PM PDT 24 Aug 07 07:14:26 PM PDT 24 178900239 ps
T542 /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.4261523820 Aug 07 07:14:25 PM PDT 24 Aug 07 07:14:27 PM PDT 24 186621277 ps
T543 /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.3290360765 Aug 07 07:14:34 PM PDT 24 Aug 07 07:14:35 PM PDT 24 39123993 ps
T544 /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.2431797158 Aug 07 07:14:35 PM PDT 24 Aug 07 07:14:35 PM PDT 24 39071233 ps
T545 /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.2424305468 Aug 07 07:14:15 PM PDT 24 Aug 07 07:14:16 PM PDT 24 11132319 ps
T546 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.3594583796 Aug 07 07:14:46 PM PDT 24 Aug 07 07:14:47 PM PDT 24 15804187 ps
T547 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.3249906477 Aug 07 07:14:35 PM PDT 24 Aug 07 07:14:35 PM PDT 24 124493599 ps
T548 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2103521506 Aug 07 07:14:47 PM PDT 24 Aug 07 07:14:48 PM PDT 24 13781489 ps
T549 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2393641022 Aug 07 07:14:05 PM PDT 24 Aug 07 07:14:06 PM PDT 24 205347255 ps
T550 /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.2827458554 Aug 07 07:14:17 PM PDT 24 Aug 07 07:14:17 PM PDT 24 34725841 ps
T551 /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.2597351299 Aug 07 07:14:47 PM PDT 24 Aug 07 07:14:48 PM PDT 24 19619609 ps
T552 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.3200648744 Aug 07 07:14:34 PM PDT 24 Aug 07 07:14:34 PM PDT 24 92107900 ps
T553 /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.1373146914 Aug 07 07:14:43 PM PDT 24 Aug 07 07:14:43 PM PDT 24 17742633 ps
T554 /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2793053542 Aug 07 07:14:45 PM PDT 24 Aug 07 07:14:46 PM PDT 24 23688363 ps
T81 /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.2714383776 Aug 07 07:13:57 PM PDT 24 Aug 07 07:13:58 PM PDT 24 57915586 ps
T555 /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.3404581413 Aug 07 07:13:57 PM PDT 24 Aug 07 07:13:58 PM PDT 24 131746255 ps
T556 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.263190762 Aug 07 07:14:05 PM PDT 24 Aug 07 07:14:06 PM PDT 24 42510830 ps
T82 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.25106218 Aug 07 07:14:22 PM PDT 24 Aug 07 07:14:22 PM PDT 24 18381155 ps
T557 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.2995787934 Aug 07 07:14:06 PM PDT 24 Aug 07 07:14:08 PM PDT 24 231872769 ps
T558 /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.719642634 Aug 07 07:14:34 PM PDT 24 Aug 07 07:14:35 PM PDT 24 25855169 ps
T559 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.709483523 Aug 07 07:14:50 PM PDT 24 Aug 07 07:14:51 PM PDT 24 41746455 ps
T560 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.455099648 Aug 07 07:14:16 PM PDT 24 Aug 07 07:14:16 PM PDT 24 13622324 ps
T561 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.4212356926 Aug 07 07:14:48 PM PDT 24 Aug 07 07:14:49 PM PDT 24 37480405 ps
T562 /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.1060837395 Aug 07 07:14:05 PM PDT 24 Aug 07 07:14:05 PM PDT 24 41964726 ps
T563 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.4107668951 Aug 07 07:14:13 PM PDT 24 Aug 07 07:14:14 PM PDT 24 33481822 ps
T564 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.2408539399 Aug 07 07:14:45 PM PDT 24 Aug 07 07:14:45 PM PDT 24 12676057 ps
T565 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.22703987 Aug 07 07:14:23 PM PDT 24 Aug 07 07:14:24 PM PDT 24 122821237 ps
T566 /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.3114305385 Aug 07 07:13:55 PM PDT 24 Aug 07 07:13:56 PM PDT 24 16931400 ps
T567 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.1340670250 Aug 07 07:14:23 PM PDT 24 Aug 07 07:14:25 PM PDT 24 195988758 ps
T568 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3144360363 Aug 07 07:14:15 PM PDT 24 Aug 07 07:14:16 PM PDT 24 95531506 ps
T569 /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1128100629 Aug 07 07:14:12 PM PDT 24 Aug 07 07:14:13 PM PDT 24 31907916 ps
T570 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.399546988 Aug 07 07:14:16 PM PDT 24 Aug 07 07:14:18 PM PDT 24 208363961 ps
T571 /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.3734859884 Aug 07 07:14:45 PM PDT 24 Aug 07 07:14:45 PM PDT 24 45337850 ps
T572 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.2816431405 Aug 07 07:14:06 PM PDT 24 Aug 07 07:14:07 PM PDT 24 31020279 ps
T573 /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.1072083116 Aug 07 07:14:46 PM PDT 24 Aug 07 07:14:46 PM PDT 24 13618130 ps
T574 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.1712789696 Aug 07 07:14:44 PM PDT 24 Aug 07 07:14:45 PM PDT 24 41109260 ps
T575 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.981755221 Aug 07 07:14:42 PM PDT 24 Aug 07 07:14:43 PM PDT 24 40452929 ps
T576 /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.2553687498 Aug 07 07:14:47 PM PDT 24 Aug 07 07:14:48 PM PDT 24 132057919 ps
T577 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.182458196 Aug 07 07:14:36 PM PDT 24 Aug 07 07:14:36 PM PDT 24 20504772 ps
T578 /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.2476152212 Aug 07 07:14:34 PM PDT 24 Aug 07 07:14:35 PM PDT 24 20805348 ps
T579 /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2533975202 Aug 07 07:13:54 PM PDT 24 Aug 07 07:13:56 PM PDT 24 409693354 ps
T580 /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.199993479 Aug 07 07:14:33 PM PDT 24 Aug 07 07:14:34 PM PDT 24 37845438 ps
T581 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.1639811450 Aug 07 07:13:57 PM PDT 24 Aug 07 07:13:58 PM PDT 24 263983014 ps

Test location /workspace/coverage/default/6.rv_timer_stress_all_with_rand_reset.88008638
Short name T10
Test name
Test status
Simulation time 71236523676 ps
CPU time 533.36 seconds
Started Aug 07 05:36:56 PM PDT 24
Finished Aug 07 05:45:50 PM PDT 24
Peak memory 214704 kb
Host smart-22bb8e4f-70ef-4077-ba76-af84c9155264
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88008638 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all_with_rand_reset.88008638
Directory /workspace/6.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.861317761
Short name T12
Test name
Test status
Simulation time 3219430541540 ps
CPU time 1009.2 seconds
Started Aug 07 05:36:46 PM PDT 24
Finished Aug 07 05:53:36 PM PDT 24
Peak memory 183432 kb
Host smart-266038a5-68ea-47c0-8595-df9b5cc22c56
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861317761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.rv_timer_cfg_update_on_fly.861317761
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.1346886974
Short name T11
Test name
Test status
Simulation time 2800833865802 ps
CPU time 1877.93 seconds
Started Aug 07 05:36:59 PM PDT 24
Finished Aug 07 06:08:17 PM PDT 24
Peak memory 191552 kb
Host smart-28cf543f-c38a-4720-b68d-8d14a71ddeeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346886974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.1346886974
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.4059792855
Short name T30
Test name
Test status
Simulation time 49845734 ps
CPU time 0.88 seconds
Started Aug 07 07:14:16 PM PDT 24
Finished Aug 07 07:14:17 PM PDT 24
Peak memory 183308 kb
Host smart-47c56113-7516-413d-852e-df30c6094f08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059792855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.4059792855
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.2067738616
Short name T110
Test name
Test status
Simulation time 1317621380538 ps
CPU time 2890.8 seconds
Started Aug 07 05:37:11 PM PDT 24
Finished Aug 07 06:25:22 PM PDT 24
Peak memory 191548 kb
Host smart-8799065a-2cda-4dd3-bb0c-de792e3701ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067738616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.2067738616
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.4030574456
Short name T129
Test name
Test status
Simulation time 574871563343 ps
CPU time 1537.31 seconds
Started Aug 07 05:37:03 PM PDT 24
Finished Aug 07 06:02:40 PM PDT 24
Peak memory 191628 kb
Host smart-2fd6a8a2-177c-4e31-aa66-681c698a624a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030574456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.4030574456
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.47585303
Short name T58
Test name
Test status
Simulation time 1180175815359 ps
CPU time 674.12 seconds
Started Aug 07 05:36:48 PM PDT 24
Finished Aug 07 05:48:02 PM PDT 24
Peak memory 191632 kb
Host smart-ab0edf78-cf58-463d-ae3f-777ae4c0c04e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47585303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.47585303
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.3274438912
Short name T109
Test name
Test status
Simulation time 1263730910514 ps
CPU time 2070.96 seconds
Started Aug 07 05:37:24 PM PDT 24
Finished Aug 07 06:11:55 PM PDT 24
Peak memory 191596 kb
Host smart-e57f3ef8-d708-4e3d-9ea7-a6b896680d3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274438912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
3274438912
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all_with_rand_reset.1202373734
Short name T40
Test name
Test status
Simulation time 81538132329 ps
CPU time 641.69 seconds
Started Aug 07 05:37:26 PM PDT 24
Finished Aug 07 05:48:08 PM PDT 24
Peak memory 206388 kb
Host smart-de837ecc-e995-4a57-bf7d-adf911f1a2ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202373734 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all_with_rand_reset.1202373734
Directory /workspace/37.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.3729536479
Short name T289
Test name
Test status
Simulation time 511359437884 ps
CPU time 1160.14 seconds
Started Aug 07 05:36:56 PM PDT 24
Finished Aug 07 05:56:17 PM PDT 24
Peak memory 191612 kb
Host smart-6286aee7-8338-4936-a907-92c94b579146
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729536479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.3729536479
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.4165258840
Short name T292
Test name
Test status
Simulation time 796546546349 ps
CPU time 3795.53 seconds
Started Aug 07 05:37:04 PM PDT 24
Finished Aug 07 06:40:19 PM PDT 24
Peak memory 191604 kb
Host smart-93f510ea-4c82-4ce6-9caf-a53678888084
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165258840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.4165258840
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.489997336
Short name T246
Test name
Test status
Simulation time 1042805912427 ps
CPU time 1869.04 seconds
Started Aug 07 05:38:10 PM PDT 24
Finished Aug 07 06:09:19 PM PDT 24
Peak memory 191636 kb
Host smart-671e28e6-4313-4774-bcb7-693d612dea93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489997336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all.
489997336
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.1523040590
Short name T142
Test name
Test status
Simulation time 1386744638858 ps
CPU time 615.69 seconds
Started Aug 07 05:37:20 PM PDT 24
Finished Aug 07 05:47:36 PM PDT 24
Peak memory 196500 kb
Host smart-676ae8e8-5b49-41af-a83f-dfce1ce1443c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523040590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.1523040590
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.489630033
Short name T17
Test name
Test status
Simulation time 251208084 ps
CPU time 0.86 seconds
Started Aug 07 05:36:45 PM PDT 24
Finished Aug 07 05:36:46 PM PDT 24
Peak memory 214712 kb
Host smart-88f1b1ae-3fd4-4487-af48-50dbee1e0157
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489630033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.489630033
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.858881988
Short name T141
Test name
Test status
Simulation time 4021990980932 ps
CPU time 1212.18 seconds
Started Aug 07 05:37:10 PM PDT 24
Finished Aug 07 05:57:22 PM PDT 24
Peak memory 191628 kb
Host smart-c0e9f2a7-a643-4c38-b771-9e5c1ae26b70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858881988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.
858881988
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.3610424699
Short name T167
Test name
Test status
Simulation time 276954707817 ps
CPU time 1977.31 seconds
Started Aug 07 05:40:32 PM PDT 24
Finished Aug 07 06:13:30 PM PDT 24
Peak memory 191528 kb
Host smart-bdf6b356-e4a4-479a-85be-a8bcd92c9759
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610424699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.3610424699
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/187.rv_timer_random.1594277347
Short name T166
Test name
Test status
Simulation time 591193908377 ps
CPU time 706.85 seconds
Started Aug 07 05:39:55 PM PDT 24
Finished Aug 07 05:51:42 PM PDT 24
Peak memory 191608 kb
Host smart-25c2f01c-5259-4781-9a2e-6e188d56aaff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594277347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.1594277347
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.2024974073
Short name T233
Test name
Test status
Simulation time 567058769916 ps
CPU time 1508.59 seconds
Started Aug 07 05:37:21 PM PDT 24
Finished Aug 07 06:02:30 PM PDT 24
Peak memory 191656 kb
Host smart-4a734282-62cf-4d43-964b-90469bfd9ffd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024974073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.2024974073
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.1948402717
Short name T56
Test name
Test status
Simulation time 493346669133 ps
CPU time 890.1 seconds
Started Aug 07 05:36:54 PM PDT 24
Finished Aug 07 05:51:44 PM PDT 24
Peak memory 191600 kb
Host smart-3f148607-8495-4d92-a0a1-b156c565feed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948402717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
1948402717
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_random.453353879
Short name T7
Test name
Test status
Simulation time 147019343649 ps
CPU time 257 seconds
Started Aug 07 05:37:02 PM PDT 24
Finished Aug 07 05:41:20 PM PDT 24
Peak memory 191612 kb
Host smart-19fb1d10-dffe-4e26-9b8c-de0664773ba3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453353879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.453353879
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.626138970
Short name T107
Test name
Test status
Simulation time 93686432286 ps
CPU time 336.94 seconds
Started Aug 07 05:40:01 PM PDT 24
Finished Aug 07 05:45:38 PM PDT 24
Peak memory 191628 kb
Host smart-2787b1cc-6631-4965-8e7a-9ab88a757681
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626138970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.626138970
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.473733974
Short name T164
Test name
Test status
Simulation time 1235787007583 ps
CPU time 1360.01 seconds
Started Aug 07 05:38:02 PM PDT 24
Finished Aug 07 06:00:43 PM PDT 24
Peak memory 191660 kb
Host smart-29d971ea-fdfb-4a1e-82f2-4f78f893a525
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473733974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all.
473733974
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/125.rv_timer_random.2508320253
Short name T185
Test name
Test status
Simulation time 138382860437 ps
CPU time 194.45 seconds
Started Aug 07 05:39:12 PM PDT 24
Finished Aug 07 05:42:26 PM PDT 24
Peak memory 191644 kb
Host smart-22bccc3e-1db1-48fc-b37a-a6956d406094
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508320253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.2508320253
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.2517181121
Short name T133
Test name
Test status
Simulation time 290987847893 ps
CPU time 598.45 seconds
Started Aug 07 05:39:55 PM PDT 24
Finished Aug 07 05:49:53 PM PDT 24
Peak memory 191512 kb
Host smart-20c60b6f-b76a-4897-af51-4dc9afcbf8bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517181121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.2517181121
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/110.rv_timer_random.3762088813
Short name T287
Test name
Test status
Simulation time 689565689608 ps
CPU time 912.34 seconds
Started Aug 07 05:38:54 PM PDT 24
Finished Aug 07 05:54:06 PM PDT 24
Peak memory 191660 kb
Host smart-62974648-b583-432b-8473-86a1cb9de5a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762088813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.3762088813
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.2566110026
Short name T204
Test name
Test status
Simulation time 385370539041 ps
CPU time 580.78 seconds
Started Aug 07 05:39:28 PM PDT 24
Finished Aug 07 05:49:09 PM PDT 24
Peak memory 191632 kb
Host smart-37ed9423-ca0f-4643-bdda-cb4a39c0e9ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566110026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.2566110026
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.1475499056
Short name T262
Test name
Test status
Simulation time 394801320266 ps
CPU time 635.35 seconds
Started Aug 07 05:39:55 PM PDT 24
Finished Aug 07 05:50:31 PM PDT 24
Peak memory 191668 kb
Host smart-af4c35c4-4df9-4157-8f38-bc51dd6f4ab7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475499056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.1475499056
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.2792194082
Short name T236
Test name
Test status
Simulation time 185316918793 ps
CPU time 2014.7 seconds
Started Aug 07 05:38:40 PM PDT 24
Finished Aug 07 06:12:15 PM PDT 24
Peak memory 191632 kb
Host smart-00846ec4-0fdf-4367-ad5d-887b2ef5b8d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792194082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.2792194082
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.3661689500
Short name T29
Test name
Test status
Simulation time 202214096310 ps
CPU time 2209.5 seconds
Started Aug 07 05:39:11 PM PDT 24
Finished Aug 07 06:16:01 PM PDT 24
Peak memory 194268 kb
Host smart-e3f8c81c-11cc-4b5b-987f-580db3950bec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661689500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.3661689500
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.1082842471
Short name T423
Test name
Test status
Simulation time 135549917336 ps
CPU time 586.1 seconds
Started Aug 07 05:39:35 PM PDT 24
Finished Aug 07 05:49:22 PM PDT 24
Peak memory 191584 kb
Host smart-0c370c7d-d8b2-478a-9cd9-326bf23662b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082842471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.1082842471
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.2442840934
Short name T181
Test name
Test status
Simulation time 83661806214 ps
CPU time 133.92 seconds
Started Aug 07 05:37:04 PM PDT 24
Finished Aug 07 05:39:18 PM PDT 24
Peak memory 191620 kb
Host smart-00c3f32b-a0d5-49cb-9771-a23ef119572d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442840934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.2442840934
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/74.rv_timer_random.2352098442
Short name T91
Test name
Test status
Simulation time 1519788323242 ps
CPU time 444.22 seconds
Started Aug 07 05:38:31 PM PDT 24
Finished Aug 07 05:45:55 PM PDT 24
Peak memory 191540 kb
Host smart-0f6c6677-5e61-4a77-8c6b-aa5f5dd2617d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352098442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.2352098442
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.1228264332
Short name T54
Test name
Test status
Simulation time 250138382 ps
CPU time 2.79 seconds
Started Aug 07 07:13:55 PM PDT 24
Finished Aug 07 07:13:58 PM PDT 24
Peak memory 191336 kb
Host smart-c9445741-fd27-41ef-8291-f45f1287bd74
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228264332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.1228264332
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/default/108.rv_timer_random.195800282
Short name T216
Test name
Test status
Simulation time 150446584156 ps
CPU time 449.9 seconds
Started Aug 07 05:38:55 PM PDT 24
Finished Aug 07 05:46:25 PM PDT 24
Peak memory 191656 kb
Host smart-1fba3218-1e63-4e4b-8d85-1688ec652990
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195800282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.195800282
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.1068798032
Short name T293
Test name
Test status
Simulation time 179845492230 ps
CPU time 1058.77 seconds
Started Aug 07 05:39:00 PM PDT 24
Finished Aug 07 05:56:39 PM PDT 24
Peak memory 191620 kb
Host smart-cd22e1d9-7c66-41c4-a2dc-2629d3b96ca1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068798032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.1068798032
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.1632793331
Short name T198
Test name
Test status
Simulation time 99824626717 ps
CPU time 139.86 seconds
Started Aug 07 05:39:00 PM PDT 24
Finished Aug 07 05:41:20 PM PDT 24
Peak memory 191676 kb
Host smart-82c810f0-711f-4252-b183-4a4223acbf45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632793331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.1632793331
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.391504365
Short name T205
Test name
Test status
Simulation time 620498364388 ps
CPU time 489.23 seconds
Started Aug 07 05:39:18 PM PDT 24
Finished Aug 07 05:47:28 PM PDT 24
Peak memory 191644 kb
Host smart-1d983f00-8041-462b-b111-c87911158857
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391504365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.391504365
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.3791367695
Short name T176
Test name
Test status
Simulation time 122756947780 ps
CPU time 268.12 seconds
Started Aug 07 05:39:39 PM PDT 24
Finished Aug 07 05:44:07 PM PDT 24
Peak memory 194968 kb
Host smart-872017c4-3b07-4016-bb0f-0226108d3e97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791367695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.3791367695
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.416898926
Short name T135
Test name
Test status
Simulation time 275153608792 ps
CPU time 714.8 seconds
Started Aug 07 05:38:22 PM PDT 24
Finished Aug 07 05:50:17 PM PDT 24
Peak memory 191648 kb
Host smart-ee596f00-989a-4990-8841-206f36444c18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416898926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.416898926
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.1101505010
Short name T24
Test name
Test status
Simulation time 152046453555 ps
CPU time 686.61 seconds
Started Aug 07 05:38:21 PM PDT 24
Finished Aug 07 05:49:47 PM PDT 24
Peak memory 191648 kb
Host smart-7baffe2c-7229-4bc0-9d7d-83619976800c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101505010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.1101505010
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random.1433143185
Short name T155
Test name
Test status
Simulation time 147844176955 ps
CPU time 265.81 seconds
Started Aug 07 05:36:51 PM PDT 24
Finished Aug 07 05:41:17 PM PDT 24
Peak memory 191648 kb
Host smart-6ed123da-4da3-4509-a19d-1e242f3f3957
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433143185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.1433143185
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.115476284
Short name T5
Test name
Test status
Simulation time 2706606656446 ps
CPU time 526.99 seconds
Started Aug 07 05:39:00 PM PDT 24
Finished Aug 07 05:47:47 PM PDT 24
Peak memory 191592 kb
Host smart-6156396d-1b72-442b-8daa-50b32152e61d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115476284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.115476284
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.3672193436
Short name T152
Test name
Test status
Simulation time 1160780843278 ps
CPU time 465 seconds
Started Aug 07 05:39:07 PM PDT 24
Finished Aug 07 05:46:52 PM PDT 24
Peak memory 191624 kb
Host smart-17784710-5e02-4f80-9bae-984baed0e241
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672193436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.3672193436
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.2196117125
Short name T171
Test name
Test status
Simulation time 791550336404 ps
CPU time 795.05 seconds
Started Aug 07 05:39:06 PM PDT 24
Finished Aug 07 05:52:22 PM PDT 24
Peak memory 191556 kb
Host smart-d6b5d4d5-73df-490c-b4e9-ee427b293e3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196117125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.2196117125
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.3625591521
Short name T212
Test name
Test status
Simulation time 199011717915 ps
CPU time 306.29 seconds
Started Aug 07 05:39:27 PM PDT 24
Finished Aug 07 05:44:34 PM PDT 24
Peak memory 191528 kb
Host smart-51f67551-0df2-4c75-8c1f-aa12a1f6f4c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625591521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.3625591521
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.4169645066
Short name T201
Test name
Test status
Simulation time 57355116751 ps
CPU time 100.36 seconds
Started Aug 07 05:39:38 PM PDT 24
Finished Aug 07 05:41:19 PM PDT 24
Peak memory 191668 kb
Host smart-8464f02e-b502-40a8-a972-12e037675a71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169645066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.4169645066
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.2767717110
Short name T104
Test name
Test status
Simulation time 1315974475647 ps
CPU time 318.4 seconds
Started Aug 07 05:39:49 PM PDT 24
Finished Aug 07 05:45:07 PM PDT 24
Peak memory 191660 kb
Host smart-63e78737-8b15-47fc-b91b-6881d6f42fda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767717110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.2767717110
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random.3758653737
Short name T270
Test name
Test status
Simulation time 97122781135 ps
CPU time 2236.14 seconds
Started Aug 07 05:37:11 PM PDT 24
Finished Aug 07 06:14:27 PM PDT 24
Peak memory 191608 kb
Host smart-355003c6-757d-4f31-b875-b25945cfcb8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758653737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.3758653737
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.1426455689
Short name T268
Test name
Test status
Simulation time 117092160759 ps
CPU time 188.07 seconds
Started Aug 07 05:36:54 PM PDT 24
Finished Aug 07 05:40:02 PM PDT 24
Peak memory 183428 kb
Host smart-6e68ab8f-2bd2-4564-bba1-7364e8b691fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426455689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.1426455689
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_random.4165005240
Short name T26
Test name
Test status
Simulation time 1367197017279 ps
CPU time 586.08 seconds
Started Aug 07 05:36:51 PM PDT 24
Finished Aug 07 05:46:37 PM PDT 24
Peak memory 191596 kb
Host smart-ac427b02-1e6d-4823-a699-63321c39c219
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165005240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.4165005240
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.331495766
Short name T88
Test name
Test status
Simulation time 99979010689 ps
CPU time 313.56 seconds
Started Aug 07 05:39:28 PM PDT 24
Finished Aug 07 05:44:42 PM PDT 24
Peak memory 191620 kb
Host smart-d468f142-50eb-45a6-be26-5bd6b18c1198
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331495766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.331495766
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.4068605819
Short name T120
Test name
Test status
Simulation time 581328913576 ps
CPU time 438.17 seconds
Started Aug 07 05:39:33 PM PDT 24
Finished Aug 07 05:46:51 PM PDT 24
Peak memory 191632 kb
Host smart-0440c19b-27ab-445e-8336-05c77b2e944e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068605819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.4068605819
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.1693805014
Short name T266
Test name
Test status
Simulation time 130762869375 ps
CPU time 516.48 seconds
Started Aug 07 05:39:39 PM PDT 24
Finished Aug 07 05:48:16 PM PDT 24
Peak memory 194972 kb
Host smart-b7f25038-1db7-4b33-9a96-f8c6037ddb81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693805014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.1693805014
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.3139646931
Short name T139
Test name
Test status
Simulation time 552402947678 ps
CPU time 803.7 seconds
Started Aug 07 05:37:15 PM PDT 24
Finished Aug 07 05:50:39 PM PDT 24
Peak memory 195644 kb
Host smart-2a3f95ea-8d19-4c05-8cc2-c56f1afc9e94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139646931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.3139646931
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.3498239963
Short name T223
Test name
Test status
Simulation time 378865220806 ps
CPU time 887.71 seconds
Started Aug 07 05:37:20 PM PDT 24
Finished Aug 07 05:52:08 PM PDT 24
Peak memory 195776 kb
Host smart-73bf4c85-2bd8-402d-8509-e5596a5a41b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498239963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.3498239963
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_random.63203329
Short name T182
Test name
Test status
Simulation time 1399026792043 ps
CPU time 558.05 seconds
Started Aug 07 05:37:19 PM PDT 24
Finished Aug 07 05:46:37 PM PDT 24
Peak memory 191620 kb
Host smart-a867b2f3-30d2-471c-ab5d-eb3e4cbbddee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63203329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.63203329
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.2973073213
Short name T66
Test name
Test status
Simulation time 410168146767 ps
CPU time 535.16 seconds
Started Aug 07 05:37:51 PM PDT 24
Finished Aug 07 05:46:46 PM PDT 24
Peak memory 191628 kb
Host smart-505047d3-273e-4e38-8442-f298f279589e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973073213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.2973073213
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/71.rv_timer_random.3606252521
Short name T210
Test name
Test status
Simulation time 100978765856 ps
CPU time 742.18 seconds
Started Aug 07 05:38:32 PM PDT 24
Finished Aug 07 05:50:54 PM PDT 24
Peak memory 191580 kb
Host smart-70c10d5b-be22-4aff-9b3a-ce20faeef619
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606252521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.3606252521
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.3172748932
Short name T203
Test name
Test status
Simulation time 1381608240273 ps
CPU time 991.57 seconds
Started Aug 07 05:36:51 PM PDT 24
Finished Aug 07 05:53:23 PM PDT 24
Peak memory 194600 kb
Host smart-09991f2d-576b-4920-a51e-e6e5271fa233
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172748932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
3172748932
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.1736725344
Short name T92
Test name
Test status
Simulation time 50032672 ps
CPU time 0.65 seconds
Started Aug 07 07:13:57 PM PDT 24
Finished Aug 07 07:13:57 PM PDT 24
Peak memory 191740 kb
Host smart-cef81ad2-688e-4e04-a010-9763ad1b80b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736725344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.1736725344
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.545812375
Short name T99
Test name
Test status
Simulation time 70794683 ps
CPU time 1.07 seconds
Started Aug 07 07:14:23 PM PDT 24
Finished Aug 07 07:14:24 PM PDT 24
Peak memory 195332 kb
Host smart-bb486554-ebd2-4295-9823-606652800c7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545812375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_in
tg_err.545812375
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/104.rv_timer_random.4275558578
Short name T242
Test name
Test status
Simulation time 679058133925 ps
CPU time 1157.77 seconds
Started Aug 07 05:38:56 PM PDT 24
Finished Aug 07 05:58:14 PM PDT 24
Peak memory 191632 kb
Host smart-68a1bbd6-396b-4feb-857c-2484e8243151
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275558578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.4275558578
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.2077368032
Short name T3
Test name
Test status
Simulation time 184519489506 ps
CPU time 102.04 seconds
Started Aug 07 05:39:06 PM PDT 24
Finished Aug 07 05:40:48 PM PDT 24
Peak memory 191536 kb
Host smart-8973977b-6e39-40c1-8748-add4d10de869
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077368032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.2077368032
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.2004964891
Short name T258
Test name
Test status
Simulation time 274783173189 ps
CPU time 231.08 seconds
Started Aug 07 05:39:19 PM PDT 24
Finished Aug 07 05:43:10 PM PDT 24
Peak memory 195256 kb
Host smart-f25fb98a-3e10-45d8-af07-65413eb43179
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004964891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.2004964891
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.135161651
Short name T118
Test name
Test status
Simulation time 66760848575 ps
CPU time 166.1 seconds
Started Aug 07 05:36:57 PM PDT 24
Finished Aug 07 05:39:43 PM PDT 24
Peak memory 195152 kb
Host smart-fb16e9a5-4af1-406a-8d93-b1b4e131638d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135161651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.135161651
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/152.rv_timer_random.1811004583
Short name T189
Test name
Test status
Simulation time 649402129836 ps
CPU time 1712.71 seconds
Started Aug 07 05:39:36 PM PDT 24
Finished Aug 07 06:08:09 PM PDT 24
Peak memory 191576 kb
Host smart-b4c44425-e8e5-46fb-9e9c-d1ef5a3af550
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811004583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.1811004583
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/160.rv_timer_random.1462741745
Short name T240
Test name
Test status
Simulation time 75932971671 ps
CPU time 146.77 seconds
Started Aug 07 05:39:36 PM PDT 24
Finished Aug 07 05:42:03 PM PDT 24
Peak memory 191512 kb
Host smart-0e4c90a2-7f85-49f6-a961-3668a6589157
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462741745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.1462741745
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.2309715993
Short name T340
Test name
Test status
Simulation time 190856878662 ps
CPU time 154.18 seconds
Started Aug 07 05:39:32 PM PDT 24
Finished Aug 07 05:42:06 PM PDT 24
Peak memory 191504 kb
Host smart-79beab0b-c334-45aa-97ff-ec42a5d2dad2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309715993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.2309715993
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.3990003055
Short name T239
Test name
Test status
Simulation time 103006355594 ps
CPU time 194.61 seconds
Started Aug 07 05:40:00 PM PDT 24
Finished Aug 07 05:43:15 PM PDT 24
Peak memory 191616 kb
Host smart-c6fff9be-dd7d-4bea-905e-937dea13fa7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990003055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.3990003055
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.3544919653
Short name T244
Test name
Test status
Simulation time 137361341286 ps
CPU time 154.58 seconds
Started Aug 07 05:37:03 PM PDT 24
Finished Aug 07 05:39:38 PM PDT 24
Peak memory 195224 kb
Host smart-630aacca-c533-45f4-8caa-b6ef66313e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544919653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.3544919653
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.3364569636
Short name T310
Test name
Test status
Simulation time 622467060963 ps
CPU time 1040.01 seconds
Started Aug 07 05:37:02 PM PDT 24
Finished Aug 07 05:54:23 PM PDT 24
Peak memory 183428 kb
Host smart-49bc14a5-b5a9-46e6-9e31-2cfff1cca1fe
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364569636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.3364569636
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.3301380593
Short name T325
Test name
Test status
Simulation time 1381406981060 ps
CPU time 781.88 seconds
Started Aug 07 05:37:10 PM PDT 24
Finished Aug 07 05:50:12 PM PDT 24
Peak memory 183412 kb
Host smart-6f1abc87-375a-4703-bcb0-c90293c6ec6b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301380593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.3301380593
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_random.880273134
Short name T27
Test name
Test status
Simulation time 999479659355 ps
CPU time 377.45 seconds
Started Aug 07 05:37:15 PM PDT 24
Finished Aug 07 05:43:32 PM PDT 24
Peak memory 191660 kb
Host smart-59c8fdd6-8c54-4566-84d3-df75de1b38bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880273134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.880273134
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.2648078037
Short name T175
Test name
Test status
Simulation time 426236529606 ps
CPU time 590.53 seconds
Started Aug 07 05:38:16 PM PDT 24
Finished Aug 07 05:48:06 PM PDT 24
Peak memory 191600 kb
Host smart-7f424408-5c21-4360-9505-9d7c132d56f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648078037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.2648078037
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/53.rv_timer_random.1586027430
Short name T154
Test name
Test status
Simulation time 216583640983 ps
CPU time 596.76 seconds
Started Aug 07 05:38:20 PM PDT 24
Finished Aug 07 05:48:17 PM PDT 24
Peak memory 191664 kb
Host smart-dfd490de-a9bb-44b6-9848-3a230b8d37f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586027430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.1586027430
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.1832595607
Short name T329
Test name
Test status
Simulation time 131650269240 ps
CPU time 494.74 seconds
Started Aug 07 05:38:23 PM PDT 24
Finished Aug 07 05:46:38 PM PDT 24
Peak memory 194456 kb
Host smart-b730f0c2-ff63-48fc-871b-ecd0208a5ff8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832595607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.1832595607
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.3795229301
Short name T172
Test name
Test status
Simulation time 539780625546 ps
CPU time 925.41 seconds
Started Aug 07 05:38:18 PM PDT 24
Finished Aug 07 05:53:44 PM PDT 24
Peak memory 191620 kb
Host smart-461b499e-4de5-4a0a-a29c-915933d5173e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795229301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.3795229301
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.1792000797
Short name T134
Test name
Test status
Simulation time 678225803277 ps
CPU time 665.31 seconds
Started Aug 07 05:38:34 PM PDT 24
Finished Aug 07 05:49:40 PM PDT 24
Peak memory 195332 kb
Host smart-a06c6a12-0296-486e-8b67-c016ee0a33b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792000797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.1792000797
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.2875279378
Short name T334
Test name
Test status
Simulation time 316973928547 ps
CPU time 274.93 seconds
Started Aug 07 05:38:42 PM PDT 24
Finished Aug 07 05:43:17 PM PDT 24
Peak memory 191636 kb
Host smart-671cb490-5439-4f4a-a7be-88d8027fb1e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875279378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.2875279378
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.2377271331
Short name T196
Test name
Test status
Simulation time 157212062262 ps
CPU time 588.77 seconds
Started Aug 07 05:38:46 PM PDT 24
Finished Aug 07 05:48:35 PM PDT 24
Peak memory 191632 kb
Host smart-33230991-71cb-41e0-ad2f-e157683ce1df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377271331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.2377271331
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random.1985783706
Short name T170
Test name
Test status
Simulation time 126899403027 ps
CPU time 848.34 seconds
Started Aug 07 05:36:57 PM PDT 24
Finished Aug 07 05:51:06 PM PDT 24
Peak memory 191608 kb
Host smart-88dd20fb-fe5c-40a2-8777-f255c8c46730
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985783706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.1985783706
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.2718482001
Short name T161
Test name
Test status
Simulation time 257116844994 ps
CPU time 912.76 seconds
Started Aug 07 05:36:57 PM PDT 24
Finished Aug 07 05:52:10 PM PDT 24
Peak memory 195308 kb
Host smart-18fd987e-418b-46f1-93e4-1288ef291cc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718482001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.2718482001
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/123.rv_timer_random.3221920109
Short name T330
Test name
Test status
Simulation time 70833859634 ps
CPU time 69.59 seconds
Started Aug 07 05:39:07 PM PDT 24
Finished Aug 07 05:40:16 PM PDT 24
Peak memory 191676 kb
Host smart-30b1463c-06d0-44d1-a7ec-0c455d75bd0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221920109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.3221920109
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.1070912510
Short name T256
Test name
Test status
Simulation time 128676626224 ps
CPU time 53.95 seconds
Started Aug 07 05:39:06 PM PDT 24
Finished Aug 07 05:40:00 PM PDT 24
Peak memory 183456 kb
Host smart-9404a5b2-cdf5-4341-bc9f-7409d6e27719
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070912510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.1070912510
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random.307300982
Short name T298
Test name
Test status
Simulation time 130395307965 ps
CPU time 228.96 seconds
Started Aug 07 05:36:56 PM PDT 24
Finished Aug 07 05:40:46 PM PDT 24
Peak memory 191600 kb
Host smart-8fc71ae2-0b83-4631-80a9-a29e51c7d4b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307300982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.307300982
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.3624854267
Short name T316
Test name
Test status
Simulation time 164554720367 ps
CPU time 72.19 seconds
Started Aug 07 05:39:16 PM PDT 24
Finished Aug 07 05:40:29 PM PDT 24
Peak memory 191572 kb
Host smart-b5183b27-3066-4131-9861-d29c18179e53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624854267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.3624854267
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.1179428965
Short name T232
Test name
Test status
Simulation time 99303010620 ps
CPU time 349.65 seconds
Started Aug 07 05:39:19 PM PDT 24
Finished Aug 07 05:45:09 PM PDT 24
Peak memory 191668 kb
Host smart-649cdeff-f79a-4312-bf12-6bc213047004
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179428965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.1179428965
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.147964586
Short name T352
Test name
Test status
Simulation time 326470968662 ps
CPU time 379.81 seconds
Started Aug 07 05:39:32 PM PDT 24
Finished Aug 07 05:45:52 PM PDT 24
Peak memory 191552 kb
Host smart-174632a9-7a99-456d-b00f-e543250ea7f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147964586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.147964586
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.2960523931
Short name T131
Test name
Test status
Simulation time 42628009638 ps
CPU time 96.37 seconds
Started Aug 07 05:39:32 PM PDT 24
Finished Aug 07 05:41:08 PM PDT 24
Peak memory 183396 kb
Host smart-7605af87-6b5b-4ad2-be37-5436c3984965
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960523931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.2960523931
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.2854103698
Short name T346
Test name
Test status
Simulation time 59354428832 ps
CPU time 523.73 seconds
Started Aug 07 05:36:58 PM PDT 24
Finished Aug 07 05:45:42 PM PDT 24
Peak memory 191528 kb
Host smart-c3e94754-6722-4c1f-b8c2-07ea231b2677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854103698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.2854103698
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.111538124
Short name T217
Test name
Test status
Simulation time 1720695749779 ps
CPU time 817.15 seconds
Started Aug 07 05:36:56 PM PDT 24
Finished Aug 07 05:50:34 PM PDT 24
Peak memory 183420 kb
Host smart-79a24d7c-7e12-4350-bd39-c013cd956692
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111538124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.rv_timer_cfg_update_on_fly.111538124
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/189.rv_timer_random.3949979066
Short name T146
Test name
Test status
Simulation time 867368240174 ps
CPU time 240.17 seconds
Started Aug 07 05:39:54 PM PDT 24
Finished Aug 07 05:43:54 PM PDT 24
Peak memory 191628 kb
Host smart-20d95520-8d9c-4f03-af44-8f61de0501d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949979066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.3949979066
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/190.rv_timer_random.3157654314
Short name T351
Test name
Test status
Simulation time 781376618911 ps
CPU time 811.95 seconds
Started Aug 07 05:39:55 PM PDT 24
Finished Aug 07 05:53:27 PM PDT 24
Peak memory 191676 kb
Host smart-d7dd9a25-dc0c-48a6-b626-fb3fb24e7dd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157654314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.3157654314
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.2763723786
Short name T125
Test name
Test status
Simulation time 247385216255 ps
CPU time 250.8 seconds
Started Aug 07 05:40:00 PM PDT 24
Finished Aug 07 05:44:11 PM PDT 24
Peak memory 191684 kb
Host smart-93026195-595c-4d12-8c68-4589ebcea59d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763723786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.2763723786
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.1276124325
Short name T264
Test name
Test status
Simulation time 300391399844 ps
CPU time 183.86 seconds
Started Aug 07 05:37:03 PM PDT 24
Finished Aug 07 05:40:07 PM PDT 24
Peak memory 195568 kb
Host smart-f59d0644-f5db-4b69-92fc-bf38f2619f7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276124325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.1276124325
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.1996769154
Short name T160
Test name
Test status
Simulation time 454264921453 ps
CPU time 373.07 seconds
Started Aug 07 05:37:10 PM PDT 24
Finished Aug 07 05:43:24 PM PDT 24
Peak memory 183372 kb
Host smart-5b56a3c9-80a4-49a2-9693-7027d1e2db4e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996769154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.1996769154
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.3846724153
Short name T43
Test name
Test status
Simulation time 744449484488 ps
CPU time 352.95 seconds
Started Aug 07 05:38:18 PM PDT 24
Finished Aug 07 05:44:11 PM PDT 24
Peak memory 183376 kb
Host smart-431eadd9-b520-47a4-afea-e2755588012c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846724153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.3846724153
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/90.rv_timer_random.2740412987
Short name T302
Test name
Test status
Simulation time 262447392000 ps
CPU time 487.48 seconds
Started Aug 07 05:38:42 PM PDT 24
Finished Aug 07 05:46:50 PM PDT 24
Peak memory 191548 kb
Host smart-4df69491-4a06-481e-ac80-ce0f8235324a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740412987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.2740412987
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.4068342951
Short name T481
Test name
Test status
Simulation time 500668298 ps
CPU time 0.83 seconds
Started Aug 07 07:13:54 PM PDT 24
Finished Aug 07 07:13:55 PM PDT 24
Peak memory 192892 kb
Host smart-72203162-5abd-40e6-8b35-8ca6c9824299
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068342951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.4068342951
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.3262086827
Short name T477
Test name
Test status
Simulation time 19493911 ps
CPU time 0.58 seconds
Started Aug 07 07:13:56 PM PDT 24
Finished Aug 07 07:13:56 PM PDT 24
Peak memory 182944 kb
Host smart-42f8ad43-c72b-40b0-bf2d-e0f4d7a41a2b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262086827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.3262086827
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.3404581413
Short name T555
Test name
Test status
Simulation time 131746255 ps
CPU time 0.84 seconds
Started Aug 07 07:13:57 PM PDT 24
Finished Aug 07 07:13:58 PM PDT 24
Peak memory 196704 kb
Host smart-d4e4db20-78e4-4798-bbba-a8e94d7f98a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404581413 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.3404581413
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.3114305385
Short name T566
Test name
Test status
Simulation time 16931400 ps
CPU time 0.58 seconds
Started Aug 07 07:13:55 PM PDT 24
Finished Aug 07 07:13:56 PM PDT 24
Peak memory 182960 kb
Host smart-76b57753-b27c-499c-b5e9-2aeedcbae599
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114305385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.3114305385
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.2238724807
Short name T535
Test name
Test status
Simulation time 44389902 ps
CPU time 0.56 seconds
Started Aug 07 07:13:55 PM PDT 24
Finished Aug 07 07:13:56 PM PDT 24
Peak memory 182784 kb
Host smart-82880afc-fa50-469f-8183-b1ce7a9a33e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238724807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.2238724807
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.476771021
Short name T526
Test name
Test status
Simulation time 85090916 ps
CPU time 0.71 seconds
Started Aug 07 07:13:56 PM PDT 24
Finished Aug 07 07:13:57 PM PDT 24
Peak memory 193364 kb
Host smart-a8ef92b8-4c2f-428e-b350-431cb64202fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476771021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_tim
er_same_csr_outstanding.476771021
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.1639811450
Short name T581
Test name
Test status
Simulation time 263983014 ps
CPU time 1.51 seconds
Started Aug 07 07:13:57 PM PDT 24
Finished Aug 07 07:13:58 PM PDT 24
Peak memory 197716 kb
Host smart-8a393014-45bf-4920-8084-ddd25f75808d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639811450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.1639811450
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1156517803
Short name T32
Test name
Test status
Simulation time 231020050 ps
CPU time 1.41 seconds
Started Aug 07 07:13:55 PM PDT 24
Finished Aug 07 07:13:57 PM PDT 24
Peak memory 195792 kb
Host smart-3e8c78a2-41ee-46f5-80ba-7c197a8031d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156517803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.1156517803
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.539096793
Short name T459
Test name
Test status
Simulation time 29980137 ps
CPU time 0.6 seconds
Started Aug 07 07:13:54 PM PDT 24
Finished Aug 07 07:13:55 PM PDT 24
Peak memory 182888 kb
Host smart-e602b19a-1555-47a2-be34-9f051d021138
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539096793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alias
ing.539096793
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2533975202
Short name T579
Test name
Test status
Simulation time 409693354 ps
CPU time 1.57 seconds
Started Aug 07 07:13:54 PM PDT 24
Finished Aug 07 07:13:56 PM PDT 24
Peak memory 193072 kb
Host smart-33f2034f-77b6-4fbd-aae7-68e6218f98fe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533975202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.2533975202
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1738280342
Short name T453
Test name
Test status
Simulation time 16238657 ps
CPU time 0.54 seconds
Started Aug 07 07:13:55 PM PDT 24
Finished Aug 07 07:13:56 PM PDT 24
Peak memory 182872 kb
Host smart-121f67bc-c6f7-4e88-a010-5ade364e9699
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738280342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.1738280342
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.557092884
Short name T540
Test name
Test status
Simulation time 51624002 ps
CPU time 0.62 seconds
Started Aug 07 07:13:56 PM PDT 24
Finished Aug 07 07:13:57 PM PDT 24
Peak memory 192952 kb
Host smart-bc96fae0-35f7-444d-95a7-da2a9e4a7cb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557092884 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.557092884
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.1482016691
Short name T474
Test name
Test status
Simulation time 15148850 ps
CPU time 0.61 seconds
Started Aug 07 07:13:56 PM PDT 24
Finished Aug 07 07:13:56 PM PDT 24
Peak memory 182968 kb
Host smart-8939ebe5-6324-4f57-af03-26749fa92f72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482016691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.1482016691
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.1200179693
Short name T485
Test name
Test status
Simulation time 16398252 ps
CPU time 0.59 seconds
Started Aug 07 07:13:55 PM PDT 24
Finished Aug 07 07:13:56 PM PDT 24
Peak memory 182812 kb
Host smart-15d137b6-5a03-43a6-9b9b-e946a12fca08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200179693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.1200179693
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.2370035600
Short name T484
Test name
Test status
Simulation time 136067919 ps
CPU time 1.43 seconds
Started Aug 07 07:13:56 PM PDT 24
Finished Aug 07 07:13:57 PM PDT 24
Peak memory 197700 kb
Host smart-f8193b70-dd41-4c7e-ae89-919d147536dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370035600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.2370035600
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3461867244
Short name T460
Test name
Test status
Simulation time 350850288 ps
CPU time 1.32 seconds
Started Aug 07 07:13:56 PM PDT 24
Finished Aug 07 07:13:57 PM PDT 24
Peak memory 195456 kb
Host smart-93231a90-b274-434c-a17e-36e38e0919f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461867244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.3461867244
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.1193859179
Short name T470
Test name
Test status
Simulation time 26543179 ps
CPU time 0.72 seconds
Started Aug 07 07:14:22 PM PDT 24
Finished Aug 07 07:14:23 PM PDT 24
Peak memory 195412 kb
Host smart-e33b9934-85d9-4931-b6e0-ef163cd5fd2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193859179 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.1193859179
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.22703987
Short name T565
Test name
Test status
Simulation time 122821237 ps
CPU time 0.62 seconds
Started Aug 07 07:14:23 PM PDT 24
Finished Aug 07 07:14:24 PM PDT 24
Peak memory 182964 kb
Host smart-2d343b73-8a9c-4618-9df9-2ac541d2ce68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22703987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.22703987
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.4160793924
Short name T493
Test name
Test status
Simulation time 49493702 ps
CPU time 0.56 seconds
Started Aug 07 07:14:25 PM PDT 24
Finished Aug 07 07:14:25 PM PDT 24
Peak memory 182800 kb
Host smart-f0ba06ab-443d-4fe4-92a8-da1b02739c9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160793924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.4160793924
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.3770129590
Short name T34
Test name
Test status
Simulation time 27654502 ps
CPU time 0.72 seconds
Started Aug 07 07:14:24 PM PDT 24
Finished Aug 07 07:14:24 PM PDT 24
Peak memory 192480 kb
Host smart-1208f52b-099f-425b-a719-bb47f607ef29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770129590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.3770129590
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.399546988
Short name T570
Test name
Test status
Simulation time 208363961 ps
CPU time 1.31 seconds
Started Aug 07 07:14:16 PM PDT 24
Finished Aug 07 07:14:18 PM PDT 24
Peak memory 196304 kb
Host smart-e391b59c-0c86-46e2-9197-d7a14b9ce690
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399546988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.399546988
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.2815136630
Short name T463
Test name
Test status
Simulation time 30227654 ps
CPU time 1.12 seconds
Started Aug 07 07:14:24 PM PDT 24
Finished Aug 07 07:14:26 PM PDT 24
Peak memory 197684 kb
Host smart-3a1fedd7-139d-4f4f-98ef-3a6ec1680a26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815136630 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.2815136630
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.1572489011
Short name T480
Test name
Test status
Simulation time 44859071 ps
CPU time 0.58 seconds
Started Aug 07 07:14:23 PM PDT 24
Finished Aug 07 07:14:24 PM PDT 24
Peak memory 182968 kb
Host smart-ba37eb51-6d75-466c-9077-1c41dede9862
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572489011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.1572489011
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.3417250611
Short name T506
Test name
Test status
Simulation time 17620297 ps
CPU time 0.56 seconds
Started Aug 07 07:14:23 PM PDT 24
Finished Aug 07 07:14:24 PM PDT 24
Peak memory 182776 kb
Host smart-893346f9-4ef8-439b-bc4b-40a8177ed146
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417250611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.3417250611
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.1996205546
Short name T94
Test name
Test status
Simulation time 14386087 ps
CPU time 0.58 seconds
Started Aug 07 07:14:23 PM PDT 24
Finished Aug 07 07:14:24 PM PDT 24
Peak memory 192192 kb
Host smart-b7798fd4-8c97-489a-bef7-01c7e21d34c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996205546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.1996205546
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.2287827011
Short name T490
Test name
Test status
Simulation time 299632754 ps
CPU time 1.54 seconds
Started Aug 07 07:14:23 PM PDT 24
Finished Aug 07 07:14:25 PM PDT 24
Peak memory 197724 kb
Host smart-d978260e-c7ab-4d8a-875b-17b5cedf1f59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287827011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.2287827011
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.4261523820
Short name T542
Test name
Test status
Simulation time 186621277 ps
CPU time 1.47 seconds
Started Aug 07 07:14:25 PM PDT 24
Finished Aug 07 07:14:27 PM PDT 24
Peak memory 195584 kb
Host smart-c88fd70b-43c8-48d6-8def-7c3dd9cc7ca7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261523820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.4261523820
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3723860900
Short name T449
Test name
Test status
Simulation time 34984860 ps
CPU time 0.83 seconds
Started Aug 07 07:14:26 PM PDT 24
Finished Aug 07 07:14:27 PM PDT 24
Peak memory 196480 kb
Host smart-78186bc4-640d-411d-8789-331afe3124b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723860900 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.3723860900
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.90400279
Short name T511
Test name
Test status
Simulation time 21582257 ps
CPU time 0.56 seconds
Started Aug 07 07:14:24 PM PDT 24
Finished Aug 07 07:14:25 PM PDT 24
Peak memory 183016 kb
Host smart-50c6d1fb-4d6f-401d-a78a-82a9b9ac021c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90400279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.90400279
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.2891130378
Short name T539
Test name
Test status
Simulation time 51998004 ps
CPU time 0.55 seconds
Started Aug 07 07:14:23 PM PDT 24
Finished Aug 07 07:14:23 PM PDT 24
Peak memory 182688 kb
Host smart-3bd10503-8bbd-417f-b335-63ccf7a0c4b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891130378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.2891130378
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.725704291
Short name T51
Test name
Test status
Simulation time 99455557 ps
CPU time 0.7 seconds
Started Aug 07 07:14:21 PM PDT 24
Finished Aug 07 07:14:22 PM PDT 24
Peak memory 193340 kb
Host smart-f1a78275-85a2-4a7a-9042-63b44d11eb2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725704291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_ti
mer_same_csr_outstanding.725704291
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.175087442
Short name T541
Test name
Test status
Simulation time 178900239 ps
CPU time 1.18 seconds
Started Aug 07 07:14:24 PM PDT 24
Finished Aug 07 07:14:26 PM PDT 24
Peak memory 197468 kb
Host smart-b5b8137d-4daa-405a-975f-50eb59164d99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175087442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.175087442
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.2036513246
Short name T498
Test name
Test status
Simulation time 375554009 ps
CPU time 1.26 seconds
Started Aug 07 07:14:24 PM PDT 24
Finished Aug 07 07:14:25 PM PDT 24
Peak memory 195536 kb
Host smart-bf8bbece-3377-4fa0-bbfe-e4a6e0789d90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036513246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.2036513246
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.3070894260
Short name T482
Test name
Test status
Simulation time 32355166 ps
CPU time 1.3 seconds
Started Aug 07 07:14:24 PM PDT 24
Finished Aug 07 07:14:26 PM PDT 24
Peak memory 197720 kb
Host smart-d23f9026-a17e-48ee-a382-72a569c4089c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070894260 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.3070894260
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.25106218
Short name T82
Test name
Test status
Simulation time 18381155 ps
CPU time 0.6 seconds
Started Aug 07 07:14:22 PM PDT 24
Finished Aug 07 07:14:22 PM PDT 24
Peak memory 182960 kb
Host smart-d4378249-a041-4d56-8436-56c6167fbfa2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25106218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.25106218
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3056428341
Short name T509
Test name
Test status
Simulation time 11406443 ps
CPU time 0.55 seconds
Started Aug 07 07:14:23 PM PDT 24
Finished Aug 07 07:14:24 PM PDT 24
Peak memory 182748 kb
Host smart-9a51ac3f-ea9e-4478-aa66-47ce46e5d010
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056428341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.3056428341
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1435656209
Short name T527
Test name
Test status
Simulation time 61579201 ps
CPU time 0.78 seconds
Started Aug 07 07:14:26 PM PDT 24
Finished Aug 07 07:14:27 PM PDT 24
Peak memory 193624 kb
Host smart-40411884-4ab1-43e2-bad4-ada2d7840017
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435656209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.1435656209
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.1340670250
Short name T567
Test name
Test status
Simulation time 195988758 ps
CPU time 2.45 seconds
Started Aug 07 07:14:23 PM PDT 24
Finished Aug 07 07:14:25 PM PDT 24
Peak memory 197664 kb
Host smart-60732cf3-680e-45a4-8706-72ee0b2ba8a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340670250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.1340670250
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.3948340414
Short name T515
Test name
Test status
Simulation time 99341740 ps
CPU time 1.32 seconds
Started Aug 07 07:14:23 PM PDT 24
Finished Aug 07 07:14:25 PM PDT 24
Peak memory 195392 kb
Host smart-7c9f34d0-9de5-4619-8513-f28528038641
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948340414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.3948340414
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.4125503888
Short name T504
Test name
Test status
Simulation time 113802494 ps
CPU time 1.18 seconds
Started Aug 07 07:14:35 PM PDT 24
Finished Aug 07 07:14:37 PM PDT 24
Peak memory 197740 kb
Host smart-dd96dcc2-8083-44c8-b714-ce1bb567cc86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125503888 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.4125503888
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.4272336822
Short name T467
Test name
Test status
Simulation time 22911369 ps
CPU time 0.56 seconds
Started Aug 07 07:14:35 PM PDT 24
Finished Aug 07 07:14:36 PM PDT 24
Peak memory 182892 kb
Host smart-61a43786-42e3-4139-8b8f-a030a5f20881
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272336822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.4272336822
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.2476152212
Short name T578
Test name
Test status
Simulation time 20805348 ps
CPU time 0.54 seconds
Started Aug 07 07:14:34 PM PDT 24
Finished Aug 07 07:14:35 PM PDT 24
Peak memory 182744 kb
Host smart-a3a5850e-1cfa-49a4-b3c8-2c6dc0114f10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476152212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.2476152212
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.3395577638
Short name T95
Test name
Test status
Simulation time 23740526 ps
CPU time 0.76 seconds
Started Aug 07 07:14:34 PM PDT 24
Finished Aug 07 07:14:35 PM PDT 24
Peak memory 193484 kb
Host smart-3546cf22-c326-45e6-9fa4-0acfa5bb19a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395577638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.3395577638
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.1171419351
Short name T473
Test name
Test status
Simulation time 159455198 ps
CPU time 2.08 seconds
Started Aug 07 07:14:26 PM PDT 24
Finished Aug 07 07:14:28 PM PDT 24
Peak memory 197684 kb
Host smart-d83a49dc-3ef1-4a98-b45e-0ddc597db91b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171419351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.1171419351
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.1791464077
Short name T100
Test name
Test status
Simulation time 1358654576 ps
CPU time 1.34 seconds
Started Aug 07 07:14:24 PM PDT 24
Finished Aug 07 07:14:25 PM PDT 24
Peak memory 195708 kb
Host smart-51ccd6e0-7a82-436b-8aaf-a507c23404d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791464077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.1791464077
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.719642634
Short name T558
Test name
Test status
Simulation time 25855169 ps
CPU time 0.74 seconds
Started Aug 07 07:14:34 PM PDT 24
Finished Aug 07 07:14:35 PM PDT 24
Peak memory 195648 kb
Host smart-66891aa2-d3f4-4523-8b05-182d9be9f757
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719642634 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.719642634
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.2431797158
Short name T544
Test name
Test status
Simulation time 39071233 ps
CPU time 0.54 seconds
Started Aug 07 07:14:35 PM PDT 24
Finished Aug 07 07:14:35 PM PDT 24
Peak memory 182944 kb
Host smart-650fa3b7-1240-4f78-8a4e-dad29e3519be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431797158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.2431797158
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.3467394418
Short name T520
Test name
Test status
Simulation time 68846002 ps
CPU time 0.52 seconds
Started Aug 07 07:14:34 PM PDT 24
Finished Aug 07 07:14:34 PM PDT 24
Peak memory 182224 kb
Host smart-c1f22eb1-627f-4e5d-8167-88168e5b1c69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467394418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.3467394418
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.1186242678
Short name T35
Test name
Test status
Simulation time 154218546 ps
CPU time 0.78 seconds
Started Aug 07 07:14:34 PM PDT 24
Finished Aug 07 07:14:35 PM PDT 24
Peak memory 192056 kb
Host smart-0d932971-14f8-4658-9555-2cbf35af566e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186242678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.1186242678
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.4055284274
Short name T456
Test name
Test status
Simulation time 27572558 ps
CPU time 1.33 seconds
Started Aug 07 07:14:34 PM PDT 24
Finished Aug 07 07:14:35 PM PDT 24
Peak memory 197660 kb
Host smart-7e67fd69-8f87-4a81-a191-0f93cfef6eb7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055284274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.4055284274
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1734519671
Short name T98
Test name
Test status
Simulation time 236683164 ps
CPU time 0.83 seconds
Started Aug 07 07:14:35 PM PDT 24
Finished Aug 07 07:14:36 PM PDT 24
Peak memory 193940 kb
Host smart-a2f5e808-02ce-435b-8c48-12eb22e0a220
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734519671 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.1734519671
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.1149432454
Short name T516
Test name
Test status
Simulation time 49252203 ps
CPU time 1.12 seconds
Started Aug 07 07:14:34 PM PDT 24
Finished Aug 07 07:14:35 PM PDT 24
Peak memory 197708 kb
Host smart-c8e0800f-f98c-4c21-a0e7-474266bc586b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149432454 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.1149432454
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.3398349316
Short name T494
Test name
Test status
Simulation time 21391829 ps
CPU time 0.55 seconds
Started Aug 07 07:14:35 PM PDT 24
Finished Aug 07 07:14:36 PM PDT 24
Peak memory 182892 kb
Host smart-023263a1-9b05-4819-9178-f2f4b5d6d895
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398349316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.3398349316
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.1054191509
Short name T522
Test name
Test status
Simulation time 10649453 ps
CPU time 0.52 seconds
Started Aug 07 07:14:35 PM PDT 24
Finished Aug 07 07:14:36 PM PDT 24
Peak memory 182212 kb
Host smart-9d95d005-e633-4f4a-b351-222def8a7e90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054191509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.1054191509
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.3249906477
Short name T547
Test name
Test status
Simulation time 124493599 ps
CPU time 0.6 seconds
Started Aug 07 07:14:35 PM PDT 24
Finished Aug 07 07:14:35 PM PDT 24
Peak memory 192180 kb
Host smart-c13e788f-e2e6-4ce4-b7fa-1a9dc9cc4d61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249906477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.3249906477
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.1222966281
Short name T458
Test name
Test status
Simulation time 342883722 ps
CPU time 1.97 seconds
Started Aug 07 07:14:34 PM PDT 24
Finished Aug 07 07:14:36 PM PDT 24
Peak memory 197680 kb
Host smart-91cd8f36-3f7c-4452-8385-0ffb8e195215
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222966281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.1222966281
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.1259477919
Short name T55
Test name
Test status
Simulation time 89195914 ps
CPU time 1.12 seconds
Started Aug 07 07:14:35 PM PDT 24
Finished Aug 07 07:14:36 PM PDT 24
Peak memory 195344 kb
Host smart-3844235f-9613-4e0c-8867-459a5bf00b6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259477919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.1259477919
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.2974027285
Short name T478
Test name
Test status
Simulation time 23764372 ps
CPU time 1.02 seconds
Started Aug 07 07:14:34 PM PDT 24
Finished Aug 07 07:14:35 PM PDT 24
Peak memory 197544 kb
Host smart-e2d98351-41ed-4018-88a6-c769af2aca9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974027285 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.2974027285
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.1038231847
Short name T77
Test name
Test status
Simulation time 54195649 ps
CPU time 0.58 seconds
Started Aug 07 07:14:33 PM PDT 24
Finished Aug 07 07:14:34 PM PDT 24
Peak memory 182972 kb
Host smart-7e6a0aa3-6ad0-4a41-aa4c-3b6bc50c9100
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038231847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.1038231847
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.182458196
Short name T577
Test name
Test status
Simulation time 20504772 ps
CPU time 0.57 seconds
Started Aug 07 07:14:36 PM PDT 24
Finished Aug 07 07:14:36 PM PDT 24
Peak memory 182752 kb
Host smart-30f0c153-64c3-443c-abf1-5f9f979e5db3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182458196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.182458196
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.199993479
Short name T580
Test name
Test status
Simulation time 37845438 ps
CPU time 0.78 seconds
Started Aug 07 07:14:33 PM PDT 24
Finished Aug 07 07:14:34 PM PDT 24
Peak memory 193772 kb
Host smart-90188421-5e54-4e44-ae1e-78d7543a6c91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199993479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_ti
mer_same_csr_outstanding.199993479
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.4153840797
Short name T501
Test name
Test status
Simulation time 35850500 ps
CPU time 1.17 seconds
Started Aug 07 07:14:33 PM PDT 24
Finished Aug 07 07:14:35 PM PDT 24
Peak memory 197476 kb
Host smart-66c84b1a-1f9c-4635-8a28-d164db097736
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153840797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.4153840797
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.1600911762
Short name T472
Test name
Test status
Simulation time 851073475 ps
CPU time 1.08 seconds
Started Aug 07 07:14:32 PM PDT 24
Finished Aug 07 07:14:34 PM PDT 24
Peak memory 195444 kb
Host smart-d4cfa64f-0d8b-44db-bc2f-d3f4730d5f61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600911762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.1600911762
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.796989046
Short name T523
Test name
Test status
Simulation time 25054421 ps
CPU time 0.82 seconds
Started Aug 07 07:14:44 PM PDT 24
Finished Aug 07 07:14:45 PM PDT 24
Peak memory 196928 kb
Host smart-b8883bb8-8c98-4758-833d-ac6a20a7130f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796989046 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.796989046
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.3290360765
Short name T543
Test name
Test status
Simulation time 39123993 ps
CPU time 0.56 seconds
Started Aug 07 07:14:34 PM PDT 24
Finished Aug 07 07:14:35 PM PDT 24
Peak memory 182976 kb
Host smart-e948ce5e-9f57-4cdd-8c83-713d3613b8ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290360765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.3290360765
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.216765515
Short name T464
Test name
Test status
Simulation time 14358130 ps
CPU time 0.53 seconds
Started Aug 07 07:14:34 PM PDT 24
Finished Aug 07 07:14:35 PM PDT 24
Peak memory 182240 kb
Host smart-9c584783-c8d7-42c8-8180-a7a94bcb0f6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216765515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.216765515
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.2553687498
Short name T576
Test name
Test status
Simulation time 132057919 ps
CPU time 0.8 seconds
Started Aug 07 07:14:47 PM PDT 24
Finished Aug 07 07:14:48 PM PDT 24
Peak memory 191924 kb
Host smart-b2c258fb-0b50-4f20-a23d-4bf7640039b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553687498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.2553687498
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.2221774273
Short name T487
Test name
Test status
Simulation time 54320058 ps
CPU time 2.49 seconds
Started Aug 07 07:14:34 PM PDT 24
Finished Aug 07 07:14:37 PM PDT 24
Peak memory 197716 kb
Host smart-cd034d80-a2d4-4010-98fa-6d79a1caff51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221774273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.2221774273
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.3200648744
Short name T552
Test name
Test status
Simulation time 92107900 ps
CPU time 0.81 seconds
Started Aug 07 07:14:34 PM PDT 24
Finished Aug 07 07:14:34 PM PDT 24
Peak memory 193388 kb
Host smart-27bf2880-88a0-41d7-ab58-eba3b9e671d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200648744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.3200648744
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.2622237777
Short name T531
Test name
Test status
Simulation time 155823516 ps
CPU time 0.89 seconds
Started Aug 07 07:14:43 PM PDT 24
Finished Aug 07 07:14:44 PM PDT 24
Peak memory 197468 kb
Host smart-061821da-064b-41fe-81d5-046a72b5d1ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622237777 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.2622237777
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.2597351299
Short name T551
Test name
Test status
Simulation time 19619609 ps
CPU time 0.55 seconds
Started Aug 07 07:14:47 PM PDT 24
Finished Aug 07 07:14:48 PM PDT 24
Peak memory 182948 kb
Host smart-24bb2efb-0313-4cd1-95e5-fb466c58a726
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597351299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.2597351299
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.2607906795
Short name T519
Test name
Test status
Simulation time 19152535 ps
CPU time 0.62 seconds
Started Aug 07 07:14:47 PM PDT 24
Finished Aug 07 07:14:47 PM PDT 24
Peak memory 182788 kb
Host smart-18b7085e-35ea-42fa-aea6-83b5835ef3db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607906795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.2607906795
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.3272260119
Short name T73
Test name
Test status
Simulation time 39344059 ps
CPU time 0.61 seconds
Started Aug 07 07:14:45 PM PDT 24
Finished Aug 07 07:14:46 PM PDT 24
Peak memory 192384 kb
Host smart-1ec1f13e-90ee-4088-a4cf-2fc4d93cd2d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272260119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.3272260119
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.1183877854
Short name T457
Test name
Test status
Simulation time 182279690 ps
CPU time 1.89 seconds
Started Aug 07 07:14:44 PM PDT 24
Finished Aug 07 07:14:46 PM PDT 24
Peak memory 197668 kb
Host smart-635282f9-209d-47a2-927e-b22881c8d4c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183877854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.1183877854
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.4163462634
Short name T534
Test name
Test status
Simulation time 80822554 ps
CPU time 1.08 seconds
Started Aug 07 07:14:44 PM PDT 24
Finished Aug 07 07:14:46 PM PDT 24
Peak memory 183456 kb
Host smart-9e85a1a4-22d3-47e4-92b6-38fbcd341ee5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163462634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.4163462634
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.4252664961
Short name T496
Test name
Test status
Simulation time 29676125 ps
CPU time 0.73 seconds
Started Aug 07 07:13:55 PM PDT 24
Finished Aug 07 07:13:55 PM PDT 24
Peak memory 192712 kb
Host smart-98835e40-1dfe-4b33-9938-d44ab72efa00
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252664961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.4252664961
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.3630747728
Short name T508
Test name
Test status
Simulation time 230334424 ps
CPU time 1.38 seconds
Started Aug 07 07:13:57 PM PDT 24
Finished Aug 07 07:13:59 PM PDT 24
Peak memory 192364 kb
Host smart-68cfb491-789b-40f3-abe1-7f4e007b5d48
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630747728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.3630747728
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.2714383776
Short name T81
Test name
Test status
Simulation time 57915586 ps
CPU time 0.59 seconds
Started Aug 07 07:13:57 PM PDT 24
Finished Aug 07 07:13:58 PM PDT 24
Peak memory 182952 kb
Host smart-b9851597-b33c-4a9a-a1eb-f30740b79a5a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714383776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.2714383776
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3866914456
Short name T483
Test name
Test status
Simulation time 83370445 ps
CPU time 1.11 seconds
Started Aug 07 07:14:04 PM PDT 24
Finished Aug 07 07:14:05 PM PDT 24
Peak memory 197772 kb
Host smart-03524bba-0fe9-4ed4-8f01-8f9a4dbacb64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866914456 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.3866914456
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.2127045764
Short name T79
Test name
Test status
Simulation time 30239205 ps
CPU time 0.55 seconds
Started Aug 07 07:13:54 PM PDT 24
Finished Aug 07 07:13:55 PM PDT 24
Peak memory 182984 kb
Host smart-6e404981-bcee-43ff-9110-7dd29821bb02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127045764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.2127045764
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.894889341
Short name T513
Test name
Test status
Simulation time 53520391 ps
CPU time 0.55 seconds
Started Aug 07 07:13:55 PM PDT 24
Finished Aug 07 07:13:55 PM PDT 24
Peak memory 182764 kb
Host smart-bc4dfad0-05d3-4c66-8416-0af989b71757
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894889341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.894889341
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.3306638109
Short name T514
Test name
Test status
Simulation time 152149504 ps
CPU time 0.8 seconds
Started Aug 07 07:14:06 PM PDT 24
Finished Aug 07 07:14:07 PM PDT 24
Peak memory 193668 kb
Host smart-0883cd80-7e85-41a0-98c9-f7622f320b4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306638109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.3306638109
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.1704709680
Short name T529
Test name
Test status
Simulation time 75330224 ps
CPU time 0.91 seconds
Started Aug 07 07:13:56 PM PDT 24
Finished Aug 07 07:13:57 PM PDT 24
Peak memory 195956 kb
Host smart-20e26b14-cc15-4794-a4e6-69129da01c2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704709680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.1704709680
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.676410262
Short name T518
Test name
Test status
Simulation time 93143071 ps
CPU time 0.84 seconds
Started Aug 07 07:13:55 PM PDT 24
Finished Aug 07 07:13:56 PM PDT 24
Peak memory 193928 kb
Host smart-33dc20e7-4980-4e37-8330-694ec666631f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676410262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_int
g_err.676410262
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.1993688243
Short name T468
Test name
Test status
Simulation time 59936593 ps
CPU time 0.51 seconds
Started Aug 07 07:14:45 PM PDT 24
Finished Aug 07 07:14:46 PM PDT 24
Peak memory 182432 kb
Host smart-0349b2b4-0079-4f69-9f61-c60ce7229ba2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993688243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.1993688243
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.230764895
Short name T497
Test name
Test status
Simulation time 40111835 ps
CPU time 0.52 seconds
Started Aug 07 07:14:46 PM PDT 24
Finished Aug 07 07:14:46 PM PDT 24
Peak memory 182232 kb
Host smart-56a87408-f232-45ac-a385-551e2780d7b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230764895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.230764895
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.3552553730
Short name T530
Test name
Test status
Simulation time 45964026 ps
CPU time 0.54 seconds
Started Aug 07 07:14:43 PM PDT 24
Finished Aug 07 07:14:44 PM PDT 24
Peak memory 182412 kb
Host smart-f66e9c48-01ee-4670-8a91-d933d3ec81e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552553730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.3552553730
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.3471493932
Short name T465
Test name
Test status
Simulation time 36221629 ps
CPU time 0.54 seconds
Started Aug 07 07:14:43 PM PDT 24
Finished Aug 07 07:14:44 PM PDT 24
Peak memory 182472 kb
Host smart-18ecc6dc-91c2-4126-a469-b76697a0fc0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471493932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.3471493932
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2793053542
Short name T554
Test name
Test status
Simulation time 23688363 ps
CPU time 0.55 seconds
Started Aug 07 07:14:45 PM PDT 24
Finished Aug 07 07:14:46 PM PDT 24
Peak memory 182248 kb
Host smart-fca22f81-09d1-440b-bc41-3ec87d0051ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793053542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.2793053542
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.1072083116
Short name T573
Test name
Test status
Simulation time 13618130 ps
CPU time 0.55 seconds
Started Aug 07 07:14:46 PM PDT 24
Finished Aug 07 07:14:46 PM PDT 24
Peak memory 182748 kb
Host smart-2758c773-eec3-4b40-a6d6-d86883fad563
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072083116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.1072083116
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.3584366822
Short name T500
Test name
Test status
Simulation time 38127362 ps
CPU time 0.53 seconds
Started Aug 07 07:14:47 PM PDT 24
Finished Aug 07 07:14:47 PM PDT 24
Peak memory 182740 kb
Host smart-fc6a328c-065f-4521-be0f-d5bb9da4933b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584366822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.3584366822
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.2408539399
Short name T564
Test name
Test status
Simulation time 12676057 ps
CPU time 0.55 seconds
Started Aug 07 07:14:45 PM PDT 24
Finished Aug 07 07:14:45 PM PDT 24
Peak memory 182700 kb
Host smart-9f61de7d-bbe1-41f7-869a-4465cccfef62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408539399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.2408539399
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.984375326
Short name T499
Test name
Test status
Simulation time 27130198 ps
CPU time 0.56 seconds
Started Aug 07 07:14:43 PM PDT 24
Finished Aug 07 07:14:44 PM PDT 24
Peak memory 182740 kb
Host smart-05871215-600c-4542-a465-143383849fe1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984375326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.984375326
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.3481048236
Short name T491
Test name
Test status
Simulation time 54187034 ps
CPU time 0.57 seconds
Started Aug 07 07:14:48 PM PDT 24
Finished Aug 07 07:14:48 PM PDT 24
Peak memory 182760 kb
Host smart-23c4b802-2d91-4e40-b47d-14804756c04b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481048236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.3481048236
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3607586444
Short name T476
Test name
Test status
Simulation time 77125117 ps
CPU time 0.65 seconds
Started Aug 07 07:14:05 PM PDT 24
Finished Aug 07 07:14:06 PM PDT 24
Peak memory 182884 kb
Host smart-6661efe7-c54c-47aa-a28f-eb820b0bdd4d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607586444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.3607586444
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.152597760
Short name T533
Test name
Test status
Simulation time 175973505 ps
CPU time 3.13 seconds
Started Aug 07 07:14:05 PM PDT 24
Finished Aug 07 07:14:08 PM PDT 24
Peak memory 194180 kb
Host smart-ae649b05-f862-4439-8f2e-5c9c6e253988
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152597760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_b
ash.152597760
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3124803633
Short name T74
Test name
Test status
Simulation time 41873026 ps
CPU time 0.55 seconds
Started Aug 07 07:14:06 PM PDT 24
Finished Aug 07 07:14:06 PM PDT 24
Peak memory 182944 kb
Host smart-c8b08762-547c-478d-8af4-87f29e880f4a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124803633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.3124803633
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.2816431405
Short name T572
Test name
Test status
Simulation time 31020279 ps
CPU time 0.82 seconds
Started Aug 07 07:14:06 PM PDT 24
Finished Aug 07 07:14:07 PM PDT 24
Peak memory 195240 kb
Host smart-1ea6e85a-22d7-48d3-9669-151f9c524008
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816431405 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.2816431405
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.2013951310
Short name T479
Test name
Test status
Simulation time 31130502 ps
CPU time 0.55 seconds
Started Aug 07 07:14:04 PM PDT 24
Finished Aug 07 07:14:04 PM PDT 24
Peak memory 182812 kb
Host smart-0f36752e-68b7-4f13-9562-21acf05cf6f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013951310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.2013951310
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.1141612339
Short name T517
Test name
Test status
Simulation time 29970388 ps
CPU time 0.53 seconds
Started Aug 07 07:14:04 PM PDT 24
Finished Aug 07 07:14:05 PM PDT 24
Peak memory 182676 kb
Host smart-52de5dc5-7090-4bb8-8c0c-e6d9fa063eaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141612339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.1141612339
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.731108064
Short name T503
Test name
Test status
Simulation time 59388181 ps
CPU time 0.75 seconds
Started Aug 07 07:14:06 PM PDT 24
Finished Aug 07 07:14:07 PM PDT 24
Peak memory 193596 kb
Host smart-5c29ecf6-bd59-449f-810d-d689c5e01a5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731108064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_tim
er_same_csr_outstanding.731108064
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.1533902217
Short name T475
Test name
Test status
Simulation time 72637987 ps
CPU time 1.11 seconds
Started Aug 07 07:14:05 PM PDT 24
Finished Aug 07 07:14:06 PM PDT 24
Peak memory 197584 kb
Host smart-3489d914-55a3-459d-8f9d-1085941de7f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533902217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.1533902217
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.2205640452
Short name T486
Test name
Test status
Simulation time 43791571 ps
CPU time 0.85 seconds
Started Aug 07 07:14:05 PM PDT 24
Finished Aug 07 07:14:06 PM PDT 24
Peak memory 194092 kb
Host smart-9e20097a-3006-420f-846d-67ba57e67181
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205640452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.2205640452
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.1391464469
Short name T455
Test name
Test status
Simulation time 13522941 ps
CPU time 0.57 seconds
Started Aug 07 07:14:43 PM PDT 24
Finished Aug 07 07:14:44 PM PDT 24
Peak memory 182716 kb
Host smart-79807a9d-7c92-49ea-a9c1-17c9451366d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391464469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.1391464469
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.400841188
Short name T488
Test name
Test status
Simulation time 87791988 ps
CPU time 0.55 seconds
Started Aug 07 07:14:46 PM PDT 24
Finished Aug 07 07:14:47 PM PDT 24
Peak memory 182732 kb
Host smart-3e4fe216-4a9d-473a-b119-b44e9f96e171
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400841188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.400841188
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.74478101
Short name T461
Test name
Test status
Simulation time 12212230 ps
CPU time 0.57 seconds
Started Aug 07 07:14:44 PM PDT 24
Finished Aug 07 07:14:45 PM PDT 24
Peak memory 182780 kb
Host smart-aa67c374-74ac-4106-8ace-ffc3a9499358
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74478101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.74478101
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.4190671409
Short name T489
Test name
Test status
Simulation time 69810910 ps
CPU time 0.54 seconds
Started Aug 07 07:14:44 PM PDT 24
Finished Aug 07 07:14:45 PM PDT 24
Peak memory 182756 kb
Host smart-bac9715d-32ce-4024-bc44-c91186875348
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190671409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.4190671409
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.3594583796
Short name T546
Test name
Test status
Simulation time 15804187 ps
CPU time 0.54 seconds
Started Aug 07 07:14:46 PM PDT 24
Finished Aug 07 07:14:47 PM PDT 24
Peak memory 182732 kb
Host smart-ea76d894-0aca-402a-86f6-86e1834e081a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594583796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.3594583796
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.1712789696
Short name T574
Test name
Test status
Simulation time 41109260 ps
CPU time 0.53 seconds
Started Aug 07 07:14:44 PM PDT 24
Finished Aug 07 07:14:45 PM PDT 24
Peak memory 182728 kb
Host smart-ded19c99-ebf5-4c68-9d9d-a1b511934308
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712789696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.1712789696
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.244611602
Short name T448
Test name
Test status
Simulation time 15405080 ps
CPU time 0.53 seconds
Started Aug 07 07:14:44 PM PDT 24
Finished Aug 07 07:14:45 PM PDT 24
Peak memory 182236 kb
Host smart-9d4e5727-21cd-42eb-aa8a-ac98e5e2ea22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244611602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.244611602
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.1373146914
Short name T553
Test name
Test status
Simulation time 17742633 ps
CPU time 0.57 seconds
Started Aug 07 07:14:43 PM PDT 24
Finished Aug 07 07:14:43 PM PDT 24
Peak memory 182804 kb
Host smart-1ba3111c-9665-4f39-a606-63218da7b1a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373146914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.1373146914
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.1761563295
Short name T471
Test name
Test status
Simulation time 135337388 ps
CPU time 0.56 seconds
Started Aug 07 07:14:47 PM PDT 24
Finished Aug 07 07:14:48 PM PDT 24
Peak memory 182724 kb
Host smart-3b2fba9e-b729-4594-97c5-548b6a27d6dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761563295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.1761563295
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.4140096739
Short name T446
Test name
Test status
Simulation time 30052093 ps
CPU time 0.54 seconds
Started Aug 07 07:14:43 PM PDT 24
Finished Aug 07 07:14:44 PM PDT 24
Peak memory 182416 kb
Host smart-1b93ee62-9d17-4c87-81d9-01e2275f6114
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140096739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.4140096739
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.807542875
Short name T75
Test name
Test status
Simulation time 20670903 ps
CPU time 0.59 seconds
Started Aug 07 07:14:04 PM PDT 24
Finished Aug 07 07:14:05 PM PDT 24
Peak memory 182872 kb
Host smart-d0f437f8-0413-4634-8748-d64dc191ef48
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807542875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alias
ing.807542875
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.2589183830
Short name T532
Test name
Test status
Simulation time 194424262 ps
CPU time 1.52 seconds
Started Aug 07 07:14:06 PM PDT 24
Finished Aug 07 07:14:08 PM PDT 24
Peak memory 191316 kb
Host smart-9eff22da-84d7-4fc1-8237-e6ebd68dfa22
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589183830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.2589183830
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.263190762
Short name T556
Test name
Test status
Simulation time 42510830 ps
CPU time 0.53 seconds
Started Aug 07 07:14:05 PM PDT 24
Finished Aug 07 07:14:06 PM PDT 24
Peak memory 182380 kb
Host smart-7a6acc67-1c33-4f9e-a6bd-8d6fa15a29ef
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263190762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_re
set.263190762
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.2206070744
Short name T454
Test name
Test status
Simulation time 24770851 ps
CPU time 0.75 seconds
Started Aug 07 07:14:04 PM PDT 24
Finished Aug 07 07:14:04 PM PDT 24
Peak memory 195676 kb
Host smart-6d1d3714-268f-49fa-9a3c-2152d0d752bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206070744 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.2206070744
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.315895094
Short name T80
Test name
Test status
Simulation time 39737663 ps
CPU time 0.58 seconds
Started Aug 07 07:14:06 PM PDT 24
Finished Aug 07 07:14:07 PM PDT 24
Peak memory 182956 kb
Host smart-0175994e-6beb-4858-ba0e-052d4a943004
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315895094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.315895094
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.1060837395
Short name T562
Test name
Test status
Simulation time 41964726 ps
CPU time 0.54 seconds
Started Aug 07 07:14:05 PM PDT 24
Finished Aug 07 07:14:05 PM PDT 24
Peak memory 182244 kb
Host smart-13beeb5a-8e10-4195-8759-c6a40ee32ac3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060837395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.1060837395
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.565422231
Short name T510
Test name
Test status
Simulation time 14246752 ps
CPU time 0.66 seconds
Started Aug 07 07:14:05 PM PDT 24
Finished Aug 07 07:14:06 PM PDT 24
Peak memory 192308 kb
Host smart-411d68e6-6736-4481-b62d-4118dad665f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565422231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_tim
er_same_csr_outstanding.565422231
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1894989523
Short name T521
Test name
Test status
Simulation time 56656071 ps
CPU time 1.29 seconds
Started Aug 07 07:14:04 PM PDT 24
Finished Aug 07 07:14:06 PM PDT 24
Peak memory 197640 kb
Host smart-75df7af7-1de3-45cc-b64f-a1a8aaac99e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894989523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.1894989523
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2393641022
Short name T549
Test name
Test status
Simulation time 205347255 ps
CPU time 0.86 seconds
Started Aug 07 07:14:05 PM PDT 24
Finished Aug 07 07:14:06 PM PDT 24
Peak memory 193992 kb
Host smart-76a19c5d-8294-4289-9ebd-dbab2ec00432
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393641022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.2393641022
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.1310998435
Short name T492
Test name
Test status
Simulation time 25139353 ps
CPU time 0.55 seconds
Started Aug 07 07:14:46 PM PDT 24
Finished Aug 07 07:14:47 PM PDT 24
Peak memory 182812 kb
Host smart-7ee96a6a-b4db-42bb-815a-74fe0444bc4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310998435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.1310998435
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.3734859884
Short name T571
Test name
Test status
Simulation time 45337850 ps
CPU time 0.57 seconds
Started Aug 07 07:14:45 PM PDT 24
Finished Aug 07 07:14:45 PM PDT 24
Peak memory 182764 kb
Host smart-0c066f58-397e-4204-bc12-f4037070fdc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734859884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.3734859884
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.3438403397
Short name T447
Test name
Test status
Simulation time 56909578 ps
CPU time 0.58 seconds
Started Aug 07 07:14:44 PM PDT 24
Finished Aug 07 07:14:45 PM PDT 24
Peak memory 182776 kb
Host smart-654e489d-2f8a-4019-a066-3604ceed9ed3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438403397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.3438403397
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.709483523
Short name T559
Test name
Test status
Simulation time 41746455 ps
CPU time 0.53 seconds
Started Aug 07 07:14:50 PM PDT 24
Finished Aug 07 07:14:51 PM PDT 24
Peak memory 182764 kb
Host smart-df61c40b-832e-47c2-a727-4d6d07fa7c13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709483523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.709483523
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.981755221
Short name T575
Test name
Test status
Simulation time 40452929 ps
CPU time 0.55 seconds
Started Aug 07 07:14:42 PM PDT 24
Finished Aug 07 07:14:43 PM PDT 24
Peak memory 182208 kb
Host smart-b2577eb5-6e8a-4e7c-9426-f413e583e35a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981755221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.981755221
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.4189908944
Short name T528
Test name
Test status
Simulation time 13869020 ps
CPU time 0.55 seconds
Started Aug 07 07:14:45 PM PDT 24
Finished Aug 07 07:14:46 PM PDT 24
Peak memory 182284 kb
Host smart-01f464dd-da18-42c8-b3ef-448a12dd0f1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189908944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.4189908944
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.4212356926
Short name T561
Test name
Test status
Simulation time 37480405 ps
CPU time 0.58 seconds
Started Aug 07 07:14:48 PM PDT 24
Finished Aug 07 07:14:49 PM PDT 24
Peak memory 182792 kb
Host smart-b83437ef-9dca-4748-a696-8133b2e5c2c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212356926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.4212356926
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2103521506
Short name T548
Test name
Test status
Simulation time 13781489 ps
CPU time 0.54 seconds
Started Aug 07 07:14:47 PM PDT 24
Finished Aug 07 07:14:48 PM PDT 24
Peak memory 182284 kb
Host smart-7a66693d-4879-4815-9c78-6917d700513d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103521506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.2103521506
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.1857294544
Short name T462
Test name
Test status
Simulation time 44605696 ps
CPU time 0.57 seconds
Started Aug 07 07:14:44 PM PDT 24
Finished Aug 07 07:14:45 PM PDT 24
Peak memory 182724 kb
Host smart-7e7c4834-300b-4297-8c93-b40217323295
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857294544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.1857294544
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.1585979155
Short name T525
Test name
Test status
Simulation time 54681091 ps
CPU time 0.58 seconds
Started Aug 07 07:14:45 PM PDT 24
Finished Aug 07 07:14:46 PM PDT 24
Peak memory 182804 kb
Host smart-8b5b7a77-aba7-4060-8e4a-3a79ac5391cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585979155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.1585979155
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2866880687
Short name T507
Test name
Test status
Simulation time 77079357 ps
CPU time 0.85 seconds
Started Aug 07 07:14:17 PM PDT 24
Finished Aug 07 07:14:18 PM PDT 24
Peak memory 196200 kb
Host smart-3c6e8a14-ff8b-4ac3-80b4-8731c2efdd3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866880687 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.2866880687
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.969303820
Short name T76
Test name
Test status
Simulation time 26067248 ps
CPU time 0.58 seconds
Started Aug 07 07:14:13 PM PDT 24
Finished Aug 07 07:14:14 PM PDT 24
Peak memory 182880 kb
Host smart-e73278c4-8bd1-41a1-8a65-f3c63aea08c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969303820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.969303820
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.2330162908
Short name T450
Test name
Test status
Simulation time 30926324 ps
CPU time 0.54 seconds
Started Aug 07 07:14:16 PM PDT 24
Finished Aug 07 07:14:16 PM PDT 24
Peak memory 182216 kb
Host smart-86839a9c-0b71-4c1a-87d7-412b70604006
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330162908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.2330162908
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1128100629
Short name T569
Test name
Test status
Simulation time 31907916 ps
CPU time 0.74 seconds
Started Aug 07 07:14:12 PM PDT 24
Finished Aug 07 07:14:13 PM PDT 24
Peak memory 191896 kb
Host smart-414a7713-3773-4bbd-a13d-8ff9fd40fbc7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128100629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.1128100629
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.3958160217
Short name T524
Test name
Test status
Simulation time 22645791 ps
CPU time 1.19 seconds
Started Aug 07 07:14:07 PM PDT 24
Finished Aug 07 07:14:08 PM PDT 24
Peak memory 197716 kb
Host smart-10f849dc-466d-4824-8756-96219f969110
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958160217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.3958160217
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.2995787934
Short name T557
Test name
Test status
Simulation time 231872769 ps
CPU time 1.38 seconds
Started Aug 07 07:14:06 PM PDT 24
Finished Aug 07 07:14:08 PM PDT 24
Peak memory 195436 kb
Host smart-22c4abf8-f6b2-4ebc-b628-23eab832b474
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995787934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.2995787934
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.2827458554
Short name T550
Test name
Test status
Simulation time 34725841 ps
CPU time 0.86 seconds
Started Aug 07 07:14:17 PM PDT 24
Finished Aug 07 07:14:17 PM PDT 24
Peak memory 196616 kb
Host smart-8d7d74a2-1be3-4faf-8cb1-ebcf7b1ddc30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827458554 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.2827458554
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.994502074
Short name T78
Test name
Test status
Simulation time 13315228 ps
CPU time 0.55 seconds
Started Aug 07 07:14:14 PM PDT 24
Finished Aug 07 07:14:14 PM PDT 24
Peak memory 182892 kb
Host smart-9128c098-1c7a-42e6-89f7-a892a3564fdb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994502074 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.994502074
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.1439785079
Short name T452
Test name
Test status
Simulation time 100485223 ps
CPU time 0.55 seconds
Started Aug 07 07:14:19 PM PDT 24
Finished Aug 07 07:14:19 PM PDT 24
Peak memory 182792 kb
Host smart-bf357bc5-7995-48a2-b2ca-16a3ba1851df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439785079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.1439785079
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.346223807
Short name T93
Test name
Test status
Simulation time 74242387 ps
CPU time 0.77 seconds
Started Aug 07 07:14:15 PM PDT 24
Finished Aug 07 07:14:15 PM PDT 24
Peak memory 193540 kb
Host smart-f49b328e-23ca-4c7c-bce9-552c427a0c7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346223807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_tim
er_same_csr_outstanding.346223807
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.3678059877
Short name T505
Test name
Test status
Simulation time 66792639 ps
CPU time 2.27 seconds
Started Aug 07 07:14:12 PM PDT 24
Finished Aug 07 07:14:15 PM PDT 24
Peak memory 197632 kb
Host smart-dd8c8775-46f0-4f69-862c-4879638b8f49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678059877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.3678059877
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.3940937549
Short name T537
Test name
Test status
Simulation time 37469249 ps
CPU time 0.94 seconds
Started Aug 07 07:14:14 PM PDT 24
Finished Aug 07 07:14:16 PM PDT 24
Peak memory 197432 kb
Host smart-9af0d005-bd97-4db3-88da-16bbb417e4ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940937549 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.3940937549
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.1388727999
Short name T512
Test name
Test status
Simulation time 15855663 ps
CPU time 0.57 seconds
Started Aug 07 07:14:13 PM PDT 24
Finished Aug 07 07:14:13 PM PDT 24
Peak memory 182976 kb
Host smart-4daf4051-4529-4be7-8d39-f57bc995d969
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388727999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.1388727999
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.2424305468
Short name T545
Test name
Test status
Simulation time 11132319 ps
CPU time 0.61 seconds
Started Aug 07 07:14:15 PM PDT 24
Finished Aug 07 07:14:16 PM PDT 24
Peak memory 182776 kb
Host smart-ac7409c2-fba2-4824-8268-e7065778f3d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424305468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.2424305468
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3213852975
Short name T502
Test name
Test status
Simulation time 14199887 ps
CPU time 0.62 seconds
Started Aug 07 07:14:13 PM PDT 24
Finished Aug 07 07:14:14 PM PDT 24
Peak memory 191760 kb
Host smart-a26d7326-9f57-43f2-99dd-80a35751592f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213852975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.3213852975
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.363357350
Short name T469
Test name
Test status
Simulation time 1287589731 ps
CPU time 2.58 seconds
Started Aug 07 07:14:14 PM PDT 24
Finished Aug 07 07:14:17 PM PDT 24
Peak memory 197856 kb
Host smart-0d0c0be1-8d63-494f-a59e-012da77e5e41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363357350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.363357350
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.2264349968
Short name T31
Test name
Test status
Simulation time 101379320 ps
CPU time 0.87 seconds
Started Aug 07 07:14:16 PM PDT 24
Finished Aug 07 07:14:17 PM PDT 24
Peak memory 183416 kb
Host smart-5f777cf7-502d-4f73-a827-9949c951a15c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264349968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.2264349968
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.2079391410
Short name T495
Test name
Test status
Simulation time 76921951 ps
CPU time 0.72 seconds
Started Aug 07 07:14:12 PM PDT 24
Finished Aug 07 07:14:13 PM PDT 24
Peak memory 195368 kb
Host smart-74c92023-0f0b-4290-aa45-6a50f54af2dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079391410 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.2079391410
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.3095760392
Short name T72
Test name
Test status
Simulation time 13432539 ps
CPU time 0.58 seconds
Started Aug 07 07:14:16 PM PDT 24
Finished Aug 07 07:14:17 PM PDT 24
Peak memory 182968 kb
Host smart-d82b697b-787a-4f65-bba1-a7547dfb2744
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095760392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.3095760392
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.3768763440
Short name T538
Test name
Test status
Simulation time 40857363 ps
CPU time 0.54 seconds
Started Aug 07 07:14:17 PM PDT 24
Finished Aug 07 07:14:18 PM PDT 24
Peak memory 182744 kb
Host smart-66656285-d81d-4c2d-846a-7d0563b4998e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768763440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.3768763440
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.4107668951
Short name T563
Test name
Test status
Simulation time 33481822 ps
CPU time 0.74 seconds
Started Aug 07 07:14:13 PM PDT 24
Finished Aug 07 07:14:14 PM PDT 24
Peak memory 191908 kb
Host smart-34b1f84d-e7cd-4778-8df6-1f32bed19c1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107668951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.4107668951
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3839352345
Short name T451
Test name
Test status
Simulation time 61138990 ps
CPU time 0.97 seconds
Started Aug 07 07:14:15 PM PDT 24
Finished Aug 07 07:14:16 PM PDT 24
Peak memory 197316 kb
Host smart-9e92cee8-0e0c-490c-99ea-7e75fe446ab6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839352345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.3839352345
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.2374181307
Short name T52
Test name
Test status
Simulation time 48772310 ps
CPU time 0.85 seconds
Started Aug 07 07:14:16 PM PDT 24
Finished Aug 07 07:14:17 PM PDT 24
Peak memory 193700 kb
Host smart-0fc42db9-46f9-4f8a-b359-749dbdd67d25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374181307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.2374181307
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.1396865552
Short name T53
Test name
Test status
Simulation time 124326985 ps
CPU time 0.89 seconds
Started Aug 07 07:14:16 PM PDT 24
Finished Aug 07 07:14:17 PM PDT 24
Peak memory 197572 kb
Host smart-d855baab-c739-4b67-9a74-af01d5a60c2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396865552 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.1396865552
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.455099648
Short name T560
Test name
Test status
Simulation time 13622324 ps
CPU time 0.55 seconds
Started Aug 07 07:14:16 PM PDT 24
Finished Aug 07 07:14:16 PM PDT 24
Peak memory 182896 kb
Host smart-d77eb508-ae92-48ad-9cf8-28bb7dd0dd4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455099648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.455099648
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.1296595064
Short name T466
Test name
Test status
Simulation time 19414427 ps
CPU time 0.53 seconds
Started Aug 07 07:14:15 PM PDT 24
Finished Aug 07 07:14:16 PM PDT 24
Peak memory 182724 kb
Host smart-850600c1-2837-40fa-8125-129030c31c5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296595064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.1296595064
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1572007717
Short name T33
Test name
Test status
Simulation time 19436517 ps
CPU time 0.62 seconds
Started Aug 07 07:14:18 PM PDT 24
Finished Aug 07 07:14:18 PM PDT 24
Peak memory 192260 kb
Host smart-33cb1a0a-77a2-4beb-9210-1f9d9e776a19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572007717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.1572007717
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.31198718
Short name T536
Test name
Test status
Simulation time 221030852 ps
CPU time 1.41 seconds
Started Aug 07 07:14:16 PM PDT 24
Finished Aug 07 07:14:18 PM PDT 24
Peak memory 197688 kb
Host smart-53d16db7-3218-4d10-bd00-14dd9c54ff74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31198718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.31198718
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3144360363
Short name T568
Test name
Test status
Simulation time 95531506 ps
CPU time 0.83 seconds
Started Aug 07 07:14:15 PM PDT 24
Finished Aug 07 07:14:16 PM PDT 24
Peak memory 194032 kb
Host smart-ac96fe06-de40-426a-8b0c-9ab7d28ce326
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144360363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.3144360363
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.1690307485
Short name T191
Test name
Test status
Simulation time 266798297233 ps
CPU time 451.84 seconds
Started Aug 07 05:36:48 PM PDT 24
Finished Aug 07 05:44:20 PM PDT 24
Peak memory 183412 kb
Host smart-32bdc8f6-69f1-4fd7-b901-da05b5e427dc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690307485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.1690307485
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.2854960162
Short name T412
Test name
Test status
Simulation time 155507179169 ps
CPU time 115.95 seconds
Started Aug 07 05:36:46 PM PDT 24
Finished Aug 07 05:38:42 PM PDT 24
Peak memory 183380 kb
Host smart-afabf446-759d-4834-813d-112dace64093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854960162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.2854960162
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.4293627922
Short name T303
Test name
Test status
Simulation time 70845468512 ps
CPU time 56.82 seconds
Started Aug 07 05:36:43 PM PDT 24
Finished Aug 07 05:37:40 PM PDT 24
Peak memory 183448 kb
Host smart-811e6786-e33e-4060-9924-d3d492ab2e50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293627922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.4293627922
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.2782523936
Short name T378
Test name
Test status
Simulation time 620036474 ps
CPU time 0.89 seconds
Started Aug 07 05:36:47 PM PDT 24
Finished Aug 07 05:36:48 PM PDT 24
Peak memory 183084 kb
Host smart-1cea625e-db42-4df9-8869-6a22aca075ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782523936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.2782523936
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.373929333
Short name T62
Test name
Test status
Simulation time 25859403 ps
CPU time 0.59 seconds
Started Aug 07 05:36:46 PM PDT 24
Finished Aug 07 05:36:46 PM PDT 24
Peak memory 183212 kb
Host smart-633e9dc7-0c1c-434d-bfbe-6e3c11e3a1e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373929333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.373929333
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.4101207645
Short name T399
Test name
Test status
Simulation time 524990871461 ps
CPU time 178.89 seconds
Started Aug 07 05:36:44 PM PDT 24
Finished Aug 07 05:39:43 PM PDT 24
Peak memory 183416 kb
Host smart-baf27db2-35ee-4089-bfc9-0e92ac7af8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101207645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.4101207645
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.601935884
Short name T421
Test name
Test status
Simulation time 651524179402 ps
CPU time 235.15 seconds
Started Aug 07 05:36:45 PM PDT 24
Finished Aug 07 05:40:41 PM PDT 24
Peak memory 191668 kb
Host smart-5e6979b7-928c-45a2-80e7-1ef142ae991e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601935884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.601935884
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.487481638
Short name T323
Test name
Test status
Simulation time 32698569407 ps
CPU time 56.41 seconds
Started Aug 07 05:36:48 PM PDT 24
Finished Aug 07 05:37:45 PM PDT 24
Peak memory 191616 kb
Host smart-29e5ce9c-589f-4ed7-9e3d-fe73d0c144ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487481638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.487481638
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.944107769
Short name T18
Test name
Test status
Simulation time 154936957 ps
CPU time 0.97 seconds
Started Aug 07 05:36:48 PM PDT 24
Finished Aug 07 05:36:49 PM PDT 24
Peak memory 214076 kb
Host smart-62d7502c-cd85-4693-819c-21b318bce337
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944107769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.944107769
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.3021884277
Short name T354
Test name
Test status
Simulation time 2584519797192 ps
CPU time 1087.33 seconds
Started Aug 07 05:36:42 PM PDT 24
Finished Aug 07 05:54:50 PM PDT 24
Peak memory 194988 kb
Host smart-634aec4f-7b86-4a59-8598-d7c7e54ea2cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021884277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
3021884277
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.1971149019
Short name T108
Test name
Test status
Simulation time 25086497985 ps
CPU time 20.03 seconds
Started Aug 07 05:36:54 PM PDT 24
Finished Aug 07 05:37:14 PM PDT 24
Peak memory 183328 kb
Host smart-4688f8a9-8e74-4541-90e3-0172e0d00329
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971149019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.1971149019
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.164151431
Short name T89
Test name
Test status
Simulation time 389421240562 ps
CPU time 178.26 seconds
Started Aug 07 05:36:51 PM PDT 24
Finished Aug 07 05:39:49 PM PDT 24
Peak memory 183456 kb
Host smart-3e6e4f1c-e8a7-4b67-bda8-83d4149888d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164151431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.164151431
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.2649293045
Short name T409
Test name
Test status
Simulation time 60410024 ps
CPU time 0.64 seconds
Started Aug 07 05:36:54 PM PDT 24
Finished Aug 07 05:36:55 PM PDT 24
Peak memory 183156 kb
Host smart-b336e7c1-213d-4bb6-a75c-9705ec1ab722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649293045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.2649293045
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/100.rv_timer_random.3994054430
Short name T138
Test name
Test status
Simulation time 210631596571 ps
CPU time 209.94 seconds
Started Aug 07 05:38:48 PM PDT 24
Finished Aug 07 05:42:18 PM PDT 24
Peak memory 191864 kb
Host smart-3f7aee92-1bc9-4a9d-a280-d3989622ff4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994054430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.3994054430
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.433363589
Short name T214
Test name
Test status
Simulation time 871014608578 ps
CPU time 375.85 seconds
Started Aug 07 05:38:48 PM PDT 24
Finished Aug 07 05:45:04 PM PDT 24
Peak memory 191600 kb
Host smart-b013d6f2-9fb7-4b27-b021-f7e2cf3e5a73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433363589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.433363589
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.3584663587
Short name T403
Test name
Test status
Simulation time 85078543488 ps
CPU time 78.45 seconds
Started Aug 07 05:38:53 PM PDT 24
Finished Aug 07 05:40:11 PM PDT 24
Peak memory 183424 kb
Host smart-f1a58cf6-ec26-4a82-980b-d98c8f8468c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584663587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.3584663587
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.2673605888
Short name T140
Test name
Test status
Simulation time 101155995835 ps
CPU time 165.42 seconds
Started Aug 07 05:38:54 PM PDT 24
Finished Aug 07 05:41:39 PM PDT 24
Peak memory 191596 kb
Host smart-20d5a580-9b59-42b3-ad74-72bbe73dcd6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673605888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.2673605888
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.2657746140
Short name T21
Test name
Test status
Simulation time 168043586361 ps
CPU time 1474.51 seconds
Started Aug 07 05:38:53 PM PDT 24
Finished Aug 07 06:03:28 PM PDT 24
Peak memory 183328 kb
Host smart-d29e6e02-236e-4c87-ad09-44e0753d3784
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657746140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.2657746140
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.3046886414
Short name T324
Test name
Test status
Simulation time 142987418198 ps
CPU time 262.99 seconds
Started Aug 07 05:38:57 PM PDT 24
Finished Aug 07 05:43:20 PM PDT 24
Peak memory 195220 kb
Host smart-428669ce-4c71-4481-a7d7-413675f8cc29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046886414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.3046886414
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.3532958967
Short name T429
Test name
Test status
Simulation time 268712554246 ps
CPU time 126.54 seconds
Started Aug 07 05:38:54 PM PDT 24
Finished Aug 07 05:41:01 PM PDT 24
Peak memory 191668 kb
Host smart-48cb6872-24b5-4d61-98bd-9e5a364152ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532958967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.3532958967
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.180069385
Short name T319
Test name
Test status
Simulation time 599251278424 ps
CPU time 592.62 seconds
Started Aug 07 05:36:55 PM PDT 24
Finished Aug 07 05:46:48 PM PDT 24
Peak memory 183468 kb
Host smart-38bb38b9-55dd-4933-a80c-a6cb3cbf6f60
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180069385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.rv_timer_cfg_update_on_fly.180069385
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.2348348597
Short name T47
Test name
Test status
Simulation time 277867837047 ps
CPU time 204.78 seconds
Started Aug 07 05:36:59 PM PDT 24
Finished Aug 07 05:40:24 PM PDT 24
Peak memory 183344 kb
Host smart-283e1e6a-a90d-4da6-ab82-227108366671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348348597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.2348348597
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.2016023680
Short name T257
Test name
Test status
Simulation time 343258255237 ps
CPU time 537.17 seconds
Started Aug 07 05:37:02 PM PDT 24
Finished Aug 07 05:45:59 PM PDT 24
Peak memory 191520 kb
Host smart-6b2b9031-f035-4d66-8b80-9a243d0f23e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016023680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.2016023680
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.2564774664
Short name T373
Test name
Test status
Simulation time 23015390 ps
CPU time 0.56 seconds
Started Aug 07 05:36:57 PM PDT 24
Finished Aug 07 05:36:58 PM PDT 24
Peak memory 182832 kb
Host smart-e73bb8ba-f2a9-4a27-9a01-389f3b591381
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564774664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.2564774664
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/114.rv_timer_random.333825775
Short name T442
Test name
Test status
Simulation time 127849712545 ps
CPU time 78.52 seconds
Started Aug 07 05:39:00 PM PDT 24
Finished Aug 07 05:40:18 PM PDT 24
Peak memory 183412 kb
Host smart-3419ea8f-9c05-4544-a711-8fc8b55b4aaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333825775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.333825775
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.2823766421
Short name T393
Test name
Test status
Simulation time 100704015694 ps
CPU time 52.33 seconds
Started Aug 07 05:39:05 PM PDT 24
Finished Aug 07 05:39:58 PM PDT 24
Peak memory 183388 kb
Host smart-c71a5e24-d946-4f50-b2a1-9086cff2b290
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823766421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.2823766421
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.77798932
Short name T180
Test name
Test status
Simulation time 3938100981905 ps
CPU time 777.81 seconds
Started Aug 07 05:36:57 PM PDT 24
Finished Aug 07 05:49:55 PM PDT 24
Peak memory 183336 kb
Host smart-2c52803c-f236-4eb4-b9a2-706af28b8086
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77798932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.rv_timer_cfg_update_on_fly.77798932
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.1245728882
Short name T368
Test name
Test status
Simulation time 432668865547 ps
CPU time 159.75 seconds
Started Aug 07 05:37:00 PM PDT 24
Finished Aug 07 05:39:40 PM PDT 24
Peak memory 183344 kb
Host smart-8daa188e-a7e4-4057-b6c0-1e349bb2af49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245728882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.1245728882
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.2060440467
Short name T291
Test name
Test status
Simulation time 348856410565 ps
CPU time 350.47 seconds
Started Aug 07 05:37:04 PM PDT 24
Finished Aug 07 05:42:54 PM PDT 24
Peak memory 191644 kb
Host smart-d805e2ce-c0f6-49cc-9752-4d4202d5fa2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060440467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.2060440467
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.1700161104
Short name T347
Test name
Test status
Simulation time 108817521330 ps
CPU time 58.91 seconds
Started Aug 07 05:36:57 PM PDT 24
Finished Aug 07 05:37:56 PM PDT 24
Peak memory 191648 kb
Host smart-139fac2c-a516-4fe5-949c-fcd643e001e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700161104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.1700161104
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all_with_rand_reset.87286608
Short name T37
Test name
Test status
Simulation time 87445249899 ps
CPU time 326.76 seconds
Started Aug 07 05:37:02 PM PDT 24
Finished Aug 07 05:42:29 PM PDT 24
Peak memory 206312 kb
Host smart-c64f3dcb-319d-4512-ac49-82ac0fe53d02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87286608 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all_with_rand_reset.87286608
Directory /workspace/12.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.rv_timer_random.2025105255
Short name T425
Test name
Test status
Simulation time 15323481392 ps
CPU time 23.03 seconds
Started Aug 07 05:39:05 PM PDT 24
Finished Aug 07 05:39:29 PM PDT 24
Peak memory 191580 kb
Host smart-44eab20c-9e23-4d6d-bf32-b11a99249da8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025105255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.2025105255
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.2562458850
Short name T194
Test name
Test status
Simulation time 164760564840 ps
CPU time 298.31 seconds
Started Aug 07 05:39:06 PM PDT 24
Finished Aug 07 05:44:04 PM PDT 24
Peak memory 191636 kb
Host smart-1c6d3393-0a44-4c79-b1b4-48183ef01580
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562458850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.2562458850
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.2338356363
Short name T326
Test name
Test status
Simulation time 9158503277 ps
CPU time 14.41 seconds
Started Aug 07 05:39:06 PM PDT 24
Finished Aug 07 05:39:21 PM PDT 24
Peak memory 183216 kb
Host smart-dd06a7d2-46db-4a45-8496-eb30d3acf41c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338356363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.2338356363
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.3561532805
Short name T269
Test name
Test status
Simulation time 125708969353 ps
CPU time 632.62 seconds
Started Aug 07 05:39:13 PM PDT 24
Finished Aug 07 05:49:46 PM PDT 24
Peak memory 183420 kb
Host smart-bff74743-ae98-4175-8bee-ce671350ab16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561532805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.3561532805
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.997565610
Short name T275
Test name
Test status
Simulation time 25617796305 ps
CPU time 40.04 seconds
Started Aug 07 05:39:11 PM PDT 24
Finished Aug 07 05:39:51 PM PDT 24
Peak memory 194248 kb
Host smart-7d515ff8-b243-469a-9a9c-0e3c544e4118
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997565610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.997565610
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.1148621042
Short name T288
Test name
Test status
Simulation time 187588953268 ps
CPU time 152.62 seconds
Started Aug 07 05:39:13 PM PDT 24
Finished Aug 07 05:41:46 PM PDT 24
Peak memory 191856 kb
Host smart-440c563f-8f2c-4a65-983a-eff1f1dd174b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148621042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.1148621042
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.2997523077
Short name T296
Test name
Test status
Simulation time 1542106996613 ps
CPU time 829.16 seconds
Started Aug 07 05:37:04 PM PDT 24
Finished Aug 07 05:50:53 PM PDT 24
Peak memory 183432 kb
Host smart-064eb3ae-e339-44b7-9e89-fbaaa6863ad2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997523077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.2997523077
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.2954673887
Short name T380
Test name
Test status
Simulation time 76395168832 ps
CPU time 118.49 seconds
Started Aug 07 05:36:56 PM PDT 24
Finished Aug 07 05:38:55 PM PDT 24
Peak memory 183420 kb
Host smart-f9c4ac63-be85-44a0-85af-64543b55dc9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954673887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.2954673887
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.2743333233
Short name T226
Test name
Test status
Simulation time 163912278612 ps
CPU time 104.82 seconds
Started Aug 07 05:36:59 PM PDT 24
Finished Aug 07 05:38:44 PM PDT 24
Peak memory 191540 kb
Host smart-9c7e5e10-e1e4-48e2-90d0-8552f9f2366c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743333233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.2743333233
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.3168677912
Short name T60
Test name
Test status
Simulation time 936397544469 ps
CPU time 386.54 seconds
Started Aug 07 05:36:59 PM PDT 24
Finished Aug 07 05:43:26 PM PDT 24
Peak memory 191684 kb
Host smart-30825622-456c-46bd-9b85-cd3d2b7859b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168677912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.3168677912
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/130.rv_timer_random.604170720
Short name T208
Test name
Test status
Simulation time 433994757219 ps
CPU time 1353.34 seconds
Started Aug 07 05:39:20 PM PDT 24
Finished Aug 07 06:01:54 PM PDT 24
Peak memory 191624 kb
Host smart-6ede7892-8094-4962-974d-5932ee5b941b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604170720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.604170720
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.3800840948
Short name T151
Test name
Test status
Simulation time 349214205896 ps
CPU time 277.68 seconds
Started Aug 07 05:39:18 PM PDT 24
Finished Aug 07 05:43:56 PM PDT 24
Peak memory 191528 kb
Host smart-76ccf38c-39a4-4ef9-a05f-1b2337997a1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800840948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.3800840948
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.361519469
Short name T435
Test name
Test status
Simulation time 61753455992 ps
CPU time 15.27 seconds
Started Aug 07 05:39:20 PM PDT 24
Finished Aug 07 05:39:35 PM PDT 24
Peak memory 183460 kb
Host smart-e14cfb1c-d25c-4912-a156-591714677505
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361519469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.361519469
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.860760426
Short name T430
Test name
Test status
Simulation time 95402969463 ps
CPU time 78.96 seconds
Started Aug 07 05:39:19 PM PDT 24
Finished Aug 07 05:40:38 PM PDT 24
Peak memory 183408 kb
Host smart-4c96cf18-be12-44b1-88f3-e6a2d18183dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860760426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.860760426
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.1865090121
Short name T222
Test name
Test status
Simulation time 181358988747 ps
CPU time 284.1 seconds
Started Aug 07 05:39:18 PM PDT 24
Finished Aug 07 05:44:02 PM PDT 24
Peak memory 191628 kb
Host smart-abcf10cf-fdaa-44c4-8264-6fc9f86cde24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865090121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.1865090121
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.2051553760
Short name T398
Test name
Test status
Simulation time 414114418317 ps
CPU time 477.15 seconds
Started Aug 07 05:37:00 PM PDT 24
Finished Aug 07 05:44:57 PM PDT 24
Peak memory 183420 kb
Host smart-5fe3d775-98cf-4b77-8e4d-f340905bde9e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051553760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.2051553760
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_random.1695544938
Short name T192
Test name
Test status
Simulation time 393789909190 ps
CPU time 190.95 seconds
Started Aug 07 05:36:56 PM PDT 24
Finished Aug 07 05:40:07 PM PDT 24
Peak memory 191620 kb
Host smart-c52ca242-e169-4340-8967-1abd9ed23ff1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695544938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.1695544938
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/140.rv_timer_random.4289776481
Short name T132
Test name
Test status
Simulation time 126633630608 ps
CPU time 674.59 seconds
Started Aug 07 05:39:27 PM PDT 24
Finished Aug 07 05:50:42 PM PDT 24
Peak memory 191596 kb
Host smart-760b76bc-40d6-4ac8-9583-c26c0df312d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289776481 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.4289776481
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.93543438
Short name T127
Test name
Test status
Simulation time 68202111275 ps
CPU time 98.8 seconds
Started Aug 07 05:39:27 PM PDT 24
Finished Aug 07 05:41:06 PM PDT 24
Peak memory 191688 kb
Host smart-bcf9998b-e599-4cf3-b365-de02853c259b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93543438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.93543438
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.3787185228
Short name T332
Test name
Test status
Simulation time 634755259694 ps
CPU time 1171.98 seconds
Started Aug 07 05:39:27 PM PDT 24
Finished Aug 07 05:58:59 PM PDT 24
Peak memory 191632 kb
Host smart-a28cbf03-a54e-4f8d-976e-01790cd693e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787185228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.3787185228
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.483649312
Short name T150
Test name
Test status
Simulation time 4664231735 ps
CPU time 3.09 seconds
Started Aug 07 05:39:28 PM PDT 24
Finished Aug 07 05:39:31 PM PDT 24
Peak memory 183468 kb
Host smart-67d3ae84-9105-4692-a9b1-4fb72dece06f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483649312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.483649312
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.671707974
Short name T443
Test name
Test status
Simulation time 65159058338 ps
CPU time 104.61 seconds
Started Aug 07 05:39:27 PM PDT 24
Finished Aug 07 05:41:12 PM PDT 24
Peak memory 191644 kb
Host smart-b144998f-b0fe-4c38-99bc-1d0e905e3dae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671707974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.671707974
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.3255202942
Short name T297
Test name
Test status
Simulation time 67386254328 ps
CPU time 686.89 seconds
Started Aug 07 05:39:27 PM PDT 24
Finished Aug 07 05:50:54 PM PDT 24
Peak memory 191588 kb
Host smart-29a9c32a-c572-4cb1-be7a-bc0813b707f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255202942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.3255202942
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.1097463465
Short name T237
Test name
Test status
Simulation time 185010216792 ps
CPU time 81.59 seconds
Started Aug 07 05:39:29 PM PDT 24
Finished Aug 07 05:40:51 PM PDT 24
Peak memory 191548 kb
Host smart-a979eb63-99ea-4f1d-83aa-12c3f6632913
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097463465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.1097463465
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.971701485
Short name T312
Test name
Test status
Simulation time 26147432631 ps
CPU time 49.11 seconds
Started Aug 07 05:39:31 PM PDT 24
Finished Aug 07 05:40:20 PM PDT 24
Peak memory 183392 kb
Host smart-9044765b-f221-4ef0-9ce1-ba7b2838bf25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971701485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.971701485
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.2999709965
Short name T106
Test name
Test status
Simulation time 1853565647534 ps
CPU time 841.36 seconds
Started Aug 07 05:36:57 PM PDT 24
Finished Aug 07 05:50:59 PM PDT 24
Peak memory 183408 kb
Host smart-c8b42bbf-ab11-403b-91b8-14ee42e374fe
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999709965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.2999709965
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.3756930575
Short name T28
Test name
Test status
Simulation time 178557907449 ps
CPU time 252.87 seconds
Started Aug 07 05:36:54 PM PDT 24
Finished Aug 07 05:41:07 PM PDT 24
Peak memory 183424 kb
Host smart-e79096a9-1385-4322-ab6f-8929f1901dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756930575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.3756930575
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.4258159579
Short name T144
Test name
Test status
Simulation time 115844662021 ps
CPU time 184.54 seconds
Started Aug 07 05:36:59 PM PDT 24
Finished Aug 07 05:40:04 PM PDT 24
Peak memory 191668 kb
Host smart-97108468-e01e-402b-8957-129b5a1b3435
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258159579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.4258159579
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.3809171812
Short name T304
Test name
Test status
Simulation time 91460693474 ps
CPU time 935.91 seconds
Started Aug 07 05:36:59 PM PDT 24
Finished Aug 07 05:52:35 PM PDT 24
Peak memory 195284 kb
Host smart-660870e2-4e1f-470d-87b4-c29c51678156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809171812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.3809171812
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.530654090
Short name T36
Test name
Test status
Simulation time 53442098197 ps
CPU time 323.4 seconds
Started Aug 07 05:37:00 PM PDT 24
Finished Aug 07 05:42:23 PM PDT 24
Peak memory 206256 kb
Host smart-0c677f2d-8208-431a-a550-acf73cb33c3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530654090 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all_with_rand_reset.530654090
Directory /workspace/15.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.rv_timer_random.4225047908
Short name T114
Test name
Test status
Simulation time 226361131451 ps
CPU time 157.47 seconds
Started Aug 07 05:39:33 PM PDT 24
Finished Aug 07 05:42:10 PM PDT 24
Peak memory 183436 kb
Host smart-37de688f-9c8b-4003-8f00-5f890f14a83f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225047908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.4225047908
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.67819682
Short name T437
Test name
Test status
Simulation time 255468593449 ps
CPU time 180.96 seconds
Started Aug 07 05:39:34 PM PDT 24
Finished Aug 07 05:42:36 PM PDT 24
Peak memory 191632 kb
Host smart-e6490af4-50ee-4389-866a-50f000443e03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67819682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.67819682
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.4224327660
Short name T188
Test name
Test status
Simulation time 82845241029 ps
CPU time 73.7 seconds
Started Aug 07 05:39:35 PM PDT 24
Finished Aug 07 05:40:49 PM PDT 24
Peak memory 183420 kb
Host smart-fdff28cd-f752-4bc4-8058-9d11ff77d29e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224327660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.4224327660
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.3227916589
Short name T432
Test name
Test status
Simulation time 98156063906 ps
CPU time 1722.38 seconds
Started Aug 07 05:39:36 PM PDT 24
Finished Aug 07 06:08:19 PM PDT 24
Peak memory 191648 kb
Host smart-166077a6-4a21-4142-9ba3-a3039304cfbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227916589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.3227916589
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.1292555664
Short name T45
Test name
Test status
Simulation time 224104870851 ps
CPU time 178.52 seconds
Started Aug 07 05:39:33 PM PDT 24
Finished Aug 07 05:42:32 PM PDT 24
Peak memory 191596 kb
Host smart-997c67a8-b7fe-4317-9a13-536a57dddaeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292555664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.1292555664
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.1227839069
Short name T339
Test name
Test status
Simulation time 42814905281 ps
CPU time 17.78 seconds
Started Aug 07 05:36:55 PM PDT 24
Finished Aug 07 05:37:13 PM PDT 24
Peak memory 183328 kb
Host smart-c7caa280-1e0f-4b9f-9596-72ec3ee61714
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227839069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.1227839069
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.426019054
Short name T395
Test name
Test status
Simulation time 384120865498 ps
CPU time 145.6 seconds
Started Aug 07 05:36:57 PM PDT 24
Finished Aug 07 05:39:23 PM PDT 24
Peak memory 183404 kb
Host smart-55c1b594-2551-4a86-b9eb-f1c133f83bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426019054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.426019054
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.3215497619
Short name T6
Test name
Test status
Simulation time 375030643213 ps
CPU time 177.25 seconds
Started Aug 07 05:36:58 PM PDT 24
Finished Aug 07 05:39:55 PM PDT 24
Peak memory 191624 kb
Host smart-13e6bab1-8d95-4ccc-8489-ad8727baa334
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215497619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.3215497619
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.1827888511
Short name T424
Test name
Test status
Simulation time 430596803323 ps
CPU time 188.16 seconds
Started Aug 07 05:37:00 PM PDT 24
Finished Aug 07 05:40:08 PM PDT 24
Peak memory 183324 kb
Host smart-72e5c5ca-20ea-4053-a1f1-7ae44db1fc68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827888511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.1827888511
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/161.rv_timer_random.1350271182
Short name T83
Test name
Test status
Simulation time 335944851160 ps
CPU time 391.51 seconds
Started Aug 07 05:39:33 PM PDT 24
Finished Aug 07 05:46:05 PM PDT 24
Peak memory 191628 kb
Host smart-5738cf39-4277-4267-8af0-2122bdeef970
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350271182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.1350271182
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.4043800123
Short name T307
Test name
Test status
Simulation time 30412013733 ps
CPU time 53.09 seconds
Started Aug 07 05:39:37 PM PDT 24
Finished Aug 07 05:40:30 PM PDT 24
Peak memory 191640 kb
Host smart-f9b31e4e-4b36-41f5-a8a6-71e6e709c18c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043800123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.4043800123
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.3274637451
Short name T200
Test name
Test status
Simulation time 299513481610 ps
CPU time 1736.82 seconds
Started Aug 07 05:39:39 PM PDT 24
Finished Aug 07 06:08:36 PM PDT 24
Peak memory 191596 kb
Host smart-3e773d8b-37c5-4342-8ca1-95b6b511b3d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274637451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.3274637451
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.2803806253
Short name T231
Test name
Test status
Simulation time 173505993228 ps
CPU time 468.52 seconds
Started Aug 07 05:39:39 PM PDT 24
Finished Aug 07 05:47:28 PM PDT 24
Peak memory 191520 kb
Host smart-16895ab1-a8d8-4170-ba8c-af3becd6ef0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803806253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.2803806253
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.1636540849
Short name T284
Test name
Test status
Simulation time 298216205689 ps
CPU time 625.86 seconds
Started Aug 07 05:39:38 PM PDT 24
Finished Aug 07 05:50:04 PM PDT 24
Peak memory 191624 kb
Host smart-2cbdf79e-afe8-4309-a52d-d812e9afda5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636540849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.1636540849
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.245202768
Short name T436
Test name
Test status
Simulation time 18918186206 ps
CPU time 32.51 seconds
Started Aug 07 05:39:39 PM PDT 24
Finished Aug 07 05:40:12 PM PDT 24
Peak memory 183384 kb
Host smart-17732d02-b871-41c7-97ca-70b511f3e693
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245202768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.245202768
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.1536724934
Short name T391
Test name
Test status
Simulation time 134074530288 ps
CPU time 199.92 seconds
Started Aug 07 05:37:00 PM PDT 24
Finished Aug 07 05:40:20 PM PDT 24
Peak memory 183420 kb
Host smart-29cadb02-201e-40f2-9d91-a8b7aacc2be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536724934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.1536724934
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.1602532058
Short name T276
Test name
Test status
Simulation time 416341910459 ps
CPU time 238.96 seconds
Started Aug 07 05:36:57 PM PDT 24
Finished Aug 07 05:40:57 PM PDT 24
Peak memory 191552 kb
Host smart-b60738bc-93e0-496e-9853-3dab16a52d2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602532058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.1602532058
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.1882533592
Short name T206
Test name
Test status
Simulation time 41673897253 ps
CPU time 57.71 seconds
Started Aug 07 05:36:59 PM PDT 24
Finished Aug 07 05:37:57 PM PDT 24
Peak memory 191616 kb
Host smart-8c457dec-9fcb-421c-baa8-99bd991e9ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882533592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.1882533592
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.4243137096
Short name T301
Test name
Test status
Simulation time 2215633243002 ps
CPU time 1610.69 seconds
Started Aug 07 05:36:59 PM PDT 24
Finished Aug 07 06:03:50 PM PDT 24
Peak memory 191664 kb
Host smart-857f5740-4e7e-4d11-9886-fc8406e8d9c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243137096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.4243137096
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.2496622306
Short name T50
Test name
Test status
Simulation time 36726959452 ps
CPU time 168.47 seconds
Started Aug 07 05:36:59 PM PDT 24
Finished Aug 07 05:39:47 PM PDT 24
Peak memory 198060 kb
Host smart-a54f499e-5f53-42e4-b048-401b0718871d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496622306 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all_with_rand_reset.2496622306
Directory /workspace/17.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.2373119020
Short name T137
Test name
Test status
Simulation time 130065380643 ps
CPU time 130.3 seconds
Started Aug 07 05:39:39 PM PDT 24
Finished Aug 07 05:41:50 PM PDT 24
Peak memory 191648 kb
Host smart-83e10c5f-6245-4974-abd6-3bd74e45324d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373119020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.2373119020
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.1237457880
Short name T280
Test name
Test status
Simulation time 390789702996 ps
CPU time 871.56 seconds
Started Aug 07 05:39:38 PM PDT 24
Finished Aug 07 05:54:09 PM PDT 24
Peak memory 191604 kb
Host smart-087cb4d0-e516-440b-b623-1f843af2b887
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237457880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.1237457880
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.909620370
Short name T241
Test name
Test status
Simulation time 234025742484 ps
CPU time 289.56 seconds
Started Aug 07 05:39:45 PM PDT 24
Finished Aug 07 05:44:34 PM PDT 24
Peak memory 191684 kb
Host smart-ce2393fe-51f5-45a7-bd12-4385f60a603b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909620370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.909620370
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.2658406912
Short name T427
Test name
Test status
Simulation time 153711562668 ps
CPU time 159.55 seconds
Started Aug 07 05:41:00 PM PDT 24
Finished Aug 07 05:43:39 PM PDT 24
Peak memory 183348 kb
Host smart-0624a6e2-de31-427c-84d3-d0f631046643
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658406912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.2658406912
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.2913786102
Short name T225
Test name
Test status
Simulation time 163159671092 ps
CPU time 1036.28 seconds
Started Aug 07 05:39:44 PM PDT 24
Finished Aug 07 05:57:01 PM PDT 24
Peak memory 191628 kb
Host smart-381a1f01-6215-450a-abc9-0f550958ab16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913786102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.2913786102
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.68726923
Short name T143
Test name
Test status
Simulation time 4934494476 ps
CPU time 8.47 seconds
Started Aug 07 05:39:44 PM PDT 24
Finished Aug 07 05:39:53 PM PDT 24
Peak memory 183356 kb
Host smart-9236d463-1a8f-47b2-96c7-fe578b46ddbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68726923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.68726923
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.2424282678
Short name T320
Test name
Test status
Simulation time 42217470654 ps
CPU time 64.05 seconds
Started Aug 07 05:39:51 PM PDT 24
Finished Aug 07 05:40:55 PM PDT 24
Peak memory 191648 kb
Host smart-7338f5d1-71b4-4a13-bd31-88fe97383e1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424282678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.2424282678
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.3017129826
Short name T321
Test name
Test status
Simulation time 38206605065 ps
CPU time 56.42 seconds
Started Aug 07 05:39:48 PM PDT 24
Finished Aug 07 05:40:45 PM PDT 24
Peak memory 183244 kb
Host smart-85368b2f-02db-436d-ab89-5953a558c651
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017129826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.3017129826
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.3471712989
Short name T4
Test name
Test status
Simulation time 79903556544 ps
CPU time 339.91 seconds
Started Aug 07 05:39:50 PM PDT 24
Finished Aug 07 05:45:30 PM PDT 24
Peak memory 191528 kb
Host smart-59861451-d95f-4595-bbe3-2c3301abb3a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471712989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.3471712989
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.2591654175
Short name T115
Test name
Test status
Simulation time 198154886363 ps
CPU time 102.37 seconds
Started Aug 07 05:36:57 PM PDT 24
Finished Aug 07 05:38:40 PM PDT 24
Peak memory 183428 kb
Host smart-a0152591-9958-43f0-be89-fc8966235959
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591654175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.2591654175
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.4130276586
Short name T387
Test name
Test status
Simulation time 302124429665 ps
CPU time 119.9 seconds
Started Aug 07 05:36:58 PM PDT 24
Finished Aug 07 05:38:58 PM PDT 24
Peak memory 183400 kb
Host smart-bc8f4f59-f3e2-4bec-a8a9-76dbfbd20559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130276586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.4130276586
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.2612035408
Short name T119
Test name
Test status
Simulation time 159099960782 ps
CPU time 491.2 seconds
Started Aug 07 05:36:59 PM PDT 24
Finished Aug 07 05:45:11 PM PDT 24
Peak memory 191668 kb
Host smart-dafb4e15-7a84-442a-a5d8-219fa38e409d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612035408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.2612035408
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.2678885327
Short name T404
Test name
Test status
Simulation time 939817723 ps
CPU time 1.33 seconds
Started Aug 07 05:37:02 PM PDT 24
Finished Aug 07 05:37:03 PM PDT 24
Peak memory 193660 kb
Host smart-9167b3ed-ccc5-4a39-a781-39b8265c6470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678885327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.2678885327
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.215816775
Short name T248
Test name
Test status
Simulation time 417429921701 ps
CPU time 583.95 seconds
Started Aug 07 05:37:03 PM PDT 24
Finished Aug 07 05:46:47 PM PDT 24
Peak memory 195184 kb
Host smart-a7d89056-8ba1-4492-b6bb-dcf4729f81de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215816775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all.
215816775
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.2814622914
Short name T38
Test name
Test status
Simulation time 55430971180 ps
CPU time 530.81 seconds
Started Aug 07 05:37:05 PM PDT 24
Finished Aug 07 05:45:56 PM PDT 24
Peak memory 208192 kb
Host smart-f43cbaea-e990-4815-b8a8-0a8496bb0856
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814622914 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all_with_rand_reset.2814622914
Directory /workspace/18.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.rv_timer_random.1763853485
Short name T331
Test name
Test status
Simulation time 200077854683 ps
CPU time 267.3 seconds
Started Aug 07 05:39:50 PM PDT 24
Finished Aug 07 05:44:18 PM PDT 24
Peak memory 191624 kb
Host smart-bd8e4f59-e85c-445a-a4b0-cd3d24c87581
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763853485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.1763853485
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.1942816445
Short name T174
Test name
Test status
Simulation time 30672205341 ps
CPU time 38.55 seconds
Started Aug 07 05:39:53 PM PDT 24
Finished Aug 07 05:40:31 PM PDT 24
Peak memory 191672 kb
Host smart-ef874917-2824-4119-8764-1b6dae3f13e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942816445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.1942816445
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.436188911
Short name T123
Test name
Test status
Simulation time 129027980388 ps
CPU time 233.73 seconds
Started Aug 07 05:39:54 PM PDT 24
Finished Aug 07 05:43:48 PM PDT 24
Peak memory 191596 kb
Host smart-b38b471f-1164-4a34-8264-33af7f38d9eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436188911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.436188911
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.932976776
Short name T197
Test name
Test status
Simulation time 556179959427 ps
CPU time 423.91 seconds
Started Aug 07 05:39:56 PM PDT 24
Finished Aug 07 05:47:00 PM PDT 24
Peak memory 191628 kb
Host smart-832a95fe-b22b-4d28-a5e3-680ea50c7d55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932976776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.932976776
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.3064821219
Short name T277
Test name
Test status
Simulation time 116064045507 ps
CPU time 764.74 seconds
Started Aug 07 05:39:54 PM PDT 24
Finished Aug 07 05:52:39 PM PDT 24
Peak memory 192708 kb
Host smart-3bb1729a-f498-4a1b-9f29-f59f9b3b3812
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064821219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.3064821219
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.3063427908
Short name T259
Test name
Test status
Simulation time 118112003893 ps
CPU time 201.17 seconds
Started Aug 07 05:37:04 PM PDT 24
Finished Aug 07 05:40:25 PM PDT 24
Peak memory 183464 kb
Host smart-6e46aebd-c220-44d8-97d4-8510c47bda46
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063427908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.3063427908
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.4099840021
Short name T384
Test name
Test status
Simulation time 148895675569 ps
CPU time 213.98 seconds
Started Aug 07 05:37:03 PM PDT 24
Finished Aug 07 05:40:37 PM PDT 24
Peak memory 183456 kb
Host smart-b68e119a-da98-4b0c-8fed-672e48c848e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099840021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.4099840021
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/191.rv_timer_random.1836189268
Short name T309
Test name
Test status
Simulation time 208610421641 ps
CPU time 231.46 seconds
Started Aug 07 05:40:01 PM PDT 24
Finished Aug 07 05:43:52 PM PDT 24
Peak memory 191580 kb
Host smart-1bd5761e-95ab-4d66-b685-eb853915af30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836189268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.1836189268
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.4264656098
Short name T317
Test name
Test status
Simulation time 162478565871 ps
CPU time 312 seconds
Started Aug 07 05:40:00 PM PDT 24
Finished Aug 07 05:45:12 PM PDT 24
Peak memory 191688 kb
Host smart-4c430922-b0c5-4fab-871f-5c8494a4e862
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264656098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.4264656098
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.3835977636
Short name T285
Test name
Test status
Simulation time 92540468657 ps
CPU time 694.28 seconds
Started Aug 07 05:39:59 PM PDT 24
Finished Aug 07 05:51:33 PM PDT 24
Peak memory 191608 kb
Host smart-8475ddae-801f-475d-b7bb-15f0013dce83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835977636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.3835977636
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.4052027599
Short name T279
Test name
Test status
Simulation time 171886086312 ps
CPU time 85.33 seconds
Started Aug 07 05:40:06 PM PDT 24
Finished Aug 07 05:41:32 PM PDT 24
Peak memory 191668 kb
Host smart-d2281374-4c6c-4a67-b754-7f8c84b1c47e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052027599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.4052027599
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.3749772194
Short name T252
Test name
Test status
Simulation time 83568743495 ps
CPU time 589.83 seconds
Started Aug 07 05:40:06 PM PDT 24
Finished Aug 07 05:49:56 PM PDT 24
Peak memory 191608 kb
Host smart-30ca87ef-701e-42f2-8d31-ed98af0070d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749772194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.3749772194
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.3482768499
Short name T274
Test name
Test status
Simulation time 79178457327 ps
CPU time 480.87 seconds
Started Aug 07 05:40:05 PM PDT 24
Finished Aug 07 05:48:06 PM PDT 24
Peak memory 191580 kb
Host smart-f67a7679-73b0-4598-93a0-15756438100e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482768499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.3482768499
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.3791329845
Short name T65
Test name
Test status
Simulation time 1414375647770 ps
CPU time 563.54 seconds
Started Aug 07 05:36:44 PM PDT 24
Finished Aug 07 05:46:07 PM PDT 24
Peak memory 183420 kb
Host smart-df3c2d0d-0981-4886-b883-1745a51c17b2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791329845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.3791329845
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.3155356321
Short name T382
Test name
Test status
Simulation time 94784620681 ps
CPU time 126.57 seconds
Started Aug 07 05:36:44 PM PDT 24
Finished Aug 07 05:38:51 PM PDT 24
Peak memory 183424 kb
Host smart-47d6b4c7-0582-4f2c-a44d-45abc091097a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155356321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.3155356321
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.1355589954
Short name T173
Test name
Test status
Simulation time 14489505279 ps
CPU time 21.17 seconds
Started Aug 07 05:36:44 PM PDT 24
Finished Aug 07 05:37:05 PM PDT 24
Peak memory 183464 kb
Host smart-91a1923f-04b5-40ca-a1f9-2875ae20d0b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355589954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.1355589954
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.3501570862
Short name T440
Test name
Test status
Simulation time 939344379 ps
CPU time 1.24 seconds
Started Aug 07 05:36:45 PM PDT 24
Finished Aug 07 05:36:46 PM PDT 24
Peak memory 183148 kb
Host smart-1720e555-a2d0-428b-bf20-7826a9eb395c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501570862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.3501570862
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.1697743330
Short name T19
Test name
Test status
Simulation time 50366697 ps
CPU time 0.74 seconds
Started Aug 07 05:36:47 PM PDT 24
Finished Aug 07 05:36:48 PM PDT 24
Peak memory 213988 kb
Host smart-46e7d6bf-6658-45f5-897f-c1ba103a382f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697743330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.1697743330
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all_with_rand_reset.3788648596
Short name T39
Test name
Test status
Simulation time 92309286332 ps
CPU time 694.86 seconds
Started Aug 07 05:36:45 PM PDT 24
Finished Aug 07 05:48:21 PM PDT 24
Peak memory 208036 kb
Host smart-bddeffe4-3e10-406b-bd05-ef8f4fcdfc06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788648596 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all_with_rand_reset.3788648596
Directory /workspace/2.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.3015821983
Short name T327
Test name
Test status
Simulation time 112014975686 ps
CPU time 166.79 seconds
Started Aug 07 05:37:03 PM PDT 24
Finished Aug 07 05:39:50 PM PDT 24
Peak memory 183468 kb
Host smart-1301a847-9b50-41b1-a48f-b064f9205193
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015821983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.3015821983
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.2501590528
Short name T360
Test name
Test status
Simulation time 142175298004 ps
CPU time 207.86 seconds
Started Aug 07 05:37:04 PM PDT 24
Finished Aug 07 05:40:32 PM PDT 24
Peak memory 183320 kb
Host smart-65673c2f-8473-4cf9-9c85-55c15fbf4153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501590528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.2501590528
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.2144493412
Short name T261
Test name
Test status
Simulation time 335928206017 ps
CPU time 713.51 seconds
Started Aug 07 05:37:04 PM PDT 24
Finished Aug 07 05:48:58 PM PDT 24
Peak memory 191604 kb
Host smart-bcd327ab-388b-43ce-8ab6-10a300fb7518
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144493412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.2144493412
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.3817085433
Short name T224
Test name
Test status
Simulation time 179173383817 ps
CPU time 437.34 seconds
Started Aug 07 05:37:04 PM PDT 24
Finished Aug 07 05:44:21 PM PDT 24
Peak memory 183424 kb
Host smart-70597485-e053-4e20-b939-b3a967e8360b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817085433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.3817085433
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.2633100116
Short name T359
Test name
Test status
Simulation time 104094272043 ps
CPU time 151.04 seconds
Started Aug 07 05:37:04 PM PDT 24
Finished Aug 07 05:39:35 PM PDT 24
Peak memory 195880 kb
Host smart-bbd3165d-64b9-4c27-a142-d4f0ff27d6d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633100116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.2633100116
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.1883343741
Short name T186
Test name
Test status
Simulation time 953438940810 ps
CPU time 422.49 seconds
Started Aug 07 05:37:08 PM PDT 24
Finished Aug 07 05:44:11 PM PDT 24
Peak memory 183380 kb
Host smart-32b899fc-5615-4d4b-a031-b74deed784da
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883343741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.1883343741
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.1142036095
Short name T375
Test name
Test status
Simulation time 142057687761 ps
CPU time 201.13 seconds
Started Aug 07 05:37:03 PM PDT 24
Finished Aug 07 05:40:25 PM PDT 24
Peak memory 183396 kb
Host smart-b0ce0330-09b2-406d-9537-af02780e0ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142036095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.1142036095
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.1919714048
Short name T220
Test name
Test status
Simulation time 78240761849 ps
CPU time 1370.09 seconds
Started Aug 07 05:37:04 PM PDT 24
Finished Aug 07 05:59:55 PM PDT 24
Peak memory 191608 kb
Host smart-bc2306cd-722d-4089-897f-5d7591710b43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919714048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.1919714048
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.1807871686
Short name T386
Test name
Test status
Simulation time 104747132 ps
CPU time 0.57 seconds
Started Aug 07 05:37:04 PM PDT 24
Finished Aug 07 05:37:05 PM PDT 24
Peak memory 183120 kb
Host smart-770b1c24-c791-4f64-a022-25ed2d3f3c53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807871686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.1807871686
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all_with_rand_reset.3741960906
Short name T15
Test name
Test status
Simulation time 337786178371 ps
CPU time 641.07 seconds
Started Aug 07 05:37:03 PM PDT 24
Finished Aug 07 05:47:44 PM PDT 24
Peak memory 214260 kb
Host smart-0cdb9b7c-0fd1-4853-a632-22181e7c7611
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741960906 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all_with_rand_reset.3741960906
Directory /workspace/21.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.575351656
Short name T361
Test name
Test status
Simulation time 106259228209 ps
CPU time 137.29 seconds
Started Aug 07 05:37:02 PM PDT 24
Finished Aug 07 05:39:20 PM PDT 24
Peak memory 183312 kb
Host smart-7c05f03d-6d6e-4806-a052-9cd1a4581b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575351656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.575351656
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.3864613547
Short name T290
Test name
Test status
Simulation time 37685670171 ps
CPU time 474.31 seconds
Started Aug 07 05:37:04 PM PDT 24
Finished Aug 07 05:44:58 PM PDT 24
Peak memory 183400 kb
Host smart-6cc5ecea-1c05-4797-8173-40b1012f8d55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864613547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.3864613547
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.284842120
Short name T105
Test name
Test status
Simulation time 126909900274 ps
CPU time 105.21 seconds
Started Aug 07 05:37:05 PM PDT 24
Finished Aug 07 05:38:50 PM PDT 24
Peak memory 183392 kb
Host smart-fb8aac9c-3ee3-4f9d-9768-030cd7c3d1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284842120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.284842120
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.1213027415
Short name T243
Test name
Test status
Simulation time 1147342628786 ps
CPU time 598.71 seconds
Started Aug 07 05:37:02 PM PDT 24
Finished Aug 07 05:47:01 PM PDT 24
Peak memory 183424 kb
Host smart-5d46b3ae-d4e8-43dd-acc1-93a6aa1b36f5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213027415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.1213027415
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.1933797072
Short name T408
Test name
Test status
Simulation time 162058605674 ps
CPU time 115.27 seconds
Started Aug 07 05:37:02 PM PDT 24
Finished Aug 07 05:38:57 PM PDT 24
Peak memory 183396 kb
Host smart-c0526eb5-8038-4580-8d3c-2cb846953cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933797072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.1933797072
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.1082380182
Short name T128
Test name
Test status
Simulation time 238241432292 ps
CPU time 111.76 seconds
Started Aug 07 05:37:03 PM PDT 24
Finished Aug 07 05:38:55 PM PDT 24
Peak memory 191640 kb
Host smart-07e00e2b-2f5d-410a-8730-bd0c056fddc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082380182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.1082380182
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.3556109745
Short name T158
Test name
Test status
Simulation time 97748159969 ps
CPU time 124.43 seconds
Started Aug 07 05:37:08 PM PDT 24
Finished Aug 07 05:39:12 PM PDT 24
Peak memory 191592 kb
Host smart-a3609cdc-5319-4370-888c-e1677e9dc85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556109745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.3556109745
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.2983611538
Short name T445
Test name
Test status
Simulation time 91737458027 ps
CPU time 118.9 seconds
Started Aug 07 05:37:10 PM PDT 24
Finished Aug 07 05:39:09 PM PDT 24
Peak memory 183408 kb
Host smart-799f9118-b375-422d-a590-d538a78ea0d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983611538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.2983611538
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.3230816248
Short name T116
Test name
Test status
Simulation time 926076355780 ps
CPU time 779.77 seconds
Started Aug 07 05:37:09 PM PDT 24
Finished Aug 07 05:50:08 PM PDT 24
Peak memory 183420 kb
Host smart-76678892-0e21-4dec-8b5d-fc11f50f635e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230816248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.3230816248
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.1815737618
Short name T358
Test name
Test status
Simulation time 27965382897 ps
CPU time 42.4 seconds
Started Aug 07 05:37:10 PM PDT 24
Finished Aug 07 05:37:52 PM PDT 24
Peak memory 183424 kb
Host smart-f61bb1e4-a489-44f5-ae67-f107059bcfa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815737618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.1815737618
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.2304390851
Short name T202
Test name
Test status
Simulation time 181438318583 ps
CPU time 341.67 seconds
Started Aug 07 05:37:11 PM PDT 24
Finished Aug 07 05:42:53 PM PDT 24
Peak memory 191616 kb
Host smart-ff0a30f7-741c-4150-a1c8-5ae9c6e05504
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304390851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.2304390851
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.226650521
Short name T335
Test name
Test status
Simulation time 29905755759 ps
CPU time 76.98 seconds
Started Aug 07 05:37:09 PM PDT 24
Finished Aug 07 05:38:27 PM PDT 24
Peak memory 183372 kb
Host smart-44635d64-e3f8-4bdd-b3d0-3c0f410be53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226650521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.226650521
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.2879426214
Short name T411
Test name
Test status
Simulation time 350676721251 ps
CPU time 313.72 seconds
Started Aug 07 05:37:13 PM PDT 24
Finished Aug 07 05:42:27 PM PDT 24
Peak memory 183344 kb
Host smart-46390820-80c6-4668-97d6-1677e841fd8c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879426214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.2879426214
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.126636952
Short name T402
Test name
Test status
Simulation time 399213310463 ps
CPU time 180.13 seconds
Started Aug 07 05:37:12 PM PDT 24
Finished Aug 07 05:40:12 PM PDT 24
Peak memory 183344 kb
Host smart-69d3f614-d4dd-4ffd-b81e-4571863be47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126636952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.126636952
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.2202165144
Short name T315
Test name
Test status
Simulation time 53560950721 ps
CPU time 414.79 seconds
Started Aug 07 05:37:15 PM PDT 24
Finished Aug 07 05:44:10 PM PDT 24
Peak memory 191564 kb
Host smart-cb081528-af9b-42a2-b96a-b6df698c6e78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202165144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.2202165144
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.2458721415
Short name T385
Test name
Test status
Simulation time 49539411812 ps
CPU time 79.53 seconds
Started Aug 07 05:37:10 PM PDT 24
Finished Aug 07 05:38:30 PM PDT 24
Peak memory 183432 kb
Host smart-892a65df-06a7-420a-87b9-bcfb4483380e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458721415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.2458721415
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.4151274035
Short name T61
Test name
Test status
Simulation time 292736040797 ps
CPU time 383.73 seconds
Started Aug 07 05:37:11 PM PDT 24
Finished Aug 07 05:43:34 PM PDT 24
Peak memory 191552 kb
Host smart-ea8d4241-2a5e-4333-96f3-b011e181ed8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151274035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.4151274035
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.1037086105
Short name T374
Test name
Test status
Simulation time 169541838499 ps
CPU time 213.73 seconds
Started Aug 07 05:37:09 PM PDT 24
Finished Aug 07 05:40:43 PM PDT 24
Peak memory 183468 kb
Host smart-888d27b1-3f15-446e-bd1f-b695577f0be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037086105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.1037086105
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.4041941563
Short name T308
Test name
Test status
Simulation time 54327938387 ps
CPU time 78.36 seconds
Started Aug 07 05:37:10 PM PDT 24
Finished Aug 07 05:38:29 PM PDT 24
Peak memory 183384 kb
Host smart-17769ee3-755f-406b-b744-e26d90833984
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041941563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.4041941563
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.60712575
Short name T71
Test name
Test status
Simulation time 18593921 ps
CPU time 0.53 seconds
Started Aug 07 05:37:11 PM PDT 24
Finished Aug 07 05:37:11 PM PDT 24
Peak memory 183092 kb
Host smart-763db6a5-daf0-4dbb-9a6d-e12e171fcad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60712575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.60712575
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.2359046703
Short name T420
Test name
Test status
Simulation time 201861213696 ps
CPU time 292.62 seconds
Started Aug 07 05:37:09 PM PDT 24
Finished Aug 07 05:42:02 PM PDT 24
Peak memory 183420 kb
Host smart-32c73016-8f80-4dc7-8314-fa56ebb2588c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359046703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.2359046703
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.3871726616
Short name T235
Test name
Test status
Simulation time 69455221984 ps
CPU time 111.54 seconds
Started Aug 07 05:37:10 PM PDT 24
Finished Aug 07 05:39:02 PM PDT 24
Peak memory 183404 kb
Host smart-5c96ed74-4dde-4689-9cdc-76eeb94485de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871726616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.3871726616
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.51660208
Short name T149
Test name
Test status
Simulation time 335344881530 ps
CPU time 1023.21 seconds
Started Aug 07 05:37:18 PM PDT 24
Finished Aug 07 05:54:21 PM PDT 24
Peak memory 195204 kb
Host smart-89b87d0f-cc34-404e-867c-e149be17f37e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51660208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all.51660208
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.2489577364
Short name T267
Test name
Test status
Simulation time 394870554419 ps
CPU time 674.55 seconds
Started Aug 07 05:37:15 PM PDT 24
Finished Aug 07 05:48:30 PM PDT 24
Peak memory 183432 kb
Host smart-b641d26e-52a6-4eb4-bd82-4402b506751d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489577364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.2489577364
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.1194518036
Short name T394
Test name
Test status
Simulation time 50398240081 ps
CPU time 62.99 seconds
Started Aug 07 05:37:16 PM PDT 24
Finished Aug 07 05:38:19 PM PDT 24
Peak memory 183328 kb
Host smart-39cbf210-e41c-47a7-91d2-504b6dec5075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194518036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.1194518036
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.3296735486
Short name T405
Test name
Test status
Simulation time 112428918026 ps
CPU time 93.33 seconds
Started Aug 07 05:37:26 PM PDT 24
Finished Aug 07 05:38:59 PM PDT 24
Peak memory 191560 kb
Host smart-3ee9322a-97d5-4056-81ba-65e3c3b774a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296735486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.3296735486
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.2690957950
Short name T44
Test name
Test status
Simulation time 8563403503 ps
CPU time 7.14 seconds
Started Aug 07 05:37:16 PM PDT 24
Finished Aug 07 05:37:23 PM PDT 24
Peak memory 183460 kb
Host smart-710bc6e8-f210-4230-8b41-7a732584f939
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690957950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.2690957950
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.749834438
Short name T372
Test name
Test status
Simulation time 200033575291 ps
CPU time 74.34 seconds
Started Aug 07 05:37:15 PM PDT 24
Finished Aug 07 05:38:29 PM PDT 24
Peak memory 183396 kb
Host smart-cd2d4b9a-bb71-4aff-8677-3b03ca563a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749834438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.749834438
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.1619804104
Short name T434
Test name
Test status
Simulation time 141923521207 ps
CPU time 74.59 seconds
Started Aug 07 05:37:14 PM PDT 24
Finished Aug 07 05:38:29 PM PDT 24
Peak memory 191648 kb
Host smart-9519d395-b25c-44c3-a6b3-5ee1183bbda9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619804104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.1619804104
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.1075135199
Short name T295
Test name
Test status
Simulation time 46778437112 ps
CPU time 481.26 seconds
Started Aug 07 05:37:14 PM PDT 24
Finished Aug 07 05:45:15 PM PDT 24
Peak memory 183436 kb
Host smart-7822f64c-21db-4f66-86ca-3f92f52926ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075135199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.1075135199
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.746530429
Short name T388
Test name
Test status
Simulation time 143768492407 ps
CPU time 138.34 seconds
Started Aug 07 05:37:14 PM PDT 24
Finished Aug 07 05:39:33 PM PDT 24
Peak memory 194884 kb
Host smart-8d4f1de7-1550-47c3-ae67-f6a8c25502dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746530429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all.
746530429
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all_with_rand_reset.4030655118
Short name T416
Test name
Test status
Simulation time 90856716221 ps
CPU time 159.42 seconds
Started Aug 07 05:37:16 PM PDT 24
Finished Aug 07 05:39:56 PM PDT 24
Peak memory 206684 kb
Host smart-b653485a-062f-4e08-832e-f55add03403b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030655118 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all_with_rand_reset.4030655118
Directory /workspace/29.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.623285998
Short name T209
Test name
Test status
Simulation time 215127222054 ps
CPU time 112.52 seconds
Started Aug 07 05:36:48 PM PDT 24
Finished Aug 07 05:38:40 PM PDT 24
Peak memory 183436 kb
Host smart-546d1f31-f522-454e-8cfe-4d0ed70fa959
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623285998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.rv_timer_cfg_update_on_fly.623285998
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.3375766877
Short name T364
Test name
Test status
Simulation time 329107226352 ps
CPU time 259.27 seconds
Started Aug 07 05:36:46 PM PDT 24
Finished Aug 07 05:41:06 PM PDT 24
Peak memory 183408 kb
Host smart-373c1137-0dc9-48f2-b1d9-4d0a75563cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375766877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.3375766877
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.781917565
Short name T247
Test name
Test status
Simulation time 255888632491 ps
CPU time 359.97 seconds
Started Aug 07 05:36:46 PM PDT 24
Finished Aug 07 05:42:46 PM PDT 24
Peak memory 191548 kb
Host smart-854afdad-39d5-4d91-9c80-108da226365e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781917565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.781917565
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.2649161984
Short name T215
Test name
Test status
Simulation time 59862861912 ps
CPU time 606.24 seconds
Started Aug 07 05:36:54 PM PDT 24
Finished Aug 07 05:47:00 PM PDT 24
Peak memory 195212 kb
Host smart-db7549fb-07af-4df1-b0f2-3fea2a41d491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649161984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.2649161984
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.760551428
Short name T16
Test name
Test status
Simulation time 394820525 ps
CPU time 0.82 seconds
Started Aug 07 05:36:45 PM PDT 24
Finished Aug 07 05:36:46 PM PDT 24
Peak memory 214660 kb
Host smart-ba9fb6ff-8844-40a2-bb3d-49554be1d881
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760551428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.760551428
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.3973921576
Short name T370
Test name
Test status
Simulation time 337466647026 ps
CPU time 56.48 seconds
Started Aug 07 05:36:49 PM PDT 24
Finished Aug 07 05:37:45 PM PDT 24
Peak memory 194344 kb
Host smart-1a6d5056-91c6-499c-9406-cf7be4a75e1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973921576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
3973921576
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.3216182404
Short name T218
Test name
Test status
Simulation time 306480135674 ps
CPU time 498.46 seconds
Started Aug 07 05:37:16 PM PDT 24
Finished Aug 07 05:45:34 PM PDT 24
Peak memory 183424 kb
Host smart-da171620-3cf1-4342-912d-eb7683a0249f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216182404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.3216182404
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.3841689695
Short name T418
Test name
Test status
Simulation time 125099010141 ps
CPU time 172.2 seconds
Started Aug 07 05:37:15 PM PDT 24
Finished Aug 07 05:40:08 PM PDT 24
Peak memory 183420 kb
Host smart-936766fa-faed-496d-9b27-86fcd0559271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841689695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.3841689695
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.2909712507
Short name T163
Test name
Test status
Simulation time 495614040429 ps
CPU time 268.01 seconds
Started Aug 07 05:37:14 PM PDT 24
Finished Aug 07 05:41:43 PM PDT 24
Peak memory 191620 kb
Host smart-2d43a122-7082-4834-8149-d86951806de0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909712507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.2909712507
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.1912803966
Short name T48
Test name
Test status
Simulation time 177435472528 ps
CPU time 62.42 seconds
Started Aug 07 05:37:16 PM PDT 24
Finished Aug 07 05:38:19 PM PDT 24
Peak memory 194752 kb
Host smart-4bf54875-4cd8-442c-9cda-3a8bd2b87e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912803966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.1912803966
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.471850671
Short name T369
Test name
Test status
Simulation time 74394100242 ps
CPU time 68.48 seconds
Started Aug 07 05:37:17 PM PDT 24
Finished Aug 07 05:38:25 PM PDT 24
Peak memory 183364 kb
Host smart-1b913690-ccce-49f2-98a7-c05ff542710e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471850671 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all.
471850671
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.4226396680
Short name T159
Test name
Test status
Simulation time 1022912331 ps
CPU time 2.1 seconds
Started Aug 07 05:37:16 PM PDT 24
Finished Aug 07 05:37:18 PM PDT 24
Peak memory 183116 kb
Host smart-2f91477c-4e13-4bab-b002-56394aadb783
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226396680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.4226396680
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.301950355
Short name T84
Test name
Test status
Simulation time 178311402912 ps
CPU time 127.01 seconds
Started Aug 07 05:37:16 PM PDT 24
Finished Aug 07 05:39:23 PM PDT 24
Peak memory 183384 kb
Host smart-d0740bbe-4b66-4be4-8d31-c7f68fe70fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301950355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.301950355
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.3350091829
Short name T265
Test name
Test status
Simulation time 807135589695 ps
CPU time 478.62 seconds
Started Aug 07 05:37:14 PM PDT 24
Finished Aug 07 05:45:13 PM PDT 24
Peak memory 191524 kb
Host smart-5503f67e-beb5-423f-ad6c-fda5d3252ef3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350091829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.3350091829
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.2205493828
Short name T294
Test name
Test status
Simulation time 67484666905 ps
CPU time 47.51 seconds
Started Aug 07 05:37:22 PM PDT 24
Finished Aug 07 05:38:10 PM PDT 24
Peak memory 191596 kb
Host smart-943f27cc-84ab-497c-8e61-342d368bd9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205493828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.2205493828
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.2634297756
Short name T428
Test name
Test status
Simulation time 23277145 ps
CPU time 0.56 seconds
Started Aug 07 05:37:22 PM PDT 24
Finished Aug 07 05:37:23 PM PDT 24
Peak memory 183112 kb
Host smart-402be9de-17e3-4b30-9a0d-5810d999f344
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634297756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.2634297756
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.3719452580
Short name T130
Test name
Test status
Simulation time 7623135922 ps
CPU time 8.06 seconds
Started Aug 07 05:37:22 PM PDT 24
Finished Aug 07 05:37:30 PM PDT 24
Peak memory 183352 kb
Host smart-e65d37c9-24a1-44a7-9b6d-8568af775927
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719452580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.3719452580
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.1884542232
Short name T22
Test name
Test status
Simulation time 72127183526 ps
CPU time 115.91 seconds
Started Aug 07 05:37:24 PM PDT 24
Finished Aug 07 05:39:20 PM PDT 24
Peak memory 183384 kb
Host smart-9624fc59-38d0-43e6-94ab-96e6056b41ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884542232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.1884542232
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.2189373876
Short name T338
Test name
Test status
Simulation time 48190563280 ps
CPU time 75.82 seconds
Started Aug 07 05:37:22 PM PDT 24
Finished Aug 07 05:38:38 PM PDT 24
Peak memory 183420 kb
Host smart-9ef81f3c-4cf4-4b5d-8458-4190446d66f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189373876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.2189373876
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.619881752
Short name T300
Test name
Test status
Simulation time 33594429917 ps
CPU time 66.46 seconds
Started Aug 07 05:37:21 PM PDT 24
Finished Aug 07 05:38:27 PM PDT 24
Peak memory 191624 kb
Host smart-9d11c854-7c45-4dd6-b949-6a9f147cee24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619881752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.619881752
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.3920868237
Short name T348
Test name
Test status
Simulation time 309127811251 ps
CPU time 322.59 seconds
Started Aug 07 05:37:23 PM PDT 24
Finished Aug 07 05:42:46 PM PDT 24
Peak memory 191608 kb
Host smart-516b7da4-68a4-4015-b553-3abe326fd0f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920868237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.3920868237
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.2045723832
Short name T328
Test name
Test status
Simulation time 1420266835695 ps
CPU time 724.45 seconds
Started Aug 07 05:37:23 PM PDT 24
Finished Aug 07 05:49:28 PM PDT 24
Peak memory 183404 kb
Host smart-63602f29-44f4-4279-b951-7bdaf493c79f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045723832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.2045723832
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.2608751112
Short name T397
Test name
Test status
Simulation time 30369479407 ps
CPU time 12.1 seconds
Started Aug 07 05:37:21 PM PDT 24
Finished Aug 07 05:37:33 PM PDT 24
Peak memory 183444 kb
Host smart-46e5cd37-870d-47ac-a7d9-1de47db1dbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608751112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.2608751112
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.1842449317
Short name T219
Test name
Test status
Simulation time 1107124422326 ps
CPU time 218.02 seconds
Started Aug 07 05:37:23 PM PDT 24
Finished Aug 07 05:41:01 PM PDT 24
Peak memory 191636 kb
Host smart-98a31e61-23ef-4c6d-9789-fbd924e9fdbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842449317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.1842449317
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.2435778413
Short name T318
Test name
Test status
Simulation time 24532825671 ps
CPU time 34.51 seconds
Started Aug 07 05:37:19 PM PDT 24
Finished Aug 07 05:37:54 PM PDT 24
Peak memory 183232 kb
Host smart-2b946ad7-0131-4d04-96ed-3b34f203ea3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435778413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.2435778413
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.3227496317
Short name T311
Test name
Test status
Simulation time 46053924317 ps
CPU time 40.7 seconds
Started Aug 07 05:37:23 PM PDT 24
Finished Aug 07 05:38:04 PM PDT 24
Peak memory 183432 kb
Host smart-433675d6-faac-428a-8fa8-b74ad2772c2d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227496317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.3227496317
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.2849775254
Short name T356
Test name
Test status
Simulation time 862998902269 ps
CPU time 259.52 seconds
Started Aug 07 05:37:21 PM PDT 24
Finished Aug 07 05:41:41 PM PDT 24
Peak memory 183352 kb
Host smart-7a5ceb7c-8da0-43ea-9462-982248ef7a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849775254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.2849775254
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.2564183968
Short name T230
Test name
Test status
Simulation time 44475219543 ps
CPU time 67.02 seconds
Started Aug 07 05:37:20 PM PDT 24
Finished Aug 07 05:38:27 PM PDT 24
Peak memory 183396 kb
Host smart-420e4579-7ff1-4b2e-ad38-45d57a94d601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564183968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.2564183968
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.398398719
Short name T63
Test name
Test status
Simulation time 512738518961 ps
CPU time 396.7 seconds
Started Aug 07 05:37:23 PM PDT 24
Finished Aug 07 05:44:00 PM PDT 24
Peak memory 191628 kb
Host smart-4f644f4c-56f6-42e0-a744-5e52ca5d8c49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398398719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all.
398398719
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all_with_rand_reset.2751536848
Short name T97
Test name
Test status
Simulation time 134508358555 ps
CPU time 540.15 seconds
Started Aug 07 05:37:21 PM PDT 24
Finished Aug 07 05:46:21 PM PDT 24
Peak memory 198032 kb
Host smart-8e4b7ef8-6543-4577-8f0d-32b97259f90c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751536848 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all_with_rand_reset.2751536848
Directory /workspace/34.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.934401982
Short name T124
Test name
Test status
Simulation time 207470080583 ps
CPU time 48 seconds
Started Aug 07 05:37:22 PM PDT 24
Finished Aug 07 05:38:10 PM PDT 24
Peak memory 183348 kb
Host smart-2db2e04b-feb4-4024-a796-cf19e741efd0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934401982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.rv_timer_cfg_update_on_fly.934401982
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.2958669611
Short name T90
Test name
Test status
Simulation time 109691840119 ps
CPU time 70.84 seconds
Started Aug 07 05:37:23 PM PDT 24
Finished Aug 07 05:38:34 PM PDT 24
Peak memory 183396 kb
Host smart-b3afbc03-e6c6-4f48-b7ac-53c607e86bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958669611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.2958669611
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.3080573752
Short name T103
Test name
Test status
Simulation time 114106494882 ps
CPU time 1651.46 seconds
Started Aug 07 05:37:23 PM PDT 24
Finished Aug 07 06:04:54 PM PDT 24
Peak memory 191616 kb
Host smart-0b007935-2d1d-41de-affe-5a939e46e42d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080573752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.3080573752
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.1095082745
Short name T419
Test name
Test status
Simulation time 93648421 ps
CPU time 3.11 seconds
Started Aug 07 05:37:22 PM PDT 24
Finished Aug 07 05:37:25 PM PDT 24
Peak memory 183336 kb
Host smart-d12b78c4-c2e3-44d2-bfeb-1bee3174ea3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095082745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.1095082745
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all_with_rand_reset.821520125
Short name T41
Test name
Test status
Simulation time 28247742276 ps
CPU time 287.87 seconds
Started Aug 07 05:37:22 PM PDT 24
Finished Aug 07 05:42:10 PM PDT 24
Peak memory 198112 kb
Host smart-0164a1d8-b3a0-4995-8ed4-1ed93ceb7e4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821520125 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all_with_rand_reset.821520125
Directory /workspace/35.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.385713593
Short name T353
Test name
Test status
Simulation time 785486982253 ps
CPU time 162.46 seconds
Started Aug 07 05:37:23 PM PDT 24
Finished Aug 07 05:40:05 PM PDT 24
Peak memory 183404 kb
Host smart-fc3ca4db-847a-48cf-9299-33348fbff4c6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385713593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.rv_timer_cfg_update_on_fly.385713593
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.1819528669
Short name T396
Test name
Test status
Simulation time 199919458396 ps
CPU time 86.31 seconds
Started Aug 07 05:37:21 PM PDT 24
Finished Aug 07 05:38:48 PM PDT 24
Peak memory 183320 kb
Host smart-6e827f44-926f-4492-b2e8-acf869a24729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819528669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.1819528669
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.2168640944
Short name T121
Test name
Test status
Simulation time 152985084731 ps
CPU time 663.54 seconds
Started Aug 07 05:37:21 PM PDT 24
Finished Aug 07 05:48:25 PM PDT 24
Peak memory 191552 kb
Host smart-f8b512bb-5d34-4a8c-afe3-c3cbb8805842
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168640944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.2168640944
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.2883262937
Short name T13
Test name
Test status
Simulation time 3647215857 ps
CPU time 4.28 seconds
Started Aug 07 05:37:24 PM PDT 24
Finished Aug 07 05:37:29 PM PDT 24
Peak memory 192484 kb
Host smart-2f7b657c-8aea-4b3c-9e36-3d536ea0776b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883262937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.2883262937
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.2544806859
Short name T168
Test name
Test status
Simulation time 288139160461 ps
CPU time 410.15 seconds
Started Aug 07 05:37:28 PM PDT 24
Finished Aug 07 05:44:18 PM PDT 24
Peak memory 183436 kb
Host smart-6e3e0b52-c7f5-495e-961c-85ba542d0a32
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544806859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.2544806859
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.1077252343
Short name T357
Test name
Test status
Simulation time 181516964981 ps
CPU time 137.82 seconds
Started Aug 07 05:37:27 PM PDT 24
Finished Aug 07 05:39:45 PM PDT 24
Peak memory 183428 kb
Host smart-7f8980ac-4549-482d-aece-29bf9eaa9006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077252343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.1077252343
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.1190935500
Short name T426
Test name
Test status
Simulation time 77654209849 ps
CPU time 41.21 seconds
Started Aug 07 05:37:22 PM PDT 24
Finished Aug 07 05:38:03 PM PDT 24
Peak memory 183352 kb
Host smart-a4021c66-0e8c-4fd0-b133-8069e666eb19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190935500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.1190935500
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.395898640
Short name T350
Test name
Test status
Simulation time 37446818155 ps
CPU time 44.96 seconds
Started Aug 07 05:37:25 PM PDT 24
Finished Aug 07 05:38:10 PM PDT 24
Peak memory 183408 kb
Host smart-01c93aa6-42ac-4a7c-a089-9d1f01557252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395898640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.395898640
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.1232098959
Short name T57
Test name
Test status
Simulation time 1961353683106 ps
CPU time 1588.86 seconds
Started Aug 07 05:37:26 PM PDT 24
Finished Aug 07 06:03:55 PM PDT 24
Peak memory 196176 kb
Host smart-0531e61b-c42c-4ad7-aecb-b1e062668211
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232098959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.1232098959
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.47915486
Short name T86
Test name
Test status
Simulation time 75697368053 ps
CPU time 123.59 seconds
Started Aug 07 05:37:28 PM PDT 24
Finished Aug 07 05:39:32 PM PDT 24
Peak memory 183392 kb
Host smart-45379fe9-86f9-4053-8ba5-eaddef41f32a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47915486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.rv_timer_cfg_update_on_fly.47915486
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.3332217785
Short name T365
Test name
Test status
Simulation time 191388569543 ps
CPU time 153.98 seconds
Started Aug 07 05:37:26 PM PDT 24
Finished Aug 07 05:40:01 PM PDT 24
Peak memory 183420 kb
Host smart-15196a04-5195-4a4c-8991-70851afe103a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332217785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.3332217785
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.3433419317
Short name T401
Test name
Test status
Simulation time 81604280479 ps
CPU time 291.49 seconds
Started Aug 07 05:37:27 PM PDT 24
Finished Aug 07 05:42:18 PM PDT 24
Peak memory 191660 kb
Host smart-29c1b572-c5ff-4acf-bbb4-3fa79114ad54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433419317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.3433419317
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.4124197495
Short name T414
Test name
Test status
Simulation time 50640056 ps
CPU time 0.52 seconds
Started Aug 07 05:37:26 PM PDT 24
Finished Aug 07 05:37:26 PM PDT 24
Peak memory 183216 kb
Host smart-49147e4c-8506-4d31-96e1-7f480320bf6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124197495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.4124197495
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.2148849389
Short name T113
Test name
Test status
Simulation time 463912731415 ps
CPU time 428.21 seconds
Started Aug 07 05:37:26 PM PDT 24
Finished Aug 07 05:44:35 PM PDT 24
Peak memory 191860 kb
Host smart-4258c2ea-0490-42fd-a234-3c15310f4659
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148849389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.2148849389
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.2194847928
Short name T69
Test name
Test status
Simulation time 74082558208 ps
CPU time 115.28 seconds
Started Aug 07 05:37:26 PM PDT 24
Finished Aug 07 05:39:21 PM PDT 24
Peak memory 183384 kb
Host smart-53c1cd2c-75dc-4ecc-bb70-87fd3dc91893
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194847928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.2194847928
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.3980756221
Short name T417
Test name
Test status
Simulation time 516894139629 ps
CPU time 226.42 seconds
Started Aug 07 05:40:33 PM PDT 24
Finished Aug 07 05:44:20 PM PDT 24
Peak memory 183400 kb
Host smart-e9e1843f-e91f-4612-b1c3-f34c1e6a51af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980756221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.3980756221
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.4259041733
Short name T345
Test name
Test status
Simulation time 43338354169 ps
CPU time 74.96 seconds
Started Aug 07 05:37:27 PM PDT 24
Finished Aug 07 05:38:42 PM PDT 24
Peak memory 183480 kb
Host smart-75f80a3e-aa38-4118-9a98-16dcb2ddde8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259041733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.4259041733
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.1301653438
Short name T46
Test name
Test status
Simulation time 193371288 ps
CPU time 2.09 seconds
Started Aug 07 05:37:27 PM PDT 24
Finished Aug 07 05:37:29 PM PDT 24
Peak memory 191596 kb
Host smart-aaadc84b-8221-414f-a623-3b5316c4b6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301653438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.1301653438
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.1238603708
Short name T444
Test name
Test status
Simulation time 1079675566247 ps
CPU time 379.1 seconds
Started Aug 07 05:40:32 PM PDT 24
Finished Aug 07 05:46:52 PM PDT 24
Peak memory 191588 kb
Host smart-bea01e2c-a949-4bb2-8f98-b6775bef5f32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238603708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.1238603708
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.1176298668
Short name T177
Test name
Test status
Simulation time 303547285977 ps
CPU time 283.04 seconds
Started Aug 07 05:36:45 PM PDT 24
Finished Aug 07 05:41:28 PM PDT 24
Peak memory 183384 kb
Host smart-fe94a8d2-d6d9-4993-ac59-60397f55b879
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176298668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.1176298668
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.838352287
Short name T376
Test name
Test status
Simulation time 201665813583 ps
CPU time 282.65 seconds
Started Aug 07 05:36:47 PM PDT 24
Finished Aug 07 05:41:30 PM PDT 24
Peak memory 183436 kb
Host smart-ed250e2e-a76c-4348-b617-b33cabbc10bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838352287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.838352287
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.2487673093
Short name T145
Test name
Test status
Simulation time 184998099441 ps
CPU time 300.35 seconds
Started Aug 07 05:36:49 PM PDT 24
Finished Aug 07 05:41:49 PM PDT 24
Peak memory 191632 kb
Host smart-c3b68e7f-7ea4-4e4b-958a-90ed1608665d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487673093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.2487673093
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.211598681
Short name T362
Test name
Test status
Simulation time 367892503 ps
CPU time 1.02 seconds
Started Aug 07 05:36:52 PM PDT 24
Finished Aug 07 05:36:53 PM PDT 24
Peak memory 183072 kb
Host smart-57729aaa-d916-42be-8751-d26734004a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211598681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.211598681
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.2159203147
Short name T20
Test name
Test status
Simulation time 270638349 ps
CPU time 0.84 seconds
Started Aug 07 05:36:52 PM PDT 24
Finished Aug 07 05:36:53 PM PDT 24
Peak memory 213920 kb
Host smart-ff914505-1cdf-4fc2-88cc-c9d5c8c57a15
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159203147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.2159203147
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.701291663
Short name T136
Test name
Test status
Simulation time 2737397788618 ps
CPU time 1638.13 seconds
Started Aug 07 05:36:50 PM PDT 24
Finished Aug 07 06:04:08 PM PDT 24
Peak memory 191672 kb
Host smart-888e54ad-2770-404a-aad4-29bf0bc05b95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701291663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.701291663
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all_with_rand_reset.1373248851
Short name T96
Test name
Test status
Simulation time 105136459538 ps
CPU time 600.61 seconds
Started Aug 07 05:36:51 PM PDT 24
Finished Aug 07 05:46:52 PM PDT 24
Peak memory 206272 kb
Host smart-66550242-cf5c-46db-a516-be823dcdd28e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373248851 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all_with_rand_reset.1373248851
Directory /workspace/4.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.1241265394
Short name T234
Test name
Test status
Simulation time 1094846757429 ps
CPU time 876.91 seconds
Started Aug 07 05:37:34 PM PDT 24
Finished Aug 07 05:52:11 PM PDT 24
Peak memory 183396 kb
Host smart-f375ae91-e48c-46d9-96c3-7e62bb4e279b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241265394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.1241265394
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.2205301454
Short name T392
Test name
Test status
Simulation time 1143287294 ps
CPU time 1.35 seconds
Started Aug 07 05:37:33 PM PDT 24
Finished Aug 07 05:37:35 PM PDT 24
Peak memory 183172 kb
Host smart-4d9fd9a8-912e-412b-be2f-9a3ee32159ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205301454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.2205301454
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.4073165233
Short name T85
Test name
Test status
Simulation time 192332124782 ps
CPU time 1300.05 seconds
Started Aug 07 05:37:35 PM PDT 24
Finished Aug 07 05:59:16 PM PDT 24
Peak memory 191632 kb
Host smart-ccf6b312-f996-4e10-9396-502fa0f1c932
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073165233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.4073165233
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.3791303174
Short name T249
Test name
Test status
Simulation time 160608109778 ps
CPU time 61.08 seconds
Started Aug 07 05:37:32 PM PDT 24
Finished Aug 07 05:38:33 PM PDT 24
Peak memory 191560 kb
Host smart-3c76df18-071a-4cdd-963c-1d30e72ef9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791303174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.3791303174
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.132598444
Short name T341
Test name
Test status
Simulation time 391778156720 ps
CPU time 369.64 seconds
Started Aug 07 05:37:35 PM PDT 24
Finished Aug 07 05:43:44 PM PDT 24
Peak memory 183392 kb
Host smart-8acec6d4-905a-4bcd-b213-bb5f1881c71a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132598444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.rv_timer_cfg_update_on_fly.132598444
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.298499097
Short name T381
Test name
Test status
Simulation time 874175598241 ps
CPU time 177.32 seconds
Started Aug 07 05:37:34 PM PDT 24
Finished Aug 07 05:40:31 PM PDT 24
Peak memory 183344 kb
Host smart-702f0cb1-796c-4003-8bd5-883dcd78e858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298499097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.298499097
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.1291375065
Short name T228
Test name
Test status
Simulation time 83715006853 ps
CPU time 432.64 seconds
Started Aug 07 05:37:33 PM PDT 24
Finished Aug 07 05:44:46 PM PDT 24
Peak memory 191680 kb
Host smart-8d09dade-97df-4eca-8af5-538ba81c3ebc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291375065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.1291375065
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.3220975845
Short name T366
Test name
Test status
Simulation time 943897986 ps
CPU time 3.56 seconds
Started Aug 07 05:37:34 PM PDT 24
Finished Aug 07 05:37:37 PM PDT 24
Peak memory 194156 kb
Host smart-fea3f84e-1afd-47af-a1c4-20042580f5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220975845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.3220975845
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.4015117493
Short name T153
Test name
Test status
Simulation time 1169795598876 ps
CPU time 875.76 seconds
Started Aug 07 05:37:39 PM PDT 24
Finished Aug 07 05:52:15 PM PDT 24
Peak memory 196344 kb
Host smart-bd84417e-593f-4577-8177-5c6376086e29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015117493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.4015117493
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.1052099797
Short name T111
Test name
Test status
Simulation time 550178201002 ps
CPU time 304.45 seconds
Started Aug 07 05:37:44 PM PDT 24
Finished Aug 07 05:42:48 PM PDT 24
Peak memory 183408 kb
Host smart-fe72cd5f-9c05-447a-b3b2-6eb5fd59de34
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052099797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.1052099797
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.3891174245
Short name T406
Test name
Test status
Simulation time 645834676772 ps
CPU time 236.57 seconds
Started Aug 07 05:37:40 PM PDT 24
Finished Aug 07 05:41:36 PM PDT 24
Peak memory 183428 kb
Host smart-ceb3ee1f-3c7a-4b03-a469-54dfb5bad209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891174245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.3891174245
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.476953594
Short name T148
Test name
Test status
Simulation time 79637807439 ps
CPU time 71.17 seconds
Started Aug 07 05:37:39 PM PDT 24
Finished Aug 07 05:38:50 PM PDT 24
Peak memory 183476 kb
Host smart-ecc6ef8d-82fa-43a4-b53b-43fdc7be4f53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476953594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.476953594
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.1659323575
Short name T271
Test name
Test status
Simulation time 32805524144 ps
CPU time 16.35 seconds
Started Aug 07 05:37:44 PM PDT 24
Finished Aug 07 05:38:00 PM PDT 24
Peak memory 191552 kb
Host smart-1d3637af-8f02-4387-8ff8-473824932723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659323575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.1659323575
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.3720679619
Short name T59
Test name
Test status
Simulation time 1494068332238 ps
CPU time 656.86 seconds
Started Aug 07 05:37:44 PM PDT 24
Finished Aug 07 05:48:41 PM PDT 24
Peak memory 191608 kb
Host smart-2bb3c2a0-5e6e-44b6-9784-2deec2c6b2e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720679619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.3720679619
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.3017256024
Short name T156
Test name
Test status
Simulation time 356206658085 ps
CPU time 307.21 seconds
Started Aug 07 05:37:51 PM PDT 24
Finished Aug 07 05:42:58 PM PDT 24
Peak memory 183348 kb
Host smart-2cf7b0d1-0e5b-4c22-bbe7-6a3bda6cd818
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017256024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.3017256024
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.990304055
Short name T363
Test name
Test status
Simulation time 99437731743 ps
CPU time 142.02 seconds
Started Aug 07 05:37:47 PM PDT 24
Finished Aug 07 05:40:09 PM PDT 24
Peak memory 183392 kb
Host smart-c57dc47a-81f5-4950-8d6e-82ae0e62f8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990304055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.990304055
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.3101555773
Short name T67
Test name
Test status
Simulation time 375862983467 ps
CPU time 560.77 seconds
Started Aug 07 05:37:47 PM PDT 24
Finished Aug 07 05:47:08 PM PDT 24
Peak memory 191608 kb
Host smart-68a12ff4-10fc-411d-97e7-1e923a350f75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101555773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.3101555773
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.936425042
Short name T25
Test name
Test status
Simulation time 755499907 ps
CPU time 2.28 seconds
Started Aug 07 05:37:52 PM PDT 24
Finished Aug 07 05:37:54 PM PDT 24
Peak memory 183284 kb
Host smart-51dc94c2-dfa7-4971-939e-e89d45bb5df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936425042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.936425042
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.2273628414
Short name T344
Test name
Test status
Simulation time 16429404415 ps
CPU time 8.81 seconds
Started Aug 07 05:37:51 PM PDT 24
Finished Aug 07 05:38:00 PM PDT 24
Peak memory 183352 kb
Host smart-27884976-f2af-400f-9c3a-c1f7bc5d5825
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273628414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.2273628414
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.1760989270
Short name T49
Test name
Test status
Simulation time 143927812072 ps
CPU time 198.46 seconds
Started Aug 07 05:37:53 PM PDT 24
Finished Aug 07 05:41:12 PM PDT 24
Peak memory 183404 kb
Host smart-6820663a-2a1e-4061-8408-d1b9cea4f7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760989270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.1760989270
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.1433304422
Short name T199
Test name
Test status
Simulation time 585497147003 ps
CPU time 299.95 seconds
Started Aug 07 05:37:51 PM PDT 24
Finished Aug 07 05:42:51 PM PDT 24
Peak memory 191548 kb
Host smart-bb2b97bb-9a01-4751-94b6-aabc87047835
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433304422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.1433304422
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.2677905346
Short name T383
Test name
Test status
Simulation time 289788944 ps
CPU time 0.69 seconds
Started Aug 07 05:38:09 PM PDT 24
Finished Aug 07 05:38:09 PM PDT 24
Peak memory 183180 kb
Host smart-2d82662e-4ca7-4bb4-a340-d8f4d1f093d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677905346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.2677905346
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.2474706649
Short name T190
Test name
Test status
Simulation time 644749938369 ps
CPU time 317.13 seconds
Started Aug 07 05:37:55 PM PDT 24
Finished Aug 07 05:43:12 PM PDT 24
Peak memory 191600 kb
Host smart-9b3066ab-98ca-402b-9835-10a0035c86af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474706649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.2474706649
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.834095370
Short name T349
Test name
Test status
Simulation time 4918921449 ps
CPU time 9.47 seconds
Started Aug 07 05:38:03 PM PDT 24
Finished Aug 07 05:38:13 PM PDT 24
Peak memory 183368 kb
Host smart-105b35e8-244a-4cc0-be4d-e1ea051362b2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834095370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.rv_timer_cfg_update_on_fly.834095370
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.1733709156
Short name T400
Test name
Test status
Simulation time 80610039376 ps
CPU time 62.74 seconds
Started Aug 07 05:37:56 PM PDT 24
Finished Aug 07 05:38:59 PM PDT 24
Peak memory 183364 kb
Host smart-5a4cf494-d6ec-45cd-a966-0c0de1906a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733709156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.1733709156
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.3743114216
Short name T184
Test name
Test status
Simulation time 145999446210 ps
CPU time 286.29 seconds
Started Aug 07 05:37:58 PM PDT 24
Finished Aug 07 05:42:45 PM PDT 24
Peak memory 191612 kb
Host smart-4828ace7-0dac-4f04-889d-c5f70403f39a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743114216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.3743114216
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.4037960620
Short name T431
Test name
Test status
Simulation time 37357441441 ps
CPU time 64.09 seconds
Started Aug 07 05:38:04 PM PDT 24
Finished Aug 07 05:39:08 PM PDT 24
Peak memory 183452 kb
Host smart-49e080bd-3534-4fa8-b164-c4980cd31f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037960620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.4037960620
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.3553598123
Short name T389
Test name
Test status
Simulation time 369218806286 ps
CPU time 147.4 seconds
Started Aug 07 05:38:03 PM PDT 24
Finished Aug 07 05:40:30 PM PDT 24
Peak memory 195216 kb
Host smart-d0e61faf-3ff1-4d69-a81a-7c5088605b0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553598123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.3553598123
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.920186097
Short name T255
Test name
Test status
Simulation time 170703551530 ps
CPU time 165.88 seconds
Started Aug 07 05:38:05 PM PDT 24
Finished Aug 07 05:40:51 PM PDT 24
Peak memory 183444 kb
Host smart-f9bcf842-9f2a-4f89-a7c4-bb7b2e1988d2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920186097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.rv_timer_cfg_update_on_fly.920186097
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.3582625140
Short name T1
Test name
Test status
Simulation time 96104315066 ps
CPU time 124.25 seconds
Started Aug 07 05:38:04 PM PDT 24
Finished Aug 07 05:40:08 PM PDT 24
Peak memory 183424 kb
Host smart-4cf7e8e2-7b9e-43a6-8d31-68adcdd621a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582625140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.3582625140
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.3873359166
Short name T260
Test name
Test status
Simulation time 36558384217 ps
CPU time 58.11 seconds
Started Aug 07 05:38:04 PM PDT 24
Finished Aug 07 05:39:02 PM PDT 24
Peak memory 191668 kb
Host smart-14b1bcc8-fca4-4cc5-bb6a-03edae88fa76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873359166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.3873359166
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.2204061740
Short name T336
Test name
Test status
Simulation time 86266093806 ps
CPU time 66.76 seconds
Started Aug 07 05:38:06 PM PDT 24
Finished Aug 07 05:39:13 PM PDT 24
Peak memory 193472 kb
Host smart-0faf0b20-3330-492e-9d6c-9f49927e78c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204061740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.2204061740
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.3122478552
Short name T169
Test name
Test status
Simulation time 31680438671 ps
CPU time 50.83 seconds
Started Aug 07 05:38:09 PM PDT 24
Finished Aug 07 05:39:00 PM PDT 24
Peak memory 183324 kb
Host smart-03fd0500-036a-45b1-8f25-0934880737a5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122478552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.3122478552
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_random.1172541292
Short name T70
Test name
Test status
Simulation time 79983830562 ps
CPU time 1067.44 seconds
Started Aug 07 05:38:09 PM PDT 24
Finished Aug 07 05:55:57 PM PDT 24
Peak memory 191648 kb
Host smart-8fdfdb1f-acf4-47dd-8735-20b3a9b3436e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172541292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.1172541292
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.244065009
Short name T314
Test name
Test status
Simulation time 107708661371 ps
CPU time 43.14 seconds
Started Aug 07 05:38:09 PM PDT 24
Finished Aug 07 05:38:52 PM PDT 24
Peak memory 194732 kb
Host smart-67909563-8a97-4a5d-9c4d-84ac80f9b2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244065009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.244065009
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.543360094
Short name T281
Test name
Test status
Simulation time 707792862461 ps
CPU time 705.65 seconds
Started Aug 07 05:38:10 PM PDT 24
Finished Aug 07 05:49:56 PM PDT 24
Peak memory 183432 kb
Host smart-0d8718be-ed82-4e49-8a1f-77d97cc95f40
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543360094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.rv_timer_cfg_update_on_fly.543360094
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.1388254543
Short name T390
Test name
Test status
Simulation time 296080444333 ps
CPU time 197.9 seconds
Started Aug 07 05:38:08 PM PDT 24
Finished Aug 07 05:41:26 PM PDT 24
Peak memory 183400 kb
Host smart-01bcf649-f6b0-43c4-bab5-ac0fa25cf1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388254543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.1388254543
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.1351856455
Short name T250
Test name
Test status
Simulation time 25275570602 ps
CPU time 456.13 seconds
Started Aug 07 05:38:09 PM PDT 24
Finished Aug 07 05:45:45 PM PDT 24
Peak memory 183348 kb
Host smart-cc40f29b-4f09-456f-8699-cce85505c54f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351856455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.1351856455
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.2564643178
Short name T413
Test name
Test status
Simulation time 193620525 ps
CPU time 1.52 seconds
Started Aug 07 05:38:09 PM PDT 24
Finished Aug 07 05:38:11 PM PDT 24
Peak memory 183356 kb
Host smart-5d6cdcaa-8afa-4848-967b-6bd858dfb10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564643178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.2564643178
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all_with_rand_reset.3129617526
Short name T42
Test name
Test status
Simulation time 57448977353 ps
CPU time 405.49 seconds
Started Aug 07 05:38:09 PM PDT 24
Finished Aug 07 05:44:55 PM PDT 24
Peak memory 206408 kb
Host smart-f1e23e14-df2f-48e6-8770-6fe8aa5ec8a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129617526 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all_with_rand_reset.3129617526
Directory /workspace/48.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.398509714
Short name T433
Test name
Test status
Simulation time 188697286484 ps
CPU time 138.06 seconds
Started Aug 07 05:40:32 PM PDT 24
Finished Aug 07 05:42:50 PM PDT 24
Peak memory 183460 kb
Host smart-d6486532-4114-45e4-9f95-548f7022b8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398509714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.398509714
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.152616724
Short name T187
Test name
Test status
Simulation time 31503160947 ps
CPU time 45.42 seconds
Started Aug 07 05:38:31 PM PDT 24
Finished Aug 07 05:39:17 PM PDT 24
Peak memory 195164 kb
Host smart-1fe71286-1150-454e-885a-7b0bfc7b50ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152616724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.152616724
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.1644181844
Short name T422
Test name
Test status
Simulation time 46551394736 ps
CPU time 40.46 seconds
Started Aug 07 05:38:17 PM PDT 24
Finished Aug 07 05:38:57 PM PDT 24
Peak memory 183212 kb
Host smart-9b7c3ac5-2a83-482f-8642-5d0ff7888ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644181844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.1644181844
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.495193097
Short name T221
Test name
Test status
Simulation time 2449814522464 ps
CPU time 1462.96 seconds
Started Aug 07 05:38:19 PM PDT 24
Finished Aug 07 06:02:42 PM PDT 24
Peak memory 191572 kb
Host smart-2afda76b-94cf-4807-b18b-8418a36d6096
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495193097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all.
495193097
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.888086915
Short name T355
Test name
Test status
Simulation time 9854533319 ps
CPU time 5.29 seconds
Started Aug 07 05:36:54 PM PDT 24
Finished Aug 07 05:36:59 PM PDT 24
Peak memory 183420 kb
Host smart-8b9bd199-b031-4138-a5f4-002437f11c30
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888086915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.rv_timer_cfg_update_on_fly.888086915
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.1251602077
Short name T379
Test name
Test status
Simulation time 674862860685 ps
CPU time 262.33 seconds
Started Aug 07 05:36:52 PM PDT 24
Finished Aug 07 05:41:15 PM PDT 24
Peak memory 183420 kb
Host smart-e1edcc16-ace1-49ff-8919-c2ee191d1f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251602077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.1251602077
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.1226231202
Short name T333
Test name
Test status
Simulation time 265720114218 ps
CPU time 83.08 seconds
Started Aug 07 05:36:53 PM PDT 24
Finished Aug 07 05:38:16 PM PDT 24
Peak memory 191660 kb
Host smart-84979a57-37c3-4748-b177-19a68abf1aa3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226231202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.1226231202
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/50.rv_timer_random.3504903526
Short name T410
Test name
Test status
Simulation time 19238932115 ps
CPU time 83.51 seconds
Started Aug 07 05:40:30 PM PDT 24
Finished Aug 07 05:41:54 PM PDT 24
Peak memory 191648 kb
Host smart-2f9b9d33-e938-471c-a760-03d046d7d3ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504903526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.3504903526
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.3111062908
Short name T9
Test name
Test status
Simulation time 167019877038 ps
CPU time 80.87 seconds
Started Aug 07 05:38:15 PM PDT 24
Finished Aug 07 05:39:36 PM PDT 24
Peak memory 183356 kb
Host smart-38d5913d-2bf6-448a-afff-e47dcfe0351f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111062908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.3111062908
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.498879016
Short name T213
Test name
Test status
Simulation time 208440393086 ps
CPU time 248.39 seconds
Started Aug 07 05:38:15 PM PDT 24
Finished Aug 07 05:42:24 PM PDT 24
Peak memory 191656 kb
Host smart-8bb30788-6abc-4d72-a6bf-c60968e09b43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498879016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.498879016
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.4167923313
Short name T2
Test name
Test status
Simulation time 197608051916 ps
CPU time 251.48 seconds
Started Aug 07 05:38:19 PM PDT 24
Finished Aug 07 05:42:31 PM PDT 24
Peak memory 183416 kb
Host smart-92868918-f5b2-4773-aaac-da13fb2b215a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167923313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.4167923313
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.3186546084
Short name T112
Test name
Test status
Simulation time 174789260781 ps
CPU time 765.43 seconds
Started Aug 07 05:38:19 PM PDT 24
Finished Aug 07 05:51:04 PM PDT 24
Peak memory 191632 kb
Host smart-c424f099-1ad0-4f77-9c2a-09636c58aa93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186546084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.3186546084
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.4048779702
Short name T342
Test name
Test status
Simulation time 1050793769825 ps
CPU time 551.39 seconds
Started Aug 07 05:38:18 PM PDT 24
Finished Aug 07 05:47:30 PM PDT 24
Peak memory 191592 kb
Host smart-c329a43b-c8e6-4b2f-b1fc-7600e6817b36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048779702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.4048779702
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.1872704638
Short name T282
Test name
Test status
Simulation time 226301133650 ps
CPU time 266.76 seconds
Started Aug 07 05:38:22 PM PDT 24
Finished Aug 07 05:42:49 PM PDT 24
Peak memory 191600 kb
Host smart-8b921c35-e50b-40c8-a2c6-3f7d78ea5b63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872704638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.1872704638
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.1360237440
Short name T283
Test name
Test status
Simulation time 1906481565314 ps
CPU time 550.73 seconds
Started Aug 07 05:36:52 PM PDT 24
Finished Aug 07 05:46:03 PM PDT 24
Peak memory 183396 kb
Host smart-1f36eafd-c8f0-4f11-8ee5-6d212f835411
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360237440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.1360237440
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.4261629965
Short name T377
Test name
Test status
Simulation time 52626401226 ps
CPU time 73.54 seconds
Started Aug 07 05:36:56 PM PDT 24
Finished Aug 07 05:38:10 PM PDT 24
Peak memory 183664 kb
Host smart-2d6539f7-a93b-494f-9df2-f8034d323b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261629965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.4261629965
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.1021531973
Short name T254
Test name
Test status
Simulation time 134704251892 ps
CPU time 425.75 seconds
Started Aug 07 05:36:55 PM PDT 24
Finished Aug 07 05:44:00 PM PDT 24
Peak memory 191644 kb
Host smart-6d40aa74-9233-487f-bffa-75042562f90f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021531973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.1021531973
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.2241622214
Short name T278
Test name
Test status
Simulation time 326492972128 ps
CPU time 812.54 seconds
Started Aug 07 05:36:52 PM PDT 24
Finished Aug 07 05:50:25 PM PDT 24
Peak memory 195468 kb
Host smart-ddc9ab5a-8186-4cbe-b979-51a8c24e0530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241622214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.2241622214
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.3179967251
Short name T251
Test name
Test status
Simulation time 2546355958637 ps
CPU time 3066.4 seconds
Started Aug 07 05:36:50 PM PDT 24
Finished Aug 07 06:27:58 PM PDT 24
Peak memory 196076 kb
Host smart-95b5ba3f-5459-42bb-9aed-b25d65da331b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179967251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
3179967251
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/60.rv_timer_random.528991097
Short name T179
Test name
Test status
Simulation time 129355136800 ps
CPU time 865.62 seconds
Started Aug 07 05:38:21 PM PDT 24
Finished Aug 07 05:52:47 PM PDT 24
Peak memory 191584 kb
Host smart-e9dbd14d-f056-48ad-8123-f2a7fcf10629
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528991097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.528991097
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.929132020
Short name T415
Test name
Test status
Simulation time 71013117275 ps
CPU time 1210.86 seconds
Started Aug 07 05:40:34 PM PDT 24
Finished Aug 07 06:00:45 PM PDT 24
Peak memory 183480 kb
Host smart-a5584e93-a17b-40c3-bf0c-9a801a519073
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929132020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.929132020
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.466729566
Short name T229
Test name
Test status
Simulation time 211785234956 ps
CPU time 1293.84 seconds
Started Aug 07 05:38:26 PM PDT 24
Finished Aug 07 06:00:00 PM PDT 24
Peak memory 191644 kb
Host smart-1dac8c56-0931-42e0-87f3-ccbd45825869
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466729566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.466729566
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.3752146180
Short name T122
Test name
Test status
Simulation time 639036183423 ps
CPU time 1470.99 seconds
Started Aug 07 05:38:24 PM PDT 24
Finished Aug 07 06:02:56 PM PDT 24
Peak memory 191580 kb
Host smart-23c870c2-8b7d-4a69-b7a1-30fd87051bc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752146180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.3752146180
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.1522607761
Short name T207
Test name
Test status
Simulation time 115854746603 ps
CPU time 499.21 seconds
Started Aug 07 05:38:26 PM PDT 24
Finished Aug 07 05:46:46 PM PDT 24
Peak memory 191540 kb
Host smart-393467cc-29b0-4a70-b1ae-0d23aacdeff3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522607761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.1522607761
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.919622379
Short name T195
Test name
Test status
Simulation time 481000769902 ps
CPU time 555.79 seconds
Started Aug 07 05:38:26 PM PDT 24
Finished Aug 07 05:47:42 PM PDT 24
Peak memory 191640 kb
Host smart-ffa8d8cb-d178-4f9e-958b-3f78c74d72c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919622379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.919622379
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.3410917560
Short name T87
Test name
Test status
Simulation time 82006682179 ps
CPU time 59.41 seconds
Started Aug 07 05:38:27 PM PDT 24
Finished Aug 07 05:39:26 PM PDT 24
Peak memory 183448 kb
Host smart-bab23f08-d7d5-4864-925a-f393caea4874
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410917560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.3410917560
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.591498858
Short name T227
Test name
Test status
Simulation time 96748742748 ps
CPU time 182.89 seconds
Started Aug 07 05:38:32 PM PDT 24
Finished Aug 07 05:41:35 PM PDT 24
Peak memory 192676 kb
Host smart-a931ba9f-ec48-4b83-b7a5-bc4551bb8ddb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591498858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.591498858
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.634912125
Short name T337
Test name
Test status
Simulation time 611798535401 ps
CPU time 317.83 seconds
Started Aug 07 05:36:56 PM PDT 24
Finished Aug 07 05:42:14 PM PDT 24
Peak memory 183656 kb
Host smart-e39a37db-2d85-4c9e-ae73-902688d4d394
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634912125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.rv_timer_cfg_update_on_fly.634912125
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.4287684333
Short name T438
Test name
Test status
Simulation time 108145380334 ps
CPU time 123.27 seconds
Started Aug 07 05:36:52 PM PDT 24
Finished Aug 07 05:38:56 PM PDT 24
Peak memory 183396 kb
Host smart-0874e056-9a2d-447d-9288-ed29285614f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287684333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.4287684333
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.1502825428
Short name T178
Test name
Test status
Simulation time 124914791156 ps
CPU time 459.81 seconds
Started Aug 07 05:36:51 PM PDT 24
Finished Aug 07 05:44:31 PM PDT 24
Peak memory 191608 kb
Host smart-c2955cbb-6c29-44fd-8eaa-5fa5c1124c6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502825428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.1502825428
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.3643570539
Short name T238
Test name
Test status
Simulation time 264084123457 ps
CPU time 324.24 seconds
Started Aug 07 05:36:52 PM PDT 24
Finished Aug 07 05:42:17 PM PDT 24
Peak memory 191624 kb
Host smart-538a93ab-abdc-41ea-82c8-a7aeaee4b570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643570539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.3643570539
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.1319665576
Short name T117
Test name
Test status
Simulation time 170260187074 ps
CPU time 260.16 seconds
Started Aug 07 05:36:53 PM PDT 24
Finished Aug 07 05:41:13 PM PDT 24
Peak memory 191552 kb
Host smart-782b1d4a-7157-427e-aff5-0320b6240eb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319665576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
1319665576
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.1019228706
Short name T14
Test name
Test status
Simulation time 50261411718 ps
CPU time 186.11 seconds
Started Aug 07 05:36:53 PM PDT 24
Finished Aug 07 05:39:59 PM PDT 24
Peak memory 198128 kb
Host smart-552fea6a-4e6c-4e86-b151-a001a0e2ce09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019228706 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all_with_rand_reset.1019228706
Directory /workspace/7.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.3493393599
Short name T306
Test name
Test status
Simulation time 748662018243 ps
CPU time 560.89 seconds
Started Aug 07 05:38:31 PM PDT 24
Finished Aug 07 05:47:52 PM PDT 24
Peak memory 191616 kb
Host smart-4076c509-2b0d-42bf-99e6-b2cadacaa283
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493393599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.3493393599
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.1271253088
Short name T313
Test name
Test status
Simulation time 838781639968 ps
CPU time 246.59 seconds
Started Aug 07 05:38:32 PM PDT 24
Finished Aug 07 05:42:39 PM PDT 24
Peak memory 191596 kb
Host smart-0dc7afee-571a-42d8-b6de-9d1b5dcdf420
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271253088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.1271253088
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.2495607231
Short name T23
Test name
Test status
Simulation time 1448059965058 ps
CPU time 661.18 seconds
Started Aug 07 05:38:30 PM PDT 24
Finished Aug 07 05:49:31 PM PDT 24
Peak memory 191596 kb
Host smart-df6d5e01-4077-468b-a966-e472b2fea858
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495607231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.2495607231
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.3037129741
Short name T343
Test name
Test status
Simulation time 33794999065 ps
CPU time 692.75 seconds
Started Aug 07 05:38:31 PM PDT 24
Finished Aug 07 05:50:04 PM PDT 24
Peak memory 183388 kb
Host smart-16db9399-a8bc-457e-9b90-034703639f67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037129741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.3037129741
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.3311398420
Short name T102
Test name
Test status
Simulation time 384596753914 ps
CPU time 808.21 seconds
Started Aug 07 05:40:31 PM PDT 24
Finished Aug 07 05:54:00 PM PDT 24
Peak memory 191660 kb
Host smart-bcedaeb0-ecf9-4d85-89d6-f08bf106dffc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311398420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.3311398420
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.3592481761
Short name T211
Test name
Test status
Simulation time 1216269732024 ps
CPU time 318.68 seconds
Started Aug 07 05:38:38 PM PDT 24
Finished Aug 07 05:43:57 PM PDT 24
Peak memory 191568 kb
Host smart-54e978e5-a9c6-4a41-aa5b-e10b5be1bebf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592481761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.3592481761
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.2369249136
Short name T272
Test name
Test status
Simulation time 367157023154 ps
CPU time 652.85 seconds
Started Aug 07 05:40:36 PM PDT 24
Finished Aug 07 05:51:29 PM PDT 24
Peak memory 191684 kb
Host smart-194ee50d-2c2c-426c-ab29-6ea24a749511
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369249136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.2369249136
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.3350969498
Short name T68
Test name
Test status
Simulation time 216900368555 ps
CPU time 1779.57 seconds
Started Aug 07 05:38:37 PM PDT 24
Finished Aug 07 06:08:16 PM PDT 24
Peak memory 191592 kb
Host smart-0c7cd644-9e25-4898-81fc-4d3ed5cb87df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350969498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.3350969498
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.1696588253
Short name T273
Test name
Test status
Simulation time 26597754482 ps
CPU time 19.73 seconds
Started Aug 07 05:36:55 PM PDT 24
Finished Aug 07 05:37:14 PM PDT 24
Peak memory 183432 kb
Host smart-f7547b2e-0daf-4176-88f2-ad330da4d3a6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696588253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.1696588253
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.3651795709
Short name T367
Test name
Test status
Simulation time 321990260249 ps
CPU time 117.7 seconds
Started Aug 07 05:36:52 PM PDT 24
Finished Aug 07 05:38:50 PM PDT 24
Peak memory 183452 kb
Host smart-bc646747-9bb2-4eb2-9330-c92be26c515f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651795709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.3651795709
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.2740474780
Short name T253
Test name
Test status
Simulation time 95562139753 ps
CPU time 174.19 seconds
Started Aug 07 05:36:54 PM PDT 24
Finished Aug 07 05:39:48 PM PDT 24
Peak memory 191648 kb
Host smart-14e110ca-b6ab-4348-afcf-8fafbe203165
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740474780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.2740474780
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.3895384450
Short name T371
Test name
Test status
Simulation time 1247046367 ps
CPU time 1.41 seconds
Started Aug 07 05:36:52 PM PDT 24
Finished Aug 07 05:36:54 PM PDT 24
Peak memory 183152 kb
Host smart-74544535-81dc-4bd8-8f79-c4cbca0e8cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895384450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.3895384450
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.2754676779
Short name T101
Test name
Test status
Simulation time 408900633094 ps
CPU time 2272.95 seconds
Started Aug 07 05:38:35 PM PDT 24
Finished Aug 07 06:16:29 PM PDT 24
Peak memory 191572 kb
Host smart-b428282c-42eb-4dae-95b9-d6e3e829db0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754676779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.2754676779
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.2965590289
Short name T245
Test name
Test status
Simulation time 140306705337 ps
CPU time 509.37 seconds
Started Aug 07 05:38:37 PM PDT 24
Finished Aug 07 05:47:07 PM PDT 24
Peak memory 191608 kb
Host smart-e2ac1c89-3595-401b-a350-71b75890fdf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965590289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.2965590289
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.956973472
Short name T193
Test name
Test status
Simulation time 123639743957 ps
CPU time 212.49 seconds
Started Aug 07 05:38:35 PM PDT 24
Finished Aug 07 05:42:08 PM PDT 24
Peak memory 191620 kb
Host smart-c805774f-3267-40e8-a9a0-001af6331da8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956973472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.956973472
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.820381032
Short name T286
Test name
Test status
Simulation time 175449252228 ps
CPU time 140.45 seconds
Started Aug 07 05:38:35 PM PDT 24
Finished Aug 07 05:40:55 PM PDT 24
Peak memory 191644 kb
Host smart-e8cb8a64-2b2f-46b1-9b80-769df1486efa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820381032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.820381032
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.3523964210
Short name T165
Test name
Test status
Simulation time 195006190098 ps
CPU time 166.66 seconds
Started Aug 07 05:38:44 PM PDT 24
Finished Aug 07 05:41:31 PM PDT 24
Peak memory 191604 kb
Host smart-7d3263ff-6aba-4384-ba42-8048ceaf2481
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523964210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.3523964210
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.3460664870
Short name T162
Test name
Test status
Simulation time 244234058485 ps
CPU time 122.07 seconds
Started Aug 07 05:38:40 PM PDT 24
Finished Aug 07 05:40:42 PM PDT 24
Peak memory 191680 kb
Host smart-f9792569-cfe6-4632-8e63-34ce260dcad9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460664870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.3460664870
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.458727779
Short name T322
Test name
Test status
Simulation time 105360936000 ps
CPU time 1108.86 seconds
Started Aug 07 05:40:33 PM PDT 24
Finished Aug 07 05:59:02 PM PDT 24
Peak memory 194420 kb
Host smart-746a8028-e089-4b8c-afb7-0eabf7066e16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458727779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.458727779
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.3884856300
Short name T263
Test name
Test status
Simulation time 1173343283951 ps
CPU time 342.42 seconds
Started Aug 07 05:36:52 PM PDT 24
Finished Aug 07 05:42:34 PM PDT 24
Peak memory 183432 kb
Host smart-c0609c85-21f6-4b8c-9d70-bc78e86ffff4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884856300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.3884856300
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.3909074968
Short name T407
Test name
Test status
Simulation time 88525869229 ps
CPU time 38.43 seconds
Started Aug 07 05:36:53 PM PDT 24
Finished Aug 07 05:37:31 PM PDT 24
Peak memory 183388 kb
Host smart-0c541799-f667-4c36-887f-22c94b3d0685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909074968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.3909074968
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.3043649630
Short name T8
Test name
Test status
Simulation time 63179294510 ps
CPU time 112.61 seconds
Started Aug 07 05:36:55 PM PDT 24
Finished Aug 07 05:38:48 PM PDT 24
Peak memory 192660 kb
Host smart-f4f9876c-46e3-402a-ad25-584345e1679f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043649630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.3043649630
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/91.rv_timer_random.758987539
Short name T305
Test name
Test status
Simulation time 130890420603 ps
CPU time 275.01 seconds
Started Aug 07 05:38:40 PM PDT 24
Finished Aug 07 05:43:15 PM PDT 24
Peak memory 193792 kb
Host smart-860edd86-765c-4bfa-b5c7-a19ff6cfe316
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758987539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.758987539
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.3406395577
Short name T439
Test name
Test status
Simulation time 123121193935 ps
CPU time 499.68 seconds
Started Aug 07 05:38:46 PM PDT 24
Finished Aug 07 05:47:06 PM PDT 24
Peak memory 191648 kb
Host smart-d6a662c8-4075-4347-b74f-67a5b27079c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406395577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.3406395577
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.76979703
Short name T183
Test name
Test status
Simulation time 28066759290 ps
CPU time 22.95 seconds
Started Aug 07 05:38:48 PM PDT 24
Finished Aug 07 05:39:11 PM PDT 24
Peak memory 183412 kb
Host smart-b1913268-0729-4bf8-bc60-5d0a591b3462
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76979703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.76979703
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.2465883559
Short name T147
Test name
Test status
Simulation time 80897782442 ps
CPU time 215.25 seconds
Started Aug 07 05:38:47 PM PDT 24
Finished Aug 07 05:42:22 PM PDT 24
Peak memory 183352 kb
Host smart-2cb2e32c-12d4-4d2b-8c4b-5676adb943f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465883559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.2465883559
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.2648141413
Short name T126
Test name
Test status
Simulation time 119070192244 ps
CPU time 323.18 seconds
Started Aug 07 05:38:48 PM PDT 24
Finished Aug 07 05:44:11 PM PDT 24
Peak memory 195196 kb
Host smart-9f55c414-8df9-4a3b-b81b-e0e1c026f395
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648141413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.2648141413
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.2097534027
Short name T441
Test name
Test status
Simulation time 155667020897 ps
CPU time 279.54 seconds
Started Aug 07 05:38:46 PM PDT 24
Finished Aug 07 05:43:26 PM PDT 24
Peak memory 191628 kb
Host smart-5c1315b9-24c2-4207-8eb7-c26fa8b2d305
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097534027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.2097534027
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.235509634
Short name T157
Test name
Test status
Simulation time 325614399237 ps
CPU time 1087.58 seconds
Started Aug 07 05:38:49 PM PDT 24
Finished Aug 07 05:56:57 PM PDT 24
Peak memory 191636 kb
Host smart-c816a535-1388-4f89-b3b6-3c45ce0b58d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235509634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.235509634
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.2892806821
Short name T64
Test name
Test status
Simulation time 63014388289 ps
CPU time 49.69 seconds
Started Aug 07 05:38:46 PM PDT 24
Finished Aug 07 05:39:35 PM PDT 24
Peak memory 183392 kb
Host smart-d10470f6-057b-4629-b52a-8a703fc688f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892806821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.2892806821
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.805472574
Short name T299
Test name
Test status
Simulation time 21388192626 ps
CPU time 29.66 seconds
Started Aug 07 05:38:48 PM PDT 24
Finished Aug 07 05:39:18 PM PDT 24
Peak memory 183468 kb
Host smart-56422210-382a-4b19-98a9-491ff7f4416b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805472574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.805472574
Directory /workspace/99.rv_timer_random/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%